├── .github ├── dependabot.yml └── workflows │ ├── check-ready-to-merge.yml │ ├── isa-build.yml │ ├── merge-and-release.yml │ └── pre-commit.yml ├── .gitignore ├── .gitmodules ├── .pre-commit-config.yaml ├── LICENSE ├── Makefile ├── README.md ├── dependencies ├── Gemfile ├── README.md ├── apt_packages.txt └── package.json ├── marchid.md └── src ├── a-st-ext.adoc ├── b-st-ext.adoc ├── bfloat16.adoc ├── bibliography.adoc ├── c-st-ext.adoc ├── calling-convention.adoc ├── cmo.adoc ├── colophon.adoc ├── counters.adoc ├── d-st-ext.adoc ├── example ├── memcpy.s ├── saxpy.s ├── sgemm.S ├── strcmp.s ├── strcpy.s ├── strlen.s ├── strncpy.s └── vvaddint32.s ├── f-st-ext.adoc ├── fraclmul.adoc ├── hypervisor.adoc ├── images ├── .gitignore ├── backpage.png ├── base-unpriv-reg-state.png ├── bytefield │ ├── counteren.edn │ ├── counterinh.edn │ ├── cust-sys-instr.edn │ ├── epcreg.edn │ ├── hcounterenreg.edn │ ├── hedelegreg.edn │ ├── hgeiereg.edn │ ├── hgeipreg.edn │ ├── hidelegreg.edn │ ├── hiereg-standard.edn │ ├── hiereg.edn │ ├── hipreg-standard.edn │ ├── hipreg.edn │ ├── hpmevents.edn │ ├── htimedelta.edn │ ├── htimedeltah.edn │ ├── htinstreg.edn │ ├── htvalreg.edn │ ├── hvipreg-standard.edn │ ├── hvipreg.edn │ ├── hypv-miereg-standard.edn │ ├── hypv-mipreg-standard.edn │ ├── hypv-mstatus.edn │ ├── hypv-mstatush.edn │ ├── marchid.edn │ ├── mcausereg.edn │ ├── mconfigptrreg.edn │ ├── medeleg.edn │ ├── mepcreg.edn │ ├── mhartid.edn │ ├── mideleg.edn │ ├── miereg-standard.edn │ ├── mimpid.edn │ ├── mipreg-standard.edn │ ├── misareg.edn │ ├── mncause.edn │ ├── mnepc.edn │ ├── mnscratch.edn │ ├── mnstatus.edn │ ├── mscratch.edn │ ├── mtime.edn │ ├── mtimecmp.edn │ ├── mtinstreg.edn │ ├── mtval2reg.edn │ ├── mtvalreg.edn │ ├── mtvec.edn │ ├── mvendorid.edn │ ├── pmp-rv32.edn │ ├── pmp-rv64.edn │ ├── pmpaddr-rv32.edn │ ├── pmpaddr-rv64.edn │ ├── pmpcfg.edn │ ├── priv-instr-set.edn │ ├── rv32hgatp.edn │ ├── rv32satp.edn │ ├── rv32vsatpreg.edn │ ├── rv64hgatp.edn │ ├── rv64satp.edn │ ├── rv64vsatpreg.edn │ ├── rvc-instr-quad0.edn │ ├── rvc-instr-quad1.edn │ ├── rvc-instr-quad2.edn │ ├── scausereg.edn │ ├── scounteren.edn │ ├── sie.edn │ ├── siereg-standard.edn │ ├── sip.edn │ ├── sipreg-standard.edn │ ├── sscratch.edn │ ├── stvalreg.edn │ ├── stvec.edn │ ├── sv32pa.edn │ ├── sv32pte.edn │ ├── sv32va.edn │ ├── sv32x4va.edn │ ├── sv39pa.edn │ ├── sv39pte.edn │ ├── sv39va.edn │ ├── sv39x4va.edn │ ├── sv48pa.edn │ ├── sv48pte.edn │ ├── sv48va.edn │ ├── sv48x4va.edn │ ├── sv57pa.edn │ ├── sv57pte.edn │ ├── sv57va.edn │ ├── sv57x4va.edn │ ├── vscausereg.edn │ ├── vsepcreg.edn │ ├── vsiereg-standard.edn │ ├── vsiereg.edn │ ├── vsipreg-standard.edn │ ├── vsipreg.edn │ ├── vsscratchreg.edn │ ├── vsstatusreg-rv32.edn │ ├── vsstatusreg.edn │ ├── vstvalreg.edn │ └── vstvecreg.edn ├── draft.png ├── es_dataflow.svg ├── es_noisetest.svg ├── es_state.svg ├── graphviz │ ├── litmus_addrpo.png │ ├── litmus_addrpo.txt │ ├── litmus_datacoirfi.png │ ├── litmus_datacoirfi.txt │ ├── litmus_datarfi.png │ ├── litmus_datarfi.txt │ ├── litmus_lb_lrsc.png │ ├── litmus_lb_lrsc.txt │ ├── litmus_mp_fenceww_fri_rfi_addr.png │ ├── litmus_mp_fenceww_fri_rfi_addr.txt │ ├── litmus_ppoca.png │ ├── litmus_ppoca.txt │ ├── litmus_rsw.png │ ├── litmus_rsw.txt │ ├── litmus_sample.adoc │ ├── litmus_sample.png │ ├── litmus_sample.txt │ ├── litmus_sb_fwd.png │ ├── litmus_sb_fwd.txt │ ├── litmus_subsumption.png │ └── litmus_subsumption.txt ├── image_placeholder.png ├── png │ ├── misareg.png │ ├── mvendorid.png │ └── privimps.png ├── risc-v_logo.png ├── riscv-horizontal-color.svg ├── smepmp-visual-representation.png └── wavedrom │ ├── atomic-mem.edn │ ├── b-immediate.edn │ ├── c-andi.edn │ ├── c-breakpoint-instr.edn │ ├── c-cb-format-ls.edn │ ├── c-ci.edn │ ├── c-ciw.edn │ ├── c-cj-format-ls.edn │ ├── c-cr-format-ls.edn │ ├── c-cs-format-ls.edn │ ├── c-def-illegal-inst.edn │ ├── c-int-reg-immed.edn │ ├── c-int-reg-to-reg-ca-format.edn │ ├── c-int-reg-to-reg-cr-format.edn │ ├── c-integer-const-gen.edn │ ├── c-mop.edn │ ├── c-nop-instr.edn │ ├── c-sp-load-store-css.edn │ ├── c-sp-load-store.edn │ ├── c-srli-srai.edn │ ├── counters-diag.edn │ ├── cr-register.edn │ ├── csr-instr.edn │ ├── ct-conditional.edn │ ├── ct-unconditional-2.edn │ ├── ct-unconditional.edn │ ├── d-xwwx.edn │ ├── division-op.edn │ ├── double-fl-class.edn │ ├── double-fl-compare.edn │ ├── double-fl-compute.edn │ ├── double-fl-convert-mv.edn │ ├── double-ls.edn │ ├── env-call-breakpoint.edn │ ├── fcvt-sd-ds.edn │ ├── float-csr.edn │ ├── flt-pt-to-int-move.edn │ ├── flt-to-flt-sgn-inj-instr.edn │ ├── fsjgnjnx-d.edn │ ├── half-ls.edn │ ├── half-pr-flt-pt-class.edn │ ├── half-pr-flt-pt-compare.edn │ ├── half-prec-conv-and-mv.edn │ ├── half-prec-flpt-to-flpt-conv.edn │ ├── hinvalgvma.edn │ ├── hinvalvvma.edn │ ├── hypv-mm-fence.edn │ ├── hypv-virt-load-and-store.edn │ ├── i-immediate.edn │ ├── immediate-variants.edn │ ├── immediate.edn │ ├── instruction-formats.edn │ ├── int-comp-lui-aiupc.edn │ ├── int-comp-slli-srli-srai.edn │ ├── int-reg-reg.edn │ ├── integer-computational.edn │ ├── j-immediate.edn │ ├── load-reserve-st-conditional.edn │ ├── load-store.edn │ ├── m-st-ext-for-int-mult.edn │ ├── mem-order.edn │ ├── menvcfgreg.edn │ ├── mm-env-call.edn │ ├── mop-r.edn │ ├── mop-rr.edn │ ├── mseccfg.edn │ ├── mstatushreg.edn │ ├── mstatusreg-rv321.edn │ ├── mstatusreg.edn │ ├── nop.edn │ ├── quad-cnvrt-intch-xqqx.edn │ ├── quad-cnvrt-mv.edn │ ├── quad-cnvt-interchange.edn │ ├── quad-compute.edn │ ├── quad-float-clssfy.edn │ ├── quad-float-compare.edn │ ├── quad-ls.edn │ ├── reg-based-ldnstr.edn │ ├── rv64-lui-auipc.edn │ ├── rv64i-base-int.edn │ ├── rv64i-int-reg-reg.edn │ ├── rv64i-slli.edn │ ├── rv64i-slliw.edn │ ├── s-immediate.edn │ ├── sfenceinvalir.edn │ ├── sfencevma.edn │ ├── sfencewinval.edn │ ├── sinvalvma.edn │ ├── sp-load-store-2.edn │ ├── sp-load-store.edn │ ├── spfloat-classify.edn │ ├── spfloat-cn-cmp.edn │ ├── spfloat-comp.edn │ ├── spfloat-mv.edn │ ├── spfloat-sign-inj.edn │ ├── spfloat-zfh.edn │ ├── spfloat.edn │ ├── spfloat2-zfh.edn │ ├── spfloat2.edn │ ├── transformedatomicinst.edn │ ├── transformedloadinst.edn │ ├── transformedstoreinst.edn │ ├── transformedvmaccessinst.edn │ ├── trap-return.edn │ ├── u-immediate.edn │ ├── v-inst-table.edn │ ├── valu-format.edn │ ├── vcfg-format.edn │ ├── vfrec7.edn │ ├── vfrsqrt7.edn │ ├── vmem-format.edn │ ├── vtype-format.edn │ ├── wfi.edn │ ├── zifencei-ff.edn │ └── zihintpause-hint.edn ├── index.adoc ├── indirect-csr.adoc ├── intro.adoc ├── m-st-ext.adoc ├── machine.adoc ├── mm-alloy.adoc ├── mm-eplan.adoc ├── mm-formal.adoc ├── mm-herd.adoc ├── naming.adoc ├── priv-cfi.adoc ├── priv-csrs.adoc ├── priv-history.adoc ├── priv-insns.adoc ├── priv-intro.adoc ├── priv-preface.adoc ├── q-st-ext.adoc ├── resources └── riscv-spec.bib ├── riscv-privileged.adoc ├── riscv-unprivileged.adoc ├── rnmi.adoc ├── rv-32-64g.adoc ├── rv32.adoc ├── rv32e.adoc ├── rv64.adoc ├── rvwmo.adoc ├── scalar-crypto.adoc ├── smcdeleg.adoc ├── smcntrpmf.adoc ├── smctr.adoc ├── smdbltrp.adoc ├── smepmp.adoc ├── smstateen.adoc ├── sscofpmf.adoc ├── ssdbltrp.adoc ├── sstc.adoc ├── supervisor.adoc ├── svgnam.def ├── unpriv-cfi.adoc ├── v-st-ext.adoc ├── vector-crypto.adoc ├── vector-examples.adoc ├── zabha.adoc ├── zacas.adoc ├── zawrs.adoc ├── zc.adoc ├── zfa.adoc ├── zfh.adoc ├── zfinx.adoc ├── zicond.adoc ├── zicsr.adoc ├── zifencei.adoc ├── zihintntl.adoc ├── zihintpause.adoc ├── zilsd.adoc ├── zimop.adoc ├── zpm.adoc └── ztso-st-ext.adoc /.github/dependabot.yml: -------------------------------------------------------------------------------- 1 | --- 2 | # https://docs.github.com/en/code-security/dependabot/dependabot-version-updates/configuration-options-for-the-dependabot.yml-file#package-ecosystem 3 | version: 2 4 | updates: 5 | - package-ecosystem: gitsubmodule 6 | directory: / 7 | schedule: 8 | interval: daily 9 | -------------------------------------------------------------------------------- /.github/workflows/check-ready-to-merge.yml: -------------------------------------------------------------------------------- 1 | --- 2 | name: Check Mergeable by Label 3 | 4 | on: 5 | pull_request: 6 | types: 7 | - opened 8 | - reopened 9 | - synchronize 10 | - edited 11 | - labeled 12 | - unlabeled 13 | 14 | jobs: 15 | fail-by-label: 16 | if: contains(github.event.pull_request.labels.*.name, 'Pending Ratification') 17 | runs-on: ubuntu-latest 18 | steps: 19 | - name: Fail if PR is labeled "Pending Ratification" 20 | run: | 21 | echo "Error: This PR is labeled as 'Pending Ratification' and cannot be merged." 22 | exit 1 23 | -------------------------------------------------------------------------------- /.github/workflows/pre-commit.yml: -------------------------------------------------------------------------------- 1 | --- 2 | name: pre-commit 3 | 4 | on: 5 | pull_request: 6 | push: 7 | branches: [main] 8 | 9 | jobs: 10 | pre-commit: 11 | runs-on: ubuntu-latest 12 | steps: 13 | - uses: actions/checkout@v4 14 | - uses: actions/setup-python@v5 15 | - uses: pre-commit/action@v3.0.0 16 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | .*.swp 3 | .vscode 4 | /build/* 5 | /images/* 6 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "docs-resources"] 2 | path = docs-resources 3 | url = https://github.com/riscv/docs-resources 4 | -------------------------------------------------------------------------------- /.pre-commit-config.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | repos: 3 | - repo: https://github.com/pre-commit/pre-commit-hooks 4 | rev: v5.0.0 5 | hooks: 6 | - id: check-json 7 | - id: check-symlinks 8 | - id: check-yaml 9 | - id: end-of-file-fixer 10 | - id: trailing-whitespace 11 | args: [--markdown-linebreak-ext=md] 12 | - id: check-merge-conflict 13 | args: [--assume-in-merge] 14 | 15 | - repo: local 16 | hooks: 17 | - id: forbidden-file-extensions 18 | name: forbidden-file-extensions 19 | entry: disallow these file extensions 20 | language: fail 21 | # Disallow other asciidoc extensions except .adoc 22 | files: .*\.(asciidoc|asc)$ 23 | 24 | - repo: https://github.com/jumanjihouse/pre-commit-hook-yamlfmt 25 | rev: 0.2.3 26 | hooks: 27 | - id: yamlfmt 28 | args: [--mapping, '2', --sequence, '4', --offset, '2'] 29 | 30 | - repo: https://github.com/Lucas-C/pre-commit-hooks 31 | rev: v1.5.5 32 | hooks: 33 | - id: forbid-tabs 34 | exclude_types: 35 | - makefile 36 | -------------------------------------------------------------------------------- /dependencies/Gemfile: -------------------------------------------------------------------------------- 1 | source 'https://rubygems.org' 2 | gem 'asciidoctor' 3 | gem 'asciidoctor-bibtex' 4 | gem 'asciidoctor-diagram' 5 | gem 'asciidoctor-lists' 6 | gem 'mathematical' 7 | gem 'asciidoctor-mathematical' 8 | gem 'asciidoctor-pdf' 9 | gem 'asciidoctor-epub3' 10 | gem 'citeproc-ruby' 11 | gem 'coderay' 12 | gem 'csl-styles' 13 | gem 'json' 14 | gem 'pygments.rb' 15 | gem 'rghost' 16 | gem 'rouge' 17 | gem 'ruby_dev' 18 | -------------------------------------------------------------------------------- /dependencies/README.md: -------------------------------------------------------------------------------- 1 | Dependencies for the build environment for various package managers. Used in 2 | `.github/workflows/`. 3 | -------------------------------------------------------------------------------- /dependencies/apt_packages.txt: -------------------------------------------------------------------------------- 1 | bison 2 | build-essential 3 | cmake 4 | curl 5 | flex 6 | fonts-lyx 7 | git 8 | graphviz 9 | # For wavedrom 10 | default-jre 11 | libcairo2-dev 12 | libffi-dev 13 | libgdk-pixbuf2.0-dev 14 | libglib2.0-dev 15 | libpango1.0-dev 16 | libxml2-dev 17 | make 18 | pkg-config 19 | ruby 20 | ruby-dev 21 | libwebp-dev 22 | libzstd-dev 23 | -------------------------------------------------------------------------------- /dependencies/package.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "local", 3 | "version": "0.0.1", 4 | "dependencies": { 5 | "wavedrom-cli": "^2.6.8", 6 | "bytefield-svg": "^1.8.0" 7 | } 8 | } 9 | -------------------------------------------------------------------------------- /src/bibliography.adoc: -------------------------------------------------------------------------------- 1 | [bibliography] 2 | == Bibliography 3 | 4 | bibliography::[] 5 | -------------------------------------------------------------------------------- /src/calling-convention.adoc: -------------------------------------------------------------------------------- 1 | [appendix] 2 | == Calling Convention for Vector State (Not authoritative - Placeholder Only) 3 | 4 | NOTE: This Appendix is only a placeholder to help explain the 5 | conventions used in the code examples, and is not considered frozen or 6 | part of the ratification process. The official RISC-V psABI document 7 | is being expanded to specify the vector calling conventions. 8 | 9 | In the RISC-V psABI, the vector registers `v0`-`v31` are all caller-saved. 10 | The `vl` and `vtype` CSRs are also caller-saved. 11 | 12 | Procedures may assume that `vstart` is zero upon entry. Procedures may 13 | assume that `vstart` is zero upon return from a procedure call. 14 | 15 | NOTE: Application software should normally not write `vstart` explicitly. 16 | Any procedure that does explicitly write `vstart` to a nonzero value must 17 | zero `vstart` before either returning or calling another procedure. 18 | 19 | The `vxrm` and `vxsat` fields of `vcsr` have thread storage duration. 20 | 21 | Executing a system call causes all caller-saved vector registers 22 | (`v0`-`v31`, `vl`, `vtype`) and `vstart` to become unspecified. 23 | 24 | NOTE: This scheme allows system calls that cause context switches to avoid 25 | saving and later restoring the vector registers. 26 | 27 | NOTE: Most OSes will choose to either leave these registers intact or reset 28 | them to their initial state to avoid leaking information across process 29 | boundaries. 30 | -------------------------------------------------------------------------------- /src/example/memcpy.s: -------------------------------------------------------------------------------- 1 | .text 2 | .balign 4 3 | .global memcpy 4 | # void *memcpy(void* dest, const void* src, size_t n) 5 | # a0=dest, a1=src, a2=n 6 | # 7 | memcpy: 8 | mv a3, a0 # Copy destination 9 | loop: 10 | vsetvli t0, a2, e8, m8, ta, ma # Vectors of 8b 11 | vle8.v v0, (a1) # Load bytes 12 | add a1, a1, t0 # Bump pointer 13 | sub a2, a2, t0 # Decrement count 14 | vse8.v v0, (a3) # Store bytes 15 | add a3, a3, t0 # Bump pointer 16 | bnez a2, loop # Any more? 17 | ret # Return 18 | -------------------------------------------------------------------------------- /src/example/saxpy.s: -------------------------------------------------------------------------------- 1 | .text 2 | .balign 4 3 | .global saxpy 4 | # void 5 | # saxpy(size_t n, const float a, const float *x, float *y) 6 | # { 7 | # size_t i; 8 | # for (i=0; i eiid1 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 25 | eiid1 -> eiid2 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 26 | eiid2 -> eiid3 [label=<addrppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid2 -> eiid4 [label=<ppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid3 -> eiid4 [label=<po>, color="black", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | eiid4 -> eiid0 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 30 | } 31 | -------------------------------------------------------------------------------- /src/images/graphviz/litmus_datacoirfi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_datacoirfi.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_datacoirfi.txt: -------------------------------------------------------------------------------- 1 | digraph G { 2 | 3 | splines=spline; 4 | pad="0.000000"; 5 | 6 | 7 | /* the unlocked events */ 8 | eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,2.250000!", fixedsize="false", height="0.111111", width="0.555556"]; 9 | eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; 10 | eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.500000,3.093750!", fixedsize="false", height="0.111111", width="0.555556"]; 11 | eiid3 [label="e: Wz=1", shape="none", fontsize=8, pos="2.500000,2.531250!", fixedsize="false", height="0.111111", width="0.555556"]; 12 | eiid4 [label="f: Wz=1", shape="none", fontsize=8, pos="2.500000,1.968750!", fixedsize="false", height="0.111111", width="0.555556"]; 13 | eiid5 [label="g: Rz=1", shape="none", fontsize=8, pos="2.500000,1.406250!", fixedsize="false", height="0.111111", width="0.555556"]; 14 | eiid6 [label="h: Rx=0", shape="none", fontsize=8, pos="2.500000,0.843750!", fixedsize="false", height="0.111111", width="0.555556"]; 15 | 16 | /* the intra_causality_data edges */ 17 | 18 | 19 | /* the intra_causality_control edges */ 20 | 21 | /* the poi edges */ 22 | /* the rfmap edges */ 23 | 24 | 25 | /* The viewed-before edges */ 26 | eiid0 -> eiid1 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid1 -> eiid2 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid2 -> eiid3 [label=<datappo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | eiid3 -> eiid4 [label=<coppo>, color="bluf:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 30 | eiid4 -> eiid5 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 31 | eiid5 -> eiid6 [label=<addrppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 32 | eiid6 -> eiid0 [label=<fr>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 33 | } 34 | -------------------------------------------------------------------------------- /src/images/graphviz/litmus_datarfi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_datarfi.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_datarfi.txt: -------------------------------------------------------------------------------- 1 | digraph G { 2 | 3 | splines=spline; 4 | pad="0.000000"; 5 | 6 | 7 | /* the unlocked events */ 8 | eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; 9 | eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 10 | eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.500000,2.250000!", fixedsize="false", height="0.111111", width="0.555556"]; 11 | eiid3 [label="e: Wz=1", shape="none", fontsize=8, pos="2.500000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; 12 | eiid4 [label="f: Rz=1", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 13 | eiid5 [label="g: Rx=0", shape="none", fontsize=8, pos="2.500000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; 14 | 15 | /* the intra_causality_data edges */ 16 | 17 | 18 | /* the intra_causality_control edges */ 19 | 20 | /* the poi edges */ 21 | /* the rfmap edges */ 22 | 23 | 24 | /* The viewed-before edges */ 25 | eiid0 -> eiid1 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 26 | eiid1 -> eiid2 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid2 -> eiid3 [label=<datappo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid2 -> eiid4 [label=<ppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | eiid3 -> eiid4 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 30 | eiid4 -> eiid5 [label=<addrppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 31 | eiid5 -> eiid0 [label=<fr>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 32 | } 33 | -------------------------------------------------------------------------------- /src/images/graphviz/litmus_lb_lrsc.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_lb_lrsc.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_lb_lrsc.txt: -------------------------------------------------------------------------------- 1 | digraph G { 2 | 3 | splines=spline; 4 | pad="0.000000"; 5 | label="A sample litmus test and one forbidden execution (a0-1)." 6 | 7 | /* the unlocked events */ 8 | eiid0 [label="a: Rx=0", shape="none", fontsize=8, pos="1.000000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; 9 | eiid1 [label="b: Rz*=0", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.666667"]; 10 | eiid2 [label="c: Wz*=0", shape="none", fontsize=8, pos="1.000000,0.562500!", fixedsize="false", height="0.111111", width="0.666667"]; 11 | eiid3 [label="d: Wy=0", shape="none", fontsize=8, pos="1.000000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; 12 | eiid4 [label="e: Ry=0", shape="none", fontsize=8, pos="2.500000,1.687500!", fixedsize="false", height="0.111111", width="0.555556"]; 13 | eiid5 [label="f: Wx=0", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 14 | 15 | /* the intra_causality_data edges */ 16 | 17 | 18 | /* the intra_causality_control edges */ 19 | 20 | /* the poi edges */ 21 | /* the rfmap edges */ 22 | 23 | 24 | /* The viewed-before edges */ 25 | eiid0 -> eiid1 [label=<po>, color="black", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 26 | eiid0 -> eiid2 [label=<datappo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid1 -> eiid2 [label=<ppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid2 -> eiid3 [label=<datappo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | eiid3 -> eiid4 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 30 | eiid4 -> eiid5 [label=<datappo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 31 | eiid5 -> eiid0 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 32 | } 33 | -------------------------------------------------------------------------------- /src/images/graphviz/litmus_mp_fenceww_fri_rfi_addr.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_mp_fenceww_fri_rfi_addr.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_mp_fenceww_fri_rfi_addr.txt: -------------------------------------------------------------------------------- 1 | digraph G { 2 | 3 | splines=spline; 4 | pad="0.000000"; 5 | label="Litmus test MP+fence.w.w+fri-rfi-addr (outcome permitted)" 6 | 7 | /* the unlocked events */ 8 | eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,1.575000!", fixedsize="false", height="0.111111", width="0.555556"]; 9 | eiid1 [label="c: Wy=1", shape="none", fontsize=8, pos="1.000000,1.050000!", fixedsize="false", height="0.111111", width="0.555556"]; 10 | eiid2 [label="d: Ry=1", shape="none", fontsize=8, pos="2.500000,1.575000!", fixedsize="false", height="0.111111", width="0.555556"]; 11 | eiid3 [label="e: Wy=2", shape="none", fontsize=8, pos="2.500000,1.050000!", fixedsize="false", height="0.111111", width="0.555556"]; 12 | eiid4 [label="f: Ry=2", shape="none", fontsize=8, pos="2.500000,0.525000!", fixedsize="false", height="0.111111", width="0.555556"]; 13 | eiid5 [label="i: Rx=0", shape="none", fontsize=8, pos="2.500000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; 14 | 15 | /* the intra_causality_data edges */ 16 | 17 | 18 | /* the intra_causality_control edges */ 19 | 20 | /* the poi edges */ 21 | /* the rfmap edges */ 22 | 23 | 24 | /* The viewed-before edges */ 25 | eiid0 -> eiid1 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 26 | eiid1 -> eiid2 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid1 -> eiid3 [label=<co>, color="blue", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid2 -> eiid3 [label=<frppo>, color="#ffa040:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | eiid3 -> eiid4 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 30 | eiid4 -> eiid5 [label=<addrppo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 31 | eiid5 -> eiid0 [label=<fr>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 32 | } 33 | -------------------------------------------------------------------------------- /src/images/graphviz/litmus_ppoca.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_ppoca.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_rsw.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_rsw.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_sample.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_sample.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_sb_fwd.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_sb_fwd.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_sb_fwd.txt: -------------------------------------------------------------------------------- 1 | 2 | digraph G { 3 | 4 | splines=spline; 5 | pad="0.000000"; 6 | label="A store buffer forwarding litmus test (outcome permitted)."; 7 | 8 | /* the unlocked events */ 9 | eiid0 [label="a: Wx=1", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 10 | eiid1 [label="b: Rx=1", shape="none", fontsize=8, pos="1.000000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; 11 | eiid2 [label="d: Ry=0", shape="none", fontsize=8, pos="1.000000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; 12 | eiid3 [label="e: Wy=1", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 13 | eiid4 [label="f: Ry=1", shape="none", fontsize=8, pos="2.500000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; 14 | eiid5 [label="h: Rx=0", shape="none", fontsize=8, pos="2.500000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; 15 | 16 | /* the intra_causality_data edges */ 17 | 18 | 19 | /* the intra_causality_control edges */ 20 | 21 | /* the poi edges */ 22 | /* the rfmap edges */ 23 | 24 | 25 | /* The viewed-before edges */ 26 | eiid0 -> eiid1 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid1 -> eiid2 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid2 -> eiid3 [label=<fr>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | eiid3 -> eiid4 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 30 | eiid4 -> eiid5 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 31 | eiid5 -> eiid0 [label=<fr>, color="#ffa040", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 32 | } 33 | -------------------------------------------------------------------------------- /src/images/graphviz/litmus_subsumption.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/graphviz/litmus_subsumption.png -------------------------------------------------------------------------------- /src/images/graphviz/litmus_subsumption.txt: -------------------------------------------------------------------------------- 1 | digraph G { 2 | 3 | splines=spline; 4 | pad="0.000000"; 5 | 6 | 7 | /* the unlocked events */ 8 | eiid0 [label="a: Wx=3", shape="none", fontsize=8, pos="1.000000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 9 | eiid1 [label="b: Wy=1", shape="none", fontsize=8, pos="1.000000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; 10 | eiid2 [label="c: Ry=1", shape="none", fontsize=8, pos="2.500000,1.125000!", fixedsize="false", height="0.111111", width="0.555556"]; 11 | eiid3 [label="d: Wx=1", shape="none", fontsize=8, pos="2.500000,0.562500!", fixedsize="false", height="0.111111", width="0.555556"]; 12 | eiid4 [label="e: Wx=2", shape="none", fontsize=8, pos="2.500000,0.000000!", fixedsize="false", height="0.111111", width="0.555556"]; 13 | 14 | /* the intra_causality_data edges */ 15 | 16 | 17 | /* the intra_causality_control edges */ 18 | 19 | /* the poi edges */ 20 | /* the rfmap edges */ 21 | 22 | 23 | /* The viewed-before edges */ 24 | eiid0 -> eiid1 [label=<fenceppo>, color="darkgreen:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 25 | eiid0 -> eiid3 [label=<co>, color="blue", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 26 | eiid1 -> eiid2 [label=<rf>, color="red", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 27 | eiid2 -> eiid3 [label=<datappo>, color="indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 28 | eiid3 -> eiid4 [label=<coppo>, color="blue:indigo", fontsize=11, penwidth="3.000000", arrowsize="0.666700"]; 29 | } 30 | -------------------------------------------------------------------------------- /src/images/image_placeholder.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/image_placeholder.png -------------------------------------------------------------------------------- /src/images/png/misareg.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/png/misareg.png -------------------------------------------------------------------------------- /src/images/png/mvendorid.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/png/mvendorid.png -------------------------------------------------------------------------------- /src/images/png/privimps.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/png/privimps.png -------------------------------------------------------------------------------- /src/images/risc-v_logo.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/risc-v_logo.png -------------------------------------------------------------------------------- /src/images/smepmp-visual-representation.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/riscv/riscv-isa-manual/55ee5e3d87dd454cb7cf683880f8ed8801a75834/src/images/smepmp-visual-representation.png -------------------------------------------------------------------------------- /src/images/wavedrom/atomic-mem.edn: -------------------------------------------------------------------------------- 1 | //## 9.4 Atomic Memory Operations 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','AMO','AMO','AMO','AMO','AMO','AMO','AMO']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'funct3', attr: ['3','width','width','width','width','width','width','width']}, 9 | {bits: 5, name: 'rs1', attr: ['5','addr','addr','addr','addr','addr','addr','addr']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src','src','src','src','src','src','src']}, 11 | {bits: 1, name: 'rl', attr: ['1']}, 12 | {bits: 1, name: 'aq', attr: ['1']}, 13 | {bits: 6, name: 'funct5', attr: ['5','AMOSWAP.W/D', 'AMOADD.W/D', 'AMOAND.W/D', 'AMOOR.W/D', 'AMOXOR.W/D', 'AMOMAX[U].W/D','AMOMIN[U].W/D']}, 14 | ], config: {bits: 32}} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/b-immediate.edn: -------------------------------------------------------------------------------- 1 | //#### B-immediate 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 1, name: '0'}, 7 | {bits: 4, name: 'inst[11:8]'}, 8 | {bits: 6, name: 'inst[30:25]'}, 9 | {bits: 1, name: '[7]'}, 10 | {bits: 20, name: '— inst[31] —'}, 11 | ], config:{fontsize: 12, label:{right: 'B-immediate'}}} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-andi.edn: -------------------------------------------------------------------------------- 1 | //c-andi.adoc 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C1'],}, 7 | {bits: 5, name: 'imm[4:0]', attr: ['5','imm[4:0]']}, 8 | {bits: 3, name: 'rd′/rs1′', attr: ['3','dest'],}, 9 | {bits: 2, name: 'funct2', attr: ['2','C.ANDI'],}, 10 | {bits: 1, name: 'imm[5]', attr: ['1','imm[5]'],}, 11 | {bits: 3, name: 'funct3', attr: ['3','C.ANDI'],}, 12 | ]} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-breakpoint-instr.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2','C2'],}, 8 | {bits: 10, name: '0', attr: ['10','0'],}, 9 | {bits: 4, name: 'funct4', attr: ['4','C.EBREAK'],}, 10 | ], config: {bits: 16}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-cb-format-ls.edn: -------------------------------------------------------------------------------- 1 | //c-cb-format-ls 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C1', 'C1']}, 7 | {bits: 5, name: 'imm', attr: ['5','offset[7:6|2:1|5]', 'offset[7:6|2:1|5]']}, 8 | {bits: 3, name: 'rs1′', attr: ['3','src', 'src']}, 9 | {bits: 3, name: 'imm', attr: ['3','offset[8|4:3]', 'offset[8|4:3]'],}, 10 | {bits: 3, name: 'funct3', attr: ['3','C.BEQZ', 'C.BNEZ'],}, 11 | ], config: {bits: 16}} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-ci.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2', 'C2']}, 7 | {bits: 5, name: 'shamt[4:0]', attr: ['5', 'shamt[4:0]']}, 8 | {bits: 5, name: 'rd/rs1', attr: ['5', 'dest != 0']}, 9 | {bits: 1, name: 'shamt[5]', attr: ['1', 'shamt[5]']}, 10 | {bits: 3, name: 'funct3', attr: ['3', 'C.SLLI']}, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-ciw.edn: -------------------------------------------------------------------------------- 1 | //c-ciw.adoc 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C0'],}, 7 | {bits: 3, name: 'rd′', attr: ['3','dest'],}, 8 | {bits: 8, name: 'imm', attr: ['8','nzuimm[5:4|9:6|2|3]']}, 9 | {bits: 3, name: 'funct3', attr: ['3','C.ADDI4SPN']}, 10 | ], config: {bits: 16}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-cj-format-ls.edn: -------------------------------------------------------------------------------- 1 | //c-cj-format-ls 2 | 3 | //[wavedrom, ,svg] 4 | //.... 5 | //{reg: [ 6 | // {bits: 2, name: 'op', attr: ['2','CI','CI']}, 7 | // {bits: 10, name: 'imm'}, 8 | // {bits: 4, name: 'funct3' attr:['3','CJ','CJAL']}, 9 | //] config: {bits: 16}} 10 | //.... 11 | 12 | 13 | [wavedrom, ,svg] 14 | .... 15 | {reg: [ 16 | {bits: 2, name: 'op', attr: ['2','C1','C1']}, 17 | {bits: 11, name: 'imm', attr: ['11','offset[11|4|9:8|10|6|7|3:1|5]','offset[11|4|9:8|10|6|7|3:1|5]']}, 18 | {bits: 3, name: 'funct3', attr: ['3','C.J','C.JAL']}, 19 | ], config: {bits: 16}} 20 | .... 21 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-cr-format-ls.edn: -------------------------------------------------------------------------------- 1 | //These instructions use the CR format. 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C2', 'C2']}, 7 | {bits: 5, name: 'rs2', attr: ['5','0', '0']}, 8 | {bits: 5, name: 'rs1', attr: ['5','src≠0', 'src≠0']}, 9 | {bits: 4, name: 'funct4', attr: ['4','C.JR', 'C.JALR']}, 10 | ], config: {bits: 16}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-cs-format-ls.edn: -------------------------------------------------------------------------------- 1 | //## 16.X Load and Store Instructions 2 | //### c-cs-format-ls 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2', 'C0','C0','C0','C0','C0']}, 8 | {bits: 3, name: 'rs2ʹ', attr: ['3', 'src','src','src','src','src']}, 9 | {bits: 2, name: 'imm', attr: ['2', 'offset[2|6]','offset[7:6]','offset[7:6]','offset[2|6]','offset[7:6]']}, 10 | {bits: 3, name: 'rs1ʹ', attr: ['3', 'base','base','base','base','base']}, 11 | {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]','offset[5:3]','offset[5|4|8]','offset[5:3]','offset[5:3]']}, 12 | {bits: 3, name: 'funct3', attr: ['3', 'C.SW','C.SD','C.SQ','C.FSW','C.FSD']}, 13 | ], config: {bits: 16}} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-def-illegal-inst.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 2, name: '0', attr: ['2','0'],}, 8 | {bits: 5, name: '0', attr: ['5','0'],}, 9 | {bits: 5, name: '0', attr: ['5','0'],}, 10 | {bits: 1, name: '0', attr: ['1','0'],}, 11 | {bits: 3, name: '0', attr: ['3','0'],}, 12 | ], config: {bits: 16}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-int-reg-immed.edn: -------------------------------------------------------------------------------- 1 | //c-int-reg-immed.adoc 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C1', 'C1', 'C1']}, 7 | {bits: 5, name: 'imm[4:]', attr: ['5','nzimm[4:0]', 'imm[4:0]', 'nzimm[4|6|8:7|5]']}, 8 | {bits: 5, name: 'rd/rs1', attr: ['5','dest != 0', 'dest != 0', '2']}, 9 | {bits: 1, name: 'imm[5]', attr: ['1','nzimm[5]', 'imm[5]', 'nzimm[9]']}, 10 | {bits: 3, name: 'funct3', attr: ['3','C.ADDI', 'C.ADDIW', 'C.ADDI16SP']}, 11 | ], config: {bits: 16}} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-int-reg-to-reg-ca-format.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2', 'C1', 'C1', 'C1', 'C1', 'C1', 'C1'],}, 8 | {bits: 3, name: 'rs2′', attr: ['3', 'src', 'src', 'src', 'src', 'src', 'src'],}, 9 | {bits: 2, name: 'funct2', attr: ['2', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, 10 | {bits: 3, name: 'rd′/rs1′', attr: ['3', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'],}, 11 | {bits: 6, name: 'funct6', attr: ['6', 'C.AND', 'C.OR', 'C.XOR', 'C.SUB', 'C.ADDW', 'C.SUBW'],}, 12 | ]} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-int-reg-to-reg-cr-format.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2', 'C2', 'C2'],}, 8 | {bits: 5, name: 'rs2', attr: ['5', 'src≠0', 'src≠0'],}, 9 | {bits: 5, name: 'rd/rs1', attr: ['5', 'dest≠0', 'dest≠0'],}, 10 | {bits: 4, name: 'funct4', attr: ['4', 'C.MV', 'C.ADD'],}, 11 | ], config: {bits: 16}} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-integer-const-gen.edn: -------------------------------------------------------------------------------- 1 | //c-integer-const-gen 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C1', 'C1']}, 7 | {bits: 5, name: 'imm[4:0]', attr: ['5','imm[4:0]','nzimm[16:12]']}, 8 | {bits: 5, name: 'rd', attr: ['5','dest != 0', 'dest != {0, 2}']}, 9 | {bits: 1, name: 'imm[5]', attr: ['1','imm[5]', 'nzimm[17]'],}, 10 | {bits: 3, name: 'funct3', attr: ['3','C.LI', 'C.LUI'],}, 11 | ], config: {bits: 16}} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-mop.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg:[ 4 | { bits: 2, name: 0x1 }, 5 | { bits: 5, name: 0x0 }, 6 | { bits: 1, name: 0x1 }, 7 | { bits: 3, name: 'n[3:1]' }, 8 | { bits: 1, name: 0x0 }, 9 | { bits: 1, name: 0x0 }, 10 | { bits: 3, name: 0x3 }, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-nop-instr.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2','C1'],}, 8 | {bits: 5, name: 'imm[4:0]', attr: ['5','0'],}, 9 | {bits: 5, name: 'rd/rs1', attr: ['5','0'],}, 10 | {bits: 1, name: 'imm[5]', attr: ['1','0'],}, 11 | {bits: 3, name: 'funct3', attr: ['3','C.NOP'],}, 12 | ]} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-sp-load-store-css.edn: -------------------------------------------------------------------------------- 1 | //c-sp load and store, css format--is this correct? 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C2','C2','C2','C2','C2']}, 7 | {bits: 5, name: 'rs2', attr: ['5','src', 'src', 'src', 'src', 'src']}, 8 | {bits: 6, name: 'imm', attr: ['6','offset[5:2|7:6]', 'offset[5:3|8:6]', 'offset[5:4|9:6]', 'offset[5:2|7:6]','offset[5:3|8:6]']}, 9 | {bits: 3, name: 'funct3', attr: ['3','C.SWSP', 'C.SDSP', 'C.SQSP', 'C.FSWSP', 'C.FSDSP']}, 10 | ], config: {bits: 16}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-sp-load-store.edn: -------------------------------------------------------------------------------- 1 | //## 16.3 Load and Store Instructions 2 | //### Stack-Pointer-Based Loads and Stores 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2','C2','C2','C2','C2','C2']}, 8 | {bits: 5, name: 'imm', attr: ['5','offset[4:2|7:6]', 'offset[4:3|8:6]', 'offset[4|9:6]', 'offset[4:2|7:6]', 'offset[4:3|8:6]']}, 9 | {bits: 5, name: 'rd', attr: ['5','dest≠0', 'dest≠0', 'dest≠0', 'dest', 'dest']}, 10 | {bits: 1, name: 'imm', attr: ['1','offset[5]','offset[5]','offset[5]','offset[5]','offset[5]']}, 11 | {bits: 3, name: 'funct3', attr: ['3','C.LWSP', 'C.LDSP', 'C.LQSP', 'C.FLWSP', 'C.FLDSP']}, 12 | ], config: {bits: 16}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/c-srli-srai.edn: -------------------------------------------------------------------------------- 1 | //c-srli-srai.adoc 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 2, name: 'op', attr: ['2','C1', 'C1'],}, 7 | {bits: 5, name: 'shamt[4:0]', attr: ['5','shamt[4:0]', 'shamt[4:0]'],}, 8 | {bits: 3, name: 'rd′/rs1′', attr: ['3','dest', 'dest'],}, 9 | {bits: 2, name: 'funct2', attr: ['2','C.SRLI', 'C.SRAI'],}, 10 | {bits: 1, name: 'shamt[5]', attr: ['1','shamt[5]', 'shamt[5]'],}, 11 | {bits: 3, name: 'funct3', attr: ['3','C.SRLI', 'C.SRAI'],}, 12 | ]} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/counters-diag.edn: -------------------------------------------------------------------------------- 1 | //# 11 Counters 2 | //## 11.1 Base Counters and Timers 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM','SYSTEM']}, 8 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest']}, 9 | {bits: 3, name: 'funct3', attr: ['3','CSRRS','CSRRS','CSRRS']}, 10 | {bits: 5, name: 'rs1', attr: ['5','0','0','0']}, 11 | {bits: 12, name: 'csr', attr: ['12','RDCYCLE[H]', 'RDTIME[H]','RDINSTRET[H]']}, 12 | ]} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/csr-instr.edn: -------------------------------------------------------------------------------- 1 | //# 10 "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 2 | //## 10.1 CSR Instructions 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM', 'SYSTEM'] }, 8 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest', 'dest'] }, 9 | {bits: 3, name: 'funct3', attr: ['3', 'CSRRW', 'CSRRS', 'CSRRC', 'CSRRWI', 'CSRRSI', 'CSRRCI'] }, 10 | {bits: 5, name: 'rs1', attr: ['5', 'source', 'source', 'source', 'uimm[4:0]', 'uimm[4:0]', 'uimm[4:0]'] }, 11 | {bits: 12, name: 'csr', attr: ['12', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest', 'source/dest'], }, 12 | ]} 13 | .... 14 | 15 | //[wavedrom, ,] 16 | //.... 17 | //{reg: [ 18 | // {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM','SYSTEM','SYSTEM'] }, 19 | // {bits: 5, name: 'rd', attr: ['3', 'dest','dest', 'dest' ] }, 20 | // {bits: 3, name: 'funct3', attr: ['3', 'CSRRWI', 'CSRRSI', 'CSRRCI'] }, 21 | // {bits: 5, name: 'rs1', attr: ['5', 'uimm[4:0]','uimm[4:0]', 'uimm[4:0]'] }, 22 | // {bits: 12, name: 'csr', attr: ['12', 'source/dest','source/dest','source/dest'] }, 23 | //]} 24 | //.... 25 | -------------------------------------------------------------------------------- /src/images/wavedrom/ct-conditional.edn: -------------------------------------------------------------------------------- 1 | //### Conditional Branches 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'BRANCH', 'BRANCH', 'BRANCH'] }, 7 | {bits: 5, name: 'imm[4:1|11]', attr: ['5', 'offset[4:1|11]', 'offset[4:1|11]', 'offset[4:1|11]'] }, 8 | {bits: 3, name: 'funct3', attr: ['3', 'BEQ/BNE', 'BLT[U]', 'BGE[U]'] }, 9 | {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1'] }, 10 | {bits: 5, name: 'rs2', attr: ['5', 'src2','src2', 'src2'] }, 11 | {bits: 7, name: 'imm[12|10:5]', attr: ['7', 'offset[12|10:5]', 'offset[12|10:5]', 'offset[12|10:5]'] }, 12 | ], config:{fontsize: 10}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/ct-unconditional-2.edn: -------------------------------------------------------------------------------- 1 | //ct-unconditional-2 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'JALR'] }, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest'] }, 8 | {bits: 3, name: 'funct3', attr: ['3', '0'] }, 9 | {bits: 5, name: 'rs1', attr: ['5', 'base'] }, 10 | {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]'] }, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/ct-unconditional.edn: -------------------------------------------------------------------------------- 1 | //## 2.5 Control Transfer Instructions 2 | //### Unconditional Jumps 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7', 'JAL']}, 8 | {bits: 5, name: 'rd', attr: ['5', 'dest']}, 9 | {bits: 8, name: 'imm[19:12]', attr: ['8']}, 10 | {bits: 1, name: '[11]', attr: ['1']}, 11 | {bits: 10, name: 'imm[10:1]', attr: ['10', 'offset[20:1]']}, 12 | {bits: 1, name: '[20]', attr: ['1']}, 13 | ], config:{fontsize: 12}} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/d-xwwx.edn: -------------------------------------------------------------------------------- 1 | //xw-wx 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','000','000']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','D','D']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FMV.X.D','FMV.D.X']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/division-op.edn: -------------------------------------------------------------------------------- 1 | //## 8.2 Division Operations 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, 8 | {bits: 3, name: 'funct3', attr: ['3','DIV[U]/REM[U]', 'DIV[U]W/REM[U]W']}, 9 | {bits: 5, name: 'rs1', attr: ['5', 'dividend', 'dividend']}, 10 | {bits: 5, name: 'rs2', attr: ['5', 'divisor', 'divisor']}, 11 | {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']}, 12 | ]} 13 | .... 14 | 15 | //[wavedrom, ,svg] 16 | //.... 17 | //{reg: [ 18 | // {bits: 7, name: 'opcode', attr: 'OP-32'}, 19 | // {bits: 5, name: 'rd', attr: 'dest'}, 20 | // {bits: 3, name: 'funct3', attr: ['DIVW', 'DIVUW', 'REMW', 'REMUW']}, 21 | // {bits: 5, name: 'rs1', attr: 'dividend'}, 22 | // {bits: 5, name: 'rs2', attr: 'divisor'}, 23 | // {bits: 7, name: 'funct7', attr: 'MULDIV'}, 24 | //]} 25 | //.... 26 | -------------------------------------------------------------------------------- /src/images/wavedrom/double-fl-class.edn: -------------------------------------------------------------------------------- 1 | //## 13.7 Double-Precision Floating-Point Classify Instruction 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','1']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','D']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/double-fl-compare.edn: -------------------------------------------------------------------------------- 1 | //## 13.6 Double-Precision Floating-Point Compare Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','D']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCMP']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/double-fl-compute.edn: -------------------------------------------------------------------------------- 1 | //## 13.4 Double-Precision Floating-Point Computational Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','D','D','D','D']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, 13 | ]} 14 | .... 15 | 16 | [wavedrom, ,svg] 17 | .... 18 | {reg: [ 19 | {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, 20 | {bits: 5, name: 'rd', attr: ['5','dest']}, 21 | {bits: 3, name: 'rm', attr: ['3','RM']}, 22 | {bits: 5, name: 'rs1', attr: ['5','src']}, 23 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 24 | {bits: 2, name: 'fmt', attr: ['2','D']}, 25 | {bits: 5, name: 'rs3', attr: ['5','src3']}, 26 | ]} 27 | .... 28 | 29 | //[wavedrom, ,] 30 | //.... 31 | //{reg: [ 32 | // {bits: 7, name: 'opcode', attr: 'OP-FP'}, 33 | // {bits: 5, name: 'rd', attr: 'dest'}, 34 | // {bits: 3, name: 'funct3', attr: ['MIN', 'MAX']}, 35 | // {bits: 5, name: 'rs1', attr: 'src1'}, 36 | // {bits: 5, name: 'rs2', attr: 'src2'}, 37 | // {bits: 2, name: 'fmt', attr: 'D'}, 38 | // {bits: 5, name: 'funct5', attr: 'FMIN-MAX'}, 39 | //]} 40 | //.... 41 | 42 | //[wavedrom, ,] 43 | //.... 44 | //{reg: [ 45 | // {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, 46 | // {bits: 5, name: 'rd', attr: 'dest'}, 47 | // {bits: 3, name: 'funct3', attr: 'RM'}, 48 | // {bits: 5, name: 'rs1', attr: 'src1'}, 49 | // {bits: 5, name: 'rs2', attr: 'src2'}, 50 | // {bits: 2, name: 'fmt', attr: 'D'}, 51 | // {bits: 5, name: 'rs3', attr: 'src3'}, 52 | //]} 53 | //.... 54 | -------------------------------------------------------------------------------- /src/images/wavedrom/double-fl-convert-mv.edn: -------------------------------------------------------------------------------- 1 | //## 13.5 Double-Precision Floating-Point Conversion and Move Instructions 2 | 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 8 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 9 | {bits: 3, name: 'rm', attr: ['3','RM','RM']}, 10 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 11 | {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]']}, 12 | {bits: 2, name: 'fmt', attr: ['2','D','D']}, 13 | {bits: 5, name: 'funct5', attr: ['5','FCVT.int.D','FCVT.D.int']}, 14 | ]} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/double-ls.edn: -------------------------------------------------------------------------------- 1 | //# "D" Standard Extension for Double-Precision Floating-Point, Version 2.2 2 | //## 13.3 Double-Precision Load and Store Instructions 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','LOAD-FP']}, 8 | {bits: 5, name: 'rd', attr: ['5','dest']}, 9 | {bits: 3, name: 'width', attr: ['3','D']}, 10 | {bits: 5, name: 'rs1', attr: ['5','base']}, 11 | {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']}, 12 | ]} 13 | .... 14 | 15 | [wavedrom, ,svg] 16 | .... 17 | {reg: [ 18 | {bits: 7, name: 'opcode', attr: ['7','STORE-FP']}, 19 | {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]']}, 20 | {bits: 3, name: 'width', attr: ['3','D']}, 21 | {bits: 5, name: 'rs1', attr: ['5','base']}, 22 | {bits: 5, name: 'rs2', attr: ['5','src']}, 23 | {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']}, 24 | ]} 25 | .... 26 | -------------------------------------------------------------------------------- /src/images/wavedrom/env-call-breakpoint.edn: -------------------------------------------------------------------------------- 1 | //## 2.8 Environment Call and Breakpoints 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']}, 7 | {bits: 5, name: 'rd', attr: ['5', '0', '0']}, 8 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV', 'PRIV']}, 9 | {bits: 5, name: 'rs1', attr: ['5', '0', '0']}, 10 | {bits: 12, name: 'func12', attr: ['12', 'ECALL', 'EBREAK']}, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/fcvt-sd-ds.edn: -------------------------------------------------------------------------------- 1 | //FCVT.S.D and FCVT.D.S 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','D', 'S']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S','D']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCVT.S.D', 'FCVT.D.S']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/float-csr.edn: -------------------------------------------------------------------------------- 1 | //# "F" Standard Extension for Single-Precision Floating-Point, Version 2.2 2 | //## 12.2 Floating-Point Control and Status Register 3 | //### Figure 12.2: Floating-point control and status register. 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 1, name: 'NX', attr: ['1']}, 9 | {bits: 1, name: 'UF', attr: ['1']}, 10 | {bits: 1, name: 'OF', attr: ['1']}, 11 | {bits: 1, name: 'DZ', attr: ['1']}, 12 | {bits: 1, name: 'NV', attr: ['1']}, 13 | {bits: 3, name: 'Rounding Mode', attr:['3']}, 14 | {bits: 24, name: 'Reserved', attr:['24']}, 15 | ], config: {fontsize: 10}} 16 | .... 17 | -------------------------------------------------------------------------------- /src/images/wavedrom/flt-pt-to-int-move.edn: -------------------------------------------------------------------------------- 1 | // 16.3 Instructions for moving bit patterns between floating-point and integer registers. 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','000','000']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','H','H']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FMV.X.H','FMV.H.X']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/flt-to-flt-sgn-inj-instr.edn: -------------------------------------------------------------------------------- 1 | // 16.3 Floating point to floating point sign injection instructions. 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'funct3', attr: ['3','J[N]/JX']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','H']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/fsjgnjnx-d.edn: -------------------------------------------------------------------------------- 1 | //FSGNJ.D, FSGNJN.D, and FSGNJX.D 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','J[N]/JX']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','D']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/half-ls.edn: -------------------------------------------------------------------------------- 1 | //## 15.1 Half-Precision Load and Store Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: 'LOAD-FP'}, 7 | {bits: 5, name: 'rd', attr: 'dest'}, 8 | {bits: 3, name: 'width', attr: 'H'}, 9 | {bits: 5, name: 'rs1', attr: 'base'}, 10 | {bits: 12, name: 'imm[11:0]', attr: 'offset'}, 11 | ]} 12 | 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/half-pr-flt-pt-class.edn: -------------------------------------------------------------------------------- 1 | //## 15.5 Half-Precision Floating-Point Classify Instruction 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','001']}, 9 | {bits: 5, name: 'rs1', attr: ['5', 'src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','H']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/half-pr-flt-pt-compare.edn: -------------------------------------------------------------------------------- 1 | // 16.4 Half-Precision Floating-Point Compare Instructions. 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','H']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCMP']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/half-prec-conv-and-mv.edn: -------------------------------------------------------------------------------- 1 | //## 16.3 Half-Precision Conversion and Move Instructions 2 | 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 8 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 9 | {bits: 3, name: 'rm', attr: ['3','RM','RM']}, 10 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 11 | {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]','W[U]/L[U]']}, 12 | {bits: 2, name: 'fmt', attr: ['2','H', 'H']}, 13 | {bits: 5, name: 'funct5', attr: ['5','FCVT.int.H','FCVT.H.int']}, 14 | ]} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/half-prec-flpt-to-flpt-conv.edn: -------------------------------------------------------------------------------- 1 | //## 16.3 Half-Precision Floating Point to Floating Point Conversion Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM','RM','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src','src','src','src','SRC']}, 10 | {bits: 5, name: 'rs2', attr: ['5','H','S','H','D','H','Q']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S','H','D','H','Q','H']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCVT.S.H','FCVT.H.S','FCVT.D.H','FCVT.H.D','FCVT.Q.H','FCVT.H.Q']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/hinvalgvma.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, 5 | {bits: 5, name: 'rd', attr: ['5', '0']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, 7 | {bits: 5, name: 'rs1', attr: ['5', 'gaddr']}, 8 | {bits: 5, name: 'rs2', attr: ['5', 'vmid']}, 9 | {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.GVMA']}, 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/hinvalvvma.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, 5 | {bits: 5, name: 'rd', attr: ['5', '0']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, 7 | {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, 8 | {bits: 5, name: 'rs2', attr: ['5', 'asid']}, 9 | {bits: 7, name: 'funct7', attr: ['7', 'HINVAL.VVMA']}, 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/hypv-mm-fence.edn: -------------------------------------------------------------------------------- 1 | //hypv-mm-fence.edn 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM', 'SYSTEM']}, 7 | {bits: 5, name: 'rd', attr: ['5','0', '0']}, 8 | {bits: 3, name: 'funct3', attr: ['3','PRIV', 'PRIV']}, 9 | {bits: 5, name: 'rs1', attr: ['5','vaddr', 'gaddr']}, 10 | {bits: 5, name: 'rs2', attr: ['5','asid', 'vmid']}, 11 | {bits: 7, name: 'funct7', attr: ['7','HFENCE.VVMA', 'HFENCE.GVMA']}, 12 | ], config: {bits: 32}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/hypv-virt-load-and-store.edn: -------------------------------------------------------------------------------- 1 | //hypv-virt-load-and-store.edn 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','SYSTEM', 'SYSTEM', 'SYSTEM']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest', 'dest', '0']}, 8 | {bits: 3, name: 'funct3', attr: ['3','PRIVM', 'PRIVM', 'PRIVM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','addr', 'addr', 'addr']}, 10 | {bits: 5, name: 'rs2', attr: ['5','[U]', 'HLVX', 'src']}, 11 | {bits: 7, name: 'funct7', attr: ['7','HLV.width', 'HLVX.HU/WU', 'HSV.width']}, 12 | ], config: {bits: 32}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/i-immediate.edn: -------------------------------------------------------------------------------- 1 | //### Figure 2.4 2 | //Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31]. 3 | //#### I-immediate 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 1, name: '[20]'}, 9 | {bits: 4, name: 'inst[24:21]'}, 10 | {bits: 6, name: 'inst[30:25]'}, 11 | {bits: 21, name: '— inst[31] —'}, 12 | ], config:{fontsize: 12, label:{right: 'I-immediate'}}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/immediate-variants.edn: -------------------------------------------------------------------------------- 1 | //## 2.3 Immediate Encoding Variants 2 | //### Figure 2.3 3 | //RISC-V base instruction formats showing immediate variants. 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode'}, 9 | {bits: 5, name: 'rd'}, 10 | {bits: 3, name: 'funct3'}, 11 | {bits: 5, name: 'rs1'}, 12 | {bits: 5, name: 'rs2'}, 13 | {bits: 7, name: 'funct7'} 14 | ], config: {label: {right: 'R-Type'}}} 15 | .... 16 | 17 | [wavedrom, ,svg] 18 | .... 19 | {reg: [ 20 | {bits: 7, name: 'opcode'}, 21 | {bits: 5, name: 'rd'}, 22 | {bits: 3, name: 'funct3'}, 23 | {bits: 5, name: 'rs1'}, 24 | {bits: 12, name: 'imm[11:0]'}, 25 | ], config: {label: {right: 'I-Type'}}} 26 | .... 27 | 28 | [wavedrom, ,svg] 29 | .... 30 | {reg: [ 31 | {bits: 7, name: 'opcode'}, 32 | {bits: 5, name: 'imm[4:0]'}, 33 | {bits: 3, name: 'funct3'}, 34 | {bits: 5, name: 'rs1'}, 35 | {bits: 5, name: 'rs2'}, 36 | {bits: 7, name: 'imm[11:5]'} 37 | ], config: {label: {right: 'S-Type'}}} 38 | .... 39 | 40 | [wavedrom, ,svg] 41 | .... 42 | {reg: [ 43 | {bits: 7, name: 'opcode'}, 44 | {bits: 1, name: '[11]'}, 45 | {bits: 4, name: 'imm[4:1]'}, 46 | {bits: 3, name: 'funct3'}, 47 | {bits: 5, name: 'rs1'}, 48 | {bits: 5, name: 'rs2'}, 49 | {bits: 6, name: 'imm[10:5]'}, 50 | {bits: 1, name: '[12]'} 51 | ], config: {fontsize: 12, label: {right: 'B-Type'}}} 52 | .... 53 | 54 | [wavedrom, ,svg] 55 | .... 56 | {reg: [ 57 | {bits: 7, name: 'opcode'}, 58 | {bits: 5, name: 'rd'}, 59 | {bits: 20, name: 'imm[31:12]'} 60 | ], config: {label: {right: 'U-Type'}}} 61 | .... 62 | 63 | [wavedrom, ,svg] 64 | .... 65 | {reg: [ 66 | {bits: 7, name: 'opcode'}, 67 | {bits: 5, name: 'rd'}, 68 | {bits: 8, name: 'imm[19:12]'}, 69 | {bits: 1, name: '[11]'}, 70 | {bits: 10, name: 'imm[10:1]'}, 71 | {bits: 1, name: '[20]'} 72 | ], config: {fontsize: 12, label: {right: 'J-Type'}}} 73 | .... 74 | -------------------------------------------------------------------------------- /src/images/wavedrom/immediate.edn: -------------------------------------------------------------------------------- 1 | //### Figure 2.4 2 | //Types of immediate produced by RISC-V instructions. The fields are labeled with the instruction bits used to construct their value. Sign extension always uses inst[31]. 3 | //#### I-immediate 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 1, name: '[20]'}, 9 | {bits: 4, name: 'inst[24:21]'}, 10 | {bits: 6, name: 'inst[30:25]'}, 11 | {bits: 21, name: '— inst[31] —'}, 12 | ], config:{fontsize: 12, label:{right: 'I-immediate'}}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/instruction-formats.edn: -------------------------------------------------------------------------------- 1 | //### Figure 2.2 2 | 3 | //RISC-V base instruction formats. Each immediate subfield is labeled with the bit position (imm[x]) in the immediate value being produced, rather than the bit position within the instruction’s immediate field as is usually done. 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode'}, 9 | {bits: 5, name: 'rd'}, 10 | {bits: 3, name: 'funct3'}, 11 | {bits: 5, name: 'rs1'}, 12 | {bits: 5, name: 'rs2'}, 13 | {bits: 7, name: 'funct7'} 14 | ], config: {label: {right: 'R-Type'}}} 15 | .... 16 | 17 | [wavedrom, ,svg] 18 | .... 19 | {reg: [ 20 | {bits: 7, name: 'opcode'}, 21 | {bits: 5, name: 'rd'}, 22 | {bits: 3, name: 'funct3'}, 23 | {bits: 5, name: 'rs1'}, 24 | {bits: 12, name: 'imm[11:0]'}, 25 | ], config: {label: {right: 'I-Type'}}} 26 | .... 27 | 28 | [wavedrom, ,svg] 29 | .... 30 | {reg: [ 31 | {bits: 7, name: 'opcode'}, 32 | {bits: 5, name: 'imm[4:0]'}, 33 | {bits: 3, name: 'funct3'}, 34 | {bits: 5, name: 'rs1'}, 35 | {bits: 5, name: 'rs2'}, 36 | {bits: 7, name: 'imm[11:5]'} 37 | ], config: {label: {right: 'S-Type'}}} 38 | .... 39 | 40 | [wavedrom, ,svg] 41 | .... 42 | {reg: [ 43 | {bits: 7, name: 'opcode'}, 44 | {bits: 5, name: 'rd'}, 45 | {bits: 20, name: 'imm[31:12]'} 46 | ], config: {label: {right: 'U-Type'}}} 47 | .... 48 | -------------------------------------------------------------------------------- /src/images/wavedrom/int-comp-lui-aiupc.edn: -------------------------------------------------------------------------------- 1 | //FROM ## 2.4 Integer Computational Instructions 2 | //### Integer Register-Immediate Instructions 3 | //lui-aiupc-u-immed 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC']}, 9 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, 10 | {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']} 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/int-comp-slli-srli-srai.edn: -------------------------------------------------------------------------------- 1 | //FROM ## 2.4 Integer Computational Instructions 2 | //### Integer Register-Immediate Instructions 3 | // 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']}, 9 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, 10 | {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']}, 11 | {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, 12 | {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']}, 13 | {bits: 7, name: 'imm[11:5]', attr: ['7', 0, 0, 32]} 14 | ]} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/int-reg-reg.edn: -------------------------------------------------------------------------------- 1 | //### Integer Register-Register Operations 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP', 'OP']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest','dest']}, 8 | {bits: 3, name: 'funct3', attr: ['3', 'ADD/SLT[U]', 'AND/OR/XOR', 'SLL/SRL', 'SUB/SRA']}, 9 | {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2']}, 11 | {bits: 7, name: 'funct7', attr: ['7', 0, 0, 0, 32]} 12 | ]} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/integer-computational.edn: -------------------------------------------------------------------------------- 1 | //## 2.4 Integer Computational Instructions 2 | //### Integer Register-Immediate Instructions 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM']}, 8 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, 9 | {bits: 3, name: 'funct3', attr: ['3', 'ADDI/SLTI[U]', 'ANDI/ORI/XORI']}, 10 | {bits: 5, name: 'rs1', attr: ['5', 'src', 'src']}, 11 | {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]', 'I-immediate[11:0]']} 12 | ]} 13 | .... 14 | 15 | // 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/j-immediate.edn: -------------------------------------------------------------------------------- 1 | //#### J-immediate 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 1, name: '0'}, 7 | {bits: 4, name: 'inst[24:21]'}, 8 | {bits: 6, name: 'inst[30:25]'}, 9 | {bits: 1, name: '[20]'}, 10 | {bits: 8, name: 'inst[19:12]'}, 11 | {bits: 12, name: '— inst[31] —'}, 12 | ], config:{fontsize: 12, label:{right: 'J-immediate'}}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/load-reserve-st-conditional.edn: -------------------------------------------------------------------------------- 1 | //# 9 "A" Standard Extension for Atomic Instructions, Version 2.1 2 | //## 9.2 Load-Reserved/Store-Conditional Instructions 3 | 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode', attr: ['7', 'AMO', 'AMO']}, 9 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, 10 | {bits: 3, name: 'funct3', attr: ['3', 'width', 'width']}, 11 | {bits: 5, name: 'rs1', attr: ['5', 'addr', 'addr']}, 12 | {bits: 5, name: 'rs2', attr: ['5', '0', 'src']}, 13 | {bits: 1, name: 'rl', attr: ['1', 'ring', 'ring']}, 14 | {bits: 1, name: 'aq', attr: ['1', 'orde', 'orde']}, 15 | {bits: 5, name: 'funct5', attr: ['5', 'LR.W/D', 'SC.W/D']}, 16 | ]} 17 | .... 18 | -------------------------------------------------------------------------------- /src/images/wavedrom/load-store.edn: -------------------------------------------------------------------------------- 1 | //## 2.6 Load and Store Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'LOAD']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest']}, 8 | {bits: 3, name: 'funct3', attr: ['3', 'width']}, 9 | {bits: 5, name: 'rs1', attr: ['5', 'base']}, 10 | {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, 11 | ]} 12 | .... 13 | 14 | [wavedrom, ,svg] 15 | .... 16 | {reg: [ 17 | {bits: 7, name: 'opcode', attr: ['7', 'STORE']}, 18 | {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, 19 | {bits: 3, name: 'funct3', attr: ['3', 'width']}, 20 | {bits: 5, name: 'rs1', attr: ['5', 'base']}, 21 | {bits: 5, name: 'rs2', attr: ['5', 'src']}, 22 | {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, 23 | ]} 24 | .... 25 | -------------------------------------------------------------------------------- /src/images/wavedrom/m-st-ext-for-int-mult.edn: -------------------------------------------------------------------------------- 1 | //# 8 "M" Standard Extension for Integer Multiplication and Division, Version 2.0 2 | //## 8.1 Multiplication Operations 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP-32']}, 8 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, 9 | {bits: 3, name: 'funct3', attr: ['3', 'MUL/MULH[[S]U]', 'MULW']}, 10 | {bits: 5, name: 'rs1', attr: ['5', 'multiplicand', 'multiplicand']}, 11 | {bits: 5, name: 'rs2', attr: ['5', 'multiplier', 'multiplier']}, 12 | {bits: 7, name: 'funct7', attr: ['7', 'MULDIV', 'MULDIV']}, 13 | ]} 14 | .... 15 | 16 | //[wavedrom, ,] 17 | //.... 18 | //{reg: [ 19 | // {bits: 7, name: 'opcode', attr: 'OP-32'}, 20 | // {bits: 5, name: 'rd', attr: 'dest'}, 21 | // {bits: 3, name: 'funct3', attr: 'MULW'}, 22 | // {bits: 5, name: 'rs1', attr: 'multiplicand'}, 23 | // {bits: 5, name: 'rs2', attr: 'multiplier'}, 24 | // {bits: 7, name: 'funct7', attr: 'MULDIV'}, 25 | //]} 26 | //.... 27 | -------------------------------------------------------------------------------- /src/images/wavedrom/mem-order.edn: -------------------------------------------------------------------------------- 1 | //## 2.7 Memory Ordering Instructions 2 | 3 | [wavedrom,mem-order ,] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM']}, 7 | {bits: 5, name: 'rd', attr: ['5', '0']}, 8 | {bits: 3, name: 'funct3', attr: ['3', 'FENCE']}, 9 | {bits: 5, name: 'rs1', attr: ['5', '0']}, 10 | {bits: 1, name: 'SW', attr: 1}, 11 | {bits: 1, name: 'SR', attr: 1}, 12 | {bits: 1, name: 'SO', attr: 1}, 13 | {bits: 1, name: 'SI', attr: 1}, 14 | {bits: 1, name: 'PW', attr: 1}, 15 | {bits: 1, name: 'PR', attr: 1}, 16 | {bits: 1, name: 'PO', attr: 1}, 17 | {bits: 1, name: 'PI', attr: 1}, 18 | {bits: 4, name: 'fm', attr: ['4', 'FM']}, 19 | ]} 20 | .... 21 | -------------------------------------------------------------------------------- /src/images/wavedrom/menvcfgreg.edn: -------------------------------------------------------------------------------- 1 | //.Machine environment configuration (`menvcfg`) register. 2 | [wavedrom, ,svg] 3 | .... 4 | {reg: [ 5 | {bits: 1, name: 'FIOM'}, 6 | {bits: 1, name: 'WPRI'}, 7 | {bits: 1, name: 'LPE'}, 8 | {bits: 1, name: 'SSE'}, 9 | {bits: 2, name: 'CBIE'}, 10 | {bits: 1, name: 'CBCFE'}, 11 | {bits: 1, name: 'CBZE'}, 12 | {bits: 24, name: 'WPRI'}, 13 | {bits: 2, name: 'PMM'}, 14 | {bits: 25, name: 'WPRI'}, 15 | {bits: 1, name: 'DTE'}, 16 | {bits: 1, name: 'CDE'}, 17 | {bits: 1, name: 'ADUE'}, 18 | {bits: 1, name: 'PBMTE'}, 19 | {bits: 1, name: 'STCE'}, 20 | ], config:{lanes: 4, hspace:1024}} 21 | .... 22 | -------------------------------------------------------------------------------- /src/images/wavedrom/mm-env-call.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','SYSTEM','SYSTEM'],}, 8 | {bits: 5, name: 'rd', attr: ['5','0','0'],}, 9 | {bits: 3, name: 'funct3', attr: ['3','PRIV','PRIV'],}, 10 | {bits: 5, name: 'rs1', attr: ['5','0','0'],}, 11 | {bits: 12, name: 'funct12', attr: ['12','ECALL','EBREAK',]}, 12 | ], config: {bits: 32}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/mop-r.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg:[ 4 | { bits: 7, name: 0x73, attr: ['SYSTEM']}, 5 | { bits: 5, name: 'rd'}, 6 | { bits: 3, name: 0x4 }, 7 | { bits: 5, name: 'rs1'}, 8 | { bits: 2, name: 'n[1:0]' }, 9 | { bits: 4, name: 0x7 }, 10 | { bits: 2, name: 'n[3:2]' }, 11 | { bits: 2, name: 0x0 }, 12 | { bits: 1, name: 'n[4]' }, 13 | { bits: 1, name: 0x1 }, 14 | ], config: {fontsize: 11}} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/mop-rr.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg:[ 4 | { bits: 7, name: 0x73, attr: ['SYSTEM']}, 5 | { bits: 5, name: 'rd'}, 6 | { bits: 3, name: 0x4 }, 7 | { bits: 5, name: 'rs1'}, 8 | { bits: 5, name: 'rs2'}, 9 | { bits: 1, name: 0x1 }, 10 | { bits: 2, name: 'n[1:0]' }, 11 | { bits: 2, name: 0x0 }, 12 | { bits: 1, name: 'n[2]' }, 13 | { bits: 1, name: 0x1 }, 14 | ], config: {fontsize: 11}} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/mseccfg.edn: -------------------------------------------------------------------------------- 1 | //.Machine security configuration (`mseccfg`) register. 2 | [wavedrom, ,svg] 3 | .... 4 | {reg: [ 5 | {bits: 1, name: 'MML'}, 6 | {bits: 1, name: 'MMWP'}, 7 | {bits: 1, name: 'RLB'}, 8 | {bits: 5, name: 'WPRI'}, 9 | {bits: 1, name: 'USEED'}, 10 | {bits: 1, name: 'SSEED'}, 11 | {bits: 1, name: 'MLPE'}, 12 | {bits: 21, name: 'WPRI'}, 13 | {bits: 2, name: 'PMM'}, 14 | {bits: 30, name: 'WPRI'}, 15 | ], config:{lanes: 4, hspace:1024}} 16 | .... 17 | -------------------------------------------------------------------------------- /src/images/wavedrom/mstatushreg.edn: -------------------------------------------------------------------------------- 1 | //.Additional machine-mode status (`mstatush`) register for RV32. 2 | [wavedrom, ,svg] 3 | .... 4 | {reg: [ 5 | {bits: 4, name: 'WPRI'}, 6 | {bits: 1, name: 'SBE'}, 7 | {bits: 1, name: 'MBE'}, 8 | {bits: 1, name: 'GVA'}, 9 | {bits: 1, name: 'MPV'}, 10 | {bits: 1, name: 'WPRI'}, 11 | {bits: 1, name: 'MPELP'}, 12 | {bits: 1, name: 'MDT'}, 13 | {bits: 21, name: 'WPRI'}, 14 | ], config:{lanes: 2, hspace:1024}} 15 | .... 16 | -------------------------------------------------------------------------------- /src/images/wavedrom/mstatusreg-rv321.edn: -------------------------------------------------------------------------------- 1 | //.Machine-mode status (`mstatus`) register for RV32 2 | [wavedrom, ,svg] 3 | .... 4 | {reg: [ 5 | {bits: 1, name: 'WPRI'}, 6 | {bits: 1, name: 'SIE'}, 7 | {bits: 1, name: 'WPRI'}, 8 | {bits: 1, name: 'MIE'}, 9 | {bits: 1, name: 'WPRI'}, 10 | {bits: 1, name: 'SPIE'}, 11 | {bits: 1, name: 'UBE'}, 12 | {bits: 1, name: 'MPIE'}, 13 | {bits: 1, name: 'SPP'}, 14 | {bits: 2, name: 'VS[1:0]'}, 15 | {bits: 2, name: 'MPP[1:0]'}, 16 | {bits: 2, name: 'FS[1:0]'}, 17 | {bits: 2, name: 'XS[1:0]'}, 18 | {bits: 1, name: 'MPRV'}, 19 | {bits: 1, name: 'SUM'}, 20 | {bits: 1, name: 'MXR'}, 21 | {bits: 1, name: 'TVM'}, 22 | {bits: 1, name: 'TW'}, 23 | {bits: 1, name: 'TSR'}, 24 | {bits: 1, name: 'SPELP'}, 25 | {bits: 1, name: 'SDT'}, 26 | {bits: 6, name: 'WPRI'}, 27 | {bits: 1, name: 'SD'}, 28 | ], config:{lanes: 2, hspace:1024}} 29 | .... 30 | -------------------------------------------------------------------------------- /src/images/wavedrom/mstatusreg.edn: -------------------------------------------------------------------------------- 1 | //.Machine-mode status (`mstatus`) register for RV64 2 | [wavedrom, ,svg] 3 | .... 4 | {reg: [ 5 | {bits: 1, name: 'WPRI'}, 6 | {bits: 1, name: 'SIE'}, 7 | {bits: 1, name: 'WPRI'}, 8 | {bits: 1, name: 'MIE'}, 9 | {bits: 1, name: 'WPRI'}, 10 | {bits: 1, name: 'SPIE'}, 11 | {bits: 1, name: 'UBE'}, 12 | {bits: 1, name: 'MPIE'}, 13 | {bits: 1, name: 'SPP'}, 14 | {bits: 2, name: 'VS[1:0]'}, 15 | {bits: 2, name: 'MPP[1:0]'}, 16 | {bits: 2, name: 'FS[1:0]'}, 17 | {bits: 2, name: 'XS[1:0]'}, 18 | {bits: 1, name: 'MPRV'}, 19 | {bits: 1, name: 'SUM'}, 20 | {bits: 1, name: 'MXR'}, 21 | {bits: 1, name: 'TVM'}, 22 | {bits: 1, name: 'TW'}, 23 | {bits: 1, name: 'TSR'}, 24 | {bits: 1, name: 'SPELP'}, 25 | {bits: 1, name: 'SDT'}, 26 | {bits: 7, name: 'WPRI'}, 27 | {bits: 2, name: 'UXL[1:0]'}, 28 | {bits: 2, name: 'SXL[1:0]'}, 29 | {bits: 1, name: 'SBE'}, 30 | {bits: 1, name: 'MBE'}, 31 | {bits: 1, name: 'GVA'}, 32 | {bits: 1, name: 'MPV'}, 33 | {bits: 1, name: 'WPRI'}, 34 | {bits: 1, name: 'MPELP'}, 35 | {bits: 1, name: 'MDT'}, 36 | {bits: 20, name: 'WPRI'}, 37 | {bits: 1, name: 'SD'}, 38 | ], config:{lanes: 4, hspace:1024}} 39 | .... 40 | -------------------------------------------------------------------------------- /src/images/wavedrom/nop.edn: -------------------------------------------------------------------------------- 1 | //### NOP Instruction 2 | [wavedrom, ,svg] 3 | .... 4 | {reg: [ 5 | {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM']}, 6 | {bits: 5, name: 'rd', attr: ['5', '0']}, 7 | {bits: 3, name: 'funct3', attr: ['3', 'ADDI']}, 8 | {bits: 5, name: 'rs1', attr: ['5', '0']}, 9 | {bits: 12, name: 'imm[11:0]', attr: ['12', '0']} 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-cnvrt-intch-xqqx.edn: -------------------------------------------------------------------------------- 1 | //quad-cnvrt-intch-xqqx 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3', 'J[N]/JX']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','Q']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-cnvrt-mv.edn: -------------------------------------------------------------------------------- 1 | //## 14.3 Quad-Precision Convert and Move Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]', 'W[U]/L[U]']}, 11 | {bits: 2, name: 'fmt', attr: ['2','Q','Q']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCVT.int.Q','FCVT.Q.int']}, 13 | ]} 14 | .... 15 | 16 | //[wavedrom, ,] 17 | //.... 18 | //{reg: [ 19 | // {bits: 7, name: 'opcode', attr: 'OP-FP'}, 20 | // {bits: 5, name: 'rd', attr: 'dest'}, 21 | // {bits: 3, name: 'rm', attr: 'RM'}, 22 | // {bits: 5, name: 'rs1', attr: 'src'}, 23 | // {bits: 5, name: 'rs2', attr: ['W', 'WU', 'L', 'LU']}, 24 | // {bits: 2, name: 'fmt', attr: 'Q'}, 25 | // {bits: 5, name: 'funct5', attr: 'FCVT.Q.int'}, 26 | //]} 27 | //.... 28 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-cnvt-interchange.edn: -------------------------------------------------------------------------------- 1 | //14 conv-mv 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'OP-FP', 'OP-FP','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM','RM','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src','src','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','Q', 'S', 'Q', 'D']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S','Q', 'D', 'Q']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCVT.S.Q', 'FCVT.Q.S', 'FCVT.D.Q', 'FCVT.Q.D']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-compute.edn: -------------------------------------------------------------------------------- 1 | //## 14.2 Quad-Precision Computational Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM','MIN/MAX','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1','src1','src1','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2','src2','src2','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','Q','Q','Q','Q']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, 13 | ]} 14 | .... 15 | 16 | [wavedrom, ,svg] 17 | .... 18 | {reg: [ 19 | {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, 20 | {bits: 5, name: 'rd', attr: ['5','dest']}, 21 | {bits: 3, name: 'rm', attr: ['3','RM']}, 22 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 23 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 24 | {bits: 2, name: 'fmt', attr: ['2','Q']}, 25 | {bits: 5, name: 'rs3', attr: ['5','src3']}, 26 | ]} 27 | .... 28 | 29 | //[wavedrom, ,] 30 | //.... 31 | //{reg: [ 32 | // {bits: 7, name: 'opcode', attr: 'OP-FP'}, 33 | // {bits: 5, name: 'rd', attr: 'dest'}, 34 | // {bits: 3, name: 'funct3', attr: ['MIN', 'MAX']}, 35 | // {bits: 5, name: 'rs1', attr: 'src1'}, 36 | // {bits: 5, name: 'rs2', attr: 'src2'}, 37 | // {bits: 2, name: 'fmt', attr: 'Q'}, 38 | // {bits: 5, name: 'funct5', attr: 'FMIN-MAX'}, 39 | //]} 40 | //.... 41 | 42 | 43 | //[wavedrom, ,] 44 | //.... 45 | //{reg: [ 46 | // {bits: 7, name: 'opcode', attr: ['FMADD', 'FNMADD', 'FMSUB', 'FNMSUB']}, 47 | // {bits: 5, name: 'rd', attr: 'dest'} 48 | // {bits: 3, name: 'funct3', attr: 'RM'}, 49 | // {bits: 5, name: 'rs1', attr: 'src1'}, 50 | // {bits: 5, name: 'rs2', attr: 'src2'}, 51 | // {bits: 2, name: 'fmt', attr: 'Q'}, 52 | // {bits: 5, name: 'rs3', attr: 'src3'}, 53 | //]} 54 | //.... 55 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-float-clssfy.edn: -------------------------------------------------------------------------------- 1 | //## 14.5 Quad-Precision Floating-Point Classify Instruction 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','001']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','Q']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-float-compare.edn: -------------------------------------------------------------------------------- 1 | //## 14.4 Quad-Precision Floating-Point Compare Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','EQ/LT/LE']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','Q']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCMP']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/quad-ls.edn: -------------------------------------------------------------------------------- 1 | //## 14.1 Quad-Precision Load and Store Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','LOAD-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'width', attr: ['3','Q']}, 9 | {bits: 5, name: 'rs1', attr: ['5','base']}, 10 | {bits: 12, name: 'imm[11:0]', attr: ['12','offset[11:0]']}, 11 | ]} 12 | .... 13 | 14 | [wavedrom, ,svg] 15 | .... 16 | {reg: [ 17 | {bits: 7, name: 'opcode', attr: ['7','STORE-FP']}, 18 | {bits: 5, name: 'imm[4:0]', attr: ['5','offset[4:0]']}, 19 | {bits: 3, name: 'width', attr: ['3','Q']}, 20 | {bits: 5, name: 'rs1', attr: ['5','base']}, 21 | {bits: 5, name: 'rs2', attr: ['5','src']}, 22 | {bits: 7, name: 'imm[11:5]', attr: ['7','offset[11:5]']}, 23 | ]} 24 | .... 25 | -------------------------------------------------------------------------------- /src/images/wavedrom/reg-based-ldnstr.edn: -------------------------------------------------------------------------------- 1 | //Register-Based loads and Stores 2 | 3 | 4 | [wavedrom, ,svg] 5 | .... 6 | {reg: [ 7 | {bits: 2, name: 'op', attr: ['2', 'C0', 'C0', 'C0', 'C0', 'C0']}, 8 | {bits: 3, name: 'rdʹ', attr: ['3', 'dest', 'dest','dest','dest','dest']}, 9 | {bits: 2, name: 'imm', attr:['2', 'offset[2|6]', 'offset[7:6]', 'offset[7:6]', 'offset[2|6]', 'offset[7:6]']}, 10 | {bits: 3, name: 'rs1ʹ', attr: ['3', 'base', 'base', 'base', 'base', 'base']}, 11 | {bits: 3, name: 'imm', attr: ['3', 'offset[5:3]', 'offset[5:3]', 'offset[5|4|8]', 'offset[5:3]', 'offset[5:3]']}, 12 | {bits: 3, name: 'funct3', attr: ['3', 'C.LW', 'C.LD', 'C.LQ', 'C.FLW', 'C.FLD']}, 13 | ], config: {bits: 16}} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/rv64-lui-auipc.edn: -------------------------------------------------------------------------------- 1 | //lui-auipc 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'LUI', 'AUIPC']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest']}, 8 | {bits: 20, name: 'imm[31:12]', attr: ['20', 'U-immediate[31:12]', 'U-immediate[31:12]']} 9 | ]} 10 | .... 11 | -------------------------------------------------------------------------------- /src/images/wavedrom/rv64i-base-int.edn: -------------------------------------------------------------------------------- 1 | //# 6 RV64I Base Integer Instruction Set, Version 2.1 2 | //## 6.2 Integer Computational Instructions 3 | //### Integer Register-Immediate Instructions 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32']}, 9 | {bits: 5, name: 'rd', attr: ['5', 'dest']}, 10 | {bits: 3, name: 'funct3', attr: ['3', 'ADDIW']}, 11 | {bits: 5, name: 'rs1', attr: ['5', 'src']}, 12 | {bits: 12, name: 'imm[11:0]', attr: ['12', 'I-immediate[11:0]']} 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/rv64i-int-reg-reg.edn: -------------------------------------------------------------------------------- 1 | 2 | //rv64i int-reg-reg 3 | //### Integer Register-Register Operations 4 | 5 | [wavedrom, ,svg] 6 | .... 7 | {reg: [ 8 | {bits: 7, name: 'opcode', attr: ['7', 'OP', 'OP', 'OP-32', 'OP-32', 'OP-32']}, 9 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest', 'dest', 'dest']}, 10 | {bits: 3, name: 'funct3', attr: ['3', 'SLL/SRL', 'SRA', 'ADDW', 'SLLW/SRLW', 'SUBW/SRAW']}, 11 | {bits: 5, name: 'rs1', attr: ['5', 'src1', 'src1', 'src1', 'src1', 'src1']}, 12 | {bits: 5, name: 'rs2', attr: ['5', 'src2', 'src2', 'src2', 'src2', 'src2']}, 13 | {bits: 7, name: 'funct7', attr: ['7', '0000000', '0100000', '0000000', '0000000', '0100000']} 14 | ]} 15 | .... 16 | 17 | //[wavedrom, ,svg] 18 | //.... 19 | //{reg: [ 20 | // {bits: 7, name: 'opcode', attr: 'OP-32'}, 21 | // {bits: 5, name: 'rd', attr: 'dest'}, 22 | // {bits: 3, name: 'funct3', attr: ['ADDW', 'SLLW', 'SRLW', 'SUBW', 'SRAW']}, 23 | // {bits: 5, name: 'rs1', attr: 'src1'}, 24 | // {bits: 5, name: 'rs2', attr: 'src2'}, 25 | // {bits: 7, name: 'funct7', attr: [0, 0, 0, 32, 32]} 26 | //]} 27 | //.... 28 | -------------------------------------------------------------------------------- /src/images/wavedrom/rv64i-slli.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM', 'OP-IMM', 'OP-IMM']}, 5 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'SLLI', 'SRLI', 'SRAI']}, 7 | {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, 8 | {bits: 6, name: 'imm[5:0]', attr: ['6', 'shamt[5:0]', 'shamt[5:0]', 'shamt[5:0]']}, 9 | {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']} 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/rv64i-slliw.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'OP-IMM-32', 'OP-IMM-32', 'OP-IMM-32']}, 5 | {bits: 5, name: 'rd', attr: ['5', 'dest', 'dest', 'dest']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'SLLIW', 'SRLIW', 'SRAIW']}, 7 | {bits: 5, name: 'rs1', attr: ['5', 'src', 'src', 'src']}, 8 | {bits: 5, name: 'imm[4:0]', attr: ['5', 'shamt[4:0]', 'shamt[4:0]', 'shamt[4:0]']}, 9 | {bits: 1, name: '[5]', attr: ['1', '0', '0', '0']}, 10 | {bits: 6, name: 'imm[11:6]', attr: ['6', '000000', '000000', '010000']} 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/s-immediate.edn: -------------------------------------------------------------------------------- 1 | //#### S-immediate 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 1, name: '[7]'}, 7 | {bits: 4, name: 'inst[11:8]'}, 8 | {bits: 6, name: 'inst[30:25]'}, 9 | {bits: 21, name: '— inst[31] —'}, 10 | ], config:{fontsize: 12, label:{right: 'S-immediate'}}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/sfenceinvalir.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, 5 | {bits: 5, name: 'rd', attr: ['5', '0']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, 7 | {bits: 5, name: 'rs1', attr: ['5', '0']}, 8 | {bits: 5, name: 'rs2', attr: ['5', '1']}, 9 | {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.INVAL.IR']}, 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/sfencevma.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, 5 | {bits: 5, name: 'rd', attr: ['5', '0']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, 7 | {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, 8 | {bits: 5, name: 'rs2', attr: ['5', 'asid']}, 9 | {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.VMA']}, 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/sfencewinval.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, 5 | {bits: 5, name: 'rd', attr: ['5', '0']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, 7 | {bits: 5, name: 'rs1', attr: ['5', '0']}, 8 | {bits: 5, name: 'rs2', attr: ['5', '0']}, 9 | {bits: 7, name: 'funct7', attr: ['7', 'SFENCE.W.INVAL']}, 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/sinvalvma.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7', 'SYSTEM']}, 5 | {bits: 5, name: 'rd', attr: ['5', '0']}, 6 | {bits: 3, name: 'funct3', attr: ['3', 'PRIV']}, 7 | {bits: 5, name: 'rs1', attr: ['5', 'vaddr']}, 8 | {bits: 5, name: 'rs2', attr: ['5', 'asid']}, 9 | {bits: 7, name: 'funct7', attr: ['7', 'SINVAL.VMA']}, 10 | ]} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/sp-load-store-2.edn: -------------------------------------------------------------------------------- 1 | //## 12.5 Single-Precision Load and Store Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest']}, 8 | {bits: 3, name: 'width', attr: ['3', 'W']}, 9 | {bits: 5, name: 'rs1', attr: ['5', 'base']}, 10 | {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, 11 | ]} 12 | .... 13 | 14 | [wavedrom, ,svg] 15 | .... 16 | {reg: [ 17 | {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP']}, 18 | {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, 19 | {bits: 3, name: 'width', attr: ['3', 'W']}, 20 | {bits: 5, name: 'rs1', attr: ['5', 'base']}, 21 | {bits: 5, name: 'rs2', attr: ['5', 'src']}, 22 | {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, 23 | ]} 24 | .... 25 | -------------------------------------------------------------------------------- /src/images/wavedrom/sp-load-store.edn: -------------------------------------------------------------------------------- 1 | //## 12.5 Single-Precision Load and Store Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'LOAD-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest']}, 8 | {bits: 3, name: 'width', attr: ['3', 'H']}, 9 | {bits: 5, name: 'rs1', attr: ['5', 'base']}, 10 | {bits: 12, name: 'imm[11:0]', attr: ['12', 'offset[11:0]']}, 11 | ]} 12 | .... 13 | 14 | [wavedrom, ,svg] 15 | .... 16 | {reg: [ 17 | {bits: 7, name: 'opcode', attr: ['7', 'STORE-FP']}, 18 | {bits: 5, name: 'imm[4:0]', attr: ['5', 'offset[4:0]']}, 19 | {bits: 3, name: 'width', attr: ['3', 'H']}, 20 | {bits: 5, name: 'rs1', attr: ['5', 'base']}, 21 | {bits: 5, name: 'rs2', attr: ['5', 'src']}, 22 | {bits: 7, name: 'imm[11:5]', attr: ['7', 'offset[11:5]']}, 23 | ]} 24 | .... 25 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat-classify.edn: -------------------------------------------------------------------------------- 1 | //## 12.9 Single-Precision Floating-Point Classify Instruction 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','001']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCLASS']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat-cn-cmp.edn: -------------------------------------------------------------------------------- 1 | //sp float convert and compare 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP', 'OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest', 'dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM','RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src', 'src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','W[U]/L[U]D', 'W[U]/L[U]']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S','S']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCVT.int.fmt', 'FCVT.fmt.int']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat-comp.edn: -------------------------------------------------------------------------------- 1 | //## 12.8 Single-Precision Floating-Point Compare Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','EQ', 'LT', 'LE']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FCMP']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat-mv.edn: -------------------------------------------------------------------------------- 1 | //SP flating point move 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','000', '000']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src','src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','0','0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S','S']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FMV.X.W','FMV.W.X']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat-sign-inj.edn: -------------------------------------------------------------------------------- 1 | //sp float sign injection 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5', 'dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','J[N]/JX']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S']}, 12 | {bits: 5, name: 'funct5', attr: ['5','FSGNJ']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat-zfh.edn: -------------------------------------------------------------------------------- 1 | //## 12.6 Single-Precision Floating-Point Computational Instructions for ZFH Chapter 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'MIN/MAX', 'RM']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src1', 'src']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', 'src2', '0']}, 11 | {bits: 2, name: 'fmt', attr: ['2','H', 'H', 'H', 'H']}, 12 | {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FMIN-MAX', 'FSQRT']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat.edn: -------------------------------------------------------------------------------- 1 | //## 12.6 Single-Precision Floating-Point Computational Instructions 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7','OP-FP','OP-FP','OP-FP','OP-FP']}, 7 | {bits: 5, name: 'rd', attr: ['5','dest','dest','dest','dest']}, 8 | {bits: 3, name: 'rm', attr: ['3','RM', 'RM', 'RM','MIN/MAX']}, 9 | {bits: 5, name: 'rs1', attr: ['5','src1', 'src1', 'src', 'src1']}, 10 | {bits: 5, name: 'rs2', attr: ['5','src2', 'src2', '0', 'src2']}, 11 | {bits: 2, name: 'fmt', attr: ['2','S', 'S', 'S', 'S']}, 12 | {bits: 5, name: 'funct5', attr: ['5', 'FADD/FSUB', 'FMUL/FDIV', 'FSQRT','FMIN-MAX']}, 13 | ]} 14 | .... 15 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat2-zfh.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, 5 | {bits: 5, name: 'rd', attr: ['5','dest']}, 6 | {bits: 3, name: 'rm', attr: ['3','RM']}, 7 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 8 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 9 | {bits: 2, name: 'fmt', attr: ['2','H']}, 10 | {bits: 5, name: 'rs3', attr: ['5','src3']}, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/spfloat2.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7','F[N]MADD/F[N]MSUB']}, 5 | {bits: 5, name: 'rd', attr: ['5','dest']}, 6 | {bits: 3, name: 'rm', attr: ['3','RM']}, 7 | {bits: 5, name: 'rs1', attr: ['5','src1']}, 8 | {bits: 5, name: 'rs2', attr: ['5','src2']}, 9 | {bits: 2, name: 'fmt', attr: ['2','S']}, 10 | {bits: 5, name: 'rs3', attr: ['5','src3']}, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/transformedatomicinst.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7']}, 5 | {bits: 5, name: 'rd', attr: ['5']}, 6 | {bits: 3, name: 'funct3', attr: ['3']}, 7 | {bits: 5, name: 'Addr. Offset', attr: ['5']}, 8 | {bits: 5, name: 'rs2', attr: ['5']}, 9 | {bits: 1, name: 'rl', attr: ['1']}, 10 | {bits: 1, name: 'aq', attr: ['1']}, 11 | {bits: 5, name: 'funct5', attr: ['5']}, 12 | ], config: {bits: 32}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/transformedloadinst.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7']}, 5 | {bits: 5, name: 'rd', attr: ['5']}, 6 | {bits: 3, name: 'funct3', attr: ['3']}, 7 | {bits: 5, name: 'Addr. Offset', attr: ['5']}, 8 | {bits: 5, name: '0', attr: ['5']}, 9 | {bits: 7, name: '0', attr: ['7']}, 10 | ], config: {bits: 32}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/transformedstoreinst.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7']}, 5 | {bits: 5, name: '0', attr: ['5']}, 6 | {bits: 3, name: 'funct3', attr: ['3']}, 7 | {bits: 5, name: 'Addr. Offset', attr: ['5']}, 8 | {bits: 5, name: 'rs2', attr: ['5']}, 9 | {bits: 7, name: '0', attr: ['7']}, 10 | ], config: {bits: 32}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/transformedvmaccessinst.edn: -------------------------------------------------------------------------------- 1 | [wavedrom, ,svg] 2 | .... 3 | {reg: [ 4 | {bits: 7, name: 'opcode', attr: ['7']}, 5 | {bits: 5, name: 'rd', attr: ['5']}, 6 | {bits: 3, name: 'funct3', attr: ['3']}, 7 | {bits: 5, name: 'Addr. Offset', attr: ['5']}, 8 | {bits: 5, name: 'rs2', attr: ['5']}, 9 | {bits: 7, name: 'funct7', attr: ['7']}, 10 | ], config: {bits: 32}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/trap-return.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],}, 8 | {bits: 5, name: 'rd', attr: ['5','0'],}, 9 | {bits: 3, name: 'funct3', attr: ['3','PRIV'],}, 10 | {bits: 5, name: 'rs1', attr: ['5','0'],}, 11 | {bits: 12, name: 'funct12', attr: ['12','MRET/SRET',]}, 12 | ], config: {bits: 32}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/u-immediate.edn: -------------------------------------------------------------------------------- 1 | //#### U-immediate 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 12, name: '0'}, 7 | {bits: 8, name: 'inst[19:12]'}, 8 | {bits: 11, name: 'inst[30:20]'}, 9 | {bits: 1, name: '[31]'}, 10 | ], config:{fontsize: 12, label:{right: 'U-immediate'}}} 11 | .... 12 | -------------------------------------------------------------------------------- /src/images/wavedrom/vcfg-format.edn: -------------------------------------------------------------------------------- 1 | Formats for Vector Configuration Instructions under OP-V major opcode 2 | 3 | //// 4 | 31 30 25 24 20 19 15 14 12 11 7 6 0 5 | 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli 6 | 1 | 1| zimm[ 9:0] | uimm[4:0]| 1 1 1 | rd |1010111| vsetivli 7 | 1 | 000000 | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl 8 | 1 6 5 5 3 5 7 9 | //// 10 | 11 | [wavedrom,,svg] 12 | .... 13 | {reg: [ 14 | {bits: 7, name: 0x57, attr: 'vsetvli'}, 15 | {bits: 5, name: 'rd'}, 16 | {bits: 3, name: 7}, 17 | {bits: 5, name: 'rs1'}, 18 | {bits: 11, name: 'vtypei[10:0]'}, 19 | {bits: 1, name: '0'}, 20 | ]} 21 | .... 22 | 23 | [wavedrom,,svg] 24 | .... 25 | {reg: [ 26 | {bits: 7, name: 0x57, attr: 'vsetivli'}, 27 | {bits: 5, name: 'rd'}, 28 | {bits: 3, name: 7}, 29 | {bits: 5, name: 'uimm[4:0]'}, 30 | {bits: 10, name: 'vtypei[9:0]'}, 31 | {bits: 1, name: '1'}, 32 | {bits: 1, name: '1'}, 33 | ]} 34 | .... 35 | 36 | [wavedrom,,svg] 37 | .... 38 | {reg: [ 39 | {bits: 7, name: 0x57, attr: 'vsetvl'}, 40 | {bits: 5, name: 'rd'}, 41 | {bits: 3, name: 7}, 42 | {bits: 5, name: 'rs1'}, 43 | {bits: 5, name: 'rs2'}, 44 | {bits: 6, name: 0x00}, 45 | {bits: 1, name: 1}, 46 | ]} 47 | .... 48 | -------------------------------------------------------------------------------- /src/images/wavedrom/vtype-format.edn: -------------------------------------------------------------------------------- 1 | [wavedrom,,svg] 2 | .... 3 | {reg: [ 4 | {bits: 3, name: 'vlmul[2:0]'}, 5 | {bits: 3, name: 'vsew[2:0]'}, 6 | {bits: 1, name: 'vta'}, 7 | {bits: 1, name: 'vma'}, 8 | {bits: 23, name: 'reserved'}, 9 | {bits: 1, name: 'vill'}, 10 | ]} 11 | .... 12 | 13 | NOTE: This diagram shows the layout for RV32 systems, whereas in 14 | general `vill` should be at bit XLEN-1. 15 | 16 | .`vtype` register layout 17 | [cols=">2,4,10"] 18 | [%autowidth,float="center",align="center",options="header"] 19 | |=== 20 | | Bits | Name | Description 21 | 22 | | XLEN-1 | vill | Illegal value if set 23 | | XLEN-2:8 | 0 | Reserved if non-zero 24 | | 7 | vma | Vector mask agnostic 25 | | 6 | vta | Vector tail agnostic 26 | | 5:3 | vsew[2:0] | Selected element width (SEW) setting 27 | | 2:0 | vlmul[2:0] | Vector register group multiplier (LMUL) setting 28 | |=== 29 | -------------------------------------------------------------------------------- /src/images/wavedrom/wfi.edn: -------------------------------------------------------------------------------- 1 | // 2 | 3 | [wavedrom, ,svg] 4 | 5 | .... 6 | {reg: [ 7 | {bits: 7, name: 'opcode', attr: ['7','SYSTEM'],}, 8 | {bits: 5, name: 'rd', attr: ['5','0'],}, 9 | {bits: 3, name: 'funct3', attr: ['3','PRIV'],}, 10 | {bits: 5, name: 'rs1', attr: ['5','0'],}, 11 | {bits: 12, name: 'funct12', attr: ['12','WFI',]}, 12 | ], config: {bits: 32}} 13 | .... 14 | -------------------------------------------------------------------------------- /src/images/wavedrom/zifencei-ff.edn: -------------------------------------------------------------------------------- 1 | //# 3 "Zifencei" Instruction-Fetch Fence, Version 2.0 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: ['7', 'MISC-MEM']}, 7 | {bits: 5, name: 'rd', attr: ['5', '0']}, 8 | {bits: 3, name: 'funct3', attr: ['3', 'FENCE.I']}, 9 | {bits: 5, name: 'rs1', attr: ['5', '0']}, 10 | {bits: 12, name: 'funct12', attr: ['12', '0']}, 11 | ]} 12 | .... 13 | -------------------------------------------------------------------------------- /src/images/wavedrom/zihintpause-hint.edn: -------------------------------------------------------------------------------- 1 | //# 4 "Zihintpause" Pause Hint, Version 1.0 2 | 3 | [wavedrom, ,svg] 4 | .... 5 | {reg: [ 6 | {bits: 7, name: 'opcode', attr: 'MISC-MEM'}, 7 | {bits: 5, name: 'rd', attr: 0}, 8 | {bits: 3, name: 'funct3', attr: 'PAUSE'}, 9 | {bits: 5, name: 'rs1', attr: 0}, 10 | {bits: 1, name: 'SW', attr: 0}, 11 | {bits: 1, name: 'SR', attr: 0}, 12 | {bits: 1, name: 'SO', attr: 0}, 13 | {bits: 1, name: 'SI', attr: 0}, 14 | {bits: 1, name: 'PW', attr: 1}, 15 | {bits: 1, name: 'PR', attr: 0}, 16 | {bits: 1, name: 'PO', attr: 0}, 17 | {bits: 1, name: 'PI', attr: 0}, 18 | {bits: 4, name: 'fm', attr: 0}, 19 | ]} 20 | .... 21 | -------------------------------------------------------------------------------- /src/index.adoc: -------------------------------------------------------------------------------- 1 | [index] 2 | == Index 3 | -------------------------------------------------------------------------------- /src/priv-history.adoc: -------------------------------------------------------------------------------- 1 | == History 2 | 3 | === Research Funding at UC Berkeley 4 | 5 | Development of the RISC-V architecture and implementations has been 6 | partially funded by the following sponsors. 7 | 8 | * *Par Lab:* Research supported by Microsoft (Award #024263) and Intel 9 | (Award #024894) funding and by matching funding by U.C. Discovery (Award 10 | #DIG07-10227). Additional support came from Par Lab affiliates Nokia, 11 | NVIDIA, Oracle, and Samsung. 12 | * *Project Isis:* DoE Award DE-SC0003624. 13 | * *ASPIRE Lab*: DARPA PERFECT program, Award HR0011-12-2-0016. DARPA 14 | POEM program Award HR0011-11-C-0100. The Center for Future Architectures 15 | Research (C-FAR), a STARnet center funded by the Semiconductor Research 16 | Corporation. Additional support from ASPIRE industrial sponsor, Intel, 17 | and ASPIRE affiliates, Google, Huawei, Nokia, NVIDIA, Oracle, and 18 | Samsung. 19 | 20 | The content of this paper does not necessarily reflect the position or 21 | the policy of the US government and no official endorsement should be 22 | inferred. 23 | -------------------------------------------------------------------------------- /src/priv-insns.adoc: -------------------------------------------------------------------------------- 1 | 2 | == RISC-V Privileged Instruction Set Listings 3 | 4 | This chapter presents instruction-set listings for all instructions 5 | defined in the RISC-V Privileged Architecture. 6 | 7 | The instruction-set listings for unprivileged instructions, including 8 | the ECALL and EBREAK instructions, are provided in Volume I of this 9 | manual. 10 | 11 | .RISC-V Privileged Instructions 12 | include::images/bytefield/priv-instr-set.edn[] 13 | -------------------------------------------------------------------------------- /src/rv32e.adoc: -------------------------------------------------------------------------------- 1 | [[rv32e]] 2 | == RV32E and RV64E Base Integer Instruction Sets, Version 2.0 3 | This chapter describes a proposal for the RV32E and RV64E base integer 4 | instruction sets, designed for microcontrollers in embedded systems. 5 | RV32E and RV64E are reduced versions of RV32I and RV64I, respectively: 6 | the only change is to reduce the number of integer registers to 16. This 7 | chapter only outlines the differences between RV32E/RV64E and 8 | RV32I/RV64I, and so should be read after <> and <>. 9 | (((RV32E, design))) 10 | [NOTE] 11 | ==== 12 | RV32E was designed to provide an even smaller base core for embedded 13 | microcontrollers. There is also interest in RV64E for microcontrollers 14 | within large SoC designs, and to reduce context state for highly 15 | threaded 64-bit processors. 16 | 17 | Unless otherwise stated, standard extensions compatible with RV32I and 18 | RV64I are also compatible with RV32E and RV64E, respectively. 19 | ==== 20 | 21 | === RV32E and RV64E Programmers’ Model 22 | RV32E and RV64E reduce the integer register count to 16 general-purpose 23 | registers, (`x0-x15`), where `x0` is a dedicated zero register. 24 | 25 | [NOTE] 26 | ==== 27 | We have found that in the small RV32I core implementations, the upper 16 28 | registers consume around one quarter of the total area of the core 29 | excluding memories, thus their removal saves around 25% core area with a 30 | corresponding core power reduction. 31 | ==== 32 | 33 | === RV32E and RV64E Instruction Set Encoding 34 | (((RV32E, difference from RV32I))) 35 | RV32E and RV64E use the same instruction-set encoding as RV32I and RV64I 36 | respectively, except that only registers `x0-x15` are provided. All 37 | encodings specifying the other registers `x16-x31` are reserved. 38 | 39 | [NOTE] 40 | ==== 41 | The previous draft of this chapter made all encodings using the 42 | `x16-x31` registers available as custom. This version takes a more 43 | conservative approach, making these reserved so that they can be 44 | allocated between custom space or new standard encodings at a later 45 | date. 46 | ==== 47 | -------------------------------------------------------------------------------- /src/smdbltrp.adoc: -------------------------------------------------------------------------------- 1 | [[smdbltrp]] 2 | == "Smdbltrp" Double Trap Extension, Version 1.0 3 | 4 | The Smdbltrp extension addresses a double trap (See <>) in 5 | M-mode. When the Smrnmi extension (<>) is implemented, it enables 6 | invocation of the RNMI handler on a double trap in M-mode to handle the 7 | critical error. If the Smrnmi extension is not implemented or if a double trap 8 | occurs during the RNMI handler's execution, this extension helps transition the 9 | hart to a critical error state and enables signaling the critical error to the 10 | platform. 11 | 12 | To improve error diagnosis and resolution, this extension supports debugging 13 | harts in a critical error state. The extension introduces a mechanism to enter 14 | Debug Mode instead of asserting a critical-error signal to the platform when the 15 | hart is in a critical error state. See cite:[DEBUG_SPEC] for details. 16 | 17 | See <> for the operational details. 18 | -------------------------------------------------------------------------------- /src/ssdbltrp.adoc: -------------------------------------------------------------------------------- 1 | [[ssdbltrp]] 2 | == "Ssdbltrp" Double Trap Extension, Version 1.0 3 | 4 | The Ssdbltrp extension addresses a double trap (See <>) 5 | privilege modes lower than M. It enables HS-mode to invoke a critical error 6 | handler in a virtual machine on a double trap in VS-mode. It also allows M-mode 7 | to invoke a critical error handler in the OS/Hypervisor on a double trap in 8 | S/HS-mode. 9 | 10 | The Ssdbltrp extension adds the `menvcfg`.DTE (See <>) and the 11 | `sstatus`.SDT fields (See <>). If the hypervisor extension is 12 | additionally implemented, then the extension adds the `henvcfg`.DTE (See 13 | <>) and the `vsstatus`.SDT fields (See <>). 14 | 15 | See <> for the operational details. 16 | -------------------------------------------------------------------------------- /src/ztso-st-ext.adoc: -------------------------------------------------------------------------------- 1 | [[ztso]] 2 | == "Ztso" Extension for Total Store Ordering, Version 1.0 3 | 4 | This chapter defines the "Ztso" extension for the RISC-V Total Store 5 | Ordering (RVTSO) memory consistency model. RVTSO is defined as a delta 6 | from RVWMO, which is defined in <>. 7 | [NOTE] 8 | ==== 9 | _The Ztso extension is meant to facilitate the porting of code originally 10 | written for the x86 or SPARC architectures, both of which use TSO by 11 | default. It also supports implementations which inherently provide RVTSO 12 | behavior and want to expose that fact to software._ 13 | ==== 14 | RVTSO makes the following adjustments to RVWMO: 15 | 16 | * All load operations behave as if they have an acquire-RCpc annotation 17 | * All store operations behave as if they have a release-RCpc annotation. 18 | * All AMOs behave as if they have both acquire-RCsc and release-RCsc 19 | annotations. 20 | 21 | [NOTE] 22 | ==== 23 | _These rules render all PPO rules except 24 | <> redundant. They also make 25 | redundant any non-I/O fences that do not have both PW and SR set. 26 | Finally, they also imply that no memory operation will be reordered past 27 | an AMO in either direction._ 28 | 29 | _In the context of RVTSO, as is the case for RVWMO, the storage ordering 30 | annotations are concisely and completely defined by PPO rules 31 | <>. In both of these 32 | memory models, it is the <> that allows a hart to forward a value from its 33 | store buffer to a subsequent (in program order) load—that is to say that 34 | stores can be forwarded locally before they are visible to other harts._ 35 | ==== 36 | 37 | Additionally, if the Ztso extension is implemented, then vector memory 38 | instructions in the V extension and Zve family of extensions follow RVTSO at 39 | the instruction level. 40 | The Ztso extension does not strengthen the ordering of intra-instruction 41 | element accesses. 42 | 43 | In spite of the fact that Ztso adds no new instructions to the ISA, code 44 | written assuming RVTSO will not run correctly on implementations not 45 | supporting Ztso. Binaries compiled to run only under Ztso should 46 | indicate as such via a flag in the binary, so that platforms which do 47 | not implement Ztso can simply refuse to run them. 48 | --------------------------------------------------------------------------------