├── .github └── workflows │ ├── build.yml │ └── pre-commit.yml ├── .gitignore ├── .gitmodules ├── .pre-commit-config.yaml ├── CONTRIBUTING.md ├── LICENSE ├── MAINTAINERS.md ├── Makefile ├── README.adoc ├── build_rvm23_profile ├── dependencies ├── Gemfile ├── apt_packages.txt └── package.json └── src ├── RVA-profile-overview.adoc ├── contributors.adoc ├── old-m-profiles.adoc ├── profiles.adoc ├── rv-profile-defined-extensions.adoc ├── rva-profile-overview-body.adoc ├── rva23-profile.adoc ├── rvb23-profile.adoc └── rvm23-profile.adoc /.github/workflows/build.yml: -------------------------------------------------------------------------------- 1 | name: Create Specification Document 2 | 3 | # The workflow is triggered by pull request, push to main, and manual dispatch. 4 | on: 5 | workflow_dispatch: 6 | inputs: 7 | version: 8 | description: "Release version, e.g. X.Y.Z:" 9 | required: true 10 | type: string 11 | revision_mark: 12 | description: "Set revision mark as Draft, Release or Stable:" 13 | required: true 14 | type: string 15 | default: "Draft" 16 | prerelease: 17 | description: "Tag as a pre-release?" 18 | required: false 19 | type: boolean 20 | default: true 21 | draft: 22 | description: "Create release as a draft?" 23 | required: false 24 | type: boolean 25 | default: false 26 | pull_request: 27 | push: 28 | branches: 29 | - main 30 | 31 | jobs: 32 | build: 33 | runs-on: ubuntu-latest 34 | 35 | steps: 36 | # Step 1: Checkout the repository 37 | - name: Checkout repository 38 | uses: actions/checkout@v4 39 | with: 40 | submodules: "recursive" 41 | 42 | # Step 2: Pull the latest RISC-V Docs container image 43 | - name: Pull Container 44 | run: docker pull riscvintl/riscv-docs-base-container-image:latest 45 | 46 | # Step 3: Build Files 47 | - name: Build Files 48 | run: make 49 | env: 50 | VERSION: v${{ github.event.inputs.version }} 51 | REVMARK: ${{ github.event.inputs.revision_mark }} 52 | 53 | # Step 4: Upload the built PDF files as a single artifact 54 | - name: Upload Build Artifacts 55 | uses: actions/upload-artifact@v4 56 | with: 57 | name: Build Artifacts 58 | path: | 59 | ${{ github.workspace }}/build/*.pdf 60 | ${{ github.workspace }}/build/*.html 61 | retention-days: 30 62 | 63 | # Create Release 64 | - name: Create Release 65 | uses: softprops/action-gh-release@v1 66 | with: 67 | files: | 68 | ${{ github.workspace }}/build/*.pdf 69 | ${{ github.workspace }}/build/*.html 70 | tag_name: v${{ github.event.inputs.version }} 71 | name: Release ${{ github.event.inputs.version }} 72 | draft: ${{ github.event.inputs.draft }} 73 | prerelease: ${{ github.event.inputs.prerelease }} 74 | env: 75 | GITHUB_TOKEN: ${{ secrets.GHTOKEN }} 76 | if: github.event_name == 'workflow_dispatch' 77 | # This condition ensures this step only runs for workflow_dispatch events. 78 | -------------------------------------------------------------------------------- /.github/workflows/pre-commit.yml: -------------------------------------------------------------------------------- 1 | --- 2 | name: pre-commit 3 | 4 | on: 5 | pull_request: 6 | push: 7 | branches: [main] 8 | 9 | jobs: 10 | pre-commit: 11 | runs-on: ubuntu-latest 12 | steps: 13 | - uses: actions/checkout@v4 14 | - uses: actions/setup-python@v5 15 | - uses: pre-commit/action@v3.0.0 16 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | .*.swp 3 | /build/* 4 | /images/* 5 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "docs-resources"] 2 | path = docs-resources 3 | url = https://github.com/riscv/docs-resources.git 4 | -------------------------------------------------------------------------------- /.pre-commit-config.yaml: -------------------------------------------------------------------------------- 1 | --- 2 | repos: 3 | - repo: https://github.com/pre-commit/pre-commit-hooks 4 | rev: v4.6.0 5 | hooks: 6 | - id: check-json 7 | - id: check-symlinks 8 | - id: check-yaml 9 | - id: end-of-file-fixer 10 | - id: trailing-whitespace 11 | args: [--markdown-linebreak-ext=md] 12 | 13 | - repo: local 14 | hooks: 15 | - id: forbidden-file-extensions 16 | name: forbidden-file-extensions 17 | entry: disallow these file extensions 18 | language: fail 19 | # Disallow other asciidoc extensions except .adoc 20 | files: .*\.(asciidoc|asc)$ 21 | 22 | - repo: https://github.com/rbubley/mirrors-prettier 23 | rev: v3.2.5 24 | hooks: 25 | - id: prettier 26 | -------------------------------------------------------------------------------- /CONTRIBUTING.md: -------------------------------------------------------------------------------- 1 | # Contribution Guidelines 2 | 3 | As an open-source project, we appreciate and encourage community members to submit patches directly to the project. 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For 392 | the avoidance of doubt, this paragraph does not form part of the 393 | public licenses. 394 | 395 | Creative Commons may be contacted at creativecommons.org. 396 | -------------------------------------------------------------------------------- /MAINTAINERS.md: -------------------------------------------------------------------------------- 1 | # Maintainers 2 | 3 | This project is maintained by the following people: 4 | 5 | - FIXME 6 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # Makefile for RISC-V Doc Template 2 | # 3 | # This work is licensed under the Creative Commons Attribution-ShareAlike 4.0 4 | # International License. To view a copy of this license, visit 5 | # http://creativecommons.org/licenses/by-sa/4.0/ or send a letter to 6 | # Creative Commons, PO Box 1866, Mountain View, CA 94042, USA. 7 | # 8 | # SPDX-License-Identifier: CC-BY-SA-4.0 9 | # 10 | # Description: 11 | # 12 | # This Makefile is designed to automate the process of building and packaging 13 | # the Doc Template for RISC-V Extensions. 14 | 15 | DOCS := \ 16 | rva23-profile.adoc \ 17 | rvb23-profile.adoc \ 18 | 19 | DATE ?= $(shell date +%Y-%m-%d) 20 | VERSION ?= 1.0 21 | REVMARK ?= This document is in Ratified state. 22 | DOCKER_IMG := riscvintl/riscv-docs-base-container-image:latest 23 | ifneq ($(SKIP_DOCKER),true) 24 | DOCKER_CMD := docker run --rm -v ${PWD}:/build -w /build \ 25 | ${DOCKER_IMG} \ 26 | /bin/sh -c 27 | DOCKER_QUOTE := " 28 | endif 29 | 30 | SRC_DIR := src 31 | BUILD_DIR := build 32 | 33 | DOCS_PDF := $(DOCS:%.adoc=%.pdf) 34 | DOCS_HTML := $(DOCS:%.adoc=%.html) 35 | 36 | XTRA_ADOC_OPTS := 37 | ASCIIDOCTOR_PDF := asciidoctor-pdf 38 | ASCIIDOCTOR_HTML := asciidoctor 39 | OPTIONS := --trace \ 40 | -a compress \ 41 | -a mathematical-format=svg \ 42 | -a revnumber=\"${VERSION}\" \ 43 | -a revremark=\"${REVMARK}\" \ 44 | -a revdate=${DATE} \ 45 | -a pdf-fontsdir=docs-resources/fonts \ 46 | -a pdf-theme=docs-resources/themes/riscv-pdf.yml \ 47 | $(XTRA_ADOC_OPTS) \ 48 | -D build \ 49 | --failure-level=ERROR 50 | REQUIRES := --require=asciidoctor-diagram \ 51 | --require=asciidoctor-lists \ 52 | --require=asciidoctor-mathematical 53 | 54 | .PHONY: all build clean build-container build-no-container build-docs 55 | 56 | all: build 57 | 58 | build-docs: $(DOCS_PDF) $(DOCS_HTML) 59 | 60 | vpath %.adoc $(SRC_DIR) 61 | 62 | %.pdf: %.adoc 63 | $(DOCKER_CMD) $(DOCKER_QUOTE) $(ASCIIDOCTOR_PDF) $(OPTIONS) $(REQUIRES) $< $(DOCKER_QUOTE) 64 | 65 | %.html: %.adoc 66 | $(DOCKER_CMD) $(DOCKER_QUOTE) $(ASCIIDOCTOR_HTML) $(OPTIONS) $(REQUIRES) $< $(DOCKER_QUOTE) 67 | 68 | build: 69 | @echo "Checking if Docker is available..." 70 | @if command -v docker >/dev/null 2>&1 ; then \ 71 | echo "Docker is available, building inside Docker container..."; \ 72 | $(MAKE) build-container; \ 73 | else \ 74 | echo "Docker is not available, building without Docker..."; \ 75 | $(MAKE) build-no-container; \ 76 | fi 77 | 78 | build-container: 79 | @echo "Starting build inside Docker container..." 80 | $(MAKE) build-docs 81 | @echo "Build completed successfully inside Docker container." 82 | 83 | build-no-container: 84 | @echo "Starting build..." 85 | $(MAKE) SKIP_DOCKER=true build-docs 86 | @echo "Build completed successfully." 87 | 88 | # Update docker image to latest 89 | docker-pull-latest: 90 | docker pull ${DOCKER_IMG} 91 | 92 | clean: 93 | @echo "Cleaning up generated files..." 94 | rm -rf $(BUILD_DIR) 95 | @echo "Cleanup completed." 96 | -------------------------------------------------------------------------------- /README.adoc: -------------------------------------------------------------------------------- 1 | = RISC-V Profiles 2 | 3 | == License 4 | 5 | This work is licensed under a Creative Commons Attribution 4.0 International License (CC-BY-4.0). For details, see the link:LICENSE[LICENSE] file. 6 | 7 | == Maintainers 8 | 9 | The list of maintainers of this specification is maintained in the link:MAINTAINERS.md[MAINTAINERS] file. 10 | 11 | == Contributors 12 | 13 | The list of contributors to this specification is maintained in the link:src/contributors.adoc[contributors] file. 14 | 15 | For guidelines on how to contribute, refer to the link:CONTRIBUTING.md[CONTRIBUTING] file. 16 | 17 | == Governance 18 | 19 | The governance for this project is defined in the link:GOVERNANCE.md[GOVERNANCE] file. 20 | 21 | Community information, including meeting (if held) and mailing lists are detailed in this file. 22 | 23 | == Building the Document 24 | 25 | === Directory Structure 26 | 27 | The following directories are used to organize the contents of this repo: 28 | 29 | * `dependencies/`: software dependencies needed to build the specification 30 | * `docs-resources/`: resources for all specifications sourced from link:.gitmodules[git submodule] 31 | * `src/`: source files for the specification 32 | * `build/`: default directory where the build artifacts are generated 33 | 34 | === Prerequisites 35 | 36 | To build the document, you'll need the following tools installed on your system: 37 | 38 | * Make 39 | * asciiDoctor-pdf, asciidoctor-bibtex, asciidoctor-diagram, and asciidoctor-mathematical 40 | * Docker 41 | 42 | === Cloning the Repository 43 | 44 | ```shell 45 | git clone --recurse-submodules https://github.com/riscv/riscv-profiles.git 46 | ``` 47 | 48 | All in one single line: 49 | 50 | ```shell 51 | git clone --recurse-submodules https://github.com/riscv/riscv-profiles.git && cd riscv-profiles && git submodule update --init --recursive 52 | 53 | ``` 54 | 55 | === Building the Documentation 56 | 57 | To start the build process, run: 58 | 59 | ```shell 60 | cd ./riscv-profiles && make build 61 | ``` 62 | 63 | The link:Makefile[] script will check the availability of Docker on your system: 64 | 65 | * If Docker is available, the documentation will be built inside a Docker container using the image riscvintl/riscv-docs-base-container-image:latest. This ensures a consistent build environment across different systems. 66 | * If Docker is not available, the documentation will be built directly on your system using the installed tools. 67 | 68 | The documentation is generated from the AsciiDoctor source files in your project. The primary source file is specified by the `HEADER_SOURCE` variable in the Makefile. 69 | 70 | The build process utilizes several options, including theming and font settings, and generates a PDF document as output. 71 | 72 | === Cleaning up 73 | 74 | To clean up the generated files, run: 75 | 76 | ```shell 77 | make clean 78 | ``` 79 | 80 | == Enabling pre-commit checks locally 81 | 82 | The repository has some basic commit checks set up with https://pre-commit.com/[pre-commit] that will be enforced by the GitHub CI. 83 | To ensure these checks are also run in the local repository while making changes the following can be done: 84 | 85 | .Installing pre-commit tool 86 | [source,shell] 87 | ---- 88 | # Do once on your system 89 | pip3 install pre-commit 90 | ---- 91 | 92 | .Installing pre-commit git hook in repo 93 | [source,shell] 94 | ---- 95 | # Do once in local repo 96 | pre-commit install 97 | ---- 98 | 99 | Rather than doing the above `pre-commit install` in every repo that uses it, you can do it https://pre-commit.com/#automatically-enabling-pre-commit-on-repositories[once on your system.] 100 | 101 | When enabling additional checks https://pre-commit.com/#plugins[by editing .pre-commit-config.yaml], it is recommended running the newly added check on all files in the repository. This can be done with the following command: 102 | 103 | .Running all pre-commit hooks on all files 104 | [source,shell] 105 | ---- 106 | pre-commit run --all-files 107 | ---- 108 | -------------------------------------------------------------------------------- /build_rvm23_profile: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | # The Makefile by default will not build the RVM23 profile, which is still in draft status. 3 | # This script will set up several useful variables and then invoke the 4 | # Makefile to build the .pdf and .html for RVM23. 5 | source=rvm23-profile.adoc 6 | doc_version=$(grep :revnumber: src/${source} | awk '{print $2}') 7 | sha_version=$(git rev-parse --short HEAD) 8 | make VERSION="${doc_version} (SHA ${sha_version})" REVMARK="Draft" DOCS=${source} 9 | -------------------------------------------------------------------------------- /dependencies/Gemfile: -------------------------------------------------------------------------------- 1 | source 'https://rubygems.org' 2 | gem 'asciidoctor' 3 | gem 'asciidoctor-bibtex' 4 | gem 'asciidoctor-diagram' 5 | gem 'asciidoctor-mathematical' 6 | gem 'asciidoctor-pdf' 7 | gem 'citeproc-ruby' 8 | gem 'coderay' 9 | gem 'csl-styles' 10 | gem 'json' 11 | gem 'pygments.rb' 12 | gem 'rghost' 13 | gem 'rouge' 14 | gem 'ruby_dev' 15 | -------------------------------------------------------------------------------- /dependencies/apt_packages.txt: -------------------------------------------------------------------------------- 1 | bison 2 | build-essential 3 | cmake 4 | curl 5 | flex 6 | fonts-lyx 7 | git 8 | graphviz 9 | # For wavedrom 10 | default-jre 11 | libcairo2-dev 12 | libffi-dev 13 | libgdk-pixbuf2.0-dev 14 | libpango1.0-dev 15 | libwebp-dev 16 | libxml2-dev 17 | make 18 | pkg-config 19 | ruby 20 | ruby-dev 21 | -------------------------------------------------------------------------------- /dependencies/package.json: -------------------------------------------------------------------------------- 1 | { 2 | "name": "local", 3 | "version": "0.0.1", 4 | "dependencies": { 5 | "wavedrom-cli": "^2.6.8" 6 | } 7 | } 8 | -------------------------------------------------------------------------------- /src/RVA-profile-overview.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-doc-template]] 2 | :description: Short, text description of spect… 3 | :company: RISC-V 4 | :revdate: September 28, 2023 5 | :revnumber: 0.1-draft 6 | :revremark: This document is in Development stage. Everything could change before ratification. 7 | :url-riscv: http://riscv.org 8 | :doctype: book 9 | :preface-title: Preamble 10 | :colophon: 11 | :appendix-caption: Appendix 12 | :imagesdir: images 13 | :title-logo-image: image:riscv-images/risc-v_logo.png[pdfwidth=3.25in,align=center] 14 | // Settings: 15 | :experimental: 16 | :reproducible: 17 | :WaveDromEditorApp: wavedrom-cli 18 | :imagesoutdir: images 19 | :icons: font 20 | :lang: en 21 | :listing-caption: Listing 22 | :sectnums: 23 | :sectnumlevels: 5 24 | :toclevels: 5 25 | :toc: left 26 | :source-highlighter: pygments 27 | ifdef::backend-pdf[] 28 | :source-highlighter: coderay 29 | endif::[] 30 | :data-uri: 31 | :hide-uri-scheme: 32 | :stem: latexmath 33 | :footnote: 34 | :xrefstyle: short 35 | :numbered: 36 | :stem: latexmath 37 | :le: ≤ 38 | :ge: ≥ 39 | :ne: ≠ 40 | :approx: ≈ 41 | :inf: ∞ 42 | 43 | :sectnums!: 44 | 45 | = RISC-V RVA Profiles Overview 46 | 47 | //: This is the Preamble 48 | 49 | [WARNING] 50 | .This document is in the development state. 51 | ==== 52 | Do not use for implementations. Assume everything can change. 53 | ==== 54 | 55 | == Document History 56 | 57 | *This document is intended to address only RVA profiles and not other 58 | types of profile.* 59 | 60 | This document provides a general introduction and rationale for RISC-V 61 | RVA profiles' structure and terminology. It is based on the original 62 | introduction to the first ratified RVA profiles, and further 63 | discussion in the profiles' TG specifically regarding the RVA series 64 | of profiles. 65 | 66 | :sectnums: 67 | 68 | include::rva-profile-overview-body.adoc[] 69 | -------------------------------------------------------------------------------- /src/contributors.adoc: -------------------------------------------------------------------------------- 1 | == Contributors 2 | 3 | This RISC-V specification has been contributed to directly or indirectly by: 4 | 5 | [%hardbreaks] 6 | * FIXME: Author1 7 | * FIXME: Author2 8 | -------------------------------------------------------------------------------- /src/old-m-profiles.adoc: -------------------------------------------------------------------------------- 1 | //// 2 | This file contains text on M-mode profiles that was deleted from the proposal. 3 | 4 | === RVA20M64 Profile 5 | 6 | The RVA20M64 profile is defined to help provide compatibilty for 7 | application-processor platforms that specify an M-mode execution 8 | environment for portable software. 9 | 10 | NOTE: Most OS platforms will have no code specified to run in M-mode, 11 | instead accessing lower-level platform services via abstract 12 | environment calls from supervisor mode. 13 | 14 | NOTE: M-mode will often inherently include implementation-specific 15 | features in addition to the profile requirements. 16 | 17 | ==== RVA20M64 Mandatory Extensions 18 | 19 | - All RVA20S64 mandatory extensions, _except_ F, D, and misaligned loads 20 | and stores. 21 | - Sm1p11 22 | - mvendorid, marchid, and mimpid registers must be nonzero. 23 | - mstatus.TVM, mstatus.TW, and mstatus.TSR must be writable. 24 | - mtvec.MODE must be capable of holding the value 0 (Direct). 25 | When mtvec.MODE=Direct, 26 | mtvec.BASE must be capable of holding any valid four-byte-aligned address. 27 | - medeleg bits 3, 8, 12, 13, and 15 must be writable. 28 | - mideleg bits 1, 5, and 9 must be writable. mideleg bits 3, 7, and 11 29 | must be read-only zero. 30 | - For any mhpmcounter that is writable, the corresponding bit 31 | in mcounteren must be writable. 32 | - mtval must be written with the faulting virtual address for load, store, and 33 | instruction page-fault, access-fault, and misaligned exceptions, and for 34 | breakpoint exceptions other than those caused by execution of the EBREAK or 35 | C.EBREAK instructions. 36 | For illegal-instruction exceptions, mtval must be written with the faulting 37 | instruction. 38 | - PMP entries 0-3 must be implemented and must support modes OFF, NAPOT, 39 | and TOR, with a granularity of at most 4 KiB. 40 | 41 | ==== RVA20M64 Supported Optional Extensions 42 | 43 | - All RVA20S64 supported optional extensions 44 | - F 45 | - D 46 | - Misaligned loads and stores 47 | 48 | NOTE: There are other options and parameters in the privileged 49 | architecture that should be detailed here. 50 | 51 | ==== RVA20M64 Unsupported Optional Extensions 52 | 53 | - All RVA20S64 unsupported optional extensions 54 | 55 | ==== RVA20M64 Incompatible Extensions 56 | 57 | - All RVA20S64 incompatible extensions 58 | 59 | //// 60 | 61 | //// 62 | IGNORE this text 63 | 64 | === RVA22M64 Profile 65 | 66 | ==== RVA22M64 Mandatory Extensions 67 | 68 | - All RVA22S64 mandatory extensions, _except_ F, D, and misaligned loads 69 | and stores. 70 | - Sm1p12 71 | - mvendorid, marchid, and mimpid registers must be nonzero. 72 | - mstatus.TVM, mstatus.TW, and mstatus.TSR must be writable. 73 | - mstatus.MBE, mstatus.SBE, and mstatus.UBE must not be read-only 1. 74 | - mtvec.MODE must be capable of holding the value 0 (Direct). 75 | When mtvec.MODE=Direct, 76 | mtvec.BASE must be capable of holding any valid four-byte-aligned address. 77 | - medeleg bits 3, 8, 12, 13, and 15 must be writable. 78 | - mideleg bits 1, 5, and 9 must be writable. mideleg bits 3, 7, and 11 79 | must be read-only zero. 80 | - For any mhpmcounter that is writable, the corresponding bits 81 | in mcounteren and mcountinhibit must be writable. 82 | - mtval must be written with the faulting virtual address for load, store, and 83 | instruction page-fault, access-fault, and misaligned exceptions, and for 84 | breakpoint exceptions other than those caused by execution of the EBREAK or 85 | C.EBREAK instructions. 86 | For illegal-instruction exceptions, mtval must be written with the faulting 87 | instruction. 88 | - PMP entries 0-3 must be implemented and must support modes OFF, NAPOT, 89 | and TOR, with a granularity of at most 4 KiB. 90 | 91 | If the hypervisor extension is implemented, the following are also mandatory: 92 | - medeleg bits 10, 20, 21, 22, and 23 must additionally be writable. 93 | - mtval2 must be written with the faulting guest physical address in all 94 | circumstances permitted by the ISA. 95 | 96 | ==== RVA22M64 Supported Optional Extensions 97 | 98 | - All RVA22S64 supported optional extensions 99 | - F 100 | - D 101 | - Misaligned loads and stores 102 | 103 | NOTE: Consider making Zicbom supported-optional here to facilitate 104 | trap & emulate, for systems that use some out-of-band mechanism? 105 | 106 | NOTE: There are options and parameters in the privileged architecture 107 | that should be detailed here. 108 | 109 | ==== RVA22M64 Unsupported Optional Extensions 110 | 111 | - All RVA22S64 unsupported optional extensions 112 | 113 | ==== RVA22M64 Incompatible Extensions 114 | 115 | - All RVA22S64 incompatible extensions 116 | //// 117 | -------------------------------------------------------------------------------- /src/profiles.adoc: -------------------------------------------------------------------------------- 1 | = RISC-V Profiles 2 | :description: Short, text description of spect… 3 | :company: RISC-V.org 4 | :revdate: April 2, 2023 5 | :revnumber: 1.1 6 | :revremark: This document is in Ratified state. 7 | :url-riscv: http://riscv.org 8 | :doctype: book 9 | :preface-title: Preamble 10 | :colophon: 11 | :appendix-caption: Appendix 12 | :imagesdir: ../docs-resources/images 13 | :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center] 14 | // Settings: 15 | :experimental: 16 | :reproducible: 17 | :WaveDromEditorApp: wavedrom-cli 18 | :imagesoutdir: images 19 | :icons: font 20 | :lang: en 21 | :listing-caption: Listing 22 | :sectnums: 23 | :sectnumlevels: 5 24 | :toclevels: 5 25 | :toc: left 26 | :source-highlighter: pygments 27 | ifdef::backend-pdf[] 28 | :source-highlighter: coderay 29 | endif::[] 30 | :data-uri: 31 | :hide-uri-scheme: 32 | :stem: latexmath 33 | :footnote: 34 | :xrefstyle: short 35 | :numbered: 36 | :le: ≤ 37 | :ge: ≥ 38 | :ne: ≠ 39 | :approx: ≈ 40 | :inf: ∞ 41 | 42 | [WARNING] 43 | .This document is in the link:http://riscv.org/spec-state[Ratified state] 44 | ==== 45 | No changes are allowed. Any desired or needed changes can be the subject of a follow-on new extension. Ratified extensions are never revised 46 | ==== 47 | 48 | [preface] 49 | == Changes made since ratification 50 | 51 | - Clarified that Zihpm was optional in RVA20U64 and became mandatory in RVA22U64 52 | 53 | [preface] 54 | == Changes since Public Review version 0.8 55 | 56 | - Clarified that profile name can be used as ISA base string 57 | - Renamed Ssptead to Svade 58 | - Fixed Ssu64xl to make supporting UXL=64 mandatory 59 | - Added section listing new extension names in profiles document 60 | - Added new extension name Sscounterenw 61 | - Removed outdated text on Zicntr/Zihpm ratification plan 62 | 63 | == Introduction 64 | 65 | RISC-V was designed to provide a highly modular and extensible 66 | instruction set, and includes a large and growing set of standard 67 | extensions. In addition, users may add their own custom 68 | extensions. This flexibility can be used to highly optimize a 69 | specialized design by including only the exact set of ISA features 70 | required for an application, but the same flexibility also leads to a 71 | combinatorial explosion in possible ISA choices. Profiles specify a 72 | much smaller common set of ISA choices that capture the most value for 73 | most users, and which thereby enable the software community to focus 74 | resources on building a rich software ecosystem with application and 75 | operating system portability across different implementations. 76 | 77 | NOTE: Another pragmatic concern is the long and unwieldy ISA strings 78 | required to encode common sets of extensions, which will continue to 79 | grow as new extensions are defined. 80 | 81 | Each profile is built on a standard base ISA plus a set of mandatory 82 | ISA extensions, and provides a small set of standard ISA options to 83 | extend the mandatory components. Profiles provide a convenient 84 | shorthand for describing the ISA portions of hardware and software 85 | platforms, and also guide the development of common software 86 | toolchains shared by different platforms that use the same profile. 87 | The intent is that the software ecosystem focus on supporting the 88 | profiles' mandatory base and standard options, instead of attempting 89 | to support every possible combination of individual extensions. 90 | Similarly, hardware vendors should aim to structure their offerings 91 | around standard profiles to increase the likelihood their designs will 92 | have mainstream software support. 93 | 94 | NOTE: Profiles are not intended to prohibit the use of combinations of 95 | individual ISA extensions or the addition of custom extensions, which 96 | can continue to be used for more specialized applications albeit 97 | without the expectation of widespread software support or portability 98 | between hardware platforms. 99 | 100 | NOTE: As RISC-V evolves over time, the set of ISA features will grow, 101 | and new platforms will be added that may need different profiles. To 102 | manage this evolution, RISC-V is adopting a model of regular annual 103 | releases of new ISA profiles, following an ISA roadmap managed by the 104 | RISC-V Technical Steering Committee. The architecture profiles will 105 | also be used for branding and to advertise compatibility with the 106 | RISC-V standard. 107 | 108 | This document describes the general structure of RISC-V architecture 109 | profiles and also the specifics of the first few profiles: RVI20 is a 110 | generic RISC-V unprivileged software profile, and RVA20 and RVA22 are 111 | architecture profiles for application processors. 112 | 113 | == Profiles versus Platforms 114 | 115 | Profiles only describe ISA features, not a complete execution 116 | environment. 117 | 118 | A _software_ _platform_ is a specification for an execution 119 | environment, in which software targeted for that software platform can 120 | run. 121 | 122 | A _hardware_ _platform_ is a specification for a hardware system 123 | (which can be viewed as a physical realization of an execution 124 | environment). 125 | 126 | Both software and hardware platforms include specifications for many 127 | features beyond details of the ISA used by RISC-V harts in the 128 | platform (e.g., boot process, calling convention, behavior of 129 | environment calls, discovery mechanism, presence of certain 130 | memory-mapped hardware devices, etc.). Architecture profiles factor 131 | out ISA-specific definitions from platform definitions to allow ISA 132 | profiles to be reused across different platforms, and to be used by 133 | tools (e.g., compilers) that are common across many different 134 | platforms. 135 | 136 | A platform can add additional constraints on top of those in a 137 | profile. For example, mandating an extension that is a standard 138 | option in the underlying profile, or constraining some 139 | implementation-specific parameter in the profile to lie within a 140 | certain range. 141 | 142 | A platform cannot remove mandates or reduce other requirements in a 143 | profile. 144 | 145 | NOTE: A new profile should be proposed if existing profiles do not 146 | match the needs of a new platform. 147 | 148 | == Components of a Profile 149 | 150 | === Profile Family 151 | 152 | Every profile is a member of a _profile_ _family_. A profile family 153 | is a set of profiles that share the same base ISA but which vary in 154 | highest-supported privilege mode. The initial two types of family 155 | are: 156 | 157 | - generic unprivileged instructions (I) 158 | - application processors running rich operating systems (A) 159 | 160 | NOTE: More profile families may be added over time. 161 | 162 | A profile family may be updated no more than annually, and the release 163 | calendar year is treated as part of the profile family name. 164 | 165 | Each profile family is described in more detail below. 166 | 167 | === Profile Privilege Mode 168 | 169 | RISC-V has a layered architecture supporting multiple privilege modes, 170 | and most RISC-V platforms support more than one privilege mode. 171 | Software is usually written assuming a particular privilege mode 172 | during execution. For example, application code is written assuming 173 | it will be run in user mode, and kernel code is written assuming it 174 | will be run in supervisor mode. 175 | 176 | NOTE: Software can be run in a mode different than the one for which 177 | it was written. For example, privileged code using privileged ISA 178 | features can be run in a user-mode execution environment, but will 179 | then cause traps into the enclosing execution environment when 180 | privileged instructions are executed. This behavior might be 181 | exploited, for example, to emulate a privileged execution environment 182 | using a user-mode execution environment. 183 | 184 | The profile for a privilege mode describes the ISA features for an 185 | execution environment that has the eponymous privilege mode as the 186 | most-privileged mode available, but also includes all supported 187 | lower-privilege modes. In general, available instructions vary by 188 | privilege mode, and the behavior of RISC-V instructions can depend on 189 | the current privilege mode. For example, an S-mode profile includes 190 | U-mode as well as S-mode and describes the behavior of instructions 191 | when running in different modes in an S-mode execution environment, 192 | such as how an `ecall` instruction in U-mode causes a contained trap 193 | into an S-mode handler whereas an `ecall` in S-mode causes a requested 194 | trap out to the execution environment. 195 | 196 | A profile may specify that certain conditions will cause a requested 197 | trap (such as an `ecall` made in the highest-supported privilege mode) 198 | or fatal trap to the enclosing execution environment. The profile 199 | does not specify the behavior of the enclosing execution environment 200 | in handling requested or fatal traps. 201 | 202 | NOTE: In particular, a profile does not specify the set of ECALLs 203 | available in the outer execution environment. This should be 204 | documented in the appropriate binary interface to the outer execution 205 | environment (e.g., Linux user ABI, or RISC-V SEE). 206 | 207 | NOTE: In general, a profile can be implemented by an execution 208 | environment using any hardware or software technique that provides 209 | compatible functionality, including pure software emulation. 210 | 211 | A profile does not specify any invisible traps. 212 | 213 | NOTE: In particular, a profile does not constrain how invisible traps 214 | to a more-privileged mode can be used to emulate profile features. 215 | 216 | A more-privileged profile can always support running software to 217 | implement a less-privileged profile from the same profile family. For 218 | example, a platform supporting the S-mode profile can run a 219 | supervisor-mode operating system that provides user-mode execution 220 | environments supporting the U-mode profile. 221 | 222 | NOTE: Instructions in a U-mode profile, which are all executed in user 223 | mode, have potentially different behaviors than instructions executed 224 | in user mode in an S-mode profile. For this reason, a U-mode profile 225 | cannot be considered a subset of an S-mode profile. 226 | 227 | === Profile ISA Features 228 | 229 | An architecture profile has a mandatory ratified base instruction set 230 | (RV32I or RV64I for the current profiles). The profile also includes 231 | ratified ISA extensions placed into two categories: 232 | 233 | . Mandatory 234 | . Optional 235 | 236 | As the name implies, _Mandatory_ _ISA_ _extensions_ are a required 237 | part of the profile. Implementations of the profile must provide 238 | these. The combination of the profile base ISA plus the mandatory ISA 239 | extensions are termed the profile _mandates_, and software using the 240 | profile can assume these always exist. 241 | 242 | The _Optional_ category (also known as _options_) contains extensions 243 | that may be added as options, and which are expected to be generally 244 | supported as options by the software ecosystem for this profile. 245 | 246 | NOTE: The level of "support" for an Optional extension will likely 247 | vary greatly among different software components supporting a profile. 248 | Users would expect that software claiming compatibility with a profile 249 | would make use of any available supported options, but as a bare 250 | minimum software should not report errors or warnings when supported 251 | options are present in a system. 252 | 253 | An optional extension may comprise many individually named and 254 | ratified extensions but a profile option requires all constituent 255 | extensions are present. In particular, unless explicitly listed as a 256 | profile option, individual extensions are not by themselves a profile 257 | option even when required as part of a profile option. For example, 258 | the Zbkb extension is not by itself a profile option even though it is a 259 | required component of the Zkn option. 260 | 261 | NOTE: Profile optional extensions are intended to capture the 262 | granularity at which the broad software ecosystem is expected to cope 263 | with combinations of extensions. 264 | 265 | All components of a ratified profile must themselves have been 266 | ratified. 267 | 268 | Platforms may provide a discovery mechanism to determine what optional 269 | extensions are present. 270 | 271 | Extensions that are not explicitly listed in the mandatory or optional 272 | categories are termed _non-profile_ extensions, and are not considered 273 | parts of the profile. Some non-profile extensions can be added to an 274 | implementation without conflicting with the mandatory or optional 275 | components of a profile. In this case, the implementation is still 276 | compatible with the profile even though additional non-profile 277 | extensions are present. Other non-profile extensions added to an 278 | implementation might alter or conflict with the behavior of the 279 | mandatory or optional extensions in a profile, in which case the 280 | implementation would not be compatible with the profile. 281 | 282 | NOTE: Extensions that are released after a given profile is released 283 | are by definition non-profile extensions. For example, mandatory or 284 | optional profile extensions for a new profile might be prototyped as 285 | non-profile extensions on an earlier profile. 286 | 287 | === Profile Naming Convention 288 | 289 | A profile name is a string comprised of, in order: 290 | 291 | . Prefix *RV* for RISC-V. 292 | . A specific profile family name string. Initially a single letter (*I*, *M*, or *A*), but later profiles may have longer family name strings. 293 | . A numeric string giving the first complete calendar year for which 294 | the profile is ratified, represented as number of years after year 295 | 2000, i.e., *20* for profiles built on specifications ratified during 2019. The year string will be longer than two digits in the next century. 296 | . A privilege mode (*U*, *S*, *M*). Hypervisor support is treated as an option. 297 | . A base ISA XLEN specifier (*32*, *64*). 298 | 299 | The initial profiles based on specifications ratified in 2019 are: 300 | 301 | - RVI20U32 basic unprivileged instructions for RV32I 302 | - RVI20U64 basic unprivileged instructions for RV64I 303 | - RVA20U64, RVA20S64 64-bit application-processor profiles 304 | 305 | NOTE: Profile names are embeddable into RISC-V ISA naming strings. 306 | This implies that there will be no standard ISA extension with a name 307 | that matches the profile naming convention. This allows tools that 308 | process the RISC-V ISA naming string to parse and/or process a combined 309 | string. 310 | 311 | == RVI20 Profiles 312 | 313 | The RVI20 profiles document the initial set of unprivileged 314 | instructions. These provide a generic target for software toolchains 315 | and represent the minimum level of compatibility with RISC-V ratified 316 | standards. The two profiles RVI20U32 and RVI20U64 correspond to the 317 | RV32I and RV64I base ISAs respectively. 318 | 319 | NOTE: These are designed as _unprivileged_ profiles as opposed to 320 | _user_-_mode_ profiles. Code using this profile can run in any 321 | privilege mode, and so requested and fatal traps may be horizontal 322 | traps into an execution environment running in the same privilege 323 | mode. 324 | 325 | === RVI20U32 326 | 327 | RVI20U32 specifies the ISA features available to generic unprivileged 328 | execution environments. 329 | 330 | ==== RVI20U32 Mandatory Base 331 | 332 | RV32I is the mandatory base ISA for RVI20U32, and is little-endian. 333 | 334 | As per the unprivileged architecture specification, the `ecall` 335 | instruction causes a requested trap to the execution environment. 336 | 337 | Misaligned loads and stores might not be supported. 338 | 339 | The `fence.tso` instruction is mandatory. 340 | 341 | NOTE: The `fence.tso` instruction was incorrectly described as 342 | optional in the 2019 ratified specifications. However, `fence.tso` is 343 | encoded within the standard `fence` encoding such that implementations 344 | must treat it as a simple global fence if they do not natively support 345 | TSO-ordering optimizations. As software can always assume without any 346 | penalty that `fence.tso` is being exploited by a hardware 347 | implementation, there is no advantage to making the instruction an 348 | option. Later versions of the unprivileged ISA specifications 349 | correctly indicate that `fence.tso` is mandatory. 350 | 351 | ==== RVI20U32 Mandatory Extensions 352 | 353 | There are no mandatory extensions for RVI20U32. 354 | 355 | ==== RVI20U32 Optional Extensions 356 | 357 | - *M* Integer multiplication and division. 358 | 359 | - *A* Atomic instructions. 360 | 361 | - *F* Single-precision floating-point instructions. 362 | 363 | - *D* Double-precision floating-point instructions. 364 | 365 | NOTE: The rationale to not include Q as an optional extension is that 366 | quad-precision floating-point is unlikely to be implemented in 367 | hardware, and so we do not require or expect software to expend effort 368 | optimizing use of Q instructions in case they are present. 369 | 370 | - *C* Compressed Instructions. 371 | 372 | - *Zifencei* Instruction-fetch fence instruction. 373 | 374 | - Misaligned loads and stores may be supported. 375 | 376 | - *Zicntr* Basic counters. 377 | 378 | NOTE: The Zicsr extension is not supported independent of the Zicntr or 379 | F extensions. 380 | 381 | - *Zihpm* Hardware performance counters. 382 | 383 | === RVI20U64 384 | 385 | RVI20U64 specifies the ISA features available to generic unprivileged 386 | execution environments. 387 | 388 | ==== RVI20U64 Mandatory Base 389 | 390 | RV64I is the mandatory base ISA for RVI20U64, and is little-endian. 391 | 392 | As per the unprivileged architecture specification, the `ecall` 393 | instruction causes a requested trap to the execution environment. 394 | 395 | Misaligned loads and stores might not be supported. 396 | 397 | The `fence.tso` instruction is mandatory. 398 | 399 | NOTE: The `fence.tso` instruction was incorrectly described as 400 | optional in the 2019 ratified specifications. However, `fence.tso` is 401 | encoded within the standard `fence` encoding such that implementations 402 | must treat it as a simple global fence if they do not natively support 403 | TSO-ordering optimizations. As software can always assume without any 404 | penalty that `fence.tso` is being exploited by a hardware 405 | implementation, there is no advantage to making the instruction a 406 | profile option. Later versions of the unprivileged ISA specifications 407 | correctly indicate that `fence.tso` is mandatory. 408 | 409 | ==== RVI20U64 Mandatory Extensions 410 | 411 | There are no mandatory extensions for RVI20U64. 412 | 413 | ==== RVI20U64 Optional Extensions 414 | 415 | - *M* Integer multiplication and division. 416 | 417 | - *A* Atomic instructions. 418 | 419 | - *F* Single-precision floating-point instructions. 420 | 421 | - *D* Double-precision floating-point instructions. 422 | 423 | NOTE: The rationale to not include Q as a profile option is that 424 | quad-precision floating-point is unlikely to be implemented in 425 | hardware, and so we do not require or expect software to expend effort 426 | optimizing use of Q instructions in case they are present. 427 | 428 | - *C* Compressed Instructions. 429 | 430 | - *Zifencei* Instruction-fetch fence instruction. 431 | 432 | - Misaligned loads and stores may be supported. 433 | 434 | - *Zicntr* Basic counters. 435 | 436 | NOTE: The Zicsr extension is not supported independent of the Zicntr or 437 | F extensions. 438 | 439 | - *Zihpm* Hardware performance counters. 440 | 441 | == RVA20 Profiles 442 | 443 | The RVA20 profiles are intended to be used for 64-bit application 444 | processors running rich OS stacks. Only user-mode (RVA20U64) and 445 | supervisor-mode (RVA20S64) profiles are specified in this family. 446 | 447 | NOTE: There is no machine-mode profile currently defined for 448 | application processor families. A machine-mode profile for 449 | application processors would only be used in specifying platforms for 450 | portable machine-mode software. Given the relatively low volume of 451 | portable M-mode software in this domain, the wide variety of potential 452 | M-mode code, and the very specific needs of each type of M-mode 453 | software, we are not specifying individual M-mode ISA requirements in 454 | the A-family profiles. 455 | 456 | NOTE: Only XLEN=64 application processor profiles are currently 457 | defined. It would be possible to also define very similar XLEN=32 458 | variants. 459 | 460 | === RVA20U64 Profile 461 | 462 | The RVA20U64 profile specifies the ISA features available to user-mode 463 | execution environments in 64-bit applications processors. This is the 464 | most important profile within the application processor family in 465 | terms of the amount of software that targets this profile. 466 | 467 | RVA20U64 has one optional extension (Zihpm). 468 | 469 | ==== RVA20U64 Mandatory Base 470 | 471 | RV64I is the mandatory base ISA for RVA20U64, and is little-endian. 472 | 473 | As per the unprivileged architecture specification, the `ecall` 474 | instruction causes a requested trap to the execution environment. 475 | 476 | The `fence.tso` instruction is mandatory. 477 | 478 | NOTE: The `fence.tso` instruction was incorrectly described as 479 | optional in the 2019 ratified specifications. However, `fence.tso` is 480 | encoded within the standard `fence` encoding such that implementations 481 | must treat it as a simple global fence if they do not natively support 482 | TSO-ordering optimizations. As software can always assume without any 483 | penalty that `fence.tso` is being exploited by a hardware 484 | implementation, there is no advantage to making the instruction a 485 | profile option. Later versions of the unprivileged ISA 486 | specifications correctly indicate that `fence.tso` is mandatory. 487 | 488 | ==== RVA20U64 Mandatory Extensions 489 | 490 | - *M* Integer multiplication and division. 491 | - *A* Atomic instructions. 492 | - *F* Single-precision floating-point instructions. 493 | - *D* Double-precision floating-point instructions. 494 | - *C* Compressed Instructions. 495 | - *Zicsr* CSR instructions. These are implied by presence of Zicntr or F. 496 | - *Zicntr* Basic counters. 497 | 498 | - *Ziccif* Main memory regions with both the cacheability and 499 | coherence PMAs must support instruction fetch, and any instruction 500 | fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) 501 | (i.e., 32 bits for RVA20) are atomic. 502 | 503 | NOTE: Ziccif is a new extension name capturing this feature. The 504 | fetch atomicity requirement facilitates runtime patching of aligned 505 | instructions. 506 | 507 | - *Ziccrse* Main memory regions with both the cacheability and coherence PMAs must 508 | support RsrvEventual. 509 | 510 | NOTE: Ziccrse is a new extension name capturing this feature. 511 | 512 | - *Ziccamoa* Main memory regions with both the cacheability and coherence PMAs must 513 | support AMOArithmetic. 514 | 515 | NOTE: Ziccamoa is a new extension name capturing this feature. 516 | 517 | - *Za128rs* Reservation sets must be contiguous, naturally aligned, 518 | and at most 128 bytes in size. 519 | 520 | NOTE: Za128rs is a new extension name capturing this feature. The 521 | minimum reservation set size is effectively determined by the size of 522 | atomic accesses in the A extension. 523 | 524 | - *Zicclsm* Misaligned loads and stores to main memory regions with both the 525 | cacheability and coherence PMAs must be supported. 526 | 527 | NOTE: This introduces a new extension name for this feature. This 528 | requires misaligned support for all regular load and store 529 | instructions (including scalar and vector) but not AMOs or other 530 | specialized forms of memory access. Even though mandated, misaligned 531 | loads and stores might execute extremely slowly. Standard software 532 | distributions should assume their existence only for correctness, not 533 | for performance. 534 | 535 | ==== RVA20U64 Optional Extensions 536 | 537 | - *Zihpm* Hardware performance counters. 538 | 539 | NOTE: Hardware performance counters are a supported option in RVA20. 540 | The number of counters is platform-specific. 541 | 542 | NOTE: The rationale to not make Q an optional extension is that 543 | quad-precision floating-point is unlikely to be implemented in 544 | hardware, and so we do not require or expect A-profile software to 545 | expend effort optimizing use of Q instructions in case they are 546 | present. 547 | 548 | NOTE: Zifencei is not classed as a supported option in the user-mode 549 | profile because it is not sufficient by itself to produce the desired 550 | effect in a multiprogrammed multiprocessor environment without OS 551 | support, and so the instruction cache flush should always be performed 552 | using an OS call rather than using the `fence.i` instruction. 553 | `fence.i` semantics can be expensive to implement for some hardware 554 | memory hierarchy designs, and so alternative non-standard 555 | instruction-cache coherence mechanisms can be used behind the OS 556 | abstraction. A separate extension is being developed for more general 557 | and efficient instruction cache coherence. 558 | 559 | NOTE: The execution environment must provide a means to synchronize writes to 560 | instruction memory with instruction fetches, the implementation of which 561 | likely relies on the Zifencei extension. 562 | For example, RISC-V Linux supplies the `__riscv_flush_icache` system call and 563 | a corresponding vDSO call. 564 | 565 | ==== RVA20U64 Recommendations 566 | 567 | Recommendations are not strictly mandated but are included to guide 568 | implementers making design choices. 569 | 570 | Implementations are strongly recommended to raise illegal-instruction 571 | exceptions on attempts to execute unimplemented opcodes. 572 | 573 | === RVA20S64 Profile 574 | 575 | The RVA20S64 profile specifies the ISA features available to a 576 | supervisor-mode execution environment in 64-bit applications 577 | processors. RVA20S64 is based on privileged architecture version 578 | 1.11. 579 | 580 | RVA20S64 has one unprivileged option (Zihpm) and one privileged option 581 | (Sv48). 582 | 583 | ==== RVA20S64 Mandatory Base 584 | 585 | RV64I is the mandatory base ISA for RVA20S64, and is little-endian. 586 | 587 | The `ecall` instruction operates as per the unprivileged architecture 588 | specification. An `ecall` in user mode causes a contained trap to 589 | supervisor mode. An `ecall` in supervisor mode causes a requested 590 | trap to the execution environment. 591 | 592 | ==== RVA20S64 Mandatory Extensions 593 | 594 | The following unprivileged extensions are mandatory: 595 | 596 | - The RVA20S64 mandatory unprivileged extensions include all the 597 | mandatory unprivileged extensions in RVA20U64. 598 | 599 | - *Zifencei* Instruction-Fetch Fence. 600 | 601 | NOTE: Zifencei is mandated as it is the only standard way to support 602 | instruction-cache coherence in RVA20 application processors. A new 603 | instruction-cache coherence mechanism is under development which might 604 | be added as an option in the future. 605 | 606 | The following privileged extensions are mandatory: 607 | 608 | - *Ss1p11* Privileged Architecture version 1.11. 609 | 610 | - *Svbare* The `satp` mode Bare must be supported. 611 | 612 | NOTE: This is a new extension name for this feature. 613 | 614 | - *Sv39* Page-Based 39-bit Virtual-Memory System. 615 | 616 | - *Svade* Page-fault exceptions are raised when a page is accessed 617 | when A bit is clear, or written when D bit is clear. 618 | 619 | NOTE: This is a new extension name for this feature. 620 | 621 | - *Ssccptr* Main memory regions with both the cacheability and 622 | coherence PMAs must support hardware page-table reads. 623 | 624 | NOTE: This is a new extension name for this feature. 625 | 626 | - *Sstvecd* `stvec.MODE` must be capable of holding the value 0 (Direct). When 627 | `stvec.MODE=Direct`, `stvec.BASE` must be capable of holding any 628 | valid four-byte-aligned address. 629 | 630 | NOTE: This is a new extension name for this feature. 631 | 632 | - *Sstvala* `stval` must be written with the faulting virtual address for load, 633 | store, and instruction page-fault, access-fault, and misaligned 634 | exceptions, and for breakpoint exceptions other than those caused by 635 | execution of the `ebreak` or `c.ebreak` instructions. For 636 | virtual-instruction and illegal-instruction exceptions, `stval` must be written with the 637 | faulting instruction. 638 | 639 | NOTE: This is a new extension name for this feature. 640 | 641 | ==== RVA20S64 Optional Extensions 642 | 643 | RVA20S64 has one unprivileged option. 644 | 645 | - *Zihpm* Hardware performance counters. 646 | 647 | NOTE: The number of counters is platform-specific. 648 | 649 | RVA20S64 has the following privileged options: 650 | 651 | - *Sv48* Page-Based 48-bit Virtual-Memory System. 652 | 653 | - *Ssu64xl* `sstatus.UXL` must be capable of holding the value 2 654 | (i.e., UXLEN=64 must be supported). 655 | 656 | NOTE: This is a new extension name for this feature. 657 | 658 | == RVA22 Profiles 659 | 660 | The RVA22 profiles are intended to be used for 64-bit application 661 | processors running rich OS stacks. Only user-mode (RVA22U64) and 662 | supervisor-mode (RVA22S64) profiles are specified in this family. 663 | 664 | === RVA22U64 Profile 665 | 666 | The RVA22U64 profile specifies the ISA features available to user-mode 667 | execution environments in 64-bit applications processors. This is the 668 | most important profile within the application processor family in 669 | terms of the amount of software that targets this profile. 670 | 671 | ==== RVA22U64 Mandatory Base 672 | 673 | RV64I is the mandatory base ISA for RVA22U64, including mandatory `fence.tso`, and is little-endian. 674 | 675 | NOTE: Later versions of the RV64I unprivileged ISA specification 676 | ratified in 2021 made clear that `fence.tso` is mandatory. 677 | 678 | As per the unprivileged architecture specification, the `ecall` 679 | instruction causes a requested trap to the execution environment. 680 | 681 | ==== RVA22U64 Mandatory Extensions 682 | 683 | The following mandatory extensions were present in RVA20U64. 684 | 685 | - *M* Integer multiplication and division. 686 | - *A* Atomic instructions. 687 | - *F* Single-precision floating-point instructions. 688 | - *D* Double-precision floating-point instructions. 689 | - *C* Compressed Instructions. 690 | - *Zicsr* CSR instructions. These are implied by presence of F. 691 | - *Zicntr* Base counters and timers. 692 | 693 | - *Ziccif* Main memory regions with both the cacheability and 694 | coherence PMAs must support instruction fetch, and any instruction 695 | fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) 696 | (i.e., 32 bits for RVA22) are atomic. 697 | 698 | - *Ziccrse* Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. 699 | 700 | NOTE: Ziccrse is a new extension name capturing this feature. 701 | 702 | - *Ziccamoa* Main memory regions with both the cacheability and coherence PMAs must support AMOArithmetic. 703 | 704 | NOTE: Ziccamoa is a new extension name capturing this feature. 705 | 706 | - *Zicclsm* Misaligned loads and stores to main memory regions with both the 707 | cacheability and coherence PMAs must be supported. 708 | 709 | NOTE: This is a new extension name for this feature. Even though 710 | mandated, misaligned loads and stores might execute extremely slowly. 711 | Standard software distributions should assume their existence only for 712 | correctness, not for performance. 713 | 714 | The following mandatory feature was further restricted in RVA22U64: 715 | 716 | - *Za64rs* Reservation sets are contiguous, naturally aligned, and a 717 | maximum of 64 bytes. 718 | 719 | NOTE: This is a new extension name capturing this feature. The 720 | maximum reservation size has been reduced to match the required cache 721 | block size. The minimum reservation size is effectively set by the 722 | instructions in the mandatory A extension. 723 | 724 | The following mandatory extensions are new for RVA22U64. 725 | 726 | - *B* Bit-manipulation instructions. 727 | 728 | NOTE: The B extension comprises the Zba, Zbb, and Zbs extensions. 729 | At the time of RVA22U64's ratification, the B extension had not yet been 730 | defined, and so RVA22U64 explicitly mandated Zba, Zbb, and Zbs instead. 731 | Mandating B is equivalent. 732 | 733 | - *Zihpm* Hardware performance counters. 734 | 735 | NOTE: Zihpm was optional in RVA20U64. 736 | 737 | - *Zihintpause* Pause instruction. 738 | 739 | NOTE: While the `pause` instruction is a HINT can be implemented as a 740 | NOP and hence trivially supported by hardware implementers, its 741 | inclusion in the mandatory extension list signifies that software 742 | should use the instruction whenever it would make sense and that 743 | implementors are expected to exploit this information to optimize 744 | hardware execution. 745 | 746 | - *Zic64b* Cache blocks must be 64 bytes in size, naturally aligned in the 747 | address space. 748 | 749 | NOTE: This is a new extension name for this feature. While the general 750 | RISC-V specifications are agnostic to cache block size, selecting a 751 | common cache block size simplifies the specification and use of the 752 | following cache-block extensions within the application processor 753 | profile. Software does not have to query a discovery mechanism and/or 754 | provide dynamic dispatch to the appropriate code. We choose 64 bytes 755 | at it is effectively an industry standard. Implementations may use 756 | longer cache blocks to reduce tag cost provided they use 64-byte 757 | sub-blocks to remain compatible. Implementations may use shorter cache 758 | blocks provided they sequence cache operations across the multiple 759 | cache blocks comprising a 64-byte block to remain compatible. 760 | 761 | - *Zicbom* Cache-Block Management Operations. 762 | - *Zicbop* Cache-Block Prefetch Operations. 763 | 764 | NOTE: As with other HINTS, the inclusion of prefetches in the 765 | mandatory set of extensions indicates that software should generate 766 | these instructions where they are expected to be useful, and hardware 767 | is expected to exploit that information. 768 | 769 | - *Zicboz* Cache-Block Zero Operations. 770 | 771 | - *Zfhmin* Half-Precision Floating-point transfer and convert. 772 | 773 | NOTE: Zfhmin is a small extension that adds support to load/store and convert 774 | IEEE 754 half-precision numbers to and from the IEEE 754 single-precision 775 | format. The hardware cost for this extension is low, and mandating the 776 | extension avoids adding an option to the profile. 777 | 778 | - *Zkt* Data-independent execution time. 779 | 780 | NOTE: Zkt requires a certain subset of integer instructions execute 781 | with data-independent latency. Mandating this feature enables 782 | portable libraries for safe basic cryptographic operations. It is 783 | expected that application processors will naturally have this property 784 | and so implementation cost is low, if not zero, in most systems that 785 | would support RVA22. 786 | 787 | ==== RVA22U64 Optional Extensions 788 | 789 | RVA22U64 has four profile options (Zfh, V, Zkn, Zks): 790 | 791 | - *Zfh* Half-Precision Floating-Point. 792 | 793 | NOTE: A future profile might mandate Zfh. 794 | 795 | - *V* Vector Extension. 796 | 797 | NOTE: The smaller vector extensions (Zve32f, Zve32x, Zve64d, Zve64f, 798 | Zve64x) are not provided as separately supported profile options. The 799 | full V extension is specified as the only supported profile option. 800 | 801 | NOTE: A future profile might mandate V. 802 | 803 | - *Zkn* Scalar Crypto NIST Algorithms. 804 | - *Zks* Scalar Crypto ShangMi Algorithms. 805 | 806 | NOTE: The scalar crypto extensions are expected to be superseded by 807 | vector crypto standards in future profiles, and the scalar extensions 808 | may be removed as supported options once vector crypto is present. 809 | 810 | NOTE: The smaller component scalar crypto extensions (Zbc, Zbkb, Zbkc, 811 | Zbkx, Zknd, Zkne, Zknh, Zksed, Zksh) are not provided as separate 812 | options in the profile. Profile implementers should provide all of 813 | the instructions in a given algorithm suite as part of the Zkn or Zks 814 | supported options. 815 | 816 | NOTE: Access to the entropy source (Zkr) in a system is usually 817 | carefully controlled. While the design supports unprivileged access 818 | to the entropy source, this is unlikely to be commonly used in an 819 | application processor, and so Zkr was not added as a profile option. 820 | This also means the roll-up Zk was not added as a profile option. 821 | 822 | NOTE: The Zfinx, Zdinx, Zhinx, Zhinxmin extensions are incompatible 823 | with the profile mandates to support the F and D extensions. 824 | 825 | ==== RVA22U64 Recommendations 826 | 827 | Recommendations are not strictly mandated but are included to guide 828 | implementers making design choices. 829 | 830 | Implementations are strongly recommended to raise illegal-instruction 831 | exceptions on attempts to execute unimplemented opcodes. 832 | 833 | === RVA22S64 Profile 834 | 835 | The RVA22S64 profile specifies the ISA features available to a 836 | supervisor-mode execution environment in 64-bit applications 837 | processors. RVA22S64 is based on privileged architecture version 838 | 1.12. 839 | 840 | ==== RVA22S64 Mandatory Base 841 | 842 | RV64I is the mandatory base ISA for RVA22S64, including mandatory 843 | `fence.tso`, and is little-endian. 844 | 845 | NOTE: Later versions of the RV64I unprivileged ISA specification 846 | ratified in 2021 made clear that `fence.tso` is mandatory. 847 | 848 | The `ecall` instruction operates as per the unprivileged architecture 849 | specification. An `ecall` in user mode causes a contained trap to 850 | supervisor mode. An `ecall` in supervisor mode causes a requested 851 | trap to the execution environment. 852 | 853 | ==== RVA22S64 Mandatory Extensions 854 | 855 | The following unprivileged extensions are mandatory: 856 | 857 | - The RVA22S64 mandatory unprivileged extensions include all the 858 | mandatory unprivileged extensions in RVA22U64. 859 | 860 | - *Zifencei* Instruction-Fetch Fence. 861 | 862 | NOTE: Zifencei is mandated as it is the only standard way to support 863 | instruction-cache coherence in RVA22 application processors. A new 864 | instruction-cache coherence mechanism is under development which might 865 | be added as an option in the future. 866 | 867 | The following privileged extensions are mandatory: 868 | 869 | - *Ss1p12* Privileged Architecture version 1.12. 870 | 871 | NOTE: Ss1p12 supersedes Ss1p11. 872 | 873 | - *Svbare* The `satp` mode Bare must be supported. 874 | 875 | NOTE: This is a new extension name for this feature. 876 | 877 | - *Sv39* Page-Based 39-bit Virtual-Memory System. 878 | 879 | - *Svade* Page-fault exceptions are raised when a page is accessed 880 | when A bit is clear, or written when D bit is clear. 881 | 882 | - *Ssccptr* Main memory regions with both the cacheability and 883 | coherence PMAs must support hardware page-table reads. 884 | 885 | - *Sstvecd* `stvec.MODE` must be capable of holding the value 0 886 | (Direct). When `stvec.MODE=Direct`, `stvec.BASE` must be capable of 887 | holding any valid four-byte-aligned address. 888 | 889 | - *Sstvala* stval must be written with the faulting virtual address 890 | for load, store, and instruction page-fault, access-fault, and 891 | misaligned exceptions, and for breakpoint exceptions other than 892 | those caused by execution of the EBREAK or C.EBREAK instructions. 893 | For virtual-instruction and illegal-instruction exceptions, stval must be written with the 894 | faulting instruction. 895 | 896 | - *Sscounterenw* For any hpmcounter that is not read-only zero, the corresponding bit in scounteren must be writable. 897 | 898 | NOTE: This is new extension name capturing this feature. 899 | 900 | - *Svpbmt* Page-Based Memory Types 901 | 902 | - *Svinval* Fine-Grained Address-Translation Cache Invalidation 903 | 904 | ==== RVA22S64 Optional Extensions 905 | 906 | RVA22S64 has four unprivileged options (Zfh, V, Zkn, Zks) from 907 | RVA22U64, and eight privileged options (Sv48, Sv57, Svnapot, Ssu64xl, 908 | Sstc, Sscofpmf, Zkr, H). 909 | 910 | The privileged optional extensions are: 911 | 912 | - *Sv48* Page-Based 48-bit Virtual-Memory System. 913 | 914 | - *Sv57* Page-Based 57-bit Virtual-Memory System. 915 | 916 | - *Svnapot* NAPOT Translation Contiguity 917 | 918 | NOTE: It is expected that Svnapot will be mandatory in the next 919 | profile release. 920 | 921 | - *Ssu64xl* `sstatus.UXL` must be capable of holding the value 2 922 | (i.e., UXLEN=64 must be supported). 923 | 924 | NOTE: This is a new extension name for this feature. 925 | 926 | - *Sstc* supervisor-mode timer interrupts. 927 | 928 | NOTE: Sstc was not made mandatory in RVA22S64 as it is a more 929 | disruptive change affecting system-level architecture, and will take 930 | longer for implementations to adopt. It is expected to be made 931 | mandatory in the next profile release. 932 | 933 | - *Sscofpmf* Count Overflow and Mode-Based Filtering. 934 | 935 | NOTE: Platforms may choose to mandate the presence of Sscofpmf. 936 | 937 | - *Zkr* Entropy CSR. 938 | 939 | NOTE: Technically, Zk is also a privileged-mode option capturing that 940 | Zkr, Zkn, and Zkt are all implemented. However, the Zk rollup is less 941 | descriptive than specifying the individual extensions explicitly. 942 | 943 | - *Sha* The augmented hypervisor extension. 944 | Sha comprises the following extensions: 945 | 946 | ** *H* The hypervisor extension. 947 | 948 | ** *Ssstateen* Supervisor-mode view of the state-enable extension. The 949 | supervisor-mode (`sstateen0-3`) and hypervisor-mode (`hstateen0-3`) 950 | state-enable registers must be provided. 951 | 952 | ** *Shcounterenw* For any `hpmcounter` that is not read-only zero, the corresponding bit in `hcounteren` must be writable. 953 | 954 | ** *Shvstvala* `vstval` must be written in all cases described above for `stval`. 955 | 956 | ** *Shtvala* `htval` must be written with the faulting guest physical 957 | address in all circumstances permitted by the ISA. 958 | 959 | ** *Shvstvecd* `vstvec.MODE` must be capable of holding the value 0 (Direct). 960 | When `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding 961 | any valid four-byte-aligned address. 962 | 963 | ** *Shvsatpa* All translation modes supported in `satp` must be supported in `vsatp`. 964 | 965 | ** *Shgatpa* For each supported virtual memory scheme SvNN supported in 966 | `satp`, the corresponding hgatp SvNNx4 mode must be supported. The 967 | `hgatp` mode Bare must also be supported. 968 | 969 | NOTE: Sha, Shcounterenw, Shvstvala, Shtvala, Shvstvecd, Shvsatpa, and Shgatpa 970 | are new extension names. Sha was introduced after RVA22S64 was ratified, but 971 | the ratified text required all of Sha's constituent extensions if the optional 972 | H extension was included. Hence, offering the Sha option is equivalent. 973 | 974 | NOTE: The Smstateen extension specification is an M-mode extension as 975 | it includes M-mode features, but the supervisor-mode visible 976 | components of the extension are named as the Ssstateen extension. Only 977 | Ssstateen is mandated in the RVA22S64 profile when the hypervisor 978 | extension is implemented. These registers are not mandated or 979 | supported options without the hypervisor extension, as there are no 980 | RVA22S64 supported options with relevant state to control in the 981 | absence of the hypervisor extension. 982 | 983 | ==== RVA22S64 Recommendations 984 | 985 | - Implementations are strongly recommended to raise illegal-instruction 986 | exceptions when attempting to execute unimplemented opcodes. 987 | 988 | == New ISA Extensions 989 | 990 | This profile specification introduces the following new extension 991 | names for existing features, but none require new features: 992 | 993 | - *Ziccif*: Main memory supports instruction fetch with atomicity requirement 994 | - *Ziccrse*: Main memory supports forward progress on LR/SC sequences 995 | - *Ziccamoa*: Main memory supports all atomics in A 996 | - *Zicclsm*: Main memory supports misaligned loads/stores 997 | - *Za64rs*: Reservation set size of at most 64 bytes 998 | - *Za128rs*: Reservation set size of at most 128 bytes 999 | - *Zic64b*: Cache block size is 64 bytes 1000 | - *Svbare*: Bare mode virtual-memory translation supported 1001 | - *Svade*: Raise exceptions on improper A/D bits 1002 | - *Ssccptr*: Main memory supports page table reads 1003 | - *Sscounterenw*: Support writeable enables for any supported counter 1004 | - *Sstvecd*: `stvec` supports Direct mode 1005 | - *Sstvala*: `stval` provides all needed values 1006 | - *Ssu64xl*: UXLEN=64 must be supported 1007 | - *Ssstateen*: Supervisor-mode view of the state-enable extension 1008 | - *Shcounterenw*: Support writeable enables for any supported counter 1009 | - *Shvstvala*: `vstval` provides all needed values 1010 | - *Shtvala*: `htval` provides all needed values 1011 | - *Shvstvecd*: `vstvec` supports Direct mode 1012 | - *Shvsatpa*: `vsatp` supports all modes supported by `satp` 1013 | - *Shgatpa*: SvNNx4 mode supported for all modes supported by `satp`, as well as Bare 1014 | 1015 | == Glossary of ISA Extensions 1016 | 1017 | The following unprivileged ISA extensions are defined in Volume I 1018 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 1019 | 1020 | - M Extension for Integer Multiplication and Division 1021 | - A Extension for Atomic Memory Operations 1022 | - F Extension for Single-Precision Floating-Point 1023 | - D Extension for Double-Precision Floating-Point 1024 | - Q Extension for Quad-Precision Floating-Point 1025 | - C Extension for Compressed Instructions 1026 | - Zifencei Instruction-Fetch Synchronization Extension 1027 | - Zicsr Extension for Control and Status Register Access 1028 | - Zicntr Extension for Basic Performance Counters 1029 | - Zihpm Extension for Hardware Performance Counters 1030 | - Zihintpause Pause Hint Extension 1031 | - Zfh Extension for Half-Precision Floating-Point 1032 | - Zfhmin Minimal Extension for Half-Precision Floating-Point 1033 | - Zfinx Extension for Single-Precision Floating-Point in x-registers 1034 | - Zdinx Extension for Double-Precision Floating-Point in x-registers 1035 | - Zhinx Extension for Half-Precision Floating-Point in x-registers 1036 | - Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers 1037 | 1038 | The following privileged ISA extensions are defined in Volume II 1039 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 1040 | 1041 | - Sv32 Page-based Virtual Memory Extension, 32-bit 1042 | - Sv39 Page-based Virtual Memory Extension, 39-bit 1043 | - Sv48 Page-based Virtual Memory Extension, 48-bit 1044 | - Sv57 Page-based Virtual Memory Extension, 57-bit 1045 | - Svpbmt, Page-Based Memory Types 1046 | - Svnapot, NAPOT Translation Contiguity 1047 | - Svinval, Fine-Grained Address-Translation Cache Invalidation 1048 | - Hypervisor Extension 1049 | - Sm1p11, Machine Architecture v1.11 1050 | - Sm1p12, Machine Architecture v1.12 1051 | - Ss1p11, Supervisor Architecture v1.11 1052 | - Ss1p12, Supervisor Architecture v1.12 1053 | 1054 | The following extensions have not yet been incorporated into the RISC-V 1055 | Instruction Set Manual; the hyperlinks lead to their separate specifications. 1056 | 1057 | - https://github.com/riscv/riscv-bitmanip[Zba Address Computation Extension] 1058 | - https://github.com/riscv/riscv-bitmanip[Zbb Bit Manipulation Extension] 1059 | - https://github.com/riscv/riscv-bitmanip[Zbc Carryless Multiplication Extension] 1060 | - https://github.com/riscv/riscv-bitmanip[Zbs Single-Bit Manipulation Extension] 1061 | - https://github.com/riscv/riscv-crypto[Zbkb Extension for Bit Manipulation for Cryptography] 1062 | - https://github.com/riscv/riscv-crypto[Zbkc Extension for Carryless Multiplication for Cryptography] 1063 | - https://github.com/riscv/riscv-crypto[Zbkx Crossbar Permutation Extension] 1064 | - https://github.com/riscv/riscv-crypto[Zk Standard Scalar Cryptography Extension] 1065 | - https://github.com/riscv/riscv-crypto[Zkn NIST Cryptography Extension] 1066 | - https://github.com/riscv/riscv-crypto[Zknd AES Decryption Extension] 1067 | - https://github.com/riscv/riscv-crypto[Zkne AES Encryption Extension] 1068 | - https://github.com/riscv/riscv-crypto[Zknh SHA2 Hashing Extension] 1069 | - https://github.com/riscv/riscv-crypto[Zkr Entropy Source Extension] 1070 | - https://github.com/riscv/riscv-crypto[Zks ShangMi Cryptography Extension] 1071 | - https://github.com/riscv/riscv-crypto[Zksed SM4 Block Cypher Extension] 1072 | - https://github.com/riscv/riscv-crypto[Zksh SM3 Hashing Extension] 1073 | - https://github.com/riscv/riscv-crypto[Zkt Extension for Data-Independent Execution Latency] 1074 | - https://github.com/riscv/riscv-v-spec[V Extension for Vector Computation] 1075 | - https://github.com/riscv/riscv-v-spec[Zve32x Extension for Embedded Vector Computation (32-bit integer)] 1076 | - https://github.com/riscv/riscv-v-spec[Zve32f Extension for Embedded Vector Computation (32-bit integer, 32-bit FP)] 1077 | - https://github.com/riscv/riscv-v-spec[Zve32d Extension for Embedded Vector Computation (32-bit integer, 64-bit FP)] 1078 | - https://github.com/riscv/riscv-v-spec[Zve64x Extension for Embedded Vector Computation (64-bit integer)] 1079 | - https://github.com/riscv/riscv-v-spec[Zve64f Extension for Embedded Vector Computation (64-bit integer, 32-bit FP)] 1080 | - https://github.com/riscv/riscv-v-spec[Zve64d Extension for Embedded Vector Computation (64-bit integer, 64-bit FP)] 1081 | - https://github.com/riscv/riscv-CMOs[Zicbom Extension for Cache-Block Management] 1082 | - https://github.com/riscv/riscv-CMOs[Zicbop Extension for Cache-Block Prefetching] 1083 | - https://github.com/riscv/riscv-CMOs[Zicboz Extension for Cache-Block Zeroing] 1084 | - https://github.com/riscv/riscv-time-compare[Sstc Extension for Supervisor-mode Timer Interrupts] 1085 | - https://github.com/riscv/riscv-count-overflow[Sscofpmf Extension for Count Overflow and Mode-Based Filtering] 1086 | - https://github.com/riscv/riscv-state-enable[Smstateen Extension for State-enable] 1087 | -------------------------------------------------------------------------------- /src/rv-profile-defined-extensions.adoc: -------------------------------------------------------------------------------- 1 | == Profile-Defined Extensions 2 | 3 | This profile, as with earlier profiles, includes several new 4 | extensions defined directly in the profile text. These 5 | profile-defined extensions name optional features or combinations of 6 | features that are already present in ratified specifications, but that 7 | were not previously explicitly named. Once the profile is ratified, 8 | these extension definitions will move into the appropriate sections of 9 | the combined ISA manual. The combined ISA manual was not available at 10 | the start of this profile definition. Future profile proposals will 11 | be presented as an update to the combined ISA manual, with new 12 | profile-defined extensions provided as edits to the appropriate 13 | sections of the combined ISA manual. 14 | -------------------------------------------------------------------------------- /src/rva-profile-overview-body.adoc: -------------------------------------------------------------------------------- 1 | == RVA Profiles Rationale 2 | 3 | RISC-V was designed to provide a highly modular and extensible 4 | instruction set and includes a large and growing set of standard 5 | extensions, where each standard extension is a bundle of 6 | instruction-set features. This is no different than other industry 7 | ISAs that continue to add new ISA features. Unlike other ISAs, 8 | however, RISC-V has a broad set of contributors and implementers, and 9 | also allows users to add their own custom extensions. For some deep 10 | embedded markets, highly customized processor configurations are 11 | desirable for efficiency, and all software is compiled, ported, and/or 12 | developed in-house by the same organization for that specific 13 | processor configuration. However, for other markets that expect a 14 | substantial fraction of software to be delivered to end-customers in 15 | binary form, compatibility across multiple implementations from 16 | different RISC-V vendors is required. 17 | 18 | The RVIA ISA extension ratification process ensures that all processor 19 | vendors have agreed to the specification of a standard extension if 20 | present. However, by themselves, the ISA extension specifications do 21 | not guarantee that a certain set of standard extensions will be 22 | present in all implementations. 23 | 24 | *The primary goal of the RVA profiles is to align processor vendors 25 | targeting binary software markets, so software can rely on the 26 | existence of a certain set of ISA features in a particular generation 27 | of RISC-V implementations.* 28 | 29 | Alignment is not only for compatibility, but also to ensure RISC-V is 30 | competitive in these markets. The binary app markets are also 31 | generally those with the most competitive performance requirements 32 | (e.g., mobile, client, server). RVIA cannot mandate the ISA features 33 | that a RISC-V binary software ecosystem should use, as each ecosystem 34 | will typically select the lowest-common denominator they empirically 35 | observe in the deployed devices in their target markets. But RVIA can 36 | align hardware vendors to support a common set of features in each 37 | generation through the RVA profiles. Without proactive alignment 38 | through RVA profiles, RISC-V will be uncompetitive, as even if a 39 | particular vendor implements a certain feature, if other vendors do 40 | not, then binary distributions will not generally use that feature and 41 | all implementations will suffer. While certain features may be 42 | discoverable, and alternate code provided in case of presence/absence 43 | of a feature, the added cost to support such options is only justified 44 | for certain limited cases, and binary app markets will not support a 45 | wide range of optional features, particularly for the nascent RISC-V 46 | binary app ecosystems. 47 | 48 | To maintain alignment and increase RISC-V competitiveness over time, 49 | the mandatory set of extensions must increase over time in successive 50 | generations of RVA profile. (RVA profiles may eventually have to 51 | deprecate previously mandatory instructions, but that is unlikely in 52 | the near future.) Note that the RISC-V ISA will continue to evolve, 53 | regardless of whether a given software ecosystem settles on a certain 54 | generation of profile as the baseline for their ecosystem for many 55 | years or even decades. There are many existing binary software 56 | ecosystems, which will migrate to RISC-V and evolve at different rates, 57 | and more new ones will doubtless be created over the hopefully long 58 | lifetime of RISC-V. High-performance application processors require 59 | considerable investment, and no single binary app ecosystem can 60 | justify the development costs of these processors, especially for 61 | RISC-V in its early stage of adoption. 62 | 63 | While the heart of the profile is the set of mandatory extensions, 64 | there are several kinds of optional extension that serve important 65 | roles in the profile. 66 | 67 | The first kind are _localized_ _options_, whose presence or use 68 | necessarily differs along geo-political and/or jurisdictional 69 | boundaries, with crypto being the obvious example. These will always 70 | be optional. At least for crypto, discovery has been found to be 71 | perfectly acceptable to handle this optionality on other 72 | architectures, as the use of the extensions is well contained in 73 | certain libraries. 74 | 75 | The second kind of optional extension is a _development_ _option_, 76 | which represents a new ISA extension in an early part of its lifecycle 77 | but which is intended to become mandatory in a later generation of the 78 | RVA profile. Processor vendors and software toolchain providers will 79 | have varying development schedules, and providing an optional phase in 80 | a new extension's lifecycle provides some flexibility while 81 | maintaining overall alignment, and is particularly appropriate when 82 | hardware or software development for the extension is complex. 83 | Denoting an extension as a _development_ _option_ signals to the 84 | community that development should be prioritized for such extensions 85 | as they will become mandatory. 86 | 87 | The third kind of optional extension are _expansion_ _options_, which 88 | are those that may have a large implementation cost but are not always 89 | needed in a particular platform, and which can be readily handled by 90 | discovery. These are also intended to remain available as expansion 91 | options in future versions of the profile. Several supervisor-mode 92 | extensions fall into this category, e.g., Sv57, which has a notable 93 | PPA impact over Sv48 and is not needed on smaller platforms. Some 94 | unprivileged extensions that may fall into this category are possible 95 | future matrix extensions. These have large implementation costs, and 96 | use of matrix instructions can be readily supported with discovery and 97 | alternate math libraries. 98 | 99 | The fourth kind of optional extensions are _transitory_ _options_, 100 | where it is not clear if the extension will change to a mandatory, 101 | localized, or expansion option, or be possibly dropped over time. 102 | Cryptography provides some examples where earlier cyphers have been 103 | broken and are now deprecated. RVIA used this mechanism to enable 104 | scalar crypto until vector crypto was ready. Software security 105 | features may also be in this category, with examples of deprecated 106 | security features occuring in other architectures. As another 107 | example, the recent avalanche of new numeric datatypes for AI/ML may 108 | eventually subside with a few survivors actually being used longer 109 | term. Denoting an option as transitory signals to the community that 110 | this extension may be removed in a future profile, though the time 111 | scale may span many years. 112 | 113 | Except for the localized options, it could be argued that other three 114 | kinds of option could be left out of profiles. Binary distributions 115 | of applications willing to invest in discovery can use an optional 116 | extension, and customers compiling their own applications can take 117 | advantage of the feature on a particular implementation, even when 118 | that system is mostly running binary distributions that ignore the new 119 | extension. However, there is value in providing guidance to align 120 | hardware vendors and software developers around what extensions are 121 | worth implementing and worth discovering, by designating only a few 122 | important features as profile options and limiting their granularity. 123 | -------------------------------------------------------------------------------- /src/rva23-profile.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-doc-template]] 2 | :description: Short, text description of spect… 3 | :company: RISC-V 4 | :url-riscv: http://riscv.org 5 | :doctype: book 6 | :colophon: 7 | :appendix-caption: Appendix 8 | :imagesdir: ../docs-resources/images 9 | :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center] 10 | // Settings: 11 | :experimental: 12 | :reproducible: 13 | :WaveDromEditorApp: wavedrom-cli 14 | :imagesoutdir: images 15 | :icons: font 16 | :lang: en 17 | :listing-caption: Listing 18 | :sectnums: 19 | :sectnumlevels: 5 20 | :toclevels: 5 21 | :toc: left 22 | :source-highlighter: pygments 23 | ifdef::backend-pdf[] 24 | :source-highlighter: coderay 25 | endif::[] 26 | :data-uri: 27 | :hide-uri-scheme: 28 | :stem: latexmath 29 | :footnote: 30 | :xrefstyle: short 31 | :numbered: 32 | :stem: latexmath 33 | :le: ≤ 34 | :ge: ≥ 35 | :ne: ≠ 36 | :approx: ≈ 37 | :inf: ∞ 38 | 39 | :sectnums!: 40 | 41 | = RVA23 Profiles 42 | 43 | //: This is the Preamble 44 | 45 | include::rva-profile-overview-body.adoc[] 46 | 47 | include::rv-profile-defined-extensions.adoc[] 48 | 49 | 50 | == RVA23 Profiles 51 | 52 | The RVA23 profiles are intended to align implementations of RISC-V 53 | 64-bit application processors to allow binary software ecosystems to 54 | rely on a large set of guaranteed extensions and a small number of 55 | discoverable coarse-grain options. It is explicitly a non-goal of 56 | RVA23 to allow more hardware implementation flexibility by supporting 57 | only a minimal set of features and a large number of fine-grain 58 | extensions. 59 | 60 | Only user-mode (RVA23U64) and supervisor-mode (RVA23S64) profiles are 61 | specified in this family. 62 | 63 | === RVA23U64 Profile 64 | 65 | The RVA23U64 profile specifies the ISA features available to user-mode 66 | execution environments in 64-bit applications processors. This is the 67 | most important profile within the application processor family in 68 | terms of the amount of software that targets this profile. 69 | 70 | ==== RVA23U64 Mandatory Base 71 | 72 | RV64I is the mandatory base ISA for RVA23U64 and is little-endian. As 73 | per the unprivileged architecture specification, the `ECALL` 74 | instruction causes a requested trap to the execution environment. 75 | 76 | ==== RVA23U64 Mandatory Extensions 77 | 78 | The following mandatory extensions were present in RVA22U64. 79 | 80 | - *M* Integer multiplication and division. 81 | - *A* Atomic instructions. 82 | - *F* Single-precision floating-point instructions. 83 | - *D* Double-precision floating-point instructions. 84 | - *C* Compressed instructions. 85 | - *B* Bit-manipulation instructions. 86 | - *Zicsr* CSR instructions. These are implied by presence of F. 87 | - *Zicntr* Base counters and timers. 88 | - *Zihpm* Hardware performance counters. 89 | - *Ziccif* Main memory regions with both the cacheability and 90 | coherence PMAs must support instruction fetch, and any instruction 91 | fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) 92 | (i.e., 32 bits for RVA23) are atomic. 93 | - *Ziccrse* Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. 94 | - *Ziccamoa* Main memory regions with both the cacheability and coherence PMAs must support all atomics in A. 95 | - *Zicclsm* Misaligned loads and stores to main memory regions with both the 96 | cacheability and coherence PMAs must be supported. 97 | - *Za64rs* Reservation sets are contiguous, naturally aligned, and a 98 | maximum of 64 bytes. 99 | - *Zihintpause* Pause hint. 100 | - *Zic64b* Cache blocks must be 64 bytes in size, naturally aligned in the 101 | address space. 102 | - *Zicbom* Cache-block management instructions. 103 | - *Zicbop* Cache-block prefetch instructions. 104 | - *Zicboz* Cache-Block Zero Instructions. 105 | - *Zfhmin* Half-precision floating-point. 106 | - *Zkt* Data-independent execution latency. 107 | 108 | The following mandatory extensions are new in RVA23U64: 109 | 110 | - *V* Vector extension. 111 | 112 | NOTE: V was optional in RVA22U64. 113 | 114 | - *Zvfhmin* Vector minimal half-precision floating-point. 115 | 116 | - *Zvbb* Vector basic bit-manipulation instructions. 117 | 118 | - *Zvkt* Vector data-independent execution latency. 119 | 120 | - *Zihintntl* Non-temporal locality hints. 121 | 122 | - *Zicond* Integer conditional operations. 123 | 124 | - *Zimop* may-be-operations. 125 | 126 | - *Zcmop* Compressed may-be-operations. 127 | 128 | - *Zcb* Additional compressed instructions. 129 | 130 | - *Zfa* Additional floating-Point instructions. 131 | 132 | - *Zawrs* Wait-on-reservation-set instructions. 133 | 134 | - *Supm* Pointer masking, with the execution environment providing a means to 135 | select PMLEN=0 and PMLEN=7 at minimum. 136 | 137 | ==== RVA23U64 Optional Extensions 138 | 139 | ===== Localized Options 140 | 141 | The following localized options are new in RVA23U64: 142 | 143 | - *Zvkng* Vector crypto NIST algorithms with GCM. 144 | - *Zvksg* Vector crypto ShangMi algorithms with GCM. 145 | 146 | NOTE: The scalar crypto extensions Zkn and Zks that were options in 147 | RVA22 are not options in RVA23. The goal is for both hardware and 148 | software vendors to move to use vector crypto, as vectors are now 149 | mandatory and vector crypto is substantially faster than scalar 150 | crypto. 151 | 152 | NOTE: We have included only the Zvkng/Zvksg options with GCM to 153 | standardize on a higher performance crypto alternative. Zvbc is listed 154 | as a development option for use in other algorithms, and will become 155 | mandatory. Scalar Zbc is now listed as an expansion option, i.e., it 156 | will probably not become mandatory. 157 | 158 | ===== Development Options 159 | 160 | The following are new development options intended to become mandatory in a future RVA profile. 161 | 162 | - *Zabha* Byte and halfword atomic memory operations. 163 | - *Zacas* Compare-and-Swap instructions. 164 | - *Ziccamoc* Main memory regions with both the cacheability and coherence PMAs 165 | must provide `AMOCASQ` level PMA support. 166 | 167 | NOTE: Ziccamoc is a new profile-defined extension that ensures 168 | Compare and Swap instructions are properly supported in main memory 169 | regions. The extension will be added to the PMA section of the 170 | privileged architecture manual. 171 | 172 | - *Zvbc* Vector carryless multiplication. 173 | - *Zama16b* Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. 174 | 175 | NOTE: Zama16b is a new profile-defined extension that represents 176 | the presence of the new Misaligned Atomicity Granule feature added in 177 | Sm1p13. The extension will be added to the PMA section of the 178 | privileged architecture manual. 179 | 180 | ===== Expansion Options 181 | 182 | The following expansion options were also present in RVA22U64: 183 | 184 | - *Zfh* Scalar half-precision floating-point. 185 | 186 | The following are new expansion options in RVA23U64: 187 | 188 | - *Zbc* Scalar carryless multiply. 189 | - *Zicfilp* Landing Pads. 190 | - *Zicfiss* Shadow Stack. 191 | - *Zvfh* Vector half-precision floating-point. 192 | - *Zfbfmin* Scalar BF16 converts. 193 | - *Zvfbfmin* Vector BF16 converts. 194 | - *Zvfbfwma* Vector BF16 widening mul-add. 195 | 196 | ===== Transitory Options 197 | 198 | There are no transitory options in RVA23U64. 199 | 200 | NOTE: Scalar crypto is no longer an option in RVA23U64, though the Zbc 201 | extension has now been exposed as an expansion option. 202 | 203 | ==== RVA23U64 Recommendations 204 | 205 | Implementations are strongly recommended to raise illegal-instruction 206 | exceptions on attempts to execute unimplemented opcodes. 207 | 208 | === RVA23S64 Profile 209 | 210 | The RVA23S64 profile specifies the ISA features available to a 211 | supervisor-mode execution environment in 64-bit applications 212 | processors. RVA23S64 is based on privileged architecture version 213 | 1.13. 214 | 215 | ==== RVA23S64 Mandatory Base 216 | 217 | RV64I is the mandatory base ISA for RVA23S64 and is little-endian. 218 | The `ECALL` instruction operates as per the unprivileged architecture 219 | specification. An `ECALL` in user mode causes a contained trap to 220 | supervisor mode. An `ECALL` in supervisor mode causes a requested 221 | trap to the execution environment. 222 | 223 | ==== RVA23S64 Mandatory Extensions 224 | 225 | The following unprivileged extensions are mandatory: 226 | 227 | - The RVA23S64 mandatory unprivileged extensions include all the 228 | mandatory unprivileged extensions in RVA23U64. 229 | 230 | - *Zifencei* Instruction-Fetch Fence. 231 | 232 | NOTE: Zifencei is mandated as it is the only standard way to support 233 | instruction-cache coherence in RVA23 application processors. A new 234 | instruction-cache coherence mechanism is under development 235 | (tentatively named Zjid) which might be added as an option in the 236 | future. 237 | 238 | The following privileged extensions are mandatory: 239 | 240 | - *Ss1p13* Supervisor architecture version 1.13. 241 | 242 | NOTE: Ss1p13 supersedes Ss1p12. 243 | 244 | The following privileged extensions were also mandatory in RVA22S64: 245 | 246 | - *Svbare* The `satp` mode Bare must be supported. 247 | 248 | - *Sv39* Page-based 39-bit virtual-Memory system. 249 | 250 | - *Svade* Page-fault exceptions are raised when a page is accessed 251 | when A bit is clear, or written when D bit is clear. 252 | 253 | - *Ssccptr* Main memory regions with both the cacheability and 254 | coherence PMAs must support hardware page-table reads. 255 | 256 | - *Sstvecd* `stvec.MODE` must be capable of holding the value 0 257 | (Direct). When `stvec.MODE=Direct`, `stvec.BASE` must be capable of 258 | holding any valid four-byte-aligned address. 259 | 260 | - *Sstvala* `stval` must be written with the faulting virtual address 261 | for load, store, and instruction page-fault, access-fault, and 262 | misaligned exceptions, and for breakpoint exceptions other than 263 | those caused by execution of the `EBREAK` or `C.EBREAK` instructions. 264 | For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the 265 | faulting instruction. 266 | 267 | - *Sscounterenw* For any `hpmcounter` that is not read-only zero, the 268 | corresponding bit in `scounteren` must be writable. 269 | 270 | - *Svpbmt* Page-based memory types 271 | 272 | - *Svinval* Fine-grained address-translation cache invalidation. 273 | 274 | The following are new mandatory extensions: 275 | 276 | - *Svnapot* NAPOT translation contiguity. 277 | 278 | NOTE: Svnapot was optional in RVA22. 279 | 280 | - *Sstc* supervisor-mode timer interrupts. 281 | 282 | NOTE: Sstc was optional in RVA22. 283 | 284 | - *Sscofpmf* count overflow and mode-based filtering. 285 | 286 | - *Ssnpm* Pointer masking, with `senvcfg.PMM` and `henvcfg.PMM` supporting, 287 | at minimum, settings PMLEN=0 and PMLEN=7. 288 | 289 | - *Ssu64xl* `sstatus.UXL` must be capable of holding the value 2 290 | (i.e., UXLEN=64 must be supported). 291 | 292 | NOTE: Ssu64xl was optional in RVA22. 293 | 294 | 295 | - *Sha* The augmented hypervisor extension. 296 | 297 | NOTE: Sha is a new profile-defined extension that captures the 298 | full set of features that are mandated to be supported along with the 299 | H extension. There is no change to the features added by including 300 | the hypervisor extension in a profile--the new name is solely to 301 | simplify the text of the profiles. The definition has been added to 302 | the RVA22 profile text, where the hypervisor extension was first 303 | added, but will be added to the hypervisor section of the combined ISA 304 | manual. 305 | 306 | *Sha* comprises the following extensions: 307 | 308 | ** *H* The hypervisor extension. 309 | 310 | ** *Ssstateen* Supervisor-mode view of the state-enable extension. The 311 | supervisor-mode (`sstateen0-3`) and hypervisor-mode (`hstateen0-3`) 312 | state-enable registers must be provided. 313 | 314 | ** *Shcounterenw* For any `hpmcounter` that is not read-only zero, the corresponding bit in `hcounteren` must be writable. 315 | 316 | ** *Shvstvala* `vstval` must be written in all cases described above for `stval`. 317 | 318 | ** *Shtvala* `htval` must be written with the faulting guest physical 319 | address in all circumstances permitted by the ISA. 320 | 321 | ** *Shvstvecd* `vstvec.MODE` must be capable of holding the value 0 (Direct). 322 | When `vstvec.MODE`=Direct, `vstvec.BASE` must be capable of holding 323 | any valid four-byte-aligned address. 324 | 325 | ** *Shvsatpa* All translation modes supported in `satp` must be supported in `vsatp`. 326 | 327 | ** *Shgatpa* For each supported virtual memory scheme SvNN supported in 328 | `satp`, the corresponding hgatp SvNNx4 mode must be supported. The 329 | `hgatp` mode Bare must also be supported. 330 | 331 | NOTE: The augmented hypervisor extension (exactly equivalent to Sha) was optional in RVA22. 332 | 333 | ==== RVA23S64 Optional Extensions 334 | 335 | ===== Localized Options 336 | 337 | There are no privileged localized options in RVA23S64. 338 | 339 | ===== Development Options 340 | 341 | There are no privileged development options in RVA23S64. 342 | 343 | ===== Expansion Options 344 | 345 | The following privileged expansion options were present in RVA22S64: 346 | 347 | - *Sv48* Page-based 48-bit virtual-memory system. 348 | 349 | - *Sv57* Page-based 57-bit virtual-memory system. 350 | 351 | - *Zkr* Entropy CSR. 352 | 353 | The following are new privileged expansion options in RVA23S64 354 | 355 | - *Svadu* Hardware A/D bit updates. 356 | 357 | - *Sdtrig* Debug triggers. 358 | 359 | - *Ssstrict* No non-conforming extensions are present. Attempts to 360 | execute unimplemented opcodes or access unimplemented CSRs in the 361 | standard or reserved encoding spaces raises an illegal instruction 362 | exception that results in a contained trap to the supervisor-mode 363 | trap handler. 364 | 365 | NOTE: Ssstrict is a new profile-defined extension that restricts the 366 | behavior of reserved encoding spaces. The extension will be added to 367 | the supervisor chapter of the privileged architecture. 368 | 369 | NOTE: Ssstrict does not prescribe behavior for the custom encoding 370 | spaces or CSRs. 371 | 372 | NOTE: Ssstrict definition applies to the execution environment 373 | claiming to be RVA23-compatible, which must have the hypervisor 374 | extension. That execution environment will take a contained trap to 375 | supervisor-mode (however that trap is implemented, including, but not 376 | limited to, emulation/delegation in the outer execution 377 | environment). Ssstrict (and all the other RVA23 mandates and options) 378 | do not apply to any guest VMs run by a hypervisor. An RVA23 hypervisor 379 | can provide guest VMs that are also RVA23-compatible but with an 380 | expanded set of emulated standard instructions. An RVA23 hypervisor 381 | can also choose to implement guest VMs that are not RVA23 compatible 382 | (e.g., lacking H, or only RVA20). 383 | 384 | 385 | - *Svvptc* Transitions from invalid to valid PTEs will be visible in 386 | bounded time without an explicit memory-management fence. 387 | 388 | - *Sspm* Supervisor-mode pointer masking, with the supervisor execution 389 | environment providing a means to select PMLEN=0 and PMLEN=7 at minimum. 390 | 391 | ===== Transitory Options 392 | 393 | There are no privileged transitory options in RVA23S64. 394 | 395 | ==== RVA23S64 Recommendations 396 | 397 | - Implementations are strongly recommended to raise 398 | illegal-instruction exceptions when attempting to execute 399 | unimplemented opcodes or access unimplemented CSRs. 400 | 401 | == Glossary of ISA Extensions 402 | 403 | The following unprivileged ISA extensions are defined in Volume I 404 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 405 | 406 | - M Extension for Integer Multiplication and Division 407 | - A Extension for Atomic Instructions 408 | - F Extension for Single-Precision Floating-Point 409 | - D Extension for Double-Precision Floating-Point 410 | - H Hypervisor Extension 411 | - Q Extension for Quad-Precision Floating-Point 412 | - C Extension for Compressed Instructions 413 | - B Extension for Bit Manipulation 414 | - V Extension for Vector Computation 415 | - Zifencei Instruction-Fetch Fence Extension 416 | - Zicsr Extension for Control and Status Register Access 417 | - Zicntr Extension for Basic Performance Counters 418 | - Zihpm Extension for Hardware Performance Counters 419 | - Zihintpause Pause Hint Extension 420 | - Zfh Extension for Half-Precision Floating-Point 421 | - Zfhmin Minimal Extension for Half-Precision Floating-Point 422 | - Zfinx Extension for Single-Precision Floating-Point in x-registers 423 | - Zdinx Extension for Double-Precision Floating-Point in x-registers 424 | - Zhinx Extension for Half-Precision Floating-Point in x-registers 425 | - Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers 426 | - Zba Address Computation Extension 427 | - Zbb Bit Manipulation Extension 428 | - Zbc Carryless Multiplication Extension 429 | - Zbs Single-Bit Manipulation Extension 430 | - Zk Standard Scalar Cryptography Extension 431 | - Zkn NIST Cryptography Extension 432 | - Zknd AES Decryption Extension 433 | - Zkne AES Encryption Extension 434 | - Zknh SHA2 Hashing Extension 435 | - Zkr Entropy Source Extension 436 | - Zks ShangMi Cryptography Extension 437 | - Zksed SM4 Block Cypher Extension 438 | - Zksh SM3 Hashing Extension 439 | - Zkt Extension for Data-Independent Execution Latency 440 | - Zicbom Extension for Cache-Block Management 441 | - Zicbop Extension for Cache-Block Prefetching 442 | - Zicboz Extension for Cache-Block Zeroing 443 | - Zawrs Wait-on-reservation-set instructions 444 | - Zacas Extension for Atomic Compare-and-Swap (CAS) instructions 445 | - Zabha Extension for Byte and Halfword Atomic Memory Operations 446 | - Zbkb Extension for Bit Manipulation for Cryptography 447 | - Zbkc Extension for Carryless Multiplication for Cryptography 448 | - Zbkx Crossbar Permutation Extension 449 | - Zvbb - Vector Basic Bit-manipulation 450 | - Zvbc - Vector Carryless Multiplication 451 | - Zvkng - NIST Algorithm Suite with GCM 452 | - Zvksg - ShangMi Algorithm Suite with GCM 453 | - Zvkt - Vector Data-Independent Execution Latency 454 | 455 | The following privileged ISA extensions are defined in Volume II 456 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 457 | 458 | - Sv32 Page-based Virtual Memory Extension, 32-bit 459 | - Sv39 Page-based Virtual Memory Extension, 39-bit 460 | - Sv48 Page-based Virtual Memory Extension, 48-bit 461 | - Sv57 Page-based Virtual Memory Extension, 57-bit 462 | - Svpbmt, Page-Based Memory Types 463 | - Svnapot, NAPOT Translation Contiguity 464 | - Svinval, Fine-Grained Address-Translation Cache Invalidation 465 | - Hypervisor Extension 466 | - Sm1p11, Machine Architecture v1.11 467 | - Sm1p12, Machine Architecture v1.12 468 | - Ss1p11, Supervisor Architecture v1.11 469 | - Ss1p12, Supervisor Architecture v1.12 470 | - Ss1p13, Supervisor Architecture v1.13 471 | - Sstc Extension for Supervisor-mode Timer Interrupts 472 | - Sscofpmf Extension for Count Overflow and Mode-Based Filtering 473 | - Smstateen/Ssstateen Extension for State-enable 474 | - Svvptc Obviating Memory-management Instructions after Marking PTEs valid 475 | - Svadu Hardware Updating of A/D Bits 476 | 477 | The following extensions have not yet been incorporated into the RISC-V 478 | Instruction Set Manual; the hyperlinks lead to their separate specifications. 479 | 480 | - https://github.com/riscv/riscv-v-spec[Zve32x Extension for Embedded Vector Computation (32-bit integer)] 481 | - https://github.com/riscv/riscv-v-spec[Zve32f Extension for Embedded Vector Computation (32-bit integer, 32-bit FP)] 482 | - https://github.com/riscv/riscv-v-spec[Zve32d Extension for Embedded Vector Computation (32-bit integer, 64-bit FP)] 483 | - https://github.com/riscv/riscv-v-spec[Zve64x Extension for Embedded Vector Computation (64-bit integer)] 484 | - https://github.com/riscv/riscv-v-spec[Zve64f Extension for Embedded Vector Computation (64-bit integer, 32-bit FP)] 485 | - https://github.com/riscv/riscv-v-spec[Zve64d Extension for Embedded Vector Computation (64-bit integer, 64-bit FP)] 486 | 487 | - *Ziccif*: Main memory supports instruction fetch with atomicity requirement 488 | - *Ziccrse*: Main memory supports forward progress on LR/SC sequences 489 | - *Ziccamoa*: Main memory supports all atomics in A 490 | - *Ziccamoc* Main memory supports atomics in Zacas 491 | - *Zicclsm*: Main memory supports misaligned loads/stores 492 | - *Zama16b*: Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. 493 | - *Za64rs*: Reservation set size of at most 64 bytes 494 | - *Za128rs*: Reservation set size of at most 128 bytes 495 | - *Zic64b*: Cache block size is 64 bytes 496 | - *Svbare*: Bare mode virtual-memory translation supported 497 | - *Svade*: Raise exceptions on improper A/D bits 498 | - *Ssccptr*: Main memory supports page table reads 499 | - *Sscounterenw*: Support writeable enables for any supported counter 500 | - *Sstvecd*: `stvec` supports Direct mode 501 | - *Sstvala*: `stval` provides all needed values 502 | - *Ssu64xl*: UXLEN=64 must be supported 503 | - *Sha*: Augmented hypervisor extension 504 | - *Shcounterenw*: Support writeable enables for any supported counter 505 | - *Shvstvala*: `vstval` provides all needed values 506 | - *Shtvala*: `htval` provides all needed values 507 | - *Shvstvecd*: `vstvec` supports Direct mode 508 | - *Shvsatpa*: `vsatp` supports all modes supported by `satp` 509 | - *Shgatpa*: SvNNx4 mode supported for all modes supported by `satp`, as well as Bare 510 | - *Ssstrict*: Unimplemented reserved encodings raise illegal instruction exceptions and no non-conforming extension are present 511 | -------------------------------------------------------------------------------- /src/rvb23-profile.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-doc-template]] 2 | :description: Short, text description of spect… 3 | :company: RISC-V 4 | :url-riscv: http://riscv.org 5 | :doctype: book 6 | :colophon: 7 | :appendix-caption: Appendix 8 | :imagesdir: ../docs-resources/images 9 | :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center] 10 | // Settings: 11 | :experimental: 12 | :reproducible: 13 | :WaveDromEditorApp: wavedrom-cli 14 | :imagesoutdir: images 15 | :icons: font 16 | :lang: en 17 | :listing-caption: Listing 18 | :sectnums: 19 | :sectnumlevels: 5 20 | :toclevels: 5 21 | :toc: left 22 | :source-highlighter: pygments 23 | ifdef::backend-pdf[] 24 | :source-highlighter: coderay 25 | endif::[] 26 | :data-uri: 27 | :hide-uri-scheme: 28 | :stem: latexmath 29 | :footnote: 30 | :xrefstyle: short 31 | :numbered: 32 | :stem: latexmath 33 | :le: ≤ 34 | :ge: ≥ 35 | :ne: ≠ 36 | :approx: ≈ 37 | :inf: ∞ 38 | 39 | :sectnums!: 40 | 41 | = RVB23 Profiles 42 | 43 | == Introduction 44 | 45 | This document specifies the RVB23 profile 46 | family. RVB23 is the first major release of the RVB 47 | series of RISC-V Application Processor Profile. 48 | 49 | RVB profiles are intended to be used for customized 64-bit application 50 | processors that will run rich OS stacks, but usually as a custom build 51 | of standard OS source-code distributions. The approach is to provide 52 | a large guaranteed set of relatively inexpensive and/or widely 53 | beneficial features but allow optionality for more expensive and/or 54 | more targeted extensions. 55 | 56 | Unlike the RVA profiles, it is explicitly a non-goal of RVB profiles 57 | to provide a single standard ISA interface supporting a wide variety 58 | of binary kernel and binary application software distributions. 59 | However, individual software ecosystems may build upon RVB profiles to 60 | produce a more targeted standard interface for a certain market. 61 | 62 | == Profile-Defined Extensions 63 | 64 | RVB23 has been ratified alongside RVA23, and the same set of new 65 | profile-defined extensions defined in RVA23 are present in RVB23. 66 | These profile-defined extensions will soon move to the combined ISA manual. 67 | Future releases of RVA and RVB profiles might not 68 | proceed through ratification at the same time, and future 69 | profile-defined extensions will be presented as an edit to the 70 | combined ISA manual. 71 | 72 | == RVB23 Profiles 73 | 74 | Only user-mode (RVB23U64) and supervisor-mode (RVB23S64) profiles are 75 | specified in this family. 76 | 77 | === RVB23U64 Profile 78 | 79 | The RVB23U64 profile specifies the ISA features available to user-mode 80 | execution environments in 64-bit RVB applications processors. 81 | 82 | ==== RVB23U64 Mandatory Base 83 | 84 | RV64I is the mandatory base ISA for RVB23U64 and is little-endian. As 85 | per the unprivileged architecture specification, the `ECALL` 86 | instruction causes a requested trap to the execution environment. 87 | 88 | ==== RVB23U64 Mandatory Extensions 89 | 90 | The following mandatory extensions in RVB23U64 were also mandatory in 91 | RVA22U64. 92 | 93 | - *M* Integer multiplication and division. 94 | - *A* Atomic instructions. 95 | - *F* Single-precision floating-point instructions. 96 | - *D* Double-precision floating-point instructions. 97 | - *C* Compressed instructions. 98 | - *B* Bit-manipulation instructions. 99 | - *Zicsr* CSR instructions. These are implied by presence of F. 100 | - *Zicntr* Base counters and timers. 101 | - *Zihpm* Hardware performance counters. 102 | - *Ziccif* Main memory regions with both the cacheability and 103 | coherence PMAs must support instruction fetch, and any instruction 104 | fetches of naturally aligned power-of-2 sizes up to min(ILEN,XLEN) 105 | (i.e., 32 bits for RVB23) are atomic. 106 | - *Ziccrse* Main memory regions with both the cacheability and coherence PMAs must support RsrvEventual. 107 | - *Ziccamoa* Main memory regions with both the cacheability and coherence PMAs must support all atomics in A. 108 | - *Zicclsm* Misaligned loads and stores to main memory regions with both the 109 | cacheability and coherence PMAs must be supported. 110 | - *Za64rs* Reservation sets are contiguous, naturally aligned, and a 111 | maximum of 64 bytes. 112 | - *Zihintpause* Pause hint. 113 | - *Zic64b* Cache blocks must be 64 bytes in size, naturally aligned in the 114 | address space. 115 | - *Zicbom* Cache-block management instructions. 116 | - *Zicbop* Cache-block prefetch instructions. 117 | - *Zicboz* Cache-block zero instructions. 118 | - *Zkt* Data-independent execution latency. 119 | 120 | The following mandatory extensions are also present in RVA23U64: 121 | 122 | - *Zihintntl* Non-temporal locality hints. 123 | - *Zicond* Integer conditional operations. 124 | - *Zimop* May-be-operations. 125 | - *Zcmop* Compressed may-be-operations. 126 | - *Zcb* Additional compressed instructions. 127 | - *Zfa* Additional floating-point instructions. 128 | - *Zawrs* Wait-on-reservation-set instructions. 129 | 130 | ==== RVB23U64 Optional Extensions 131 | 132 | RVB23U64 has 18 profile options listed below. 133 | 134 | ===== Localized Options 135 | 136 | The following extensions are localized options in both RVA23U64 and RVB23U64: 137 | 138 | - *Zvkng* Vector crypto NIST Algorithms with GCM. 139 | - *Zvksg* Vector crypto ShangMi Algorithms with GCM. 140 | 141 | The following extensions options are localized options in RVB23U64 but 142 | are not present in RVA23U64: 143 | 144 | - *Zvkg* Vector GCM/GMAC instructions. 145 | - *Zvknc* Vector crypto NIST algorithms with carryless multiply. 146 | - *Zvksc* Vector crypto ShangMi algorithms with carryless multiply. 147 | 148 | NOTE: RVA profiles mandate the higher-performing but more expensive 149 | GHASH options when adding vector crypto. To reduce implementation cost, RVB 150 | profiles also allow these carryless multiply options (Zvknc and Zvksc) 151 | to implement GCM efficiently, with GHASH available as a separate 152 | option. 153 | 154 | - *Zkn* Scalar crypto NIST algorithms. 155 | - *Zks* Scalar crypto ShangMi algorithms. 156 | 157 | NOTE: RVA23 profiles drop support for scalar crypto as an option, as 158 | the vector extension is now mandatory in RVA23. RVB23 profiles 159 | support scalar crypto, as the vector extension is optional in RVB23. 160 | 161 | ===== Development Options 162 | 163 | The following are new development options intended to become mandatory in a later RVB profile: 164 | 165 | - *Zabha* Byte and halfword atomic memory operations. 166 | - *Zacas* Compare-and-Swap instructions. 167 | - *Ziccamoc* Main memory regions with both the cacheability and coherence PMAs 168 | must provide `AMOCASQ` level PMA support. 169 | - *Zama16b* Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. 170 | 171 | ===== Expansion Options 172 | 173 | The following are expansion options in RVB23U64, but are mandatory in 174 | RVA23U64. 175 | 176 | - *Zfhmin* Half-precision floating-point. 177 | 178 | - *V* Vector extension. 179 | 180 | NOTE: Unclear if other Zve* extensions should also be supported in RVB. 181 | 182 | - *Zvfhmin* Vector minimal half-precision floating-point. 183 | - *Zvbb* Vector basic bit-manipulation instructions. 184 | - *Zvkt* Vector data-independent execution latency. 185 | - *Supm* Pointer masking, with the execution environment providing a means to 186 | select PMLEN=0 and PMLEN=7 at minimum. 187 | 188 | The following extensions are expansion options in both RVA23U64 and RVB23U64: 189 | 190 | - *Zfh* Scalar half-precision floating-point. 191 | - *Zbc* Scalar carryless multiplication. 192 | - *Zicfilp* Landing Pads. 193 | - *Zicfiss* Shadow Stack. 194 | - *Zvfh* Vector half-precision floating-point. 195 | - *Zfbfmin* Scalar BF16 converts. 196 | - *Zvfbfmin* Vector BF16 converts. 197 | - *Zvfbfwma* Vector BF16 widening mul-add. 198 | 199 | The following are expansion options for RVB23U64 as they are not 200 | intended to be made mandatory in future RVB profiles, but are listed 201 | as RVA23U64 development options as they are intended to become 202 | mandatory in future RVA profiles. 203 | 204 | - *Zvbc* Vector carryless multiplication. 205 | 206 | ===== Transitory Options 207 | 208 | There are no transitory options in RVB23U64. 209 | 210 | ==== RVB23U64 Recommendations 211 | 212 | Implementations are strongly recommended to raise illegal-instruction 213 | exceptions on attempts to execute unimplemented opcodes. 214 | 215 | === RVB23S64 Profile 216 | 217 | The RVB23S64 profile specifies the ISA features available to a 218 | supervisor-mode execution environment in 64-bit applications 219 | processors. RVB23S64 is based on privileged architecture version 220 | 1.13. 221 | 222 | NOTE: Priv 1.13 is still being defined. 223 | 224 | ==== RVB23S64 Mandatory Base 225 | 226 | RV64I is the mandatory base ISA for RVB23S64 and is little-endian. 227 | The `ECALL` instruction operates as per the unprivileged architecture 228 | specification. An `ECALL` in user mode causes a contained trap to 229 | supervisor mode. An `ECALL` in supervisor mode causes a requested 230 | trap to the execution environment. 231 | 232 | ==== RVB23S64 Mandatory Extensions 233 | 234 | The following unprivileged extensions are mandatory: 235 | 236 | - The RVB23S64 mandatory unprivileged extensions include all the 237 | mandatory unprivileged extensions in RVB23U64. 238 | 239 | - *Zifencei* Instruction-Fetch Fence. 240 | 241 | NOTE: Zifencei is mandated as it is the only standard way to support 242 | instruction-cache coherence in RVB23 application processors. A new 243 | instruction-cache coherence mechanism is under development 244 | (tentatively named Zjid) which might be added as an option in the 245 | future. 246 | 247 | The following privileged extensions are mandatory, and are also 248 | mandatory in RVA23S64. 249 | 250 | - *Ss1p13* Supervisor architecture version 1.13. 251 | 252 | NOTE: Ss1p13 supersedes Ss1p12 but is not yet ratified. 253 | 254 | - *Svnapot* NAPOT translation contiguity. 255 | 256 | NOTE: Svnapot is very low cost to provide, so is made mandatory even 257 | in RVB. 258 | 259 | - *Svbare* The `satp` mode Bare must be supported. 260 | 261 | - *Sv39* Page-Based 39-bit Virtual-Memory System. 262 | 263 | - *Svade* Page-fault exceptions are raised when a page is accessed 264 | when A bit is clear, or written when D bit is clear. 265 | 266 | - *Ssccptr* Main memory regions with both the cacheability and 267 | coherence PMAs must support hardware page-table reads. 268 | 269 | - *Sstvecd* `stvec.MODE` must be capable of holding the value 0 270 | (Direct). When `stvec.MODE=Direct`, `stvec.BASE` must be capable of 271 | holding any valid four-byte-aligned address. 272 | 273 | - *Sstvala* `stval` must be written with the faulting virtual address 274 | for load, store, and instruction page-fault, access-fault, and 275 | misaligned exceptions, and for breakpoint exceptions other than 276 | those caused by execution of the `EBREAK` or `C.EBREAK` instructions. 277 | For virtual-instruction and illegal-instruction exceptions, `stval` must be written with the 278 | faulting instruction. 279 | 280 | - *Sscounterenw* For any `hpmcounter` that is not read-only zero, the 281 | corresponding bit in `scounteren` must be writable. 282 | 283 | - *Svpbmt* Page-based memory types. 284 | 285 | - *Svinval* Fine-grained address-translation cache invalidation. 286 | 287 | - *Sstc* supervisor-mode timer interrupts. 288 | 289 | - *Sscofpmf* Count overflow and mode-based filtering. 290 | 291 | - *Ssu64xl* `sstatus.UXL` must be capable of holding the value 2 292 | (i.e., UXLEN=64 must be supported). 293 | 294 | ==== RVB23S64 Optional Extensions 295 | 296 | RVB23S64 has the same unprivileged options as RVB23U64, 297 | 298 | The privileged options in RVB23S64 are listed in the following 299 | sections. 300 | 301 | ===== Localized Options 302 | 303 | There are no privileged localized options in RVB23S64. 304 | 305 | ===== Development Options 306 | 307 | There are no privileged development options in RVB23S64. 308 | 309 | ===== Expansion Options 310 | 311 | The following are privileged expansion options in RVB23S64, but are 312 | mandatory in RVA23S64: 313 | 314 | - *Ssnpm* Pointer masking, with `senvcfg.PMM` supporting at minimum, 315 | settings PMLEN=0 and PMLEN=7. 316 | 317 | - *Sha* The augmented hypervisor extension. 318 | 319 | When the hypervisor extension is implemented, the following are also mandatory: 320 | 321 | - If the hypervisor extension is implemented and pointer masking 322 | (Ssnpm) is supported then `henvcfg.PMM` must support at minimum, 323 | settings PMLEN=0 and PMLEN=7. 324 | 325 | The following are privileged expansion options in RVB23S64 that are 326 | also privileged expansion options in RVA23S64: 327 | 328 | - *Sv48* Page-based 48-bit virtual-memory system. 329 | 330 | - *Sv57* Page-based 57-bit virtual-memory system. 331 | 332 | - *Svadu* Hardware A/D bit updates. 333 | 334 | - *Zkr* Entropy CSR. 335 | 336 | - *Sdtrig* Debug triggers. 337 | 338 | - *Ssstrict* No non-conforming extensions are present. Attempts to 339 | execute unimplemented opcodes or access unimplemented CSRs in the 340 | standard or reserved encoding spaces raises an illegal instruction 341 | exception that results in a contained trap to the supervisor-mode 342 | trap handler. 343 | 344 | NOTE: Ssstrict does not prescribe behavior for the custom encoding 345 | spaces or CSRs. 346 | 347 | NOTE: Ssstrict definition applies to the execution environment 348 | claiming to be RVA23-compatible, which must have the hypervisor 349 | extension. That execution environment will take a contained trap to 350 | supervisor-mode (however that trap is implemented, including, but not 351 | limited to, emulation/delegation in the outer execution 352 | environment). Ssstrict (and all the other RVA23 mandates and options) 353 | do not apply to any guest VMs run by a hypervisor. An RVA23 hypervisor 354 | can provide guest VMs that are also RVA23-compatible but with an 355 | expanded set of emulated standard instructions. An RVA23 hypervisor 356 | can also choose to implement guest VMs that are not RVA23 compatible 357 | (e.g., lacking H, or only RVA20). 358 | 359 | - *Svvptc* Transitions from invalid to valid PTEs will be visible in 360 | bounded time without an explicit memory-management fence. 361 | 362 | - *Sspm* Supervisor-mode pointer masking, with the supervisor execution 363 | environment providing a means to select PMLEN=0 and PMLEN=7 at minimum. 364 | 365 | ==== RVB23S64 Recommendations 366 | 367 | - Implementations are strongly recommended to raise illegal-instruction 368 | exceptions when attempting to execute unimplemented opcodes. 369 | 370 | == Glossary of ISA Extensions 371 | 372 | The following unprivileged ISA extensions are defined in Volume I 373 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 374 | 375 | - M Extension for Integer Multiplication and Division 376 | - A Extension for Atomic Memory Instructions 377 | - F Extension for Single-Precision Floating-Point 378 | - D Extension for Double-Precision Floating-Point 379 | - H Hypervisor Extension 380 | - Q Extension for Quad-Precision Floating-Point 381 | - C Extension for Compressed Instructions 382 | - B Extension for Bit Manipulation 383 | - V Extension for Vector Computation 384 | - Zifencei Instruction-Fetch Fence Extension 385 | - Zicsr Extension for Control and Status Register Access 386 | - Zicntr Extension for Basic Performance Counters 387 | - Zihpm Extension for Hardware Performance Counters 388 | - Zihintpause Pause Hint Extension 389 | - Zfh Extension for Half-Precision Floating-Point 390 | - Zfhmin Minimal Extension for Half-Precision Floating-Point 391 | - Zfinx Extension for Single-Precision Floating-Point in x-registers 392 | - Zdinx Extension for Double-Precision Floating-Point in x-registers 393 | - Zhinx Extension for Half-Precision Floating-Point in x-registers 394 | - Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers 395 | 396 | - Zba Address Computation Extension 397 | - Zbb Bit Manipulation Extension 398 | - Zbc Carryless Multiplication Extension 399 | - Zbs Single-Bit Manipulation Extension 400 | - Zk Standard Scalar Cryptography Extension 401 | - Zkn NIST Cryptography Extension 402 | - Zknd AES Decryption Extension 403 | - Zkne AES Encryption Extension 404 | - Zknh SHA2 Hashing Extension 405 | - Zkr Entropy Source Extension 406 | - Zks ShangMi Cryptography Extension 407 | - Zksed SM4 Block Cypher Extension 408 | - Zksh SM3 Hashing Extension 409 | - Zkt Extension for Data-Independent Execution Latency 410 | - Zicbom Extension for Cache-Block Management 411 | - Zicbop Extension for Cache-Block Prefetching 412 | - Zicboz Extension for Cache-Block Zeroing 413 | - Zawrs Wait-on-reservation-set instructions 414 | - Zacas Extension for Atomic Compare-and-Swap (CAS) instructions 415 | - Zabha Extension for Byte and Halfword Atomic Memory Operations 416 | - Zbkb Extension for Bit Manipulation for Cryptography 417 | - Zbkc Extension for Carryless Multiplication for Cryptography 418 | - Zbkx Crossbar Permutation Extension 419 | - Zvbb - Vector Basic Bit-manipulation 420 | - Zvbc - Vector Carryless Multiplication 421 | - Zvkng - NIST Algorithm Suite with GCM 422 | - Zvksg - ShangMi Algorithm Suite with GCM 423 | - Zvkt - Vector Data-Independent Execution Latency 424 | 425 | The following privileged ISA extensions are defined in Volume II 426 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 427 | 428 | - Sv32 Page-based Virtual Memory Extension, 32-bit 429 | - Sv39 Page-based Virtual Memory Extension, 39-bit 430 | - Sv48 Page-based Virtual Memory Extension, 48-bit 431 | - Sv57 Page-based Virtual Memory Extension, 57-bit 432 | - Svpbmt, Page-Based Memory Types 433 | - Svnapot, NAPOT Translation Contiguity 434 | - Svinval, Fine-Grained Address-Translation Cache Invalidation 435 | - Hypervisor Extension 436 | - Sm1p11, Machine Architecture v1.11 437 | - Sm1p12, Machine Architecture v1.12 438 | - Ss1p11, Supervisor Architecture v1.11 439 | - Ss1p12, Supervisor Architecture v1.12 440 | - Ss1p13, Supervisor Architecture v1.13 441 | - Sstc Extension for Supervisor-mode Timer Interrupts 442 | - Sscofpmf Extension for Count Overflow and Mode-Based Filtering 443 | - Smstateen/Ssstateen Extension for State-enable 444 | - Svvptc Obviating Memory-management Instructions after Marking PTEs valid 445 | - Svadu Hardware Updating of A/D Bits 446 | 447 | The following extensions have not yet been incorporated into the RISC-V 448 | Instruction Set Manual; the hyperlinks lead to their separate specifications. 449 | 450 | - https://github.com/riscv/riscv-v-spec[Zve32x Extension for Embedded Vector Computation (32-bit integer)] 451 | - https://github.com/riscv/riscv-v-spec[Zve32f Extension for Embedded Vector Computation (32-bit integer, 32-bit FP)] 452 | - https://github.com/riscv/riscv-v-spec[Zve32d Extension for Embedded Vector Computation (32-bit integer, 64-bit FP)] 453 | - https://github.com/riscv/riscv-v-spec[Zve64x Extension for Embedded Vector Computation (64-bit integer)] 454 | - https://github.com/riscv/riscv-v-spec[Zve64f Extension for Embedded Vector Computation (64-bit integer, 32-bit FP)] 455 | - https://github.com/riscv/riscv-v-spec[Zve64d Extension for Embedded Vector Computation (64-bit integer, 64-bit FP)] 456 | 457 | - *Ziccif*: Main memory supports instruction fetch with atomicity requirement 458 | - *Ziccrse*: Main memory supports forward progress on LR/SC sequences 459 | - *Ziccamoa*: Main memory supports all atomics in A 460 | - *Ziccamoc* Main memory supports atomics in Zacas 461 | - *Zicclsm*: Main memory supports misaligned loads/stores 462 | - *Zama16b*: Misaligned loads, stores, and AMOs to main memory regions that do not cross a naturally aligned 16-byte boundary are atomic. 463 | - *Za64rs*: Reservation set size of at most 64 bytes 464 | - *Za128rs*: Reservation set size of at most 128 bytes 465 | - *Zic64b*: Cache block size is 64 bytes 466 | - *Svbare*: Bare mode virtual-memory translation supported 467 | - *Svade*: Raise exceptions on improper A/D bits 468 | - *Ssccptr*: Main memory supports page table reads 469 | - *Sscounterenw*: Support writeable enables for any supported counter 470 | - *Sstvecd*: `stvec` supports Direct mode 471 | - *Sstvala*: `stval` provides all needed values 472 | - *Ssu64xl*: UXLEN=64 must be supported 473 | - *Sha*: Augmented hypervisor extension 474 | - *Shcounterenw*: Support writeable enables for any supported counter 475 | - *Shvstvala*: `vstval` provides all needed values 476 | - *Shtvala*: `htval` provides all needed values 477 | - *Shvstvecd*: `vstvec` supports Direct mode 478 | - *Shvsatpa*: `vsatp` supports all modes supported by `satp` 479 | - *Shgatpa*: SvNNx4 mode supported for all modes supported by `satp`, as well as Bare 480 | - *Ssstrict*: Unimplemented reserved encodings raise illegal instruction exceptions and no non-conforming extension are present 481 | -------------------------------------------------------------------------------- /src/rvm23-profile.adoc: -------------------------------------------------------------------------------- 1 | [[riscv-doc-template]] 2 | :description: Short, text description of spect… 3 | :company: RISC-V 4 | :revdate: May 11, 2023 5 | :revnumber: 0.1-draft 6 | :revremark: This document is in Development stage. Everything could change before ratification. 7 | :url-riscv: http://riscv.org 8 | :doctype: book 9 | :preface-title: Preamble 10 | :colophon: 11 | :appendix-caption: Appendix 12 | :imagesdir: ../docs-resources/images 13 | :title-logo-image: image:risc-v_logo.png["RISC-V International Logo",pdfwidth=3.25in,align=center] 14 | // Settings: 15 | :experimental: 16 | :reproducible: 17 | :WaveDromEditorApp: wavedrom-cli 18 | :imagesoutdir: images 19 | :icons: font 20 | :lang: en 21 | :listing-caption: Listing 22 | :sectnums: 23 | :sectnumlevels: 5 24 | :toclevels: 5 25 | :toc: left 26 | :source-highlighter: pygments 27 | ifdef::backend-pdf[] 28 | :source-highlighter: coderay 29 | endif::[] 30 | :data-uri: 31 | :hide-uri-scheme: 32 | :stem: latexmath 33 | :footnote: 34 | :xrefstyle: short 35 | :numbered: 36 | :stem: latexmath 37 | :le: ≤ 38 | :ge: ≥ 39 | :ne: ≠ 40 | :approx: ≈ 41 | :inf: ∞ 42 | 43 | :sectnums!: 44 | 45 | = RVM23 Profiles 46 | 47 | //: This is the Preamble 48 | 49 | [WARNING] 50 | .This document is in the development state. 51 | ==== 52 | Do not use for implementations. Assume everything can change. 53 | ==== 54 | 55 | :sectnums!: 56 | 57 | == Initial draft version, in progress 58 | 59 | :sectnums: 60 | 61 | == RVM23 Profiles 62 | 63 | The RVM23 profile is intended for microcontrollers, with the goal of 64 | simplifying the demands on the software ecosystem particularly 65 | toolchains and library suppliers. 66 | 67 | The RVM23 profile only specifies unprivileged ISA features. ISA 68 | features related to interrupt and exception handling or privileged 69 | execution are not included as these are often highly 70 | platform-specific. The separate RVM-CSI effort is tackling 71 | source-code level portability for certain platform-level features. 72 | 73 | A non-goal of RVM23 is to provide maximum flexibility for 74 | microcontroller developers. Maximum flexibility can already be 75 | achieved using individual RISC-V extensions. The goal of RVM23 is 76 | mandate a common set of standard extensions to simplify software 77 | support. 78 | 79 | === RVM23U32 80 | 81 | RVM23U32 corresponds to a 32-bit address-space microcontroller. 82 | 83 | NOTE: Initially only 32b RVM profiles are defined, but a corresponding 84 | RVM64 profile can also be developed. 85 | 86 | ==== RVM23U32 Mandatory Base 87 | 88 | RV32I is the mandatory base ISA for RVM23U32, and is little-endian. 89 | 90 | NOTE: A separate RV32ME profile uses RV32E as the base ISA. 91 | 92 | As per the unprivileged architecture specification, the `ecall` 93 | instruction causes a requested trap to the execution environment. 94 | 95 | Misaligned loads and stores might not be supported. 96 | 97 | NOTE: Software should not assume that misaligned loads and stores will 98 | work, or that all misaligned loads and stores will necessarily cause a 99 | trap. 100 | 101 | ==== RVM23U32 Mandatory Extensions 102 | 103 | - *M* Integer multiplication and division. 104 | 105 | NOTE: Mandating divide instructions versus only multiplies (Zmmul) is likely 106 | controversial, but RVM is not intended for the smallest possible 107 | microcontrollers, and including divide instructions reduces 108 | optionality. 109 | 110 | - *B* Bit-manipulation instructions. 111 | 112 | - *Zicond* Conditional Zeroing instructions. 113 | 114 | - *Zihintpause* 115 | 116 | NOTE: These are hints, so implementations are allowed to treat as NOPs. 117 | 118 | - *Zihintntl* 119 | 120 | NOTE: These are hints, so implementations are allowed to treat as NOPs. 121 | 122 | - *Zce* Code size extension. The `jvt` CSR must be writable and 123 | support the jump table mode. 124 | 125 | NOTE: Zce includes Zicsr. Whether and what support is mandated for 126 | `jvt` in the profile is a topic for discussion. 127 | 128 | - *Zicbop* Cache-Block Prefetch Operations. 129 | 130 | NOTE: These are hints, so implementations are allowed to treat as NOPs. 131 | 132 | - *Zimop* Maybe-Operations 133 | - *Zcmop* Compressed Maybe-Operations 134 | 135 | NOTE: Implementations can simply write zero to the destination register (for 136 | Zimop) or treat as a NOP (for Zcmop), unless these instructions' behavior is 137 | overridden by another extension. 138 | 139 | ==== RVM23U32 Optional Extensions 140 | 141 | - *Zaamo* Atomic instructions. 142 | 143 | NOTE: Many microcontroller systems will not have caches and so will 144 | not naturally be able to support `Zalrsc`. 145 | 146 | - *A* Atomic instructions. 147 | 148 | NOTE: The assumption is that if Zalrsc is implemented on a 149 | microcontroller, then Zaamo will also be implemented, so we do not 150 | make Zalrsc available as a separate option. 151 | 152 | - *F* Single-precision floating-point instructions. 153 | 154 | NOTE: This profile does not support Zfinx and related options. A 155 | similar set of profiles, tentatively named RVN, would define Zfinx 156 | systems. 157 | 158 | - *D* Double-precision floating-point instructions. 159 | 160 | - *V* Vector Extension. 161 | 162 | - *P* Packed-SIMD Extension 163 | 164 | NOTE: The P extension has not yet been frozen or ratified. 165 | 166 | - *Zawrs* Wait on reservation set. 167 | 168 | NOTE: Zawrs includes Zalrsc. 169 | 170 | - *Zifencei* Instruction-fetch fence instruction. 171 | 172 | NOTE: Zifencei is only an option because how instruction-cache 173 | coherence is maintained is considered a platform issue for 174 | microcontrollers. 175 | 176 | - Misaligned loads and stores may be supported. 177 | 178 | - *Zicntr* Basic counters. 179 | 180 | - *Zihpm* Hardware performance counters. 181 | 182 | - *Zicbom* Cache-Block Management Operations. 183 | - *Zicboz* Cache-Block Zero Operations. 184 | 185 | - *Zicfisslp* Shadow-stack and landing pads. 186 | 187 | - *Zkt* Data-independent execution time. 188 | 189 | - *Zfa* Additional scalar FP instructions. 190 | 191 | - *Zfhmin* Half-Precision Floating-point transfer and convert. 192 | 193 | - *Zfh* Half-precision floating-point instructions. 194 | 195 | - *Zfbfmin* Scalar BF16 FP conversions. 196 | - *Zvfbfmin* Vector BF16 FP conversions. 197 | - *Zvfbfwma* Vector BF16 widening mul-add. 198 | 199 | - *Zbc* Scalar carryless multiply. 200 | 201 | - *Zve32x* 202 | - *Zve32f* 203 | - *Zve64x* 204 | - *Zve64f* 205 | - *Zve64d* 206 | - *Zvfhmin* Vector half-precision floating-point conversion instructions 207 | - *Zvfh* Vector half-precision floating-point instructions. 208 | 209 | - *Zkn* Scalar Crypto NIST Algorithms. 210 | - *Zks* Scalar Crypto ShangMi Algorithms. 211 | - *Zkr* Entropy CSR. 212 | 213 | - *Zvkng* Vector Crypto NIST Algorithms including GHASH. 214 | - *Zvksg* Vector Crypto ShangMi Algorithms including GHASH. 215 | 216 | - *Zvbb* Vector bitmanip extension. 217 | - *Zvbc* Vector carryless multiply. 218 | 219 | - *Zvkg* Vector GHASH instructions 220 | - *Zvkn* Vector Crypto NIST Algorithms 221 | - *Zvks* Vector Crypto ShangMi Algorithms 222 | 223 | but where either of Zvkn or Zvks is implemented, either Zvbc or Zvkg 224 | must also be implemented. 225 | 226 | NOTE: Should probably define new Zvknc and Zvksc extensions to 227 | represent Zvknn + Zvbc and Zvsn + Zvbc respectively. 228 | 229 | == Glossary of ISA Extensions 230 | 231 | The following unprivileged ISA extensions are defined in Volume I 232 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 233 | 234 | - M Extension for Integer Multiplication and Division 235 | - A Extension for Atomic Memory Operations 236 | - F Extension for Single-Precision Floating-Point 237 | - D Extension for Double-Precision Floating-Point 238 | - Q Extension for Quad-Precision Floating-Point 239 | - C Extension for Compressed Instructions 240 | - Zifencei Instruction-Fetch Synchronization Extension 241 | - Zicsr Extension for Control and Status Register Access 242 | - Zicntr Extension for Basic Performance Counters 243 | - Zihpm Extension for Hardware Performance Counters 244 | - Zihintpause Pause Hint Extension 245 | - Zfh Extension for Half-Precision Floating-Point 246 | - Zfhmin Minimal Extension for Half-Precision Floating-Point 247 | - Zfinx Extension for Single-Precision Floating-Point in x-registers 248 | - Zdinx Extension for Double-Precision Floating-Point in x-registers 249 | - Zhinx Extension for Half-Precision Floating-Point in x-registers 250 | - Zhinxmin Minimal Extension for Half-Precision Floating-Point in x-registers 251 | 252 | The following privileged ISA extensions are defined in Volume II 253 | of the https://github.com/riscv/riscv-isa-manual[RISC-V Instruction Set Manual]. 254 | 255 | - Sv32 Page-based Virtual Memory Extension, 32-bit 256 | - Sv39 Page-based Virtual Memory Extension, 39-bit 257 | - Sv48 Page-based Virtual Memory Extension, 48-bit 258 | - Sv57 Page-based Virtual Memory Extension, 57-bit 259 | - Svpbmt, Page-Based Memory Types 260 | - Svnapot, NAPOT Translation Contiguity 261 | - Svinval, Fine-Grained Address-Translation Cache Invalidation 262 | - Hypervisor Extension 263 | - Sm1p11, Machine Architecture v1.11 264 | - Sm1p12, Machine Architecture v1.12 265 | - Ss1p11, Supervisor Architecture v1.11 266 | - Ss1p12, Supervisor Architecture v1.12 267 | - Ss1p13, Supervisor Architecture v1.13 268 | 269 | The following extensions have not yet been incorporated into the RISC-V 270 | Instruction Set Manual; the hyperlinks lead to their separate specifications. 271 | 272 | - https://github.com/riscv/riscv-bitmanip[Zba Address Computation Extension] 273 | - https://github.com/riscv/riscv-bitmanip[Zbb Bit Manipulation Extension] 274 | - https://github.com/riscv/riscv-bitmanip[Zbc Carryless Multiplication Extension] 275 | - https://github.com/riscv/riscv-bitmanip[Zbs Single-Bit Manipulation Extension] 276 | - https://github.com/riscv/riscv-crypto[Zbkb Extension for Bit Manipulation for Cryptography] 277 | - https://github.com/riscv/riscv-crypto[Zbkc Extension for Carryless Multiplication for Cryptography] 278 | - https://github.com/riscv/riscv-crypto[Zbkx Crossbar Permutation Extension] 279 | - https://github.com/riscv/riscv-crypto[Zk Standard Scalar Cryptography Extension] 280 | - https://github.com/riscv/riscv-crypto[Zkn NIST Cryptography Extension] 281 | - https://github.com/riscv/riscv-crypto[Zknd AES Decryption Extension] 282 | - https://github.com/riscv/riscv-crypto[Zkne AES Encryption Extension] 283 | - https://github.com/riscv/riscv-crypto[Zknh SHA2 Hashing Extension] 284 | - https://github.com/riscv/riscv-crypto[Zkr Entropy Source Extension] 285 | - https://github.com/riscv/riscv-crypto[Zks ShangMi Cryptography Extension] 286 | - https://github.com/riscv/riscv-crypto[Zksed SM4 Block Cypher Extension] 287 | - https://github.com/riscv/riscv-crypto[Zksh SM3 Hashing Extension] 288 | - https://github.com/riscv/riscv-crypto[Zkt Extension for Data-Independent Execution Latency] 289 | - https://github.com/riscv/riscv-v-spec[V Extension for Vector Computation] 290 | - https://github.com/riscv/riscv-v-spec[Zve32x Extension for Embedded Vector Computation (32-bit integer)] 291 | - https://github.com/riscv/riscv-v-spec[Zve32f Extension for Embedded Vector Computation (32-bit integer, 32-bit FP)] 292 | - https://github.com/riscv/riscv-v-spec[Zve32d Extension for Embedded Vector Computation (32-bit integer, 64-bit FP)] 293 | - https://github.com/riscv/riscv-v-spec[Zve64x Extension for Embedded Vector Computation (64-bit integer)] 294 | - https://github.com/riscv/riscv-v-spec[Zve64f Extension for Embedded Vector Computation (64-bit integer, 32-bit FP)] 295 | - https://github.com/riscv/riscv-v-spec[Zve64d Extension for Embedded Vector Computation (64-bit integer, 64-bit FP)] 296 | - https://github.com/riscv/riscv-CMOs[Zicbom Extension for Cache-Block Management] 297 | - https://github.com/riscv/riscv-CMOs[Zicbop Extension for Cache-Block Prefetching] 298 | - https://github.com/riscv/riscv-CMOs[Zicboz Extension for Cache-Block Zeroing] 299 | - https://github.com/riscv/riscv-time-compare[Sstc Extension for Supervisor-mode Timer Interrupts] 300 | - https://github.com/riscv/riscv-count-overflow[Sscofpmf Extension for Count Overflow and Mode-Based Filtering] 301 | - https://github.com/riscv/riscv-state-enable[Smstateen Extension for State-enable] 302 | 303 | - *Ziccif*: Main memory supports instruction fetch with atomicity requirement 304 | - *Ziccrse*: Main memory supports forward progress on LR/SC sequences 305 | - *Ziccamoa*: Main memory supports all atomics in A 306 | - *Zicclsm*: Main memory supports misaligned loads/stores 307 | - *Za64rs*: Reservation set size of at most 64 bytes 308 | - *Za128rs*: Reservation set size of at most 128 bytes 309 | - *Zic64b*: Cache block size is 64 bytes 310 | - *Svbare*: Bare mode virtual-memory translation supported 311 | - *Svade*: Raise exceptions on improper A/D bits 312 | - *Ssccptr*: Main memory supports page table reads 313 | - *Sscounterenw*: Support writeable enables for any supported counter 314 | - *Sstvecd*: `stvec` supports Direct mode 315 | - *Sstvala*: `stval` provides all needed values 316 | - *Ssu64xl*: UXLEN=64 must be supported 317 | - *Ssstateen*: Supervisor-mode view of the state-enable extension 318 | - *Shcounterenw*: Support writeable enables for any supported counter 319 | - *Shvstvala*: `vstval` provides all needed values 320 | - *Shtvala*: `htval` provides all needed values 321 | - *Shvstvecd*: `vstvec` supports Direct mode 322 | - *Shvsatpa*: `vsatp` supports all modes supported by `satp` 323 | - *Shgatpa*: SvNNx4 mode supported for all modes supported by `satp`, as well as Bare 324 | --------------------------------------------------------------------------------