├── .gitignore ├── App_Common.cpp ├── App_Common.h ├── CoPro_Cmds.cpp ├── CoPro_Cmds.h ├── Gpu.h ├── Gpu_Hal.cpp ├── Gpu_Hal.h ├── Hal_Utils.cpp ├── Hal_Utils.h ├── Platform.h ├── README.md ├── Riverdi_Modules.h └── riverdi-eve-arduino.ino /.gitignore: -------------------------------------------------------------------------------- 1 | riverdi-demo 2 | *.bin 3 | *.hex 4 | *.elf 5 | *.map 6 | *.o 7 | tags 8 | -------------------------------------------------------------------------------- /App_Common.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) Bridgetek Pte Ltd 4 | Copyright (c) Riverdi Sp. z o.o. sp. k. 5 | Copyright (c) Lukasz Skalski 6 | 7 | THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 8 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 9 | OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 10 | BRIDGETEK PTE LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 11 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 12 | OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) 13 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 14 | TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 15 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | 17 | BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON BRIDGETEK PARTS. 18 | 19 | BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE INFORMATION IS NOT MODIFIED. 20 | 21 | IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, IT IS THE 22 | RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES AND SUBSEQUENT WHQL 23 | RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 24 | 25 | Abstract: 26 | 27 | Application to demonstrate function of EVE. 28 | 29 | Author : Bridgetek 30 | 31 | Revision History: 32 | 0.1 - date 2017.03.24 - Initial version 33 | */ 34 | 35 | #include "Platform.h" 36 | #include "App_Common.h" 37 | 38 | /************************************************************************************************* 39 | * These functions work with FT8XX GPU buffer 40 | **************************************************************************************************/ 41 | 42 | uint32_t CmdBuffer_Index; 43 | volatile uint32_t DlBuffer_Index; 44 | 45 | #ifdef BUFFER_OPTIMIZATION 46 | uint8_t DlBuffer[DL_SIZE]; 47 | uint8_t CmdBuffer[CMD_FIFO_SIZE]; 48 | #endif 49 | 50 | void App_WrCoCmd_Buffer(Gpu_Hal_Context_t *phost,uint32_t cmd) 51 | { 52 | #ifdef BUFFER_OPTIMIZATION 53 | /* Copy the command instruction into buffer */ 54 | uint32_t *pBuffcmd; 55 | /* Prevent buffer overflow */ 56 | if (CmdBuffer_Index >= CMD_FIFO_SIZE) 57 | { 58 | //printf("CmdBuffer overflow\n"); 59 | 60 | if (CmdBuffer_Index > 0) { 61 | Gpu_Hal_WrCmdBuf_nowait(phost, CmdBuffer, CmdBuffer_Index); 62 | } 63 | CmdBuffer_Index = 0; 64 | } 65 | 66 | pBuffcmd = (uint32_t*)&CmdBuffer[CmdBuffer_Index]; 67 | *pBuffcmd = cmd; 68 | 69 | 70 | #endif 71 | 72 | #if defined (STM32_PLATFORM) || defined (ARDUINO_PLATFORM) 73 | Gpu_Hal_WrCmd32(phost,cmd); 74 | #endif 75 | /* Increment the command index */ 76 | CmdBuffer_Index += CMD_SIZE; 77 | } 78 | 79 | void App_WrDl_Buffer(Gpu_Hal_Context_t *phost,uint32_t cmd) 80 | { 81 | #ifdef BUFFER_OPTIMIZATION 82 | /* Copy the command instruction into buffer */ 83 | uint32_t *pBuffcmd; 84 | /* Prevent buffer overflow */ 85 | if (DlBuffer_Index < DL_SIZE) 86 | { 87 | pBuffcmd = (uint32_t*)&DlBuffer[DlBuffer_Index]; 88 | *pBuffcmd = cmd; 89 | } 90 | else 91 | { 92 | printf("DlBuffer overflow\n"); 93 | } 94 | 95 | #endif 96 | 97 | #if defined (STM32_PLATFORM) || defined (ARDUINO_PLATFORM) 98 | Gpu_Hal_Wr32(phost,(RAM_DL+DlBuffer_Index),cmd); 99 | #endif 100 | /* Increment the command index */ 101 | DlBuffer_Index += CMD_SIZE; 102 | } 103 | 104 | void App_WrCoStr_Buffer(Gpu_Hal_Context_t *phost,const char8_t *s) 105 | { 106 | #ifdef BUFFER_OPTIMIZATION 107 | uint16_t length = 0; 108 | 109 | if (CmdBuffer_Index >= CMD_FIFO_SIZE) 110 | { 111 | printf("CmdBuffer overflow\n"); 112 | 113 | if (CmdBuffer_Index > 0) { 114 | Gpu_Hal_WrCmdBuf(phost, CmdBuffer, CmdBuffer_Index);//This blocking state may be infinite due to Display list overflow 115 | } 116 | CmdBuffer_Index = 0; 117 | } 118 | 119 | 120 | length = strlen(s) + 1;//last for the null termination 121 | 122 | strcpy((char*)&CmdBuffer[CmdBuffer_Index],s); 123 | 124 | /* increment the length and align it by 4 bytes */ 125 | CmdBuffer_Index += ((length + 3) & ~3); 126 | #endif 127 | } 128 | 129 | void App_Flush_DL_Buffer(Gpu_Hal_Context_t *phost) 130 | { 131 | #ifdef BUFFER_OPTIMIZATION 132 | if (DlBuffer_Index> 0) 133 | Gpu_Hal_WrMem(phost,RAM_DL,DlBuffer,DlBuffer_Index); 134 | #endif 135 | DlBuffer_Index = 0; 136 | } 137 | 138 | void App_Flush_Co_Buffer(Gpu_Hal_Context_t *phost) 139 | { 140 | #ifdef BUFFER_OPTIMIZATION 141 | if (CmdBuffer_Index > 0) 142 | Gpu_Hal_WrCmdBuf(phost,CmdBuffer,CmdBuffer_Index); 143 | #endif 144 | CmdBuffer_Index = 0; 145 | } 146 | 147 | void App_Flush_Co_Buffer_nowait(Gpu_Hal_Context_t *phost) 148 | { 149 | #ifdef BUFFER_OPTIMIZATION 150 | if (CmdBuffer_Index > 0) 151 | Gpu_Hal_WrCmdBuf_nowait(phost, CmdBuffer, CmdBuffer_Index); 152 | #endif 153 | CmdBuffer_Index = 0; 154 | } 155 | 156 | void App_Set_DlBuffer_Index(uint32_t index) 157 | { 158 | DlBuffer_Index = index; 159 | } 160 | 161 | void App_Set_CmdBuffer_Index(uint32_t index) 162 | { 163 | CmdBuffer_Index = index; 164 | } 165 | /************************************************************************************************* 166 | * Application Utilities 167 | **************************************************************************************************/ 168 | 169 | static uint8_t sk=0; 170 | uint8_t App_Read_Tag(Gpu_Hal_Context_t *phost) 171 | { 172 | static uint8_t Read_tag=0,temp_tag=0,ret_tag=0; 173 | Read_tag = Gpu_Hal_Rd8(phost,REG_TOUCH_TAG); 174 | ret_tag = 0; 175 | if(Read_tag!=0) // Allow if the Key is released 176 | { 177 | if(temp_tag!=Read_tag) 178 | { 179 | temp_tag = Read_tag; 180 | sk = Read_tag; // Load the Read tag to temp variable 181 | } 182 | } 183 | else 184 | { 185 | if(temp_tag!=0) 186 | { 187 | ret_tag = temp_tag; 188 | temp_tag = 0; //The event will be processed. Clear the tag 189 | } 190 | sk = 0; 191 | } 192 | return ret_tag; 193 | } 194 | 195 | uint8_t App_Touch_Update(Gpu_Hal_Context_t *phost, uint8_t *currTag, uint16_t *x, uint16_t *y) 196 | { 197 | static uint8_t Read_tag = 0, temp_tag = 0, ret_tag = 0; 198 | uint32_t touch; 199 | Read_tag = Gpu_Hal_Rd8(phost, REG_TOUCH_TAG); 200 | ret_tag = 0; 201 | if (Read_tag != 0) // Allow if the Key is released 202 | { 203 | if (temp_tag != Read_tag) 204 | { 205 | temp_tag = Read_tag; 206 | sk = Read_tag; // Load the Read tag to temp variable 207 | } 208 | } 209 | else 210 | { 211 | if (temp_tag != 0) 212 | { 213 | ret_tag = temp_tag; 214 | temp_tag = 0; //The event will be processed. Clear the tag 215 | } 216 | sk = 0; 217 | } 218 | *currTag = Read_tag; 219 | touch = Gpu_Hal_Rd32(phost, REG_TOUCH_SCREEN_XY); 220 | *x = (uint16_t)(touch >> 16); 221 | *y = (uint16_t)(touch & 0xFFFF); 222 | return ret_tag; 223 | } 224 | void App_Play_Sound(Gpu_Hal_Context_t *phost, uint8_t sound,uint8_t vol,uint8_t midi) 225 | { 226 | uint16_t val = (midi << 8) | sound; 227 | Gpu_Hal_Wr8(phost,REG_VOL_SOUND,vol); 228 | Gpu_Hal_Wr16(phost,REG_SOUND,val); 229 | Gpu_Hal_Wr8(phost,REG_PLAY,1); 230 | } 231 | 232 | 233 | void App_Calibrate_Screen(Gpu_Hal_Context_t *phost) 234 | { 235 | Gpu_CoCmd_Dlstart(phost); 236 | App_WrCoCmd_Buffer(phost,CLEAR(1,1,1)); 237 | App_WrCoCmd_Buffer(phost,COLOR_RGB(255,255,255)); 238 | Gpu_CoCmd_Text(phost,DispWidth/2,DispHeight/2,26,OPT_CENTERX|OPT_CENTERY,"Please tap on a dot"); 239 | 240 | /* Calibration */ 241 | Gpu_CoCmd_Calibrate(phost,0); 242 | App_Flush_Co_Buffer(phost); 243 | Gpu_Hal_WaitCmdfifo_empty(phost); 244 | } 245 | 246 | 247 | /************************************************************************************************* 248 | THIS PART DRAW BRIDGETEK LOGO 249 | *************************************************************************************************/ 250 | //#define LOGO_SCALE_ANIMATION 251 | /* Use bridgetek animation as default */ 252 | 253 | PROGMEM prog_uchar8_t logo_graphics[6224] = { 254 | 120, 218, 237, 93, 127, 112, 36, 71, 117, 158, 221, 213, 207, 149, 116, 255 | 44, 190, 56, 56, 72, 156, 20, 2, 4, 167, 184, 72, 49, 113, 165, 42, 196, 256 | 58, 249, 42, 135, 77, 37, 172, 20, 199, 103, 42, 14, 142, 54, 63, 140, 257 | 147, 2, 35, 37, 113, 217, 247, 7, 70, 138, 139, 248, 206, 84, 138, 85, 258 | 202, 137, 203, 103, 130, 87, 132, 10, 96, 217, 176, 71, 8, 33, 6, 131, 259 | 46, 84, 81, 16, 27, 103, 239, 236, 194, 21, 59, 94, 246, 226, 51, 196, 260 | 196, 216, 123, 62, 73, 43, 233, 36, 109, 103, 102, 119, 167, 231, 189, 261 | 158, 215, 61, 61, 163, 93, 157, 118, 153, 249, 235, 116, 253, 230, 125, 262 | 243, 125, 211, 63, 94, 191, 238, 233, 53, 140, 250, 92, 209, 175, 104, 263 | 24, 237, 95, 209, 112, 84, 208, 48, 218, 207, 86, 52, 28, 105, 24, 237, 264 | 103, 222, 70, 166, 35, 111, 35, 211, 145, 167, 145, 229, 200, 211, 200, 265 | 114, 228, 101, 84, 113, 228, 101, 84, 113, 228, 97, 84, 117, 228, 97, 84, 266 | 117, 164, 54, 170, 57, 82, 27, 213, 28, 41, 141, 108, 71, 74, 35, 219, 267 | 145, 202, 136, 59, 82, 25, 113, 71, 10, 35, 199, 145, 194, 200, 113, 36, 268 | 55, 2, 142, 228, 70, 192, 145, 212, 8, 58, 146, 26, 65, 71, 50, 35, 228, 269 | 72, 102, 132, 28, 73, 140, 176, 35, 137, 17, 118, 68, 27, 9, 142, 104, 270 | 35, 193, 17, 105, 36, 58, 34, 141, 68, 71, 148, 145, 203, 17, 101, 228, 271 | 114, 68, 24, 185, 29, 17, 70, 110, 71, 110, 35, 194, 145, 219, 136, 112, 272 | 228, 50, 162, 28, 185, 140, 40, 71, 162, 17, 233, 72, 52, 34, 29, 9, 70, 273 | 180, 35, 193, 136, 118, 132, 141, 36, 142, 176, 145, 196, 17, 50, 146, 274 | 57, 66, 70, 50, 71, 208, 72, 234, 8, 26, 73, 29, 1, 35, 185, 35, 96, 36, 275 | 119, 228, 24, 41, 28, 57, 70, 10, 71, 220, 72, 229, 136, 27, 169, 28, 276 | 217, 70, 74, 71, 182, 145, 210, 81, 205, 72, 237, 168, 102, 164, 118, 277 | 84, 53, 242, 112, 84, 53, 242, 112, 84, 49, 242, 114, 84, 49, 242, 114, 278 | 100, 25, 121, 58, 178, 140, 60, 29, 153, 70, 222, 142, 76, 35, 111, 71, 279 | 166, 81, 65, 195, 168, 141, 105, 24, 69, 138, 58, 112, 73, 29, 163, 182, 280 | 162, 134, 145, 134, 43, 211, 200, 219, 149, 245, 238, 146, 58, 70, 158, 281 | 174, 42, 245, 41, 169, 99, 228, 229, 170, 90, 199, 147, 58, 70, 30, 174, 282 | 106, 237, 46, 169, 99, 164, 118, 101, 247, 5, 73, 29, 35, 165, 43, 222, 283 | 63, 37, 117, 140, 84, 174, 156, 62, 51, 169, 99, 164, 112, 5, 250, 241, 284 | 164, 142, 145, 220, 21, 28, 91, 146, 58, 70, 82, 87, 104, 188, 75, 234, 285 | 24, 201, 92, 225, 49, 56, 169, 99, 36, 113, 37, 196, 5, 73, 29, 35, 218, 286 | 149, 24, 171, 36, 117, 140, 72, 87, 174, 248, 41, 169, 99, 68, 185, 114, 287 | 199, 116, 73, 29, 35, 194, 21, 17, 103, 38, 117, 140, 220, 174, 168, 288 | 216, 55, 169, 99, 228, 114, 69, 198, 227, 163, 58, 70, 177, 162, 134, 289 | 145, 232, 138, 54, 18, 92, 73, 230, 45, 163, 58, 70, 216, 149, 108, 46, 290 | 53, 170, 99, 132, 92, 73, 231, 119, 163, 58, 70, 208, 149, 124, 206, 57, 291 | 170, 99, 4, 92, 41, 230, 193, 163, 58, 70, 142, 43, 213, 220, 124, 84, 292 | 199, 136, 187, 82, 230, 11, 70, 117, 140, 108, 87, 234, 28, 198, 168, 293 | 142, 81, 205, 149, 71, 94, 101, 84, 199, 168, 234, 202, 43, 215, 51, 294 | 170, 99, 84, 113, 229, 153, 127, 26, 213, 49, 178, 92, 121, 231, 196, 295 | 70, 117, 140, 76, 87, 26, 121, 186, 81, 29, 163, 88, 81, 195, 200, 24, 296 | 213, 49, 138, 125, 95, 39, 87, 25, 49, 118, 242, 122, 125, 128, 123, 297 | 218, 254, 70, 39, 11, 42, 94, 151, 107, 189, 94, 241, 250, 57, 157, 74, 298 | 232, 186, 58, 138, 129, 110, 203, 176, 32, 183, 245, 179, 32, 183, 69, 299 | 114, 129, 110, 27, 96, 65, 110, 179, 193, 124, 222, 54, 192, 130, 220, 300 | 198, 193, 252, 221, 54, 192, 130, 220, 230, 128, 249, 186, 109, 128, 301 | 5, 185, 13, 128, 249, 185, 109, 128, 5, 185, 13, 130, 177, 23, 3, 129, 302 | 253, 40, 16, 88, 121, 36, 16, 216, 217, 16, 44, 4, 11, 193, 66, 176, 16, 303 | 172, 105, 192, 10, 129, 192, 222, 20, 130, 133, 96, 33, 88, 8, 22, 130, 304 | 133, 96, 33, 88, 8, 246, 211, 4, 246, 66, 48, 176, 161, 221, 9, 54, 16, 305 | 8, 204, 200, 6, 2, 235, 10, 6, 54, 30, 8, 204, 200, 5, 2, 107, 15, 6, 306 | 214, 23, 8, 12, 80, 243, 3, 102, 164, 3, 129, 57, 138, 248, 2, 139, 4, 307 | 3, 139, 5, 2, 115, 244, 95, 242, 151, 240, 181, 111, 155, 247, 117, 27, 308 | 175, 145, 211, 190, 110, 235, 180, 111, 155, 51, 2, 113, 243, 37, 164, 309 | 193, 55, 167, 108, 38, 252, 220, 22, 229, 239, 237, 223, 125, 193, 21, 310 | 130, 193, 101, 130, 193, 57, 45, 192, 23, 220, 62, 22, 8, 174, 147, 5, 311 | 131, 43, 4, 131, 155, 10, 6, 23, 103, 129, 224, 96, 234, 192, 15, 220, 312 | 47, 7, 131, 131, 203, 192, 126, 224, 70, 67, 184, 16, 46, 132, 11, 225, 313 | 66, 184, 16, 238, 98, 195, 157, 14, 6, 183, 21, 194, 133, 112, 33, 92, 314 | 8, 23, 194, 237, 90, 184, 161, 96, 112, 79, 133, 112, 33, 92, 8, 183, 315 | 227, 112, 79, 7, 131, 99, 95, 14, 6, 183, 18, 12, 206, 207, 30, 195, 316 | 209, 96, 183, 233, 237, 137, 87, 193, 249, 186, 77, 111, 223, 188, 2, 317 | 206, 223, 109, 122, 123, 235, 229, 112, 62, 111, 211, 219, 127, 239, 318 | 190, 174, 10, 118, 91, 100, 49, 208, 109, 70, 119, 176, 219, 140, 223, 319 | 14, 118, 91, 229, 190, 0, 183, 25, 191, 184, 24, 232, 54, 195, 248, 133, 320 | 131, 164, 92, 232, 175, 71, 18, 40, 7, 10, 103, 130, 89, 56, 193, 139, 321 | 163, 105, 98, 22, 206, 254, 226, 104, 14, 153, 133, 83, 195, 56, 154, 322 | 96, 102, 225, 188, 49, 142, 102, 159, 89, 56, 169, 236, 70, 83, 83, 97, 323 | 198, 153, 68, 133, 109, 69, 217, 199, 155, 41, 248, 169, 82, 201, 130, 324 | 79, 130, 34, 167, 176, 84, 125, 236, 36, 40, 178, 11, 75, 54, 221, 36, 325 | 40, 170, 22, 150, 28, 153, 146, 160, 200, 42, 44, 65, 121, 147, 41, 185, 326 | 244, 170, 235, 29, 99, 224, 143, 104, 1, 238, 68, 222, 207, 202, 99, 160, 327 | 8, 110, 83, 182, 62, 205, 229, 133, 213, 143, 121, 95, 4, 69, 188, 208, 328 | 254, 206, 247, 69, 80, 84, 43, 116, 62, 1, 126, 209, 128, 31, 13, 155, 329 | 133, 240, 235, 224, 179, 232, 51, 224, 23, 162, 104, 33, 52, 142, 150, 330 | 28, 65, 134, 220, 90, 149, 26, 64, 43, 91, 188, 176, 186, 96, 53, 128, 331 | 134, 193, 90, 161, 61, 184, 13, 160, 17, 178, 82, 232, 140, 123, 3, 104, 332 | 240, 52, 11, 225, 144, 56, 128, 198, 213, 200, 147, 104, 180, 188, 68, 333 | 245, 30, 226, 232, 253, 25, 89, 244, 114, 227, 232, 205, 91, 117, 184, 334 | 132, 10, 97, 113, 22, 85, 168, 56, 170, 109, 118, 237, 47, 161, 66, 187, 335 | 56, 139, 42, 113, 28, 213, 112, 184, 38, 92, 194, 127, 90, 197, 240, 69, 336 | 136, 197, 67, 168, 184, 132, 144, 170, 200, 113, 84, 232, 44, 54, 165, 337 | 96, 247, 233, 112, 202, 32, 74, 213, 98, 160, 71, 6, 201, 97, 21, 35, 338 | 45, 51, 72, 74, 163, 187, 132, 223, 195, 152, 178, 181, 224, 73, 78, 339 | 39, 222, 183, 63, 83, 134, 55, 119, 226, 109, 253, 51, 12, 182, 166, 340 | 78, 188, 235, 127, 134, 193, 246, 212, 137, 63, 10, 152, 97, 176, 69, 341 | 117, 226, 111, 6, 102, 24, 108, 83, 157, 248, 147, 130, 25, 180, 218, 342 | 13, 10, 217, 58, 42, 180, 22, 58, 115, 168, 16, 238, 28, 152, 131, 173, 343 | 167, 82, 8, 138, 231, 96, 251, 169, 21, 242, 226, 57, 216, 130, 120, 97, 344 | 173, 120, 14, 182, 33, 80, 88, 41, 134, 43, 175, 145, 220, 58, 146, 121, 345 | 96, 206, 208, 239, 234, 186, 240, 27, 203, 156, 198, 227, 50, 154, 181, 346 | 102, 208, 108, 180, 27, 79, 106, 51, 104, 178, 218, 141, 131, 225, 44, 347 | 138, 169, 227, 56, 86, 206, 162, 144, 59, 142, 67, 233, 44, 138, 200, 348 | 163, 66, 164, 45, 4, 236, 40, 16, 199, 33, 104, 9, 135, 150, 41, 20, 349 | 195, 149, 112, 108, 150, 66, 49, 87, 9, 199, 82, 41, 20, 146, 149, 112, 350 | 168, 149, 66, 17, 91, 9, 71, 98, 168, 89, 141, 226, 102, 21, 75, 41, 227, 351 | 42, 188, 87, 103, 0, 53, 171, 72, 14, 53, 171, 1, 212, 172, 172, 170, 3, 352 | 138, 7, 80, 179, 170, 86, 59, 94, 60, 128, 154, 149, 93, 101, 107, 197, 353 | 3, 168, 89, 57, 213, 189, 82, 60, 128, 154, 21, 218, 195, 45, 238, 205, 354 | 22, 54, 120, 195, 63, 207, 34, 79, 149, 253, 73, 78, 241, 89, 244, 20, 355 | 181, 205, 75, 118, 241, 89, 196, 128, 239, 108, 170, 22, 159, 69, 236, 356 | 193, 182, 39, 171, 248, 44, 82, 14, 237, 137, 138, 228, 240, 198, 170, 357 | 55, 170, 54, 76, 69, 113, 43, 154, 69, 141, 104, 13, 183, 161, 89, 212, 358 | 132, 214, 112, 11, 154, 69, 13, 104, 13, 245, 232, 181, 66, 59, 40, 91, 359 | 67, 99, 65, 165, 208, 137, 215, 214, 96, 145, 85, 8, 118, 246, 88, 133, 360 | 105, 6, 11, 225, 214, 164, 85, 84, 184, 138, 246, 45, 89, 251, 68, 210, 361 | 168, 213, 116, 225, 33, 50, 141, 218, 76, 23, 30, 92, 211, 168, 197, 116, 362 | 225, 97, 57, 141, 218, 75, 23, 30, 208, 211, 168, 181, 116, 41, 26, 75, 363 | 59, 26, 159, 38, 97, 75, 105, 135, 45, 193, 152, 132, 237, 164, 29, 182, 364 | 3, 171, 200, 41, 236, 128, 173, 192, 222, 210, 176, 12, 138, 204, 107, 365 | 12, 20, 85, 11, 59, 28, 205, 198, 208, 70, 136, 101, 88, 196, 46, 192, 366 | 34, 54, 223, 142, 138, 106, 179, 41, 123, 95, 79, 63, 40, 50, 64, 225, 367 | 188, 5, 222, 15, 138, 156, 194, 249, 234, 67, 247, 131, 34, 187, 112, 368 | 222, 38, 219, 15, 138, 170, 133, 243, 142, 72, 253, 160, 200, 42, 156, 369 | 135, 226, 254, 172, 17, 94, 187, 241, 234, 165, 14, 218, 40, 191, 242, 370 | 252, 227, 119, 31, 244, 233, 105, 15, 112, 112, 74, 102, 212, 134, 59, 371 | 150, 6, 243, 168, 94, 27, 127, 209, 26, 60, 24, 251, 78, 162, 53, 120, 372 | 176, 31, 182, 8, 15, 246, 233, 22, 225, 225, 35, 19, 189, 171, 121, 176, 373 | 147, 45, 194, 99, 173, 69, 120, 176, 137, 22, 225, 113, 170, 69, 120, 374 | 44, 181, 8, 143, 245, 22, 225, 81, 110, 17, 30, 218, 13, 125, 183, 243, 375 | 152, 107, 17, 30, 39, 90, 132, 199, 169, 22, 225, 113, 174, 69, 120, 376 | 232, 14, 32, 125, 175, 58, 215, 201, 139, 204, 35, 159, 207, 23, 116, 377 | 78, 73, 12, 124, 237, 12, 143, 202, 88, 241, 150, 27, 49, 143, 213, 38, 378 | 229, 33, 158, 235, 216, 188, 60, 218, 2, 70, 238, 187, 141, 7, 62, 254, 379 | 121, 189, 121, 121, 164, 91, 132, 199, 1, 134, 114, 188, 77, 203, 99, 380 | 184, 69, 120, 12, 162, 180, 98, 243, 242, 120, 93, 43, 242, 104, 226, 381 | 122, 181, 167, 21, 121, 172, 183, 8, 143, 181, 86, 231, 113, 233, 61, 382 | 15, 255, 224, 249, 71, 143, 122, 30, 241, 177, 247, 125, 31, 127, 242, 383 | 249, 135, 110, 79, 168, 121, 188, 237, 147, 79, 190, 242, 196, 67, 127, 384 | 105, 104, 120, 123, 236, 123, 249, 87, 159, 127, 226, 161, 251, 255, 385 | 216, 23, 15, 30, 39, 222, 184, 192, 175, 207, 24, 70, 196, 14, 139, 386 | 203, 127, 94, 45, 238, 118, 138, 23, 224, 156, 222, 182, 219, 248, 67, 387 | 21, 143, 143, 212, 254, 243, 255, 126, 199, 250, 235, 1, 199, 213, 16, 388 | 102, 251, 69, 248, 104, 155, 159, 187, 58, 0, 143, 52, 154, 147, 92, 389 | 229, 228, 228, 71, 84, 243, 193, 247, 58, 255, 251, 183, 114, 30, 55, 390 | 57, 207, 48, 141, 3, 60, 200, 35, 250, 41, 87, 86, 234, 239, 180, 121, 391 | 148, 72, 30, 112, 135, 231, 89, 5, 143, 55, 194, 69, 136, 49, 25, 15, 392 | 184, 35, 110, 115, 68, 198, 35, 154, 33, 166, 171, 255, 53, 164, 201, 393 | 99, 133, 228, 49, 9, 111, 75, 200, 121, 44, 226, 166, 38, 225, 177, 40, 394 | 116, 144, 36, 143, 72, 134, 156, 119, 255, 175, 230, 56, 184, 76, 241, 395 | 136, 34, 87, 179, 82, 30, 61, 24, 115, 158, 230, 33, 90, 209, 60, 100, 396 | 191, 56, 243, 45, 189, 248, 234, 60, 197, 35, 142, 60, 157, 145, 242, 397 | 152, 18, 146, 197, 52, 143, 25, 49, 165, 76, 241, 144, 254, 186, 78, 398 | 57, 165, 21, 239, 158, 161, 120, 28, 112, 167, 84, 40, 30, 174, 159, 399 | 209, 249, 19, 138, 71, 84, 180, 154, 165, 120, 168, 127, 145, 202, 123, 400 | 254, 113, 146, 226, 177, 232, 158, 194, 83, 60, 186, 68, 200, 11, 20, 401 | 143, 30, 209, 106, 149, 224, 17, 41, 200, 83, 233, 35, 18, 30, 83, 100, 402 | 126, 23, 240, 216, 16, 158, 78, 198, 163, 79, 107, 201, 110, 88, 101, 403 | 53, 36, 147, 4, 31, 248, 68, 242, 128, 167, 92, 87, 247, 17, 185, 102, 404 | 187, 204, 21, 218, 83, 60, 134, 181, 120, 164, 117, 120, 236, 83, 216, 405 | 92, 160, 121, 196, 232, 245, 15, 57, 220, 150, 140, 199, 148, 22, 143, 406 | 130, 14, 143, 140, 218, 136, 226, 209, 79, 135, 87, 105, 245, 90, 15, 407 | 197, 35, 171, 195, 35, 198, 52, 120, 68, 61, 214, 54, 8, 30, 111, 43, 408 | 208, 233, 221, 0, 60, 22, 117, 120, 116, 232, 240, 232, 84, 26, 189, 38, 409 | 228, 119, 143, 31, 63, 254, 176, 240, 150, 103, 183, 195, 35, 167, 195, 410 | 35, 174, 195, 163, 71, 105, 180, 226, 153, 111, 7, 155, 166, 3, 240, 40, 411 | 234, 240, 232, 211, 225, 177, 199, 99, 49, 214, 139, 199, 178, 177, 29, 412 | 30, 90, 91, 37, 6, 117, 120, 140, 195, 255, 123, 233, 250, 43, 14, 221, 413 | 137, 2, 120, 47, 30, 112, 83, 104, 163, 120, 12, 235, 240, 72, 187, 102, 414 | 218, 232, 113, 188, 120, 192, 15, 107, 26, 197, 3, 69, 15, 207, 28, 188, 415 | 228, 154, 34, 193, 3, 246, 24, 167, 221, 17, 238, 144, 154, 199, 122, 66, 416 | 194, 163, 124, 239, 155, 175, 201, 249, 228, 241, 210, 193, 189, 191, 417 | 239, 197, 99, 221, 213, 166, 135, 220, 99, 204, 188, 123, 128, 31, 81, 418 | 242, 120, 9, 77, 42, 211, 66, 179, 137, 251, 227, 81, 233, 49, 166, 8, 419 | 30, 227, 162, 212, 81, 130, 71, 209, 213, 133, 162, 238, 122, 76, 193, 420 | 163, 252, 57, 188, 61, 49, 45, 72, 210, 230, 143, 199, 146, 40, 181, 205, 421 | 99, 210, 37, 117, 193, 205, 3, 122, 170, 30, 88, 216, 142, 54, 43, 200, 422 | 121, 124, 71, 76, 132, 164, 5, 87, 17, 127, 60, 206, 136, 195, 25, 197, 423 | 99, 214, 213, 24, 170, 60, 34, 30, 60, 82, 114, 30, 47, 223, 119, 181, 424 | 156, 199, 132, 127, 30, 39, 69, 112, 138, 199, 180, 43, 156, 25, 114, 425 | 135, 37, 254, 120, 152, 215, 183, 235, 206, 163, 45, 32, 143, 216, 182, 426 | 120, 224, 134, 126, 49, 121, 180, 109, 143, 7, 250, 24, 239, 98, 242, 427 | 104, 223, 38, 15, 16, 38, 54, 55, 143, 141, 22, 225, 33, 137, 219, 155, 428 | 143, 199, 114, 139, 240, 40, 39, 90, 131, 135, 83, 177, 154, 135, 71, 429 | 249, 176, 121, 253, 233, 35, 152, 199, 255, 236, 58, 30, 196, 149, 162, 430 | 242, 37, 239, 101, 94, 235, 6, 213, 77, 164, 119, 216, 215, 237, 187, 431 | 147, 7, 78, 115, 108, 74, 121, 120, 239, 235, 187, 200, 60, 198, 201, 76, 432 | 88, 243, 241, 192, 25, 140, 137, 166, 229, 209, 201, 168, 68, 117, 243, 433 | 241, 192, 119, 157, 106, 90, 30, 56, 227, 122, 174, 105, 121, 68, 133, 434 | 228, 105, 179, 242, 64, 179, 97, 190, 64, 216, 124, 60, 112, 222, 105, 435 | 169, 69, 120, 44, 183, 8, 143, 149, 22, 225, 81, 106, 17, 30, 107, 45, 436 | 194, 99, 125, 183, 241, 184, 235, 205, 174, 43, 161, 193, 227, 194, 110, 437 | 227, 49, 173, 187, 31, 46, 228, 177, 155, 121, 172, 135, 60, 46, 50, 143, 438 | 200, 238, 238, 119, 181, 121, 196, 90, 132, 7, 254, 176, 104, 181, 105, 439 | 121, 180, 55, 5, 143, 215, 131, 139, 230, 209, 181, 187, 227, 171, 105, 440 | 119, 118, 42, 229, 189, 239, 117, 87, 196, 237, 109, 129, 120, 76, 238, 441 | 186, 249, 96, 44, 8, 143, 104, 174, 17, 121, 134, 83, 117, 94, 175, 245, 442 | 230, 241, 81, 214, 136, 188, 207, 57, 177, 229, 5, 94, 63, 159, 117, 111, 443 | 238, 74, 185, 246, 145, 29, 127, 164, 32, 196, 246, 39, 130, 243, 40, 444 | 138, 221, 197, 155, 60, 120, 104, 237, 103, 152, 115, 59, 159, 240, 94, 445 | 255, 216, 78, 62, 177, 40, 228, 87, 225, 105, 115, 36, 15, 173, 253, 37, 446 | 39, 220, 175, 104, 76, 131, 199, 116, 112, 30, 232, 213, 110, 30, 189, 447 | 37, 75, 197, 9, 227, 98, 44, 231, 181, 223, 103, 201, 189, 29, 80, 135, 448 | 199, 72, 157, 120, 136, 151, 175, 253, 87, 80, 129, 45, 107, 115, 91, 449 | 100, 6, 61, 163, 55, 143, 242, 54, 214, 63, 114, 190, 121, 184, 174, 33, 450 | 98, 39, 240, 214, 67, 71, 239, 193, 91, 106, 135, 188, 121, 92, 216, 6, 451 | 143, 69, 29, 30, 131, 58, 60, 212, 155, 255, 88, 194, 155, 199, 202, 54, 452 | 120, 164, 117, 120, 212, 97, 191, 232, 166, 198, 57, 19, 175, 109, 131, 453 | 135, 214, 190, 112, 173, 253, 187, 106, 163, 117, 63, 231, 176, 4, 224, 454 | 49, 174, 195, 163, 83, 135, 71, 135, 71, 157, 233, 213, 238, 174, 130, 455 | 240, 24, 212, 225, 17, 213, 225, 17, 41, 170, 235, 140, 143, 115, 163, 456 | 2, 240, 232, 213, 225, 161, 238, 213, 134, 116, 170, 232, 73, 111, 30, 457 | 47, 108, 135, 135, 187, 202, 20, 9, 30, 51, 58, 60, 148, 189, 193, 152, 458 | 55, 143, 233, 237, 240, 112, 85, 153, 242, 56, 193, 99, 159, 14, 15, 85, 459 | 134, 119, 195, 251, 92, 156, 11, 198, 118, 120, 184, 170, 204, 202, 48, 460 | 193, 67, 124, 196, 173, 28, 193, 67, 53, 22, 45, 121, 243, 152, 219, 30, 461 | 15, 177, 195, 154, 167, 120, 136, 143, 248, 84, 150, 226, 209, 163, 172, 462 | 51, 30, 60, 214, 140, 237, 241, 232, 22, 170, 85, 130, 228, 49, 128, 141, 463 | 134, 72, 30, 242, 143, 123, 74, 94, 61, 10, 219, 154, 216, 38, 15, 225, 464 | 107, 185, 21, 131, 228, 17, 65, 213, 239, 172, 65, 243, 232, 150, 46, 465 | 126, 120, 241, 216, 74, 25, 219, 228, 97, 188, 3, 41, 61, 65, 243, 64, 466 | 95, 19, 175, 39, 36, 60, 170, 191, 4, 228, 190, 190, 236, 213, 195, 191, 467 | 60, 97, 108, 155, 7, 154, 57, 61, 109, 72, 120, 128, 71, 180, 130, 114, 468 | 9, 15, 227, 253, 82, 26, 114, 30, 229, 103, 255, 200, 48, 182, 207, 195, 469 | 104, 115, 136, 108, 36, 164, 60, 140, 27, 107, 3, 203, 143, 199, 12, 57, 470 | 15, 227, 90, 215, 144, 249, 114, 237, 4, 129, 182, 195, 212, 117, 253, 471 | 59, 127, 222, 253, 160, 111, 5, 6, 196, 65, 201, 208, 19, 248, 138, 199, 472 | 136, 253, 67, 13, 242, 171, 214, 35, 93, 234, 24, 93, 135, 110, 143, 221, 473 | 243, 216, 15, 126, 242, 232, 199, 36, 249, 18, 254, 122, 127, 239, 27, 474 | 176, 222, 63, 126, 155, 177, 131, 87, 236, 134, 35, 199, 143, 222, 124, 475 | 181, 254, 13, 114, 30, 214, 216, 122, 232, 150, 35, 247, 28, 191, 255, 476 | 232, 237, 55, 31, 52, 118, 249, 165, 228, 209, 68, 87, 200, 35, 228, 17, 477 | 242, 104, 57, 30, 61, 226, 83, 195, 24, 32, 209, 60, 60, 122, 69, 30, 478 | 48, 184, 52, 154, 146, 199, 152, 152, 92, 47, 55, 39, 143, 57, 113, 86, 479 | 191, 213, 156, 60, 214, 204, 230, 16, 153, 66, 153, 194, 166, 108, 231, 480 | 108, 227, 243, 247, 124, 83, 72, 33, 52, 205, 213, 173, 57, 177, 222, 481 | 237, 151, 234, 136, 149, 165, 38, 226, 161, 202, 221, 158, 105, 34, 30, 482 | 170, 4, 239, 124, 51, 197, 33, 138, 229, 183, 137, 102, 226, 145, 145, 483 | 103, 108, 154, 42, 46, 148, 175, 16, 46, 55, 21, 143, 120, 107, 52, 15, 484 | 121, 67, 47, 55, 217, 236, 99, 82, 194, 227, 197, 38, 155, 56, 73, 70, 485 | 144, 173, 38, 123, 29, 134, 241, 97, 146, 199, 151, 154, 110, 38, 27, 486 | 165, 86, 105, 158, 105, 194, 41, 121, 135, 123, 44, 252, 118, 83, 230, 487 | 22, 98, 15, 210, 9, 232, 230, 187, 174, 249, 130, 211, 192, 191, 118, 488 | 155, 209, 196, 215, 222, 67, 55, 28, 57, 122, 251, 7, 14, 255, 138, 17, 489 | 94, 254, 175, 134, 103, 153, 66, 128, 16, 32, 4, 8, 1, 234, 3, 16, 165, 490 | 119, 211, 132, 0, 33, 64, 8, 16, 2, 132, 0, 33, 64, 8, 176, 219, 0, 46, 491 | 121, 247, 199, 191, 254, 189, 252, 171, 249, 39, 22, 238, 191, 45, 225, 492 | 23, 160, 123, 97, 225, 97, 152, 141, 170, 254, 192, 202, 63, 1, 139, 75, 493 | 209, 15, 147, 108, 253, 219, 117, 30, 0, 240, 55, 95, 38, 100, 31, 33, 494 | 56, 63, 52, 24, 249, 136, 171, 240, 43, 9, 37, 192, 56, 218, 220, 236, 495 | 5, 16, 249, 40, 81, 90, 217, 9, 39, 5, 200, 224, 165, 104, 15, 128, 91, 496 | 233, 189, 200, 9, 5, 64, 17, 111, 133, 87, 3, 200, 18, 210, 63, 148, 3, 497 | 180, 11, 217, 119, 53, 64, 214, 59, 225, 45, 2, 196, 133, 253, 136, 74, 498 | 128, 184, 198, 134, 109, 17, 96, 80, 216, 14, 173, 4, 200, 104, 236, 499 | 108, 23, 1, 166, 132, 175, 42, 84, 0, 49, 157, 47, 125, 68, 128, 69, 500 | 97, 33, 71, 5, 160, 58, 160, 158, 159, 253, 40, 0, 68, 197, 5, 97, 21, 501 | 192, 184, 206, 238, 127, 1, 160, 83, 92, 169, 85, 1, 40, 63, 183, 56, 502 | 69, 3, 244, 137, 38, 10, 0, 245, 119, 41, 37, 26, 0, 46, 73, 205, 122, 503 | 0, 116, 104, 125, 89, 32, 0, 164, 197, 79, 115, 20, 0, 234, 143, 152, 504 | 182, 104, 128, 130, 104, 161, 0, 192, 63, 96, 119, 253, 21, 87, 126, 505 | 144, 250, 198, 2, 3, 184, 63, 177, 86, 0, 64, 57, 171, 63, 137, 112, 506 | 128, 88, 117, 197, 0, 221, 174, 229, 126, 5, 192, 148, 203, 184, 147, 507 | 168, 167, 24, 192, 189, 51, 186, 253, 240, 225, 247, 193, 205, 43, 96, 508 | 35, 113, 218, 181, 104, 143, 154, 246, 44, 5, 48, 73, 245, 38, 178, 49, 509 | 57, 227, 122, 154, 8, 241, 97, 7, 6, 32, 55, 212, 201, 0, 178, 232, 3, 510 | 165, 202, 69, 244, 216, 8, 32, 66, 238, 228, 145, 1, 44, 170, 1, 78, 511 | 16, 0, 29, 228, 184, 46, 3, 200, 249, 7, 128, 251, 232, 207, 123, 2, 512 | 20, 252, 3, 12, 187, 111, 81, 0, 20, 253, 3, 204, 144, 31, 91, 201, 513 | 0, 152, 127, 128, 2, 185, 43, 179, 126, 0, 123, 233, 237, 96, 245, 3, 514 | 184, 140, 172, 68, 117, 4, 216, 71, 86, 162, 58, 2, 76, 82, 223, 155, 515 | 214, 19, 32, 39, 124, 238, 83, 119, 0, 70, 207, 21, 116, 0, 136, 75, 516 | 13, 176, 97, 52, 24, 160, 212, 104, 128, 215, 26, 13, 112, 162, 209, 0, 517 | 179, 141, 6, 56, 213, 104, 128, 165, 70, 3, 172, 53, 26, 96, 171, 33, 518 | 0, 69, 38, 110, 175, 174, 51, 192, 12, 253, 185, 106, 253, 0, 134, 233, 519 | 253, 149, 245, 3, 232, 167, 119, 168, 213, 15, 224, 13, 180, 167, 250, 520 | 1, 92, 66, 205, 18, 245, 0, 190, 69, 156, 58, 73, 68, 21, 57, 114, 83, 521 | 165, 143, 1, 199, 43, 227, 53, 67, 102, 27, 234, 8, 112, 128, 236, 176, 522 | 235, 8, 208, 71, 14, 57, 117, 4, 232, 34, 7, 205, 58, 2, 180, 145, 195, 523 | 126, 29, 1, 80, 192, 156, 106, 4, 64, 134, 186, 167, 158, 0, 147, 84, 524 | 240, 232, 3, 32, 2, 142, 181, 163, 26, 26, 58, 30, 97, 53, 0, 192, 148, 525 | 199, 252, 0, 255, 122, 115, 128, 25, 142, 39, 0, 58, 24, 97, 196, 255, 526 | 28, 205, 19, 128, 58, 70, 12, 1, 108, 168, 103, 153, 158, 0, 232, 79, 527 | 234, 116, 139, 77, 73, 253, 168, 217, 206, 120, 2, 76, 17, 161, 75, 84, 528 | 18, 117, 103, 221, 3, 96, 198, 99, 166, 143, 79, 46, 90, 167, 0, 102, 529 | 233, 92, 197, 107, 110, 213, 200, 92, 5, 250, 164, 157, 60, 217, 30, 4, 530 | 76, 105, 215, 127, 183, 123, 102, 91, 112, 198, 103, 140, 0, 96, 207, 531 | 221, 125, 228, 129, 175, 87, 254, 31, 237, 12, 182, 126, 73, 222, 248, 532 | 3, 111, 128, 24, 145, 144, 137, 72, 194, 178, 65, 148, 136, 125, 232, 533 | 232, 145, 79, 49, 207, 132, 20, 174, 220, 103, 100, 163, 123, 21, 64, 534 | 125, 140, 19, 157, 82, 195, 194, 174, 16, 77, 22, 0, 116, 171, 1, 134, 535 | 104, 128, 3, 68, 179, 45, 208, 0, 237, 65, 210, 154, 56, 9, 152, 144, 536 | 4, 200, 91, 146, 119, 163, 145, 152, 197, 188, 83, 238, 246, 9, 159, 537 | 46, 27, 32, 181, 140, 15, 203, 172, 181, 246, 3, 18, 0, 229, 121, 98, 538 | 231, 53, 22, 137, 236, 246, 185, 71, 2, 160, 250, 200, 138, 135, 231, 539 | 46, 128, 172, 155, 102, 151, 4, 64, 117, 226, 147, 108, 129, 2, 183, 540 | 207, 77, 137, 35, 187, 134, 40, 142, 98, 90, 147, 174, 163, 13, 18, 117, 541 | 57, 45, 1, 80, 36, 248, 191, 36, 5, 232, 33, 154, 123, 143, 108, 6, 39, 542 | 165, 176, 33, 95, 9, 236, 160, 130, 133, 156, 4, 160, 221, 255, 66, 29, 543 | 238, 59, 237, 186, 214, 47, 155, 131, 94, 78, 251, 255, 190, 106, 61, 544 | 57, 71, 189, 170, 15, 203, 38, 185, 191, 68, 249, 127, 70, 185, 96, 61, 545 | 67, 121, 138, 220, 41, 155, 69, 255, 154, 171, 35, 217, 252, 152, 122, 546 | 69, 124, 152, 10, 93, 12, 227, 61, 255, 73, 3, 24, 198, 181, 143, 129, 547 | 106, 92, 126, 226, 239, 241, 194, 250, 149, 224, 144, 147, 234, 255, 548 | 160, 3, 84, 134, 128, 233, 91, 111, 57, 114, 252, 216, 237, 55, 255, 549 | 230, 21, 174, 163, 84, 34, 87, 86, 78, 254, 56, 118, 199, 7, 14, 54, 550 | 209, 215, 233, 63, 53, 215, 222, 235, 135, 52, 172, 126, 230, 250, 29, 551 | 124, 119, 111, 249, 93, 77, 176, 200, 149, 7, 181, 74, 162, 135, 92, 552 | 123, 254, 173, 30, 232, 39, 247, 218, 127, 153, 61, 97, 249, 113, 158, 553 | 94, 234, 227, 221, 203, 140, 117, 194, 145, 211, 142, 46, 47, 130, 51, 554 | 180, 114, 224, 48, 196, 105, 51, 218, 227, 191, 164, 247, 46, 179, 159, 555 | 28, 169, 167, 30, 157, 104, 248, 155, 66, 173, 248, 253, 213, 175, 220, 556 | 107, 113, 112, 202, 156, 29, 217, 41, 160, 113, 43, 110, 158, 228, 107, 557 | 40, 209, 44, 248, 150, 166, 23, 46, 28, 68, 30, 132, 253, 150, 117, 18, 558 | 211, 63, 243, 200, 125, 194, 226, 89, 235, 219, 103, 249, 205, 214, 72, 559 | 96, 251, 221, 131, 79, 202, 230, 153, 131, 104, 1, 246, 162, 5, 187, 560 | 55, 234, 180, 6, 135, 46, 158, 193, 104, 19, 146, 86, 219, 191, 186, 561 | 208, 64, 50, 3, 195, 251, 10, 141, 211, 156, 219, 180, 249, 218, 237, 562 | 160, 115, 210, 50, 154, 226, 93, 230, 40, 92, 222, 234, 131, 201, 217, 563 | 253, 40, 79, 56, 9, 250, 217, 41, 19, 51, 106, 70, 7, 29, 40, 154, 237, 564 | 69, 9, 112, 65, 44, 158, 138, 234, 65, 249, 77, 40, 214, 107, 64, 172, 565 | 125, 66, 126, 172, 161, 98, 13, 195, 153, 151, 40, 150, 249, 128, 142, 566 | 88, 5, 56, 9, 68, 98, 45, 66, 37, 170, 227, 119, 77, 254, 65, 115, 62, 567 | 209, 201, 86, 77, 177, 202, 11, 57, 94, 155, 123, 217, 230, 195, 69, 568 | 126, 3, 20, 235, 185, 111, 58, 41, 142, 113, 182, 241, 103, 69, 46, 41, 569 | 20, 107, 5, 136, 53, 195, 46, 124, 144, 254, 81, 129, 160, 87, 219, 194, 570 | 2, 99, 95, 91, 224, 49, 248, 115, 11, 11, 159, 231, 15, 184, 246, 33, 571 | 30, 254, 187, 196, 154, 118, 196, 50, 43, 199, 103, 63, 193, 99, 125, 572 | 40, 150, 57, 155, 251, 215, 79, 112, 37, 204, 23, 115, 223, 162, 221, 573 | 152, 122, 76, 179, 30, 83, 140, 14, 51, 254, 234, 224, 225, 97, 175, 574 | 217, 110, 250, 121, 68, 6, 197, 154, 53, 123, 130, 37, 46, 195, 73, 83, 575 | 176, 51, 132, 88, 235, 64, 172, 69, 243, 158, 25, 180, 76, 83, 135, 11, 576 | 172, 223, 206, 192, 212, 122, 206, 20, 132, 63, 136, 75, 172, 19, 142, 577 | 88, 221, 166, 80, 29, 224, 103, 25, 29, 177, 58, 204, 118, 22, 227, 130, 578 | 247, 154, 21, 169, 203, 174, 171, 29, 102, 167, 51, 104, 146, 182, 196, 579 | 50, 97, 198, 28, 177, 98, 92, 93, 44, 214, 30, 222, 105, 101, 205, 199, 580 | 116, 58, 127, 40, 214, 22, 16, 171, 192, 172, 3, 3, 207, 236, 140, 88, 581 | 69, 147, 65, 218, 158, 247, 185, 196, 58, 231, 136, 213, 99, 138, 16, 582 | 229, 146, 64, 177, 186, 45, 105, 120, 239, 178, 199, 44, 137, 241, 73, 583 | 140, 249, 143, 113, 211, 105, 69, 172, 69, 27, 198, 18, 203, 224, 103, 584 | 240, 96, 177, 122, 121, 159, 110, 213, 153, 246, 187, 71, 8, 177, 216, 585 | 144, 35, 150, 133, 219, 249, 215, 67, 59, 35, 150, 213, 47, 189, 235, 62, 586 | 89, 51, 92, 118, 196, 234, 51, 95, 121, 132, 123, 129, 98, 197, 45, 177, 587 | 138, 118, 199, 60, 104, 149, 28, 189, 142, 51, 78, 100, 204, 123, 106, 588 | 98, 77, 0, 177, 138, 206, 65, 213, 80, 172, 30, 48, 171, 159, 70, 73, 589 | 67, 46, 214, 22, 75, 97, 177, 234, 126, 169, 196, 2, 57, 58, 44, 86, 97, 590 | 205, 37, 214, 136, 91, 172, 30, 171, 50, 0, 177, 64, 80, 97, 222, 158, 591 | 42, 108, 26, 85, 177, 114, 246, 205, 181, 154, 149, 160, 196, 138, 123, 592 | 139, 181, 198, 230, 161, 88, 35, 59, 38, 86, 4, 157, 16, 38, 138, 149, 593 | 222, 132, 98, 173, 128, 71, 115, 137, 85, 176, 219, 24, 22, 107, 144, 594 | 253, 163, 149, 44, 183, 196, 138, 240, 14, 207, 18, 43, 202, 83, 181, 595 | 88, 172, 110, 46, 86, 14, 238, 160, 128, 98, 45, 179, 51, 187, 81, 172, 596 | 36, 75, 112, 177, 246, 40, 196, 90, 5, 98, 13, 35, 177, 122, 216, 143, 597 | 172, 191, 205, 49, 224, 87, 63, 196, 151, 24, 44, 177, 248, 24, 32, 136, 598 | 213, 197, 71, 73, 169, 88, 231, 11, 75, 92, 172, 72, 67, 142, 131, 67, 599 | 98, 125, 154, 47, 158, 136, 98, 221, 251, 206, 223, 0, 98, 253, 22, 155, 600 | 0, 98, 45, 87, 135, 3, 90, 172, 156, 35, 22, 220, 207, 97, 142, 159, 86, 601 | 224, 36, 70, 240, 107, 55, 100, 249, 168, 135, 197, 234, 4, 98, 77, 92, 602 | 118, 236, 216, 93, 132, 88, 233, 85, 36, 214, 219, 143, 29, 251, 171, 6, 603 | 138, 229, 36, 159, 35, 196, 186, 130, 35, 214, 187, 217, 156, 150, 88, 604 | 37, 44, 86, 236, 216, 177, 99, 78, 205, 181, 186, 158, 14, 52, 193, 233, 605 | 133, 113, 171, 32, 86, 7, 111, 158, 102, 80, 48, 236, 204, 126, 160, 88, 606 | 227, 27, 80, 44, 179, 242, 163, 202, 220, 0, 177, 206, 241, 120, 91, 33, 607 | 214, 65, 118, 10, 136, 181, 4, 66, 37, 40, 86, 175, 197, 104, 209, 17, 608 | 235, 92, 23, 88, 218, 89, 172, 0, 87, 107, 214, 89, 40, 214, 214, 72, 609 | 96, 177, 246, 176, 203, 118, 161, 88, 99, 133, 243, 219, 21, 107, 170, 610 | 66, 222, 148, 224, 208, 173, 96, 186, 3, 55, 254, 200, 155, 97, 74, 34, 611 | 86, 15, 187, 22, 54, 195, 201, 198, 138, 245, 236, 241, 227, 179, 116, 612 | 51, 252, 234, 29, 119, 66, 177, 50, 165, 32, 205, 176, 3, 136, 53, 88, 613 | 233, 214, 43, 163, 97, 209, 137, 224, 87, 223, 227, 44, 40, 171, 58, 614 | 248, 110, 254, 48, 80, 172, 14, 118, 12, 117, 240, 189, 13, 21, 75, 615 | 119, 52, 28, 155, 188, 32, 138, 53, 162, 213, 193, 23, 153, 147, 173, 616 | 90, 174, 137, 101, 78, 251, 102, 249, 104, 24, 115, 22, 121, 229, 161, 617 | 195, 180, 68, 172, 40, 251, 46, 10, 29, 250, 208, 152, 114, 209, 196, 618 | 26, 44, 7, 11, 29, 72, 177, 102, 236, 180, 135, 21, 58, 20, 216, 144, 619 | 225, 29, 148, 198, 73, 177, 140, 194, 250, 197, 18, 75, 17, 193, 143, 620 | 245, 176, 76, 160, 160, 148, 121, 138, 149, 225, 241, 185, 124, 186, 621 | 51, 43, 19, 43, 83, 70, 211, 157, 61, 59, 36, 150, 122, 186, 51, 214, 622 | 201, 138, 254, 167, 59, 75, 18, 177, 210, 160, 25, 154, 211, 235, 147, 623 | 26, 19, 233, 30, 158, 4, 69, 98, 77, 50, 65, 172, 115, 59, 39, 86, 242, 624 | 209, 33, 137, 88, 49, 198, 160, 88, 81, 205, 137, 116, 132, 20, 11, 101, 625 | 29, 28, 137, 176, 88, 251, 56, 124, 198, 124, 204, 94, 14, 131, 196, 26, 626 | 100, 40, 69, 243, 186, 157, 76, 209, 100, 100, 41, 154, 49, 43, 61, 170, 627 | 155, 162, 1, 33, 70, 196, 73, 241, 59, 98, 117, 50, 152, 207, 138, 243, 628 | 225, 16, 137, 21, 93, 4, 203, 23, 167, 141, 3, 188, 206, 32, 177, 122, 629 | 28, 177, 178, 102, 219, 158, 218, 169, 228, 223, 34, 155, 139, 72, 147, 630 | 127, 150, 142, 78, 242, 111, 211, 74, 143, 144, 201, 191, 173, 68, 59, 631 | 72, 254, 173, 155, 118, 23, 68, 177, 88, 158, 129, 56, 107, 217, 104, 632 | 39, 39, 210, 175, 20, 156, 220, 252, 1, 182, 245, 0, 153, 86, 62, 95, 633 | 205, 195, 243, 56, 238, 147, 245, 77, 43, 139, 98, 189, 146, 207, 255, 634 | 55, 255, 99, 227, 65, 158, 14, 112, 139, 53, 201, 197, 106, 99, 236, 63, 635 | 22, 249, 236, 183, 143, 149, 243, 249, 124, 202, 14, 108, 159, 253, 34, 636 | 15, 143, 76, 34, 223, 93, 116, 214, 104, 184, 88, 96, 17, 198, 18, 43, 637 | 194, 168, 124, 22, 92, 83, 142, 163, 191, 144, 88, 49, 71, 172, 190, 638 | 186, 47, 88, 16, 17, 124, 25, 174, 142, 172, 74, 197, 26, 116, 30, 55, 639 | 7, 119, 16, 244, 193, 153, 113, 6, 42, 81, 221, 225, 113, 138, 16, 139, 640 | 255, 2, 77, 37, 159, 197, 123, 48, 65, 44, 126, 172, 99, 101, 27, 68, 641 | 137, 202, 58, 88, 127, 217, 98, 197, 138, 96, 30, 213, 104, 177, 218, 642 | 224, 170, 148, 91, 172, 94, 71, 172, 253, 112, 101, 10, 137, 213, 143, 643 | 118, 193, 90, 75, 102, 206, 129, 156, 85, 177, 218, 242, 249, 231, 31, 644 | 229, 22, 241, 252, 83, 134, 113, 83, 190, 214, 25, 244, 228, 237, 41, 645 | 245, 173, 166, 213, 103, 157, 74, 242, 134, 2, 219, 224, 105, 208, 47, 646 | 228, 107, 46, 219, 45, 243, 59, 243, 246, 88, 106, 188, 189, 200, 126, 647 | 92, 239, 44, 205, 55, 242, 252, 41, 110, 50, 27, 16, 111, 134, 198, 175, 648 | 131, 5, 210, 59, 243, 19, 70, 87, 254, 233, 218, 95, 87, 153, 207, 215, 649 | 158, 183, 31, 178, 242, 137, 254, 103, 28, 190, 121, 222, 12, 141, 200, 650 | 173, 140, 253, 11, 71, 138, 154, 205, 250, 46, 3, 9, 19, 240, 138, 92, 651 | 161, 101, 181, 147, 103, 222, 69, 181, 193, 246, 14, 233, 149, 236, 117, 652 | 117, 33, 255, 15, 136, 52, 18, 253}; 653 | 654 | static const struct element { 655 | uint32_t src; 656 | uint16_t w, h, x0, y0; 657 | } el[] = { 658 | { 0, 74, 145, 54, 48 }, 659 | { 5365, 110, 218, 18, 11 }, 660 | { 17355, 28, 29, 8, 66 }, 661 | { 17761, 28, 29, 8, 145 }, 662 | { 18167, 30, 28, 29, 45 }, 663 | { 18587, 30, 29, 29, 167 }, 664 | { 19022, 30, 28, 51, 23 }, 665 | { 19442, 30, 28, 51, 189 }, 666 | { 19862, 28, 28, 73, 1 }, 667 | { 20254, 28, 28, 73, 211 }, 668 | { 20646, 400, 149, 190, 47 }, 669 | { 50446, 194, 120, 597, 47 }, 670 | { 62086, 602, 29, 190, 183 } 671 | }; 672 | 673 | static int32_t scaling; 674 | static int16_t YOFFSET; 675 | 676 | #define FX16(x) ((int32_t)((x) * 65536.0f)) 677 | 678 | static int32_t tween(int32_t t, int32_t a, int32_t b) 679 | { 680 | uint16_t tu, tu2, tu3; 681 | if (t < 0) 682 | return a; 683 | if (t > 65535) 684 | return b; 685 | tu = t; 686 | tu = ~tu; 687 | tu2 = ((uint32_t)tu * tu) >> 16; 688 | tu3 = ((uint32_t)tu2 * tu) >> 16; 689 | tu3 = ~tu3; 690 | return a + (((int32_t)tu3 * (b - a)) >> 16); 691 | } 692 | 693 | int32_t dc(int16_t c) 694 | { 695 | return (scaling * c) >> 12; 696 | } 697 | static void setup_element(Gpu_Hal_Context_t *phost, const struct element *e) 698 | { 699 | App_WrCoCmd_Buffer(phost, BITMAP_SOURCE(e->src)); 700 | App_WrCoCmd_Buffer(phost, BITMAP_LAYOUT(L4, e->w / 2, e->h)); 701 | App_WrCoCmd_Buffer(phost, BITMAP_SIZE(BILINEAR,BORDER,BORDER,(dc(e->w) >> 4) + 1,(dc(e->h) >> 4) + 1)); 702 | #ifdef FT81X_ENABLE 703 | App_WrCoCmd_Buffer(phost, BITMAP_LAYOUT_H((e->w / 2)>>10, 0)); 704 | App_WrCoCmd_Buffer(phost, BITMAP_SIZE_H(((dc(e->w) >> 4) + 1)>>9, ((dc(e->h) >> 4) + 1)>>9)); 705 | #endif 706 | } 707 | 708 | static void draw(Gpu_Hal_Context_t *phost, const struct element *e, int32_t x) 709 | { 710 | setup_element(phost, e); 711 | App_WrCoCmd_Buffer(phost, VERTEX2F(dc(e->x0) + x, YOFFSET + dc(e->y0))); 712 | } 713 | 714 | void App_Show_Logo(Gpu_Hal_Context_t *phost) 715 | { 716 | uint16_t ff,frame,i; 717 | int32_t syo ; 718 | 719 | scaling = FX16(1) * DispWidth / 800; 720 | YOFFSET = ((DispHeight << 4) - dc(242)) / 2; 721 | syo = YOFFSET * (FX16(800 / 16) / DispWidth); 722 | 723 | Gpu_Hal_WrCmd32(phost,CMD_INFLATE); 724 | Gpu_Hal_WrCmd32(phost,0); 725 | Gpu_Hal_WrCmdBufFromFlash(phost, (uint8_t*)logo_graphics, sizeof(logo_graphics)); 726 | App_Flush_Co_Buffer(phost); 727 | Gpu_Hal_WaitCmdfifo_empty(phost); 728 | 729 | for (frame = 0, ff = 0; frame < 120; frame++, ff += 550) { 730 | Gpu_CoCmd_Dlstart(phost); 731 | App_WrCoCmd_Buffer(phost, CLEAR_COLOR_RGB(255,255,255)); 732 | App_WrCoCmd_Buffer(phost, CLEAR(1, 1, 1)); 733 | App_WrCoCmd_Buffer(phost, BITMAP_HANDLE(LOGO_ICON_HANDLE)); 734 | App_WrCoCmd_Buffer(phost, BEGIN(BITMAPS)); 735 | 736 | Gpu_CoCmd_LoadIdentity(phost); 737 | Gpu_CoCmd_Scale(phost, scaling, scaling); 738 | Gpu_CoCmd_SetMatrix(phost); 739 | 740 | App_WrCoCmd_Buffer(phost, COLOR_RGB( 35, 31, 32)); // gray 741 | for (i = 0; i < 10; i++) { 742 | if (i == 9) 743 | App_WrCoCmd_Buffer(phost, COLOR_RGB(237, 28, 36)); // red 744 | draw(phost, &el[i], tween((ff - FX16(.1)) * 3 - FX16(.1) * i, dc(-130), 0)); 745 | } 746 | 747 | App_WrCoCmd_Buffer(phost, COLOR_RGB( 56, 113, 193)); // blue 748 | App_WrCoCmd_Buffer(phost, SAVE_CONTEXT()); 749 | setup_element(phost, &el[10]); 750 | App_WrCoCmd_Buffer(phost, BITMAP_SIZE(BILINEAR, BORDER, BORDER, 0, 0)); 751 | Gpu_CoCmd_LoadIdentity(phost); 752 | Gpu_CoCmd_Scale(phost, scaling, scaling); 753 | Gpu_CoCmd_Translate(phost, (int32_t)el[10].x0 << 16, ((int32_t)el[10].y0 << 16) + syo + FX16(60)); 754 | Gpu_CoCmd_Rotate(phost, -tween((ff - FX16(.1)) * 2, 0x4000, 0x0000)); 755 | Gpu_CoCmd_Translate(phost, FX16(0), FX16(-60)); 756 | Gpu_CoCmd_SetMatrix(phost); 757 | App_WrCoCmd_Buffer(phost, VERTEX2F(0, 0)); 758 | App_WrCoCmd_Buffer(phost, RESTORE_CONTEXT()); 759 | 760 | draw(phost, &el[11], tween((ff - FX16(.4)) * 3, dc(210), 0)); 761 | 762 | App_WrCoCmd_Buffer(phost, COLOR_RGB( 35, 31, 32)); // gray 763 | App_WrCoCmd_Buffer(phost, COLOR_A(tween((ff - FX16(.75)) * 4, 0, 255))); 764 | draw(phost, &el[12], 0); 765 | 766 | App_WrCoCmd_Buffer(phost, DISPLAY()); 767 | 768 | Gpu_CoCmd_Swap(phost); 769 | App_Flush_Co_Buffer(phost); 770 | Gpu_Hal_WaitCmdfifo_empty(phost); 771 | } 772 | 773 | /* Show dummy clear screen to clean up logo after animation */ 774 | Gpu_CoCmd_Dlstart(phost); 775 | Gpu_ClearScreen(phost); 776 | App_Flush_Co_Buffer(phost); 777 | Gpu_Hal_WaitCmdfifo_empty(phost); 778 | Gpu_Hal_Sleep(20); 779 | } 780 | 781 | /******************************************************************************/ 782 | 783 | void App_Common_Init(Gpu_Hal_Context_t *phost) { 784 | Gpu_HalInit_t halinit; 785 | uint8_t chipid; 786 | 787 | Gpu_Hal_Init(&halinit); 788 | Gpu_Hal_Open(phost); 789 | 790 | Gpu_Hal_Powercycle(phost, TRUE); 791 | 792 | /* FT81x will be in SPI Single channel after POR 793 | If we are here with FT4222 in multi channel, then 794 | an explicit switch to single channel is essential 795 | */ 796 | #if (defined(FT81X_ENABLE)) || (defined(BT81X_ENABLE)) 797 | Gpu_Hal_SetSPI(phost, GPU_SPI_SINGLE_CHANNEL, GPU_SPI_ONEDUMMY); 798 | #endif 799 | 800 | // Gpu_HostCommand(phost,0x68); 801 | // Gpu_Hal_Sleep(300); 802 | 803 | /* access address 0 to wake up the chip */ 804 | //Gpu_HostCommand(phost, GPU_SLEEP_M); 805 | 806 | //Gpu_Hal_Sleep(300); 807 | 808 | #if (defined(EVE_2) && (defined(NTP_50)||defined(RTP_50)||defined(CTP_50)||defined(NTP_70)||defined(RTP_70)||defined(CTP_70))) 809 | Gpu_HostCommand(phost,GPU_INTERNAL_OSC); 810 | #else 811 | #if (defined(EVE_4_INTERNAL_OSC)) 812 | Gpu_HostCommand(phost, GPU_INTERNAL_OSC); 813 | #else 814 | Gpu_HostCommand(phost,GPU_EXTERNAL_OSC); 815 | #endif 816 | #endif 817 | 818 | Gpu_Hal_Sleep(100); 819 | Gpu_HostCommand(phost, GPU_ACTIVE_M); 820 | Gpu_Hal_Sleep(300); 821 | 822 | //Gpu_HostCommand(phost,GPU_EXTERNAL_OSC); 823 | //Gpu_HostCommand(phost,GPU_PLL_48M); 824 | //Gpu_81X_SelectSysCLK(phost, GPU_SYSCLK_72M); 825 | 826 | Gpu_Hal_Wr32(phost, REG_FREQUENCY, 72000000); 827 | 828 | uint32_t freq = Gpu_Hal_Rd32(phost, REG_FREQUENCY); 829 | 830 | Gpu_Hal_Wr8(phost, REG_TRIM, 25); 831 | 832 | /* read Register ID to check if chip ID series is correct */ 833 | chipid = Gpu_Hal_Rd8(phost, REG_ID); 834 | while (chipid != 0x7C) { 835 | chipid = Gpu_Hal_Rd8(phost, REG_ID); 836 | Gpu_Hal_Sleep(100); 837 | } 838 | 839 | /* read REG_CPURESET to confirm 0 is returned */ 840 | { 841 | uint8_t engine_status; 842 | 843 | /* Read REG_CPURESET to check if engines are ready. 844 | Bit 0 for coprocessor engine, 845 | Bit 1 for touch engine, 846 | Bit 2 for audio engine. 847 | */ 848 | engine_status = Gpu_Hal_Rd8(phost, REG_CPURESET); 849 | while (engine_status != 0x00) { 850 | engine_status = Gpu_Hal_Rd8(phost, REG_CPURESET); 851 | Gpu_Hal_Sleep(100); 852 | } 853 | } 854 | 855 | Gpu_Hal_Wr16(phost, REG_PWM_HZ, 4000); 856 | Gpu_Hal_Wr8(phost, REG_PWM_DUTY, 128); 857 | 858 | uint16_t pwmHz = Gpu_Hal_Rd16(phost, REG_PWM_HZ); 859 | 860 | #if defined (EVE_4) 861 | Gpu_Hal_Wr16(phost, REG_PCLK_FREQ, DispPLCLKFREQ); 862 | Gpu_Hal_Wr8(phost, REG_PCLK_2X, DispPCLK2x); 863 | #endif 864 | 865 | /* configuration of LCD display */ 866 | Gpu_Hal_Wr16(phost, REG_HCYCLE, DispHCycle); 867 | Gpu_Hal_Wr16(phost, REG_HOFFSET, DispHOffset); 868 | Gpu_Hal_Wr16(phost, REG_HSYNC0, DispHSync0); 869 | Gpu_Hal_Wr16(phost, REG_HSYNC1, DispHSync1); 870 | Gpu_Hal_Wr16(phost, REG_VCYCLE, DispVCycle); 871 | Gpu_Hal_Wr16(phost, REG_VOFFSET, DispVOffset); 872 | Gpu_Hal_Wr16(phost, REG_VSYNC0, DispVSync0); 873 | Gpu_Hal_Wr16(phost, REG_VSYNC1, DispVSync1); 874 | Gpu_Hal_Wr8(phost, REG_SWIZZLE, DispSwizzle); 875 | Gpu_Hal_Wr8(phost, REG_PCLK_POL, DispPCLKPol); 876 | Gpu_Hal_Wr16(phost, REG_HSIZE, DispWidth); 877 | Gpu_Hal_Wr16(phost, REG_VSIZE, DispHeight); 878 | Gpu_Hal_Wr16(phost, REG_CSPREAD, DispCSpread); 879 | Gpu_Hal_Wr16(phost, REG_DITHER, DispDither); 880 | 881 | /* GPIO configuration */ 882 | #if (defined(FT81X_ENABLE)) || (defined(BT81X_ENABLE)) 883 | Gpu_Hal_Wr16(phost, REG_GPIOX_DIR, 0xFFFF); 884 | Gpu_Hal_Wr16(phost, REG_GPIOX, 0xFFFF); 885 | #else 886 | Gpu_Hal_Wr8(phost, REG_GPIO_DIR, 0xFF); 887 | Gpu_Hal_Wr8(phost, REG_GPIO, 0xFF); 888 | #endif 889 | 890 | Gpu_ClearScreen(phost); 891 | 892 | /* after this display is visible on the LCD */ 893 | Gpu_Hal_Wr8(phost, REG_PCLK, DispPCLK); 894 | 895 | phost->cmd_fifo_wp = Gpu_Hal_Rd16(phost, REG_CMD_WRITE); 896 | } 897 | 898 | void App_Common_Close(Gpu_Hal_Context_t *phost) { 899 | Gpu_Hal_Close(phost); 900 | Gpu_Hal_DeInit(); 901 | } 902 | -------------------------------------------------------------------------------- /App_Common.h: -------------------------------------------------------------------------------- 1 | /* 2 | 3 | Copyright (c) Bridgetek Pte Ltd 4 | 5 | THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 6 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 7 | OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 8 | BRIDGETEK PTE LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 9 | SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 10 | OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) 11 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 12 | TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 13 | EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 14 | 15 | BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON BRIDGETEK PARTS. 16 | 17 | BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE INFORMATION IS NOT MODIFIED. 18 | 19 | IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, IT IS THE 20 | RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES AND SUBSEQUENT WHQL 21 | RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 22 | 23 | Author : BRIDGETEK 24 | 25 | Revision History: 26 | 0.1 - date 2017.02.23 - Initial version 27 | */ 28 | 29 | #ifndef _APP_COMMON_H_ 30 | #define _APP_COMMON_H_ 31 | 32 | #if defined(FT80X_ENABLE) 33 | #define RAM_G_END_ADDR 0x40000 //General purpose graphics RAM 256 kB 34 | #elif defined(FT81X_ENABLE) 35 | #define RAM_G_END_ADDR (0x100000) //General purpose graphics RAM 1024 kB 36 | #elif defined(BT81X_ENABLE) 37 | #define RAM_G_END_ADDR (0x100000) //General purpose graphics RAM 1024 kB 38 | #else 39 | #error "Should select a GPU chip in Platform.h" 40 | #endif 41 | 42 | #define SIZE_HOME_START_ICON (460) 43 | #define SIZE_LOGO (6703) 44 | 45 | #define START_ICON_ADDR (RAM_G_END_ADDR - SIZE_HOME_START_ICON*6) //*6 to Reserve space for inflate images. 46 | #define LOGO_ADDR (START_ICON_ADDR - SIZE_LOGO) 47 | 48 | #define START_ICON_HANDLE 14 49 | #define LOGO_ICON_HANDLE 15 50 | 51 | /******************************************************************************/ 52 | 53 | void App_WrCoCmd_Buffer(Gpu_Hal_Context_t *phost,uint32_t cmd); 54 | void App_WrDl_Buffer(Gpu_Hal_Context_t *phost,uint32_t cmd); 55 | void App_WrCoStr_Buffer(Gpu_Hal_Context_t *phost,const char8_t *s); 56 | void App_Flush_DL_Buffer(Gpu_Hal_Context_t *phost); 57 | void App_Flush_Co_Buffer(Gpu_Hal_Context_t *phost); 58 | void App_Flush_Co_Buffer_nowait(Gpu_Hal_Context_t *phost); 59 | void App_Set_DlBuffer_Index(uint32_t index); 60 | void App_Set_CmdBuffer_Index(uint32_t index); 61 | 62 | /******************************************************************************/ 63 | 64 | uint8_t App_Read_Tag(Gpu_Hal_Context_t *phost); 65 | uint8_t App_Touch_Update(Gpu_Hal_Context_t *phost, uint8_t *currTag, uint16_t *x, uint16_t *y); 66 | void App_Play_Sound(Gpu_Hal_Context_t *phost, uint8_t sound,uint8_t vol,uint8_t midi); 67 | void App_Calibrate_Screen(Gpu_Hal_Context_t *phost); 68 | void App_Show_Logo(Gpu_Hal_Context_t *phost); 69 | 70 | /******************************************************************************/ 71 | 72 | void App_Common_Init(Gpu_Hal_Context_t *phost); 73 | void App_Common_Close(Gpu_Hal_Context_t *phost); 74 | 75 | #endif /* _APP_COMMON_H_ */ 76 | -------------------------------------------------------------------------------- /CoPro_Cmds.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Bridgetek Pte Ltd 3 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 4 | * Copyright (c) Skalski Embedded Technologies 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 7 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 8 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9 | * ARE DISCLAIMED. IN NO EVENT SHALL BRIDGETEK PTE LTD BE LIABLE FOR ANY 10 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES 12 | * LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 13 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 14 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 15 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | * 17 | * BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON 18 | * BRIDGETEK PARTS. 19 | * 20 | * BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE 21 | * INFORMATION IS NOT MODIFIED. 22 | * 23 | * IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, 24 | * IT IS THE RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES 25 | * AND SUBSEQUENT WHQL RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 26 | */ 27 | 28 | #include "Platform.h" 29 | #include "App_Common.h" 30 | 31 | #ifdef BT81X_ENABLE 32 | static uint8_t COUNT_ARGS(const char* str) 33 | { 34 | uint8_t count = 0; 35 | const char *tmp = str; 36 | 37 | while ((tmp = strstr(tmp, "%"))) 38 | { 39 | if (*(tmp + 1) == '%') 40 | { 41 | tmp += 2; 42 | } 43 | else 44 | { 45 | count++; 46 | tmp++; 47 | } 48 | } 49 | return count; 50 | } 51 | #endif 52 | 53 | void Gpu_CoCmd_Text(Gpu_Hal_Context_t *phost, int16_t x, int16_t y, int16_t font, uint16_t options, const char8_t* s, ...) 54 | { 55 | va_list args; 56 | uint8_t i, num=0; 57 | uint8_t len = strlen(s); 58 | 59 | va_start(args, s); 60 | 61 | #ifdef BT81X_ENABLE 62 | num = (options & OPT_FORMAT) ? (COUNT_ARGS(s)) : (0); 63 | #endif 64 | 65 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * (3+ num) + ((len + 1 + 3) & ~3)); 66 | Gpu_Copro_SendCmd(phost, CMD_TEXT); 67 | Gpu_Copro_SendCmd(phost, (((uint32_t)y << 16) | (x & 0xffff))); 68 | Gpu_Copro_SendCmd(phost, (((uint32_t)options << 16) | (font & 0xffff))); 69 | Gpu_CoCmd_SendStr(phost, s); 70 | 71 | for (i = 0; i < num; i++) 72 | Gpu_Copro_SendCmd(phost, (uint32_t)va_arg(args, uint32_t)); 73 | 74 | Gpu_CoCmd_EndFunc(phost, CMD_SIZE * (3+ num) + ((len + 1 + 3) & ~3)); 75 | va_end(args); 76 | } 77 | 78 | void Gpu_CoCmd_Number(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t font, uint16_t options, int32_t n) 79 | { 80 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 81 | Gpu_Copro_SendCmd(phost, CMD_NUMBER); 82 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 83 | Gpu_Copro_SendCmd(phost, (((uint32_t)options<<16)|(font&0xffff))); 84 | Gpu_Copro_SendCmd(phost, n); 85 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 86 | } 87 | 88 | void Gpu_CoCmd_LoadIdentity(Gpu_Hal_Context_t *phost) 89 | { 90 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 91 | Gpu_Copro_SendCmd(phost, CMD_LOADIDENTITY); 92 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 93 | } 94 | 95 | void Gpu_CoCmd_Toggle(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t font, uint16_t options, uint16_t state, const char8_t* s, ...) 96 | { 97 | va_list args; 98 | uint8_t i, num = 0; 99 | 100 | va_start(args, s); 101 | 102 | #ifdef BT81X_ENABLE 103 | num = (options & OPT_FORMAT) ? (COUNT_ARGS(s)) : (0); 104 | #endif 105 | 106 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*(4 + num) + strlen(s) + 1); 107 | Gpu_Copro_SendCmd(phost, CMD_TOGGLE); 108 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 109 | Gpu_Copro_SendCmd(phost, (((uint32_t)font<<16)|(w&0xffff))); 110 | Gpu_Copro_SendCmd(phost, (((uint32_t)state<<16)|options)); 111 | Gpu_CoCmd_SendStr(phost, s); 112 | 113 | for (i = 0; i < num; i++) 114 | Gpu_Copro_SendCmd(phost, (uint32_t)va_arg(args, uint32_t)); 115 | 116 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*(4 + num) + strlen(s) + 1)); 117 | va_end(args); 118 | } 119 | 120 | void Gpu_CoCmd_Gauge(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t r, uint16_t options, uint16_t major, uint16_t minor, uint16_t val, uint16_t range) 121 | { 122 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 123 | Gpu_Copro_SendCmd(phost, CMD_GAUGE); 124 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 125 | Gpu_Copro_SendCmd(phost, (((uint32_t)options<<16)|(r&0xffff))); 126 | Gpu_Copro_SendCmd(phost, (((uint32_t)minor<<16)|(major&0xffff))); 127 | Gpu_Copro_SendCmd(phost, (((uint32_t)range<<16)|(val&0xffff))); 128 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 129 | } 130 | 131 | void Gpu_CoCmd_RegRead(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t result) 132 | { 133 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 134 | Gpu_Copro_SendCmd(phost, CMD_REGREAD); 135 | Gpu_Copro_SendCmd(phost, ptr); 136 | Gpu_Copro_SendCmd(phost, 0); 137 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 138 | } 139 | 140 | void Gpu_CoCmd_GetProps(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t w, uint32_t h) 141 | { 142 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 143 | Gpu_Copro_SendCmd(phost, CMD_GETPROPS); 144 | Gpu_Copro_SendCmd(phost, ptr); 145 | Gpu_Copro_SendCmd(phost, w); 146 | Gpu_Copro_SendCmd(phost, h); 147 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 148 | } 149 | 150 | void Gpu_CoCmd_Memcpy(Gpu_Hal_Context_t *phost,uint32_t dest, uint32_t src, uint32_t num) 151 | { 152 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 153 | Gpu_Copro_SendCmd(phost, CMD_MEMCPY); 154 | Gpu_Copro_SendCmd(phost, dest); 155 | Gpu_Copro_SendCmd(phost, src); 156 | Gpu_Copro_SendCmd(phost, num); 157 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 158 | } 159 | 160 | void Gpu_CoCmd_Spinner(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, uint16_t style, uint16_t scale) 161 | { 162 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 163 | Gpu_Copro_SendCmd(phost, CMD_SPINNER); 164 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 165 | Gpu_Copro_SendCmd(phost, (((uint32_t)scale<<16)|(style&0xffff))); 166 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 167 | } 168 | 169 | void Gpu_CoCmd_BgColor(Gpu_Hal_Context_t *phost,uint32_t c) 170 | { 171 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 172 | Gpu_Copro_SendCmd(phost, CMD_BGCOLOR); 173 | Gpu_Copro_SendCmd(phost, c); 174 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 175 | } 176 | 177 | void Gpu_CoCmd_Swap(Gpu_Hal_Context_t *phost) 178 | { 179 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 180 | Gpu_Copro_SendCmd(phost, CMD_SWAP); 181 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 182 | } 183 | 184 | void Gpu_CoCmd_Inflate(Gpu_Hal_Context_t *phost,uint32_t ptr) 185 | { 186 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 187 | Gpu_Copro_SendCmd(phost, CMD_INFLATE); 188 | Gpu_Copro_SendCmd(phost, ptr); 189 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 190 | } 191 | 192 | void Gpu_CoCmd_Translate(Gpu_Hal_Context_t *phost,int32_t tx, int32_t ty) 193 | { 194 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 195 | Gpu_Copro_SendCmd(phost, CMD_TRANSLATE); 196 | Gpu_Copro_SendCmd(phost, tx); 197 | Gpu_Copro_SendCmd(phost, ty); 198 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 199 | } 200 | 201 | void Gpu_CoCmd_Stop(Gpu_Hal_Context_t *phost) 202 | { 203 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 204 | Gpu_Copro_SendCmd(phost, CMD_STOP); 205 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 206 | } 207 | 208 | void Gpu_CoCmd_Slider(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, uint16_t options, uint16_t val, uint16_t range) 209 | { 210 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 211 | Gpu_Copro_SendCmd(phost, CMD_SLIDER); 212 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 213 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 214 | Gpu_Copro_SendCmd(phost, (((uint32_t)val<<16)|(options&0xffff))); 215 | Gpu_Copro_SendCmd(phost, range); 216 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 217 | } 218 | 219 | void Gpu_CoCmd_TouchTransform(Gpu_Hal_Context_t *phost,int32_t x0, int32_t y0, int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t tx0, int32_t ty0, int32_t tx1, int32_t ty1, int32_t tx2, int32_t ty2, uint16_t result) 220 | { 221 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*6*2+CMD_SIZE*2); 222 | Gpu_Copro_SendCmd(phost, CMD_TOUCH_TRANSFORM); 223 | Gpu_Copro_SendCmd(phost, x0); 224 | Gpu_Copro_SendCmd(phost, y0); 225 | Gpu_Copro_SendCmd(phost, x1); 226 | Gpu_Copro_SendCmd(phost, y1); 227 | Gpu_Copro_SendCmd(phost, x2); 228 | Gpu_Copro_SendCmd(phost, y2); 229 | Gpu_Copro_SendCmd(phost, tx0); 230 | Gpu_Copro_SendCmd(phost, ty0); 231 | Gpu_Copro_SendCmd(phost, tx1); 232 | Gpu_Copro_SendCmd(phost, ty1); 233 | Gpu_Copro_SendCmd(phost, tx2); 234 | Gpu_Copro_SendCmd(phost, ty2); 235 | Gpu_Copro_SendCmd(phost, result); 236 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*6*2+CMD_SIZE*2)); 237 | } 238 | 239 | void Gpu_CoCmd_Interrupt(Gpu_Hal_Context_t *phost,uint32_t ms) 240 | { 241 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 242 | Gpu_Copro_SendCmd(phost, CMD_INTERRUPT); 243 | Gpu_Copro_SendCmd(phost, ms); 244 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 245 | } 246 | 247 | void Gpu_CoCmd_FgColor(Gpu_Hal_Context_t *phost,uint32_t c) 248 | { 249 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 250 | Gpu_Copro_SendCmd(phost, CMD_FGCOLOR); 251 | Gpu_Copro_SendCmd(phost, c); 252 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 253 | } 254 | 255 | void Gpu_CoCmd_Rotate(Gpu_Hal_Context_t *phost,int32_t a) 256 | { 257 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 258 | Gpu_Copro_SendCmd(phost, CMD_ROTATE); 259 | Gpu_Copro_SendCmd(phost, a); 260 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 261 | } 262 | 263 | void Gpu_CoCmd_Button(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, int16_t font, uint16_t options, const char8_t* s, ...) 264 | { 265 | va_list args; 266 | uint8_t i, num = 0; 267 | 268 | va_start(args, s); 269 | 270 | #ifdef BT81X_ENABLE 271 | num = (options & OPT_FORMAT) ? (COUNT_ARGS(s)) : (0); 272 | #endif 273 | 274 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*(4 + num) + strlen(s) + 1); 275 | Gpu_Copro_SendCmd(phost, CMD_BUTTON); 276 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 277 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 278 | Gpu_Copro_SendCmd(phost, (((uint32_t)options<<16)|(font&0xffff))); 279 | Gpu_CoCmd_SendStr(phost, s); 280 | 281 | for (i = 0; i < num; i++) 282 | Gpu_Copro_SendCmd(phost, (uint32_t)va_arg(args, uint32_t)); 283 | 284 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*(4 + num) + strlen(s) + 1)); 285 | va_end(args); 286 | } 287 | 288 | void Gpu_CoCmd_MemWrite(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num) 289 | { 290 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 291 | Gpu_Copro_SendCmd(phost, CMD_MEMWRITE); 292 | Gpu_Copro_SendCmd(phost, ptr); 293 | Gpu_Copro_SendCmd(phost, num); 294 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 295 | } 296 | 297 | void Gpu_CoCmd_Scrollbar(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, uint16_t options, uint16_t val, uint16_t size, uint16_t range) 298 | { 299 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 300 | Gpu_Copro_SendCmd(phost, CMD_SCROLLBAR); 301 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 302 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 303 | Gpu_Copro_SendCmd(phost, (((uint32_t)val<<16)|(options&0xffff))); 304 | Gpu_Copro_SendCmd(phost, (((uint32_t)range<<16)|(size&0xffff))); 305 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 306 | } 307 | 308 | void Gpu_CoCmd_GetMatrix(Gpu_Hal_Context_t *phost,int32_t a, int32_t b, int32_t c, int32_t d, int32_t e, int32_t f) 309 | { 310 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*7); 311 | Gpu_Copro_SendCmd(phost, CMD_GETMATRIX); 312 | Gpu_Copro_SendCmd(phost, a); 313 | Gpu_Copro_SendCmd(phost, b); 314 | Gpu_Copro_SendCmd(phost, c); 315 | Gpu_Copro_SendCmd(phost, d); 316 | Gpu_Copro_SendCmd(phost, e); 317 | Gpu_Copro_SendCmd(phost, f); 318 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*7)); 319 | } 320 | 321 | void Gpu_CoCmd_Sketch(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, uint16_t w, uint16_t h, uint32_t ptr, uint16_t format) 322 | { 323 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 324 | Gpu_Copro_SendCmd(phost, CMD_SKETCH); 325 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 326 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 327 | Gpu_Copro_SendCmd(phost, ptr); 328 | Gpu_Copro_SendCmd(phost, format); 329 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 330 | } 331 | 332 | void Gpu_CoCmd_MemSet(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t value, uint32_t num) 333 | { 334 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 335 | Gpu_Copro_SendCmd(phost, CMD_MEMSET); 336 | Gpu_Copro_SendCmd(phost, ptr); 337 | Gpu_Copro_SendCmd(phost, value); 338 | Gpu_Copro_SendCmd(phost, num); 339 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 340 | } 341 | 342 | void Gpu_CoCmd_GradColor(Gpu_Hal_Context_t *phost,uint32_t c) 343 | { 344 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 345 | Gpu_Copro_SendCmd(phost, CMD_GRADCOLOR); 346 | Gpu_Copro_SendCmd(phost, c); 347 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 348 | } 349 | 350 | void Gpu_CoCmd_BitmapTransform(Gpu_Hal_Context_t *phost,int32_t x0, int32_t y0, int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t tx0, int32_t ty0, int32_t tx1, int32_t ty1, int32_t tx2, int32_t ty2, uint16_t result) 351 | { 352 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*6*2+CMD_SIZE*2); 353 | Gpu_Copro_SendCmd(phost, CMD_BITMAP_TRANSFORM); 354 | Gpu_Copro_SendCmd(phost, x0); 355 | Gpu_Copro_SendCmd(phost, y0); 356 | Gpu_Copro_SendCmd(phost, x1); 357 | Gpu_Copro_SendCmd(phost, y1); 358 | Gpu_Copro_SendCmd(phost, x2); 359 | Gpu_Copro_SendCmd(phost, y2); 360 | Gpu_Copro_SendCmd(phost, tx0); 361 | Gpu_Copro_SendCmd(phost, ty0); 362 | Gpu_Copro_SendCmd(phost, tx1); 363 | Gpu_Copro_SendCmd(phost, ty1); 364 | Gpu_Copro_SendCmd(phost, tx2); 365 | Gpu_Copro_SendCmd(phost, ty2); 366 | Gpu_Copro_SendCmd(phost, result); 367 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*6*2+CMD_SIZE*2)); 368 | } 369 | 370 | void Gpu_CoCmd_Calibrate(Gpu_Hal_Context_t *phost,uint32_t result) 371 | { 372 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 373 | Gpu_Copro_SendCmd(phost, CMD_CALIBRATE); 374 | Gpu_Copro_SendCmd(phost, result); 375 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 376 | Gpu_Hal_WaitCmdfifo_empty(phost); 377 | } 378 | 379 | void Gpu_CoCmd_SetFont(Gpu_Hal_Context_t *phost,uint32_t font, uint32_t ptr) 380 | { 381 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 382 | Gpu_Copro_SendCmd(phost, CMD_SETFONT); 383 | Gpu_Copro_SendCmd(phost, font); 384 | Gpu_Copro_SendCmd(phost, ptr); 385 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 386 | } 387 | 388 | void Gpu_CoCmd_Logo(Gpu_Hal_Context_t *phost) 389 | { 390 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 391 | Gpu_Copro_SendCmd(phost, CMD_LOGO); 392 | Gpu_CoCmd_EndFunc(phost,CMD_SIZE*1); 393 | } 394 | 395 | void Gpu_CoCmd_Append(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num) 396 | { 397 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 398 | Gpu_Copro_SendCmd(phost, CMD_APPEND); 399 | Gpu_Copro_SendCmd(phost, ptr); 400 | Gpu_Copro_SendCmd(phost, num); 401 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 402 | } 403 | 404 | void Gpu_CoCmd_MemZero(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num) 405 | { 406 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 407 | Gpu_Copro_SendCmd(phost, CMD_MEMZERO); 408 | Gpu_Copro_SendCmd(phost, ptr); 409 | Gpu_Copro_SendCmd(phost, num); 410 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 411 | } 412 | 413 | void Gpu_CoCmd_Scale(Gpu_Hal_Context_t *phost,int32_t sx, int32_t sy) 414 | { 415 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 416 | Gpu_Copro_SendCmd(phost, CMD_SCALE); 417 | Gpu_Copro_SendCmd(phost, sx); 418 | Gpu_Copro_SendCmd(phost, sy); 419 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 420 | } 421 | 422 | void Gpu_CoCmd_Clock(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t r, uint16_t options, uint16_t h, uint16_t m, uint16_t s, uint16_t ms) 423 | { 424 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 425 | Gpu_Copro_SendCmd(phost, CMD_CLOCK); 426 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 427 | Gpu_Copro_SendCmd(phost, (((uint32_t)options<<16)|(r&0xffff))); 428 | Gpu_Copro_SendCmd(phost, (((uint32_t)m<<16)|(h&0xffff))); 429 | Gpu_Copro_SendCmd(phost, (((uint32_t)ms<<16)|(s&0xffff))); 430 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 431 | } 432 | 433 | void Gpu_CoCmd_Gradient(Gpu_Hal_Context_t *phost,int16_t x0, int16_t y0, uint32_t rgb0, int16_t x1, int16_t y1, uint32_t rgb1) 434 | { 435 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 436 | Gpu_Copro_SendCmd(phost, CMD_GRADIENT); 437 | Gpu_Copro_SendCmd(phost, (((uint32_t)y0<<16)|(x0 & 0xffff))); 438 | Gpu_Copro_SendCmd(phost, rgb0); 439 | Gpu_Copro_SendCmd(phost, (((uint32_t)y1<<16)|(x1 & 0xffff))); 440 | Gpu_Copro_SendCmd(phost, rgb1); 441 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 442 | } 443 | 444 | void Gpu_CoCmd_SetMatrix(Gpu_Hal_Context_t *phost) 445 | { 446 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 447 | Gpu_Copro_SendCmd(phost, CMD_SETMATRIX); 448 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 449 | } 450 | 451 | void Gpu_CoCmd_Track(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, int16_t tag) 452 | { 453 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 454 | Gpu_Copro_SendCmd(phost, CMD_TRACK); 455 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 456 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 457 | Gpu_Copro_SendCmd(phost, tag); 458 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 459 | } 460 | 461 | void Gpu_CoCmd_GetPtr(Gpu_Hal_Context_t *phost,uint32_t result) 462 | { 463 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 464 | Gpu_Copro_SendCmd(phost, CMD_GETPTR); 465 | Gpu_Copro_SendCmd(phost, result); 466 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 467 | } 468 | 469 | void Gpu_CoCmd_Progress(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, uint16_t options, uint16_t val, uint16_t range) 470 | { 471 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 472 | Gpu_Copro_SendCmd(phost, CMD_PROGRESS); 473 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 474 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 475 | Gpu_Copro_SendCmd(phost, (((uint32_t)val<<16)|(options&0xffff))); 476 | Gpu_Copro_SendCmd(phost, range); 477 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 478 | } 479 | 480 | void Gpu_CoCmd_ColdStart(Gpu_Hal_Context_t *phost) 481 | { 482 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 483 | Gpu_Copro_SendCmd(phost, CMD_COLDSTART); 484 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 485 | } 486 | 487 | void Gpu_CoCmd_Keys(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, int16_t font, uint16_t options, const char8_t* s) 488 | { 489 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4 + strlen(s) + 1); 490 | Gpu_Copro_SendCmd(phost, CMD_KEYS); 491 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 492 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 493 | Gpu_Copro_SendCmd(phost, (((uint32_t)options<<16)|(font&0xffff))); 494 | Gpu_CoCmd_SendStr(phost, s); 495 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4 + strlen(s) + 1)); 496 | } 497 | 498 | void Gpu_CoCmd_Dial(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t r, uint16_t options, uint16_t val) 499 | { 500 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 501 | Gpu_Copro_SendCmd(phost, CMD_DIAL); 502 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 503 | Gpu_Copro_SendCmd(phost, (((uint32_t)options<<16)|(r&0xffff))); 504 | Gpu_Copro_SendCmd(phost, val); 505 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 506 | } 507 | 508 | void Gpu_CoCmd_LoadImage(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t options) 509 | { 510 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 511 | Gpu_Copro_SendCmd(phost, CMD_LOADIMAGE); 512 | Gpu_Copro_SendCmd(phost, ptr); 513 | Gpu_Copro_SendCmd(phost, options); 514 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 515 | } 516 | 517 | void Gpu_CoCmd_Dlstart(Gpu_Hal_Context_t *phost) 518 | { 519 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 520 | Gpu_Copro_SendCmd(phost, CMD_DLSTART); 521 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 522 | } 523 | 524 | void Gpu_CoCmd_Snapshot(Gpu_Hal_Context_t *phost,uint32_t ptr) 525 | { 526 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 527 | Gpu_Copro_SendCmd(phost, CMD_SNAPSHOT); 528 | Gpu_Copro_SendCmd(phost, ptr); 529 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 530 | } 531 | 532 | void Gpu_CoCmd_ScreenSaver(Gpu_Hal_Context_t *phost) 533 | { 534 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 535 | Gpu_Copro_SendCmd(phost, CMD_SCREENSAVER); 536 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 537 | } 538 | 539 | void Gpu_CoCmd_MemCrc(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num, uint32_t result) 540 | { 541 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 542 | Gpu_Copro_SendCmd(phost, CMD_MEMCRC); 543 | Gpu_Copro_SendCmd(phost, ptr); 544 | Gpu_Copro_SendCmd(phost, num); 545 | Gpu_Copro_SendCmd(phost, result); 546 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 547 | } 548 | 549 | uint32_t GET_ASTC_FORMAT(uint16_t w, uint16_t h) 550 | { 551 | #ifdef BT81X_ENABLE 552 | if ((w == 4) && (h == 4)) return COMPRESSED_RGBA_ASTC_4x4_KHR; 553 | else if ((w == 5) && (h == 4)) return COMPRESSED_RGBA_ASTC_5x4_KHR; 554 | else if ((w == 5) && (h == 5)) return COMPRESSED_RGBA_ASTC_5x5_KHR; 555 | else if ((w == 6) && (h == 5)) return COMPRESSED_RGBA_ASTC_6x5_KHR; 556 | else if ((w == 6) && (h == 6)) return COMPRESSED_RGBA_ASTC_6x6_KHR; 557 | else if ((w == 8) && (h == 5)) return COMPRESSED_RGBA_ASTC_8x5_KHR; 558 | else if ((w == 8) && (h == 6)) return COMPRESSED_RGBA_ASTC_8x6_KHR; 559 | else if ((w == 8) && (h == 8)) return COMPRESSED_RGBA_ASTC_8x8_KHR; 560 | else if ((w == 10) && (h == 5)) return COMPRESSED_RGBA_ASTC_10x5_KHR; 561 | else if ((w == 10) && (h == 6)) return COMPRESSED_RGBA_ASTC_10x6_KHR; 562 | else if ((w == 10) && (h == 8)) return COMPRESSED_RGBA_ASTC_10x8_KHR; 563 | else if ((w == 10) && (h == 10)) return COMPRESSED_RGBA_ASTC_10x10_KHR; 564 | else if ((w == 12) && (h == 10)) return COMPRESSED_RGBA_ASTC_12x10_KHR; 565 | else if ((w == 12) && (h == 12)) return COMPRESSED_RGBA_ASTC_12x12_KHR; 566 | else return 0; 567 | #else 568 | return 0; 569 | #endif 570 | } 571 | 572 | void astc_tile2(uint8_t *iData, uint16_t bw, uint16_t bh, uint32_t size, uint8_t *oData) 573 | { 574 | uint32_t i, j, next; 575 | uint8_t *d, *r; 576 | 577 | d = iData; 578 | r = oData; 579 | 580 | for (j = 0; j < bh - 1; j += 2) 581 | { 582 | for (i = 0; i < bw; i += 2) 583 | { 584 | if (i < (bw - 1)) 585 | { 586 | next = 16 * (bw * j + i); 587 | memcpy(r, d + next, 16); 588 | r += 16; 589 | 590 | next = 16 * (bw * (j + 1) + i); 591 | memcpy(r, d + next, 16); 592 | r += 16; 593 | 594 | next = 16 * (bw * (j + 1) + (i + 1)); 595 | memcpy(r, d + next, 16); 596 | r += 16; 597 | 598 | next = 16 * (bw * j + (i + 1)); 599 | memcpy(r, d + next, 16); 600 | r += 16; 601 | } 602 | else 603 | { 604 | next = 16 * (bw * j + i); 605 | memcpy(r, d + next, 16); 606 | r += 16; 607 | 608 | next = 16 * (bw * (j + 1) + i); 609 | memcpy(r, d + next, 16); 610 | r += 16; 611 | } 612 | } 613 | } 614 | 615 | if (bh & 1) 616 | { 617 | for (i = bw * (bh - 1); i < (size)/16 ; i += 1) 618 | { 619 | next = 16 * i; 620 | memcpy(r, d + next, 16); 621 | r += 16; 622 | } 623 | } 624 | } 625 | 626 | #ifdef FT81X_ENABLE 627 | void Gpu_CoCmd_SetBitmap(Gpu_Hal_Context_t *phost,uint32_t source, uint16_t fmt, uint16_t w, uint16_t h) 628 | { 629 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 630 | Gpu_Copro_SendCmd(phost, CMD_SETBITMAP); 631 | Gpu_Copro_SendCmd(phost, source); 632 | Gpu_Copro_SendCmd(phost, (((uint32_t)w<<16)|(fmt & 0xffff))); 633 | Gpu_Copro_SendCmd(phost, h); 634 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 635 | } 636 | 637 | void Gpu_CoCmd_SetScratch(Gpu_Hal_Context_t *phost,uint32_t handle) 638 | { 639 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 640 | Gpu_Copro_SendCmd(phost, CMD_SETSCRATCH); 641 | Gpu_Copro_SendCmd(phost, handle); 642 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 643 | } 644 | 645 | void Gpu_CoCmd_VideoStart(Gpu_Hal_Context_t *phost) 646 | { 647 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 648 | Gpu_Copro_SendCmd(phost, CMD_VIDEOSTART); 649 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 650 | } 651 | 652 | void Gpu_CoCmd_SetBase(Gpu_Hal_Context_t *phost,uint32_t base) 653 | { 654 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 655 | Gpu_Copro_SendCmd(phost, CMD_SETBASE); 656 | Gpu_Copro_SendCmd(phost, base); 657 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 658 | } 659 | 660 | void Gpu_CoCmd_VideoFrame(Gpu_Hal_Context_t *phost,uint32_t dst, uint32_t ptr) 661 | { 662 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 663 | Gpu_Copro_SendCmd(phost, CMD_VIDEOFRAME); 664 | Gpu_Copro_SendCmd(phost, dst); 665 | Gpu_Copro_SendCmd(phost, ptr); 666 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 667 | } 668 | 669 | void Gpu_CoCmd_RomFont(Gpu_Hal_Context_t *phost,uint32_t font, uint32_t romslot) 670 | { 671 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 672 | Gpu_Copro_SendCmd(phost, CMD_ROMFONT); 673 | Gpu_Copro_SendCmd(phost, font); 674 | Gpu_Copro_SendCmd(phost, romslot); 675 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 676 | } 677 | 678 | void Gpu_CoCmd_PlayVideo(Gpu_Hal_Context_t *phost,uint32_t options) 679 | { 680 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 681 | Gpu_Copro_SendCmd(phost, CMD_PLAYVIDEO); 682 | Gpu_Copro_SendCmd(phost, options); 683 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 684 | } 685 | 686 | void Gpu_CoCmd_Sync(Gpu_Hal_Context_t *phost) 687 | { 688 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*1); 689 | Gpu_Copro_SendCmd(phost, CMD_SYNC); 690 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*1)); 691 | } 692 | 693 | void Gpu_CoCmd_Int_RAMShared(Gpu_Hal_Context_t *phost,uint32_t ptr) 694 | { 695 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 696 | Gpu_Copro_SendCmd(phost, CMD_INT_RAMSHARED); 697 | Gpu_Copro_SendCmd(phost, ptr); 698 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 699 | } 700 | 701 | void Gpu_CoCmd_Int_SWLoadImage(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t options) 702 | { 703 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 704 | Gpu_Copro_SendCmd(phost, CMD_INT_SWLOADIMAGE); 705 | Gpu_Copro_SendCmd(phost, ptr); 706 | Gpu_Copro_SendCmd(phost, options); 707 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 708 | } 709 | 710 | void Gpu_CoCmd_MediaFifo(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t size) 711 | { 712 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 713 | Gpu_Copro_SendCmd(phost, CMD_MEDIAFIFO); 714 | Gpu_Copro_SendCmd(phost, ptr); 715 | Gpu_Copro_SendCmd(phost, size); 716 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 717 | } 718 | 719 | void Gpu_CoCmd_Snapshot2(Gpu_Hal_Context_t *phost,uint32_t fmt, uint32_t ptr, int16_t x, int16_t y, int16_t w, int16_t h) 720 | { 721 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 722 | Gpu_Copro_SendCmd(phost, CMD_SNAPSHOT2); 723 | Gpu_Copro_SendCmd(phost, fmt); 724 | Gpu_Copro_SendCmd(phost, ptr); 725 | Gpu_Copro_SendCmd(phost, (((uint32_t)y<<16)|(x & 0xffff))); 726 | Gpu_Copro_SendCmd(phost, (((uint32_t)h<<16)|(w&0xffff))); 727 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 728 | } 729 | 730 | void Gpu_CoCmd_SetFont2(Gpu_Hal_Context_t *phost,uint32_t font, uint32_t ptr, uint32_t firstchar) 731 | { 732 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 733 | Gpu_Copro_SendCmd(phost, CMD_SETFONT2); 734 | Gpu_Copro_SendCmd(phost, font); 735 | Gpu_Copro_SendCmd(phost, ptr); 736 | Gpu_Copro_SendCmd(phost, firstchar); 737 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 738 | } 739 | 740 | void Gpu_CoCmd_SetRotate(Gpu_Hal_Context_t *phost,uint32_t r) 741 | { 742 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 743 | Gpu_Copro_SendCmd(phost, CMD_SETROTATE); 744 | Gpu_Copro_SendCmd(phost, r); 745 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 746 | } 747 | 748 | void Set_GpuClock(Gpu_Hal_Context_t *phost) 749 | { 750 | static uint32_t x = 1; 751 | 752 | Gpu_CoCmd_Sync(phost); 753 | Gpu_CoCmd_Memcpy(phost, x * 4, REG_CLOCK, 4); 754 | App_Flush_Co_Buffer(phost); 755 | Gpu_Hal_WaitCmdfifo_empty(phost); 756 | 757 | x = x ^ 1; 758 | } 759 | 760 | uint32_t Get_GpuClock(Gpu_Hal_Context_t *phost) 761 | { 762 | uint32_t a = Gpu_Hal_Rd32(phost, 0); 763 | uint32_t b = Gpu_Hal_Rd32(phost, 4); 764 | 765 | return (a < b) ? (b - a) : (a - b); 766 | } 767 | #endif /* FT81X_ENABLE */ 768 | 769 | #ifdef BT81X_ENABLE 770 | void Gpu_CoCmd_VideoStartF(Gpu_Hal_Context_t *phost) 771 | { 772 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 1); 773 | Gpu_Copro_SendCmd(phost, CMD_VIDEOSTARTF); 774 | Gpu_CoCmd_EndFunc(phost, (CMD_SIZE * 1)); 775 | } 776 | 777 | void Gpu_CoCmd_FillWidth(Gpu_Hal_Context_t *phost, uint32_t s) 778 | { 779 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 780 | Gpu_Copro_SendCmd(phost, CMD_FILLWIDTH); 781 | Gpu_Copro_SendCmd(phost, s); 782 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 783 | } 784 | 785 | void Gpu_CoCmd_Nop(Gpu_Hal_Context_t *phost) 786 | { 787 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 788 | Gpu_Copro_SendCmd(phost, CMD_NOP); 789 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 790 | } 791 | 792 | void Gpu_CoCmd_GetPoint(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, uint32_t sx, uint32_t sy) 793 | { 794 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 795 | Gpu_Copro_SendCmd(phost, CMD_GETPOINT); 796 | Gpu_Copro_SendCmd(phost, ((uint32_t)y<<16) |(x & 0xFFFF)); 797 | Gpu_Copro_SendCmd(phost, sx); 798 | Gpu_Copro_SendCmd(phost, sy); 799 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 800 | } 801 | 802 | void Gpu_CoCmd_Inflate2(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t options) 803 | { 804 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 805 | Gpu_Copro_SendCmd(phost, CMD_INFLATE2); 806 | Gpu_Copro_SendCmd(phost, ptr); 807 | Gpu_Copro_SendCmd(phost, options); 808 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 809 | } 810 | 811 | void Gpu_CoCmd_RotateAround(Gpu_Hal_Context_t *phost,int32_t x, int32_t y, int32_t a, int32_t s) 812 | { 813 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*5); 814 | Gpu_Copro_SendCmd(phost,CMD_ROTATEAROUND); 815 | Gpu_Copro_SendCmd(phost,x); 816 | Gpu_Copro_SendCmd(phost,y); 817 | Gpu_Copro_SendCmd(phost,a); 818 | Gpu_Copro_SendCmd(phost,s); 819 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*5)); 820 | } 821 | 822 | void Gpu_CoCmd_FlashErase(Gpu_Hal_Context_t *phost) 823 | { 824 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 825 | Gpu_Copro_SendCmd(phost, CMD_FLASHERASE); 826 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 827 | } 828 | 829 | /* 830 | * Write data to flash. Constraints: 831 | * - destination flash address must be virgin (not used before) 832 | * - data array must be aligned 256-bit 833 | */ 834 | void Gpu_CoCmd_FlashWriteExt(Gpu_Hal_Context_t *phost,uint32_t dest, uint32_t num, uint8_t *data) 835 | { 836 | uint32_t i, send_data32=0, totalnum = (num+3)/4; 837 | 838 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE*(3+totalnum)); 839 | Gpu_Copro_SendCmd(phost,CMD_FLASHWRITE); 840 | Gpu_Copro_SendCmd(phost,dest); 841 | Gpu_Copro_SendCmd(phost, num); 842 | 843 | for (i = 0; i < num; i=i+4) 844 | { 845 | send_data32 = *data++; 846 | send_data32 |= (*data++) << 8; 847 | send_data32 |= (*data++) << 16; 848 | send_data32 |= (*data++) << 24; 849 | Gpu_Copro_SendCmd(phost, send_data32); 850 | } 851 | 852 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*(3+totalnum))); 853 | } 854 | 855 | void Gpu_CoCmd_FlashWrite(Gpu_Hal_Context_t *phost, uint32_t ptr, uint32_t num) 856 | { 857 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 858 | Gpu_Copro_SendCmd(phost, CMD_FLASHWRITE); 859 | Gpu_Copro_SendCmd(phost, ptr); 860 | Gpu_Copro_SendCmd(phost, num); 861 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 862 | } 863 | 864 | /* 865 | * Writes the given data to flash. 866 | * If the data matches the existing contents of flash, nothing is done. 867 | * Otherwise the flash is erased in 4K units, and the data is written. 868 | */ 869 | void Gpu_CoCmd_FlashUpdate(Gpu_Hal_Context_t *phost, uint32_t dest, uint32_t src, uint32_t num) 870 | { 871 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 4); 872 | Gpu_Copro_SendCmd(phost, CMD_FLASHUPDATE); 873 | Gpu_Copro_SendCmd(phost, dest); 874 | Gpu_Copro_SendCmd(phost, src); 875 | Gpu_Copro_SendCmd(phost, num); 876 | Gpu_CoCmd_EndFunc(phost, (CMD_SIZE * 4)); 877 | } 878 | 879 | /* Read data from flash into main memory */ 880 | void Gpu_CoCmd_FlashRead(Gpu_Hal_Context_t *phost,uint32_t dest, uint32_t src, uint32_t num) 881 | { 882 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 883 | Gpu_Copro_SendCmd(phost, CMD_FLASHREAD); 884 | Gpu_Copro_SendCmd(phost, dest); 885 | Gpu_Copro_SendCmd(phost, src); 886 | Gpu_Copro_SendCmd(phost, num); 887 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 888 | } 889 | 890 | void Gpu_CoCmd_FlashSource(Gpu_Hal_Context_t *phost,uint32_t ptr) 891 | { 892 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 893 | Gpu_Copro_SendCmd(phost,CMD_FLASHSOURCE); 894 | Gpu_Copro_SendCmd(phost,ptr); 895 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 896 | } 897 | 898 | void Gpu_CoCmd_FlashSpiTx(Gpu_Hal_Context_t *phost,uint32_t num) 899 | { 900 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 901 | Gpu_Copro_SendCmd(phost,CMD_FLASHSPITX); 902 | Gpu_Copro_SendCmd(phost,num); 903 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 904 | } 905 | 906 | void Gpu_CoCmd_FlashFast(Gpu_Hal_Context_t *phost,uint32_t result) 907 | { 908 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 909 | Gpu_Copro_SendCmd(phost,CMD_FLASHFAST); 910 | Gpu_Copro_SendCmd(phost,result); 911 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 912 | } 913 | 914 | void Gpu_CoCmd_FlashSpiRx(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num) 915 | { 916 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*3); 917 | Gpu_Copro_SendCmd(phost, CMD_FLASHSPIRX); 918 | Gpu_Copro_SendCmd(phost, ptr); 919 | Gpu_Copro_SendCmd(phost, num); 920 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*3)); 921 | } 922 | 923 | void Gpu_CoCmd_FlashAttach(Gpu_Hal_Context_t *phost) 924 | { 925 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 926 | Gpu_Copro_SendCmd(phost, CMD_FLASHATTACH); 927 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 928 | } 929 | 930 | void Gpu_CoCmd_FlashDetach(Gpu_Hal_Context_t *phost) 931 | { 932 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 933 | Gpu_Copro_SendCmd(phost,CMD_FLASHDETACH); 934 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 935 | } 936 | 937 | void Gpu_CoCmd_FlashSpiDesel(Gpu_Hal_Context_t *phost) 938 | { 939 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 940 | Gpu_Copro_SendCmd(phost, CMD_FLASHSPIDESEL); 941 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 942 | } 943 | 944 | void Gpu_CoCmd_ClearCache(Gpu_Hal_Context_t *phost) 945 | { 946 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 947 | Gpu_Copro_SendCmd(phost,CMD_CLEARCACHE); 948 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 949 | } 950 | 951 | void Gpu_CoCmd_Int_RamShared(Gpu_Hal_Context_t *phost,uint32_t ptr) 952 | { 953 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 954 | Gpu_Copro_SendCmd(phost, CMD_INT_RAMSHARED); 955 | Gpu_Copro_SendCmd(phost, ptr); 956 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 957 | } 958 | 959 | void Gpu_CoCmd_Sha1(Gpu_Hal_Context_t *phost,uint32_t src, uint32_t num, uint32_t hash) 960 | { 961 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*4); 962 | Gpu_Copro_SendCmd(phost, CMD_SHA1); 963 | Gpu_Copro_SendCmd(phost, src); 964 | Gpu_Copro_SendCmd(phost, num); 965 | Gpu_Copro_SendCmd(phost, hash); 966 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*4)); 967 | } 968 | 969 | void Gpu_CoCmd_ResetFonts(Gpu_Hal_Context_t *phost) 970 | { 971 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE); 972 | Gpu_Copro_SendCmd(phost,CMD_RESETFONTS); 973 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE)); 974 | } 975 | 976 | void Gpu_CoCmd_AnimStart(Gpu_Hal_Context_t *phost, int32_t ch, uint32_t aoptr, uint32_t loop) 977 | { 978 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 4); 979 | Gpu_Copro_SendCmd(phost, CMD_ANIMSTART); 980 | Gpu_Copro_SendCmd(phost, ch); 981 | Gpu_Copro_SendCmd(phost, aoptr); 982 | Gpu_Copro_SendCmd(phost, loop); 983 | Gpu_CoCmd_EndFunc(phost, (CMD_SIZE * 4)); 984 | } 985 | 986 | void Gpu_CoCmd_GradientA(Gpu_Hal_Context_t *phost, int16_t x0, int16_t y0, uint32_t argb0, int16_t x1, int16_t y1, uint32_t argb1) 987 | { 988 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 5); 989 | Gpu_Copro_SendCmd(phost, CMD_GRADIENTA); 990 | Gpu_Copro_SendCmd(phost, ((uint32_t)y0<<16) |(x0 & 0xFFFF)); 991 | Gpu_Copro_SendCmd(phost, argb0); 992 | Gpu_Copro_SendCmd(phost, ((uint32_t)y1<<16) |(x1 & 0xFFFF)); 993 | Gpu_Copro_SendCmd(phost, argb1); 994 | Gpu_CoCmd_EndFunc(phost, (CMD_SIZE * 5)); 995 | } 996 | 997 | void Gpu_CoCmd_AnimStop(Gpu_Hal_Context_t *phost, int32_t ch) 998 | { 999 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 2); 1000 | Gpu_Copro_SendCmd(phost, CMD_ANIMSTOP); 1001 | Gpu_Copro_SendCmd(phost, ch); 1002 | Gpu_CoCmd_EndFunc(phost, CMD_SIZE * 2); 1003 | } 1004 | 1005 | void Gpu_CoCmd_AnimXY(Gpu_Hal_Context_t *phost, int32_t ch, int16_t x, int16_t y) 1006 | { 1007 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 3); 1008 | Gpu_Copro_SendCmd(phost, CMD_ANIMXY); 1009 | Gpu_Copro_SendCmd(phost, ch); 1010 | Gpu_Copro_SendCmd(phost, ((uint32_t)y<<16) |(x & 0xFFFF)); 1011 | Gpu_CoCmd_EndFunc(phost, (CMD_SIZE * 3)); 1012 | } 1013 | 1014 | void Gpu_CoCmd_AnimDraw(Gpu_Hal_Context_t *phost, int32_t ch) 1015 | { 1016 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE *2); 1017 | Gpu_Copro_SendCmd(phost, CMD_ANIMDRAW); 1018 | Gpu_Copro_SendCmd(phost, ch); 1019 | Gpu_CoCmd_EndFunc(phost, CMD_SIZE * 2); 1020 | } 1021 | 1022 | void Gpu_CoCmd_AnimFrame(Gpu_Hal_Context_t *phost, int16_t x, int16_t y, uint32_t aoptr, uint32_t frame) 1023 | { 1024 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE * 4); 1025 | Gpu_Copro_SendCmd(phost, CMD_ANIMFRAME); 1026 | Gpu_Copro_SendCmd(phost, ((uint32_t)y << 16) | (x & 0xFFFF)); 1027 | Gpu_Copro_SendCmd(phost, aoptr); 1028 | Gpu_Copro_SendCmd(phost, frame); 1029 | Gpu_CoCmd_EndFunc(phost, CMD_SIZE * 4); 1030 | } 1031 | 1032 | void Gpu_CoCmd_AppendF(Gpu_Hal_Context_t *phost, uint32_t ptr, uint32_t num) 1033 | { 1034 | Gpu_CoCmd_StartFunc(phost, CMD_SIZE *3); 1035 | Gpu_Copro_SendCmd(phost, CMD_APPENDF); 1036 | Gpu_Copro_SendCmd(phost, ptr); 1037 | Gpu_Copro_SendCmd(phost, num); 1038 | Gpu_CoCmd_EndFunc(phost, CMD_SIZE * 3); 1039 | } 1040 | 1041 | void Gpu_CoCmd_FlashHelper_Init(Gpu_Hal_Context_t *phost) 1042 | { 1043 | while (FLASH_STATUS_DETACHED == Gpu_Hal_Rd8(phost, REG_FLASH_STATUS)) 1044 | Gpu_CoCmd_FlashAttach(phost); 1045 | } 1046 | 1047 | /* 1048 | * Switch to other flash state 1049 | * Error code: 1050 | * - 0x0 command succeeds 1051 | * - 0xffff command fails (invalid transition state) 1052 | * - 0xe001 flash is not attached 1053 | * - 0xe002 no header detected in sector 0 - is flash blank? 1054 | * - 0xe003 sector 0 data failed integrity check 1055 | * - 0xe004 device/blob mismatch - was correct blob loaded? 1056 | * - 0xe005 failed full-speed test - check board wiring 1057 | */ 1058 | uint32_t Gpu_CoCmd_FlashHelper_SwitchState(Gpu_Hal_Context_t *phost, uint8_t nextState) 1059 | { 1060 | uint32_t ret = 0; 1061 | uint8_t curr_flash_state = Gpu_Hal_Rd8(phost, REG_FLASH_STATUS); 1062 | uint16_t ret_addr = 0; 1063 | 1064 | if (curr_flash_state != nextState) 1065 | { 1066 | if (FLASH_STATUS_DETACHED == nextState) 1067 | { 1068 | Gpu_CoCmd_FlashDetach(phost); 1069 | App_Flush_Co_Buffer(phost); 1070 | } 1071 | else if (FLASH_STATUS_BASIC == nextState) 1072 | { 1073 | if (FLASH_STATUS_FULL == curr_flash_state) 1074 | { 1075 | do 1076 | { 1077 | Gpu_CoCmd_FlashDetach(phost); 1078 | App_Flush_Co_Buffer(phost); 1079 | } while (FLASH_STATUS_DETACHED != Gpu_Hal_Rd8(phost, REG_FLASH_STATUS)); 1080 | } 1081 | 1082 | Gpu_CoCmd_FlashAttach(phost); 1083 | App_Flush_Co_Buffer(phost); 1084 | } 1085 | else if (FLASH_STATUS_FULL == nextState) 1086 | { 1087 | if (FLASH_STATUS_BASIC != curr_flash_state) 1088 | { 1089 | do 1090 | { 1091 | Gpu_CoCmd_FlashAttach(phost); 1092 | App_Flush_Co_Buffer(phost); 1093 | } while (FLASH_STATUS_BASIC != Gpu_Hal_Rd8(phost, REG_FLASH_STATUS)); 1094 | } 1095 | 1096 | Gpu_CoCmd_FlashFast(phost, 0); 1097 | App_Flush_Co_Buffer(phost); 1098 | 1099 | /* read the return code in CMD_BUFFER */ 1100 | ret_addr = (phost->cmd_fifo_wp - 4) & FIFO_SIZE_MASK; 1101 | ret_addr = (ret_addr + 3) & FIFO_BYTE_ALIGNMENT_MASK; 1102 | 1103 | ret = Gpu_Hal_Rd32(phost, RAM_CMD + ret_addr); 1104 | } 1105 | else 1106 | { 1107 | ret = 0xffff; 1108 | } 1109 | } 1110 | return ret; 1111 | } 1112 | 1113 | uint32_t Gpu_CoCmd_FlashHelper_SwitchFullMode(Gpu_Hal_Context_t *phost) 1114 | { 1115 | uint8_t val; 1116 | 1117 | Gpu_CoCmd_FlashDetach(phost); 1118 | App_Flush_Co_Buffer(phost); 1119 | Gpu_Hal_WaitCmdfifo_empty(phost); 1120 | val = Gpu_Hal_Rd8(phost, REG_FLASH_STATUS); 1121 | 1122 | if (FLASH_STATUS_DETACHED != val) 1123 | { 1124 | /* error, flash is not able to detatch */ 1125 | return 0; 1126 | } 1127 | 1128 | Gpu_CoCmd_FlashAttach(phost); 1129 | App_Flush_Co_Buffer(phost); 1130 | Gpu_Hal_WaitCmdfifo_empty(phost); 1131 | val = Gpu_Hal_Rd8(phost, REG_FLASH_STATUS); 1132 | 1133 | if (FLASH_STATUS_BASIC != val) 1134 | { 1135 | /* error, flash is not able to attach */ 1136 | return 0; 1137 | } 1138 | 1139 | Gpu_CoCmd_FlashFast(phost, 0); 1140 | App_Flush_Co_Buffer(phost); 1141 | Gpu_Hal_WaitCmdfifo_empty(phost); 1142 | val = Gpu_Hal_Rd8(phost, REG_FLASH_STATUS); 1143 | 1144 | if (FLASH_STATUS_FULL != val) 1145 | { 1146 | /* error, flash is not able to get into full mode */ 1147 | return 0; 1148 | } 1149 | 1150 | return 1; 1151 | } 1152 | 1153 | /* 1154 | * Write data to flash, and align byte if needed. 1155 | * Note: 1156 | * - Destination flash address must be virgin (not used before). 1157 | * Otherwise, users have to perform flash erase before using. 1158 | * - Destination address must be 256-byte aligned. 1159 | * - Automatically padding 0xFF to non-aligned num. 1160 | */ 1161 | Flash_Cmd_Status_t Gpu_CoCmd_FlashHelper_Write(Gpu_Hal_Context_t *phost, uint32_t dest_flash, uint32_t num, uint8_t *write_data) 1162 | { 1163 | uint32_t i; 1164 | uint8_t padding_arr[FLASH_WRITE_ALIGN_BYTE]; /* write_data must be 256-byte aligned */ 1165 | uint32_t aligned_length = num % FLASH_WRITE_ALIGN_BYTE; 1166 | 1167 | if (dest_flash % FLASH_WRITE_ALIGN_BYTE != 0) 1168 | return FLASH_CMD_ALIGNED_ERR; 1169 | 1170 | if (aligned_length == 0) /* write_data is already aligned */ 1171 | { 1172 | Gpu_CoCmd_FlashWriteExt(phost, dest_flash, num, write_data); 1173 | App_Flush_Co_Buffer(phost); 1174 | Gpu_Hal_WaitCmdfifo_empty(phost); 1175 | } 1176 | else 1177 | { 1178 | /* write first aligned chunks of write_data */ 1179 | if (num - aligned_length > 0) 1180 | { 1181 | Gpu_CoCmd_FlashWriteExt(phost, dest_flash, num - aligned_length, write_data); 1182 | App_Flush_Co_Buffer(phost); 1183 | Gpu_Hal_WaitCmdfifo_empty(phost); 1184 | } 1185 | 1186 | /* write the rest write_data */ 1187 | write_data = write_data + num - aligned_length; 1188 | for (i = 0; i < FLASH_WRITE_ALIGN_BYTE; i++) 1189 | { 1190 | if (i < aligned_length) 1191 | padding_arr[i] = *write_data++; 1192 | else 1193 | padding_arr[i] = 0xFF; /* should use 0xFF instead of 0x00 to avoid writing overhead */ 1194 | } 1195 | 1196 | Gpu_CoCmd_FlashWriteExt(phost, dest_flash + num - aligned_length, FLASH_WRITE_ALIGN_BYTE, padding_arr); 1197 | App_Flush_Co_Buffer(phost); 1198 | Gpu_Hal_WaitCmdfifo_empty(phost); 1199 | } 1200 | 1201 | return FLASH_CMD_SUCCESS; 1202 | } 1203 | 1204 | /* 1205 | * Writes the given data to flash. 1206 | * If the data matches the existing contents of flash, nothing is done. 1207 | * Otherwise the flash is erased in 4K units, and the data is written. 1208 | * @dest_flash: destination address in flash memory. Must be 4096-byte aligned 1209 | * @src_ram: source data in main memory. Must be 4-byte aligned 1210 | * @num: number of bytes to write, should be multiple of 4096, otherwise, dummy data will be padded 1211 | */ 1212 | Flash_Cmd_Status_t Gpu_CoCmd_FlashHelper_Update(Gpu_Hal_Context_t *phost, uint32_t dest_flash, uint32_t src_ram, uint32_t num) 1213 | { 1214 | /* must be multiple of 4096. Cut off the extended data */ 1215 | uint32_t last_chunk = (num%4096); 1216 | 1217 | if ((dest_flash % FLASH_UPDATE_ALIGN_BYTE != 0)||((src_ram % 4) != 0)) 1218 | return FLASH_CMD_ALIGNED_ERR; 1219 | 1220 | if (num < FLASH_UPDATE_ALIGN_BYTE) 1221 | { 1222 | Gpu_CoCmd_FlashUpdate(phost, dest_flash, src_ram, FLASH_UPDATE_ALIGN_BYTE); 1223 | App_Flush_Co_Buffer(phost); 1224 | Gpu_Hal_WaitCmdfifo_empty(phost); 1225 | } 1226 | else if (last_chunk == 0) /* num is multiple of 4k */ 1227 | { 1228 | Gpu_CoCmd_FlashUpdate(phost, dest_flash, src_ram, num); 1229 | App_Flush_Co_Buffer(phost); 1230 | Gpu_Hal_WaitCmdfifo_empty(phost); 1231 | } 1232 | else /* num is not fit in multiple of 4k */ 1233 | { 1234 | Gpu_CoCmd_FlashUpdate(phost, dest_flash, src_ram, num - last_chunk); 1235 | App_Flush_Co_Buffer(phost); 1236 | Gpu_Hal_WaitCmdfifo_empty(phost); 1237 | 1238 | Gpu_CoCmd_FlashUpdate(phost, dest_flash + num - last_chunk, src_ram + num - last_chunk, FLASH_UPDATE_ALIGN_BYTE); 1239 | App_Flush_Co_Buffer(phost); 1240 | Gpu_Hal_WaitCmdfifo_empty(phost); 1241 | } 1242 | 1243 | return FLASH_CMD_SUCCESS; 1244 | } 1245 | 1246 | /* Read date from flash to array 1247 | * @dest_ram: address in ram where the flash copy data to 1248 | * @src_flash: source address in flash memory. Must be 64-byte aligned. From 0 to 64*1024 for 64MB flash 1249 | * @num: number of bytes would be read 1250 | * @read_data: pointer to user read data 1251 | */ 1252 | Flash_Cmd_Status_t Gpu_CoCmd_FlashHelper_Read(Gpu_Hal_Context_t *phost, uint32_t dest_ram, uint32_t src_flash, uint32_t num, uint8_t *read_data) 1253 | { 1254 | num = num - (num%4); 1255 | 1256 | if ((src_flash % FLASH_READ_ALIGN_BYTE != 0) || ((dest_ram % 4) != 0)) 1257 | return FLASH_CMD_ALIGNED_ERR; 1258 | 1259 | Gpu_CoCmd_FlashRead(phost, dest_ram, src_flash, num); 1260 | App_Flush_Co_Buffer(phost); 1261 | Gpu_Hal_WaitCmdfifo_empty(phost); 1262 | 1263 | Gpu_Hal_RdMem(phost, dest_ram, read_data, num); 1264 | return FLASH_CMD_SUCCESS; 1265 | } 1266 | 1267 | /* Erase entire flash */ 1268 | void Gpu_CoCmd_FlashHelper_Erase(Gpu_Hal_Context_t *phost) 1269 | { 1270 | Gpu_CoCmd_FlashErase(phost); 1271 | App_Flush_Co_Buffer(phost); 1272 | Gpu_Hal_WaitCmdfifo_empty(phost); 1273 | } 1274 | 1275 | /* 1276 | * Clears the graphics system's flash cache. It should be executed after 1277 | * modifying graphics data in flash, otherwise bitmaps from flash may render 1278 | * "stale" data. This command must be executed when the display list is in use, 1279 | * immediately after a CMD SWAP command. 1280 | */ 1281 | void Gpu_CoCmd_FlashHelper_ClearCache(Gpu_Hal_Context_t *phost) 1282 | { 1283 | Gpu_CoCmd_ClearCache(phost); 1284 | App_Flush_Co_Buffer(phost); 1285 | Gpu_Hal_WaitCmdfifo_empty(phost); 1286 | } 1287 | 1288 | /* 1289 | * Flash state/status: 1290 | * - FLASH_STATUS_BASIC 2UL 1291 | * - FLASH_STATUS_DETACHED 1UL 1292 | * - FLASH_STATUS_FULL 3UL 1293 | * - FLASH_STATUS_INIT 0UL 1294 | */ 1295 | uint8_t Gpu_CoCmd_FlashHelper_GetState(Gpu_Hal_Context_t *phost) 1296 | { 1297 | return Gpu_Hal_Rd8(phost, REG_FLASH_STATUS); 1298 | } 1299 | #endif /* BT81X_ENABLE */ 1300 | 1301 | void Gpu_Copro_SendCmd(Gpu_Hal_Context_t *phost,uint32_t cmd) 1302 | { 1303 | #if defined (LINUX_PLATFORM) || defined (FT232H_MINGW_PLATFORM) 1304 | #ifdef BUFFER_OPTIMIZATION 1305 | App_WrCoCmd_Buffer(phost,cmd); 1306 | #else 1307 | Gpu_Hal_Transfer32(phost,cmd); 1308 | #endif 1309 | #endif 1310 | 1311 | #if defined (STM32_PLATFORM) || defined (ARDUINO_PLATFORM) 1312 | #if defined (STM32_PLATFORM_COCMD_BURST) || defined (ARDUINO_PLATFORM_COCMD_BURST) 1313 | Gpu_Hal_Transfer32(phost,cmd); 1314 | #else 1315 | Gpu_Hal_WrCmd32(phost,cmd); 1316 | #endif 1317 | #endif 1318 | } 1319 | 1320 | void Gpu_CoCmd_SendStr(Gpu_Hal_Context_t *phost,const char8_t *s) 1321 | { 1322 | #if defined (LINUX_PLATFORM) || defined (FT232H_MINGW_PLATFORM) 1323 | #ifdef BUFFER_OPTIMIZATION 1324 | App_WrCoStr_Buffer(phost,s); 1325 | #else 1326 | Gpu_Hal_TransferString(phost,s); 1327 | #endif 1328 | #endif 1329 | 1330 | #if defined (STM32_PLATFORM) || defined (ARDUINO_PLATFORM) 1331 | #if defined (STM32_PLATFORM_COCMD_BURST) || defined (ARDUINO_PLATFORM_COCMD_BURST) 1332 | Gpu_Hal_TransferString(phost,s); 1333 | #else 1334 | Gpu_Hal_WrCmdBuf(phost,(uint8_t*)s,length); 1335 | #endif 1336 | 1337 | /* align 4 byte in coprocessor command buffer */ 1338 | uint8_t i=0; 1339 | uint16_t length = 0; 1340 | length = strlen(s) + 1; 1341 | for (i=0; i< (4-length%4)%4 ;i++) 1342 | Gpu_Hal_Transfer8(phost,0); 1343 | #endif 1344 | } 1345 | 1346 | void Gpu_CoCmd_StartFunc(Gpu_Hal_Context_t *phost,uint16_t count) 1347 | { 1348 | #if defined (LINUX_PLATFORM) || defined (FT232H_MINGW_PLATFORM) 1349 | #ifndef BUFFER_OPTIMIZATION 1350 | Gpu_Hal_CheckCmdBuffer(phost,count); 1351 | Gpu_Hal_StartCmdTransfer(phost,GPU_WRITE,count); 1352 | #endif 1353 | #endif 1354 | 1355 | #if defined (STM32_PLATFORM) || defined (ARDUINO_PLATFORM) 1356 | #if defined (STM32_PLATFORM_COCMD_BURST) || defined (ARDUINO_PLATFORM_COCMD_BURST) 1357 | Gpu_Hal_CheckCmdBuffer(phost,count); 1358 | Gpu_Hal_StartCmdTransfer(phost,GPU_WRITE,count); 1359 | #endif 1360 | #endif 1361 | } 1362 | 1363 | void Gpu_CoCmd_EndFunc(Gpu_Hal_Context_t *phost,uint16_t count) 1364 | { 1365 | #if defined (LINUX_PLATFORM) || defined (FT232H_MINGW_PLATFORM) 1366 | #ifndef BUFFER_OPTIMIZATION 1367 | Gpu_Hal_EndTransfer(phost); 1368 | Gpu_Hal_Updatecmdfifo(phost,count); 1369 | #endif 1370 | #endif 1371 | 1372 | #if defined (STM32_PLATFORM) || defined (ARDUINO_PLATFORM) 1373 | #if defined (STM32_PLATFORM_COCMD_BURST) || defined (ARDUINO_PLATFORM_COCMD_BURST) 1374 | Gpu_Hal_EndTransfer(phost); 1375 | Gpu_Hal_Updatecmdfifo(phost,count); 1376 | #endif 1377 | #endif 1378 | } 1379 | 1380 | void Gpu_CoCmd_Hsf(Gpu_Hal_Context_t *phost,uint32_t w) 1381 | { 1382 | #if defined (EVE_3) 1383 | Gpu_CoCmd_StartFunc(phost,CMD_SIZE*2); 1384 | Gpu_Copro_SendCmd(phost, CMD_HSF); 1385 | Gpu_Copro_SendCmd(phost, w); 1386 | Gpu_CoCmd_EndFunc(phost,(CMD_SIZE*2)); 1387 | #endif 1388 | } 1389 | -------------------------------------------------------------------------------- /CoPro_Cmds.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Bridgetek Pte Ltd 3 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 4 | * Copyright (c) Skalski Embedded Technologies 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 7 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 8 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9 | * ARE DISCLAIMED. IN NO EVENT SHALL BRIDGETEK PTE LTD BE LIABLE FOR ANY 10 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES 12 | * LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 13 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 14 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 15 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | * 17 | * BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON 18 | * BRIDGETEK PARTS. 19 | * 20 | * BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE 21 | * INFORMATION IS NOT MODIFIED. 22 | * 23 | * IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, 24 | * IT IS THE RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES 25 | * AND SUBSEQUENT WHQL RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 26 | */ 27 | 28 | #ifndef _COPRO_CMDS_H_ 29 | #define _COPRO_CMDS_H_ 30 | 31 | void Gpu_CoCmd_Text(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t font, uint16_t options, const char8_t* s, ...); 32 | void Gpu_CoCmd_Number(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t font, uint16_t options, int32_t n); 33 | void Gpu_CoCmd_LoadIdentity(Gpu_Hal_Context_t *phost); 34 | void Gpu_CoCmd_Toggle(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t font, uint16_t options, uint16_t state, const char8_t* s, ...); 35 | void Gpu_CoCmd_Gauge(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t r, uint16_t options, uint16_t major, uint16_t minor, uint16_t val, uint16_t range); 36 | void Gpu_CoCmd_RegRead(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t result); 37 | void Gpu_CoCmd_GetProps(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t w, uint32_t h); 38 | void Gpu_CoCmd_Memcpy(Gpu_Hal_Context_t *phost,uint32_t dest, uint32_t src, uint32_t num); 39 | void Gpu_CoCmd_Spinner(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, uint16_t style, uint16_t scale); 40 | void Gpu_CoCmd_BgColor(Gpu_Hal_Context_t *phost,uint32_t c); 41 | void Gpu_CoCmd_Swap(Gpu_Hal_Context_t *phost); 42 | void Gpu_CoCmd_Inflate(Gpu_Hal_Context_t *phost,uint32_t ptr); 43 | void Gpu_CoCmd_Translate(Gpu_Hal_Context_t *phost,int32_t tx, int32_t ty); 44 | void Gpu_CoCmd_Stop(Gpu_Hal_Context_t *phost); 45 | void Gpu_CoCmd_Slider(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, uint16_t options, uint16_t val, uint16_t range); 46 | void Gpu_CoCmd_TouchTransform(Gpu_Hal_Context_t *phost,int32_t x0, int32_t y0, int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t tx0, int32_t ty0, int32_t tx1, int32_t ty1, int32_t tx2, int32_t ty2, uint16_t result); 47 | void Gpu_CoCmd_Interrupt(Gpu_Hal_Context_t *phost,uint32_t ms); 48 | void Gpu_CoCmd_FgColor(Gpu_Hal_Context_t *phost,uint32_t c); 49 | void Gpu_CoCmd_Rotate(Gpu_Hal_Context_t *phost,int32_t a); 50 | void Gpu_CoCmd_Button(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, int16_t font, uint16_t options, const char8_t* s, ...); 51 | void Gpu_CoCmd_MemWrite(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num); 52 | void Gpu_CoCmd_Scrollbar(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, uint16_t options, uint16_t val, uint16_t size, uint16_t range); 53 | void Gpu_CoCmd_GetMatrix(Gpu_Hal_Context_t *phost,int32_t a, int32_t b, int32_t c, int32_t d, int32_t e, int32_t f); 54 | void Gpu_CoCmd_Sketch(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, uint16_t w, uint16_t h, uint32_t ptr, uint16_t format); 55 | void Gpu_CoCmd_MemSet(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t value, uint32_t num); 56 | void Gpu_CoCmd_GradColor(Gpu_Hal_Context_t *phost,uint32_t c); 57 | void Gpu_CoCmd_Bitmap_Transform(Gpu_Hal_Context_t *phost,int32_t x0, int32_t y0, int32_t x1, int32_t y1, int32_t x2, int32_t y2, int32_t tx0, int32_t ty0, int32_t tx1, int32_t ty1, int32_t tx2, int32_t ty2, uint16_t result); 58 | void Gpu_CoCmd_Calibrate(Gpu_Hal_Context_t *phost,uint32_t result); 59 | void Gpu_CoCmd_SetFont(Gpu_Hal_Context_t *phost,uint32_t font, uint32_t ptr); 60 | void Gpu_CoCmd_Logo(Gpu_Hal_Context_t *phost); 61 | void Gpu_CoCmd_Append(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num); 62 | void Gpu_CoCmd_MemZero(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num); 63 | void Gpu_CoCmd_Scale(Gpu_Hal_Context_t *phost,int32_t sx, int32_t sy); 64 | void Gpu_CoCmd_Clock(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t r, uint16_t options, uint16_t h, uint16_t m, uint16_t s, uint16_t ms); 65 | void Gpu_CoCmd_Gradient(Gpu_Hal_Context_t *phost,int16_t x0, int16_t y0, uint32_t rgb0, int16_t x1, int16_t y1, uint32_t rgb1); 66 | void Gpu_CoCmd_SetMatrix(Gpu_Hal_Context_t *phost); 67 | void Gpu_CoCmd_Track(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, int16_t tag); 68 | void Gpu_CoCmd_GetPtr(Gpu_Hal_Context_t *phost,uint32_t result); 69 | void Gpu_CoCmd_Progress(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, uint16_t options, uint16_t val, uint16_t range); 70 | void Gpu_CoCmd_ColdStart(Gpu_Hal_Context_t *phost); 71 | void Gpu_CoCmd_Keys(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t w, int16_t h, int16_t font, uint16_t options, const char8_t* s); 72 | void Gpu_CoCmd_Dial(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, int16_t r, uint16_t options, uint16_t val); 73 | void Gpu_CoCmd_LoadImage(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t options); 74 | void Gpu_CoCmd_Dlstart(Gpu_Hal_Context_t *phost); 75 | void Gpu_CoCmd_Snapshot(Gpu_Hal_Context_t *phost,uint32_t ptr); 76 | void Gpu_CoCmd_ScreenSaver(Gpu_Hal_Context_t *phost); 77 | void Gpu_CoCmd_MemCrc(Gpu_Hal_Context_t *phost, uint32_t ptr, uint32_t num, uint32_t result); 78 | void Gpu_CoCmd_Hsf(Gpu_Hal_Context_t *phost, uint32_t w); 79 | 80 | uint32_t GET_ASTC_FORMAT(uint16_t w, uint16_t h); 81 | void astc_tile2(uint8_t *iData, uint16_t bw, uint16_t bh, uint32_t size, uint8_t *oData); 82 | 83 | #ifdef FT81X_ENABLE 84 | void Gpu_CoCmd_SetBitmap(Gpu_Hal_Context_t *phost,uint32_t source, uint16_t fmt, uint16_t w, uint16_t h); 85 | void Gpu_CoCmd_SetScratch(Gpu_Hal_Context_t *phost,uint32_t handle); 86 | void Gpu_CoCmd_VideoStart(Gpu_Hal_Context_t *phost); 87 | void Gpu_CoCmd_SetBase(Gpu_Hal_Context_t *phost,uint32_t base); 88 | void Gpu_CoCmd_VideoFrame(Gpu_Hal_Context_t *phost,uint32_t dst, uint32_t ptr); 89 | void Gpu_CoCmd_RomFont(Gpu_Hal_Context_t *phost,uint32_t font, uint32_t romslot); 90 | void Gpu_CoCmd_PlayVideo(Gpu_Hal_Context_t *phost,uint32_t options); 91 | void Gpu_CoCmd_Sync(Gpu_Hal_Context_t *phost); 92 | void Gpu_CoCmd_Int_RAMShared(Gpu_Hal_Context_t *phost,uint32_t ptr); 93 | void Gpu_CoCmd_Int_SWLoadImage(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t options); 94 | void Gpu_CoCmd_MediaFifo(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t size); 95 | void Gpu_CoCmd_Snapshot2(Gpu_Hal_Context_t *phost,uint32_t fmt, uint32_t ptr, int16_t x, int16_t y, int16_t w, int16_t h); 96 | void Gpu_CoCmd_SetFont2(Gpu_Hal_Context_t *phost,uint32_t font, uint32_t ptr, uint32_t firstchar); 97 | void Gpu_CoCmd_SetRotate(Gpu_Hal_Context_t *phost,uint32_t r); 98 | void Set_GpuClock(Gpu_Hal_Context_t *phost); 99 | uint32_t Get_GpuClock(Gpu_Hal_Context_t *phost); 100 | #endif /* FT81X_ENABLE */ 101 | 102 | #ifdef BT81X_ENABLE 103 | 104 | typedef enum{ 105 | FLASH_CMD_SUCCESS =0, 106 | FLASH_CMD_ALIGNED_ERR 107 | }Flash_Cmd_Status_t; 108 | 109 | #define FLASH_WRITE_ALIGN_BYTE (256) 110 | #define FLASH_UPDATE_ALIGN_BYTE (4096) 111 | #define FLASH_READ_ALIGN_BYTE (64) 112 | 113 | void Gpu_CoCmd_VideoStartF(Gpu_Hal_Context_t *phost); 114 | void Gpu_CoCmd_FillWidth(Gpu_Hal_Context_t *phost, uint32_t s); 115 | void Gpu_CoCmd_Nop(Gpu_Hal_Context_t *phost); 116 | void Gpu_CoCmd_GetPoint(Gpu_Hal_Context_t *phost,int16_t x, int16_t y, uint32_t sx, uint32_t sy); 117 | void Gpu_CoCmd_Inflate2(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t options); 118 | void Gpu_CoCmd_RotateAround(Gpu_Hal_Context_t *phost,int32_t x, int32_t y, int32_t a, int32_t s); 119 | 120 | void Gpu_CoCmd_FlashErase(Gpu_Hal_Context_t *phost); 121 | void Gpu_CoCmd_FlashWriteExt(Gpu_Hal_Context_t *phost,uint32_t dest, uint32_t num, uint8_t *data); 122 | void Gpu_CoCmd_FlashWrite(Gpu_Hal_Context_t *phost, uint32_t ptr, uint32_t num); 123 | void Gpu_CoCmd_FlashUpdate(Gpu_Hal_Context_t *phost, uint32_t dest, uint32_t src, uint32_t num); 124 | void Gpu_CoCmd_FlashRead(Gpu_Hal_Context_t *phost,uint32_t dest, uint32_t src, uint32_t num); 125 | void Gpu_CoCmd_FlashSource(Gpu_Hal_Context_t *phost,uint32_t ptr); 126 | void Gpu_CoCmd_FlashSpiTx(Gpu_Hal_Context_t *phost,uint32_t num); 127 | void Gpu_CoCmd_FlashFast(Gpu_Hal_Context_t *phost,uint32_t result); 128 | void Gpu_CoCmd_FlashSpiRx(Gpu_Hal_Context_t *phost,uint32_t ptr, uint32_t num); 129 | void Gpu_CoCmd_FlashAttach(Gpu_Hal_Context_t *phost); 130 | void Gpu_CoCmd_FlashDetach(Gpu_Hal_Context_t *phost); 131 | void Gpu_CoCmd_FlashSpiDesel(Gpu_Hal_Context_t *phost); 132 | 133 | void Gpu_CoCmd_ClearCache(Gpu_Hal_Context_t *phost); 134 | void Gpu_CoCmd_Int_RamShared(Gpu_Hal_Context_t *phost,uint32_t ptr); 135 | void Gpu_CoCmd_Sha1(Gpu_Hal_Context_t *phost,uint32_t src, uint32_t num, uint32_t hash); 136 | void Gpu_CoCmd_ResetFonts(Gpu_Hal_Context_t *phost); 137 | void Gpu_CoCmd_AnimStart(Gpu_Hal_Context_t *phost, int32_t ch, uint32_t aoptr, uint32_t loop); 138 | void Gpu_CoCmd_GradientA(Gpu_Hal_Context_t *phost, int16_t x0, int16_t y0, uint32_t argb0, int16_t x1, int16_t y1, uint32_t argb1); 139 | void Gpu_CoCmd_AppendF(Gpu_Hal_Context_t *phost, uint32_t ptr, uint32_t num); 140 | 141 | void Gpu_CoCmd_AnimStop(Gpu_Hal_Context_t *phost, int32_t ch); 142 | void Gpu_CoCmd_AnimXY(Gpu_Hal_Context_t *phost, int32_t ch, int16_t x, int16_t y); 143 | void Gpu_CoCmd_AnimDraw(Gpu_Hal_Context_t *phost, int32_t ch); 144 | void Gpu_CoCmd_AnimFrame(Gpu_Hal_Context_t *phost, int16_t x, int16_t y, uint32_t aoptr, uint32_t frame); 145 | 146 | void Gpu_CoCmd_FlashHelper_Init(Gpu_Hal_Context_t *phost); 147 | uint32_t Gpu_CoCmd_FlashHelper_SwitchState(Gpu_Hal_Context_t *phost, uint8_t nextState); 148 | uint32_t Gpu_CoCmd_FlashHelper_SwitchFullMode(Gpu_Hal_Context_t *phost); 149 | Flash_Cmd_Status_t Gpu_CoCmd_FlashHelper_Write(Gpu_Hal_Context_t *phost, uint32_t dest_flash, uint32_t num, uint8_t *write_data); 150 | Flash_Cmd_Status_t Gpu_CoCmd_FlashHelper_Update(Gpu_Hal_Context_t *phost, uint32_t dest_flash, uint32_t src_ram, uint32_t num); 151 | Flash_Cmd_Status_t Gpu_CoCmd_FlashHelper_Read(Gpu_Hal_Context_t *phost, uint32_t dest_ram, uint32_t src_flash, uint32_t num, uint8_t *read_data); 152 | void Gpu_CoCmd_FlashHelper_Erase(Gpu_Hal_Context_t *phost); 153 | void Gpu_CoCmd_FlashHelper_ClearCache(Gpu_Hal_Context_t *phost); 154 | uint8_t Gpu_CoCmd_FlashHelper_GetState(Gpu_Hal_Context_t *phost); 155 | 156 | #endif /* BT81X_ENABLE */ 157 | 158 | void Gpu_Copro_SendCmd(Gpu_Hal_Context_t *phost,uint32_t cmd); 159 | void Gpu_CoCmd_SendStr(Gpu_Hal_Context_t *phost,const char8_t *s); 160 | void Gpu_CoCmd_StartFunc(Gpu_Hal_Context_t *phost,uint16_t count); 161 | void Gpu_CoCmd_EndFunc(Gpu_Hal_Context_t *phost,uint16_t count); 162 | 163 | #endif /*COPRO_CMDS_H*/ 164 | -------------------------------------------------------------------------------- /Gpu_Hal.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Bridgetek Pte Ltd 3 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 4 | * Copyright (c) Skalski Embedded Technologies 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 7 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 8 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9 | * ARE DISCLAIMED. IN NO EVENT SHALL BRIDGETEK PTE LTD BE LIABLE FOR ANY 10 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES 12 | * LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 13 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 14 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 15 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | * 17 | * BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON 18 | * BRIDGETEK PARTS. 19 | * 20 | * BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE 21 | * INFORMATION IS NOT MODIFIED. 22 | * 23 | * IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, 24 | * IT IS THE RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES 25 | * AND SUBSEQUENT WHQL RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 26 | */ 27 | 28 | #include "Platform.h" 29 | 30 | /*****************************************************************************/ 31 | 32 | /* 33 | * Gpu_Hal_Init() 34 | */ 35 | bool_t 36 | Gpu_Hal_Init (Gpu_HalInit_t *halinit) 37 | { 38 | return TRUE; 39 | } 40 | 41 | 42 | /* 43 | * Gpu_Hal_Open() 44 | */ 45 | bool_t 46 | Gpu_Hal_Open (Gpu_Hal_Context_t *host) 47 | { 48 | /* gpio */ 49 | pinMode(GPIO_CS, OUTPUT); 50 | digitalWrite(GPIO_CS, HIGH); 51 | 52 | pinMode(GPIO_PD, OUTPUT); 53 | digitalWrite(GPIO_PD, HIGH); 54 | 55 | /* spi */ 56 | #ifdef ESP32 /* Riverdi IoT Display */ 57 | SPI.begin(14, 2, 15, 4); 58 | #else 59 | SPI.begin(); 60 | #endif 61 | 62 | SPI.setClockDivider(SPI_CLOCK_DIV2); 63 | SPI.setBitOrder(MSBFIRST); 64 | SPI.setDataMode(SPI_MODE0); 65 | 66 | /* initialize the context valriables */ 67 | host->cmd_fifo_wp = host->dl_buff_wp = 0; 68 | host->spinumdummy = GPU_SPI_ONEDUMMY; 69 | host->status = GPU_HAL_OPENED; 70 | 71 | return TRUE; 72 | } 73 | 74 | 75 | /* 76 | * Gpu_Hal_Close() 77 | */ 78 | void 79 | Gpu_Hal_Close (Gpu_Hal_Context_t *host) 80 | { 81 | SPI.end(); 82 | host->status = GPU_HAL_CLOSED; 83 | } 84 | 85 | 86 | /* 87 | * Gpu_Hal_DeInit() 88 | */ 89 | void 90 | Gpu_Hal_DeInit() 91 | { 92 | return; 93 | } 94 | 95 | /*****************************************************************************/ 96 | 97 | /* 98 | * Gpu_Hal_StartTransfer 99 | */ 100 | void 101 | Gpu_Hal_StartTransfer (Gpu_Hal_Context_t *host, 102 | GPU_TRANSFERDIR_T rw, 103 | uint32_t addr) 104 | { 105 | if (GPU_READ == rw) 106 | { 107 | digitalWrite (GPIO_CS, LOW); 108 | 109 | SPI.transfer (addr >> 16); 110 | SPI.transfer (highByte(addr)); 111 | SPI.transfer (lowByte(addr)); 112 | SPI.transfer (0); 113 | 114 | host->status = GPU_HAL_READING; 115 | } 116 | else 117 | { 118 | digitalWrite (GPIO_CS, LOW); 119 | 120 | SPI.transfer (0x80 | (addr >> 16)); 121 | SPI.transfer (highByte(addr)); 122 | SPI.transfer (lowByte(addr)); 123 | 124 | host->status = GPU_HAL_WRITING; 125 | } 126 | } 127 | 128 | 129 | /* 130 | * Gpu_Hal_StartCmdTransfer() 131 | */ 132 | void 133 | Gpu_Hal_StartCmdTransfer (Gpu_Hal_Context_t *host, 134 | GPU_TRANSFERDIR_T rw, 135 | uint16_t count) 136 | { 137 | Gpu_Hal_StartTransfer(host,rw,host->cmd_fifo_wp + RAM_CMD); 138 | } 139 | 140 | 141 | /* 142 | * Gpu_Hal_TransferString() 143 | */ 144 | void 145 | Gpu_Hal_TransferString (Gpu_Hal_Context_t *host, 146 | const char8_t *string) 147 | { 148 | uint16_t length = strlen(string); 149 | 150 | while(length --) 151 | { 152 | Gpu_Hal_Transfer8(host,*string); 153 | string ++; 154 | } 155 | 156 | /* append one null as ending flag */ 157 | Gpu_Hal_Transfer8(host,0); 158 | } 159 | 160 | 161 | /* 162 | * Gpu_Hal_Transfer8() 163 | */ 164 | uint8_t 165 | Gpu_Hal_Transfer8 (Gpu_Hal_Context_t *host, 166 | uint8_t value) 167 | { 168 | return SPI.transfer (value); 169 | } 170 | 171 | 172 | /* 173 | * Gpu_Hal_Transfer16() 174 | */ 175 | uint16_t 176 | Gpu_Hal_Transfer16 (Gpu_Hal_Context_t *host, 177 | uint16_t value) 178 | { 179 | uint16_t retVal = 0; 180 | 181 | if (host->status == GPU_HAL_WRITING) 182 | { 183 | Gpu_Hal_Transfer8(host,value & 0xFF); 184 | Gpu_Hal_Transfer8(host,(value >> 8) & 0xFF); 185 | } 186 | else 187 | { 188 | retVal = Gpu_Hal_Transfer8(host,0); 189 | retVal |= (uint16_t)Gpu_Hal_Transfer8(host,0) << 8; 190 | } 191 | 192 | return retVal; 193 | } 194 | 195 | 196 | /* 197 | * Gpu_Hal_Transfer32() 198 | */ 199 | uint32_t 200 | Gpu_Hal_Transfer32 (Gpu_Hal_Context_t *host, 201 | uint32_t value) 202 | { 203 | uint32_t retVal = 0; 204 | 205 | if (host->status == GPU_HAL_WRITING) 206 | { 207 | Gpu_Hal_Transfer16(host,value & 0xFFFF); 208 | Gpu_Hal_Transfer16(host,(value >> 16) & 0xFFFF); 209 | } 210 | else 211 | { 212 | retVal = Gpu_Hal_Transfer16(host,0); 213 | retVal |= (uint32_t)Gpu_Hal_Transfer16(host,0) << 16; 214 | } 215 | 216 | return retVal; 217 | } 218 | 219 | 220 | /* 221 | * Gpu_Hal_EndTransfer() 222 | */ 223 | void 224 | Gpu_Hal_EndTransfer (Gpu_Hal_Context_t *host) 225 | { 226 | digitalWrite (GPIO_CS, HIGH); 227 | host->status = GPU_HAL_OPENED; 228 | } 229 | 230 | /*****************************************************************************/ 231 | 232 | /* 233 | * Gpu_Hal_Rd8() 234 | */ 235 | uint8_t 236 | Gpu_Hal_Rd8 (Gpu_Hal_Context_t *host, 237 | uint32_t addr) 238 | { 239 | uint8_t value = 0; 240 | 241 | Gpu_Hal_StartTransfer(host,GPU_READ,addr); 242 | value = Gpu_Hal_Transfer8 (host, 0); 243 | Gpu_Hal_EndTransfer(host); 244 | 245 | return value; 246 | } 247 | 248 | 249 | /* 250 | * Gpu_Hal_Rd16() 251 | */ 252 | uint16_t 253 | Gpu_Hal_Rd16 (Gpu_Hal_Context_t *host, 254 | uint32_t addr) 255 | { 256 | uint16_t value = 0; 257 | 258 | Gpu_Hal_StartTransfer(host,GPU_READ,addr); 259 | value = Gpu_Hal_Transfer16 (host, 0); 260 | Gpu_Hal_EndTransfer(host); 261 | 262 | return value; 263 | } 264 | 265 | 266 | /* 267 | * Gpu_Hal_Rd32() 268 | */ 269 | uint32_t 270 | Gpu_Hal_Rd32 (Gpu_Hal_Context_t *host, 271 | uint32_t addr) 272 | { 273 | uint32_t value = 0; 274 | 275 | Gpu_Hal_StartTransfer(host,GPU_READ,addr); 276 | value = Gpu_Hal_Transfer32 (host, 0); 277 | Gpu_Hal_EndTransfer(host); 278 | 279 | return value; 280 | } 281 | 282 | /*****************************************************************************/ 283 | 284 | /* 285 | * Gpu_Hal_Wr8() 286 | */ 287 | void 288 | Gpu_Hal_Wr8 (Gpu_Hal_Context_t *host, 289 | uint32_t addr, 290 | uint8_t v) 291 | { 292 | Gpu_Hal_StartTransfer(host,GPU_WRITE,addr); 293 | Gpu_Hal_Transfer8(host,v); 294 | Gpu_Hal_EndTransfer(host); 295 | } 296 | 297 | 298 | /* 299 | * Gpu_Hal_Wr16() 300 | */ 301 | void 302 | Gpu_Hal_Wr16 (Gpu_Hal_Context_t *host, 303 | uint32_t addr, 304 | uint16_t v) 305 | { 306 | Gpu_Hal_StartTransfer(host,GPU_WRITE,addr); 307 | Gpu_Hal_Transfer16(host,v); 308 | Gpu_Hal_EndTransfer(host); 309 | } 310 | 311 | 312 | /* 313 | * Gpu_Hal_Wr32() 314 | */ 315 | void 316 | Gpu_Hal_Wr32 (Gpu_Hal_Context_t *host, 317 | uint32_t addr, 318 | uint32_t v) 319 | { 320 | Gpu_Hal_StartTransfer(host,GPU_WRITE,addr); 321 | Gpu_Hal_Transfer32(host,v); 322 | Gpu_Hal_EndTransfer(host); 323 | } 324 | 325 | /*****************************************************************************/ 326 | 327 | /* 328 | * Gpu_HostCommand() 329 | */ 330 | void 331 | Gpu_HostCommand (Gpu_Hal_Context_t *host, 332 | uint8_t cmd) 333 | { 334 | digitalWrite (GPIO_CS, LOW); 335 | 336 | SPI.transfer (cmd); 337 | SPI.transfer (0); 338 | SPI.transfer (0); 339 | 340 | digitalWrite (GPIO_CS, HIGH); 341 | } 342 | 343 | 344 | /* 345 | * Gpu_HostCommand_Ext3() 346 | */ 347 | void 348 | Gpu_HostCommand_Ext3 (Gpu_Hal_Context_t *host, 349 | uint32_t cmd) 350 | { 351 | digitalWrite (GPIO_CS, LOW); 352 | 353 | SPI.transfer (cmd); 354 | SPI.transfer ((cmd>>8) & 0xff); 355 | SPI.transfer ((cmd>>16) & 0xff); 356 | 357 | digitalWrite (GPIO_CS, HIGH); 358 | } 359 | 360 | /*****************************************************************************/ 361 | 362 | /* 363 | * Gpu_Hal_Powercycle() 364 | */ 365 | void 366 | Gpu_Hal_Powercycle (Gpu_Hal_Context_t *host, 367 | bool_t up) 368 | { 369 | if (up) 370 | { 371 | digitalWrite (GPIO_PD, LOW); 372 | Gpu_Hal_Sleep (20); 373 | digitalWrite (GPIO_PD, HIGH); 374 | Gpu_Hal_Sleep (20); 375 | } 376 | else 377 | { 378 | digitalWrite (GPIO_PD, HIGH); 379 | Gpu_Hal_Sleep (20); 380 | digitalWrite (GPIO_PD, LOW); 381 | Gpu_Hal_Sleep (20); 382 | } 383 | } 384 | 385 | 386 | /* 387 | * Gpu_Hal_Sleep() 388 | */ 389 | void 390 | Gpu_Hal_Sleep (uint32_t ms) 391 | { 392 | delay (ms); 393 | } 394 | 395 | /*****************************************************************************/ 396 | 397 | /* 398 | * Gpu_Hal_WrMem() 399 | */ 400 | void 401 | Gpu_Hal_WrMem (Gpu_Hal_Context_t *host, 402 | uint32_t addr, 403 | const uint8_t *buffer, 404 | uint32_t length) 405 | { 406 | Gpu_Hal_StartTransfer(host,GPU_WRITE,addr); 407 | 408 | while (length--) 409 | { 410 | Gpu_Hal_Transfer8(host,*buffer); 411 | buffer++; 412 | } 413 | 414 | Gpu_Hal_EndTransfer(host); 415 | } 416 | 417 | 418 | /* 419 | * Gpu_Hal_RdMem() 420 | */ 421 | void 422 | Gpu_Hal_RdMem (Gpu_Hal_Context_t *host, 423 | uint32_t addr, 424 | uint8_t *buffer, 425 | uint32_t length) 426 | { 427 | Gpu_Hal_StartTransfer(host,GPU_READ,addr); 428 | 429 | while (length--) 430 | { 431 | *buffer = Gpu_Hal_Transfer8(host,0); 432 | buffer++; 433 | } 434 | 435 | Gpu_Hal_EndTransfer(host); 436 | } 437 | 438 | 439 | /* 440 | * Gpu_Hal_DLSwap() 441 | * 442 | * API to check the status of previous DLSWAP and perform DLSWAP of new DL. 443 | * Check for the status of previous DLSWAP and if still not done wait for 444 | * few ms and check again 445 | */ 446 | void 447 | Gpu_Hal_DLSwap (Gpu_Hal_Context_t *host, 448 | uint8_t DL_Swap_Type) 449 | { 450 | uint8_t Swap_Type = DLSWAP_FRAME,Swap_Done = DLSWAP_FRAME; 451 | 452 | if (DL_Swap_Type == DLSWAP_LINE) 453 | Swap_Type = DLSWAP_LINE; 454 | 455 | /* perform a new DL swap */ 456 | Gpu_Hal_Wr8(host,REG_DLSWAP,Swap_Type); 457 | 458 | /* wait till the swap is done */ 459 | while(Swap_Done) 460 | { 461 | Swap_Done = Gpu_Hal_Rd8(host,REG_DLSWAP); 462 | if(DLSWAP_DONE != Swap_Done) 463 | Gpu_Hal_Sleep(1); 464 | } 465 | } 466 | 467 | 468 | /* 469 | * Gpu_Hal_ResetDLBuffer() 470 | */ 471 | void 472 | Gpu_Hal_ResetDLBuffer(Gpu_Hal_Context_t *host) 473 | { 474 | host->dl_buff_wp = 0; 475 | } 476 | 477 | /*****************************************************************************/ 478 | 479 | void 480 | Gpu_ClockSelect (Gpu_Hal_Context_t *host, 481 | GPU_PLL_SOURCE_T pllsource) 482 | { 483 | Gpu_HostCommand(host,pllsource); 484 | } 485 | 486 | void 487 | Gpu_PLL_FreqSelect (Gpu_Hal_Context_t *host, 488 | GPU_PLL_FREQ_T freq) 489 | { 490 | Gpu_HostCommand(host,freq); 491 | } 492 | 493 | void 494 | Gpu_PowerModeSwitch (Gpu_Hal_Context_t *host, 495 | GPU_POWER_MODE_T pwrmode) 496 | { 497 | Gpu_HostCommand(host,pwrmode); 498 | } 499 | 500 | void 501 | Gpu_CoreReset (Gpu_Hal_Context_t *host) 502 | { 503 | Gpu_HostCommand(host,0x68); 504 | } 505 | 506 | /*****************************************************************************/ 507 | 508 | #if (defined(FT81X_ENABLE)) || (defined(BT81X_ENABLE)) 509 | 510 | /* 511 | * Gpu_81X_SelectSysCLK() 512 | * 513 | * This API can only be called when PLL is stopped (SLEEP mode). 514 | * For compatibility, set frequency to the GPU_12MHZ option in the 515 | * GPU_SETPLLSP1_T table. 516 | */ 517 | void 518 | Gpu_81X_SelectSysCLK (Gpu_Hal_Context_t *host, 519 | GPU_81X_PLL_FREQ_T freq) 520 | { 521 | if(GPU_SYSCLK_72M == freq) 522 | Gpu_HostCommand_Ext3(host, (uint32_t)0x61 | (0x40 << 8) | (0x06 << 8)); 523 | else if(GPU_SYSCLK_60M == freq) 524 | Gpu_HostCommand_Ext3(host, (uint32_t)0x61 | (0x40 << 8) | (0x05 << 8)); 525 | else if(GPU_SYSCLK_48M == freq) 526 | Gpu_HostCommand_Ext3(host, (uint32_t)0x61 | (0x40 << 8) | (0x04 << 8)); 527 | else if(GPU_SYSCLK_36M == freq) 528 | Gpu_HostCommand_Ext3(host, (uint32_t)0x61 | (0x03 << 8)); 529 | else if(GPU_SYSCLK_24M == freq) 530 | Gpu_HostCommand_Ext3(host, (uint32_t)0x61 | (0x02 << 8)); 531 | else if(GPU_SYSCLK_DEFAULT == freq) 532 | Gpu_HostCommand_Ext3(host, 0x61); 533 | } 534 | 535 | 536 | /* 537 | * Gpu_81X_PowerOffComponents() 538 | * 539 | * Power down or up ROMs and ADCs. Specified one or more elements in the 540 | * GPU_81X_ROM_AND_ADC_T table to power down, unspecified elements will be 541 | * powered up. The application must retain the state of the ROMs and ADCs 542 | * as they're not readable from the device. 543 | */ 544 | void 545 | Gpu_81X_PowerOffComponents (Gpu_Hal_Context_t *host, 546 | uint8_t val) 547 | { 548 | Gpu_HostCommand_Ext3(host, (uint32_t)0x49 | (val<<8)); 549 | } 550 | 551 | 552 | /* 553 | * Gpu_81X_PadDriveStrength() 554 | * 555 | * This API sets the current strength of supported GPIO/IO group(s). 556 | */ 557 | void 558 | Gpu_81X_PadDriveStrength (Gpu_Hal_Context_t *host, 559 | GPU_81X_GPIO_DRIVE_STRENGTH_T strength, 560 | GPU_81X_GPIO_GROUP_T group) 561 | { 562 | Gpu_HostCommand_Ext3(host, (uint32_t)0x70 | (group << 8) | (strength << 8)); 563 | } 564 | 565 | 566 | /* 567 | * Gpu_81X_ResetActive() 568 | * 569 | * This API will hold the system reset active, Gpu_81X_ResetRemoval() must be 570 | * called to release the system reset. 571 | */ 572 | void 573 | Gpu_81X_ResetActive (Gpu_Hal_Context_t *host) 574 | { 575 | Gpu_HostCommand_Ext3(host, GPU_81X_RESET_ACTIVE); 576 | } 577 | 578 | 579 | /* 580 | * Gpu_81X_ResetRemoval() 581 | * 582 | * This API will release the system reset, and the system will exit reset and 583 | * behave as after POR, settings done through SPI will not be affected. 584 | */ 585 | void 586 | Gpu_81X_ResetRemoval (Gpu_Hal_Context_t *host) 587 | { 588 | Gpu_HostCommand_Ext3(host, GPU_81X_RESET_REMOVAL); 589 | } 590 | 591 | 592 | /* 593 | * Gpu_Hal_SetSPI() 594 | * 595 | * Set EVE spi communication mode 596 | */ 597 | int16_t 598 | Gpu_Hal_SetSPI (Gpu_Hal_Context_t *host, 599 | GPU_SPI_NUMCHANNELS_T numchnls, 600 | GPU_SPI_NUMDUMMYBYTES numdummy) 601 | { 602 | uint8_t writebyte = 0; 603 | 604 | if((numchnls > GPU_SPI_QUAD_CHANNEL) || 605 | (numdummy > GPU_SPI_TWODUMMY) || 606 | (numdummy < GPU_SPI_ONEDUMMY)) 607 | return -1; 608 | 609 | /* swicth EVE to multi channel SPI mode */ 610 | writebyte = numchnls; 611 | if(numdummy == GPU_SPI_TWODUMMY) 612 | writebyte |= SPI_TWO_DUMMY_BYTE; 613 | Gpu_Hal_Wr8(host, REG_SPI_WIDTH, writebyte); 614 | 615 | /* FT81x swicthed to dual/quad mode, now update global HAL context */ 616 | host->spichannel = numchnls; 617 | host->spinumdummy = numdummy; 618 | 619 | return 0; 620 | } 621 | 622 | #endif /* (FT81X_ENABLE) || (BT81X_ENABLE) */ 623 | 624 | /*****************************************************************************/ 625 | 626 | /* 627 | * Gpu_Hal_Updatecmdfifo() 628 | * 629 | * Function to update global HAL context variable cmd_fifo_wp pointer and write 630 | * to REG_CMD_WRITE to indicate GPU to start processing new commands in RAM_CMD 631 | */ 632 | void 633 | Gpu_Hal_Updatecmdfifo (Gpu_Hal_Context_t *host, 634 | uint32_t count) 635 | { 636 | host->cmd_fifo_wp = (host->cmd_fifo_wp + count) & FIFO_SIZE_MASK; 637 | 638 | /* 4 byte alignment */ 639 | host->cmd_fifo_wp = (host->cmd_fifo_wp + 3) & FIFO_BYTE_ALIGNMENT_MASK; 640 | Gpu_Hal_Wr16(host,REG_CMD_WRITE,host->cmd_fifo_wp); 641 | } 642 | 643 | 644 | /* 645 | * Gpu_Cmdfifo_Freespace() 646 | * 647 | * Function to compute available freespace in RAM_CMD. RAM_CMD is 4K in size. 648 | * REG_CMD_READ reg provides command buffer read pointer. 649 | */ 650 | uint16_t 651 | Gpu_Cmdfifo_Freespace (Gpu_Hal_Context_t *host) 652 | { 653 | uint16_t fullness,retval; 654 | 655 | fullness = (host->cmd_fifo_wp-Gpu_Hal_Rd16(host,REG_CMD_READ))&FIFO_SIZE_MASK; 656 | retval = (CMD_FIFO_SIZE - 4) - fullness; 657 | 658 | return (retval); 659 | } 660 | 661 | 662 | /* 663 | * Gpu_Hal_WrCmdBuf() 664 | * 665 | * Continuous write to RAM_CMD with wait with start address as 666 | * host->cmd_fifo_wp + RAM_CMD. FT81x RAM_CMD size is 4K (4096 bytes). 667 | * Hence one SPI write is adequate. 668 | */ 669 | void 670 | Gpu_Hal_WrCmdBuf (Gpu_Hal_Context_t *host, 671 | uint8_t *buffer, 672 | uint32_t count) 673 | { 674 | uint32_t length =0, SizeTransfered = 0,availablefreesize; 675 | 676 | do 677 | { 678 | length = count; 679 | availablefreesize = Gpu_Cmdfifo_Freespace(host); 680 | 681 | if (length > availablefreesize) 682 | length = availablefreesize; 683 | 684 | Gpu_Hal_CheckCmdBuffer(host,length); 685 | Gpu_Hal_StartCmdTransfer(host,GPU_WRITE,length); 686 | 687 | SizeTransfered = 0; 688 | while (length--) 689 | { 690 | Gpu_Hal_Transfer8(host,*buffer); 691 | buffer++; 692 | SizeTransfered ++; 693 | } 694 | 695 | buffer += SizeTransfered; 696 | length = SizeTransfered; 697 | 698 | Gpu_Hal_EndTransfer(host); 699 | Gpu_Hal_Updatecmdfifo(host,length); 700 | Gpu_Hal_WaitCmdfifo_empty(host); 701 | 702 | count -= length; 703 | 704 | } while (count > 0); 705 | } 706 | 707 | 708 | /* 709 | * Gpu_Hal_CheckCmdBuffer() 710 | * 711 | * Blocking function call. Blocks until "count" number of bytes gets available 712 | * in RAM_CMD. 713 | */ 714 | void 715 | Gpu_Hal_CheckCmdBuffer (Gpu_Hal_Context_t *host, 716 | uint32_t count) 717 | { 718 | uint16_t getfreespace; 719 | do 720 | { 721 | getfreespace = Gpu_Cmdfifo_Freespace(host); 722 | } while(getfreespace < count); 723 | } 724 | 725 | 726 | /* 727 | * Gpu_Hal_WaitCmdfifo_empty() 728 | * 729 | * Blocking function call. Blocks until all commands in RAM_CMD are executed and 730 | * it is fully empty. 731 | */ 732 | void 733 | Gpu_Hal_WaitCmdfifo_empty (Gpu_Hal_Context_t *host) 734 | { 735 | while(Gpu_Hal_Rd16(host,REG_CMD_READ) != Gpu_Hal_Rd16(host,REG_CMD_WRITE)); 736 | 737 | host->cmd_fifo_wp = Gpu_Hal_Rd16(host,REG_CMD_WRITE); 738 | } 739 | 740 | 741 | /* 742 | * Gpu_Hal_WrCmdBuf_nowait() 743 | * 744 | * Continuous write to RAM_CMD with no wait. 745 | */ 746 | void 747 | Gpu_Hal_WrCmdBuf_nowait (Gpu_Hal_Context_t *host, 748 | uint8_t *buffer, 749 | uint32_t count) 750 | { 751 | uint32_t length =0, SizeTransfered = 0 , availablefreesize; 752 | 753 | do 754 | { 755 | length = count; 756 | availablefreesize = Gpu_Cmdfifo_Freespace(host); 757 | 758 | if (length > availablefreesize) 759 | length = availablefreesize; 760 | 761 | Gpu_Hal_CheckCmdBuffer(host,length); 762 | Gpu_Hal_StartCmdTransfer(host,GPU_WRITE,length); 763 | 764 | SizeTransfered = 0; 765 | while (length--) 766 | { 767 | Gpu_Hal_Transfer8(host,*buffer); 768 | buffer++; 769 | SizeTransfered ++; 770 | } 771 | 772 | buffer += SizeTransfered; 773 | length = SizeTransfered; 774 | 775 | Gpu_Hal_EndTransfer(host); 776 | Gpu_Hal_Updatecmdfifo(host,length); 777 | 778 | count -= length; 779 | 780 | } while (count > 0); 781 | } 782 | 783 | 784 | /* 785 | * Gpu_Hal_WaitCmdfifo_empty_status() 786 | */ 787 | uint8_t 788 | Gpu_Hal_WaitCmdfifo_empty_status (Gpu_Hal_Context_t *host) 789 | { 790 | if(Gpu_Hal_Rd16(host,REG_CMD_READ) != Gpu_Hal_Rd16(host,REG_CMD_WRITE)) 791 | { 792 | return 0; 793 | } 794 | else 795 | { 796 | host->cmd_fifo_wp = Gpu_Hal_Rd16(host,REG_CMD_WRITE); 797 | return 1; 798 | } 799 | } 800 | 801 | 802 | /* 803 | * Gpu_Hal_WaitLogo_Finish() 804 | */ 805 | void 806 | Gpu_Hal_WaitLogo_Finish (Gpu_Hal_Context_t *host) 807 | { 808 | int16_t cmdrdptr,cmdwrptr; 809 | 810 | do 811 | { 812 | cmdrdptr = Gpu_Hal_Rd16(host,REG_CMD_READ); 813 | cmdwrptr = Gpu_Hal_Rd16(host,REG_CMD_WRITE); 814 | } while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0)); 815 | 816 | host->cmd_fifo_wp = 0; 817 | } 818 | 819 | 820 | /* 821 | * Gpu_Hal_ResetCmdFifo() 822 | */ 823 | void 824 | Gpu_Hal_ResetCmdFifo (Gpu_Hal_Context_t *host) 825 | { 826 | host->cmd_fifo_wp = 0; 827 | } 828 | 829 | 830 | /* 831 | * Gpu_Hal_WrCmd32() 832 | */ 833 | void 834 | Gpu_Hal_WrCmd32 (Gpu_Hal_Context_t *host, 835 | uint32_t cmd) 836 | { 837 | Gpu_Hal_CheckCmdBuffer(host,sizeof(cmd)); 838 | Gpu_Hal_Wr32(host,RAM_CMD + host->cmd_fifo_wp,cmd); 839 | Gpu_Hal_Updatecmdfifo(host,sizeof(cmd)); 840 | } 841 | 842 | /*****************************************************************************/ 843 | 844 | /* 845 | * Fifo_Init() 846 | * 847 | * Init all the parameters of fifo buffer. 848 | */ 849 | void 850 | Fifo_Init (Fifo_t *pFifo, 851 | uint32_t StartAddress, 852 | uint32_t Length, 853 | uint32_t HWReadRegAddress, 854 | uint32_t HWWriteRegAddress) 855 | { 856 | /* update the context parameters */ 857 | pFifo->fifo_buff = StartAddress; 858 | pFifo->fifo_len = Length; 859 | pFifo->fifo_rp = pFifo->fifo_wp = 0; 860 | 861 | /* update the hardware register addresses - specific to FT800 series chips */ 862 | pFifo->HW_Read_Reg = HWReadRegAddress; 863 | pFifo->HW_Write_Reg = HWWriteRegAddress; 864 | } 865 | 866 | 867 | /* 868 | * Fifo_Update() 869 | * 870 | * Update both the read and write pointers. 871 | */ 872 | void 873 | Fifo_Update (Gpu_Hal_Context_t *host, 874 | Fifo_t *pFifo) 875 | { 876 | pFifo->fifo_rp = Gpu_Hal_Rd32(host,pFifo->HW_Read_Reg); 877 | } 878 | 879 | 880 | /* 881 | * Fifo_Write() 882 | * 883 | * Just write and update the write register. 884 | */ 885 | uint32_t 886 | Fifo_Write (Gpu_Hal_Context_t *host, 887 | Fifo_t *pFifo, 888 | uint8_t *buffer, 889 | uint32_t NumbytetoWrite) 890 | { 891 | uint32_t FreeSpace = Fifo_GetFreeSpace(host,pFifo),TotalBytes = NumbytetoWrite; 892 | 893 | if(NumbytetoWrite > FreeSpace) 894 | { 895 | /* update the read pointer and get the free space */ 896 | Fifo_Update(host,pFifo); 897 | FreeSpace = Fifo_GetFreeSpace(host,pFifo); 898 | 899 | if(NumbytetoWrite > FreeSpace) 900 | TotalBytes = FreeSpace; 901 | } 902 | 903 | /* sanity check */ 904 | if(TotalBytes <= 0) 905 | return 0; /* error condition */ 906 | 907 | /* check for the loopback conditions */ 908 | if(pFifo->fifo_wp + TotalBytes >= pFifo->fifo_len) 909 | { 910 | uint32_t partialchunk, secpartialchunk; 911 | partialchunk = pFifo->fifo_len - pFifo->fifo_wp; 912 | secpartialchunk = TotalBytes - partialchunk; 913 | 914 | Gpu_Hal_WrMem(host,pFifo->fifo_buff + pFifo->fifo_wp,buffer,partialchunk); 915 | if(secpartialchunk > 0) 916 | Gpu_Hal_WrMem(host,pFifo->fifo_buff,buffer + partialchunk,secpartialchunk); 917 | 918 | pFifo->fifo_wp = secpartialchunk; 919 | } 920 | else 921 | { 922 | Gpu_Hal_WrMem(host,pFifo->fifo_buff + pFifo->fifo_wp,buffer,TotalBytes); 923 | pFifo->fifo_wp += TotalBytes; 924 | } 925 | 926 | /* update the write pointer address in write register */ 927 | Gpu_Hal_Wr32(host,pFifo->HW_Write_Reg,pFifo->fifo_wp); 928 | 929 | return TotalBytes; 930 | } 931 | 932 | 933 | /* 934 | * Fifo_Write32() 935 | * 936 | * Just write one word and update the write register 937 | */ 938 | void 939 | Fifo_Write32 (Gpu_Hal_Context_t *host, 940 | Fifo_t *pFifo, 941 | uint32_t WriteWord) 942 | { 943 | Fifo_WriteWait(host,pFifo,(uint8_t *)&WriteWord,4); 944 | } 945 | 946 | 947 | /* 948 | * Fifo_WriteWait() 949 | * 950 | * Write and wait for the fifo to be empty. Handle cases even if the Numbytes 951 | * are more than freespace. 952 | */ 953 | void 954 | Fifo_WriteWait (Gpu_Hal_Context_t *host, 955 | Fifo_t *pFifo, 956 | uint8_t *buffer, 957 | uint32_t Numbyte) 958 | { 959 | uint32_t TotalBytes = Numbyte,currchunk = 0,FreeSpace; 960 | uint8_t *pbuff = buffer; 961 | 962 | /* blocking call, manage to check for the error case and break in case of error */ 963 | while(TotalBytes > 0) 964 | { 965 | currchunk = TotalBytes; 966 | FreeSpace = Fifo_GetFreeSpace(host,pFifo); 967 | 968 | if(currchunk > FreeSpace) 969 | currchunk = FreeSpace; 970 | 971 | Fifo_Write(host,pFifo,pbuff,currchunk); 972 | pbuff += currchunk; 973 | TotalBytes -= currchunk; 974 | } 975 | } 976 | 977 | 978 | /* 979 | * Fifo_GetFreeSpace() 980 | * 981 | * Get the free space in the fifo - make sure the return value is maximum 982 | * of (LENGTH - 4). 983 | */ 984 | uint32_t 985 | Fifo_GetFreeSpace (Gpu_Hal_Context_t *host, 986 | Fifo_t *pFifo) 987 | { 988 | uint32_t FreeSpace = 0; 989 | 990 | Fifo_Update(host,pFifo); 991 | 992 | if(pFifo->fifo_wp >= pFifo->fifo_rp) 993 | FreeSpace = pFifo->fifo_len - pFifo->fifo_wp + pFifo->fifo_rp; 994 | else 995 | FreeSpace = pFifo->fifo_rp - pFifo->fifo_wp; 996 | 997 | if(FreeSpace >= 4) 998 | FreeSpace -= 4; 999 | 1000 | return FreeSpace; 1001 | } 1002 | 1003 | /*****************************************************************************/ 1004 | 1005 | /* 1006 | * Gpu_Hal_Dec2Ascii() 1007 | */ 1008 | int32_t 1009 | Gpu_Hal_Dec2Ascii (char8_t *pSrc, 1010 | int32_t value) 1011 | { 1012 | int16_t Length; 1013 | char8_t *pdst,charval; 1014 | int32_t CurrVal = value,tmpval,i; 1015 | char8_t tmparray[16]; 1016 | uchar8_t idx = 0; 1017 | 1018 | Length = strlen(pSrc); 1019 | pdst = pSrc + Length; 1020 | 1021 | if(0 == value) 1022 | { 1023 | *pdst++ = '0'; 1024 | *pdst++ = '\0'; 1025 | return 0; 1026 | } 1027 | 1028 | if(CurrVal < 0) 1029 | { 1030 | *pdst++ = '-'; 1031 | CurrVal = - CurrVal; 1032 | } 1033 | /* insert the value */ 1034 | while(CurrVal > 0){ 1035 | tmpval = CurrVal; 1036 | CurrVal /= 10; 1037 | tmpval = tmpval - CurrVal*10; 1038 | charval = '0' + tmpval; 1039 | tmparray[idx++] = charval; 1040 | } 1041 | 1042 | for(i=0;i getfreespace) 1084 | length = getfreespace; 1085 | 1086 | Gpu_Hal_CheckCmdBuffer(host,length); 1087 | Gpu_Hal_StartCmdTransfer(host,GPU_WRITE,length); 1088 | 1089 | SizeTransfered = 0; 1090 | while (length--) 1091 | { 1092 | Gpu_Hal_Transfer8(host,pgm_read_byte_near(buffer)); 1093 | buffer++; 1094 | SizeTransfered ++; 1095 | } 1096 | 1097 | length = SizeTransfered; 1098 | 1099 | Gpu_Hal_EndTransfer(host); 1100 | Gpu_Hal_Updatecmdfifo(host,length); 1101 | 1102 | Gpu_Hal_WaitCmdfifo_empty(host); 1103 | 1104 | count -= length; 1105 | } while (count > 0); 1106 | } 1107 | -------------------------------------------------------------------------------- /Gpu_Hal.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Bridgetek Pte Ltd 3 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 4 | * Copyright (c) Skalski Embedded Technologies 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 7 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 8 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9 | * ARE DISCLAIMED. IN NO EVENT SHALL BRIDGETEK PTE LTD BE LIABLE FOR ANY 10 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES 12 | * LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 13 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 14 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 15 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | * 17 | * BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON 18 | * BRIDGETEK PARTS. 19 | * 20 | * BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE 21 | * INFORMATION IS NOT MODIFIED. 22 | * 23 | * IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, 24 | * IT IS THE RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES 25 | * AND SUBSEQUENT WHQL RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 26 | */ 27 | 28 | #ifndef _GPU_HAL_H_ 29 | #define _GPU_HAL_H_ 30 | 31 | #define DUMMY_BYTE 0x00 32 | #define FIFO_SIZE_MASK (4095) 33 | #define FIFO_BYTE_ALIGNMENT_MASK (0xFFC) 34 | 35 | /* only for FT232H_MINGW_PLATFORM */ 36 | #define SPI_TRANSFER_OPTIONS_CHIPSELECT_ENABLE 0x00000002 37 | #define SPI_TRANSFER_OPTIONS_CHIPSELECT_DISABLE 0x00000004 38 | 39 | /******************************************************************************/ 40 | 41 | typedef enum { 42 | GPU_I2C_MODE = 0, 43 | GPU_SPI_MODE, 44 | GPU_MODE_COUNT, 45 | GPU_MODE_UNKNOWN = GPU_MODE_COUNT 46 | }GPU_HAL_MODE_E; 47 | 48 | /******************************************************************************/ 49 | 50 | typedef enum { 51 | GPU_HAL_OPENED, 52 | GPU_HAL_READING, 53 | GPU_HAL_WRITING, 54 | GPU_HAL_CLOSED, 55 | GPU_HAL_STATUS_COUNT, 56 | GPU_HAL_STATUS_ERROR = GPU_HAL_STATUS_COUNT 57 | }GPU_HAL_STATUS_E; 58 | 59 | /******************************************************************************/ 60 | 61 | typedef struct { 62 | union { 63 | uint8_t spi_cs_pin_no; /* spi chip select number of ft8xx chip */ 64 | uint8_t i2c_addr; /* i2c address of ft8xx chip */ 65 | }; 66 | union { 67 | uint16_t spi_clockrate_khz; 68 | uint16_t i2c_clockrate_khz; 69 | }; 70 | uint8_t channel_no; /* mpsse channel number */ 71 | uint8_t pdn_pin_no; /* ft8xx power down pin number */ 72 | }Gpu_Hal_Config_t; 73 | 74 | /******************************************************************************/ 75 | 76 | typedef struct { 77 | uint8_t reserved; 78 | }Gpu_App_Context_t; 79 | 80 | /******************************************************************************/ 81 | 82 | typedef struct { 83 | uint32_t TotalChannelNum; 84 | }Gpu_HalInit_t; 85 | 86 | /******************************************************************************/ 87 | 88 | typedef enum { 89 | GPU_READ = 0, 90 | GPU_WRITE, 91 | }GPU_TRANSFERDIR_T; 92 | 93 | /******************************************************************************/ 94 | 95 | typedef struct { 96 | Gpu_App_Context_t app_header; 97 | Gpu_Hal_Config_t hal_config; 98 | 99 | uint16_t cmd_fifo_wp; /* coprocessor fifo write pointer */ 100 | uint16_t dl_buff_wp; /* display command memory write pointer */ 101 | 102 | GPU_HAL_STATUS_E status; 103 | void *hal_handle; 104 | void *hal_handle2; 105 | 106 | /* additions specific to ft81x */ 107 | uint8_t spichannel; 108 | uint8_t spinumdummy; 109 | uint8_t *spiwrbuf_ptr; 110 | }Gpu_Hal_Context_t; 111 | 112 | /******************************************************************************/ 113 | 114 | typedef struct Fifo_t{ 115 | uint32_t fifo_buff; /* fifo buffer address */ 116 | int32_t fifo_len; /* fifo length */ 117 | int32_t fifo_wp; /* fifo write pointer - maintained by host */ 118 | int32_t fifo_rp; /* fifo read point - maintained by devicea */ 119 | 120 | /* FT800 series specific registers */ 121 | uint32_t HW_Read_Reg; /* hardware fifo read register */ 122 | uint32_t HW_Write_Reg; /* hardware fifo write register */ 123 | }Fifo_t; 124 | 125 | /******************************************************************************/ 126 | 127 | typedef enum { 128 | GPU_INTERNAL_OSC = 0x48, /* default */ 129 | GPU_EXTERNAL_OSC = 0x44, 130 | }GPU_PLL_SOURCE_T; 131 | 132 | typedef enum { 133 | GPU_PLL_48M = 0x62, /* default */ 134 | GPU_PLL_36M = 0x61, 135 | GPU_PLL_24M = 0x64, 136 | }GPU_PLL_FREQ_T; 137 | 138 | typedef enum { 139 | GPU_ACTIVE_M = 0x00, 140 | GPU_STANDBY_M = 0x41, /* default */ 141 | GPU_SLEEP_M = 0x42, 142 | GPU_POWERDOWN_M = 0x50, 143 | }GPU_POWER_MODE_T; 144 | 145 | /******************************************************************************/ 146 | 147 | typedef enum { 148 | GPU_SPI_SINGLE_CHANNEL = 0, 149 | GPU_SPI_DUAL_CHANNEL = 1, 150 | GPU_SPI_QUAD_CHANNEL = 2, 151 | }GPU_SPI_NUMCHANNELS_T; 152 | 153 | typedef enum { 154 | GPU_SPI_ONEDUMMY = 1, 155 | GPU_SPI_TWODUMMY = 2, 156 | }GPU_SPI_NUMDUMMYBYTES; 157 | 158 | #define SPI_ONE_DUMMY_BYTE (0x00) 159 | #define SPI_TWO_DUMMY_BYTE (0x04) 160 | #define SPI_SINGLE_CHANNEL (0x00) 161 | #define SPI_DUAL_CHANNEL (0x01) 162 | #define SPI_QUAD_CHANNEL (0x02) 163 | 164 | /******************************************************************************/ 165 | 166 | bool_t Gpu_Hal_Init(Gpu_HalInit_t *halinit); 167 | bool_t Gpu_Hal_Open(Gpu_Hal_Context_t *host); 168 | void Gpu_Hal_Close(Gpu_Hal_Context_t *host); 169 | void Gpu_Hal_DeInit(); 170 | 171 | /******************************************************************************/ 172 | 173 | void Gpu_Hal_StartTransfer(Gpu_Hal_Context_t *host,GPU_TRANSFERDIR_T rw,uint32_t addr); 174 | void Gpu_Hal_StartCmdTransfer(Gpu_Hal_Context_t *host,GPU_TRANSFERDIR_T rw, uint16_t count); 175 | void Gpu_Hal_TransferString(Gpu_Hal_Context_t *host,const char8_t *string); 176 | uint8_t Gpu_Hal_Transfer8(Gpu_Hal_Context_t *host,uint8_t value); 177 | uint16_t Gpu_Hal_Transfer16(Gpu_Hal_Context_t *host,uint16_t value); 178 | uint32_t Gpu_Hal_Transfer32(Gpu_Hal_Context_t *host,uint32_t value); 179 | void Gpu_Hal_EndTransfer(Gpu_Hal_Context_t *host); 180 | 181 | /******************************************************************************/ 182 | 183 | uint8_t Gpu_Hal_Rd8(Gpu_Hal_Context_t *host,uint32_t addr); 184 | uint16_t Gpu_Hal_Rd16(Gpu_Hal_Context_t *host,uint32_t addr); 185 | uint32_t Gpu_Hal_Rd32(Gpu_Hal_Context_t *host,uint32_t addr); 186 | 187 | /******************************************************************************/ 188 | 189 | void Gpu_Hal_Wr8(Gpu_Hal_Context_t *host,uint32_t addr, uint8_t v); 190 | void Gpu_Hal_Wr16(Gpu_Hal_Context_t *host,uint32_t addr, uint16_t v); 191 | void Gpu_Hal_Wr32(Gpu_Hal_Context_t *host,uint32_t addr, uint32_t v); 192 | 193 | /******************************************************************************/ 194 | 195 | void Gpu_HostCommand(Gpu_Hal_Context_t *host,uint8_t cmd); 196 | void Gpu_HostCommand_Ext3(Gpu_Hal_Context_t *host,uint32_t cmd); 197 | 198 | /******************************************************************************/ 199 | 200 | void Gpu_Hal_Powercycle(Gpu_Hal_Context_t *host,bool_t up); 201 | void Gpu_Hal_Sleep(uint32_t ms); 202 | 203 | /******************************************************************************/ 204 | 205 | void Gpu_Hal_WrMem(Gpu_Hal_Context_t *host,uint32_t addr, const uint8_t *buffer, uint32_t length); 206 | void Gpu_Hal_RdMem(Gpu_Hal_Context_t *host,uint32_t addr, uint8_t *buffer, uint32_t length); 207 | void Gpu_Hal_DLSwap(Gpu_Hal_Context_t *host, uint8_t DL_Swap_Type); 208 | void Gpu_Hal_ResetDLBuffer(Gpu_Hal_Context_t *host); 209 | 210 | /******************************************************************************/ 211 | 212 | void Gpu_ClockSelect(Gpu_Hal_Context_t *host,GPU_PLL_SOURCE_T pllsource); 213 | void Gpu_PLL_FreqSelect(Gpu_Hal_Context_t *host,GPU_PLL_FREQ_T freq); 214 | void Gpu_PowerModeSwitch(Gpu_Hal_Context_t *host,GPU_POWER_MODE_T pwrmode); 215 | void Gpu_CoreReset(Gpu_Hal_Context_t *host); 216 | 217 | /******************************************************************************/ 218 | 219 | #if (defined(FT81X_ENABLE)) || (defined(BT81X_ENABLE)) 220 | 221 | #define GPU_81X_RESET_ACTIVE 0x000268 222 | #define GPU_81X_RESET_REMOVAL 0x002068 223 | 224 | typedef enum { 225 | GPU_SYSCLK_DEFAULT = 0x00, /* default 60MHz */ 226 | GPU_SYSCLK_84M = 0x07, 227 | GPU_SYSCLK_72M = 0x06, 228 | GPU_SYSCLK_60M = 0x05, 229 | GPU_SYSCLK_48M = 0x04, 230 | GPU_SYSCLK_36M = 0x03, 231 | GPU_SYSCLK_24M = 0x02, 232 | }GPU_81X_PLL_FREQ_T; 233 | 234 | typedef enum { 235 | GPU_MAIN_ROM = 0x80, /* main graphicas ROM used */ 236 | GPU_RCOSATAN_ROM = 0x40, /* line slope table used for */ 237 | GPU_SAMPLE_ROM = 0x20, /* JA samples */ 238 | GPU_JABOOT_ROM = 0x10, /* JA microcode */ 239 | GPU_J1BOOT_ROM = 0x08, /* J1 microcode */ 240 | GPU_ADC = 0x01, 241 | GPU_POWER_ON_ROM_AND_ADC = 0x00, 242 | }GPU_81X_ROM_AND_ADC_T; 243 | 244 | typedef enum { 245 | GPU_5MA = 0x00, /* default current */ 246 | GPU_10MA = 0x01, 247 | GPU_15MA = 0x02, 248 | GPU_20MA = 0x03, 249 | }GPU_81X_GPIO_DRIVE_STRENGTH_T; 250 | 251 | typedef enum { 252 | GPU_GPIO0 = 0x00, 253 | GPU_GPIO1 = 0x04, 254 | GPU_GPIO2 = 0x08, 255 | GPU_GPIO3 = 0x0C, 256 | GPU_GPIO4 = 0x10, 257 | GPU_DISP = 0x20, 258 | GPU_DE = 0x24, 259 | GPU_VSYNC_HSYNC = 0x28, 260 | GPU_PCLK = 0x2C, 261 | GPU_BACKLIGHT = 0x30, 262 | GPU_R_G_B = 0x34, 263 | GPU_AUDIO_L = 0x38, 264 | GPU_INT_N = 0x3C, 265 | GPU_TOUCHWAKE = 0x40, 266 | GPU_SCL = 0x44, 267 | GPU_SDA = 0x48, 268 | GPU_SPI_MISO_MOSI_IO2_IO3 = 0x4C, 269 | }GPU_81X_GPIO_GROUP_T; 270 | 271 | void Gpu_81X_SelectSysCLK(Gpu_Hal_Context_t *host, GPU_81X_PLL_FREQ_T freq); 272 | void Gpu_81X_PowerOffComponents(Gpu_Hal_Context_t *host, uint8_t val); 273 | void Gpu_81X_PadDriveStrength(Gpu_Hal_Context_t *host, GPU_81X_GPIO_DRIVE_STRENGTH_T strength, GPU_81X_GPIO_GROUP_T group); 274 | void Gpu_81X_ResetActive(Gpu_Hal_Context_t *host); 275 | void Gpu_81X_ResetRemoval(Gpu_Hal_Context_t *host); 276 | int16_t Gpu_Hal_SetSPI(Gpu_Hal_Context_t *host,GPU_SPI_NUMCHANNELS_T numchnls,GPU_SPI_NUMDUMMYBYTES numdummy); 277 | 278 | #endif /* (FT81X_ENABLE) || (BT81X_ENABLE) */ 279 | 280 | /******************************************************************************/ 281 | 282 | void Gpu_Hal_Updatecmdfifo(Gpu_Hal_Context_t *host,uint32_t count); 283 | uint16_t Gpu_Cmdfifo_Freespace(Gpu_Hal_Context_t *host); 284 | void Gpu_Hal_WrCmdBuf(Gpu_Hal_Context_t *host,uint8_t *buffer,uint32_t count); 285 | void Gpu_Hal_CheckCmdBuffer(Gpu_Hal_Context_t *host,uint32_t count); 286 | void Gpu_Hal_WaitCmdfifo_empty(Gpu_Hal_Context_t *host); 287 | void Gpu_Hal_WrCmdBuf_nowait(Gpu_Hal_Context_t *host,uint8_t *buffer,uint32_t count); 288 | uint8_t Gpu_Hal_WaitCmdfifo_empty_status(Gpu_Hal_Context_t *host); 289 | void Gpu_Hal_WaitLogo_Finish(Gpu_Hal_Context_t *host); 290 | void Gpu_Hal_ResetCmdFifo(Gpu_Hal_Context_t *host); 291 | void Gpu_Hal_WrCmd32(Gpu_Hal_Context_t *host,uint32_t cmd); 292 | 293 | /*******************************************************************************/ 294 | 295 | void Fifo_Init(Fifo_t *pFifo,uint32_t StartAddress,uint32_t Length,uint32_t HWReadRegAddress,uint32_t HWWriteRegAddress); 296 | void Fifo_Update(Gpu_Hal_Context_t *host,Fifo_t *pFifo); 297 | uint32_t Fifo_Write(Gpu_Hal_Context_t *host,Fifo_t *pFifo,uint8_t *buffer,uint32_t NumbytetoWrite); 298 | void Fifo_Write32(Gpu_Hal_Context_t *host,Fifo_t *pFifo,uint32_t WriteWord); 299 | void Fifo_WriteWait(Gpu_Hal_Context_t *host,Fifo_t *pFifo,uint8_t *buffer,uint32_t Numbyte); 300 | uint32_t Fifo_GetFreeSpace(Gpu_Hal_Context_t *host,Fifo_t *pFifo); 301 | 302 | /*******************************************************************************/ 303 | 304 | int32_t Gpu_Hal_Dec2Ascii(char8_t *pSrc,int32_t value); 305 | void Gpu_ClearScreen(Gpu_Hal_Context_t *host); 306 | 307 | /*******************************************************************************/ 308 | 309 | void Gpu_Hal_WrCmdBufFromFlash(Gpu_Hal_Context_t *host, PROGMEM prog_uchar8_t *buffer,uint32_t count); 310 | 311 | #endif /* _GPU_HAL_H_ */ 312 | -------------------------------------------------------------------------------- /Hal_Utils.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Bridgetek Pte Ltd 3 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 4 | * Copyright (c) Skalski Embedded Technologies 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 7 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 8 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9 | * ARE DISCLAIMED. IN NO EVENT SHALL BRIDGETEK PTE LTD BE LIABLE FOR ANY 10 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES 12 | * LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 13 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 14 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 15 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | * 17 | * BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON 18 | * BRIDGETEK PARTS. 19 | * 20 | * BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE 21 | * INFORMATION IS NOT MODIFIED. 22 | * 23 | * IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, 24 | * IT IS THE RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES 25 | * AND SUBSEQUENT WHQL RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 26 | */ 27 | 28 | 29 | #include "Platform.h" 30 | #include "Hal_Utils.h" 31 | #include "App_Common.h" 32 | 33 | 34 | /* fadeout effect by changing the display PWM from 100 till 0 */ 35 | void fadeout(Gpu_Hal_Context_t *phost) 36 | { 37 | int32_t i; 38 | 39 | for (i = 100; i >= 0; i -= 3) 40 | { 41 | Gpu_Hal_Wr8(phost,REG_PWM_DUTY,i); 42 | Gpu_Hal_Sleep(2); 43 | } 44 | } 45 | 46 | 47 | /* fadein effect by changing the display PWM from 0 till 100 and finally 128 */ 48 | void fadein(Gpu_Hal_Context_t *phost) 49 | { 50 | int32_t i; 51 | 52 | for (i = 0; i <=100 ; i += 3) 53 | { 54 | Gpu_Hal_Wr8(phost,REG_PWM_DUTY,i); 55 | Gpu_Hal_Sleep(2);//sleep for 2 ms 56 | } 57 | /* Finally make the PWM 100% */ 58 | i = 128; 59 | Gpu_Hal_Wr8(phost,REG_PWM_DUTY,i); 60 | } 61 | 62 | 63 | float_t cal_average(float_t * ptr_elements , uint16_t elements) 64 | { 65 | float_t average = 0.0, sum = 0.0; 66 | uint16_t i = 0; 67 | 68 | for (i = 0; i < elements; i++) 69 | sum += *(ptr_elements + i); 70 | 71 | average = sum / elements; 72 | 73 | return(average); 74 | } 75 | 76 | #ifdef POLAR_UTIL 77 | 78 | const uint16_t sintab[] = { 79 | 0, 402, 804, 1206, 1607, 2009, 2410, 2811, 3211, 3611, 4011, 4409, 4807, 80 | 5205, 5601, 5997, 6392, 6786, 7179, 7571, 7961, 8351, 8739, 9126, 9511, 81 | 9895, 10278, 10659, 11038, 11416, 11792, 12166, 12539, 12909, 13278, 82 | 13645, 14009, 14372, 14732, 15090, 15446, 15799, 16150, 16499, 16845, 83 | 17189, 17530, 17868, 18204, 18537, 18867, 19194, 19519, 19840, 20159, 84 | 20474, 20787, 21096, 21402, 21705, 22004, 22301, 22594, 22883, 23169, 85 | 23452, 23731, 24006, 24278, 24546, 24811, 25072, 25329, 25582, 25831, 86 | 26077, 26318, 26556, 26789, 27019, 27244, 27466, 27683, 27896, 28105, 87 | 28309, 28510, 28706, 28897, 29085, 29268, 29446, 29621, 29790, 29955, 88 | 30116, 30272, 30424, 30571, 30713, 30851, 30984, 31113, 31236, 31356, 89 | 31470, 31580, 31684, 31785, 31880, 31970, 32056, 32137, 32213, 32284, 90 | 32350, 32412, 32468, 32520, 32567, 32609, 32646, 32678, 32705, 32727, 91 | 32744, 32757, 32764, 32767, 32764}; 92 | 93 | 94 | int16_t qsin(uint16_t a) 95 | { 96 | uint8_t f; 97 | int16_t s0,s1; 98 | 99 | if (a & 32768) 100 | return -qsin(a & 32767); 101 | if (a & 16384) 102 | a = 32768 - a; 103 | f = a & 127; 104 | s0 = *(uint16_t *)(sintab + (a >> 7)); 105 | s1 = *(uint16_t *)(sintab + (a >> 7) + 1); 106 | return (s0 + ((int32_t)f * (s1 - s0) >> 7)); 107 | } 108 | 109 | 110 | int16_t qcos(uint16_t a) 111 | { 112 | return (qsin(a + 16384)); 113 | } 114 | 115 | void polarxy(int32_t r, float_t th, int32_t *x, 116 | int32_t *y, int32_t ox, int32_t oy) 117 | { 118 | *x = (16 * ox) + (((long)r * qsin(th)) >> 11) + 16 ; 119 | *y = (16 * oy) - (((long)r * qcos(th)) >> 11); 120 | } 121 | 122 | 123 | void polar(Gpu_Hal_Context_t *phost, int32_t r, 124 | float_t th, int32_t ox, int32_t oy) 125 | { 126 | int32_t x, y; 127 | polarxy(r, th, &x, &y, ox, oy); 128 | App_WrCoCmd_Buffer(phost,VERTEX2F(x,y)); 129 | 130 | } 131 | 132 | float_t da(float_t i, int16_t degree) 133 | { 134 | return (i - degree)* 32768 /360 ; 135 | } 136 | 137 | #endif /* POLAR_UTIL */ 138 | -------------------------------------------------------------------------------- /Hal_Utils.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Bridgetek Pte Ltd 3 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 4 | * Copyright (c) Skalski Embedded Technologies 5 | * 6 | * THIS SOFTWARE IS PROVIDED BY BRIDGETEK PTE LTD "AS IS" 7 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 8 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 9 | * ARE DISCLAIMED. IN NO EVENT SHALL BRIDGETEK PTE LTD BE LIABLE FOR ANY 10 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 11 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES 12 | * LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 13 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 14 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 15 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 16 | * 17 | * BRIDGETEK DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON 18 | * BRIDGETEK PARTS. 19 | * 20 | * BRIDGETEK DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE 21 | * INFORMATION IS NOT MODIFIED. 22 | * 23 | * IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, 24 | * IT IS THE RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES 25 | * AND SUBSEQUENT WHQL RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES. 26 | */ 27 | 28 | #ifndef _HAL_UTILS_H_ 29 | #define _HAL_UTILS_H_ 30 | 31 | /* Enable sin()/cos() calculator utilities */ 32 | #define POLAR_UTIL 33 | 34 | /* Undefine RGB from wingdi.h in Visual Studio */ 35 | #ifdef RGB 36 | #undef RGB 37 | #endif 38 | 39 | #define RGB(r,g,b) ((((vc_int32_t)(r)) << 16) | (((vc_int32_t)(g))<<8) | (b)) 40 | #define SQ(v) ((v) * (v)) 41 | #define MIN(x,y) ((x) > (y) ? (y) : (x)) 42 | #define MAX(x,y) ((x) > (y) ? (x) : (y)) 43 | #define PLAYCOLOR 0x00A0A080 44 | #define NOTE(n, sharp) (((n) - 'C') + ((sharp) * 128)) 45 | #define F16(s) ((int32_t)((s) * 65536)) 46 | #define INVALID_TOUCH_XY 0x8000 47 | #define ABS(x) ((x) > (0) ? (x) : (-x)) 48 | #define ALIGN_TWO_POWER_N(val,alignval) (((val)+(alignval-1))&(~(alignval-1))) 49 | 50 | void fadeout(Gpu_Hal_Context_t *phost); 51 | void fadein(Gpu_Hal_Context_t *phost); 52 | 53 | float_t cal_average(float_t * ptr_elements , uint16_t elements); 54 | 55 | #ifdef POLAR_UTIL 56 | 57 | int16_t qsin(uint16_t a); 58 | int16_t qcos(uint16_t a); 59 | 60 | void polarxy(int32_t r, float_t th, int32_t *x, int32_t *y, int32_t ox, int32_t oy); 61 | void polar(Gpu_Hal_Context_t *phost, int32_t r, float_t th, int32_t ox, int32_t oy); 62 | 63 | float_t da(float_t i, int16_t degree); 64 | 65 | #endif /* POLAR_UTIL */ 66 | 67 | #endif /* _HAL_UTILS_H_ */ 68 | -------------------------------------------------------------------------------- /Platform.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 3 | * Copyright (c) Skalski Embedded Technologies 4 | */ 5 | 6 | #ifndef _PLATFORM_H_ 7 | #define _PLATFORM_H_ 8 | 9 | /*****************************************************************************/ 10 | 11 | //#define EVE_1 1 12 | //#define EVE_2 1 13 | //#define EVE_3 1 14 | #define EVE_4 1 15 | 16 | #define EVE_4_INTERNAL_OSC 1 17 | //#define EVE_4_EXTERNAL_OSC 1 18 | 19 | //#define NTP_35 1 20 | //#define RTP_35 1 21 | //#define CTP_35 1 22 | //#define NTP_43 1 23 | //#define RTP_43 1 24 | //#define CTP_43 1 25 | //#define NTP_50 1 26 | //#define RTP_50 1 27 | //#define CTP_50 1 28 | //#define NTP_70 1 29 | //#define RTP_70 1 30 | //#define CTP_70 1 31 | //#define IPS_35 1 32 | //#define IPS_43 1 33 | //#define IPS_50 1 34 | //#define IPS_70 1 35 | #define IPS_101 1 36 | 37 | /*****************************************************************************/ 38 | 39 | #define ARDUINO_PLATFORM 40 | #define ARDUINO_PLATFORM_COCMD_BURST 41 | 42 | #ifdef __AVR__ 43 | #define GPIO_CS 10 44 | #define GPIO_PD 8 45 | #endif 46 | 47 | #ifdef ESP32 /* Riverdi IoT Display */ 48 | #define GPIO_CS 4 49 | #define GPIO_PD 33 50 | #endif 51 | 52 | /* Standard C libraries */ 53 | #include 54 | 55 | /* Standard Arduino libraries */ 56 | #include 57 | #include 58 | #include 59 | 60 | #ifdef __AVR__ 61 | #include 62 | #endif 63 | 64 | /*****************************************************************************/ 65 | 66 | /* type definitions for EVE HAL library */ 67 | 68 | #define TRUE (1) 69 | #define FALSE (0) 70 | 71 | typedef char bool_t; 72 | typedef char char8_t; 73 | typedef unsigned char uchar8_t; 74 | typedef signed char schar8_t; 75 | typedef float float_t; 76 | 77 | #ifdef ESP32 /* Riverdi IoT Display */ 78 | typedef PROGMEM const unsigned char prog_uchar8_t; 79 | #endif 80 | 81 | #ifdef __AVR__ 82 | typedef PROGMEM const unsigned char prog_uchar8_t; 83 | typedef PROGMEM const char prog_char8_t; 84 | typedef PROGMEM const uint8_t prog_uint8_t; 85 | typedef PROGMEM const int8_t prog_int8_t; 86 | typedef PROGMEM const uint16_t prog_uint16_t; 87 | typedef PROGMEM const int16_t prog_int16_t; 88 | typedef PROGMEM const uint32_t prog_uint32_t; 89 | typedef PROGMEM const int32_t prog_int32_t; 90 | #endif 91 | 92 | /* Predefined Riverdi modules */ 93 | #include "Riverdi_Modules.h" 94 | 95 | /* EVE inclusions */ 96 | #include "Gpu_Hal.h" 97 | #include "Gpu.h" 98 | #include "CoPro_Cmds.h" 99 | #include "Hal_Utils.h" 100 | 101 | #endif /*_PLATFORM_H_*/ 102 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | OVERVIEW 2 | -------- 3 | ![alt text](http://circuitcellar.com/wp-content/uploads/2016/10/FTDI-Img.png "riverdi-logo") 4 | 5 | *riverdi-eve-arduino* is an easy-to-use library and example Arduino app (good starting poiny for you own projects) for [*Riverdi Intelligent Display*](https://riverdi.com/product-category/intelligent-displays/bt817q/) driven by [*Bridgetek EVE graphics controllers*](http://brtchip.com/eve/): 6 | 7 | - __EVE 1__ series: FT800 and FT801, 8 | - __EVE 2__ series: FT810, FT811, FT812 and FT813, 9 | - __EVE 3__ series: BT815 and BT816, 10 | - __EVE 4__ series: BT817 and BT818 11 | 12 | Library supports instructions in a similar format to the [*FT80x and FT81x Series Programmers Guides*](https://brtchip.com/wp-content/uploads/Support/Documentation/Programming_Guides/ICs/EVE/FT81X_Series_Programmer_Guide.pdf), [*BT81X Series Programming Guide*](https://brtchip.com/wp-content/uploads/2022/12/BRT_AN_033_BT81X-Series-Programming-Guide.pdf) and the [*EVE Screen Editor*](https://brtchip.com/ese-2/). 13 | 14 | __Note:__ *a pure C version of library is available as a separate GitHub repository - [*riverdi-eve-lib*](https://github.com/riverdi/riverdi-eve-lib)* 15 | 16 | LIBRARY ARCHITECTURE 17 | -------------------- 18 | 19 | #### Example App 20 | 21 | The *riverdi-eve-arduino.ino* file can be edited to produce the final application, calling the functions from the underlying layers. 22 | 23 | #### API Layer 24 | 25 | This layer is designed to allow the main application to use syntax close to that of the *FT80X/FT81X Programmers Guide* and make it more user friendly. The functions provided in this layer handle co-processor operation and assist with creating and executing co-processor lists as well as keeping track of the offset within the FIFO for each command and sending parameters of commands such as text strings. 26 | 27 | #### EVE Layer / Host Layer 28 | 29 | This layer translates the calls from the API layer above into a series of SPI byte transfers formatted for the protocol used by the FT8XX. It includes a series of functions which send the register address as well as for reading and writing 8/16/32-bit values. It also has functions for checking the read and write pointers of the RAM_CMD FIFO and for checking the free space available, which are used by the layers above. This layer provides also an interface to the hardware. It takes the SPI transfers from the EVE layer and translates them into the low-level operations (SPI and GPIO operations for chip select and power down). 30 | 31 | COMPILING LIBRARY 32 | ----------------- 33 | 34 | 1. Clone the repository (if you haven't done so already): 35 | ``` 36 | git clone https://github.com/riverdi/riverdi-eve-arduino.git 37 | ``` 38 | 2. Download and install the Arduino IDE from http://www.arduino.cc/en/Main/Software 39 | 3. Start the Arduino IDE 40 | 4. File > Open > select the *riverdi-eve-arduino.ino* file 41 | 5. Build (Ctrl+R) and upload (Ctrl+U) project to your Arduino Device. 42 | 43 | __Note:__ *before compilation please edit Platform.h file to choose Embedded Video Engine series (-DEVE_1, -DEVE_2, -DEVE_3 or -DEVE_4 flags), choose type and size of connected TFT module (choose predefined macros for Riverdi EVE modules or edit timings manually in Riverdi_Modules.h file for custom displays) or to redefine Chip Select and Power Down pins (default configuration supports [*Arduino Riverdi TFT Shield*](https://riverdi.com/product/arduino-riverdi-tft-shield/)).* 44 | 45 | GETTING HELP 46 | ------------ 47 | 48 | Please contact Riverdi support - [**](contact@riverdi.com) 49 | 50 | LICENSE 51 | ------- 52 | 53 | See *LICENSE.txt* file for details. 54 | -------------------------------------------------------------------------------- /Riverdi_Modules.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) Riverdi Sp. z o.o. sp. k. 3 | * Copyright (c) Skalski Embedded Technologies 4 | */ 5 | 6 | #ifndef _MODULES_H_ 7 | #define _MODULES_H_ 8 | 9 | /* 10 | * Embedded Video Engine Series 11 | */ 12 | 13 | #if defined (EVE_1) 14 | #define FT80X_ENABLE 15 | #elif defined (EVE_2) 16 | #define FT81X_ENABLE 17 | #elif defined (EVE_3) 18 | #define BT81X_ENABLE 19 | #elif defined (EVE_4) 20 | #define BT81X_ENABLE 21 | 22 | #else 23 | #error "Please choose generation of Embedded Video Engine (EVE_1, EVE_2, EVE_3, EVE_4)" 24 | #endif 25 | 26 | /* 27 | * Definitions for Riverdi Intelligent Modules 28 | */ 29 | 30 | #if defined (EVE_1) 31 | #if defined (NTP_50) || defined (RTP_50) || defined (CTP_50) || \ 32 | defined (NTP_70) || defined (RTP_70) || defined (CTP_70) || \ 33 | defined (IPS_35) || defined (IPS_43) || defined (IPS_50) || \ 34 | defined (IPS_70) || defined (IPS_101) 35 | #error "Not supported configuration - please contact Riverdi support " 36 | #endif 37 | 38 | #endif 39 | #if defined (EVE_2) 40 | #if defined (NTP_35) || defined (RTP_35) || defined (CTP_35) || \ 41 | defined (NTP_43) || defined (RTP_43) || defined (CTP_43) || \ 42 | defined (IPS_35) || defined (IPS_43) || defined (IPS_50) || \ 43 | defined (IPS_70) || defined (IPS_101) 44 | #error "Not supported configuration - please contact Riverdi support " 45 | #endif 46 | #endif 47 | #if defined (EVE_3) 48 | #if defined (IPS_35) || defined (IPS_43) || defined (IPS_50) || \ 49 | defined (IPS_70) || defined (IPS_101) 50 | #error "Not supported configuration - please contact Riverdi support " 51 | #endif 52 | #endif 53 | #if defined (EVE_4) 54 | #if defined (NTP_35) || defined (RTP_35) || defined (CTP_35) || \ 55 | defined (NTP_43) || defined (RTP_43) || defined (CTP_43) || \ 56 | defined (NTP_50) || defined (RTP_50) || defined (CTP_50) || \ 57 | defined (NTP_70) || defined (RTP_70) || defined (CTP_70) 58 | #error "Not supported configuration - please contact Riverdi support " 59 | #endif 60 | #endif 61 | 62 | #if defined (NTP_35) || defined (RTP_35) || defined (CTP_35) 63 | #define DispWidth 320L 64 | #define DispHeight 240L 65 | #define DispHCycle 408L 66 | #define DispHOffset 70L 67 | #define DispHSync0 0L 68 | #define DispHSync1 10L 69 | #define DispVCycle 263L 70 | #define DispVOffset 13L 71 | #define DispVSync0 0L 72 | #define DispVSync1 2L 73 | #define DispPCLK 6 74 | #define DispSwizzle 2 75 | #define DispPCLKPol 1 76 | #define DispCSpread 0 77 | #define DispDither 1 78 | #elif defined (IPS_35) 79 | #define DispWidth 320L 80 | #define DispHeight 240L 81 | #define DispHCycle 371L 82 | #define DispHOffset 43L 83 | #define DispHSync0 0L 84 | #define DispHSync1 4L 85 | #define DispVCycle 260L 86 | #define DispVOffset 12L 87 | #define DispVSync0 0L 88 | #define DispVSync1 4L 89 | #define DispPCLK 1 90 | #define DispSwizzle 0 91 | #define DispPCLKPol 1 92 | #define DispCSpread 0 93 | #define DispDither 0 94 | #define DispPLCLKFREQ 0x22 95 | #define DispPCLK2x 0 96 | #elif defined (NTP_43) || defined (RTP_43) || defined (CTP_43) 97 | #define DispWidth 480L 98 | #define DispHeight 272L 99 | #define DispHCycle 548L 100 | #define DispHOffset 43L 101 | #define DispHSync0 0L 102 | #define DispHSync1 41L 103 | #define DispVCycle 292L 104 | #define DispVOffset 12L 105 | #define DispVSync0 0L 106 | #define DispVSync1 10L 107 | #define DispPCLK 3 108 | #define DispSwizzle 0 109 | #define DispPCLKPol 1 110 | #define DispCSpread 0 111 | #define DispDither 1 112 | #elif defined (IPS_43) 113 | #define DispWidth 480L 114 | #define DispHeight 272L 115 | #define DispHCycle 531L 116 | #define DispHOffset 43L 117 | #define DispHSync0 0L 118 | #define DispHSync1 4L 119 | #define DispVCycle 292L 120 | #define DispVOffset 12L 121 | #define DispVSync0 0L 122 | #define DispVSync1 4L 123 | #define DispPCLK 1 124 | #define DispSwizzle 0 125 | #define DispPCLKPol 1 126 | #define DispCSpread 0 127 | #define DispDither 0 128 | #define DispPLCLKFREQ 0x232 129 | #define DispPCLK2x 0 130 | #elif defined (NTP_50) || defined (RTP_50) || defined (CTP_50) 131 | #define DispWidth 800L 132 | #define DispHeight 480L 133 | #define DispHCycle 1056L 134 | #define DispHOffset 46L 135 | #define DispHSync0 0L 136 | #define DispHSync1 10L 137 | #define DispVCycle 525L 138 | #define DispVOffset 23L 139 | #define DispVSync0 0L 140 | #define DispVSync1 10L 141 | #define DispPCLK 2 142 | #define DispSwizzle 0 143 | #define DispPCLKPol 0 144 | #define DispCSpread 0 145 | #define DispDither 1 146 | #elif defined (IPS_50) 147 | #define DispWidth 800L 148 | #define DispHeight 480L 149 | #define DispHCycle 816L 150 | #define DispHOffset 8L 151 | #define DispHSync0 0L 152 | #define DispHSync1 4L 153 | #define DispVCycle 496L 154 | #define DispVOffset 8L 155 | #define DispVSync0 0L 156 | #define DispVSync1 4L 157 | #define DispPCLK 1 158 | #define DispSwizzle 0 159 | #define DispPCLKPol 1 160 | #define DispCSpread 0 161 | #define DispDither 0 162 | #define DispPLCLKFREQ 0xD14 163 | #define DispPCLK2x 0 164 | #elif defined (NTP_70) || defined (RTP_70) || defined (CTP_70) 165 | #define DispWidth 800L 166 | #define DispHeight 480L 167 | #define DispHCycle 1056L 168 | #define DispHOffset 16L 169 | #define DispHSync0 0L 170 | #define DispHSync1 30L 171 | #define DispVCycle 525L 172 | #define DispVOffset 10L 173 | #define DispVSync0 0L 174 | #define DispVSync1 13L 175 | #define DispPCLK 2 176 | #define DispSwizzle 0 177 | #define DispPCLKPol 0 178 | #define DispCSpread 0 179 | #define DispDither 0 180 | #elif defined (IPS_70) 181 | #define DispWidth 1024L 182 | #define DispWidth_hsf 1076L 183 | #define DispHeight 600L 184 | #define DispHCycle 1344L 185 | #define DispHOffset 160L 186 | #define DispHSync0 0L 187 | #define DispHSync1 70L 188 | #define DispVCycle 635L 189 | #define DispVOffset 23L 190 | #define DispVSync0 0L 191 | #define DispVSync1 10L 192 | #define DispPCLK 1 193 | #define DispSwizzle 0 194 | #define DispPCLKPol 1 195 | #define DispCSpread 0 196 | #define DispDither 0 197 | #define DispPLCLKFREQ 0xD12 198 | #define DispPCLK2x 0 199 | #elif defined (IPS_101) 200 | #define DispWidth 1280L 201 | #define DispHeight 800L 202 | #define DispHCycle 1440L 203 | #define DispHOffset 88L 204 | #define DispHSync0 0L 205 | #define DispHSync1 20L 206 | #define DispVCycle 838L 207 | #define DispVOffset 23L 208 | #define DispVSync0 0L 209 | #define DispVSync1 10L 210 | #define DispPCLK 1 211 | #define DispSwizzle 0 212 | #define DispPCLKPol 1 213 | #define DispCSpread 0 214 | #define DispDither 0 215 | #define DispPLCLKFREQ 0x8c1 216 | #define DispPCLK2x 1 217 | #endif 218 | 219 | #endif /*_MODULES_H_*/ 220 | -------------------------------------------------------------------------------- /riverdi-eve-arduino.ino: -------------------------------------------------------------------------------- 1 | #include "Platform.h" 2 | #include "App_Common.h" 3 | 4 | /* Global used for buffer optimization */ 5 | Gpu_Hal_Context_t host, *phost; 6 | 7 | static void SAMAPP_GPU_Ball_Stencil(); 8 | 9 | /* setup */ 10 | void setup() 11 | { 12 | phost = &host; 13 | 14 | /* Init HW Hal */ 15 | App_Common_Init(&host); 16 | 17 | /* Screen Calibration*/ 18 | //App_Calibrate_Screen(&host); 19 | } 20 | 21 | /* loop */ 22 | void loop() 23 | { 24 | /* Show Bridgetek logo */ 25 | App_Show_Logo(&host); 26 | 27 | /* Main application - endless loop */ 28 | SAMAPP_GPU_Ball_Stencil(); 29 | 30 | /* Close all the opened handles */ 31 | Gpu_Hal_Close(phost); 32 | Gpu_Hal_DeInit(); 33 | } 34 | 35 | static void 36 | SAMAPP_GPU_Ball_Stencil() 37 | { 38 | uint8_t xflag, yflag; 39 | int16_t xball, yball, rball, pixel_precision, gridsize; 40 | int32_t displ, dispr, dispa, dispb; 41 | 42 | /* grid margins */ 43 | displ = 10; 44 | dispr = (DispWidth - 10); 45 | dispa = 50; 46 | dispb = (DispHeight - 10); 47 | 48 | /* grid size */ 49 | gridsize = 20; 50 | 51 | /* ball dimensions */ 52 | xball = (DispWidth/2); 53 | yball = (DispHeight/2); 54 | rball = (DispWidth/8); 55 | xflag = 1; 56 | yflag = 1; 57 | 58 | dispr -= ((dispr - displ)%gridsize); 59 | dispb -= ((dispb - dispa)%gridsize); 60 | 61 | /* endless loop */ 62 | while(1) 63 | { 64 | /* ball movement */ 65 | if(((xball + rball + 2) >= dispr) || ((xball - rball - 2) <= displ)) 66 | xflag ^= 1; 67 | 68 | if(((yball + rball + 8) >= dispb) || ((yball - rball - 8) <= dispa)) 69 | yflag ^= 1; 70 | 71 | if(xflag) 72 | xball += 2; 73 | else 74 | xball -= 2; 75 | 76 | if(yflag) 77 | yball += 8; 78 | else 79 | yball -= 8; 80 | 81 | /* set the precision of VERTEX2F coordinates */ 82 | #if defined (IPS_70) || (IPS_101) 83 | /* VERTEX2F range: -2048 to 2047 */ 84 | App_WrDl_Buffer(phost, VERTEX_FORMAT(3)); 85 | pixel_precision = 8; 86 | #else 87 | /* use default VERTEX_FORMAT(3) with VERTEX2F range: -1024 to 1023 */ 88 | pixel_precision = 16; 89 | #endif 90 | 91 | /* init and set background */ 92 | App_WrDl_Buffer(phost, CLEAR_COLOR_RGB(255, 255, 255)); 93 | App_WrDl_Buffer(phost, CLEAR(1, 1, 1)); 94 | App_WrDl_Buffer(phost, STENCIL_OP(INCR,INCR)); 95 | App_WrDl_Buffer(phost, COLOR_RGB(0, 0, 0)); 96 | 97 | /* draw grid */ 98 | App_WrDl_Buffer(phost, LINE_WIDTH(pixel_precision)); 99 | App_WrDl_Buffer(phost, BEGIN(LINES)); 100 | 101 | for(uint16_t i=0; i<=((dispr - displ)/gridsize); i++) 102 | { 103 | App_WrDl_Buffer(phost, VERTEX2F((displ + i*gridsize)*pixel_precision,dispa*pixel_precision)); 104 | App_WrDl_Buffer(phost, VERTEX2F((displ + i*gridsize)*pixel_precision,dispb*pixel_precision)); 105 | } 106 | 107 | for(uint16_t i=0; i<=((dispb - dispa)/gridsize); i++) 108 | { 109 | App_WrDl_Buffer(phost, VERTEX2F(displ*pixel_precision,(dispa + i*gridsize)*pixel_precision)); 110 | App_WrDl_Buffer(phost, VERTEX2F(dispr*pixel_precision,(dispa + i*gridsize)*pixel_precision)); 111 | } 112 | App_WrDl_Buffer(phost, END()); 113 | 114 | /* add simple text using built-in fonts */ 115 | { 116 | Gpu_Fonts_t font; 117 | uint8_t font_size; 118 | uint32_t font_table; 119 | uint32_t text_hoffset, text_voffset; 120 | 121 | #if defined (NTP_35) || (RTP_35) || (CTP_35) || (IPS_35) || (NTP_43) || (RTP_43) || (CTP_43) || (IPS_43) 122 | const uint8_t text[] = "Riverdi EVE Demo"; 123 | #elif defined (NTP_50) || (RTP_50) || (CTP_50) || (IPS_50) || (NTP_70) || (RTP_70) || (CTP_70) || (IPS_70) 124 | const uint8_t text[] = "Riverdi EVE Demo - https://www.riverdi.com"; 125 | #elif defined (IPS_101) 126 | const uint8_t text[] = "Riverdi EVE Demo - https://www.riverdi.com - contact@riverdi.com"; 127 | #endif 128 | 129 | text_hoffset = displ; /* set the same offset like for grid */ 130 | text_voffset = 5; 131 | 132 | font_size = 30; 133 | font_table = Gpu_Hal_Rd32(phost, ROMFONT_TABLEADDRESS); 134 | 135 | Gpu_Hal_RdMem(phost, (font_table + (font_size-16) * GPU_FONT_TABLE_SIZE), 136 | (uint8_t*)&font, GPU_FONT_TABLE_SIZE); 137 | 138 | App_WrDl_Buffer(phost, COLOR_RGB(0, 96, 169)); 139 | App_WrDl_Buffer(phost, BEGIN(BITMAPS)); 140 | App_WrDl_Buffer(phost, BITMAP_HANDLE((font_size%32))); 141 | 142 | for (uint8_t cnt = 0; cnt < sizeof(text)-1; cnt++) 143 | { 144 | App_WrDl_Buffer(phost, CELL(text[cnt])); 145 | App_WrDl_Buffer(phost, VERTEX2F(text_hoffset*pixel_precision, text_voffset*pixel_precision)); 146 | text_hoffset += font.FontWidth[text[cnt]]; 147 | } 148 | App_WrDl_Buffer(phost, END()); 149 | } 150 | 151 | /* draw ball and shadow */ 152 | App_WrDl_Buffer(phost, COLOR_MASK(1,1,1,1)); 153 | App_WrDl_Buffer(phost, STENCIL_FUNC(ALWAYS,1,255)); 154 | App_WrDl_Buffer(phost, STENCIL_OP(KEEP,KEEP)); 155 | App_WrDl_Buffer(phost, COLOR_RGB(255, 255, 255)); 156 | App_WrDl_Buffer(phost, POINT_SIZE(rball*16)); 157 | App_WrDl_Buffer(phost, BEGIN(FTPOINTS)); 158 | App_WrDl_Buffer(phost, VERTEX2F((xball - 1)*pixel_precision,(yball - 1)*pixel_precision)); 159 | App_WrDl_Buffer(phost, COLOR_RGB(0, 0, 0)); 160 | App_WrDl_Buffer(phost, COLOR_A(160)); 161 | App_WrDl_Buffer(phost, VERTEX2F((xball+pixel_precision)*pixel_precision,(yball+8)*pixel_precision)); 162 | App_WrDl_Buffer(phost, COLOR_A(255)); 163 | App_WrDl_Buffer(phost, COLOR_RGB(254, 172, 0)); 164 | App_WrDl_Buffer(phost, VERTEX2F(xball*pixel_precision,yball*pixel_precision)); 165 | App_WrDl_Buffer(phost, COLOR_RGB(255, 255, 255)); 166 | App_WrDl_Buffer(phost, STENCIL_FUNC(GEQUAL,1,1)); 167 | App_WrDl_Buffer(phost, STENCIL_OP(KEEP,KEEP)); 168 | App_WrDl_Buffer(phost, VERTEX2F(xball*pixel_precision,yball*pixel_precision)); 169 | App_WrDl_Buffer(phost, END()); 170 | 171 | /* display */ 172 | App_WrDl_Buffer(phost, DISPLAY()); 173 | 174 | /* download display list into DL RAM */ 175 | App_Flush_DL_Buffer(phost); 176 | 177 | /* do a swap */ 178 | Gpu_Hal_DLSwap(phost, DLSWAP_FRAME); 179 | 180 | } /* while */ 181 | } 182 | --------------------------------------------------------------------------------