├── import ├── __init__py ├── instructions │ ├── README.md │ ├── IMPORTED_l2gclean_Rtt.json │ ├── IMPORTED_l2gcleaninv_Rtt.json │ ├── IMPORTED_Rd_Ss.json │ ├── IMPORTED_Sd_Rs.json │ ├── IMPORTED_Rdd_Sss.json │ ├── IMPORTED_Sdd_Rss.json │ └── UNDOCUMENTED_SA2_TFRSI.json ├── registers │ ├── README.md │ ├── CtrRegs-C22.json │ ├── CtrRegs-C23.json │ ├── CtrRegs-C24.json │ ├── CtrRegs-C25.json │ ├── CtrRegs-C26.json │ ├── CtrRegs-C27.json │ ├── CtrRegs-C28.json │ ├── CtrRegs-C29.json │ ├── CtrRegs-C21.json │ ├── CtrRegs-C20.json │ ├── CtrRegs64-C21_20.json │ ├── CtrRegs64-C23_22.json │ ├── CtrRegs64-C25_24.json │ ├── CtrRegs64-C27_26.json │ └── CtrRegs64-C29_28.json ├── Register-template.json ├── README.md ├── Register64-template.json ├── gen_registers.py ├── SysRegs64-template.json ├── import_instructions.py └── Instruction-template.json ├── optional_requirements.txt ├── requirements.txt ├── test-bins ├── main.o └── hexagon-hello-loop ├── .gitmodules ├── __init__.py ├── Tests ├── __init__.py ├── testCodeGeneration.py ├── testRegister.py ├── testHelperFunction.py ├── testImmediate.py ├── testEncoding.py └── testInstruction.py ├── handwritten ├── misc_il_insns.json ├── hexagon_arch_h │ ├── includes.h │ ├── typedefs.h │ └── declarations.h ├── hexagon_il_c │ ├── exclude.c │ └── includes.c ├── hexagon_reg_tables_h │ └── includes.h ├── hexagon_il_X_ops_c │ ├── excludes.h │ ├── includes.h │ └── non_insn_ops.c ├── hexagon_il_h │ ├── includes.h │ ├── declarations.h │ └── macros.h ├── hexagon_il_getter_table_h │ └── includes.h ├── hexagon_h │ ├── includes.h │ ├── declarations.h │ └── macros.h ├── hexagon_arch_c │ └── include.c ├── asm_hexagon_c │ ├── include.c │ └── initialization.c ├── analysis_hexagon_c │ ├── include.c │ ├── initialization.c │ └── functions.c ├── README.md ├── hexagon_c │ ├── include.c │ └── functions.c ├── hexagon_disas_c │ ├── include.c │ └── types.c ├── asm-tests │ └── hexagon └── rzil-tests │ └── hexagon ├── .gitignore ├── setup.py ├── UnexpectedException.py ├── ImplementationException.py ├── HexagonArchInfo.py ├── .github └── workflows │ ├── reuse.yaml │ ├── black.yaml │ └── flake8.yml ├── PluginInfo.py ├── .clang-format ├── SubInstruction.py ├── .reuse └── dep5 ├── Conf.py ├── Instruction.py ├── InstructionEncoding.py ├── README.md ├── Operand.py ├── HardwareRegister.py ├── Immediate.py └── LICENSES ├── CC0-1.0.txt └── LGPL-3.0-only.txt /import/__init__py: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /optional_requirements.txt: -------------------------------------------------------------------------------- 1 | colorama~=0.4.3 -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | bitarray~=2.1.0 2 | setuptools~=68.1.2 -------------------------------------------------------------------------------- /test-bins/main.o: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rizinorg/rz-hexagon/HEAD/test-bins/main.o -------------------------------------------------------------------------------- /test-bins/hexagon-hello-loop: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/rizinorg/rz-hexagon/HEAD/test-bins/hexagon-hello-loop -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "rzil_compiler"] 2 | path = rzil_compiler 3 | url = git@github.com:rizinorg/rz-rzilcompiler.git 4 | -------------------------------------------------------------------------------- /__init__.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | -------------------------------------------------------------------------------- /Tests/__init__.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | -------------------------------------------------------------------------------- /handwritten/misc_il_insns.json: -------------------------------------------------------------------------------- 1 | { 2 | "qemu_defined" : [ 3 | "J2_endloop01", 4 | "J2_endloop1", 5 | "J2_endloop0" 6 | ] 7 | } -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | __pycache__ 2 | .idea 3 | rz_hexagon.egg-info/ 4 | Hexagon.json 5 | .config 6 | .last_llvm_commit_info 7 | .venv/ 8 | .vscode 9 | rizin/ 10 | -------------------------------------------------------------------------------- /handwritten/hexagon_arch_h/includes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_c/exclude.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | -------------------------------------------------------------------------------- /handwritten/hexagon_reg_tables_h/includes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_X_ops_c/excludes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include -------------------------------------------------------------------------------- /import/instructions/README.md: -------------------------------------------------------------------------------- 1 | Add an instruction here for import: 2 | - `cp ../Instruction-template.json UNDOCUMENTED_InstructionName.json` 3 | - Set data within the `UNDOCUMENTED_InstructionName.json` 4 | - Done. `LLVMImporter` will add the instruction. -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | from setuptools import setup, find_packages 6 | 7 | setup(name="rz-hexagon", version="1.0", packages=find_packages()) 8 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_h/includes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | -------------------------------------------------------------------------------- /UnexpectedException.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | 6 | class UnexpectedException(Exception): 7 | def __init__(self, message): 8 | super().__init__(message) 9 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_X_ops_c/includes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include "../hexagon_il.h" 6 | #include 7 | #include 8 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_getter_table_h/includes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | -------------------------------------------------------------------------------- /handwritten/hexagon_h/includes.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | -------------------------------------------------------------------------------- /handwritten/hexagon_arch_c/include.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | -------------------------------------------------------------------------------- /ImplementationException.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | 6 | class ImplementationException(NotImplementedError): 7 | def __init__(self, message): 8 | message = "\n\n" + message + "\nPlease update the implementation to cover this yet unknown" " case." 9 | super().__init__(message) 10 | -------------------------------------------------------------------------------- /handwritten/asm_hexagon_c/include.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | -------------------------------------------------------------------------------- /handwritten/analysis_hexagon_c/include.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | -------------------------------------------------------------------------------- /handwritten/README.md: -------------------------------------------------------------------------------- 1 | Some instructions are not parsed by the disassembler generator, because they are irrelevant for it. 2 | `endloop` instructions are one example. 3 | 4 | The names used in QEMU for them, can be added to `misc_il_insn.json`. 5 | They will be written to `hexagon_il_non_insn_ops.c` and declared in `hexagon_il.h`. 6 | 7 | If you need to define an arbitrary sub-routine, 8 | you can add it in `rzil_compiler/Resources/Hexagon/sub_routines.json`. -------------------------------------------------------------------------------- /handwritten/analysis_hexagon_c/initialization.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | RzAnalysisPlugin rz_analysis_plugin_hexagon = { 5 | .name = "hexagon", 6 | .desc = "Qualcomm Hexagon (QDSP6) V6", 7 | .license = "LGPL3", 8 | .arch = "hexagon", 9 | .bits = 32, 10 | .op = hexagon_v6_op, 11 | .esil = false, 12 | .get_reg_profile = get_reg_profile, 13 | .il_config = rz_hexagon_il_config, 14 | }; 15 | -------------------------------------------------------------------------------- /import/registers/README.md: -------------------------------------------------------------------------------- 1 | Add a register here for import: 2 | - `cp ../Register-template.json UNDOCUMENTED_RegisterName.json` 3 | - Set data within the `UNDOCUMENTED_RegisterName.json` 4 | - Done. `LLVMImporter` will add the register. 5 | 6 | If you need to add a register which already belongs to a certain class, simply name the file `-,json`. 7 | So for the `C20` register it would be `CtrRegs-C20.json`. 8 | 9 | Same logic applies for register classes (like `SysRegs64-template.json`). -------------------------------------------------------------------------------- /handwritten/hexagon_il_c/includes.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | -------------------------------------------------------------------------------- /HexagonArchInfo.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | ALL_REG_NAMES = list() # R0, ..., R30, R31, ..., C3, C1_0, ..., UPCYCLELO, VFR0, ... 6 | LLVM_FAKE_REGS = list() 7 | CALLEE_SAVED_REGS = list() 8 | CC_REGS = dict() # The register used in the calling convention. Argument and return regs. 9 | 10 | INSTRUCTION_LENGTH = 32 11 | 12 | IMMEDIATE_TYPES = dict() 13 | REG_CLASS_NAMES = dict() 14 | 15 | MAX_IMM_LEN = 32 16 | -------------------------------------------------------------------------------- /.github/workflows/reuse.yaml: -------------------------------------------------------------------------------- 1 | name: reuse 2 | 3 | on: [pull_request] 4 | 5 | jobs: 6 | linter: 7 | runs-on: ubuntu-latest 8 | steps: 9 | - uses: actions/checkout@v3 10 | - name: Set up Python 3.10 11 | uses: actions/setup-python@v3 12 | with: 13 | python-version: '3.10' 14 | - name: Install reuse 15 | run: | 16 | python -m pip install --upgrade pip 17 | pip install reuse 18 | - name: Analysing the code with reuse 19 | run: reuse lint 20 | -------------------------------------------------------------------------------- /handwritten/hexagon_c/include.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | #include 15 | #include 16 | -------------------------------------------------------------------------------- /Tests/testCodeGeneration.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import unittest 6 | 7 | from LLVMImporter import LLVMImporter 8 | 9 | 10 | class TestInstruction(unittest.TestCase): 11 | def setUp(self): 12 | self.interface = LLVMImporter(False, test_mode=True, gen_rzil=False, skip_pcpp=True, rzil_compile=False) 13 | self.json = self.interface.hexArch 14 | 15 | def test_code_generation(self) -> None: 16 | pass 17 | -------------------------------------------------------------------------------- /.github/workflows/black.yaml: -------------------------------------------------------------------------------- 1 | name: black 2 | 3 | on: [pull_request] 4 | 5 | jobs: 6 | linter: 7 | runs-on: ubuntu-latest 8 | steps: 9 | - uses: actions/checkout@v3 10 | - name: Set up Python 3.10 11 | uses: actions/setup-python@v3 12 | with: 13 | python-version: '3.10' 14 | - name: Install black 15 | run: | 16 | python -m pip install --upgrade pip 17 | pip install black 18 | - name: Analysing the code with black 19 | run: black -l 120 --check $(git ls-files '*.py') 20 | -------------------------------------------------------------------------------- /.github/workflows/flake8.yml: -------------------------------------------------------------------------------- 1 | name: flake8 2 | 3 | on: [pull_request] 4 | 5 | jobs: 6 | linter: 7 | runs-on: ubuntu-latest 8 | steps: 9 | - uses: actions/checkout@v3 10 | - name: Set up Python 3.10 11 | uses: actions/setup-python@v3 12 | with: 13 | python-version: '3.10' 14 | - name: Install flake8 15 | run: | 16 | python -m pip install --upgrade pip 17 | pip install flake8 18 | - name: Analysing the code with flake8 19 | run: flake8 --select=W504 --ignore=E203,W503 --max-line-length=120 $(git ls-files '*.py') 20 | -------------------------------------------------------------------------------- /handwritten/hexagon_disas_c/include.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | #include 10 | #include 11 | #include 12 | #include 13 | #include 14 | 15 | #if ASAN && !defined(__clang__) 16 | #define NO_OPT_IF_ASAN __attribute__((optimize(0))) 17 | #else 18 | #define NO_OPT_IF_ASAN 19 | #endif 20 | -------------------------------------------------------------------------------- /import/Register-template.json: -------------------------------------------------------------------------------- 1 | { 2 | "SSR": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "SSR", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Si", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 0 21 | ], 22 | "HWEncoding": [], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C22.json: -------------------------------------------------------------------------------- 1 | { 2 | "C22": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C22", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c22", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 89 21 | ], 22 | "HWEncoding": [0,1,1,0,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C23.json: -------------------------------------------------------------------------------- 1 | { 2 | "C23": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C23", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c23", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 90 21 | ], 22 | "HWEncoding": [1,1,1,0,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C24.json: -------------------------------------------------------------------------------- 1 | { 2 | "C24": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C24", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c24", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 91 21 | ], 22 | "HWEncoding": [0,0,0,1,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C25.json: -------------------------------------------------------------------------------- 1 | { 2 | "C25": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C25", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c25", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 92 21 | ], 22 | "HWEncoding": [1,0,0,1,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C26.json: -------------------------------------------------------------------------------- 1 | { 2 | "C26": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C26", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c26", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 93 21 | ], 22 | "HWEncoding": [0,1,0,1,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C27.json: -------------------------------------------------------------------------------- 1 | { 2 | "C27": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C27", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c27", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 94 21 | ], 22 | "HWEncoding": [1,1,0,1,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs-C28.json: -------------------------------------------------------------------------------- 1 | { 2 | "C28": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C28", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c28", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 95 21 | ], 22 | "HWEncoding": [0,0,1,1,1,0,0,0,0,0,0,0,0,0], 23 | "Namespace": "Hexagon", 24 | "RegAltNameIndices": [], 25 | "SubRegIndices": [], 26 | "SubRegs": [], 27 | "isArtificial": 0 28 | } 29 | } -------------------------------------------------------------------------------- /PluginInfo.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | HEX_INSTR_VAR_SYNTAX = "hi_u32" 6 | LINE_INDENT = "\t" 7 | REPO_URL = "https://github.com/rizinorg/rz-hexagon" 8 | GENERATION_WARNING_DELIMITER = "//" + "=" * 40 9 | GENERAL_ENUM_PREFIX = "HEX_" 10 | GENERAL_FCN_PREFIX = "hex_" 11 | INSTR_ENUM_PREFIX = GENERAL_ENUM_PREFIX + "INS_" 12 | REGISTER_ENUM_PREFIX = GENERAL_ENUM_PREFIX + "REG_" 13 | REGISTER_ALIAS_ENUM_PREFIX = REGISTER_ENUM_PREFIX + "ALIAS_" 14 | REGISTER_LOOKUP_TABLE_NAME_V69 = "hexagon_{}_lt_v69" 15 | ALIAS_REGISTER_LOOKUP_TABLE_v69 = "hex_alias_reg_lt_v69" 16 | 17 | FRAMEWORK_NAME = "rizin" 18 | MAX_OPERANDS = 6 19 | NUM_HEX_IL_INSN_MEMBERS = 3 20 | -------------------------------------------------------------------------------- /handwritten/hexagon_h/declarations.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | RZ_API RZ_BORROW RzConfig *hexagon_get_config(); 5 | RZ_API void hex_extend_op(HexState *state, RZ_INOUT HexOp *op, const bool set_new_extender, const ut32 addr); 6 | int resolve_n_register(const int reg_num, const ut32 addr, const HexPkt *p); 7 | int hexagon_disasm_instruction(HexState *state, const ut32 hi_u32, RZ_INOUT HexInsnContainer *hi, HexPkt *pkt); 8 | RZ_API const HexOp hex_alias_to_op(HexRegAlias alias, bool tmp_reg); 9 | RZ_API const char *hex_alias_to_reg_name(HexRegAlias alias, bool tmp_reg); 10 | RZ_API const HexOp hex_explicit_to_op(ut32 reg_num, HexRegClass reg_class, bool tmp_reg); 11 | -------------------------------------------------------------------------------- /import/README.md: -------------------------------------------------------------------------------- 1 | LLVM does not define all instructions and registers. That's why we have to import them from the manual. 2 | `import_instructions.py` parses a `.txt` version of the SYSTEM chapter, parses the encoding, asm string and name into an LLVM style and stores it as `.json` file. 3 | 4 | `gen_registers.py` does the same for a given list of registers. The list of system registers can be retrieved by compiling assembly instructions which use all system registers once. Afterwards it can be decompiled with the SDKs `objdump`. 5 | 6 | The `.json` files are than used by `LLVMImporter.py` to update the LLVM definitions. 7 | 8 | It is important to keep in mind, that the instruction and register templates only set those values to a correct value, which are currrently used by `LLVMImport.py`. -------------------------------------------------------------------------------- /import/registers/CtrRegs-C29.json: -------------------------------------------------------------------------------- 1 | { 2 | "C29": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C29", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [], 14 | "AsmName": "c29", 15 | "CostPerUse": [ 16 | 0 17 | ], 18 | "CoveredBySubRegs": 0, 19 | "DwarfNumbers": [ 20 | 96 21 | ], 22 | "HWEncoding": [ 23 | 1, 24 | 0, 25 | 1, 26 | 1, 27 | 1, 28 | 0, 29 | 0, 30 | 0, 31 | 0, 32 | 0, 33 | 0, 34 | 0, 35 | 0, 36 | 0 37 | ], 38 | "Namespace": "Hexagon", 39 | "RegAltNameIndices": [], 40 | "SubRegIndices": [], 41 | "SubRegs": [], 42 | "isArtificial": 0 43 | } 44 | } -------------------------------------------------------------------------------- /handwritten/hexagon_h/macros.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #define HEX_INSN_SIZE 4 5 | #define HEX_MAX_INSN_PER_PKT 4 6 | 7 | #define HEX_PC_ALIGNMENT 0x4 8 | 9 | #define HEX_PRED_WIDTH 8 10 | #define HEX_GPR_WIDTH 32 11 | #define HEX_GPR64_WIDTH 64 12 | #define HEX_CTR_WIDTH 32 13 | #define HEX_CTR64_WIDTH 64 14 | 15 | #define HEX_INVALID_INSN_0 0x00000000 16 | #define HEX_INVALID_INSN_F 0xffffffff 17 | 18 | #define MAX_CONST_EXT 512 19 | #define HEXAGON_STATE_PKTS 8 20 | #define ARRAY_LEN(a) (sizeof(a) / sizeof((a)[0])) 21 | 22 | #define ALIAS2OP(alias, is_new) hex_alias_to_op(alias, is_new) 23 | #define EXPLICIT2OP(num, class, is_new) hex_explicit_to_op(num, class, is_new) 24 | #define NREG2OP(bundle, isa_id) hex_nreg_to_op(bundle, isa_id) -------------------------------------------------------------------------------- /import/registers/CtrRegs-C21.json: -------------------------------------------------------------------------------- 1 | { 2 | "C21": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C21", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [ 14 | ], 15 | "AsmName": "c21", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 0, 20 | "DwarfNumbers": [ 21 | 88 22 | ], 23 | "HWEncoding": [ 24 | 1, 25 | 0, 26 | 1, 27 | 0, 28 | 1, 29 | 0, 30 | 0, 31 | 0, 32 | 0, 33 | 0, 34 | 0, 35 | 0, 36 | 0, 37 | 0 38 | ], 39 | "Namespace": "Hexagon", 40 | "RegAltNameIndices": [], 41 | "SubRegIndices": [], 42 | "SubRegs": [], 43 | "isArtificial": 0 44 | } 45 | } -------------------------------------------------------------------------------- /handwritten/hexagon_arch_h/typedefs.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | // The packet position indicators added to the instruction text. 5 | typedef enum { 6 | SINGLE_IN_PKT, 7 | FIRST_IN_PKT, 8 | MID_IN_PKT, 9 | LAST_IN_PKT, 10 | ELOOP_0_PKT, 11 | ELOOP_1_PKT, 12 | ELOOP_01_PKT, 13 | } HexPktSyntaxIndicator; 14 | 15 | // The type of opcode reversing which is be done on the opcode. 16 | typedef enum { 17 | HEXAGON_ANALYSIS, 18 | HEXAGON_DISAS, 19 | } HexReverseAction; 20 | 21 | /** 22 | * \brief Pointer to the rizin structs for disassembled and analysed instructions. 23 | * 24 | */ 25 | typedef struct { 26 | HexReverseAction action; // Whether ana_op, asm_op or both should be filled. 27 | RzAnalysisOp *ana_op; 28 | RzAsmOp *asm_op; 29 | } HexReversedOpcode; 30 | -------------------------------------------------------------------------------- /import/registers/CtrRegs-C20.json: -------------------------------------------------------------------------------- 1 | { 2 | "C20": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C20", 6 | "!superclasses": [ 7 | "Register", 8 | "HexagonReg", 9 | "Rc", 10 | "DwarfRegNum" 11 | ], 12 | "Aliases": [], 13 | "AltNames": [ 14 | "C20" 15 | ], 16 | "AsmName": "c20", 17 | "CostPerUse": [ 18 | 0 19 | ], 20 | "CoveredBySubRegs": 0, 21 | "DwarfNumbers": [ 22 | 87 23 | ], 24 | "HWEncoding": [ 25 | 0, 26 | 0, 27 | 1, 28 | 0, 29 | 1, 30 | 0, 31 | 0, 32 | 0, 33 | 0, 34 | 0, 35 | 0, 36 | 0, 37 | 0, 38 | 0 39 | ], 40 | "Namespace": "Hexagon", 41 | "RegAltNameIndices": [], 42 | "SubRegIndices": [], 43 | "SubRegs": [], 44 | "isArtificial": 0 45 | } 46 | } -------------------------------------------------------------------------------- /.clang-format: -------------------------------------------------------------------------------- 1 | Language: Cpp 2 | MaxEmptyLinesToKeep: 1 3 | SpaceBeforeParens: ControlStatements 4 | SpaceInEmptyParentheses: false 5 | SpacesInContainerLiterals: true 6 | BasedOnStyle: LLVM 7 | ContinuationIndentWidth: 8 8 | IndentCaseLabels: false 9 | IndentFunctionDeclarationAfterType: false 10 | IndentWidth: 8 11 | UseTab: ForContinuationAndIndentation 12 | ColumnLimit: 0 13 | BreakBeforeBraces: Attach 14 | BreakBeforeTernaryOperators: true 15 | AllowShortIfStatementsOnASingleLine: false 16 | AllowShortCaseLabelsOnASingleLine: true 17 | AllowShortFunctionsOnASingleLine: Inline 18 | AllowShortLoopsOnASingleLine: false 19 | AlignAfterOpenBracket: DontAlign 20 | AlignEscapedNewlines: DontAlign 21 | AlignConsecutiveMacros: true 22 | AlignTrailingComments: false 23 | AlignOperands: false 24 | Cpp11BracedListStyle: false 25 | ForEachMacros: ['rz_list_foreach', 'rz_list_foreach_safe', 'rz_pvector_foreach', 'rz_rbtree_foreach', 'rz_interval_tree_foreach', 'ls_foreach', 'rz_skiplist_foreach', 'graph_foreach_anode'] 26 | SortIncludes: false 27 | -------------------------------------------------------------------------------- /import/Register64-template.json: -------------------------------------------------------------------------------- 1 | { 2 | "S15_14": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "S15_14", 6 | "!superclasses": [ 7 | "Register", 8 | "RegisterWithSubRegs", 9 | "HexagonDoubleReg", 10 | "Sgg", 11 | "DwarfRegNum" 12 | ], 13 | "Aliases": [], 14 | "AltNames": [], 15 | "AsmName": "s15:14", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 1, 20 | "DwarfNumbers": [ 21 | 0 22 | ], 23 | "HWEncoding": [], 24 | "Namespace": "Hexagon", 25 | "RegAltNameIndices": [], 26 | "SubRegIndices": [ 27 | { 28 | "def": "isub_lo", 29 | "kind": "def", 30 | "printable": "isub_lo" 31 | }, 32 | { 33 | "def": "isub_hi", 34 | "kind": "def", 35 | "printable": "isub_hi" 36 | } 37 | ], 38 | "SubRegs": [ 39 | { 40 | "def": "S14", 41 | "kind": "def", 42 | "printable": "S14" 43 | }, 44 | { 45 | "def": "S15", 46 | "kind": "def", 47 | "printable": "S15" 48 | } 49 | ], 50 | "isArtificial": 0 51 | } 52 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs64-C21_20.json: -------------------------------------------------------------------------------- 1 | { 2 | "C21_20": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C21_20", 6 | "!superclasses": [ 7 | "Register", 8 | "RegisterWithSubRegs", 9 | "HexagonDoubleReg", 10 | "Rcc", 11 | "DwarfRegNum" 12 | ], 13 | "Aliases": [], 14 | "AltNames": [], 15 | "AsmName": "c21:20", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 1, 20 | "DwarfNumbers": [ 21 | 0 22 | ], 23 | "HWEncoding": [0,0,1,0,1,0,0,0,0,0,0,0,0,0], 24 | "Namespace": "Hexagon", 25 | "RegAltNameIndices": [], 26 | "SubRegIndices": [ 27 | { 28 | "def": "isub_lo", 29 | "kind": "def", 30 | "printable": "isub_lo" 31 | }, 32 | { 33 | "def": "isub_hi", 34 | "kind": "def", 35 | "printable": "isub_hi" 36 | } 37 | ], 38 | "SubRegs": [ 39 | { 40 | "def": "C20", 41 | "kind": "def", 42 | "printable": "C20" 43 | }, 44 | { 45 | "def": "C21", 46 | "kind": "def", 47 | "printable": "C21" 48 | } 49 | ], 50 | "isArtificial": 0 51 | } 52 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs64-C23_22.json: -------------------------------------------------------------------------------- 1 | { 2 | "C23_22": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C23_22", 6 | "!superclasses": [ 7 | "Register", 8 | "RegisterWithSubRegs", 9 | "HexagonDoubleReg", 10 | "Rcc", 11 | "DwarfRegNum" 12 | ], 13 | "Aliases": [], 14 | "AltNames": [], 15 | "AsmName": "c23:22", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 1, 20 | "DwarfNumbers": [ 21 | 0 22 | ], 23 | "HWEncoding": [0,1,1,0,1,0,0,0,0,0,0,0,0,0], 24 | "Namespace": "Hexagon", 25 | "RegAltNameIndices": [], 26 | "SubRegIndices": [ 27 | { 28 | "def": "isub_lo", 29 | "kind": "def", 30 | "printable": "isub_lo" 31 | }, 32 | { 33 | "def": "isub_hi", 34 | "kind": "def", 35 | "printable": "isub_hi" 36 | } 37 | ], 38 | "SubRegs": [ 39 | { 40 | "def": "C22", 41 | "kind": "def", 42 | "printable": "C22" 43 | }, 44 | { 45 | "def": "C23", 46 | "kind": "def", 47 | "printable": "C23" 48 | } 49 | ], 50 | "isArtificial": 0 51 | } 52 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs64-C25_24.json: -------------------------------------------------------------------------------- 1 | { 2 | "C25_24": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C25_24", 6 | "!superclasses": [ 7 | "Register", 8 | "RegisterWithSubRegs", 9 | "HexagonDoubleReg", 10 | "Rcc", 11 | "DwarfRegNum" 12 | ], 13 | "Aliases": [], 14 | "AltNames": [], 15 | "AsmName": "c25:24", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 1, 20 | "DwarfNumbers": [ 21 | 0 22 | ], 23 | "HWEncoding": [0,0,0,1,1,0,0,0,0,0,0,0,0,0], 24 | "Namespace": "Hexagon", 25 | "RegAltNameIndices": [], 26 | "SubRegIndices": [ 27 | { 28 | "def": "isub_lo", 29 | "kind": "def", 30 | "printable": "isub_lo" 31 | }, 32 | { 33 | "def": "isub_hi", 34 | "kind": "def", 35 | "printable": "isub_hi" 36 | } 37 | ], 38 | "SubRegs": [ 39 | { 40 | "def": "C24", 41 | "kind": "def", 42 | "printable": "C24" 43 | }, 44 | { 45 | "def": "C25", 46 | "kind": "def", 47 | "printable": "C25" 48 | } 49 | ], 50 | "isArtificial": 0 51 | } 52 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs64-C27_26.json: -------------------------------------------------------------------------------- 1 | { 2 | "C27_26": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C27_26", 6 | "!superclasses": [ 7 | "Register", 8 | "RegisterWithSubRegs", 9 | "HexagonDoubleReg", 10 | "Rcc", 11 | "DwarfRegNum" 12 | ], 13 | "Aliases": [], 14 | "AltNames": [], 15 | "AsmName": "c27:26", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 1, 20 | "DwarfNumbers": [ 21 | 0 22 | ], 23 | "HWEncoding": [0,1,0,1,1,0,0,0,0,0,0,0,0,0], 24 | "Namespace": "Hexagon", 25 | "RegAltNameIndices": [], 26 | "SubRegIndices": [ 27 | { 28 | "def": "isub_lo", 29 | "kind": "def", 30 | "printable": "isub_lo" 31 | }, 32 | { 33 | "def": "isub_hi", 34 | "kind": "def", 35 | "printable": "isub_hi" 36 | } 37 | ], 38 | "SubRegs": [ 39 | { 40 | "def": "C26", 41 | "kind": "def", 42 | "printable": "C26" 43 | }, 44 | { 45 | "def": "C27", 46 | "kind": "def", 47 | "printable": "C27" 48 | } 49 | ], 50 | "isArtificial": 0 51 | } 52 | } -------------------------------------------------------------------------------- /import/registers/CtrRegs64-C29_28.json: -------------------------------------------------------------------------------- 1 | { 2 | "C29_28": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "C29_28", 6 | "!superclasses": [ 7 | "Register", 8 | "RegisterWithSubRegs", 9 | "HexagonDoubleReg", 10 | "Rcc", 11 | "DwarfRegNum" 12 | ], 13 | "Aliases": [], 14 | "AltNames": [], 15 | "AsmName": "c29:28", 16 | "CostPerUse": [ 17 | 0 18 | ], 19 | "CoveredBySubRegs": 1, 20 | "DwarfNumbers": [ 21 | 0 22 | ], 23 | "HWEncoding": [0,0,1,1,1,0,0,0,0,0,0,0,0,0], 24 | "Namespace": "Hexagon", 25 | "RegAltNameIndices": [], 26 | "SubRegIndices": [ 27 | { 28 | "def": "isub_lo", 29 | "kind": "def", 30 | "printable": "isub_lo" 31 | }, 32 | { 33 | "def": "isub_hi", 34 | "kind": "def", 35 | "printable": "isub_hi" 36 | } 37 | ], 38 | "SubRegs": [ 39 | { 40 | "def": "C28", 41 | "kind": "def", 42 | "printable": "C28" 43 | }, 44 | { 45 | "def": "C29", 46 | "kind": "def", 47 | "printable": "C29" 48 | } 49 | ], 50 | "isArtificial": 0 51 | } 52 | } -------------------------------------------------------------------------------- /SubInstruction.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | from enum import StrEnum 6 | 7 | from ImplementationException import ImplementationException 8 | from Instruction import Instruction 9 | from UnexpectedException import UnexpectedException 10 | 11 | 12 | class SubInstrNamespace(StrEnum): 13 | A = "SUBINSN_A" 14 | L1 = "SUBINSN_L1" 15 | L2 = "SUBINSN_L2" 16 | S1 = "SUBINSN_S1" 17 | S2 = "SUBINSN_S2" 18 | 19 | 20 | class SubInstruction(Instruction): 21 | def __init__(self, llvm_instruction: dict): 22 | if llvm_instruction["Type"]["def"] != "TypeSUBINSN": 23 | raise UnexpectedException( 24 | "Can not initialize a sub instruction with a normal" 25 | " instruction object:" + "{}".format(llvm_instruction["!name"]) 26 | ) 27 | super(SubInstruction, self).__init__(llvm_instruction) 28 | 29 | namespace = llvm_instruction["DecoderNamespace"] 30 | try: 31 | self.namespace = SubInstrNamespace(namespace) 32 | except KeyError: 33 | raise ImplementationException("Sub instruction namespace: {} is not in Enum".format(namespace)) 34 | self.is_sub_instruction = True 35 | self.enc_number_representation = None 36 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_h/declarations.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | /// Immutable bits of CTR registers as in QEMU. 5 | static const ut64 hex_ctr_immut_masks[32] = { 6 | [HEX_REG_CTR_REGS_C8] = 0xc13000c0, // USR 7 | [HEX_REG_CTR_REGS_C9] = HEX_IMMUTABLE_REG, // PC 8 | [HEX_REG_CTR_REGS_C11] = 0x3f, // GP 9 | [HEX_REG_CTR_REGS_C14] = HEX_IMMUTABLE_REG, // UPCYCLELO 10 | [HEX_REG_CTR_REGS_C15] = HEX_IMMUTABLE_REG, // UPCYCLEHI 11 | [HEX_REG_CTR_REGS_C30] = HEX_IMMUTABLE_REG, // UTIMERLO 12 | [HEX_REG_CTR_REGS_C31] = HEX_IMMUTABLE_REG, // UTIMERHI 13 | }; 14 | 15 | RZ_IPI bool hex_shuffle_insns(RZ_INOUT HexPkt *p); 16 | RZ_IPI RzILOpEffect *hex_get_il_op(const ut32 addr, const bool get_pkt_op); 17 | RZ_IPI RZ_OWN RzILOpPure *hex_get_rf_property_val(const HexRegFieldProperty property, const HexRegField field); 18 | RZ_IPI RZ_OWN RzILOpEffect *hex_get_npc(const HexPkt *pkt); 19 | RZ_IPI RZ_OWN RzILOpEffect *hex_il_op_jump_flag_init(HexInsnPktBundle *bundle); 20 | RZ_IPI RZ_OWN RzILOpEffect *hex_il_op_next_pkt_jmp(HexInsnPktBundle *bundle); 21 | RZ_IPI RZ_OWN RzILOpEffect *hex_commit_packet(HexInsnPktBundle *bundle); 22 | RZ_IPI RZ_OWN RzILOpEffect *hex_write_reg(RZ_BORROW HexInsnPktBundle *bundle, const HexOp *op, RzILOpPure *val); 23 | RZ_IPI RZ_OWN RzILOpPure *hex_read_reg(RZ_BORROW HexPkt *pkt, const HexOp *op, bool tmp_reg); 24 | RZ_IPI RZ_OWN RzILOpEffect *hex_cancel_slot(RZ_BORROW HexPkt *pkt, ut8 slot); 25 | RZ_IPI void hex_reset_il_pkt_stats(HexILExecData *stats); 26 | RzILOpPure *hex_get_corresponding_cs(RZ_BORROW HexPkt *pkt, const HexOp *Mu); 27 | -------------------------------------------------------------------------------- /.reuse/dep5: -------------------------------------------------------------------------------- 1 | Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/ 2 | Upstream-Name: Rizin 3 | Upstream-Contact: RizinOrg 4 | Source: https://github.com/rizinorg/rizin 5 | 6 | Files: paths.json 7 | Copyright: 2024 Rot127 8 | License: LGPL-3.0-only 9 | 10 | Files: .github/** 11 | Copyright: 2021 RizinOrg 12 | License: LGPL-3.0-only 13 | 14 | Files: .clang-format 15 | Copyright: 2021 RizinOrg 16 | License: LGPL-3.0-only 17 | 18 | Files: .gitattributes 19 | Copyright: 2021 RizinOrg 20 | License: LGPL-3.0-only 21 | 22 | Files: .gitignore 23 | Copyright: 2021 RizinOrg 24 | License: LGPL-3.0-only 25 | 26 | Files: .gitmodules 27 | Copyright: 2022 Rot127 28 | License: LGPL-3.0-only 29 | 30 | Files: .pylintrc 31 | Copyright: 2021 RizinOrg 32 | License: LGPL-3.0-only 33 | 34 | Files: *.yml 35 | Copyright: 2021 RizinOrg 36 | License: LGPL-3.0-only 37 | 38 | Files: *.md 39 | Copyright: 2021 RizinOrg 40 | License: LGPL-3.0-only 41 | 42 | Files: requirements.txt 43 | Copyright: 2021 Rot127 44 | License: CC0-1.0 45 | 46 | Files: optional_requirements.txt 47 | Copyright: 2021 Rot127 48 | License: CC0-1.0 49 | 50 | Files: handwritten/*-tests/* 51 | Copyright: 2021 Rot127 52 | License: LGPL-3.0-only 53 | 54 | Files: test-bins/* 55 | Copyright: 2021 Rot127 56 | License: LGPL-3.0-only 57 | 58 | Files: import/* 59 | Copyright: 2022 Rot127 60 | License: LGPL-3.0-only 61 | 62 | Files: handwritten/*.json 63 | Copyright: 2023 Rot127 64 | License: LGPL-3.0-only 65 | -------------------------------------------------------------------------------- /handwritten/analysis_hexagon_c/functions.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | RZ_API int hexagon_v6_op(RzAnalysis *analysis, RzAnalysisOp *op, ut64 addr, const ut8 *buf, int len, RzAnalysisOpMask mask) { 5 | rz_return_val_if_fail(analysis && op && buf, -1); 6 | if (len < HEX_INSN_SIZE) { 7 | return -1; 8 | } 9 | if (analysis->pcalign == 0) { 10 | analysis->pcalign = HEX_PC_ALIGNMENT; 11 | } 12 | 13 | // Disassemble as many instructions as possible from the buffer. 14 | ut32 buf_offset = 0; 15 | while (buf_offset + HEX_INSN_SIZE <= len && buf_offset <= HEX_INSN_SIZE * HEX_MAX_INSN_PER_PKT) { 16 | const ut32 buf_ptr = rz_read_at_le32(buf, buf_offset); 17 | if (buf_offset > 0 && (buf_ptr == HEX_INVALID_INSN_0 || buf_ptr == HEX_INVALID_INSN_F)) { 18 | // Do not disassemble invalid instructions, if we already have a valid one. 19 | break; 20 | } 21 | 22 | HexReversedOpcode rev = { .action = HEXAGON_ANALYSIS, .ana_op = op, .asm_op = NULL }; 23 | hexagon_reverse_opcode(NULL, &rev, buf + buf_offset, addr + buf_offset, false); 24 | buf_offset += HEX_INSN_SIZE; 25 | } 26 | // Copy operation actually requested. 27 | HexReversedOpcode rev = { .action = HEXAGON_ANALYSIS, .ana_op = op, .asm_op = NULL }; 28 | hexagon_reverse_opcode(NULL, &rev, buf, addr, true); 29 | bool decoded_packet = len > HEX_INSN_SIZE; 30 | if (mask & RZ_ANALYSIS_OP_MASK_IL) { 31 | op->il_op = hex_get_il_op(addr, decoded_packet); 32 | } 33 | 34 | return HEX_INSN_SIZE; 35 | } 36 | 37 | static RzAnalysisILConfig *rz_hexagon_il_config(RzAnalysis *a) { 38 | HexState *state = hexagon_state(false); 39 | state->just_init = true; 40 | return rz_analysis_il_config_new(32, a->big_endian, 32); 41 | } 42 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_h/macros.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #define WRITE_REG(pkt, op, val) hex_write_reg(pkt, op, val) 5 | #define READ_REG(pkt, op, tmp_reg) hex_read_reg(pkt, op, tmp_reg) 6 | #define ISA2REG(hi, var, tmp_reg) hex_isa_to_reg(hi, var, tmp_reg) 7 | #define ISA2IMM(hi, var) hex_isa_to_imm(hi, var) 8 | #define HEX_REGFIELD(prop, reg) hex_get_rf_property_val(prop, reg) 9 | #define HEX_EXTRACT64(val, start, len) hex_extract64(val, start, len) 10 | #define HEX_SEXTRACT64(val, start, len) hex_sextract64(val, start, len) 11 | #define HEX_DEPOSIT64(val, start, len, fieldval) hex_deposit64(val, start, len, fieldval) 12 | #define HEX_GET_NPC(pkt) hex_get_npc(pkt) 13 | #define HEX_WRITE_GLOBAL(name, val) hex_write_global(name, val) 14 | #define INC(val, size) ADD(val, UN(size, 1)) 15 | #define DEC(val, size) SUB(val, UN(size, 1)) 16 | #define HEX_STORE_SLOT_CANCELLED(pkt, slot) hex_cancel_slot(pkt, slot) 17 | #define HEX_FCIRC_ADD(bundle, RxV, offset, mu, CS) hex_fcircadd(bundle, RxV, offset, mu, CS) 18 | #define HEX_GET_CORRESPONDING_CS(pkt, Mu) hex_get_corresponding_cs(pkt, Mu) 19 | #define HEX_GET_INSN_RMODE(insn) (insn->fround_mode) 20 | #define HEX_D_TO_SINT(mode, fval) F2SINT(64, mode, fval) 21 | #define HEX_F_TO_SINT(mode, fval) F2SINT(32, mode, fval) 22 | #define HEX_D_TO_INT(mode, fval) F2INT(64, mode, fval) 23 | #define HEX_F_TO_INT(mode, fval) F2INT(32, mode, fval) 24 | #define HEX_SINT_TO_D(mode, fval) SINT2F(64, mode, fval) 25 | #define HEX_SINT_TO_F(mode, fval) SINT2F(32, mode, fval) 26 | #define HEX_INT_TO_D(mode, fval) INT2F(64, mode, fval) 27 | #define HEX_INT_TO_F(mode, fval) INT2F(32, mode, fval) 28 | 29 | #define HEX_IMMUTABLE_REG (~0) 30 | #define HEX_NOT_MASKED 0 31 | -------------------------------------------------------------------------------- /Tests/testRegister.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import unittest 6 | 7 | from Instruction import Instruction 8 | from LLVMImporter import LLVMImporter 9 | 10 | 11 | class TestRegister(unittest.TestCase): 12 | def setUp(self) -> None: 13 | self.interface = LLVMImporter(False, test_mode=True, gen_rzil=False, skip_pcpp=True, rzil_compile=False) 14 | self.json = self.interface.hexArch 15 | 16 | def test_parse_reg_type(self): 17 | # Syntax (llvm): "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new" 18 | instr = Instruction(self.json["V6_vS32b_nt_new_pred_ppu"]) 19 | operand = instr.operands["Os8"] 20 | self.assertEqual(0, instr.operands["Pv4"].syntax_index) 21 | self.assertEqual(1, instr.operands["Rx32"].syntax_index) # Rx32 is also an out operand because of the ++ 22 | # self.assertEqual(2, instr.operands["Rx32in"].index) 23 | self.assertEqual(2, instr.operands["Mu2"].syntax_index) 24 | self.assertEqual(3, instr.operands["Os8"].syntax_index) 25 | self.assertEqual(3, instr.new_operand_index) 26 | self.assertTrue(operand.is_new_value) 27 | 28 | # Syntax (llvm): "if ($Pv4.new) memw($Rs32+$Ru32<<#$Ii) = $Nt8.new" 29 | instr = Instruction(self.json["S4_pstorerinewtnew_rr"]) 30 | operand = instr.operands["Pv4"] 31 | self.assertTrue(operand.is_new_value) 32 | self.assertTrue(operand.is_predicate) 33 | 34 | operand = instr.operands["Nt8"] 35 | self.assertTrue(operand.is_new_value) 36 | 37 | self.assertEqual(0, instr.operands["Pv4"].syntax_index) 38 | self.assertEqual(1, instr.operands["Rs32"].syntax_index) 39 | self.assertEqual(2, instr.operands["Ru32"].syntax_index) 40 | self.assertEqual(3, instr.operands["Ii"].syntax_index) 41 | self.assertEqual(4, instr.operands["Nt8"].syntax_index) 42 | -------------------------------------------------------------------------------- /Tests/testHelperFunction.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import unittest 6 | 7 | from bitarray import bitarray 8 | 9 | from helperFunctions import bitarray_to_uint, list_to_bitarray, list_to_int 10 | 11 | 12 | class TestHelperFunction(unittest.TestCase): 13 | def test_list_to_bitarray(self): 14 | array = list_to_bitarray([0, 0, 1], endian="little") 15 | self.assertEqual(bitarray("001", endian="little"), array) 16 | 17 | array = list_to_bitarray([0, 0, 1], endian="big") 18 | self.assertEqual(bitarray("001", endian="big"), array) 19 | 20 | array = list_to_bitarray([1, 0, 0], endian="little") 21 | self.assertEqual(bitarray("100", endian="little"), array) 22 | 23 | array = list_to_bitarray([1, 0, 0], endian="big") 24 | self.assertEqual(bitarray("100", endian="big"), array) 25 | 26 | def test_bitarray_to_int(self): 27 | n = bitarray_to_uint(bitarray("001"), endian="little") 28 | self.assertEqual(4, n) 29 | 30 | n = bitarray_to_uint(bitarray("001"), endian="big") 31 | self.assertEqual(1, n) 32 | 33 | n = bitarray_to_uint(bitarray("010"), endian="little") 34 | self.assertEqual(2, n) 35 | 36 | n = bitarray_to_uint(bitarray("010"), endian="big") 37 | self.assertEqual(2, n) 38 | 39 | n = bitarray_to_uint(bitarray("011"), endian="little") 40 | self.assertEqual(6, n) 41 | 42 | n = bitarray_to_uint(bitarray("011"), endian="big") 43 | self.assertEqual(3, n) 44 | 45 | def test_list_to_int(self): 46 | n = list_to_int([0, 0, 1], endian="little") 47 | self.assertEqual(4, n) 48 | 49 | n = list_to_int([0, 0, 1], endian="big") 50 | self.assertEqual(1, n) 51 | 52 | n = list_to_int([0, 1, 0], endian="little") 53 | self.assertEqual(2, n) 54 | 55 | n = list_to_int([0, 1, 0], endian="big") 56 | self.assertEqual(2, n) 57 | 58 | n = list_to_int([0, 1, 1], endian="little") 59 | self.assertEqual(6, n) 60 | 61 | n = list_to_int([0, 1, 1], endian="big") 62 | self.assertEqual(3, n) 63 | -------------------------------------------------------------------------------- /handwritten/hexagon_arch_h/declarations.h: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #define HEX_PKT_UNK "? " 5 | #define HEX_PKT_SINGLE "[ " 6 | #define HEX_PKT_SINGLE_UTF8 "[ " 7 | #define HEX_PKT_FIRST_UTF8 "┌ " 8 | #define HEX_PKT_MID_UTF8 "│ " 9 | #define HEX_PKT_LAST_UTF8 "└ " 10 | #define HEX_PKT_FIRST_SDK "{ " 11 | #define HEX_PKT_SDK_PADDING " " 12 | #define HEX_PKT_LAST_SDK " }" 13 | #define HEX_PKT_FIRST "/ " 14 | #define HEX_PKT_MID "| " 15 | #define HEX_PKT_LAST "\\ " 16 | #define HEX_PKT_ELOOP_01_UTF8 " ∎ endloop01" 17 | #define HEX_PKT_ELOOP_1_UTF8 " ∎ endloop1" 18 | #define HEX_PKT_ELOOP_0_UTF8 " ∎ endloop0" 19 | #define HEX_PKT_ELOOP_01 " < endloop01" 20 | #define HEX_PKT_ELOOP_1 " < endloop1" 21 | #define HEX_PKT_ELOOP_0 " < endloop0" 22 | #define HEX_PKT_ELOOP_01_SDK ":endloop01" 23 | #define HEX_PKT_ELOOP_1_SDK ":endloop1" 24 | #define HEX_PKT_ELOOP_0_SDK ":endloop0" 25 | 26 | RZ_API HexInsn *hexagon_alloc_instr(); 27 | RZ_API void hex_insn_free(RZ_NULLABLE HexInsn *i); 28 | RZ_API HexInsnContainer *hexagon_alloc_instr_container(); 29 | RZ_API void hex_insn_container_free(RZ_NULLABLE HexInsnContainer *c); 30 | RZ_API void hex_const_ext_free(RZ_NULLABLE HexConstExt *ce); 31 | RZ_API HexState *hexagon_state(bool reset); 32 | RZ_IPI void hexagon_state_fini(HexState *state); 33 | RZ_API void hexagon_reverse_opcode(const RzAsm *rz_asm, HexReversedOpcode *rz_reverse, const ut8 *buf, const ut64 addr, const bool copy_result); 34 | RZ_API ut8 hexagon_get_pkt_index_of_addr(const ut32 addr, const HexPkt *p); 35 | RZ_API HexLoopAttr hex_get_loop_flag(const HexPkt *p); 36 | RZ_API const HexOp *hex_isa_to_reg(const HexInsn *hi, const char isa_id, bool new_reg); 37 | RZ_API ut64 hex_isa_to_imm(const HexInsn *hi, const char isa_id); 38 | void hex_set_hic_text(RZ_INOUT HexInsnContainer *hic); 39 | RZ_API void hex_move_insn_container(RZ_OUT HexInsnContainer *dest, const HexInsnContainer *src); 40 | RZ_API HexPkt *hex_get_pkt(RZ_BORROW HexState *state, const ut32 addr); 41 | RZ_API HexInsnContainer *hex_get_hic_at_addr(HexState *state, const ut32 addr); 42 | RZ_API const HexOp hex_nreg_to_op(const HexInsnPktBundle *bundle, const char isa_id); 43 | -------------------------------------------------------------------------------- /handwritten/hexagon_disas_c/types.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Florian Märkl 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | #define HEX_OP_MASKS_MAX 4 5 | 6 | typedef enum { 7 | HEX_OP_TEMPLATE_TYPE_NONE = 0, 8 | HEX_OP_TEMPLATE_TYPE_IMM = 1, 9 | HEX_OP_TEMPLATE_TYPE_IMM_CONST = 2, 10 | HEX_OP_TEMPLATE_TYPE_REG = 3, 11 | HEX_OP_TEMPLATE_TYPE_MASK = 3 12 | } HexOpTemplateType; 13 | 14 | typedef enum { 15 | // 1 << 0 and 1 << 1 reserved by HexOpTemplateType 16 | // for HEX_OP_TEMPLATE_TYPE_REG: 17 | HEX_OP_TEMPLATE_FLAG_REG_OUT = 1 << 2, 18 | HEX_OP_TEMPLATE_FLAG_REG_PAIR = 1 << 3, 19 | HEX_OP_TEMPLATE_FLAG_REG_QUADRUPLE = 1 << 4, 20 | HEX_OP_TEMPLATE_FLAG_REG_N_REG = 1 << 5, 21 | // for HEX_OP_TEMPLATE_TYPE_IMM: 22 | HEX_OP_TEMPLATE_FLAG_IMM_SIGNED = 1 << 2, 23 | HEX_OP_TEMPLATE_FLAG_IMM_EXTENDABLE = 1 << 3, 24 | HEX_OP_TEMPLATE_FLAG_IMM_PC_RELATIVE = 1 << 4, 25 | HEX_OP_TEMPLATE_FLAG_IMM_DOUBLE_HASH = 1 << 5 26 | } HexOpTemplateFlag; 27 | 28 | // Note: 29 | // The structs below are using ut8 instead of direct enum types 30 | // where possible to optimize for size. Members are also ordered 31 | // deliberately to make them well packed. 32 | // Keep this in mind when changing anything here! 33 | 34 | typedef struct { 35 | ut8 bits; // number of bits this part has 36 | ut8 shift; // index of the first bit in the instruction where this part starts 37 | } HexOpMask; 38 | 39 | typedef struct { 40 | ut8 info; // HexOpTemplateType | HexOpTemplateFlag 41 | ut8 syntax; // offset into HexInsnTemplate.syntax where to insert this op 42 | char isa_id; 43 | HexOpMask masks[HEX_OP_MASKS_MAX]; 44 | union { 45 | ut8 imm_scale; 46 | ut8 reg_cls; // HexRegClass 47 | }; 48 | } HexOpTemplate; 49 | 50 | typedef enum { 51 | HEX_INSN_TEMPLATE_FLAG_CALL = 1 << 0, 52 | HEX_INSN_TEMPLATE_FLAG_PREDICATED = 1 << 1, 53 | HEX_INSN_TEMPLATE_FLAG_HAS_JMP_TGT = 1 << 2, 54 | HEX_INSN_TEMPLATE_FLAG_LOOP_BEGIN = 1 << 3, 55 | HEX_INSN_TEMPLATE_FLAG_LOOP_0 = 1 << 4, 56 | HEX_INSN_TEMPLATE_FLAG_LOOP_1 = 1 << 5 57 | } HexInsnTemplateFlag; 58 | 59 | typedef struct { 60 | struct { 61 | ut32 mask; 62 | ut32 op; 63 | } encoding; 64 | HexInsnID id; 65 | HexOpTemplate ops[HEX_MAX_OPERANDS]; 66 | ut8 pred; // HexPred 67 | ut8 cond; // RzTypeCond 68 | ut8 flags; // HexInsnTemplateFlag 69 | const char *syntax; 70 | _RzAnalysisOpType type; 71 | } HexInsnTemplate; 72 | -------------------------------------------------------------------------------- /Tests/testImmediate.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import unittest 6 | 7 | from Immediate import Immediate 8 | from Instruction import Instruction 9 | from LLVMImporter import LLVMImporter 10 | from helperFunctions import log, LogLevel 11 | 12 | 13 | class TestImmediate(unittest.TestCase): 14 | def setUp(self) -> None: 15 | self.interface = LLVMImporter(False, test_mode=True, gen_rzil=False, skip_pcpp=True, rzil_compile=False) 16 | self.json = self.interface.hexArch 17 | 18 | def test_immediate_initialization(self): 19 | # Syntax (llvm): $Rd32 = mux($Pu4,#$Ii,#$II) 20 | instr = Instruction(self.json["C2_muxii"]) 21 | imm = instr.operands["Ii"] 22 | self.assertTrue(imm.is_signed) 23 | self.assertTrue(imm.is_extendable) 24 | self.assertEqual(2, imm.syntax_index) 25 | self.assertEqual(32, imm.total_width) 26 | self.assertEqual(0, imm.scale) 27 | self.assertEqual(32, imm.encoding_width) 28 | self.assertEqual("s32_0Imm", imm.llvm_type) 29 | self.assertEqual("Ii", imm.llvm_syntax) 30 | 31 | imm = instr.operands["II"] 32 | self.assertTrue(imm.is_signed) 33 | self.assertFalse(imm.is_extendable) 34 | self.assertEqual(3, imm.syntax_index) 35 | self.assertEqual(8, imm.total_width) 36 | self.assertEqual(0, imm.scale) 37 | self.assertEqual(8, imm.encoding_width) 38 | self.assertEqual("s8_0Imm", imm.llvm_type) 39 | self.assertEqual("II", imm.llvm_syntax) 40 | 41 | # J2_jump 42 | instr = Instruction(self.json["J2_jump"]) 43 | imm = instr.operands["Ii"] 44 | self.assertTrue(imm.is_signed) 45 | self.assertTrue(imm.is_extendable) 46 | self.assertTrue(imm.is_pc_relative) 47 | self.assertEqual(0, imm.syntax_index) 48 | self.assertEqual(32, imm.total_width) 49 | self.assertEqual(2, imm.scale) 50 | self.assertEqual(30, imm.encoding_width) 51 | self.assertEqual("b30_2Imm", imm.llvm_type) 52 | self.assertEqual("Ii", imm.llvm_syntax) 53 | 54 | def test_extendable_imm_coverage(self): 55 | for llvm_instr_name in [ 56 | name 57 | for name, i in self.interface.llvm_instructions.items() 58 | if i["isExtendable"][0] and "OpcodeDuplex" not in i["!superclasses"] 59 | ]: 60 | c = 0 61 | instructions = self.interface.normal_instructions 62 | instructions.update(self.interface.sub_instructions) 63 | for op_name, op in instructions[llvm_instr_name].operands.items(): 64 | if isinstance(op, Immediate) and op.is_extendable: 65 | c += 1 66 | if c != 1: 67 | log( 68 | "Extendable immediate not set in instruction: {}".format(llvm_instr_name), 69 | LogLevel.ERROR, 70 | ) 71 | self.assertEqual(1, c) 72 | -------------------------------------------------------------------------------- /Conf.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2022 Rot127 2 | # SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | import subprocess 5 | 6 | from enum import StrEnum 7 | from pathlib import Path 8 | 9 | from helperFunctions import log 10 | 11 | 12 | class OutputFile(StrEnum): 13 | """ 14 | Enum of paths used by the components. 15 | 16 | is replaced with the path to the repositories root. 17 | is replaced with the architecture name. 18 | """ 19 | 20 | OUT_BASE = "/rizin/" 21 | LIBRZ_DIR = "/rizin/librz/" 22 | IL_OPS_DIR = "/rizin/librz/arch/isa/hexagon/il_ops/" 23 | 24 | ANA_TESTS = "/rizin/test/db/analysis/hexagon" 25 | ASM_TESTS = "/rizin/test/db/asm/hexagon" 26 | RZIL_TESTS = "/rizin/test/db/rzil/hexagon" 27 | ANALYSIS_HEXAGON_C = "/rizin/librz/arch/p/analysis/analysis_hexagon.c" 28 | ASM_HEXAGON_C = "/rizin/librz/arch/p/asm/asm_hexagon.c" 29 | CC_HEXAGON_32_SDB_TXT = "/rizin/librz/arch/types/cc-hexagon-32.sdb.txt" 30 | HEXAGON_IL_C = "/rizin/librz/arch/isa/hexagon/hexagon_il.c" 31 | HEXAGON_IL_GETTER_TABLE_H = "/rizin/librz/arch/isa/hexagon/hexagon_il_getter_table.h" 32 | HEXAGON_IL_H = "/rizin/librz/arch/isa/hexagon/hexagon_il.h" 33 | HEXAGON_ARCH_C = "/rizin/librz/arch/isa/hexagon/hexagon_arch.c" 34 | HEXAGON_ARCH_H = "/rizin/librz/arch/isa/hexagon/hexagon_arch.h" 35 | HEXAGON_C = "/rizin/librz/arch/isa/hexagon/hexagon.c" 36 | HEXAGON_DISAS_C = "/rizin/librz/arch/isa/hexagon/hexagon_disas.c" 37 | HEXAGON_H = "/rizin/librz/arch/isa/hexagon/hexagon.h" 38 | HEXAGON_INSN_H = "/rizin/librz/arch/isa/hexagon/hexagon_insn.h" 39 | HEXAGON_REG_TABLES_H = "/rizin/librz/arch/isa/hexagon/hexagon_reg_tables.h" 40 | HEXAGON_DWARF_REG_TABLE_H = "/rizin/librz/arch/isa/hexagon/hexagon_dwarf_reg_num_table.inc" 41 | 42 | 43 | class Conf: 44 | """ 45 | Holds all the configurable values like paths. 46 | """ 47 | 48 | @staticmethod 49 | def replace_placeholders(path_str: str) -> str: 50 | if "" in path_str: 51 | root = subprocess.run( 52 | ["git", "rev-parse", "--show-toplevel"], 53 | check=True, 54 | stdout=subprocess.PIPE, 55 | ) 56 | root_dir = Path(root.stdout.decode("utf8").strip("\n")) 57 | if not root_dir.exists(): 58 | raise NotADirectoryError(str(root_dir)) 59 | 60 | path_str = path_str.replace("", str(root_dir)) 61 | return path_str 62 | 63 | @staticmethod 64 | def get_path(file: OutputFile) -> Path: 65 | return Path(Conf.replace_placeholders(file)) 66 | 67 | @staticmethod 68 | def check_path(path: Path, is_file: bool = True) -> None: 69 | """Checks a given path and creates the directory if it doesn't exist.""" 70 | if not path.exists(): 71 | target = path 72 | if is_file: 73 | target = path.parent 74 | log(f"Create dir {str(target)}") 75 | target.mkdir(parents=True, exist_ok=True) 76 | -------------------------------------------------------------------------------- /handwritten/hexagon_il_X_ops_c/non_insn_ops.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2022 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | /** 5 | * \brief Returns the value of an register field property. 6 | * 7 | * \param property The property to get the value for. 8 | * \param field The register field. 9 | * \return RzILOpPure The value as integer as U32 or U32_MAX on failure. 10 | */ 11 | RZ_IPI RZ_OWN RzILOpPure *hex_get_rf_property_val(const HexRegFieldProperty property, const HexRegField field) { 12 | RzILOpPure *r = NULL; 13 | switch (field) { 14 | default: 15 | RZ_LOG_WARN("Register field not implemented.\n"); 16 | break; 17 | case HEX_REG_FIELD_USR_LPCFG: 18 | if (property == HEX_RF_WIDTH) { 19 | r = U32(2); 20 | } else if (property == HEX_RF_OFFSET) { 21 | r = U32(8); 22 | } 23 | break; 24 | case HEX_REG_FIELD_USR_OVF: 25 | if (property == HEX_RF_WIDTH) { 26 | r = U32(1); 27 | } else if (property == HEX_RF_OFFSET) { 28 | r = U32(0); 29 | } 30 | break; 31 | } 32 | return r; 33 | } 34 | 35 | /** 36 | * \brief Returns the next PC as pure. 37 | * 38 | * \param pkt The instruction packet. 39 | * \return RzILOpPure* The next PC as pure. 40 | */ 41 | RZ_IPI RZ_OWN RzILOpEffect *hex_get_npc(const HexPkt *pkt) { 42 | rz_return_val_if_fail(pkt, NULL); 43 | RzILOpPure *r; 44 | r = U64(pkt->pkt_addr + (rz_list_length(pkt->bin) * HEX_INSN_SIZE)); 45 | return SETL("ret_val", r); 46 | } 47 | 48 | RZ_IPI RZ_OWN RzILOpEffect *hex_commit_packet(HexInsnPktBundle *bundle) { 49 | HexILExecData *stats = &bundle->pkt->il_op_stats; 50 | RzILOpEffect *commit_seq = EMPTY(); 51 | for (ut8 i = 0; i <= HEX_REG_CTR_REGS_C31; ++i) { 52 | if (!(rz_bv_get(stats->ctr_written, i))) { 53 | continue; 54 | } 55 | const char *dest_reg = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, i, false, false, false); 56 | const char *src_reg = hex_get_reg_in_class(HEX_REG_CLASS_CTR_REGS, i, false, true, false); 57 | commit_seq = SEQ2(commit_seq, SETG(dest_reg, VARG(src_reg))); 58 | } 59 | 60 | for (ut8 i = 0; i <= HEX_REG_INT_REGS_R31; ++i) { 61 | if (!(rz_bv_get(stats->gpr_written, i))) { 62 | continue; 63 | } 64 | const char *dest_reg = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, i, false, false, false); 65 | const char *src_reg = hex_get_reg_in_class(HEX_REG_CLASS_INT_REGS, i, false, true, false); 66 | commit_seq = SEQ2(commit_seq, SETG(dest_reg, VARG(src_reg))); 67 | } 68 | 69 | for (ut8 i = 0; i <= HEX_REG_PRED_REGS_P3; ++i) { 70 | if (!(rz_bv_get(stats->pred_written, i))) { 71 | continue; 72 | } 73 | const char *dest_reg = hex_get_reg_in_class(HEX_REG_CLASS_PRED_REGS, i, false, false, false); 74 | const char *src_reg = hex_get_reg_in_class(HEX_REG_CLASS_PRED_REGS, i, false, true, false); 75 | commit_seq = SEQ2(commit_seq, SETG(dest_reg, VARG(src_reg))); 76 | } 77 | 78 | hex_reset_il_pkt_stats(stats); 79 | return commit_seq; 80 | } 81 | 82 | RZ_IPI RZ_OWN RzILOpEffect *hex_il_op_jump_flag_init(HexInsnPktBundle *bundle) { 83 | return SETL("jump_flag", IL_FALSE); 84 | } 85 | 86 | RZ_IPI RZ_OWN RzILOpEffect *hex_il_op_next_pkt_jmp(HexInsnPktBundle *bundle) { 87 | return BRANCH(VARL("jump_flag"), JMP(VARL("jump_target")), JMP(U32(bundle->pkt->pkt_addr + (HEX_INSN_SIZE * rz_list_length(bundle->pkt->bin))))); 88 | } 89 | -------------------------------------------------------------------------------- /handwritten/hexagon_c/functions.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | /** 5 | * \brief Resolves the 3 bit value of an Nt.new reg to the general register of the producer. 6 | * 7 | * \param addr The address of the current instruction. 8 | * \param reg_num Bits of Nt.new reg. 9 | * \param p The current packet. 10 | * \return int The number of the general register. Or UT32_MAX if any error occurred. 11 | */ 12 | int resolve_n_register(const int reg_num, const ut32 addr, const HexPkt *p) { 13 | // .new values are documented in Programmers Reference Manual 14 | if (reg_num <= 1 || reg_num >= 8) { 15 | return UT32_MAX; 16 | } 17 | 18 | ut8 ahead = (reg_num >> 1); 19 | ut8 i = hexagon_get_pkt_index_of_addr(addr, p); 20 | if (i == UT8_MAX) { 21 | return UT32_MAX; 22 | } 23 | 24 | ut8 prod_i = i; // Producer index 25 | HexInsnContainer *hic; 26 | RzListIter *it; 27 | rz_list_foreach_prev(p->bin, it, hic) { 28 | if (ahead == 0) { 29 | break; 30 | } 31 | if (hic->addr < addr) { 32 | if (hic->identifier == HEX_INS_A4_EXT) { 33 | --prod_i; 34 | continue; 35 | } 36 | --ahead; 37 | --prod_i; 38 | } 39 | } 40 | 41 | hic = rz_list_get_n(p->bin, prod_i); 42 | 43 | if (!hic || !hic->bin.insn || (hic->is_duplex && (!hic->bin.sub[0] || !hic->bin.sub[1]))) { 44 | // This case happens if the current instruction (with the .new register) 45 | // is yet the only one in the packet. 46 | return UT32_MAX; 47 | } 48 | if (hic->identifier == HEX_INS_A4_EXT) { 49 | return UT32_MAX; 50 | } 51 | HexInsn *hi = !hic->is_duplex ? hic->bin.insn : (hic->bin.sub[0]->addr == addr ? hic->bin.sub[0] : hic->bin.sub[1]); 52 | for (ut8 k = 0; k < hi->op_count; ++k) { 53 | if (hi->ops[k].attr & HEX_OP_REG_OUT) { 54 | return hi->ops[k].op.reg; 55 | } 56 | } 57 | return UT32_MAX; 58 | } 59 | 60 | /** 61 | * \brief Returns a HexOp of the given register number and class. 62 | * 63 | * \param reg_num The register number as in the name. 64 | * \param reg_class The HexRegClass this register belongs to. 65 | * \param tmp_reg Flag if the register is a .new register. 66 | * 67 | * \return A setup HexOp. Currently the HexOp.attr field is *not* set! 68 | */ 69 | RZ_API const HexOp hex_explicit_to_op(ut32 reg_num, HexRegClass reg_class, bool tmp_reg) { 70 | HexOp op = { 0 }; 71 | op.type = HEX_OP_TYPE_REG; 72 | op.class = reg_class; 73 | op.op.reg = reg_num; 74 | // TODO: Add attributes? 75 | return op; 76 | } 77 | 78 | /** 79 | * \brief Returns a HexOp of the given register alias. 80 | * 81 | * \param alias The alias to get the HexOp for. 82 | * \param tmp_reg Flag if the alias is referring to the .new register. 83 | * 84 | * \return A setup HexOp. Currently the HexOp.attr field is *not* set! 85 | */ 86 | RZ_API const HexOp hex_alias_to_op(HexRegAlias alias, bool tmp_reg) { 87 | HexOp op = { 0 }; 88 | if (alias >= ARRAY_LEN(hex_alias_reg_lt_v69)) { 89 | rz_warn_if_reached(); 90 | return op; 91 | } 92 | op.type = HEX_OP_TYPE_REG; 93 | op.class = hex_alias_reg_lt_v69[alias].cls; 94 | op.op.reg = hex_alias_reg_lt_v69[alias].reg_enum; 95 | // TODO: Add attributes? 96 | return op; 97 | } 98 | 99 | /** 100 | * \brief Returns the real register name for a register alias. 101 | * 102 | * \param alias The register alias. 103 | * \param tmp_reg The register the tmp real register name. 104 | * \return const char * The corresponding register name. Or NULL on error. 105 | */ 106 | RZ_API const char *hex_alias_to_reg(HexRegAlias alias, bool tmp_reg) { 107 | if (alias >= ARRAY_LEN(hex_alias_reg_lt_v69)) { 108 | return NULL; 109 | } 110 | HexRegClass reg_class = hex_alias_reg_lt_v69[alias].cls; 111 | int reg_enum = hex_alias_reg_lt_v69[alias].reg_enum; 112 | if (alias == HEX_REG_ALIAS_PC) { 113 | return "PC"; 114 | } 115 | return hex_get_reg_in_class(reg_class, reg_enum, false, tmp_reg, true); 116 | } 117 | -------------------------------------------------------------------------------- /Tests/testEncoding.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | from bitarray import bitarray 6 | import unittest 7 | 8 | from LLVMImporter import LLVMImporter 9 | from InstructionEncoding import InstructionEncoding 10 | from Operand import SparseMask 11 | 12 | 13 | class TestInstructionEncoding(unittest.TestCase): 14 | def setUp(self) -> None: 15 | self.interface = LLVMImporter(False, test_mode=True, gen_rzil=False, skip_pcpp=True, rzil_compile=False) 16 | self.json = self.interface.hexArch 17 | 18 | def test_manual_mask(self) -> None: 19 | self.assertEqual( 20 | "011111000IIIIIIIPPIiiiiiiiiddddd", 21 | InstructionEncoding(self.json["A2_combineii"]["Inst"]).docs_mask, 22 | ) 23 | self.assertEqual( 24 | "11110101000sssssPP0ttttt000ddddd", 25 | InstructionEncoding(self.json["A2_combinew"]["Inst"]).docs_mask, 26 | ) 27 | self.assertEqual( 28 | "1011iiiiiiisssssPPiiiiiiiiiddddd", 29 | InstructionEncoding(self.json["A2_addi"]["Inst"]).docs_mask, 30 | ) 31 | self.assertEqual( 32 | "0000iiiiiiiiiiiiPPiiiiiiiiiiiiii", 33 | InstructionEncoding(self.json["A4_ext"]["Inst"]).docs_mask, 34 | ) 35 | 36 | def test_bit_masks(self) -> None: 37 | # Initializing a bitarray with a string, it interprets the bit most to the right as the MSB. 38 | # In the manual the MSB is the left most. 39 | # Therefore we reverse the string here. 40 | self.assertEqual( 41 | bitarray("00000000000000000000000000011111"[::-1], endian="little"), 42 | InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["Rdd32"], 43 | ) 44 | self.assertEqual( 45 | bitarray("00000000000000000001111111100000"[::-1], endian="little"), 46 | InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["Ii"], 47 | ) 48 | self.assertEqual( 49 | bitarray("00000000011111110010000000000000"[::-1], endian="little"), 50 | InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["II"], 51 | ) 52 | 53 | self.assertEqual( 54 | bitarray("00000000000000000001111100000000"[::-1], endian="little"), 55 | InstructionEncoding(self.json["A2_combinew"]["Inst"]).operand_masks["Rt32"], 56 | ) 57 | self.assertEqual( 58 | bitarray("00000000000111110000000000000000"[::-1], endian="little"), 59 | InstructionEncoding(self.json["A2_combinew"]["Inst"]).operand_masks["Rs32"], 60 | ) 61 | self.assertEqual( 62 | bitarray("00001111111111110011111111111111"[::-1], endian="little"), 63 | InstructionEncoding(self.json["A4_ext"]["Inst"]).operand_masks["Ii"], 64 | ) 65 | 66 | def test_get_i_class(self) -> None: 67 | self.assertEqual( 68 | 0xD, 69 | InstructionEncoding(self.json["A2_addh_h16_hh"]["Inst"]).get_i_class(), 70 | ) 71 | 72 | def test_num_representation(self) -> None: 73 | self.assertEqual( 74 | 0b1111101000110, 75 | InstructionEncoding(self.json["SL2_return_tnew"]["Inst"]).num_representation, 76 | ) 77 | 78 | def test_correct_operand_names(self) -> None: 79 | # TODO 80 | pass 81 | 82 | def test_shifting_c_code(self) -> None: 83 | self.assertEqual( 84 | "{ 0x8, 5 }", 85 | SparseMask(InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["Ii"]).c_template, 86 | ) 87 | self.assertEqual( 88 | "{ 0x1, 13 }, { 0x7, 16 }", 89 | SparseMask(InstructionEncoding(self.json["A2_combineii"]["Inst"]).operand_masks["II"]).c_template, 90 | ) 91 | 92 | self.assertEqual( 93 | "{ 0xe, 0 }, { 0xc, 16 }", 94 | SparseMask(InstructionEncoding(self.json["A4_ext"]["Inst"]).operand_masks["Ii"]).c_template, 95 | ) 96 | -------------------------------------------------------------------------------- /Tests/testInstruction.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import unittest 6 | 7 | from InstructionTemplate import InstructionTemplate 8 | from UnexpectedException import UnexpectedException 9 | from helperFunctions import normalize_llvm_syntax 10 | 11 | 12 | class TestInstruction(unittest.TestCase): 13 | # TODO Indices for: V6_vS32b_nt_new_pred_ppu: "if ($Pv4) vmem($Rx32++$Mu2):nt = $Os8.new" 14 | 15 | # TODO 16 | # - actual vs. theoretical new operands, also predicates 17 | # - Actual vs. theoretical indices 18 | # - Operand attributes (new, extendable) 19 | # - Op-type and scale values etc 20 | # - Names 21 | # - Rx and Rxin register 22 | 23 | def test_normalize_llvm_syntax(self) -> None: 24 | self.assertEqual( 25 | "Rdd = add(Rs,Rtt)", 26 | normalize_llvm_syntax("$Rdd32 = add($Rs32,$Rtt32)"), 27 | ) 28 | self.assertEqual( 29 | "RDD = add(RS,RTT)", 30 | normalize_llvm_syntax("$RDD32 = add($RS32,$RTT32)"), 31 | ) 32 | self.assertEqual( 33 | "Vxx.w += vmpy(Vu.h,Vv.h)", 34 | normalize_llvm_syntax("$Vxx32.w += vmpy($Vu32.h,$Vv32.h)"), 35 | ) 36 | self.assertEqual( 37 | "Rd = add(Rt.h,Rs.h):<<16", 38 | normalize_llvm_syntax("$Rd32 = add($Rt32.h,$Rs32.h):<<16"), 39 | ) 40 | self.assertEqual( 41 | "if (!Pu) Rd = add(Rs,Rt)", 42 | normalize_llvm_syntax("if (!$Pu4) $Rd32 = add($Rs32,$Rt32)"), 43 | ) 44 | # Specifically named registers 45 | self.assertEqual( 46 | "if (p0.new) dealloc_return:nt", 47 | normalize_llvm_syntax("if (p0.new) dealloc_return:nt"), 48 | ) 49 | self.assertEqual( 50 | "if (!p0.new) jumpr:nt r31", 51 | normalize_llvm_syntax("if (!p0.new) jumpr:nt r31"), 52 | ) 53 | # Duplex 54 | self.assertEqual( 55 | "Rx = add(Rxin,II) ; Rd = memw(Rs+Ii)", 56 | normalize_llvm_syntax("$Rx16 = add($Rx16in,#$II) ; $Rd16 = memw($Rs16+#$Ii)"), 57 | ) 58 | 59 | def test_get_syntax_operand_indices(self) -> None: 60 | syntax = "$RDD8 = combine($RS16,#0) ; $Rd16 = add($Rs16,#$n1)" 61 | operands = [ 62 | ["", "Rd16"], 63 | ["", "Rs16"], 64 | ["", "RDD8"], 65 | ["", "RS16"], 66 | ["", "n1"], 67 | ] 68 | correct_order = {"RDD8": 0, "RS16": 1, "Rd16": 2, "Rs16": 3, "n1": 4} 69 | self.assertEqual( 70 | correct_order, 71 | InstructionTemplate.get_syntax_operand_indices(syntax, operands), 72 | ) 73 | 74 | syntax = "$Rd32 = add($Rs32,#$Ii)" 75 | operands = [["", "Rd32"], ["", "Ii"], ["", "Rs32"]] 76 | correct_order = {"Rd32": 0, "Rs32": 1, "Ii": 2} 77 | self.assertEqual( 78 | correct_order, 79 | InstructionTemplate.get_syntax_operand_indices(syntax, operands), 80 | ) 81 | 82 | syntax = "$Rx16 = add($Rx16in,#$II) ; $Rd16 = memw($Rs16+#$Ii)" 83 | operands = [ 84 | ["", "Rx16"], 85 | ["", "Rx16in"], 86 | ["", "II"], 87 | ["", "Rd16"], 88 | ["", "Rs16"], 89 | ["", "Ii"], 90 | ] 91 | correct_order = { 92 | "Rx16": 0, 93 | "Rx16in": 1, 94 | "II": 2, 95 | "Rd16": 3, 96 | "Rs16": 4, 97 | "Ii": 5, 98 | } 99 | self.assertEqual( 100 | correct_order, 101 | InstructionTemplate.get_syntax_operand_indices(syntax, operands), 102 | ) 103 | 104 | syntax = "$Rd32 = add($Rs32,#$Ii)" 105 | operands = [["", "Ii"], ["", "Ii"], ["", "Rs32"]] 106 | with self.assertRaises(UnexpectedException) as context: 107 | InstructionTemplate.get_syntax_operand_indices(syntax, operands) 108 | self.assertTrue( 109 | "Two operands with the same name given.\n" + "Syntax $Rd32 = add($Rs32,#$Ii), op: Ii" 110 | in str(context.exception) 111 | ) 112 | -------------------------------------------------------------------------------- /handwritten/asm-tests/hexagon: -------------------------------------------------------------------------------- 1 | d "? immext(##0x0)" 00400000 0x0 2 | d "? immext(##0x40)" 01400000 0x0 3 | d "? immext(##0xffffffc0)" ff7fff0f 0x0 4 | 5 | d "? R0 = ##0x101" 20e00078 0x0 6 | d "? R5 = add(clb(LR),#-0x1)" 05ff3f8c 0x0 7 | d "? R4 = add(R19,##0x33)" 64c613b0 0x0 8 | 9 | d "? nop" 00c0007f 0x10000000 10 | d "? LR = add(R0,##0x2)" 5f4000b0 0x0 11 | 12 | d "? P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x14" 04e3c611 0xc 13 | d "? P0 = tstbit(R6,#0); if (!P0.new) jump:t 0x8" fce3f611 0x10 14 | 15 | d "? R7 = ##0x4 ; R0 = -1" 003a4728 0x0 16 | d "? R1:0 = memd(R29+#0x40) ; if (P0) dealloc_return" 441f403e 0x0 17 | d "? R7:6 = memd(R29+#0x40) ; if (!P0) dealloc_return" 451f433e 0x0 18 | d "? R23:22 = combine(#0,#0x2) ; R17:16 = memd(R29+#0x40)" 443e475c 0x0 19 | d "? if (!P0.new) R23 = #0 ; jumpr R31" c03f5f5a 0x0 20 | d "? R4 = add(R4,##0x4) ; R5 = add(R5,#1)" 55314420 21 | 22 | d "? G9:8 = R9:8" 08c00863 0x0 23 | d "? GELR = LR" 00c01f62 0x0 24 | 25 | d "? R11:10 = memb_fifo(R12++M0:brev)" 0a408c9e 0x0 26 | d "? R15:14 = memb_fifo(R7=##0x3)" 6ed0879a 0x0 27 | dB "? C21:20 = R19:18" 14c03263 0x0 28 | d "? C17:16 = R19:18" 10c03263 0x0 29 | d "? PKTCOUNT = LR:FP" 12c03e63 0x0 30 | 31 | d "? V31.h = vsat(V0.w,V13.w)" 7fc06d1f 0x0 32 | 33 | d "? loop0(0x6c,#0x10)" 88c00069 0x68 34 | 35 | d "? memb(R10=##0x7) = R4" 87c40aab 0x9c 36 | d "? R23 = ##0x1f ; R0 = ##0x1f" f029ff29 37 | d "? R23 = ##0x20 ; R0 = ##0x20" 002a0f2a 38 | d "? R1 = ##0x3 ; R23 = -1" 0f3a3128 0x0 39 | d "? R23 = -1 ; R0 = -1" 003a0f3a 0x0 40 | d "? R6 = ##0x4 ; R4 = ##0x0" 04284628 41 | d "? CSwi(R0)" 20400064 0x0 42 | d "? SGP0 = SP" 00401d67 0x0 43 | d "? EVB = R0" 10400067 0x0 44 | d "? S60 = R0" 3c400067 0x0 45 | d "? LR = S80" 1f40d06e 0x0 46 | d "? S35 = R0" 23400067 0x0 47 | d "? ISDBEN = R2" 2a400267 0x0 48 | d "? S61:60 = R1:0" 3c40006d 0x0 49 | d "? S79:78 = R1:0" 4e40006d 0x0 50 | d "? SGP1:0 = R1:0" 004c006d 0x0 51 | d "? R1:0 = SGP1:0" 0040006f 0x0 52 | d "? R1:0 = S79:78" 00404e6f 0x0 53 | 54 | d "? R1:0 = combine(##0x1b,#0x3)" 6063017c 0x0 55 | d "? if (!P0) R5:4 = memd(R0+R2<<#0x0)" 04c2c031 0x0 56 | d "? if (!P0.new) R2 = add(R2,##0x8)" 02618274 0x0 57 | d "? invalid" ffffffff 0x0 58 | d "? invalid ; invalid" ff3fffff 0x0 59 | 60 | d "? barrier" 00c000a8 0x0 61 | d "? dckill" 00c000a2 0x0 62 | d "? l2kill" 00c020a8 0x0 63 | d "? syncht" 00c040a8 0x0 64 | d "? dccleana(R10)" 00c00aa0 0x0 65 | d "? dcinva(R11)" 00c02ba0 0x0 66 | d "? dccleaninva(R12)" 00c04ca0 0x0 67 | d "? dccleanidx(R13)" 00c02da2 0x0 68 | d "? dctagw(R16,R17)" 00d110a4 0x0 69 | d "? dcinvidx(R14)" 00c04ea2 0x0 70 | d "? dccleaninvidx(R15)" 00c06fa2 0x0 71 | d "? R18 = dctagr(R19)" 12c033a4 0x0 72 | d "? l2tagw(R20,R21)" 00d554a4 0x0 73 | d "? R22 = l2tagr(R23)" 16c077a4 0x0 74 | d "? l2fetch(R24,R25)" 00d918a6 0x0 75 | d "? l2cleaninvidx(R26)" 00c07aa8 0x0 76 | d "? swi(R1)" 00c00164 0x0 77 | d "? CSwi(R2)" 20c00264 0x0 78 | d "? iassignw(R3)" 40c00364 0x0 79 | d "? ciad(R4)" 60c00464 0x0 80 | d "? wait(R5)" 00c04564 0x0 81 | d "? resume(R6)" 20c04664 0x0 82 | d "? stop(R7)" 00c06764 0x0 83 | d "? start(R8)" 20c06864 0x0 84 | d "? nmi(R9)" 40c06964 0x0 85 | d "? siad(R10)" 60c08a64 0x0 86 | d "? setimask(P3,R11)" 00c38b64 0x0 87 | d "? crswap(R12,SGP0)" 00c00c65 0x0 88 | d "? crswap(R13,SGP1)" 00c02d65 0x0 89 | d "? R14 = getimask(R15)" 0ec00f66 0x0 90 | d "? R16 = iassignr(R17)" 10c07166 0x0 91 | d "? SSR = R0" 06c00067 0x0 92 | d "? tlbw(R13:12,R3)" 00c30c6c 0x0 93 | d "? brkpt" 00c0206c 0x0 94 | d "? tlblock" 20c0206c 0x0 95 | d "? tlbunlock" 40c0206c 0x0 96 | d "? k0lock" 60c0206c 0x0 97 | d "? k0unlock" 80c0206c 0x0 98 | d "? R3:2 = tlbr(R4)" 02c0446c 0x0 99 | d "? R5 = tlbp(R6)" 05c0866c 0x0 100 | d "? S63:62 = R11:10" 3ec00a6d 0x0 101 | d "? R0 = SSR" 00c0866e 0x0 102 | d "? R1:0 = S63:62" 00c03e6f 0x0 103 | d "? LR = add(PC,##0x4)" 1fc2496a 0x0 104 | d "? trace(LR)" 00c05f62 0x0 105 | d "? R11 = tlboc(R7:6)" 0bc0e66c 0x0 106 | d "? tlbinvasid(R28)" 00c0bc6c 0x0 107 | d "? l2invidx(R22)" 00c056a6 0x0 108 | d "? l2fetch(R19,R1:0)" 00c093a6 0x0 109 | d "? l2cleanidx(R20)" 00c034a6 0x0 110 | d "? R12 = ctlbw(R7:6,R6)" 0cc6c66c 0x0 111 | d "? l2fetch(R24,R13)" 00cd18a6 0x0 112 | -------------------------------------------------------------------------------- /Instruction.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import re 6 | 7 | from InstructionTemplate import InstructionTemplate, LoopMembership 8 | from InstructionEncoding import InstructionEncoding 9 | from helperFunctions import normalize_llvm_syntax, list_to_int 10 | 11 | 12 | class Instruction(InstructionTemplate): 13 | """ 14 | Definition of the instruction with the maximum processing done before being used for disassembly. 15 | """ 16 | 17 | __slots__ = [ 18 | "encoding", 19 | "llvm_instr", 20 | "i_class", 21 | "is_imm_ext", 22 | "llvm_filtered_operands", 23 | "mult_inst", 24 | "imm_ops", 25 | "reg_ops", 26 | "opt_ops", 27 | "branch", 28 | "behavior", 29 | "tokens", 30 | "name", 31 | "type", 32 | "syntax", 33 | "llvm_syntax", 34 | "predicated", 35 | "llvm_filtered_operands", 36 | "is_sub_instruction", 37 | "has_extendable_imm", 38 | "llvm_ext_operand_index", 39 | "must_be_extended", 40 | "extendable_alignment", 41 | "is_solo", 42 | "addr_mode", 43 | "access_size", 44 | "has_new_non_predicate", 45 | "llvm_new_operand_index", 46 | ] 47 | 48 | def __init__(self, llvm_instruction): 49 | super(Instruction, self).__init__(llvm_instruction) 50 | 51 | # Syntax and encoding 52 | self.encoding = InstructionEncoding(self.llvm_instr["Inst"]) 53 | self.llvm_syntax = self.llvm_instr["AsmString"] 54 | self.syntax = normalize_llvm_syntax(self.llvm_instr["AsmString"]) 55 | 56 | # Packet and Duplex 57 | # Has to be only instruction in packet. 58 | self.is_solo = self.llvm_instr["isSolo"][0] if "isSolo" in self.llvm_instr else None 59 | 60 | self.is_sub_instruction = False 61 | 62 | # Operands 63 | self.num_operands = self.get_num_operands(self.llvm_syntax, self.llvm_in_out_operands) 64 | 65 | # Immediate operands 66 | self.has_extendable_imm = self.llvm_instr["isExtendable"][0] == 1 67 | self.must_be_extended = self.llvm_instr["isExtended"][0] == 1 68 | self.ext_operand_index = list_to_int(self.llvm_instr["opExtendable"]) 69 | self.extendable_alignment = list_to_int(self.llvm_instr["opExtentAlign"]) 70 | 71 | # Register operands 72 | self.has_new_non_predicate = self.llvm_instr["isNewValue"][0] == 1 73 | self.new_operand_index = list_to_int(self.llvm_instr["opNewValue"]) 74 | self.is_predicated = self.llvm_instr["isPredicated"][0] == 1 75 | self.is_pred_false |= self.llvm_instr["isPredicatedFalse"][0] == 1 76 | self.is_pred_true |= self.llvm_instr["isPredicatedFalse"][0] == 0 77 | self.is_pred_new |= self.llvm_instr["isPredicatedNew"][0] == 1 78 | 79 | # Special 80 | self.is_endloop = "endloop" in self.name 81 | self.is_loop_begin = "loop" in self.name and not self.is_endloop 82 | self.is_loop = self.is_endloop or self.is_loop_begin 83 | self.loop_member = self.get_loop_membership(self.llvm_syntax) 84 | 85 | self.parse_instruction() 86 | 87 | @staticmethod 88 | def get_num_operands(llvm_syntax: str, llvm_operands: list) -> int: 89 | """Counts operands which actually appear in the syntax. This is necessary in case of 90 | InOutRegisters like Rx/RxIn. 91 | They are always listed in the LLVM instr. but not necessarily appear in the syntax. 92 | """ 93 | s = 0 94 | for op in llvm_operands: 95 | name = op[1] 96 | s += 1 if name in llvm_syntax else 0 97 | return s 98 | 99 | @staticmethod 100 | def get_loop_membership(syntax: str) -> int: 101 | """Returns loop membership to a loop name. 102 | The syntax has to be parsed as some loops have the number not in the name (e.g. J2_ploop3sr). 103 | """ 104 | if re.search(r"loop0[^\d]", syntax): 105 | return LoopMembership.HEX_LOOP_0 106 | elif re.search(r"loop1[^\d]", syntax): 107 | return LoopMembership.HEX_LOOP_1 108 | elif re.search(r"endloop01", syntax): 109 | return ( 110 | LoopMembership.HEX_ENDS_LOOP_0 111 | | LoopMembership.HEX_ENDS_LOOP_1 112 | | LoopMembership.HEX_LOOP_0 113 | | LoopMembership.HEX_LOOP_1 114 | ) 115 | elif re.search(r"enloop1[^\d]", syntax): 116 | return LoopMembership.HEX_LOOP_1 | LoopMembership.HEX_ENDS_LOOP_1 117 | elif re.search(r"enloop0[^\d]", syntax): 118 | return LoopMembership.HEX_LOOP_0 | LoopMembership.HEX_ENDS_LOOP_0 119 | else: 120 | return LoopMembership.HEX_NO_LOOP 121 | -------------------------------------------------------------------------------- /import/gen_registers.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # SPDX-FileCopyrightText: 2021 Rot127 4 | # 5 | # SPDX-License-Identifier: LGPL-3.0-only 6 | 7 | import json 8 | 9 | regs = [ 10 | "sgp0", # s0 11 | "sgp1", # s1 12 | "stid", # s2 13 | "elr", # s3 14 | "badva0", # s4 15 | "badva1", # s5 16 | "ssr", # s6 17 | "ccr", # s7 18 | "htid", # s8 19 | "badva", # s9 20 | "imask", # s10 21 | "gevb", # s11 22 | "s12", # s12 23 | "s13", # s13 24 | "s14", # s14 25 | "s15", # s15 26 | "evb", # s16 27 | "modectl", # s17 28 | "syscfg", # s18 29 | "s19", # s19 30 | "ipendad", # s20 31 | "vid", # s21 32 | "vid1", # s22 33 | "bestwait", # s23 34 | "s24", # s24 35 | "schedcfg", # s25 36 | "s26", # s26 37 | "cfgbase", # s27 38 | "diag", # s28 39 | "rev", # s29 40 | "pcyclelo", # s30 41 | "pcyclehi", # s31 42 | "isdbst", # s32 43 | "isdbcfg0", # s33 44 | "isdbcfg1", # s34 45 | "livelock", # s35 46 | "brkptpc0", # s36 47 | "brkptcfg0", # s37 48 | "brkptpc1", # s38 49 | "brkptcfg1", # s39 50 | "isdbmbxin", # s40 51 | "isdbmbxout", # s41 52 | "isdben", # s42 53 | "isdbgpr", # s43 54 | "pmucnt4", # s44 55 | "pmucnt5", # s45 56 | "pmucnt6", # s46 57 | "pmucnt7", # s47 58 | "pmucnt0", # s48 59 | "pmucnt1", # s49 60 | "pmucnt2", # s50 61 | "pmucnt3", # s51 62 | "pmuevtcfg", # s52 63 | "s53", # s53 64 | "pmuevtcfg1", # s54 65 | "pmustid1", # s55 66 | "timerlo", # s56 67 | "timerhi", # s57 68 | "s58", # s58 69 | "s59", # s59 70 | "s60", # s60 71 | "s61", # s61 72 | "s62", # s62 73 | "s63", # s63 74 | "commit1t", # s64 75 | "commit2t", # s65 76 | "commit3t", # s66 77 | "commit4t", # s67 78 | "commit5t", # s68 79 | "commit6t", # s69 80 | "pcycle1t", # s70 81 | "pcycle2t", # s71 82 | "pcycle3t", # s72 83 | "pcycle4t", # s73 84 | "pcycle5t", # s74 85 | "pcycle6t", # s75 86 | "stfinst", # s76 87 | "isdbcmd", # s77 88 | "isdbver", # s78 89 | "brkptinfo", # s79 90 | "rgdr3", # s80 91 | ] 92 | 93 | with open("Register-template.json") as f: 94 | reg_temp = json.load(f) 95 | with open("Register64-template.json") as f: 96 | reg64_temp = json.load(f) 97 | with open("SysRegs-template.json") as f: 98 | sysregs = json.load(f) 99 | with open("SysRegs64-template.json") as f: 100 | sysregs64 = json.load(f) 101 | 102 | sysregs["SysRegs"]["MemberList"]["args"] = list() 103 | sysregs["SysRegs"]["MemberList"]["printable"] = "(add " 104 | sysregs64["SysRegs64"]["MemberList"]["args"] = list() 105 | sysregs64["SysRegs64"]["MemberList"]["printable"] = "(add " 106 | 107 | for i in range(81): 108 | number_name = "S" + str(i) 109 | name = regs[i].upper() 110 | sysregs["SysRegs"]["MemberList"]["args"].append([{"def": name, "kind": "def", "printable": name}]) 111 | sysregs["SysRegs"]["MemberList"]["printable"] += name + ", " 112 | 113 | reg = dict() 114 | reg[name] = reg_temp 115 | 116 | reg[name]["!name"] = name 117 | reg[name]["AsmName"] = name.lower() 118 | if name != number_name: 119 | reg[name]["AltNames"] = [number_name.lower()] 120 | reg[name]["HWEncoding"] = list() 121 | x = i 122 | for _ in range(16): 123 | reg[name]["HWEncoding"].append(x % 2) 124 | x = x >> 1 125 | with open("registers/{}.json".format(name.upper()), "w") as f: 126 | f.write(json.dumps(reg, indent=2)) 127 | 128 | # Gen double reg 129 | if i % 2 == 1: 130 | reg = dict() 131 | number_name = "S{}_{}".format(i, i - 1) 132 | name = number_name 133 | sysregs64["SysRegs64"]["MemberList"]["args"].append([{"def": name, "kind": "def", "printable": name}]) 134 | sysregs64["SysRegs64"]["MemberList"]["printable"] += name + ", " 135 | 136 | reg[name] = reg_temp 137 | 138 | reg[name]["!name"] = name 139 | reg[name]["AsmName"] = "s{}:{}".format(i, i - 1) 140 | reg[name]["HWEncoding"] = list() 141 | x = i - 1 142 | for _ in range(16): 143 | reg[name]["HWEncoding"].append(x % 2) 144 | x = x >> 1 145 | with open("registers/{}.json".format(name.upper()), "w") as f: 146 | f.write(json.dumps(reg, indent=2)) 147 | 148 | sysregs["SysRegs"]["MemberList"]["printable"] = sysregs["SysRegs"]["MemberList"]["printable"][:-2] + ")" 149 | sysregs64["SysRegs64"]["MemberList"]["printable"] = sysregs64["SysRegs64"]["MemberList"]["printable"][:-2] + ")" 150 | with open("registers/SysRegs.json".format(name.upper()), "w") as f: 151 | f.write(json.dumps(sysregs, indent=2)) 152 | with open("registers/SysRegs64.json".format(name.upper()), "w") as f: 153 | f.write(json.dumps(sysregs64, indent=2)) 154 | -------------------------------------------------------------------------------- /InstructionEncoding.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | from bitarray import bitarray 6 | 7 | from helperFunctions import bitarray_to_uint, log, LogLevel 8 | import HexagonArchInfo 9 | 10 | 11 | class InstructionEncoding: 12 | """ 13 | Represents the encoding of an instruction. 14 | 15 | Attributes: 16 | llvm_encoding: The encoding of an instruction, as it is found in an instruction object of 17 | the llvm-tblgen generated json file. 18 | docs_mask: The mask as it can be found in the Programmers Reference Manual. 19 | llvm_operand_names: A list of llvm type operand names which are encoded in the instruction. 20 | operand_masks: Masks of all operands encoded in the instruction. 21 | num_representation: The first 13bits of the instruction interpreted as number. Variable bits are treated as 0. 22 | Needed for sub instr. comparison. 23 | op_code: The op code as number. 24 | instruction_mask: The mask of the instruction. 25 | """ 26 | 27 | __slots__ = [ 28 | "docs_mask", 29 | "llvm_operand_names", 30 | "operand_masks", 31 | "instruction_mask", 32 | "llvm_encoding", 33 | "op_code", 34 | "num_representation", 35 | "parse_bits_mask", 36 | ] 37 | 38 | def __init__(self, llvm_encoding: list): 39 | self.llvm_operand_names = list() 40 | self.operand_masks = dict() 41 | self.instruction_mask: int = 0 42 | self.op_code: int = 0 43 | self.parse_bits_mask: int = 0 44 | self.docs_mask = "" 45 | self.llvm_encoding = llvm_encoding 46 | # The first 13bit of the encoding as 13bit unsigned int. Variable fields are interpreted as 0. 47 | self.num_representation = 0 48 | 49 | self.parse_encoding() 50 | 51 | def parse_encoding(self): 52 | """Parses each bit in the LLVM encoding and extracts masks and operands from those bits.""" 53 | 54 | instruction_mask = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") 55 | instruction_mask.setall(0) 56 | op_code = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") 57 | op_code.setall(0) 58 | p_bits_mask = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") 59 | p_bits_mask.setall(0) 60 | 61 | for i in range(0, 32): 62 | bit = self.llvm_encoding[i] 63 | # Instruction bits 64 | if bit == 0 or bit == 1: 65 | if i < 13: # Number representation for SubInstruction comparison (Duplex generation). 66 | self.num_representation |= bit << i 67 | 68 | # Parsing bits in Duplex instructions are indicated by E. 69 | if i == 14 or i == 15: 70 | self.docs_mask = "E" + self.docs_mask 71 | p_bits_mask[i] = 1 72 | else: 73 | self.docs_mask = str(bit) + self.docs_mask 74 | 75 | # In the encoding of Qualcomm (see: hexagon_iset_v5.h) we can find some some irrelevant bits 76 | # (depicted as '-'). In the LLVM encoding they are simply set to 0. So we include them in the mask 77 | # and opcode anyways. 78 | instruction_mask[i] = 1 79 | op_code[i] = bit 80 | # The parse bits are set to null/None 81 | elif bit is None: 82 | if i == 14 or i == 15: 83 | self.docs_mask = "P" + self.docs_mask 84 | p_bits_mask[i] = 1 85 | elif bit == "-": # Reserved bit 86 | self.docs_mask = "-" + self.docs_mask 87 | # Variable bits encoding a register or immediate 88 | else: 89 | op_name = bit["var"] 90 | # Not yet parsed operand in encoding found. Create new mask. 91 | if op_name not in self.llvm_operand_names: 92 | self.llvm_operand_names.append(op_name) 93 | self.operand_masks[op_name] = bitarray(HexagonArchInfo.INSTRUCTION_LENGTH, endian="little") 94 | self.operand_masks[op_name].setall(0) 95 | self.operand_masks[op_name][i] = 1 96 | 97 | # We just assume that the second letter is the correct representative. Rd32 -> d, Ii -> i etc. 98 | self.docs_mask = op_name[1] + self.docs_mask 99 | 100 | self.instruction_mask = bitarray_to_uint(instruction_mask, endian="little") 101 | self.op_code = bitarray_to_uint(op_code, endian="little") 102 | self.parse_bits_mask = bitarray_to_uint(p_bits_mask, endian="little") 103 | 104 | log("Added encoding: {} with operands: {}".format(self.docs_mask, self.llvm_operand_names), LogLevel.VERBOSE) 105 | 106 | def get_i_class(self) -> int: 107 | i_class = self.llvm_encoding[28:32] 108 | return i_class[3] << 3 | i_class[2] << 2 | i_class[1] << 1 | i_class[0] 109 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 6 | 7 | # rz-hexagon 8 | 9 | This is a Hexagon disassembly and analysis plugin generator for `rizin`. 10 | It uses the [LLVM target description source code](https://github.com/llvm/llvm-project/tree/main/llvm/lib/Target/Hexagon) 11 | of the Hexagon architecture and additional hand-written code. 12 | 13 | # Missing features and bugs 14 | 15 | This plugin is under continuous work. So checkout the Github issues for missing features or not yet fixed bugs. 16 | 17 | # Prerequisites 18 | 19 | ### Requirements 20 | 21 | - For formatting we need `clang-format`. If it is not available on your distribution, you can install it from https://apt.llvm.org/. 22 | 23 | - Python requirements are in `requirements.txt` 24 | - As a developer you also need `black`, `flake8`, `reuse`. 25 | 26 | ### Hexagon Target Description 27 | 28 | We take all the information about the Hexagon instructions and operands from the many LLVM target description files. 29 | 30 | Luckily there is a tool which combines all the information of those files into one `.json` file which we name `Hexagon.json`. 31 | So `Hexagon.json` will hold all information about the Hexagon instructions and operands. 32 | 33 | In order to generate the `Hexagon.json` file we need the `llvm-tblgen` binary. 34 | 35 | Unfortunately `llvm-tblgen` is usually not provided via the package manager. You have to compile LLVM by yourself. 36 | 37 | ### Build LLVM 38 | 39 | Please follow the [LLVM docs](https://llvm.org/docs/GettingStarted.html#getting-the-source-code-and-building-llvm) 40 | (Build the release version to save **a lot** of RAM). 41 | 42 | `llvm-tblgen` should be in `/llvm-project/build/bin/` after the build. 43 | 44 | Please add this directory to your `PATH`. 45 | 46 | # Install 47 | 48 | **Python 3.11** 49 | 50 | We require `Python 3.11`. Please follow the install-instructions from the [Python documentation](https://docs.python.org/3.11/). 51 | 52 | **Clone repository** 53 | 54 | ```bash 55 | git clone --recurse-submodules https://github.com/rizinorg/rz-hexagon.git 56 | cd rz-hexagon/ 57 | ``` 58 | 59 | **Setup a virtual environment** 60 | 61 | ```bash 62 | python3 -m venv .venv 63 | # Activate the virtual environment. 64 | # This step might differ from shell to shell (the one below is for bash/zsh). 65 | # Take a look at the Python docs if you are using another one. 66 | # https://docs.python.org/3.11/library/venv.html?highlight=virtual%20environment 67 | source .venv/bin/activate 68 | ``` 69 | 70 | **Install `rz-hexagon` as package** 71 | 72 | ```bash 73 | pip3 install -r requirements.txt -r rzil_compiler/requirements.txt 74 | # If you enjoy some colors 75 | pip3 install -r optional_requirements.txt 76 | # Install as develop package 77 | pip3 install -e rzil_compiler/ 78 | pip3 install -e . 79 | ``` 80 | 81 | # Generate PlugIn 82 | 83 | The first time you run the generator you need to add the `-j` option. 84 | This will generate the `Hexagon.json` from the current `LLVM` source. 85 | ``` 86 | ./LLVMImporter.py -j 87 | ``` 88 | 89 | It processes the LLVM definition files and generates C code in `./rizin` and its subdirectories. 90 | 91 | Copy the generated files to the `rizin` directory with 92 | ```commandline 93 | rsync -a rizin/ / 94 | ``` 95 | 96 | ## Test 97 | 98 | You can run the tests with: 99 | ```bash 100 | cd Tests 101 | python3 -m unittest discover -s . -t . 102 | ``` 103 | 104 | # Development info 105 | 106 | **Before you open a PR please run and fix the warnings.: 107 | ```bash 108 | black -l 120 $(git ls-files '*.py') 109 | flake8 --select=W504 --ignore=E203,W503 --max-line-length=120 $(git ls-files '*.py') 110 | reuse lint 111 | ``` 112 | 113 | ### Coding info 114 | - The best way to start is to take a look at an instruction in `Hexagon.json`. 115 | We take all information from there and knowing the different objects 116 | makes it easier to understand the code. 117 | - If you need any information about a llvm specific term or variable name from the `Hexagon.json` file a simple 118 | `grep -rn "term" llvm-project/llvm/lib/Target/Hexagon/` will usually help. 119 | - If you parse LLVM data always end it with an exception else statement: 120 | ```python 121 | if x: 122 | ... 123 | elif y: 124 | ... 125 | elif z: 126 | ... 127 | else: 128 | raise ImplementationException("This case seems to be new, please add it.") 129 | ``` 130 | - Names of variables which holds data directly taken from the `Hexagon.json` file 131 | should have a name which starts with 132 | `llvm_`. 133 | 134 | For example: 135 | 136 | - `llvm_in_operands` holds a list with the content of `Hexagon.json::[Instr].InOperandList`. 137 | - `llvm_syntax` holds: `$Rdd8 = combine(#0,#$Ii)` (the syntax in LLVM style). 138 | - `syntax` holds: `Rdd = combine(#0,#Ii)` (cleaned up LLVM syntax) 139 | - `Instruction.operands` is a dictionary which contains `Register` and `Immediate` Python objects. 140 | 141 | - Please take a brief look at the [Rizin development](https://github.com/rizinorg/rizin/blob/dev/DEVELOPERS.md) guide if you plan to change C code. 142 | 143 | # Contributors 144 | 145 | * Rot127 146 | * Anton Kochkov 147 | * Florian Märkl 148 | -------------------------------------------------------------------------------- /Operand.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | from __future__ import annotations 6 | 7 | from enum import Enum 8 | 9 | from bitarray import bitarray 10 | 11 | import HexagonArchInfo 12 | from ImplementationException import ImplementationException 13 | from helperFunctions import normalize_llvm_syntax 14 | 15 | 16 | class SparseMask: 17 | """ 18 | Generates the C template which extracts the Z bits of each operand. 19 | 20 | Bits of an operand are scattered over the encoded instruction. 21 | Here we assemble them by using the mask of the field. 22 | 23 | Simple example: 24 | Let the input mask of an immediate be: 0b1111111110011111111111110 25 | The bits of the actual immediate in the instruction encoding 26 | need to be concatenated ignoring bit 15:14 and bit 0 (the zeros in the example mask). 27 | So this function returns C-code which shifts the bits of the immediate segments and ORs them 28 | to represent a valid value. 29 | 30 | hi_u32 is the encoded instruction from which we want to concatenate bit 24:16 and bit 13:1 31 | (bit 31:25 are ignored here) 32 | 33 | 2 1 34 | 432109876 54 3210987654321 0 indices 35 | 36 | Mask: 111111111|00|1111111111111|0 37 | hi_u32: 100111101|00|1010000010011|0 38 | | | 39 | | | bit[24:16] shifted three times to the right 40 | +--+-----------------|-------> ((hi_u32 & 0x1ff0000) >> 3) 41 | ____|____ | 42 | 1001111010000000000000 | bit[13:1] shifted once to the right 43 | OR 1010000010011 --+---------------------------------> ((hi_u32 & 0x3ffe) >> 1)) 44 | _______________________ 45 | imm = 1001111011010000010011 46 | 47 | output: 48 | imm = ((hi_u32 & 0x1ff0000) >> 3) | ((hi_u32 & 0x3ffe) >> 1)) 49 | 50 | Args: 51 | mask: Mask of the immediate/register 52 | """ 53 | 54 | def __init__(self, mask: bitarray): 55 | self.full_mask = mask 56 | switch = False 57 | masks_count = 0 # How many parts the mask has 58 | masks = {} 59 | bshift = {} 60 | for i in range(0, 32): 61 | if mask[i]: 62 | if not switch: 63 | switch = True 64 | masks_count += 1 65 | bshift[masks_count - 1] = i 66 | if masks_count - 1 in masks: 67 | masks[masks_count - 1] += 1 68 | else: 69 | masks[masks_count - 1] = 1 70 | else: 71 | switch = False 72 | 73 | self.masks = [(masks[i], bshift[i]) for i in range(masks_count)] 74 | 75 | @property 76 | def c_template(self): 77 | return ", ".join([f"{{ 0x{bits:x}, {shift} }}" for bits, shift in self.masks]) 78 | 79 | 80 | class OperandType(Enum): 81 | REGISTER = "HEX_OP_TYPE_REG" 82 | IMMEDIATE = "HEX_OP_TYPE_IMM" 83 | 84 | 85 | class Operand: 86 | """ 87 | Attributes: 88 | llvm_syntax: syntax of operand as found in the LLVM json (Rd32 etc.) 89 | explicit_syntax: str The register name: R0, C1, V14 etc. 90 | syntax_index: int The index in the syntax 91 | llvm_syntax: str The syntax of operands in the LLVM encoding object: Rd -> Rd32, #s8 -> Ii 92 | """ 93 | 94 | __slots__ = [ 95 | "explicit_syntax", 96 | "llvm_type", 97 | "llvm_syntax", 98 | "syntax_index", 99 | "is_in_operand", 100 | "is_out_operand", 101 | "is_in_out_operand", 102 | "type", 103 | "opcode_mask", 104 | "isa_id", 105 | ] 106 | 107 | def __init__(self, llvm_syntax: str, llvm_type: str, syntax_index: int): 108 | self.llvm_syntax = llvm_syntax 109 | self.llvm_type = llvm_type 110 | self.type: OperandType = self.get_operand_type(llvm_type) 111 | self.syntax_index = syntax_index 112 | self.explicit_syntax = normalize_llvm_syntax(self.llvm_syntax) 113 | self.opcode_mask: SparseMask = None 114 | self.isa_id = "" # ISA identifier character of the QEMU shortcode. d for Rdd, S for II of type s32_0Imm etc. 115 | 116 | self.is_in_operand = False 117 | self.is_out_operand = False 118 | self.is_in_out_operand = False 119 | 120 | def c_template(self, force_extendable=False) -> str: 121 | """Build an initializer for a HexOpTemplate struct in C, representing this operand. 122 | 123 | Keyword arguments: 124 | force_extenable -- For immediate operands, whether is_extendable should be considered 125 | to be true regardless of its stored value. 126 | """ 127 | raise ImplementationException("You need to override this method.") 128 | 129 | @staticmethod 130 | def get_operand_type(operand_type: str) -> OperandType: 131 | if operand_type in HexagonArchInfo.REG_CLASS_NAMES: 132 | return OperandType.REGISTER 133 | elif operand_type in HexagonArchInfo.IMMEDIATE_TYPES: 134 | return OperandType.IMMEDIATE 135 | else: 136 | raise ImplementationException("Unknown operand type: {}".format(operand_type)) 137 | -------------------------------------------------------------------------------- /import/SysRegs64-template.json: -------------------------------------------------------------------------------- 1 | { 2 | "SysRegs64": { 3 | "!anonymous": false, 4 | "!fields": [], 5 | "!name": "GuestRegs64", 6 | "!superclasses": [ 7 | "DAGOperand", 8 | "RegisterClass" 9 | ], 10 | "Alignment": 64, 11 | "AllocationPriority": 0, 12 | "AltOrderSelect": "", 13 | "AltOrders": [], 14 | "CopyCost": 1, 15 | "DecoderMethod": "", 16 | "DiagnosticString": "", 17 | "DiagnosticType": "", 18 | "GeneratePressureSet": 1, 19 | "MemberList": { 20 | "args": [ 21 | [ 22 | { 23 | "def": "S1_0", 24 | "kind": "def", 25 | "printable": "S1_0" 26 | } 27 | ], 28 | [ 29 | { 30 | "def": "S3_2", 31 | "kind": "def", 32 | "printable": "S3_2" 33 | } 34 | ], 35 | [ 36 | { 37 | "def": "S5_4", 38 | "kind": "def", 39 | "printable": "S5_4" 40 | } 41 | ], 42 | [ 43 | { 44 | "def": "S7_6", 45 | "kind": "def", 46 | "printable": "S7_6" 47 | } 48 | ], 49 | [ 50 | { 51 | "def": "S9_8", 52 | "kind": "def", 53 | "printable": "S9_8" 54 | } 55 | ], 56 | [ 57 | { 58 | "def": "S11_10", 59 | "kind": "def", 60 | "printable": "S11_10" 61 | } 62 | ], 63 | [ 64 | { 65 | "def": "S13_12", 66 | "kind": "def", 67 | "printable": "S13_12" 68 | } 69 | ], 70 | [ 71 | { 72 | "def": "S15_14", 73 | "kind": "def", 74 | "printable": "S15_14" 75 | } 76 | ], 77 | [ 78 | { 79 | "def": "S17_16", 80 | "kind": "def", 81 | "printable": "S17_16" 82 | } 83 | ], 84 | [ 85 | { 86 | "def": "S21_20", 87 | "kind": "def", 88 | "printable": "S21_20" 89 | } 90 | ], 91 | [ 92 | { 93 | "def": "S27_26", 94 | "kind": "def", 95 | "printable": "S27_26" 96 | } 97 | ], 98 | [ 99 | { 100 | "def": "S29_28", 101 | "kind": "def", 102 | "printable": "S29_28" 103 | } 104 | ], 105 | [ 106 | { 107 | "def": "S31_30", 108 | "kind": "def", 109 | "printable": "S31_30" 110 | } 111 | ], 112 | [ 113 | { 114 | "def": "S33_32", 115 | "kind": "def", 116 | "printable": "S33_32" 117 | } 118 | ], 119 | [ 120 | { 121 | "def": "S37_36", 122 | "kind": "def", 123 | "printable": "S37_36" 124 | } 125 | ], 126 | [ 127 | { 128 | "def": "S39_38", 129 | "kind": "def", 130 | "printable": "S39_38" 131 | } 132 | ], 133 | [ 134 | { 135 | "def": "S41_40", 136 | "kind": "def", 137 | "printable": "S41_40" 138 | } 139 | ], 140 | [ 141 | { 142 | "def": "S43_42", 143 | "kind": "def", 144 | "printable": "S43_42" 145 | } 146 | ], 147 | [ 148 | { 149 | "def": "S45_44", 150 | "kind": "def", 151 | "printable": "S45_44" 152 | } 153 | ], 154 | [ 155 | { 156 | "def": "S47_46", 157 | "kind": "def", 158 | "printable": "S47_46" 159 | } 160 | ], 161 | [ 162 | { 163 | "def": "S49_48", 164 | "kind": "def", 165 | "printable": "S49_48" 166 | } 167 | ], 168 | [ 169 | { 170 | "def": "S51_50", 171 | "kind": "def", 172 | "printable": "S51_50" 173 | } 174 | ], 175 | [ 176 | { 177 | "def": "S53_52", 178 | "kind": "def", 179 | "printable": "S53_52" 180 | } 181 | ], 182 | [ 183 | { 184 | "def": "S55_54", 185 | "kind": "def", 186 | "printable": "S55_54" 187 | } 188 | ], 189 | [ 190 | { 191 | "def": "S57_56", 192 | "kind": "def", 193 | "printable": "S57_56" 194 | } 195 | ], 196 | [ 197 | { 198 | "def": "S59_58", 199 | "kind": "def", 200 | "printable": "S59_58" 201 | } 202 | ], 203 | [ 204 | { 205 | "def": "S61_60", 206 | "kind": "def", 207 | "printable": "S61_60" 208 | } 209 | ], 210 | [ 211 | { 212 | "def": "S63_62", 213 | "kind": "def", 214 | "printable": "S63_62" 215 | } 216 | ] 217 | ], 218 | "kind": "dag", 219 | "operator": { 220 | "def": "add", 221 | "kind": "def", 222 | "printable": "add" 223 | }, 224 | "printable": "(add S1_0, S3_2, S5_4, S7_6, S9_8, S11_10, S13_12, S15_14, S17_16, S21_20, S27_26, S29_28, S31_30, S33_32, S37_36, S39_38, S41_40, S43_42, S45_44, S47_46, S49_48, S51_50, S53_52, S55_54, S57_56, S59_58, S61_60, S63_62)" 225 | }, 226 | "Namespace": "Hexagon", 227 | "OperandNamespace": "MCOI", 228 | "RegInfos": null, 229 | "RegTypes": [ 230 | { 231 | "def": "i64", 232 | "kind": "def", 233 | "printable": "i64" 234 | } 235 | ], 236 | "Size": 64, 237 | "Weight": null, 238 | "altNameIndex": { 239 | "def": "NoRegAltName", 240 | "kind": "def", 241 | "printable": "NoRegAltName" 242 | }, 243 | "isAllocatable": 0 244 | } 245 | } -------------------------------------------------------------------------------- /import/import_instructions.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | 3 | # SPDX-FileCopyrightText: 2021 Rot127 4 | # 5 | # SPDX-License-Identifier: LGPL-3.0-only 6 | 7 | # This script parses the system instructions in the prgrammers references manual. 8 | # It ignores most of fancy instruction properties like .new operands, 32bit immediates, HVX instructions 9 | # etc. Simply because it gets too complex and the system isntructions don't use those properties. 10 | 11 | import json 12 | import re 13 | 14 | 15 | def parse_ops(ops: list): 16 | ret = list() 17 | for op in ops: 18 | op_type = "" 19 | if re.search(r"R[a-z]{2}", op["op"]): 20 | op_type = "DoubleRegs" 21 | elif re.search(r"R[a-z]", op["op"]): 22 | op_type = "IntRegs" 23 | elif re.search(r"S[a-z]{2}", op["op"]): 24 | op_type = "SysRegs64" 25 | elif re.search(r"S[a-z]", op["op"]): 26 | op_type = "SysRegs" 27 | elif re.search(r"P[a-z]", op["op"]): 28 | op_type = "PredRegs" 29 | elif re.search(r"I[Ii]", op["op"]): 30 | op_type = op["sign"].lower() + op["bits"] + "_" + op["shift"] + "Imm" 31 | else: 32 | print("Operand " + op + " not yet implemented.") 33 | 34 | ret.append([{"def": op_type, "kind": "def", "printable": op_type}, op["op"]]) 35 | op.update({"type": op_type}) 36 | return ret, ops 37 | 38 | 39 | def manual_syntax_to_llvm_syntax(syntax: str) -> dict: 40 | llvm_syntax = syntax 41 | ret = {"in_ops": [], "out_ops": [], "llvm_syntax": ""} 42 | in_ops = list() 43 | out_ops = list() 44 | 45 | # Retrieve registers 46 | for reg in re.findall(r"([RSGVP][dstx]{1,2})", syntax): 47 | if reg[0] == "P": 48 | llvm_reg = "$" + reg + "4" 49 | else: 50 | llvm_reg = "$" + reg + "32" 51 | llvm_syntax = re.sub(reg, llvm_reg, llvm_syntax) 52 | if reg[1] == "d": 53 | out_ops.append({"op": llvm_reg.strip("$"), "char": reg[1], "enc_i": 0}) 54 | elif reg[1] == "x": 55 | out_ops.append({"op": llvm_reg.strip("$"), "char": reg[1], "enc_i": 0}) 56 | in_ops.append({"op": llvm_reg.strip("$") + "in", "char": reg[1]}) 57 | else: 58 | in_ops.append({"op": llvm_reg.strip("$"), "char": reg[1], "enc_i": 0}) 59 | 60 | # Replace immediate. E.g: #u11:3 with #$Ii. 61 | for tup in re.findall(r"(#[uUsS]\d{1,2})(:\d)?", llvm_syntax): 62 | imm = tup[0] if len(tup) == 1 else "".join(tup) 63 | if imm[1] == "u" or imm[1] == "s": 64 | llvm_imm = "#$Ii" 65 | llvm_syntax = re.sub(imm, llvm_imm, llvm_syntax) 66 | elif imm[1] == "U" or imm[1] == "S": 67 | llvm_imm = "#$II" 68 | llvm_syntax = re.sub(imm, llvm_imm, llvm_syntax) 69 | else: 70 | print("Unkown immediate: " + str(imm)) 71 | in_ops.append( 72 | { 73 | "op": llvm_imm.strip("#").strip("$"), 74 | "char": llvm_imm[3], 75 | "enc_i": 0, 76 | "sign": imm[1], 77 | "bits": tup[0][1:], 78 | "shift": 0 if len(tup) == 1 else tup[1][1:], 79 | } 80 | ) 81 | llvm_syntax = re.sub(r"=", " = ", llvm_syntax) 82 | 83 | ret["llvm_syntax"] = llvm_syntax 84 | ret["llvm_in_ops"], ret["in_ops"] = parse_ops(in_ops) 85 | ret["llvm_out_ops"], ret["out_ops"] = parse_ops(out_ops) 86 | return ret 87 | 88 | 89 | def syntax_to_enum_name(syntax: str) -> str: 90 | return ("IMPORTED_" + re.sub(r"[()=$#,+:]", "_", syntax)).strip("_") 91 | 92 | 93 | def main(): 94 | with open("Instruction-template.json") as f: 95 | instr_temp = json.load(f) 96 | 97 | with open("Hexagon-Prog-Manual-v67-Ch-SYSTEM.txt") as f: 98 | for line in f: 99 | # Search for encoding pattern of bits. E.g.: 100 | # 1 0 1 0 0 0 00 1 0 1 s s s s s P P - t t tt t - - - - - - d d memw_locked(Rs,Pd)=Rt 101 | res = re.search(r"^\s*(([10sPd\-xti]\s+){32})(.+$)", line) 102 | if res: 103 | enc = res.group(1).replace(" ", "") 104 | syntax = res.group(3) 105 | name = syntax_to_enum_name(syntax) 106 | llvm_bundle = manual_syntax_to_llvm_syntax(syntax) 107 | instr = dict() 108 | instr[name] = instr_temp 109 | instr[name]["!name"] = name 110 | instr[name]["AsmString"] = llvm_bundle["llvm_syntax"] 111 | instr[name]["InOperandList"]["args"] = llvm_bundle["llvm_in_ops"] 112 | instr[name]["OutOperandList"]["args"] = llvm_bundle["llvm_out_ops"] 113 | instr[name]["Constraints"] = "" 114 | if "$Rx32in" in [r[1] for r in instr[name]["InOperandList"]["args"]]: 115 | instr[name]["Constraints"] = "$Rx32 = $Rx32in" 116 | elif "$Rxx32in" in [r[1] for r in instr[name]["InOperandList"]["args"]]: 117 | instr[name]["Constraints"] = "$Rxx32 = $Rxx32in" 118 | instr[name]["Inst"] = list() 119 | for bit in enc: 120 | if bit == "1" or bit == "0": 121 | instr[name]["Inst"].insert(0, int(bit)) 122 | elif bit == "-": 123 | instr[name]["Inst"].insert(0, 0) 124 | elif bit == "P": 125 | instr[name]["Inst"].insert(0, None) 126 | else: 127 | for op in llvm_bundle["in_ops"] + llvm_bundle["out_ops"]: 128 | if bit == op["char"] and op["op"][-2:] != "in": 129 | bit_index = (enc.count(op["char"]) - int(op["enc_i"])) - 1 130 | instr[name]["Inst"].insert(0, {"index": bit_index, "var": op["op"]}) 131 | op["enc_i"] += 1 132 | break 133 | with open("./instructions/" + name + ".json", "w+") as g: 134 | g.write(json.dumps(instr, indent=2)) 135 | 136 | 137 | if __name__ == "__main__": 138 | main() 139 | -------------------------------------------------------------------------------- /HardwareRegister.py: -------------------------------------------------------------------------------- 1 | # SPDX-FileCopyrightText: 2021 Rot127 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | import re 6 | 7 | import HexagonArchInfo 8 | import PluginInfo 9 | from Register import Register 10 | from helperFunctions import list_to_int 11 | from ImplementationException import ImplementationException 12 | 13 | 14 | class HardwareRegister(Register): 15 | """Represents a concrete Hexagon hardware register. Like R13, C17, V4 etc.""" 16 | 17 | def __init__(self, llvm_reg_class: str, llvm_object: dict, name: str, size: int): 18 | index = list_to_int(llvm_object["HWEncoding"], endian="little") 19 | # We use the super class only to set all the register type flags. 20 | super().__init__( 21 | llvm_syntax=name, 22 | llvm_reg_class=llvm_reg_class, 23 | index=index, 24 | is_new_value=False, 25 | ) 26 | self.name: str = name 27 | self.asm_name = "" 28 | self.alias = "" 29 | self.set_well_defined_asm_names(llvm_object["AsmName"], llvm_object["AltNames"]) 30 | self.dwarf_numbers = llvm_object["DwarfNumbers"] 31 | self.enum_name = ( 32 | PluginInfo.REGISTER_ENUM_PREFIX 33 | + HardwareRegister.register_class_name_to_upper(llvm_reg_class) 34 | + "_" 35 | + re.sub(r":", "_", self.asm_name).upper() 36 | ) 37 | self.sorting_val = int(re.sub(r"[a-zA-Z:]", "", self.asm_name)) # Remove letter and ':' from name. 38 | 39 | self.hw_encoding = index 40 | self.size: int = size if not self.is_vector else size * 2 41 | self.sub_register_names: list = [ 42 | r["def"] for r in llvm_object["SubRegs"] if r["def"] not in HexagonArchInfo.LLVM_FAKE_REGS 43 | ] 44 | 45 | def __lt__(self, other): 46 | return self.sorting_val < other.sorting_val 47 | 48 | def set_well_defined_asm_names(self, llvm_asm: str, llvm_alt: list): 49 | """LLVM is inconsistent about register naming styles. 50 | Sometimes the 's49' style is the alias, sometimes the 'pmucnt1' style is the alias. 51 | Here we define: Alias style = 'lr:fp' Asm style = 'r31:30' and set the attributes accordingly. 52 | """ 53 | 54 | match_asm = re.search(r"^[rcpgvqs]\d{1,2}(:\d{1,2})?$", llvm_asm) 55 | match_alias = re.search(r"^[rcpgvqs]\d{1,2}(:\d{1,2})?$", ",".join(llvm_alt)) 56 | if (llvm_asm == "p3:0") or (llvm_asm in llvm_alt): 57 | match_asm = None 58 | if (llvm_asm in llvm_alt) and len(llvm_alt) == 1: 59 | # Alias of some regs equal asm name. 60 | self.asm_name = llvm_asm 61 | self.alias = [] 62 | if match_asm and match_alias: 63 | raise ImplementationException( 64 | "HW reg alias and asm names match same pattern: alias: {} asm: {}".format(",".join(llvm_alt), llvm_asm) 65 | ) 66 | elif match_asm: 67 | self.asm_name = llvm_asm 68 | self.alias = llvm_alt 69 | elif match_alias: 70 | self.asm_name = llvm_alt[0] 71 | self.alias = [llvm_asm] 72 | else: 73 | raise ImplementationException( 74 | "Alias and asm name of HW reg has no well defined name: alias: {} asm: {}".format( 75 | ",".join(llvm_alt), llvm_asm 76 | ) 77 | ) 78 | 79 | @staticmethod 80 | def get_parse_code_reg_bits(reg_class: str, var: str) -> str: 81 | """Sub register bits are encoded in a space saving way in the instruction encoding. 82 | So we need to shift the bits around before we get the register ID. Here we generate the code for that. 83 | """ 84 | indent = PluginInfo.LINE_INDENT 85 | code = "" 86 | if reg_class == "CtrRegs64" or reg_class == "DoubleRegs" or reg_class == "GuestRegs64" or reg_class == "HvxVQR": 87 | # TODO Assumption: test with actual disassembly 88 | # GuestRegs64 -> OK 89 | # DoubleRegs -> OK 90 | # CtrRegs64 -> MIXED (Missing regs in llvm) C21:20 - C29:28. But they follow the parsing pattern. 91 | # HvxVQR -> FAILS Public HexagonSDK does not support those instructions yet. 92 | # code += "{v} = {v};\n".format(v=var) 93 | pass 94 | elif reg_class == "GeneralDoubleLow8Regs": 95 | code += "{v} = {v} << 1;\n".format(v=var) 96 | code += "if ({} > 6) {{ // HEX_REG_D3 == 6\n".format(var) 97 | code += "{}{} = ({} & 0x7) | 0x10;\n}}".format(indent, var, var) 98 | pass 99 | elif reg_class == "GeneralSubRegs": 100 | code += "if ({} > 7) {{ // HEX_REG_R7 == 7\n".format(var) 101 | code += "{}{} = ({} & 0x7) | 0x10;\n}}".format(indent, var, var) 102 | return code 103 | elif reg_class == "VectRegRev": 104 | # TODO Assumption: test with actual disassembly 105 | # No instructions in LLVM found yet. 106 | # Public HexagonSDK does not support those instructions yet. 107 | code += "{v} = ({v} << 1) + 1;\n".format(v=var) 108 | elif reg_class == "ModRegs": 109 | # ModRegs are effectively control registers. M0 = C6, M1 = C7 110 | code += "{} |= 6;\n".format(var) 111 | return code 112 | 113 | def get_reg_profile(self, offset: int, is_tmp: bool) -> str: 114 | """Returns a one line register profile description. 115 | 116 | Parameters: 117 | offset: The offset into the memory where the register bits are stored. 118 | is_tmp: True if a tmp register profile line should be generated (tmp regs are for RZIL VM). 119 | returns: "type name size mem-offset packed-size" 120 | """ 121 | indent = PluginInfo.LINE_INDENT 122 | aname = self.asm_name.upper() 123 | return '"{t}{i}{n}{i}.{s}{i}{o}{i}0\\n"'.format( 124 | t=self.get_rz_reg_type(), 125 | n=aname if not is_tmp else aname + "_tmp", 126 | s=self.size if not (self.llvm_reg_class == "PredRegs") else 8, 127 | o=str(offset), 128 | i=indent, 129 | ) 130 | 131 | def get_rz_reg_type(self) -> str: 132 | if self.is_control and self.is_hvx: 133 | return "vcc" 134 | elif self.is_vector: 135 | return "vc" 136 | elif self.is_control: 137 | return "ctr" 138 | elif self.is_general or self.is_guest: 139 | return "gpr" 140 | elif self.is_system: 141 | return "sys" 142 | else: 143 | raise ImplementationException("Rizin has no register type for the register {}".format(self.llvm_type)) 144 | -------------------------------------------------------------------------------- /handwritten/rzil-tests/hexagon: -------------------------------------------------------------------------------- 1 | # These tests run the test binaries from QEMU. 2 | # Only bineries which contain 100% supported instructions are run here. 3 | # If one of those tests fails and you need to debug it, 4 | # please use BAP qemu to generate a trace of it 5 | # and compare it with rz-tracetest to Rizin. 6 | # The broken instructions will mismatch. 7 | 8 | NAME=Run test_vspliceb 9 | FILE=bins/elf/hexagon/rzil/test_vspliceb 10 | TIMEOUT=15 11 | CMDS=< 2 | # 3 | # SPDX-License-Identifier: LGPL-3.0-only 4 | 5 | from __future__ import annotations 6 | 7 | import re 8 | 9 | import HexagonArchInfo 10 | from Operand import Operand 11 | from ImplementationException import ImplementationException 12 | from UnexpectedException import UnexpectedException 13 | from helperFunctions import log, LogLevel 14 | 15 | 16 | class Immediate(Operand): 17 | """ 18 | The immediates stored on the instruction encoding have a smaller bit size than 19 | usually needed. The immediate gets extended by the processor. In the syntax 20 | this is denoted by a apply_extention(x). 21 | 22 | 23 | Args: 24 | syntax_index (int): The index of the immediate in the syntax. 25 | 26 | scale (int): Immediates which will always have a value equal to some power of 2 27 | can be shifted to the right before they are encoded into the instruction 28 | (which safes space). scale stores the number of bits the immediate has 29 | to be shifted to the left before it is used. 30 | """ 31 | 32 | __slots__ = [ 33 | "scale", 34 | "type", 35 | "syntax", 36 | "is_signed", 37 | "is_extendable", 38 | "extend_alignment", 39 | "is_pc_relative", 40 | "encoding_width", 41 | "total_width", 42 | "is_constant", 43 | ] 44 | 45 | def __init__( 46 | self, 47 | llvm_syntax: str, 48 | llvm_type: str, 49 | is_extendable: bool, 50 | extend_alignment: int, 51 | syntax_index: int, 52 | ): 53 | super(Immediate, self).__init__(llvm_syntax, llvm_type, syntax_index) 54 | self.is_signed = False 55 | self.is_constant = False 56 | 57 | self.is_extendable = is_extendable 58 | self.extend_alignment = extend_alignment # Extended immediate values are not scaled. But sometimes aligned. 59 | self.is_pc_relative = False 60 | 61 | self.scale = 0 # Num bits shifted to the left. Is set to 0 if the immediate is extendable. 62 | self.encoding_width = 0 # Num. bits stored in encoding. 63 | self.total_width = 0 64 | 65 | self.parse_imm_type(llvm_type, llvm_syntax == "II") 66 | 67 | def parse_imm_type(self, llvm_imm_type: str, is_second: bool) -> None: 68 | """Parse immediate types like: u4_2Imm. This method sets 69 | all kinds of flags, the scale, total width and ISA identifier. 70 | Args: 71 | llvm_imm_type: The llvm type string (e.g.: u4_2Imm). 72 | is_second: Flag if this immediate is the second immediate in the instruction. 73 | """ 74 | type_letter = re.search(r"^([a-z]+)\d{1,2}", llvm_imm_type) 75 | if not type_letter: 76 | raise ImplementationException("Unhandled immediate type: {}".format(llvm_imm_type)) 77 | else: 78 | type_letter = type_letter.group(1) 79 | 80 | if type_letter == "s": 81 | self.is_signed = True 82 | elif type_letter == "u": 83 | self.is_signed = False 84 | # Address used in "call" and "jmp" instructions (a for call, b for jmp) is relative to PC. 85 | elif type_letter == "a" or type_letter == "b": 86 | self.is_signed = True 87 | self.is_pc_relative = True 88 | type_letter = "r" # In QEMUs shortcode all PC relative immediates are named with 'r' 89 | # Constant value -1 90 | elif type_letter == "n": 91 | self.is_signed = True 92 | self.is_constant = True 93 | self.encoding_width = None # Is not encoded in the llvm instruction 94 | width = re.search(r"[a-z](\d+)", llvm_imm_type) 95 | if not width: 96 | raise ImplementationException("Unhandled immediate type: {}".format(llvm_imm_type)) 97 | else: 98 | self.total_width = width.group(1) 99 | self.is_extendable = False 100 | log("Parsed imm type: {}, width: {}".format(type_letter, self.total_width), LogLevel.VERBOSE) 101 | return 102 | else: 103 | raise ImplementationException("Unhandled immediate type: {}".format(llvm_imm_type)) 104 | self.isa_id = type_letter.upper() if is_second else type_letter 105 | 106 | # Value before _ represents number of encoded bits. 107 | result = re.search(r"[a-z](\d+)\_", llvm_imm_type) 108 | if result: 109 | self.encoding_width = int(result.group(1)) 110 | else: 111 | raise ImplementationException("Could not parse encoding width of immediate type: {}".format(llvm_imm_type)) 112 | 113 | # Value after the _ represents tells how often the immediate has to be shifted. 114 | result = re.search(r"\_(\d+)Imm", llvm_imm_type) 115 | if result: 116 | self.scale = int(result.group(1)) 117 | else: 118 | raise ImplementationException("Could not find parse scale of immediate type: {}".format(llvm_imm_type)) 119 | 120 | self.total_width = self.encoding_width + self.scale 121 | mx = HexagonArchInfo.MAX_IMM_LEN 122 | nw = int((self.total_width - mx) / 4) 123 | if self.total_width > mx: 124 | log( 125 | "Rizins hexagon_disas.c assumes that immediate values are not" 126 | " larger than {}bit.\n".format(mx) 127 | + "\tImmediate type: {} is {}bits long.\n".format(self.llvm_type, self.total_width) 128 | + "\tPlease increase the buffer hexagon_disas.c::signed_imm by" 129 | " at least {} bits.".format(nw), 130 | LogLevel.WARNING, 131 | ) 132 | 133 | # The extended immediate should have always the op_type of a 32/64bit wide immediate. 134 | if self.is_extendable and not (self.total_width == 32 or self.total_width == 64): 135 | raise UnexpectedException( 136 | "Extendable immediate is not 32 or 64bits long!\n" + "imm: {}".format(self.llvm_syntax) 137 | ) 138 | 139 | def c_template(self, force_extendable=False) -> str: 140 | if self.is_constant: 141 | return ".info = HEX_OP_TEMPLATE_TYPE_IMM_CONST" 142 | info = ["HEX_OP_TEMPLATE_TYPE_IMM"] 143 | if self.is_signed: 144 | if self.opcode_mask.full_mask.count(1) <= 0: 145 | raise ImplementationException( 146 | "The bits encoding the immediate value should never be <=" 147 | " 0!\nOperand type: {}, Mask: {}".format(self.llvm_type, str(self.opcode_mask.full_mask)) 148 | ) 149 | info.append("HEX_OP_TEMPLATE_FLAG_IMM_SIGNED") 150 | if self.is_extendable or force_extendable: 151 | info.append("HEX_OP_TEMPLATE_FLAG_IMM_EXTENDABLE") 152 | if self.is_pc_relative: 153 | info.append("HEX_OP_TEMPLATE_FLAG_IMM_PC_RELATIVE") 154 | if self.total_width == 32: 155 | info.append("HEX_OP_TEMPLATE_FLAG_IMM_DOUBLE_HASH") 156 | info = " | ".join(info) 157 | r = f".info = {info}, .masks = {{ {self.opcode_mask.c_template} }}, " 158 | r += f".isa_id = '{self.isa_id if self.isa_id != '' else 0}'" 159 | if self.scale > 0: 160 | r += f", .imm_scale = {self.scale}" 161 | return r 162 | -------------------------------------------------------------------------------- /LICENSES/CC0-1.0.txt: -------------------------------------------------------------------------------- 1 | Creative Commons Legal Code 2 | 3 | CC0 1.0 Universal 4 | 5 | CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE 6 | LEGAL SERVICES. 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Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. 67 | 68 | Each version is given a distinguishing version number. If the Library as you received it specifies that a certain numbered version of the GNU Lesser General Public License "or any later version" applies to it, you have the option of following the terms and conditions either of that published version or of any later version published by the Free Software Foundation. If the Library as you received it does not specify a version number of the GNU Lesser General Public License, you may choose any version of the GNU Lesser General Public License ever published by the Free Software Foundation. 69 | 70 | If the Library as you received it specifies that a proxy can decide whether future versions of the GNU Lesser General Public License shall 71 | apply, that proxy's public statement of acceptance of any version is permanent authorization for you to choose that version for the Library. 72 | -------------------------------------------------------------------------------- /handwritten/asm_hexagon_c/initialization.c: -------------------------------------------------------------------------------- 1 | // SPDX-FileCopyrightText: 2021 Rot127 2 | // SPDX-License-Identifier: LGPL-3.0-only 3 | 4 | static RZ_OWN RzPVector /**/ *get_token_patterns() { 5 | RzPVector *pvec = rz_pvector_new(rz_asm_token_pattern_free); 6 | 7 | RzAsmTokenPattern *pat = RZ_NEW0(RzAsmTokenPattern); 8 | pat->type = RZ_ASM_TOKEN_META; 9 | pat->pattern = strdup( 10 | "^[\\[\\?\\/\\|\\\\\\{┌│└]|" // Packet prefix 11 | "(∎|[<\\}])[\\s:]endloop[01]{1,2}" // Endloop markers 12 | ); 13 | rz_pvector_push(pvec, pat); 14 | 15 | pat = RZ_NEW0(RzAsmTokenPattern); 16 | pat->type = RZ_ASM_TOKEN_META; 17 | pat->pattern = strdup( 18 | "\\#{1,2}|\\}$|" // Immediate prefix, Closing packet bracket 19 | "\\.new|:n?t|:raw|" // .new and jump hints 20 | ); 21 | rz_pvector_push(pvec, pat); 22 | 23 | pat = RZ_NEW0(RzAsmTokenPattern); 24 | pat->type = RZ_ASM_TOKEN_REGISTER; 25 | pat->pattern = strdup( 26 | "[CNPRMQVO]\\d{1,2}(:\\d{1,2})?(in)?" // Registers and double registers 27 | ); 28 | rz_pvector_push(pvec, pat); 29 | 30 | pat = RZ_NEW0(RzAsmTokenPattern); 31 | pat->type = RZ_ASM_TOKEN_REGISTER; 32 | pat->pattern = strdup( 33 | "GP|HTID|UGP|LR|FP|SP" // Other regs 34 | ); 35 | rz_pvector_push(pvec, pat); 36 | 37 | pat = RZ_NEW0(RzAsmTokenPattern); 38 | pat->type = RZ_ASM_TOKEN_NUMBER; 39 | pat->pattern = strdup( 40 | "0x(\\d|[abcdef])+" // Hexadecimal numbers 41 | ); 42 | rz_pvector_push(pvec, pat); 43 | 44 | pat = RZ_NEW0(RzAsmTokenPattern); 45 | pat->type = RZ_ASM_TOKEN_MNEMONIC; 46 | pat->pattern = strdup( 47 | "\\w+_\\w+|[a-zA-Z]+\\d+[a-zA-Z]*" // Mnemonics with a decimal number in the name. 48 | ); 49 | rz_pvector_push(pvec, pat); 50 | 51 | pat = RZ_NEW0(RzAsmTokenPattern); 52 | pat->type = RZ_ASM_TOKEN_NUMBER; 53 | pat->pattern = strdup( 54 | "\\d+" // Decimal numbers 55 | ); 56 | rz_pvector_push(pvec, pat); 57 | 58 | pat = RZ_NEW0(RzAsmTokenPattern); 59 | pat->type = RZ_ASM_TOKEN_SEPARATOR; 60 | pat->pattern = strdup( 61 | "\\s+|" // Spaces and tabs 62 | "[,;\\.\\(\\)\\{\\}:]" // Brackets and others 63 | ); 64 | rz_pvector_push(pvec, pat); 65 | 66 | pat = RZ_NEW0(RzAsmTokenPattern); 67 | pat->type = RZ_ASM_TOKEN_OPERATOR; 68 | pat->pattern = strdup( 69 | "[+*&+?=!^\\/|-]{1,2}" // +,-,=,],[, ! (not the packet prefix) 70 | ); 71 | rz_pvector_push(pvec, pat); 72 | 73 | pat = RZ_NEW0(RzAsmTokenPattern); 74 | pat->type = RZ_ASM_TOKEN_OPERATOR; 75 | pat->pattern = strdup( 76 | "\\]|\\[|<{1,2}|>{1,2}" // +,-,=,],[, ! (not the packet prefix) 77 | ); 78 | rz_pvector_push(pvec, pat); 79 | 80 | pat = RZ_NEW0(RzAsmTokenPattern); 81 | pat->type = RZ_ASM_TOKEN_MNEMONIC; 82 | pat->pattern = strdup( 83 | "\\w+" // Alphanumeric mnemonics 84 | ); 85 | rz_pvector_push(pvec, pat); 86 | 87 | return pvec; 88 | } 89 | 90 | /** 91 | * \brief Setter for the plugins RzConfig nodes. 92 | * 93 | * \param user The user of the RzConfig node. If this callback is called by Core \p user = RzCore. 94 | * If it is called by the plugins config setup \p user = HexState. 95 | * \param data The node to set. Again, if called by RzCore \p date = Node from RzCore config. 96 | * If it is called by the plugins config setup \p data = a plugins config node. 97 | * \return bool True if the config was set. False otherwise. 98 | */ 99 | static bool hex_cfg_set(void *user, void *data) { 100 | rz_return_val_if_fail(user && data, false); 101 | HexState *state = hexagon_state(false); 102 | if (!state) { 103 | return false; 104 | } 105 | RzConfig *pcfg = state->cfg; 106 | 107 | RzConfigNode *cnode = (RzConfigNode *)data; // Config node from core. 108 | RzConfigNode *pnode = rz_config_node_get(pcfg, cnode->name); // Config node of plugin. 109 | if (pnode == cnode) { 110 | return true; 111 | } 112 | if (cnode) { 113 | pnode->i_value = cnode->i_value; 114 | pnode->value = strdup(cnode->value); 115 | return true; 116 | } 117 | return false; 118 | } 119 | 120 | RZ_IPI void hexagon_state_fini(HexState *state) { 121 | if (!state) { 122 | return; 123 | } 124 | rz_config_free(state->cfg); 125 | rz_pvector_free(state->token_patterns); 126 | rz_list_free(state->const_ext_l); 127 | return; 128 | } 129 | 130 | static bool hexagon_fini(void *user) { 131 | hexagon_state_fini(hexagon_state(false)); 132 | hexagon_state(true); 133 | return true; 134 | } 135 | 136 | static bool hexagon_init(void **user) { 137 | HexState *state = hexagon_state(false); 138 | rz_return_val_if_fail(state, false); 139 | 140 | state->cfg = rz_config_new(state); 141 | rz_return_val_if_fail(state->cfg, false); 142 | 143 | RzConfig *cfg = state->cfg; // Rename for SETCB macros. 144 | // Add nodes 145 | SETCB("plugins.hexagon.imm.hash", "true", &hex_cfg_set, "Display ## before 32bit immediates and # before immidiates with other width."); 146 | SETCB("plugins.hexagon.imm.sign", "true", &hex_cfg_set, "True: Print them with sign. False: Print signed immediates in unsigned representation."); 147 | SETCB("plugins.hexagon.sdk", "false", &hex_cfg_set, "Print packet syntax in objdump style."); 148 | SETCB("plugins.hexagon.reg.alias", "true", &hex_cfg_set, "Print the alias of registers (Alias from C0 = SA0)."); 149 | 150 | if (!state->token_patterns) { 151 | state->token_patterns = get_token_patterns(); 152 | } 153 | rz_asm_compile_token_patterns(state->token_patterns); 154 | 155 | return true; 156 | } 157 | 158 | RZ_API RZ_BORROW RzConfig *hexagon_get_config() { 159 | HexState *state = hexagon_state(false); 160 | rz_return_val_if_fail(state, NULL); 161 | return state->cfg; 162 | } 163 | 164 | /** 165 | * \brief Disassembles a hexagon opcode, write info to op and returns its size. 166 | * 167 | * \param a The current RzAsm struct. 168 | * \param op The RzAsmOp which is be filled with the reversed opcode information. 169 | * \param buf The buffer with the opcode. 170 | * \param l The size to read from the buffer. 171 | * \return int Size of the reversed opcode. 172 | */ 173 | static int disassemble(RzAsm *a, RzAsmOp *op, const ut8 *buf, int l) { 174 | rz_return_val_if_fail(a && op && buf, -1); 175 | if (l < HEX_INSN_SIZE) { 176 | return -1; 177 | } 178 | ut32 addr = (ut32)a->pc; 179 | // Disassemble as many instructions as possible from the buffer. 180 | ut32 buf_offset = 0; 181 | while (buf_offset + HEX_INSN_SIZE <= l && buf_offset <= HEX_INSN_SIZE * HEX_MAX_INSN_PER_PKT) { 182 | const ut32 buf_ptr = rz_read_at_le32(buf, buf_offset); 183 | if (buf_offset > 0 && (buf_ptr == HEX_INVALID_INSN_0 || buf_ptr == HEX_INVALID_INSN_F)) { 184 | // Do not disassemble invalid instructions, if we already have a valid one. 185 | break; 186 | } 187 | 188 | HexReversedOpcode rev = { .action = HEXAGON_DISAS, .ana_op = NULL, .asm_op = op }; 189 | hexagon_reverse_opcode(a, &rev, buf + buf_offset, addr + buf_offset, false); 190 | buf_offset += HEX_INSN_SIZE; 191 | } 192 | // Copy operation actually requested. 193 | HexReversedOpcode rev = { .action = HEXAGON_DISAS, .ana_op = NULL, .asm_op = op }; 194 | hexagon_reverse_opcode(a, &rev, buf, addr, true); 195 | return HEX_INSN_SIZE; 196 | } 197 | 198 | RzAsmPlugin rz_asm_plugin_hexagon = { 199 | .name = "hexagon", 200 | .arch = "hexagon", 201 | .author = "Rot127", 202 | .license = "LGPL3", 203 | .bits = 32, 204 | .desc = "Qualcomm Hexagon (QDSP6) V6", 205 | .init = &hexagon_init, 206 | .fini = &hexagon_fini, 207 | .disassemble = &disassemble, 208 | .get_config = &hexagon_get_config, 209 | }; 210 | 211 | #ifndef RZ_PLUGIN_INCORE 212 | RZ_API RzLibStruct rizin_plugin = { 213 | .type = RZ_LIB_TYPE_ASM, 214 | .data = &rz_asm_plugin_hexagon 215 | }; 216 | #endif 217 | -------------------------------------------------------------------------------- /import/instructions/IMPORTED_l2gclean_Rtt.json: -------------------------------------------------------------------------------- 1 | { 2 | "IMPORTED_l2gclean_Rtt": { 3 | "!anonymous": false, 4 | "!fields": [ 5 | "SoftFail", 6 | "Inst" 7 | ], 8 | "!name": "IMPORTED_l2gclean_Rtt", 9 | "!superclasses": [ 10 | "InstructionEncoding", 11 | "Instruction", 12 | "InstHexagon", 13 | "HInst", 14 | "OpcodeHexagon", 15 | "Enc_a51a9a" 16 | ], 17 | "AddedComplexity": 0, 18 | "AsmMatchConverter": "", 19 | "AsmString": "l2gclean($Rtt32)", 20 | "AsmVariantName": "", 21 | "BaseOpcode": "", 22 | "CVINew": 0, 23 | "CextOpcode": "", 24 | "CodeSize": 0, 25 | "Constraints": "", 26 | "DecoderMethod": "", 27 | "DecoderNamespace": "", 28 | "Defs": [], 29 | "DisableEncoding": "", 30 | "EncodingInfos": null, 31 | "FastISelShouldIgnore": 0, 32 | "InOperandList": { 33 | "args": [ 34 | [ 35 | { 36 | "def": "DoubleRegs", 37 | "kind": "def", 38 | "printable": "DoubleRegs" 39 | }, 40 | "Rtt32" 41 | ] 42 | ], 43 | "kind": "dag", 44 | "operator": { 45 | "def": "ins", 46 | "kind": "def", 47 | "printable": "ins" 48 | }, 49 | "printable": "(ins u8_0Imm:$Ii)" 50 | }, 51 | "InputType": "", 52 | "Inst": [ 53 | 0, 54 | 0, 55 | 0, 56 | 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| } 396 | } -------------------------------------------------------------------------------- /import/instructions/IMPORTED_l2gcleaninv_Rtt.json: -------------------------------------------------------------------------------- 1 | { 2 | "IMPORTED_l2gcleaninv_Rtt": { 3 | "!anonymous": false, 4 | "!fields": [ 5 | "SoftFail", 6 | "Inst" 7 | ], 8 | "!name": "IMPORTED_l2gcleaninv_Rtt", 9 | "!superclasses": [ 10 | "InstructionEncoding", 11 | "Instruction", 12 | "InstHexagon", 13 | "HInst", 14 | "OpcodeHexagon", 15 | "Enc_a51a9a" 16 | ], 17 | "AddedComplexity": 0, 18 | "AsmMatchConverter": "", 19 | "AsmString": "l2gcleaninv($Rtt32)", 20 | "AsmVariantName": "", 21 | "BaseOpcode": "", 22 | "CVINew": 0, 23 | "CextOpcode": "", 24 | "CodeSize": 0, 25 | "Constraints": "", 26 | "DecoderMethod": "", 27 | "DecoderNamespace": "", 28 | "Defs": [], 29 | "DisableEncoding": "", 30 | "EncodingInfos": null, 31 | "FastISelShouldIgnore": 0, 32 | "InOperandList": { 33 | "args": [ 34 | [ 35 | { 36 | "def": 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