├── .gitignore ├── Baremetal-applications ├── DMA_transfer_FPGA_DMAC │ ├── Makefile │ ├── README.md │ ├── alt_address_space.c │ ├── arm_cache_modified.h │ ├── arm_cache_modified.s │ ├── cycloneV-dk-ram-modified.ld │ ├── debug-hosted.ds │ ├── dma_demo.c │ ├── fpga_dmac_api.c │ ├── fpga_dmac_api.h │ └── io.c ├── DMA_transfer_PL330_ACP │ ├── Makefile │ ├── README.md │ ├── alt_address_space.c │ ├── alt_dma.c │ ├── alt_dma_modified.c │ ├── alt_dma_modified.h │ ├── alt_dma_program.c │ ├── alt_globaltmr.c │ ├── arm_cache_modified.h │ ├── arm_cache_modified.s │ ├── cycloneV-dk-ram-modified.ld │ ├── debug-hosted.ds │ ├── dma_demo.c │ └── io.c └── Second_counter_PMU │ ├── Makefile │ ├── README.md │ ├── alt_types.h │ ├── cycloneV-dk-ram-modified.ld │ ├── io.c │ ├── main.c │ ├── pmu.c │ └── pmu.h ├── CycloneVSoC.png ├── FPGA-hardware └── DE1-SoC │ ├── FPGA_DMA │ ├── FPGA_DMA.png │ ├── README.md │ ├── ghrd_top.v │ ├── ip │ │ ├── altsource_probe │ │ │ ├── hps_reset.qip │ │ │ ├── hps_reset.v │ │ │ └── hps_reset_bb.v │ │ ├── axi_conduit_merger │ │ │ ├── axi_conduit_merger.v │ │ │ └── axi_conduit_merger_hw.tcl │ │ ├── debounce │ │ │ └── debounce.v │ │ └── edge_detect │ │ │ └── altera_edge_detector.v │ ├── soc_system.qpf │ ├── soc_system.qsf │ ├── soc_system.qsys │ ├── soc_system_assignment_defaults.qdf │ └── sof_rbf │ │ ├── RD │ │ ├── soc_system.rbf │ │ └── soc_system.sof │ │ └── WR │ │ ├── soc_system.rbf │ │ └── soc_system.sof │ └── FPGA_OCR_256K │ ├── FPGA_OCR_256K.png │ ├── README.md │ ├── ghrd_top.v │ ├── ip │ ├── altsource_probe │ │ ├── hps_reset.qip │ │ ├── hps_reset.v │ │ └── hps_reset_bb.v │ ├── debounce │ │ └── debounce.v │ └── edge_detect │ │ └── altera_edge_detector.v │ ├── soc_system.qpf │ ├── soc_system.qsf │ ├── soc_system.qsys │ └── soc_system_assignment_defaults.qdf ├── LICENSE ├── Linux-applications ├── DMA_transfer_FPGA_DMAC │ ├── DMA_transfer_FPGA_DMAC.c │ ├── Makefile │ ├── README.md │ ├── fpga_dmac_api.c │ └── fpga_dmac_api.h ├── DMA_transfer_FPGA_DMAC_driver │ ├── DMA_transfer_FPGA_DMAC.c │ ├── Makefile │ ├── README.md │ ├── fpga_dmac_api.c │ └── fpga_dmac_api.h └── Test_DMA_PL330_LKM │ ├── Makefile │ ├── README.md │ └── test_DMA_PL330_LKM.c ├── Linux-modules ├── Alloc_DMAble_buff_LKM │ ├── Makefile │ ├── README.md │ ├── alloc_dmable_buffer.ko │ ├── alloc_dmable_buffer_LKM.c │ ├── alt_acpidmap.h │ ├── alt_address_space.c │ ├── alt_address_space.h │ └── hwlib_socal_linux.h ├── DMA_PL330_LKM │ ├── DMA_Data_Paths.png │ ├── DMA_PL330.ko │ ├── DMA_PL330_LKM.c │ ├── Makefile │ ├── README.md │ ├── alt_acpidmap.h │ ├── alt_address_space.c │ ├── alt_address_space.h │ ├── alt_dma.c │ ├── alt_dma.h │ ├── alt_dma_common.h │ ├── alt_dma_periph_cv_av.h │ ├── alt_dma_program.c │ ├── alt_dma_program.h │ └── hwlib_socal_linux.h ├── DMA_PL330_LKM_basic │ ├── DMA_PL330_LKM_basic.c │ ├── DMA_PL330_basic.ko │ ├── Four-examples.png │ ├── Makefile │ ├── README.md │ ├── alt_acpidmap.h │ ├── alt_address_space.c │ ├── alt_address_space.h │ ├── alt_dma.c │ ├── alt_dma.h │ ├── alt_dma_common.h │ ├── alt_dma_periph_cv_av.h │ ├── alt_dma_program.c │ ├── alt_dma_program.h │ └── hwlib_socal_linux.h └── Enable_PMU_user_space │ ├── Makefile │ ├── PMU_User_Space_EN.c │ ├── PMU_User_Space_EN.ko │ ├── README.md │ └── access_PMU_user.png ├── README.md ├── SD-baremetal ├── FAT32-partition.png ├── README.md ├── preloader-mkpimage_baremetal_watchdogOFF.bin ├── u-boot.img ├── u-boot.scr └── u-boot.script ├── SD-operating-system ├── Angstrom-v2013.12 │ ├── Files_to_build_SD_DE1-SoC │ │ ├── Angstrom-console-rootfs.tar.gz │ │ ├── DTB │ │ │ ├── Files from Terasic │ │ │ │ ├── README_terasic.txt │ │ │ │ ├── hps_common_board_info.xml │ │ │ │ ├── soc_system_board_info.xml │ │ │ │ └── socfpga.dtb │ │ │ ├── Files from WS2 │ │ │ │ ├── README.txt │ │ │ │ ├── hps_common_board_info.xml │ │ │ │ ├── soc_system_board_info.xml │ │ │ │ └── socfpga.dtb │ │ │ └── README.txt │ │ ├── README.txt │ │ ├── preloader-mkpimage.bin │ │ ├── soc_system.rbf │ │ ├── u-boot.img │ │ ├── u-boot.scr │ │ ├── u-boot.script │ │ └── zImages │ │ │ ├── 3.10ltsi │ │ │ └── zImage │ │ │ ├── 3.18 │ │ │ └── zImage │ │ │ └── Original Terasic Console │ │ │ └── zImage │ ├── README.md │ └── figs │ │ ├── Angstrom_loads_correctly.png │ │ ├── SD_card_partitions.png │ │ ├── Win32_disk_imager.png │ │ ├── dtb_generation.png │ │ ├── preloader1.png │ │ ├── preloader2.png │ │ ├── preloader3.png │ │ ├── preloader4.png │ │ ├── preloader5.png │ │ ├── preloader6.png │ │ ├── preloader7.png │ │ ├── sof_to_rbf.png │ │ ├── uboot_console.png │ │ ├── uboot_fails_zimage.png │ │ └── uboot_script_generation.png └── Angstrom-v2016.12 │ └── README.rst ├── Starting-guides └── DTE DE1-SoC Starting Guide Small.pdf └── Useful-scripts └── fixed_mac_dhcp.sh /.gitignore: -------------------------------------------------------------------------------- 1 | #Files after compilation not to be uploaded to the repository 2 | 3 | #modules 4 | **.o 5 | **.mod 6 | **.mod.c 7 | **.cmd 8 | **-swp 9 | **symvers 10 | **.order 11 | **tmp_versions/** 12 | 13 | #baremetal 14 | *.axf** 15 | **/Baremetal-applications/**/*.o 16 | **/Baremetal-applications/**/*.bin 17 | **/Baremetal-applications/**/*.bin.img 18 | 19 | #Quartus II files 20 | **/FPGA-hardware/**/**/.qsys_edit/** 21 | **/FPGA-hardware/**/**/db/** 22 | **/FPGA-hardware/**/**/incremental_db/** 23 | **/FPGA-hardware/**/**/soc_system/** 24 | **/FPGA-hardware/**/**/hps_isw_handoff/** 25 | **/FPGA-hardware/**/**/*.txt 26 | **/FPGA-hardware/**/**/*.rpt 27 | **/FPGA-hardware/**/**/*.csv 28 | **/FPGA-hardware/**/**/*.done 29 | **/FPGA-hardware/**/**/*.smsg 30 | **/FPGA-hardware/**/**/*.summary 31 | **/FPGA-hardware/**/**/*.pin 32 | **/FPGA-hardware/**/**/*.jdi 33 | **/FPGA-hardware/**/**/*.sopcinfo 34 | **/FPGA-hardware/**/**/*.sld 35 | **/FPGA-hardware/**/**/*.qws 36 | **/FPGA-hardware/**/**/*.sof 37 | **/FPGA-hardware/**/**/*.rbf 38 | **/FPGA-hardware/**/**/*.cdf 39 | **/FPGA-hardware/**/**/*.stp 40 | **/FPGA-hardware/**/**/*.cof 41 | **/FPGA-hardware/**/**/*.bak 42 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | # Copyright Altera 2013,2014 3 | # All Rights Reserved. 4 | # 5 | 6 | SOCEDS_ROOT ?= $(SOCEDS_DEST_ROOT) 7 | HWLIBS_ROOT = $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib 8 | 9 | # look for SoC EDS 15.0 directory structure 10 | ifneq (,$(wildcard $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av/socal)) 11 | SOCAL_ROOT := $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib/include/soc_cv_av 12 | endif 13 | 14 | # look for SoC EDS 14.0 directory structure 15 | ifneq (,$(wildcard $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib/include/socal)) 16 | SOCAL_ROOT := $(SOCEDS_ROOT)/ip/altera/hps/altera_hps/hwlib/include 17 | endif 18 | 19 | # this will cahnge for system to system. just needed to make the mkimage wrapper. If you are using it after uboot it is not needed. 20 | MKI := mkimage 21 | 22 | ifndef SOCAL_ROOT 23 | $(error SOCAL_ROOT is undefined) 24 | endif 25 | 26 | EXAMPLE_SRC := dma_demo.c io.c arm_cache_modified.s alt_address_space.c fpga_dmac_api.c 27 | C_SRC := $(EXAMPLE_SRC) 28 | 29 | LINKER_SCRIPT := cycloneV-dk-ram-modified.ld 30 | 31 | MULTILIBFLAGS := -mcpu=cortex-a9 -mfloat-abi=softfp -mfpu=neon 32 | CFLAGS := -g -O0 -Wall -Werror -std=c99 $(MULTILIBFLAGS) -I$(HWLIBS_ROOT)/include -I. -Imsgdma -Iqsys_headers -I$(SOCAL_ROOT) 33 | LDFLAGS := -T$(LINKER_SCRIPT) $(MULTILIBFLAGS) 34 | 35 | CROSS_COMPILE := arm-altera-eabi- 36 | CC := $(CROSS_COMPILE)gcc 37 | LD := $(CROSS_COMPILE)g++ 38 | NM := $(CROSS_COMPILE)nm 39 | OC := $(CROSS_COMPILE)objcopy 40 | OD := $(CROSS_COMPILE)objdump 41 | RM := rm -rf 42 | CP := cp -f 43 | 44 | ELF ?= $(basename $(firstword $(C_SRC))).axf 45 | OBJ := $(patsubst %.c,%.o,$(C_SRC)) 46 | #BIN = $(basename $(firstword $(C_SRC))).bin 47 | BIN = baremetalapp.bin 48 | 49 | .PHONY: all 50 | all: $(BIN) 51 | 52 | .PHONY: clean 53 | clean: 54 | $(RM) $(ELF) $(OBJ) $(BIN) 55 | $(RM) *.map 56 | $(RM) *.objdump 57 | 58 | %.c: $(HWLIBS_ROOT)/src/hwmgr/%.c 59 | $(CP) $< $@ 60 | 61 | $(OBJ): %.o: %.c Makefile 62 | $(CC) $(CFLAGS) -c $< -o $@ 63 | 64 | $(ELF): $(OBJ) 65 | $(LD) $(LDFLAGS) $(OBJ) -o $@ 66 | $(NM) $@ > $@.map 67 | $(OD) -d $@ > $@.objdump 68 | 69 | $(BIN): $(ELF) 70 | $(OC) -O binary $(ELF) $(BIN) 71 | $(MKI) -A arm -O u-boot -T standalone -C none -a 0x00100040 -e 0x00100040 -n "baremetalapp" -d $(BIN) $(BIN).img 72 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/README.md: -------------------------------------------------------------------------------- 1 | DMA_transfer_FPGA_DMAC 2 | ====================== 3 | 4 | Description 5 | ----------- 6 | This is a simple example showing how to use a DMA in the FPGA. It is intended to be used with the hardware project [DMA_FPGA](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC/FPGA_DMA). The component for doing DMA is the basic (non scatter-gather) DMA Controller available in Qsys. 7 | 8 | In this particular example the DMA controller reads a buffer in processor memory and copies to a FPGA On-Chip RAM (FPGA-OCR) using the FPGA-to-HPS port. Since the FPGA-to-HPS port access L3, FPGA has access to ACP and L3-SDRAMC port, so coherent access to cache and SDRAM access can be performed. In this example 9 | this can be controlled with a macro. 10 | 11 | At hardware level the DMAC controller should be connected to HPS using the read port and to FPGA-OCR using the write port, so data can flow in the intended direction. This DMA component is not bidirectional and there are write and read ports with fixed functionality. Using a macro it is possible in this example to change the direction of the transfer and write into HPS memories the data from the FPGA-OCR. In this case the hardware project must be modified to connect the read port of the DMA controller to the FPGA-OCR and the write port to the HPS. 12 | 13 | The macros to control the behaviour of the example: 14 | 15 | * SWITCH_ON_CACHE: if it is defined the cache is enabled and the DMAC accesses the buffer in processor memory through ACP port. Access is coherent to cache. If it is not defined the cache is disabled and access is through L3-SDRAMC port. Notice that the combination of cache enablement and port selected ensures coherency of data without cache flushing. In the case of having the cache switched on and FPGA writing to L3-SDRAM port the processor may read data in cache instead the last version living in SDRAM only. In this case processor should flush the cache before reading this data. If the operation is reading the processor should flush cache after writing data to memory so the FPGA reads the latest version of it. 16 | 17 | * DMA_TRANSFER_SIZE: size of the transfer in Bytes. 18 | 19 | * WRITE_OPERATION: if defined it means that a write operation takes place 20 | (read FPGA-OCR and write the HPS memories). If not defined (default), 21 | the read operation is done. 22 | 23 | Contents in the folder 24 | ---------------------- 25 | This example was programmed modifying the "HPS DMA Example" from Altera (File name: Altera-SoCFPGA-HardwareLib-DMA-CV-GNU.tar). 26 | * dma_demo.c: The main() function is in dma_demo.c file. 27 | * fpga_dma_api.c and fpga_dma_api.h: contain macros and functions to ease programming of the DMA Controller in the FPGA. 28 | * arm_cache_modified.c and arm_cache_modified.h: cache control functions. Original Legup functions were defined in arm_cache.c and arm_cache.h. Slight changes were done in arm_cache.c. Thats why the files arm_cache_modified.h and arm_cache_modified.c were created. The modifications are only in arm_cache.c: 29 | * L1_NORMAL_111_11 constant was changed from its original value 0x00007c0e to 0x00017c0e. This change sets S bit in table descriptors definyng normal memory region attributes, making normal memory shareable (coherent) for ACP accesses. 30 | 31 | * The io.c file gives support to the printf function to print messages in console. 32 | 33 | * The rest of the .c files were directly copied from hwlib without modifications. 34 | 35 | * cycloneV-dk-ram-modified.ld: describes the memory regions (stack, heap, etc.). 36 | 37 | * Makefile: describes compilation process. 38 | 39 | Compilation 40 | ----------- 41 | Open SoC EDS Command Shell, navigate to the folder of the example and type make. 42 | This programs was tested with Altera SoC EDS v16.1 43 | The compilation process generates two files: 44 | * baremetalapp.bin: to load the baremetal program from u-boot 45 | * baremetalapp.bin.img: to load the baremetal program from preloader 46 | 47 | How to test 48 | ----------- 49 | In the following folder there is an example on how to run baremetal examples available in this repository: 50 | [https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-baremetal](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-baremetal). 51 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/arm_cache_modified.h: -------------------------------------------------------------------------------- 1 | // 2 | // arm_cache.h 3 | // 4 | // header file for assembly functions to initialize and enable various cache 5 | // functionality 6 | // 7 | 8 | 9 | #ifndef _ARM_CACHE_H_ 10 | #define _ARM_CACHE_H_ 11 | 12 | 13 | // Initialize and enable all caches, and turn on useful optimizations 14 | // This is equivalent to calling the following functions: 15 | // * enable_MMU() 16 | // * initialize_L2C() 17 | // * enable_L1_D_side_prefetch() 18 | // * enable_L2_hint() 19 | // * enable_SCU() 20 | // * enable_caches() 21 | void enable_all_caches(void); 22 | 23 | // Enable the Memory Management Unit 24 | // This involves: 25 | // * turning off branch prediction, I cache, and D cache 26 | // * invalidating I- and D-, and unified TLBs 27 | // * invalidating L1 I and D caches 28 | // * clearing the branch predictor array 29 | // * generating the translation tables (only L1 currently) 30 | // * setting the TTBCR and TTBR0 registers for the translation table 31 | // * setting domain access control 32 | // * enabling the MMU 33 | // Note: All caches and branch prediction will be off after calling enable_MMU() 34 | void enable_MMU(void); 35 | 36 | // Initialize the L2 cache controller (ARM L2C-310) 37 | void initialize_L2C(void); 38 | 39 | // Enable L1 D-Side Prefetch 40 | void enable_L1_D_side_prefetch(void); 41 | 42 | // Enables exclusive caching, where data is only in the L1 or L2 cache, 43 | // but never both 44 | // Note: This enables the L2 cache controller 45 | void enable_exclusive_caching(void); 46 | 47 | // Enables the Snoop Control Unit 48 | void enable_SCU(void); 49 | 50 | // Enable the L1 data cache 51 | // Note: the MMU must be turned on first 52 | void enable_L1_D(void); 53 | 54 | // Enable the L1 instruction cache 55 | void enable_L1_I(void); 56 | 57 | // Enable branch prediction 58 | void enable_branch_prediction(void); 59 | 60 | // Enable the L2 cache 61 | // Note: initialize_L2C() must be called first to initialize the L2 cache controller 62 | void enable_L2(void); 63 | 64 | // Enable L1 D cache, L1 I cache, L2 cache, and branch prediction. 65 | // Equivalent to calling enable_L1_D(), enable_L1_I(), enable_branch_predition() 66 | // and enable_L2() 67 | void enable_caches(void); 68 | 69 | // invalidate and flush L1 caches and branch predictor 70 | // TODO: Invalidate L2 as well 71 | void invalidate_and_flush(void); 72 | 73 | /////////////////////////////////////// 74 | // L2C-310 + Cortex A9 Optimizations // 75 | /////////////////////////////////////// 76 | 77 | // Enable Early BRESP in L2C-310 78 | // See section 2.5.5 of L2 Cache Controller L2C-310 TRM 79 | void enable_early_BRESP(void); 80 | 81 | // Enable sending hints to the L2 cache 82 | void enable_L2_prefetch_hint(void); 83 | 84 | // Enable writing a full line of zeros 85 | // Note: This operation turns on the L2 cache controller 86 | // See section 2.5.5 of L2 Cache Controller L2C-310 TRM 87 | void enable_write_full_line_zeros(void); 88 | 89 | // Enable speculative linefills of the L2 cache 90 | // Note: enable_SCU() must be called first 91 | void enable_L2_speculative_linefill(void); 92 | 93 | // Enable Store Buffer Device Limitation in L2C-310 94 | // See section 2.5.5 of L2 Cache Controller L2C-310 TRM 95 | void enable_store_buffer_device_limitation(void); 96 | 97 | #endif 98 | 99 | 100 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/debug-hosted.ds: -------------------------------------------------------------------------------- 1 | # 2 | # Reset and stop the system. 3 | # 4 | reset system 5 | stop 6 | wait 30s 7 | 8 | # 9 | # Disable semihosting. 10 | # 11 | set semihosting enabled false 12 | 13 | 14 | # 15 | # Load the SPL preloader into memory. 16 | # 17 | loadfile "$sdir/u-boot-spl.axf" 0x0 18 | 19 | # 20 | # Enable semihosting. 21 | # 22 | set semihosting enabled true 23 | 24 | # 25 | # Delete any existing breakpoints. 26 | # 27 | delete 28 | 29 | # 30 | # Set a breakpoint in the SPL function spl_boot_device(). This function is 31 | # called right before the SPL tries to load the next stage in the preloader. 32 | # 33 | tbreak spl_boot_device 34 | 35 | # 36 | # Set the PC to the entry point and go. 37 | # 38 | run 39 | 40 | # 41 | # Wait for the breakpoint. 42 | # 43 | wait 44 | 45 | # 46 | # Load the demo program. 47 | # 48 | loadfile "$sdir/dma_demo.axf" 0x0 49 | 50 | # 51 | # Run the target and break at main(). 52 | # 53 | start 54 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/fpga_dmac_api.c: -------------------------------------------------------------------------------- 1 | //API for the Qsys DMA Controller 2 | #include "fpga_dmac_api.h" 3 | 4 | //-----------------Generic functions--------------------// 5 | //(Addresses are multiplied by 4 because the peripheral has 32-bit (4byte) regs 6 | uint32_t fpga_dma_read_reg(void* addr, uint32_t reg) 7 | { 8 | return *((uint32_t*) (addr + 4*reg)); 9 | } 10 | 11 | void fpga_dma_write_reg(void* addr, uint32_t reg, uint32_t val) 12 | { 13 | *((uint32_t*) (addr + 4*reg)) = val; 14 | } 15 | 16 | uint32_t fpga_dma_read_bit(void* addr, uint32_t reg, uint32_t bit) 17 | { 18 | return (bit & fpga_dma_read_reg(addr, reg)); 19 | } 20 | 21 | void fpga_dma_write_bit(void* addr, uint32_t reg, uint32_t bit, uint32_t val) 22 | { 23 | uint32_t old = fpga_dma_read_reg(addr, reg); 24 | if(val == 0) 25 | { 26 | fpga_dma_write_reg(addr, reg, (old & (~bit))); 27 | } 28 | else if(val == 1) 29 | { 30 | fpga_dma_write_reg(addr, reg, (old | bit)); 31 | } 32 | return; 33 | } 34 | 35 | //------------Some specific functions-------------------// 36 | void fpga_dma_init(void* addr, uint32_t control_reg_val) 37 | { 38 | fpga_dma_write_reg( addr, FPGA_DMA_CONTROL, control_reg_val); 39 | } 40 | 41 | void fpga_dma_config_transfer(void* addr, void* src, void* dst, unsigned int size) 42 | { 43 | fpga_dma_write_bit( addr,//clean go bit 44 | FPGA_DMA_CONTROL, 45 | FPGA_DMA_GO, 46 | 0); 47 | fpga_dma_write_bit( addr, //clean the done bit 48 | FPGA_DMA_STATUS, 49 | FPGA_DMA_DONE, 50 | 0); 51 | fpga_dma_write_reg( addr, //set source address 52 | FPGA_DMA_READADDRESS, 53 | (uint32_t) src); 54 | fpga_dma_write_reg( addr, //set destiny address 55 | FPGA_DMA_WRITEADDRESS, 56 | (uint32_t) dst); 57 | fpga_dma_write_reg( addr, //set transfer size 58 | FPGA_DMA_LENGTH, 59 | (uint32_t) size); 60 | //Wait a small time. Needed for the read from HPS to work. 61 | int counter=0; 62 | for(int j=0; j<10; j++) counter++; 63 | } 64 | 65 | void fpga_dma_start_transfer(void* addr) 66 | { 67 | fpga_dma_write_bit( addr, 68 | FPGA_DMA_CONTROL, 69 | FPGA_DMA_GO, 70 | 1);//start transfer 71 | } 72 | 73 | //this function returns a 1 if the DMA transfer is finished, 0 otherwise 74 | uint32_t fpga_dma_transfer_done(void* addr) 75 | { 76 | return fpga_dma_read_bit(addr, FPGA_DMA_STATUS, FPGA_DMA_DONE); 77 | } 78 | 79 | //alligned allocation to the transfer size is needed for reading HPS from FPGA 80 | 81 | void* align_malloc (size_t size, void** unaligned_addr) 82 | { 83 | char* Buffer_8 = (char*) malloc(size*2); 84 | *unaligned_addr = (void*) Buffer_8; 85 | uint8_t* Buffer_8_ptr; 86 | Buffer_8_ptr = (uint8_t*)Buffer_8; 87 | for(int k=0; k<(size); k++) 88 | { 89 | if ((((unsigned long int)Buffer_8_ptr) % ((unsigned long int)size))==0) 90 | { 91 | return (void*)Buffer_8_ptr; 92 | } 93 | else 94 | { 95 | Buffer_8_ptr++; 96 | } 97 | } 98 | return 0; 99 | } 100 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/fpga_dmac_api.h: -------------------------------------------------------------------------------- 1 | //API for the Qsys DMA Controller 2 | 3 | #ifndef __FPGA_DMAC_API__ 4 | #define __FPGA_DMAC_API__ 5 | 6 | #include 7 | #include 8 | 9 | //REGISTER MAP 10 | #define FPGA_DMA_STATUS 0 11 | #define FPGA_DMA_READADDRESS 1 12 | #define FPGA_DMA_WRITEADDRESS 2 13 | #define FPGA_DMA_LENGTH 3 14 | //RESERVED 4 15 | //RESERVED 5 16 | #define FPGA_DMA_CONTROL 6 17 | //RESERVED 7 18 | 19 | //MACROS to more easily read the control status register bits 20 | #define FPGA_DMA_DONE 0b00001 //DONE 21 | #define FPGA_DMA_BUSY 0b00010 //BUSY 22 | #define FPGA_DMA_REOP 0b00100 //REOP 23 | #define FPGA_DMA_WEOP 0b01000 //WEOP 24 | #define FPGA_DMA_LEN 0b10000 //LEN 25 | 26 | //MACROS to more easily program the control register 27 | #define FPGA_DMA_BYTE_TRANSFERS 0b0000000000001 //BYTE 28 | #define FPGA_DMA_HALFWORD_TRANSFERS 0b0000000000010 //HW 29 | #define FPGA_DMA_WORD_TRANSFERS 0b0000000000100 //WORD 30 | #define FPGA_DMA_GO 0b0000000001000 //GO 31 | #define FPGA_DMA_INTERRUPT_ENABLE 0b0000000010000 //I_EN 32 | #define FPGA_DMA_END_RD_END_OF_PACKET 0b0000000100000 //REEN 33 | #define FPGA_DMA_END_WR_END_OF_PACKET 0b0000001000000 //WEEN 34 | #define FPGA_DMA_END_WHEN_LENGHT_ZERO 0b0000010000000 //LEEN 35 | #define FPGA_DMA_READ_CONSTANT_ADDR 0b0000100000000 //RCON 36 | #define FPGA_DMA_WRITE_CONSTANT_ADDR 0b0001000000000 //WCON 37 | #define FPGA_DMA_DOUBLEWORD_TRANSFERS 0b0010000000000 //DOUBLEWORD 38 | #define FPGA_DMA_QUADWORD_TRANSFERS 0b0100000000000 //QUADWORD 39 | #define FPGA_DMA_SOFTWARE_RESET 0b1000000000000 //SOFTWARE_RESET 40 | 41 | //-----------------Generic functions--------------------// 42 | uint32_t fpga_dma_read_reg(void* addr, uint32_t reg); 43 | void fpga_dma_write_reg(void* addr, uint32_t reg, uint32_t val); 44 | uint32_t fpga_dma_read_bit(void* addr, uint32_t reg, uint32_t bit); 45 | void fpga_dma_write_bit(void* addr, uint32_t reg, uint32_t bit, uint32_t val); 46 | 47 | //------------Some specific functions-------------------// 48 | void fpga_dma_init(); 49 | void fpga_dma_config_transfer(void* addr, void* src, void* dst, unsigned int size); 50 | void fpga_dma_start_transfer(void* addr); 51 | uint32_t fpga_dma_transfer_done(void* addr); 52 | void* align_malloc (size_t size, void** unaligned_addr); 53 | 54 | #endif // __FPGA_DMAC_API__ 55 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_FPGA_DMAC/io.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2014 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. The name of the author may not be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO 21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 27 | * OF SUCH DAMAGE. 28 | * 29 | ******************************************************************************/ 30 | 31 | /* 32 | * This file contains minimal IO support to make printf work over UART 33 | * The code relies on the Preloader to set the UART module including baud rate 34 | */ 35 | 36 | #include 37 | #include 38 | 39 | #include "socal/alt_uart.h" 40 | #include "socal/hps.h" 41 | #include "socal/socal.h" 42 | 43 | #define STDOUT_FILENO 1 44 | 45 | int _close(int file) 46 | { 47 | /* Succeeds only for STDOUT */ 48 | return (file == STDOUT_FILENO) ? 0 : -1; 49 | } 50 | 51 | int _fstat(int file, void *st) 52 | { 53 | /* Succeeds only for STDOUT */ 54 | return (file == STDOUT_FILENO) ? 0 : -1; 55 | } 56 | 57 | int _isatty(int file) 58 | { 59 | /* Succeeds only for STDOUT */ 60 | return (file == STDOUT_FILENO) ? 1 : -1; 61 | } 62 | 63 | off_t _lseek(int file, off_t ptr, int dir) 64 | { 65 | /* Succeeds only for STDOUT */ 66 | return (file == STDOUT_FILENO) ? 0 : -1; 67 | } 68 | 69 | int _read(int file, void *ptr, size_t len) 70 | { 71 | /* Always fails */ 72 | return -1; 73 | } 74 | 75 | int _write(int file, char * ptr, unsigned len, int flag ) 76 | { 77 | /* Fails if not STDOUT */ 78 | if(file != STDOUT_FILENO) 79 | { 80 | return -1; 81 | } 82 | 83 | /* Print each character to UART */ 84 | for(int i=0; i $@.map 67 | $(OD) -d $@ > $@.objdump 68 | 69 | $(BIN): $(ELF) 70 | $(OC) -O binary $(ELF) $(BIN) 71 | $(MKI) -A arm -O u-boot -T standalone -C none -a 0x00100040 -e 0x00100040 -n "baremetalapp" -d $(BIN) $(BIN).img 72 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_PL330_ACP/README.md: -------------------------------------------------------------------------------- 1 | DMA_transfer_PL330_ACP 2 | ====================== 3 | 4 | Description 5 | ----------- 6 | This is a complete example on moving data using the HPS Direct Memory Access Controller (DMAC) PL330. This example also shows how to switch on the cache memories L1 and L2 and how to configure the ACP port to access cache memories from L3. 7 | 8 | This example moves data between a source buffer in processor´s memory to a destiny buffer in processor´s memory or in the FPGA: 9 | * When the macro USE_FPGA is not defined the destiny is in processors memory. 10 | * When the macro USE_FPGA is defined the destiny is a buffer in the FPGA in the address 0xC0000000, the beginning of the HPS-FPGA bridge. Therefore when selecting this option there should be a memory in the FPGA with enough space to do the transfer in address 0 of that bridge. In the folder [https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/FPGA_OCR_256K](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/FPGA_OCR_256K) you can find a hardware project implementing a 256KB On-Chip RAM memory in the FPGA for this purpose. 11 | 12 | To control the cache behaviour there is the macro SWITCH_ON_CACHE. 13 | * When SWITCH_ON_CACHE is not defined the cache system L1 and L2 are switched off. In this case the DMAC accesses the processor RAM using the direct conection between L3 interconnect and SDRAM controller. You can modify transfer pointers to access processor memories through ACP but this is slower because ACP will access L2 cache controller and L2 cache controller will finally access RAM to get the data because cache is off. So direct access to RAM is faster in this case. 14 | * When SWITCH_ON_CACHE is defined the cache L1 and L2 are switched on with optimizations using functions devekloped by Legup([http://legup.eecg.utoronto.ca/wiki/doku.php?id=using_arm_caches](http://legup.eecg.utoronto.ca/wiki/doku.php?id=using_arm_caches)). In this case the DMAC accesses the processor cached memory in a coherent way using the ACP. This is very much faster than when the cache is off because: a) the processor instructions are cached and the preparation of DMAC program is executed faster, b) the data is in cache that is faster than RAM. 15 | However for big buffers (more or less for sizes bigger than cache size) this strategy could be counterproductive because the DMA will be writing/reading cache through APC but data is not there so L2 controller will need to access external RAM anyway. In this case (not treated in this example) it is better to directly access to external RAM through the RAM Controller (like when cache is OFF). In this case, to maintain the coherency of the data the programmer should flush the cache after the transfer (when writing to the processor´s RAM) or before the transfer (when readingfrom processor´s RAM). 16 | 17 | 18 | Contents in the folder 19 | ---------------------- 20 | This example was programmed modifying the "HPS DMA Example" from Altera (File name: Altera-SoCFPGA-HardwareLib-DMA-CV-GNU.tar). 21 | * The main() function is in dma_demo.c file. 22 | * arm_cache_modified.c and arm_cache_modified.h: cache control functions. Original Legup functions were defined in arm_cache.c and arm_cache.h. Slight changes were done in arm_cache.c. Thats why the files arm_cache_modified.h and arm_cache_modified.c were created. The modifications are only in arm_cache.c: 23 | * L1_NORMAL_111_11 constant was changed from its original value 0x00007c0e to 0x00017c0e. This change sets S bit in table descriptors definyng normal memory region attributes, making normal memory shareable (coherent) for ACP accesses. 24 | 25 | * alt_dma_modified.c and alt_dma_modified.h describe the DMAC control functions. The original alt_dma.c from hwlib was modified. The changes are: 26 | * ALT_DMA_CCR_OPT_SC_DEFAULT was changed by ALT_DMA_RC_ON = 0x00003800 in alt_dma.c. ALT_DMA_CCR_OPT_DC_DEFAULT was changed by ALT_DMA_WC_ON = 0x0E000000. These changes make the channel 0 of the DMAC to do cacheable access with its AXI master port. 27 | * Other change is the split of alt_dma_memory_to_memory() into 2 functions: alt_dma_memory_to_memory_only_prepare_program() and alt_dma_channel_exec(). This way the program preparation and its execution can be run separately. The program can be prepared during initializations only once calling alt_dma_memory_to_memory_only_prepare_program() and transfers performed with alt_dma_channel_exec() passing the prepared program as argument. This transfer will be faster cause the instructions the processor executes to prepare the DMAC program are not executed. 28 | 29 | * The io.c file gives support to the printf function to print messages in console. 30 | 31 | * The rest of the .c files were directly copied from hwlib without modifications. 32 | 33 | * cycloneV-dk-ram-modified.ld: describes the memory regions (stack, heap, etc.). 34 | 35 | * Makefile: describes compilation process. 36 | 37 | Compilation 38 | ----------- 39 | Open SoC EDS Command Shell, navigate to the folder of the example and type make. 40 | This programs was tested with Altera SoC EDS v16.1 41 | The compilation process generates two files: 42 | * baremetalapp.bin: to load the baremetal program from u-boot 43 | * baremetalapp.bin.img: to load the baremetal program from preloader 44 | 45 | How to test 46 | ----------- 47 | In the following folder there is an example on how to run baremetal examples available in this repository: 48 | [https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-baremetal](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-baremetal). 49 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_PL330_ACP/arm_cache_modified.h: -------------------------------------------------------------------------------- 1 | // 2 | // arm_cache.h 3 | // 4 | // header file for assembly functions to initialize and enable various cache 5 | // functionality 6 | // 7 | 8 | 9 | #ifndef _ARM_CACHE_H_ 10 | #define _ARM_CACHE_H_ 11 | 12 | 13 | // Initialize and enable all caches, and turn on useful optimizations 14 | // This is equivalent to calling the following functions: 15 | // * enable_MMU() 16 | // * initialize_L2C() 17 | // * enable_L1_D_side_prefetch() 18 | // * enable_L2_hint() 19 | // * enable_SCU() 20 | // * enable_caches() 21 | void enable_all_caches(void); 22 | 23 | // Enable the Memory Management Unit 24 | // This involves: 25 | // * turning off branch prediction, I cache, and D cache 26 | // * invalidating I- and D-, and unified TLBs 27 | // * invalidating L1 I and D caches 28 | // * clearing the branch predictor array 29 | // * generating the translation tables (only L1 currently) 30 | // * setting the TTBCR and TTBR0 registers for the translation table 31 | // * setting domain access control 32 | // * enabling the MMU 33 | // Note: All caches and branch prediction will be off after calling enable_MMU() 34 | void enable_MMU(void); 35 | 36 | // Initialize the L2 cache controller (ARM L2C-310) 37 | void initialize_L2C(void); 38 | 39 | // Enable L1 D-Side Prefetch 40 | void enable_L1_D_side_prefetch(void); 41 | 42 | // Enables exclusive caching, where data is only in the L1 or L2 cache, 43 | // but never both 44 | // Note: This enables the L2 cache controller 45 | void enable_exclusive_caching(void); 46 | 47 | // Enables the Snoop Control Unit 48 | void enable_SCU(void); 49 | 50 | // Enable the L1 data cache 51 | // Note: the MMU must be turned on first 52 | void enable_L1_D(void); 53 | 54 | // Enable the L1 instruction cache 55 | void enable_L1_I(void); 56 | 57 | // Enable branch prediction 58 | void enable_branch_prediction(void); 59 | 60 | // Enable the L2 cache 61 | // Note: initialize_L2C() must be called first to initialize the L2 cache controller 62 | void enable_L2(void); 63 | 64 | // Enable L1 D cache, L1 I cache, L2 cache, and branch prediction. 65 | // Equivalent to calling enable_L1_D(), enable_L1_I(), enable_branch_predition() 66 | // and enable_L2() 67 | void enable_caches(void); 68 | 69 | // invalidate and flush L1 caches and branch predictor 70 | // TODO: Invalidate L2 as well 71 | void invalidate_and_flush(void); 72 | 73 | /////////////////////////////////////// 74 | // L2C-310 + Cortex A9 Optimizations // 75 | /////////////////////////////////////// 76 | 77 | // Enable Early BRESP in L2C-310 78 | // See section 2.5.5 of L2 Cache Controller L2C-310 TRM 79 | void enable_early_BRESP(void); 80 | 81 | // Enable sending hints to the L2 cache 82 | void enable_L2_prefetch_hint(void); 83 | 84 | // Enable writing a full line of zeros 85 | // Note: This operation turns on the L2 cache controller 86 | // See section 2.5.5 of L2 Cache Controller L2C-310 TRM 87 | void enable_write_full_line_zeros(void); 88 | 89 | // Enable speculative linefills of the L2 cache 90 | // Note: enable_SCU() must be called first 91 | void enable_L2_speculative_linefill(void); 92 | 93 | // Enable Store Buffer Device Limitation in L2C-310 94 | // See section 2.5.5 of L2 Cache Controller L2C-310 TRM 95 | void enable_store_buffer_device_limitation(void); 96 | 97 | #endif 98 | 99 | 100 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_PL330_ACP/debug-hosted.ds: -------------------------------------------------------------------------------- 1 | # 2 | # Reset and stop the system. 3 | # 4 | reset system 5 | stop 6 | wait 30s 7 | 8 | # 9 | # Disable semihosting. 10 | # 11 | set semihosting enabled false 12 | 13 | 14 | # 15 | # Load the SPL preloader into memory. 16 | # 17 | loadfile "$sdir/u-boot-spl.axf" 0x0 18 | 19 | # 20 | # Enable semihosting. 21 | # 22 | set semihosting enabled true 23 | 24 | # 25 | # Delete any existing breakpoints. 26 | # 27 | delete 28 | 29 | # 30 | # Set a breakpoint in the SPL function spl_boot_device(). This function is 31 | # called right before the SPL tries to load the next stage in the preloader. 32 | # 33 | tbreak spl_boot_device 34 | 35 | # 36 | # Set the PC to the entry point and go. 37 | # 38 | run 39 | 40 | # 41 | # Wait for the breakpoint. 42 | # 43 | wait 44 | 45 | # 46 | # Load the demo program. 47 | # 48 | loadfile "$sdir/dma_demo.axf" 0x0 49 | 50 | # 51 | # Run the target and break at main(). 52 | # 53 | start 54 | -------------------------------------------------------------------------------- /Baremetal-applications/DMA_transfer_PL330_ACP/io.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2014 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. The name of the author may not be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO 21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 27 | * OF SUCH DAMAGE. 28 | * 29 | ******************************************************************************/ 30 | 31 | /* 32 | * This file contains minimal IO support to make printf work over UART 33 | * The code relies on the Preloader to set the UART module including baud rate 34 | */ 35 | 36 | #include 37 | #include 38 | 39 | #include "socal/alt_uart.h" 40 | #include "socal/hps.h" 41 | #include "socal/socal.h" 42 | 43 | #define STDOUT_FILENO 1 44 | 45 | int _close(int file) 46 | { 47 | /* Succeeds only for STDOUT */ 48 | return (file == STDOUT_FILENO) ? 0 : -1; 49 | } 50 | 51 | int _fstat(int file, void *st) 52 | { 53 | /* Succeeds only for STDOUT */ 54 | return (file == STDOUT_FILENO) ? 0 : -1; 55 | } 56 | 57 | int _isatty(int file) 58 | { 59 | /* Succeeds only for STDOUT */ 60 | return (file == STDOUT_FILENO) ? 1 : -1; 61 | } 62 | 63 | off_t _lseek(int file, off_t ptr, int dir) 64 | { 65 | /* Succeeds only for STDOUT */ 66 | return (file == STDOUT_FILENO) ? 0 : -1; 67 | } 68 | 69 | int _read(int file, void *ptr, size_t len) 70 | { 71 | /* Always fails */ 72 | return -1; 73 | } 74 | 75 | int _write(int file, char * ptr, unsigned len, int flag ) 76 | { 77 | /* Fails if not STDOUT */ 78 | if(file != STDOUT_FILENO) 79 | { 80 | return -1; 81 | } 82 | 83 | /* Print each character to UART */ 84 | for(int i=0; i $@.map 67 | $(OD) -d $@ > $@.objdump 68 | 69 | $(BIN): $(ELF) 70 | $(OC) -O binary $(ELF) $(BIN) 71 | $(MKI) -A arm -O u-boot -T standalone -C none -a 0x00100040 -e 0x00100040 -n "baremetalapp" -d $(BIN) $(BIN).img 72 | 73 | -------------------------------------------------------------------------------- /Baremetal-applications/Second_counter_PMU/README.md: -------------------------------------------------------------------------------- 1 | Second_counter_PMU 2 | ================== 3 | 4 | Description 5 | ----------- 6 | This example uses a counter in the Performance Monitoring Unit (PMU) timer to measure seconds and build a second counter. It prints the a number each second through the serial console. After 60 seconds the application finishes. 7 | 8 | PMU is a coprocessor located very close to the processor in ARM Cortex-A9. It is in charge of gathering statistics from the processor, i.e. the number of exceptions, divisions by 0, etc. Each processor core has its own PMU. In case of Cyclone V the processor has two cores and therefore two PMUs. PMU is not mapped in the address space of the processor. It is accessed through instructions like the Neon coprocessors. 9 | 10 | The PMU has a CPU clock cycle counter that can be used to measure time. To measure time with PMU is not a good practice because PMU counts cycles from CPU clock, not time. Therefore if the clock rate of the CPU changes (i.e. it is reduced to save energy) the time measurement will be wrong. The advantage of using the PMU is that it measures time very precisely. Therefore if clock rate is stable and we know its rate we can measure time very precisely with it. 11 | In the case of the hardware project used to test this application (https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/FPGA_OCR_256K) we set the processors frequency to 800MHz in Qsys and we do not modify it during the program execution so we can safely measure time. 12 | 13 | This example can be seen as an example on how to access and control PMU and, because it counts seconds, it can be used to test that the frequency of 14 | the processor defined in Qsys is correct and that we can do time measurements with the settings of the PMU used. 15 | 16 | When using Operating System the same code could be used to do a second counter. In that case https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/Enable_PMU_user_space should be inserted first so the application has access to PMU from user space. Be aware that if the module enabling PMU is launched in one processor and the application to count seconds is launched in the other the application will not have access to the PMU because the PMU where the module was running was the only PMU activated. 17 | 18 | Contents in the folder 19 | ---------------------- 20 | * main.c: entry point of the program. Initializes 21 | * io.c: gives support to printf so characters can be sent over UART. 22 | * pmu.c and pmu.h: functions to control the PMU timer. 23 | * alt_types.h file copied from hwlib. 24 | * cycloneV-dk-ram-modified.ld: describes the memory regions (stack, heap, etc.). 25 | * Makefile: describes compilation process. 26 | 27 | Compilation 28 | ----------- 29 | Open SoC EDS Command Shell, navigate to the folder of the example and type make. 30 | This programs was tested with Altera SoC EDS v16.1 31 | The compilation process generates two files: 32 | * baremetalapp.bin: to load the baremetal program from u-boot 33 | * baremetalapp.bin.img: to load the baremetal program from preloader 34 | 35 | How to test 36 | ----------- 37 | In the following folder there is an example on how to run baremetal examples available in this repository: 38 | (https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-baremetal. -------------------------------------------------------------------------------- /Baremetal-applications/Second_counter_PMU/alt_types.h: -------------------------------------------------------------------------------- 1 | #ifndef __ALT_TYPES_H__ 2 | #define __ALT_TYPES_H__ 3 | 4 | /****************************************************************************** 5 | * * 6 | * License Agreement * 7 | * * 8 | * Copyright (c) 2003 Altera Corporation, San Jose, California, USA. * 9 | * All rights reserved. * 10 | * * 11 | * Permission is hereby granted, free of charge, to any person obtaining a * 12 | * copy of this software and associated documentation files (the "Software"), * 13 | * to deal in the Software without restriction, including without limitation * 14 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, * 15 | * and/or sell copies of the Software, and to permit persons to whom the * 16 | * Software is furnished to do so, subject to the following conditions: * 17 | * * 18 | * The above copyright notice and this permission notice shall be included in * 19 | * all copies or substantial portions of the Software. * 20 | * * 21 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * 22 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * 23 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * 24 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * 25 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * 26 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * 27 | * DEALINGS IN THE SOFTWARE. * 28 | * * 29 | * This agreement shall be governed in all respects by the laws of the State * 30 | * of California and by the laws of the United States of America. * 31 | * * 32 | * Altera does not recommend, suggest or require that this reference design * 33 | * file be used in conjunction or combination with any other product. * 34 | ******************************************************************************/ 35 | 36 | /* 37 | * Don't declare these typedefs if this file is included by assembly source. 38 | */ 39 | #ifndef ALT_ASM_SRC 40 | typedef signed char alt_8; 41 | typedef unsigned char alt_u8; 42 | typedef signed short alt_16; 43 | typedef unsigned short alt_u16; 44 | typedef signed long alt_32; 45 | typedef unsigned long alt_u32; 46 | typedef long long alt_64; 47 | typedef unsigned long long alt_u64; 48 | #endif 49 | 50 | #define ALT_INLINE __inline__ 51 | #define ALT_ALWAYS_INLINE __attribute__ ((always_inline)) 52 | #define ALT_WEAK __attribute__((weak)) 53 | 54 | #endif /* __ALT_TYPES_H__ */ 55 | -------------------------------------------------------------------------------- /Baremetal-applications/Second_counter_PMU/io.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2014 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. The name of the author may not be used to endorse or promote products 16 | * derived from this software without specific prior written permission. 17 | * 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR 19 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 20 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO 21 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 22 | * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT 23 | * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 26 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 27 | * OF SUCH DAMAGE. 28 | * 29 | ******************************************************************************/ 30 | 31 | /* 32 | * This file contains minimal IO support to make printf work over UART 33 | * The code relies on the Preloader to set the UART module including baud rate 34 | */ 35 | 36 | #include 37 | #include 38 | 39 | #include "socal/alt_uart.h" 40 | #include "socal/hps.h" 41 | #include "socal/socal.h" 42 | 43 | #define STDOUT_FILENO 1 44 | 45 | int _close(int file) 46 | { 47 | /* Succeeds only for STDOUT */ 48 | return (file == STDOUT_FILENO) ? 0 : -1; 49 | } 50 | 51 | int _fstat(int file, void *st) 52 | { 53 | /* Succeeds only for STDOUT */ 54 | return (file == STDOUT_FILENO) ? 0 : -1; 55 | } 56 | 57 | int _isatty(int file) 58 | { 59 | /* Succeeds only for STDOUT */ 60 | return (file == STDOUT_FILENO) ? 1 : -1; 61 | } 62 | 63 | off_t _lseek(int file, off_t ptr, int dir) 64 | { 65 | /* Succeeds only for STDOUT */ 66 | return (file == STDOUT_FILENO) ? 0 : -1; 67 | } 68 | 69 | int _read(int file, void *ptr, size_t len) 70 | { 71 | /* Always fails */ 72 | return -1; 73 | } 74 | 75 | int _write(int file, char * ptr, unsigned len, int flag ) 76 | { 77 | /* Fails if not STDOUT */ 78 | if(file != STDOUT_FILENO) 79 | { 80 | return -1; 81 | } 82 | 83 | /* Print each character to UART */ 84 | for(int i=0; i 12 | #include "pmu.h" 13 | 14 | int __auto_semihosting; 15 | 16 | int main(void) 17 | { 18 | printf("Hello World!!\r\n"); 19 | 20 | pmu_init_ns(800, 1); //Initialize PMU cycle counter, 800MHz source, frequency divider 1 21 | pmu_counter_enable();//Enable cycle counter inside PMU (it starts counting) 22 | float pmu_res = pmu_getres_ns(); 23 | printf("PMU is used like timer with the following characteristics\n\r"); 24 | printf("PMU cycle counter resolution is %f ns\n\r", pmu_res ); 25 | 26 | //Timing 60 seconds with PMU 27 | int seconds=0; 28 | unsigned long long pmu_counter_ns; 29 | 30 | pmu_counter_reset(); 31 | printf("%d\n\r",seconds); 32 | 33 | while (seconds<61) 34 | { 35 | pmu_counter_read_ns(&pmu_counter_ns); 36 | if(pmu_counter_ns>1000000000) 37 | { 38 | pmu_counter_reset(); 39 | seconds ++; 40 | printf("%d\n\r",seconds); 41 | } 42 | } 43 | 44 | printf("The end...\n\r"); 45 | return 0; 46 | } 47 | -------------------------------------------------------------------------------- /Baremetal-applications/Second_counter_PMU/pmu.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Baremetal-applications/Second_counter_PMU/pmu.c -------------------------------------------------------------------------------- /Baremetal-applications/Second_counter_PMU/pmu.h: -------------------------------------------------------------------------------- 1 | #ifndef __PMU_H 2 | #define __PMU_H 3 | 4 | #ifdef __cplusplus 5 | extern "C" { 6 | #endif 7 | 8 | 9 | /* Includes ---------------------------------------------*/ 10 | 11 | /* Exported types ---------------------------------------*/ 12 | 13 | /* Exported constants -----------------------------------*/ 14 | 15 | /* Exported macros --------------------------------------*/ 16 | 17 | /* Exported functions -----------------------------------*/ 18 | 19 | void extern pmu_init(void); 20 | 21 | void extern pmu_init_ns(int cpu_freq, int freq_div); 22 | 23 | float extern pmu_getres_ns(void); 24 | 25 | void extern pmu_counter_enable(void); 26 | 27 | void extern pmu_counter_disable(void); 28 | 29 | void extern pmu_counter_reset(void); 30 | 31 | int extern pmu_counter_read(unsigned int *counter_value); 32 | 33 | int extern pmu_counter_read_ns(unsigned long long int *value_ns); 34 | 35 | #ifdef __cplusplus 36 | } 37 | #endif 38 | 39 | #endif /* __PMU_H */ 40 | -------------------------------------------------------------------------------- /CycloneVSoC.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/CycloneVSoC.png -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/FPGA_DMA.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/FPGA-hardware/DE1-SoC/FPGA_DMA/FPGA_DMA.png -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/README.md: -------------------------------------------------------------------------------- 1 | FPGA_DMA 2 | =========== 3 | 4 | Description 5 | ------------ 6 | This project implements a double port On-Chip RAM (FPGA-OCR) and a DMA Controller Core (available in Qsys) controller in the FPGA. Its purpose is to test the DMA Controller in the FPGA and test writing/reading to HPS using the FPGA as master. The project comes with DMA Controller write port connected to FPGA-OCR and read port connected to HPS. Therefore data can be copied from HPS to the FPGA-OCR. If you want to move data in the oposite direction switch the connectiion of write and read port in DMA Controller (in Qsys). This project is a modification of the DE1-SoC Golden Hardware Reference Design (GHRD) available in the DE1-SoC CD-ROM documentation. 7 | 8 | The OCR configured in the FPGA has the following characteristics: 9 | 10 | * Implemented using embedded 10kB memory blocks. 11 | * Size = 1kB. 12 | * Data_size is 128bits. The bigger the data size the faster the data rates achieved so 128 bits is selected cause it is the maximum of the bridge where it is connected. 13 | * Double port. One port is connected to the HPS-to-FPGA bridge so the processor 14 | can access it. Its address relative to the HPS-to-FPGA bridge is 0x0 (0x00000000 in Qsys). The physical address to be used from processor is threfore the sum of the beginning of the HPS-to-FPGA bridge (0xC0000000) plus the Qsys address (0x0). The second port is connected to the write port of the DMA Controller core at address 0x0 too. 15 | 16 | The DMA Controller Core has the following characteristics: 17 | * The 32-bit control bridge is connected to the HPS-to-FPGA bridge at address 0x10000 so the processor can control it. Therefore the physical addresss of the component as seen by the processor is again the sum of the bridge address (0xC0000000) plus the DMA Controller address (0x10000) equal to 0xC0010000. 18 | * The Read master bus is configured 128-bit and connected to the second port of the FPGA-OCR. The Write master is connected to the FPGA-to-HPS bridge so it can write to all HPS addresses, including SDRAM-Controller, ACP and HPS On-Chip RAM (HPS-OCR). 19 | * Bursts are not enabled. 20 | * Max transfer size allowed 16MB. 21 | * FIFO depth 128 Bytes. 22 | 23 | There are some secondary components: 24 | * A PLL generates 100MHz frequency clock to be used in all components in the FPGA, including the FPGA side of the HPS-to-FPGA and FPGA-to-HPS bridge. Input frequency is 50MHz clock from external oscillator in the DE1-SoC board. 25 | * An AXI Conduit Merger. Since the DMA Controller is Avalon and the FPGA-to-HPS bridge is AXI, Qsys automatically performs a transformation. However the default values for some of the AXI signals that Qsys provides are not suitable for writing through ACP. Moreover it is desirable to change the values of this signals from processor to test which combination of signals is better. The AXI conduit merger allows AWCACHE, AWPROT, AWUSER, ARCACHE, ARPROT, ARUSER, to be controlled using Conduit signals. 26 | * A 32-bit GPIO to connect the Conduit signals of the AXI Conduit Merger to processor and be able to change this lines by program. 27 | 28 | It was found that the best combination of signals (do not fail and give higher speed) are: 29 | * GPIO[3-0] = AWCACHE = 0111 (Cacheable write-back, allocate reads only) 30 | * GPIO[6-4] = AWPROT = 000 (normal access, non-secure, data) 31 | * GPIO[11-7] = AWUSER = 00001 (Coherent access) 32 | * GPIOGPIO[19-16] = ARCACHE = 0111 33 | * GPIO[22-20] = ARPROT = 000 34 | * GPIO[27-23] = ARUSER = 00001 35 | 36 | The following drawing depicts the hardware just described: 37 | 38 |

39 | Cyclone V SoC with DMA in FPGA 40 |

41 | 42 | Compilation instructions 43 | -------------------------- 44 | This hardware project was tested on Quartus II and Altera SoC EDS v16.0 Update 2. To compile this project: 45 | 46 | * Open Quartus (v16.0 Update 2). **Open project > soc_system.qpf** 47 | * Open Qsys and **load soc_system.qsys** 48 | * On Qsys, Select **Generate > Generate HDL...** De-select “Create block symbol file” option and specify desired HDL language (VHDL our case). Press “Generate” button. 49 | * After generation ends, go to Quartus and press the **Start Analysis & Synthesis** button 50 | * When synthesis ends, go to **Tools > Tcl scripts...** and run the scripts hps_sdram_p0_parameters.tcl and hps_sdram_p0_pin_assignments.tcl. Wait for confirmation pop-up window. 51 | * Perform again the **Analysis & Synthesis** of the project 52 | * Run the **Fitter (Place & Route)** utility 53 | * Run the **Assembler (Generate programming files)** utility 54 | 55 | **NOTE:** The last 3 steps could be run altogether pressing the “Start Compilation” button 56 | 57 | 58 | Generate hardware address map header 59 | ----------------------------------------- 60 | To generate the system header file, first open the *SoC EDS Command Shell*. Then, the following instruction can be run from the project root directory, and it will generate a header file describing the HPS address map. It can be used by an HPS C/C++ program to get base addresses and other specifications of the FPGA 61 | peripherals. 62 | ```bash 63 | $ sopc-create-header-files --single hps_0.h --module hps_0 64 | ``` 65 | After running it, a header named *hps_0.h* will be generated on the current directory. 66 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/ip/altsource_probe/hps_reset.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "In-System Sources and Probes" 2 | set_global_assignment -name IP_TOOL_VERSION "16.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hps_reset.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hps_reset_bb.v"] 6 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/ip/altsource_probe/hps_reset.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: hps_reset.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.0.2 Build 222 07/20/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus Prime License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module hps_reset ( 41 | probe, 42 | source_clk, 43 | source); 44 | 45 | input probe; 46 | input source_clk; 47 | output [2:0] source; 48 | 49 | wire [2:0] sub_wire0; 50 | wire [2:0] source = sub_wire0[2:0]; 51 | 52 | altsource_probe altsource_probe_component ( 53 | .probe (probe), 54 | .source_clk (source_clk), 55 | .source (sub_wire0) 56 | // synopsys translate_off 57 | , 58 | .clr (), 59 | .ena (), 60 | .ir_in (), 61 | .ir_out (), 62 | .jtag_state_cdr (), 63 | .jtag_state_cir (), 64 | .jtag_state_e1dr (), 65 | .jtag_state_sdr (), 66 | .jtag_state_tlr (), 67 | .jtag_state_udr (), 68 | .jtag_state_uir (), 69 | .raw_tck (), 70 | .source_ena (), 71 | .tdi (), 72 | .tdo (), 73 | .usr1 () 74 | // synopsys translate_on 75 | ); 76 | defparam 77 | altsource_probe_component.enable_metastability = "YES", 78 | altsource_probe_component.instance_id = "RST", 79 | altsource_probe_component.probe_width = 0, 80 | altsource_probe_component.sld_auto_instance_index = "YES", 81 | altsource_probe_component.sld_instance_index = 0, 82 | altsource_probe_component.source_initial_value = " 0", 83 | altsource_probe_component.source_width = 3; 84 | 85 | 86 | endmodule 87 | 88 | // ============================================================ 89 | // CNX file retrieval info 90 | // ============================================================ 91 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES" 94 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 95 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0" 96 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 97 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 98 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 99 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3" 100 | // Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe" 101 | // Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]" 102 | // Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk" 103 | // Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0 104 | // Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0 105 | // Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE 110 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE 111 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE 112 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/ip/altsource_probe/hps_reset_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: hps_reset.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.0.2 Build 222 07/20/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus Prime License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module hps_reset ( 36 | probe, 37 | source_clk, 38 | source); 39 | 40 | input probe; 41 | input source_clk; 42 | output [2:0] source; 43 | 44 | endmodule 45 | 46 | // ============================================================ 47 | // CNX file retrieval info 48 | // ============================================================ 49 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 50 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 51 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES" 52 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 53 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0" 54 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 55 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 56 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 57 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3" 58 | // Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe" 59 | // Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]" 60 | // Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk" 61 | // Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0 62 | // Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0 63 | // Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0 64 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE 65 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE 66 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE 67 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE 68 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE 69 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE 70 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/ip/axi_conduit_merger/axi_conduit_merger.v: -------------------------------------------------------------------------------- 1 | module axi_conduit_merger #( 2 | parameter ID_WIDTH = 1, 3 | parameter DATA_WIDTH = 32, 4 | parameter ADDRESS_WIDTH = 32, 5 | parameter AXUSER_WIDTH = 5 6 | ) ( 7 | // axi master 8 | output m_awvalid, 9 | output [3:0] m_awlen , 10 | output [2:0] m_awsize , 11 | output [1:0] m_awburst, 12 | output [1:0] m_awlock , 13 | output [3:0] m_awcache, 14 | output [2:0] m_awprot , 15 | input m_awready, 16 | output [AXUSER_WIDTH-1:0] m_awuser , 17 | output m_arvalid, 18 | output [3:0] m_arlen , 19 | output [2:0] m_arsize , 20 | output [1:0] m_arburst, 21 | output [1:0] m_arlock , 22 | output [3:0] m_arcache, 23 | output [2:0] m_arprot , 24 | input m_arready, 25 | output [AXUSER_WIDTH-1:0] m_aruser , 26 | input m_rvalid , 27 | input m_rlast , 28 | input [1:0] m_rresp , 29 | output m_rready , 30 | output m_wvalid , 31 | output m_wlast , 32 | input m_wready , 33 | input m_bvalid , 34 | input [1:0] m_bresp , 35 | output m_bready , 36 | output [ADDRESS_WIDTH-1:0] m_awaddr , 37 | output [ID_WIDTH-1:0] m_awid , 38 | output [ADDRESS_WIDTH-1:0] m_araddr , 39 | output [ID_WIDTH-1:0] m_arid , 40 | input [DATA_WIDTH-1:0] m_rdata , 41 | input [ID_WIDTH-1:0] m_rid , 42 | output [DATA_WIDTH-1:0] m_wdata , 43 | output [DATA_WIDTH/8-1:0] m_wstrb , 44 | output [ID_WIDTH-1:0] m_wid , 45 | input [ID_WIDTH-1:0] m_bid , 46 | 47 | // axi slave 48 | input s_awvalid, 49 | input [3:0] s_awlen , 50 | input [2:0] s_awsize , 51 | input [1:0] s_awburst, 52 | input [1:0] s_awlock , 53 | input [3:0] s_awcache, 54 | input [2:0] s_awprot , 55 | output s_awready, 56 | input [AXUSER_WIDTH-1:0] s_awuser , 57 | input s_arvalid, 58 | input [3:0] s_arlen , 59 | input [2:0] s_arsize , 60 | input [1:0] s_arburst, 61 | input [1:0] s_arlock , 62 | input [3:0] s_arcache, 63 | input [2:0] s_arprot , 64 | output s_arready, 65 | input [AXUSER_WIDTH-1:0] s_aruser , 66 | output s_rvalid , 67 | output s_rlast , 68 | output [1:0] s_rresp , 69 | input s_rready , 70 | input s_wvalid , 71 | input s_wlast , 72 | output s_wready , 73 | output s_bvalid , 74 | output [1:0] s_bresp , 75 | input s_bready , 76 | input [ADDRESS_WIDTH-1:0] s_awaddr, 77 | input [ID_WIDTH-1:0] s_awid , 78 | input [ADDRESS_WIDTH-1:0] s_araddr, 79 | input [ID_WIDTH-1:0] s_arid , 80 | output [DATA_WIDTH-1:0] s_rdata , 81 | output [ID_WIDTH-1:0] s_rid , 82 | input [DATA_WIDTH-1:0] s_wdata , 83 | input [DATA_WIDTH/8-1:0] s_wstrb , 84 | input [ID_WIDTH-1:0] s_wid , 85 | output [ID_WIDTH-1:0] s_bid , 86 | 87 | // conduits 88 | input [3:0] c_awcache, 89 | input [2:0] c_awprot , 90 | input [AXUSER_WIDTH-1:0] c_awuser, 91 | input [3:0] c_arcache, 92 | input [2:0] c_arprot , 93 | input [AXUSER_WIDTH-1:0] c_aruser, 94 | 95 | // clock and reset 96 | input clk, 97 | input rst_n 98 | ); 99 | 100 | wire axi_wbus_bp; 101 | wire axi_rbus_bp; 102 | wire [3:0] v_awcache; 103 | wire [2:0] v_awprot; 104 | wire [AXUSER_WIDTH-1:0] v_awuser; 105 | reg [3:0] r_awcache; 106 | reg [2:0] r_awprot; 107 | reg [AXUSER_WIDTH-1:0] r_awuser; 108 | wire [3:0] v_arcache; 109 | wire [2:0] v_arprot; 110 | wire [AXUSER_WIDTH-1:0] v_aruser; 111 | reg [3:0] r_arcache; 112 | reg [2:0] r_arprot; 113 | reg [AXUSER_WIDTH-1:0] r_aruser; 114 | 115 | assign axi_wbus_bp = s_awvalid & ~m_awready; 116 | assign v_awcache = (!axi_wbus_bp) ? c_awcache : r_awcache; 117 | assign v_awprot = (!axi_wbus_bp) ? c_awprot : r_awprot; 118 | assign v_awuser = (!axi_wbus_bp) ? c_awuser : r_awuser; 119 | assign v_arcache = (!axi_rbus_bp) ? c_arcache : r_arcache; 120 | assign v_arprot = (!axi_rbus_bp) ? c_arprot : r_arprot; 121 | assign v_aruser = (!axi_rbus_bp) ? c_aruser : r_aruser; 122 | 123 | always @(posedge clk or negedge rst_n) begin 124 | if (!rst_n) begin 125 | r_awcache <= 4'd0; 126 | r_awprot <= 3'd0; 127 | r_awuser <= {AXUSER_WIDTH{1'b0}}; 128 | r_arcache <= 4'd0; 129 | r_arprot <= 3'd0; 130 | r_aruser <= {AXUSER_WIDTH{1'b0}}; 131 | end 132 | else begin 133 | r_awcache <= v_awcache; 134 | r_awprot <= v_awprot; 135 | r_awuser <= v_awuser; 136 | r_arcache <= v_arcache; 137 | r_arprot <= v_arprot; 138 | r_aruser <= v_aruser; 139 | end 140 | end 141 | 142 | // conduit signals replacement 143 | assign m_awcache = r_awcache; 144 | assign m_awprot = r_awprot; 145 | assign m_awuser = r_awuser; 146 | assign m_arcache = r_arcache; 147 | assign m_arprot = r_arprot; 148 | assign m_aruser = r_aruser; 149 | 150 | // axi bus assignment 151 | assign m_awvalid = s_awvalid ; 152 | assign m_awlen = s_awlen ; 153 | assign m_awsize = s_awsize ; 154 | assign m_awburst = s_awburst ; 155 | assign m_awlock = s_awlock ; 156 | // assign m_awcache = s_awcache; 157 | // assign m_awprot = s_awprot ; 158 | // assign m_awuser = s_awuser ; 159 | assign m_awaddr = s_awaddr ; 160 | assign m_awid = s_awid ; 161 | assign s_awready = m_awready ; 162 | assign m_arvalid = s_arvalid ; 163 | assign m_arlen = s_arlen ; 164 | assign m_arsize = s_arsize ; 165 | assign m_arburst = s_arburst ; 166 | assign m_arlock = s_arlock ; 167 | // assign m_arcache = s_arcache; 168 | // assign m_arprot = s_arprot ; 169 | // assign m_aruser = s_aruser ; 170 | assign m_araddr = s_araddr ; 171 | assign m_arid = s_arid ; 172 | assign s_arready = m_arready ; 173 | assign s_rvalid = m_rvalid ; 174 | assign s_rlast = m_rlast ; 175 | assign s_rresp = m_rresp ; 176 | assign s_rdata = m_rdata ; 177 | assign s_rid = m_rid ; 178 | assign m_rready = s_rready ; 179 | assign m_wvalid = s_wvalid ; 180 | assign m_wlast = s_wlast ; 181 | assign m_wdata = s_wdata ; 182 | assign m_wstrb = s_wstrb ; 183 | assign m_wid = s_wid ; 184 | assign s_wready = m_wready ; 185 | assign s_bvalid = m_bvalid ; 186 | assign s_bresp = m_bresp ; 187 | assign s_bid = m_bid ; 188 | assign m_bready = s_bready ; 189 | 190 | endmodule 191 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | module altera_edge_detector #( 2 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 3 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 4 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 5 | ) ( 6 | input clk, 7 | input rst_n, 8 | input signal_in, 9 | output pulse_out 10 | ); 11 | 12 | localparam IDLE = 0, ARM = 1, CAPT = 2; 13 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 14 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 15 | 16 | reg [1:0] state, next_state; 17 | reg pulse_detect; 18 | wire busy_pulsing; 19 | 20 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 21 | assign reset_qual_n = rst_n | busy_pulsing; 22 | 23 | generate 24 | if (PULSE_EXT > 1) begin: pulse_extend 25 | integer i; 26 | reg [PULSE_EXT-1:0] extend_pulse; 27 | always @(posedge clk or negedge reset_qual_n) begin 28 | if (!reset_qual_n) 29 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 30 | else begin 31 | for (i = 1; i < PULSE_EXT; i = i+1) begin 32 | extend_pulse[i] <= extend_pulse[i-1]; 33 | end 34 | extend_pulse[0] <= pulse_detect; 35 | end 36 | end 37 | assign pulse_out = |extend_pulse; 38 | end 39 | else begin: single_pulse 40 | reg pulse_reg; 41 | always @(posedge clk or negedge reset_qual_n) begin 42 | if (!reset_qual_n) 43 | pulse_reg <= 1'b0; 44 | else 45 | pulse_reg <= pulse_detect; 46 | end 47 | assign pulse_out = pulse_reg; 48 | end 49 | endgenerate 50 | 51 | always @(posedge clk) begin 52 | if (!rst_n) 53 | state <= IDLE; 54 | else 55 | state <= next_state; 56 | end 57 | 58 | // edge detect 59 | always @(*) begin 60 | next_state = state; 61 | pulse_detect = 1'b0; 62 | case (state) 63 | IDLE : begin 64 | pulse_detect = 1'b0; 65 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 66 | else next_state = IDLE; 67 | end 68 | ARM : begin 69 | pulse_detect = 1'b0; 70 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 71 | else next_state = ARM; 72 | end 73 | CAPT : begin 74 | pulse_detect = 1'b1; 75 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 76 | else next_state = IDLE; 77 | end 78 | default : begin 79 | pulse_detect = 1'b0; 80 | next_state = IDLE; 81 | end 82 | endcase 83 | end 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/soc_system.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 154 09/04/2013 SJ Full Version 21 | # Date created = 08:49:17 September 11, 2013 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "08:49:17 September 11, 2013" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "soc_system" 31 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/RD/soc_system.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/RD/soc_system.rbf -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/RD/soc_system.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/RD/soc_system.sof -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/WR/soc_system.rbf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/WR/soc_system.rbf -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/WR/soc_system.sof: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/FPGA-hardware/DE1-SoC/FPGA_DMA/sof_rbf/WR/soc_system.sof -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/FPGA_OCR_256K.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/FPGA-hardware/DE1-SoC/FPGA_OCR_256K/FPGA_OCR_256K.png -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/README.md: -------------------------------------------------------------------------------- 1 | FPGA_OCR_256K 2 | =========== 3 | 4 | Description 5 | ------------ 6 | This is a very simple project with an On-Chip RAM (OCR) in the FPGA. It is used to perform transfer tests between processor and FPGA. This project is a modification of the DE1-SoC Golden Hardware Reference Design (GHRD) available in the DE1-SoC CD-ROM documentation. Using Qsys, all the FPGA hardware on the GHRD was removed and an OCR was added and PLL were added. 7 | 8 | The OCR configured in the FPGA has the following characteristics: 9 | 10 | * Implemented using embedded 10kB memory blocks. 11 | * Size = 256kB, the maximum power of two feasible in DE1-SoC board. 12 | * Data_size is 128bits. The bigger the data size the faster the data rates achieved so 128 bits is selected. It is the maximum of the bridge where it is connected. 13 | * Connected to the HPS-FPGA bridge configured with data size equal to 128-bit. 14 | * Address of the memory is the position 0x00000000 in the HPS-FPGA bridge address space (0x00000000 in Qsys). Since the HPS-FPGA bridge starts in 0xC0000000 in the processor address space, the FPGA OCR is also in position 0xC000000 in the processor address space. Therefore 0xC0000000 is the address to be used to access the FPGA OCR from the processor. 15 | 16 | The PLL has the following characteristics: 17 | 18 | * Input frequency: 50MHz from external oscillator in the DE1-SoC board. 19 | * Output frequency: 100MHz. This clock is used to source the FPGA OCR and the FPGA side of the HPS-FPGA bridge. 20 | 21 | The following drawing depicts the hardware just described: 22 | 23 |

24 | Cyclone V SoC simplified block diagram 25 |

26 | 27 | Compilation instructions 28 | -------------------------- 29 | 30 | This hardware project was tested on Quartus II and Altera SoC EDS v16.0 Update 2. To compile this project: 31 | 32 | * Open Quartus (v16.0 Update 2). **Open project > soc_system.qpf** 33 | * Open Qsys and **load soc_system.qsys** 34 | * On Qsys, Select **Generate > Generate HDL...** De-select “Create block symbol file” option and specify desired HDL language (VHDL our case). Press “Generate” button. 35 | * After generation ends, go to Quartus and press the **Start Analysis & Synthesis** button 36 | * When synthesis ends, go to **Tools > Tcl scripts...** and run the scripts hps_sdram_p0_parameters.tcl and hps_sdram_p0_pin_assignments.tcl. Wait for confirmation pop-up window. 37 | * Perform again the **Analysis & Synthesis** of the project 38 | * Run the **Fitter (Place & Route)** utility 39 | * Run the **Assembler (Generate programming files)** utility 40 | 41 | **NOTE:** The last 3 steps could be run altogether pressing the “Start Compilation” button 42 | 43 | 44 | Generate hardware address map header 45 | ----------------------------------------- 46 | 47 | To generate the system header file, first open the *SoC EDS Command Shell*. Then, the following instruction can be run from the project root directory, and it will generate a header file describing the HPS address map. It can be used by an HPS C/C++ program to get base addresses and other specifications of the FPGA 48 | peripherals. 49 | ```bash 50 | $ sopc-create-header-files --single hps_0.h --module hps_0 51 | ``` 52 | After running it, a header named *hps_0.h* will be generated on the current directory. 53 | 54 | 55 | 56 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/ip/altsource_probe/hps_reset.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "In-System Sources and Probes" 2 | set_global_assignment -name IP_TOOL_VERSION "16.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "hps_reset.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "hps_reset_bb.v"] 6 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/ip/altsource_probe/hps_reset.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: hps_reset.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.0.2 Build 222 07/20/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus Prime License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module hps_reset ( 41 | probe, 42 | source_clk, 43 | source); 44 | 45 | input probe; 46 | input source_clk; 47 | output [2:0] source; 48 | 49 | wire [2:0] sub_wire0; 50 | wire [2:0] source = sub_wire0[2:0]; 51 | 52 | altsource_probe altsource_probe_component ( 53 | .probe (probe), 54 | .source_clk (source_clk), 55 | .source (sub_wire0) 56 | // synopsys translate_off 57 | , 58 | .clr (), 59 | .ena (), 60 | .ir_in (), 61 | .ir_out (), 62 | .jtag_state_cdr (), 63 | .jtag_state_cir (), 64 | .jtag_state_e1dr (), 65 | .jtag_state_sdr (), 66 | .jtag_state_tlr (), 67 | .jtag_state_udr (), 68 | .jtag_state_uir (), 69 | .raw_tck (), 70 | .source_ena (), 71 | .tdi (), 72 | .tdo (), 73 | .usr1 () 74 | // synopsys translate_on 75 | ); 76 | defparam 77 | altsource_probe_component.enable_metastability = "YES", 78 | altsource_probe_component.instance_id = "RST", 79 | altsource_probe_component.probe_width = 0, 80 | altsource_probe_component.sld_auto_instance_index = "YES", 81 | altsource_probe_component.sld_instance_index = 0, 82 | altsource_probe_component.source_initial_value = " 0", 83 | altsource_probe_component.source_width = 3; 84 | 85 | 86 | endmodule 87 | 88 | // ============================================================ 89 | // CNX file retrieval info 90 | // ============================================================ 91 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 92 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 93 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES" 94 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 95 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0" 96 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 97 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 98 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 99 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3" 100 | // Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe" 101 | // Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]" 102 | // Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk" 103 | // Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0 104 | // Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0 105 | // Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0 106 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE 107 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE 108 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE 109 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE 110 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE 111 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE 112 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/ip/altsource_probe/hps_reset_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %In-System Sources and Probes%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsource_probe 5 | 6 | // ============================================================ 7 | // File Name: hps_reset.v 8 | // Megafunction Name(s): 9 | // altsource_probe 10 | // 11 | // Simulation Library Files(s): 12 | // 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 16.0.2 Build 222 07/20/2016 SJ Lite Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2016 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus Prime License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module hps_reset ( 36 | probe, 37 | source_clk, 38 | source); 39 | 40 | input probe; 41 | input source_clk; 42 | output [2:0] source; 43 | 44 | endmodule 45 | 46 | // ============================================================ 47 | // CNX file retrieval info 48 | // ============================================================ 49 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V" 50 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 51 | // Retrieval info: CONSTANT: ENABLE_METASTABILITY STRING "YES" 52 | // Retrieval info: CONSTANT: INSTANCE_ID STRING "RST" 53 | // Retrieval info: CONSTANT: PROBE_WIDTH NUMERIC "0" 54 | // Retrieval info: CONSTANT: SLD_AUTO_INSTANCE_INDEX STRING "YES" 55 | // Retrieval info: CONSTANT: SLD_INSTANCE_INDEX NUMERIC "0" 56 | // Retrieval info: CONSTANT: SOURCE_INITIAL_VALUE STRING " 0" 57 | // Retrieval info: CONSTANT: SOURCE_WIDTH NUMERIC "3" 58 | // Retrieval info: USED_PORT: probe 0 0 0 0 INPUT NODEFVAL "probe" 59 | // Retrieval info: USED_PORT: source 0 0 3 0 OUTPUT NODEFVAL "source[2..0]" 60 | // Retrieval info: USED_PORT: source_clk 0 0 0 0 INPUT NODEFVAL "source_clk" 61 | // Retrieval info: CONNECT: @probe 0 0 0 0 probe 0 0 0 0 62 | // Retrieval info: CONNECT: @source_clk 0 0 0 0 source_clk 0 0 0 0 63 | // Retrieval info: CONNECT: source 0 0 3 0 @source 0 0 3 0 64 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.v TRUE 65 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.inc FALSE 66 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.cmp FALSE 67 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset.bsf FALSE 68 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_inst.v FALSE 69 | // Retrieval info: GEN_FILE: TYPE_NORMAL hps_reset_bb.v TRUE 70 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/ip/debounce/debounce.v: -------------------------------------------------------------------------------- 1 | //Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your 2 | //use of Altera Corporation's design tools, logic functions and other 3 | //software and tools, and its AMPP partner logic functions, and any 4 | //output files any of the foregoing (including device programming or 5 | //simulation files), and any associated documentation or information are 6 | //expressly subject to the terms and conditions of the Altera Program 7 | //License Subscription Agreement or other applicable license agreement, 8 | //including, without limitation, that your use is for the sole purpose 9 | //of programming logic devices manufactured by Altera and sold by Altera 10 | //or its authorized distributors. Please refer to the applicable 11 | //agreement for further details. 12 | 13 | module debounce ( 14 | clk, 15 | reset_n, 16 | data_in, 17 | data_out 18 | ); 19 | 20 | parameter WIDTH = 32; // set to be the width of the bus being debounced 21 | parameter POLARITY = "HIGH"; // set to be "HIGH" for active high debounce or "LOW" for active low debounce 22 | parameter TIMEOUT = 50000; // number of input clock cycles the input signal needs to be in the active state 23 | parameter TIMEOUT_WIDTH = 16; // set to be ceil(log2(TIMEOUT)) 24 | 25 | input wire clk; 26 | input wire reset_n; 27 | 28 | input wire [WIDTH-1:0] data_in; 29 | output wire [WIDTH-1:0] data_out; 30 | 31 | reg [TIMEOUT_WIDTH-1:0] counter [0:WIDTH-1]; 32 | wire counter_reset [0:WIDTH-1]; 33 | wire counter_enable [0:WIDTH-1]; 34 | 35 | // need one counter per input to debounce 36 | genvar i; 37 | generate for (i = 0; i < WIDTH; i = i+1) 38 | begin: debounce_counter_loop 39 | always @ (posedge clk or negedge reset_n) 40 | begin 41 | if (reset_n == 0) 42 | begin 43 | counter[i] <= 0; 44 | end 45 | else 46 | begin 47 | if (counter_reset[i] == 1) // resetting the counter needs to win 48 | begin 49 | counter[i] <= 0; 50 | end 51 | else if (counter_enable[i] == 1) 52 | begin 53 | counter[i] <= counter[i] + 1'b1; 54 | end 55 | end 56 | end 57 | 58 | if (POLARITY == "HIGH") 59 | begin 60 | assign counter_reset[i] = (data_in[i] == 0); 61 | assign counter_enable[i] = (data_in[i] == 1) & (counter[i] < TIMEOUT); 62 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b1 : 1'b0; 63 | end 64 | else 65 | begin 66 | assign counter_reset[i] = (data_in[i] == 1); 67 | assign counter_enable[i] = (data_in[i] == 0) & (counter[i] < TIMEOUT); 68 | assign data_out[i] = (counter[i] == TIMEOUT) ? 1'b0 : 1'b1; 69 | end 70 | 71 | end 72 | endgenerate 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/ip/edge_detect/altera_edge_detector.v: -------------------------------------------------------------------------------- 1 | module altera_edge_detector #( 2 | parameter PULSE_EXT = 0, // 0, 1 = edge detection generate single cycle pulse, >1 = pulse extended for specified clock cycle 3 | parameter EDGE_TYPE = 0, // 0 = falling edge, 1 or else = rising edge 4 | parameter IGNORE_RST_WHILE_BUSY = 0 // 0 = module internal reset will be default whenever rst_n asserted, 1 = rst_n request will be ignored while generating pulse out 5 | ) ( 6 | input clk, 7 | input rst_n, 8 | input signal_in, 9 | output pulse_out 10 | ); 11 | 12 | localparam IDLE = 0, ARM = 1, CAPT = 2; 13 | localparam SIGNAL_ASSERT = EDGE_TYPE ? 1'b1 : 1'b0; 14 | localparam SIGNAL_DEASSERT = EDGE_TYPE ? 1'b0 : 1'b1; 15 | 16 | reg [1:0] state, next_state; 17 | reg pulse_detect; 18 | wire busy_pulsing; 19 | 20 | assign busy_pulsing = (IGNORE_RST_WHILE_BUSY)? pulse_out : 1'b0; 21 | assign reset_qual_n = rst_n | busy_pulsing; 22 | 23 | generate 24 | if (PULSE_EXT > 1) begin: pulse_extend 25 | integer i; 26 | reg [PULSE_EXT-1:0] extend_pulse; 27 | always @(posedge clk or negedge reset_qual_n) begin 28 | if (!reset_qual_n) 29 | extend_pulse <= {{PULSE_EXT}{1'b0}}; 30 | else begin 31 | for (i = 1; i < PULSE_EXT; i = i+1) begin 32 | extend_pulse[i] <= extend_pulse[i-1]; 33 | end 34 | extend_pulse[0] <= pulse_detect; 35 | end 36 | end 37 | assign pulse_out = |extend_pulse; 38 | end 39 | else begin: single_pulse 40 | reg pulse_reg; 41 | always @(posedge clk or negedge reset_qual_n) begin 42 | if (!reset_qual_n) 43 | pulse_reg <= 1'b0; 44 | else 45 | pulse_reg <= pulse_detect; 46 | end 47 | assign pulse_out = pulse_reg; 48 | end 49 | endgenerate 50 | 51 | always @(posedge clk) begin 52 | if (!rst_n) 53 | state <= IDLE; 54 | else 55 | state <= next_state; 56 | end 57 | 58 | // edge detect 59 | always @(*) begin 60 | next_state = state; 61 | pulse_detect = 1'b0; 62 | case (state) 63 | IDLE : begin 64 | pulse_detect = 1'b0; 65 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 66 | else next_state = IDLE; 67 | end 68 | ARM : begin 69 | pulse_detect = 1'b0; 70 | if (signal_in == SIGNAL_ASSERT) next_state = CAPT; 71 | else next_state = ARM; 72 | end 73 | CAPT : begin 74 | pulse_detect = 1'b1; 75 | if (signal_in == SIGNAL_DEASSERT) next_state = ARM; 76 | else next_state = IDLE; 77 | end 78 | default : begin 79 | pulse_detect = 1'b0; 80 | next_state = IDLE; 81 | end 82 | endcase 83 | end 84 | 85 | endmodule 86 | -------------------------------------------------------------------------------- /FPGA-hardware/DE1-SoC/FPGA_OCR_256K/soc_system.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 1991-2013 Altera Corporation 4 | # Your use of Altera Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Altera Program License 10 | # Subscription Agreement, Altera MegaCore Function License 11 | # Agreement, or other applicable license agreement, including, 12 | # without limitation, that your use is for the sole purpose of 13 | # programming logic devices manufactured by Altera and sold by 14 | # Altera or its authorized distributors. Please refer to the 15 | # applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus II 64-Bit 20 | # Version 13.1.0 Build 154 09/04/2013 SJ Full Version 21 | # Date created = 08:49:17 September 11, 2013 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "13.1" 26 | DATE = "08:49:17 September 11, 2013" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "soc_system" 31 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC/DMA_transfer_FPGA_DMAC.c: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Author: Roberto Fernandez Molanes (robertofem@gmail.com) 4 | * University of Vigo 5 | * 6 | * 09 March 2018 7 | * 8 | * This is a simple example showing how to use a DMA in the FPGA. The component 9 | * is the basic DMA Controller available in Qsys. 10 | * The files fpga_dmac_api.h and fpga_dmac_api.c are a bunch of macros and 11 | * functions to control the DMA controller. In this particular example the DMA 12 | * controller copies a buffer in a FPGA On-Chip RAM (FPGA-OCR) to the HPS 13 | * On-Chip RAM (HPS-OCR). Therefore the FPGA-OCR is connected to the read port. 14 | * To access HPS-OCR from FPGA the write port of the DMA controller is connected 15 | * to the FPGA-to-HPS bridge. 16 | ******************************************************************************/ 17 | #include 18 | #include 19 | #include 20 | #include 21 | #include 22 | #include 23 | #include 24 | #include 25 | 26 | #include "fpga_dmac_api.h" 27 | 28 | #define DMA_TRANSFER_SIZE 32 29 | 30 | /**************************SOME MACROS TO EASE PROGRAMMING*******************/ 31 | //Constants to do mmap and get access to FPGA and HPS peripherals 32 | #define HPS_FPGA_BRIDGE_BASE 0xC0000000 33 | #define HW_REGS_BASE ( HPS_FPGA_BRIDGE_BASE ) 34 | #define HW_REGS_SPAN ( 0x40000000 ) 35 | #define HW_REGS_MASK ( HW_REGS_SPAN - 1 ) 36 | 37 | //The address of FPGA-DMAC is the HPS-FPGA bridge + Qsys address assigned to it 38 | #define FPGA_DMAC_QSYS_ADDRESS 0x10000 39 | #define FPGA_DMAC_ADDRESS ((uint8_t*)0xC0000000+FPGA_DMAC_QSYS_ADDRESS) 40 | //Address of the On-Chip RAM in the FPGA, as seen by processor 41 | #define FPGA_OCR_QSYS_ADDRESS_UP 0x0 42 | #define FPGA_OCR_ADDRESS_UP ((uint8_t*)0xC0000000+FPGA_OCR_QSYS_ADDRESS_UP) 43 | //Address of the On-Chip RAM in the FPGA, as seen by DMAC 44 | #define FPGA_OCR_ADDRESS_DMAC 0x0 45 | //Address of the HPS-OCR, as seen by both processor and FPGA-DMAC 46 | #define HPS_OCR_ADDRESS 0xFFFF0000 47 | 48 | //DMAC transfer addresses (from processor they are virtual addresses) 49 | //#define WRITE_OPERATION 50 | #ifdef WRITE_OPERATION 51 | #define DMA_TRANSFER_SRC_DMAC ((uint8_t*) FPGA_OCR_ADDRESS_DMAC) 52 | #define DMA_TRANSFER_SRC_UP ((uint8_t*) FPGA_OCR_vaddr) 53 | #define DMA_TRANSFER_DST_DMAC ((uint8_t*) HPS_OCR_ADDRESS) 54 | #define DMA_TRANSFER_DST_UP ((uint8_t*) HPS_OCR_vaddr) 55 | #else 56 | #define DMA_TRANSFER_SRC_DMAC ((uint8_t*) HPS_OCR_ADDRESS) 57 | #define DMA_TRANSFER_SRC_UP ((uint8_t*) HPS_OCR_vaddr) 58 | #define DMA_TRANSFER_DST_DMAC ((uint8_t*) FPGA_OCR_ADDRESS_DMAC) 59 | #define DMA_TRANSFER_DST_UP ((uint8_t*) FPGA_OCR_vaddr) 60 | #endif 61 | 62 | void printbuff(uint8_t* buff, int size) 63 | { 64 | int i; 65 | printf("["); 66 | for (i=0; i Mode JTAG -> Select 5CSEMA5 (for DE1-SoC and DE0-nano-SoC) if asked -> Right click in the line representing the FPGA -> Change FIle -> Select the .sof file for the project you want to load -> tick Program/Configure -> Click Start. 60 | 61 | * Connect the serial console port (the mini-USB port in DE1-SoC) to the computer and open a session with a Seral Terminal (like Putty) at 115200 bauds. Now you have access to the board OS console. 62 | 63 | * Copy the executable into the SD card and run the application: 64 | ```bash 65 | $ chmod 777 DMA_transfer_FPGA_DMAC 66 | $ ./DMA_transfer_FPGA_DMAC 67 | ``` 68 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC/fpga_dmac_api.c: -------------------------------------------------------------------------------- 1 | //API for the Qsys DMA Controller v.1.1 2 | #include "fpga_dmac_api.h" 3 | 4 | //-----------------Generic functions--------------------// 5 | //(Addresses are multiplied by 4 because the peripheral has 32-bit (4byte) regs 6 | uint32_t fpga_dma_read_reg(void* addr, uint32_t reg) 7 | { 8 | return *((uint32_t*) (addr + 4*reg)); 9 | } 10 | 11 | void fpga_dma_write_reg(void* addr, uint32_t reg, uint32_t val) 12 | { 13 | *((uint32_t*) (addr + 4*reg)) = val; 14 | } 15 | 16 | uint32_t fpga_dma_read_bit(void* addr, uint32_t reg, uint32_t bit) 17 | { 18 | return (bit & fpga_dma_read_reg(addr, reg)); 19 | } 20 | 21 | void fpga_dma_write_bit(void* addr, uint32_t reg, uint32_t bit, uint32_t val) 22 | { 23 | uint32_t old = fpga_dma_read_reg(addr, reg); 24 | if(val == 0) 25 | { 26 | fpga_dma_write_reg(addr, reg, (old & (~bit))); 27 | } 28 | else if(val == 1) 29 | { 30 | fpga_dma_write_reg(addr, reg, (old | bit)); 31 | } 32 | return; 33 | } 34 | 35 | //------------Some specific functions-------------------// 36 | void fpga_dma_init(void* addr, uint32_t control_reg_val) 37 | { 38 | fpga_dma_write_reg( addr, FPGA_DMA_CONTROL, control_reg_val); 39 | } 40 | 41 | void fpga_dma_config_transfer(void* addr, void* src, void* dst, unsigned int size) 42 | { 43 | fpga_dma_write_bit( addr,//clean go bit 44 | FPGA_DMA_CONTROL, 45 | FPGA_DMA_GO, 46 | 0); 47 | fpga_dma_write_bit( addr, //clean the done bit 48 | FPGA_DMA_STATUS, 49 | FPGA_DMA_DONE, 50 | 0); 51 | fpga_dma_write_reg( addr, //set source address 52 | FPGA_DMA_READADDRESS, 53 | (uint32_t) src); 54 | fpga_dma_write_reg( addr, //set destiny address 55 | FPGA_DMA_WRITEADDRESS, 56 | (uint32_t) dst); 57 | fpga_dma_write_reg( addr, //set transfer size 58 | FPGA_DMA_LENGTH, 59 | (uint32_t) size); 60 | //Wait a small time. Needed for the read from HPS to work. 61 | int counter=0; 62 | int j; 63 | for(j=0; j<10; j++) counter++; 64 | } 65 | 66 | void fpga_dma_start_transfer(void* addr) 67 | { 68 | fpga_dma_write_bit( addr, 69 | FPGA_DMA_CONTROL, 70 | FPGA_DMA_GO, 71 | 1);//start transfer 72 | } 73 | 74 | //this function returns a 1 if the DMA transfer is finished, 0 otherwise 75 | uint32_t fpga_dma_transfer_done(void* addr) 76 | { 77 | return fpga_dma_read_bit(addr, FPGA_DMA_STATUS, FPGA_DMA_DONE); 78 | } 79 | 80 | //alligned allocation to the transfer size is needed for reading HPS from FPGA 81 | 82 | void* align_malloc (size_t size, void** unaligned_addr) 83 | { 84 | char* Buffer_8 = (char*) malloc(size*2); 85 | *unaligned_addr = (void*) Buffer_8; 86 | uint8_t* Buffer_8_ptr; 87 | Buffer_8_ptr = (uint8_t*)Buffer_8; 88 | int k; 89 | for(k=0; k<(size); k++) 90 | { 91 | if ((((unsigned long int)Buffer_8_ptr) % ((unsigned long int)size))==0) 92 | { 93 | return (void*)Buffer_8_ptr; 94 | } 95 | else 96 | { 97 | Buffer_8_ptr++; 98 | } 99 | } 100 | return 0; 101 | } 102 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC/fpga_dmac_api.h: -------------------------------------------------------------------------------- 1 | //API for the Qsys DMA Controller 2 | 3 | #ifndef __FPGA_DMAC_API__ 4 | #define __FPGA_DMAC_API__ 5 | 6 | #include 7 | #include 8 | 9 | //REGISTER MAP 10 | #define FPGA_DMA_STATUS 0 11 | #define FPGA_DMA_READADDRESS 1 12 | #define FPGA_DMA_WRITEADDRESS 2 13 | #define FPGA_DMA_LENGTH 3 14 | //RESERVED 4 15 | //RESERVED 5 16 | #define FPGA_DMA_CONTROL 6 17 | //RESERVED 7 18 | 19 | //MACROS to more easily read the control status register bits 20 | #define FPGA_DMA_DONE 0b00001 //DONE 21 | #define FPGA_DMA_BUSY 0b00010 //BUSY 22 | #define FPGA_DMA_REOP 0b00100 //REOP 23 | #define FPGA_DMA_WEOP 0b01000 //WEOP 24 | #define FPGA_DMA_LEN 0b10000 //LEN 25 | 26 | //MACROS to more easily program the control register 27 | #define FPGA_DMA_BYTE_TRANSFERS 0b0000000000001 //BYTE 28 | #define FPGA_DMA_HALFWORD_TRANSFERS 0b0000000000010 //HW 29 | #define FPGA_DMA_WORD_TRANSFERS 0b0000000000100 //WORD 30 | #define FPGA_DMA_GO 0b0000000001000 //GO 31 | #define FPGA_DMA_INTERRUPT_ENABLE 0b0000000010000 //I_EN 32 | #define FPGA_DMA_END_RD_END_OF_PACKET 0b0000000100000 //REEN 33 | #define FPGA_DMA_END_WR_END_OF_PACKET 0b0000001000000 //WEEN 34 | #define FPGA_DMA_END_WHEN_LENGHT_ZERO 0b0000010000000 //LEEN 35 | #define FPGA_DMA_READ_CONSTANT_ADDR 0b0000100000000 //RCON 36 | #define FPGA_DMA_WRITE_CONSTANT_ADDR 0b0001000000000 //WCON 37 | #define FPGA_DMA_DOUBLEWORD_TRANSFERS 0b0010000000000 //DOUBLEWORD 38 | #define FPGA_DMA_QUADWORD_TRANSFERS 0b0100000000000 //QUADWORD 39 | #define FPGA_DMA_SOFTWARE_RESET 0b1000000000000 //SOFTWARE_RESET 40 | 41 | //-----------------Generic functions--------------------// 42 | uint32_t fpga_dma_read_reg(void* addr, uint32_t reg); 43 | void fpga_dma_write_reg(void* addr, uint32_t reg, uint32_t val); 44 | uint32_t fpga_dma_read_bit(void* addr, uint32_t reg, uint32_t bit); 45 | void fpga_dma_write_bit(void* addr, uint32_t reg, uint32_t bit, uint32_t val); 46 | 47 | //------------Some specific functions-------------------// 48 | void fpga_dma_init(); 49 | void fpga_dma_config_transfer(void* addr, void* src, void* dst, unsigned int size); 50 | void fpga_dma_start_transfer(void* addr); 51 | uint32_t fpga_dma_transfer_done(void* addr); 52 | void* align_malloc (size_t size, void** unaligned_addr); 53 | 54 | #endif // __FPGA_DMAC_API__ 55 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC_driver/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | TARGET = DMA_transfer_FPGA_DMAC_driver 3 | 4 | #Compile with the toolchain from Angstrom 2013.12 compilation 5 | #CROSS_COMPILE := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/sysroots/x86_64-linux/usr/bin/armv7ahf-vfp-neon-angstrom-linux-gnueabi/arm-angstrom-linux-gnueabi- 6 | #Compile from SOC EDS toolchain (from Altera Embedded Command Shell ) 7 | CROSS_COMPILE := arm-linux-gnueabihf- 8 | 9 | CFLAGS = -g -Wall -I ${SOCEDS_DEST_ROOT}/ip/altera/hps/altera_hps/hwlib/include 10 | LDFLAGS = -g -Wall 11 | CC = $(CROSS_COMPILE)gcc 12 | ARCH= arm 13 | 14 | build: $(TARGET) 15 | 16 | $(TARGET): DMA_transfer_FPGA_DMAC.o fpga_dmac_api.o 17 | $(CC) $(LDFLAGS) $^ -o $@ 18 | 19 | %.o : %.c 20 | $(CC) $(CFLAGS) -c $< -o $@ 21 | 22 | .PHONY: clean 23 | clean: 24 | rm -f $(TARGET) *.a *.o *~ 25 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC_driver/README.md: -------------------------------------------------------------------------------- 1 | DMA_transfer_FPGA_DMAC_driver 2 | ===================== 3 | 4 | Introduction 5 | ------------- 6 | This application does a simple transfer from FPGA to a Buffer in application space using a DMA Controller (DMAC) in the FPGA. The DMAC used is the simple (non scatter-gather) DMA Controller Core available in Qsys. Its documentation is available at [DMA Controller Core doc](https://www.altera.com/documentation/sfo1400787952932.html#iga1401397703359). 7 | In this example the [Alloc_DMAble_buffer doc](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/Alloc_DMAble_buff_LKM) module is used to allocate the physically contiguous buffers needed 8 | to perform the DMA transfers. 9 | 10 | The program is intended to be used with the hardware project [FPGA_DMA](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC/FPGA_DMA) that contains: 11 | 12 | * The DMA Controller Core. The control port is connected to HPS through HPS-to-FPGA bridge at address 0x10000. The read port, intended to read the source buffer during the DMA transfers, is connected to the FPGA-HPS bridge so it can access HPS-OCR. The write port, intended to write data during DMA transfers, is connected to 13 | the FPGA-OCR at address 0. 14 | 15 | * The FPGA-OCR: 1kB of double port memory. One port is connected to the HPS-to-FPGA bridge at address 0x0 so the processor has access to the buffer and initialize the content of the memory. The second port is connected to the DMA read port, as commented above. 16 | 17 | In this particular example the DMA controller copies a buffer in the FPGA 18 | On-Chip RAM (FPGA-OCR) to a buffer in the program. Therefore the FPGA-OCR 19 | must be connected to the read port of the DMAC and the FPGA-to-HPS bridge is 20 | connected to the write port of the DMAC. This the opossite connection to the 21 | default connections in the hardware project. Therefore, before testing this 22 | example switch the connections of the read and write ports of the DMAC 23 | using Qsys and recompile the FPGA hardware. 24 | 25 | Description of the code 26 | ------------------------ 27 | 28 | This program first generates the virtual addresses to access FPGA peripherals using mmap. 1GB of address space is mapped to cover from 0xC0000000 29 | (the beginning of HPS-to-FPGA bridge where FPGA-OCR, the control port of DMAC and the GPIO to modify the AXI signals are connected) until 0xFFFFFFFF. Using this mapping the individual virtual address of each component is calculated. 30 | 31 | Later the FPGA-OCR is checked to ensure there is not an access problem like FPGA design not loaded or wrong addresses. Later it is reset to start the experiment with all Bytes of the memory to 0. 32 | 33 | After that the AXI signals of the bus connected to the FPGA-to-HPS bridge are 34 | set using a GPIO in the FPGA. Setting this signals to a correct value is mandatory 35 | to perform successgul accesses through ACP. 36 | 37 | Then an buffer is allocate with the driver to be used as destiny buffer for the 38 | DMA transfer. The buffer size is defined equal to the DMA transfer size and 39 | cached (so ACP must be used with it). 40 | 41 | Lastly the DMA Transfer takes place. Then FPGA-OCR is initialized with random values before the transfer starts. To program the transfer the control register is first loaded indicating in this case Word (32-bit) Transfers (FPGA_DMA_WORD_TRANSFERS) that end when the lenght of the remaining transfer is 0 (FPGA_DMA_END_WHEN_LENGHT_ZERO). There are other methods to end the transfer like hardware signaling but this is the most common. Using the macros in dpga_dmac_api.h the user can test all the available options. For example if FPGA_DMA_WORD_TRANSFERS is changed by FPGA_DMA_BYTE_TRANSFERS and FPGA_DMA_READ_CONSTANT_ADDR is added the DMAC will do byte transfers always reading the same first byte of the FPGA-memory and therefore the HPS-OCR will be filled with the same value. 42 | 43 | In the end of the program the source and destiny buffers are compared to check if the transfer was correct and all buffers and memory mappings are freed. 44 | 45 | Contents in the folder 46 | ---------------------- 47 | * DMA_transfer_FPGA_DMAC.c: the previously commented code is here. 48 | * fpga_dmac_api.h and fpga_dmac_api.c: macros and functions to control the DMA Controller Core in the FPGA. 49 | * Makefile: describes compilation process. 50 | 51 | Compilation 52 | ----------- 53 | Open *SoC EDS Command Shell* (*Intel FPGA SoC EDS* needs to be installed in your system), navigate to the folder of the example and type **_make_**. 54 | This program was tested with Intel *FPGA SoC EDS v16.1*. 55 | 56 | The compilation process generates the executable file *DMA_transfer_FPGA_DMAC_driver*. 57 | 58 | How to test 59 | ------------ 60 | * Configure MSEL pins: 61 | * MSEL[5:0]="000000" position when FPGA will be configured from SD card. 62 | * MSEL[5:0]="110010" position when FPGA will be configured from EPCQ device or Quartus programmer. 63 | * Switch on the board. 64 | * Compile the FPGA hardware ([FPGA_DMA](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC/FPGA_DMA) in example) and load it in the FPGA): 65 | * If MSEL[5:0]="000000" FPGA is loaded by the U-boot during start-up. Check the [tutorials to build a SD card with Operating System](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system) to learn how to configure the SD card so the FPGA is loaded from it. 66 | * If MSEL[5:0]="110010" use Quartus to load the FPGA: 67 | * Connect the USB cable (just next to the power connector). 68 | * Open Quartus programmer. 69 | * Click Autodetect -> Mode JTAG -> Select 5CSEMA5 (for DE1-SoC and DE0-nano-SoC) if asked -> Right click in the line representing the FPGA -> Change FIle -> Select the .sof file for the project you want to load -> tick Program/Configure -> Click Start. 70 | 71 | * Connect the serial console port (the mini-USB port in DE1-SoC) to the computer and open a session with a Seral Terminal (like Putty) at 115200 bauds. Now you have access to the board OS console. 72 | 73 | * Copy the executable and the driver(alloc_dmable_buff.ko) into the SD card and: 74 | ```bash 75 | $ insmod alloc_dmable_buff.ko 76 | $ chmod 777 DMA_transfer_FPGA_DMAC_driver 77 | $ ./DMA_transfer_FPGA_DMAC_driver 78 | ``` 79 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC_driver/fpga_dmac_api.c: -------------------------------------------------------------------------------- 1 | //API for the Qsys DMA Controller v.1.1 2 | #include "fpga_dmac_api.h" 3 | 4 | //-----------------Generic functions--------------------// 5 | //(Addresses are multiplied by 4 because the peripheral has 32-bit (4byte) regs 6 | uint32_t fpga_dma_read_reg(void* addr, uint32_t reg) 7 | { 8 | return *((uint32_t*) (addr + 4*reg)); 9 | } 10 | 11 | void fpga_dma_write_reg(void* addr, uint32_t reg, uint32_t val) 12 | { 13 | *((uint32_t*) (addr + 4*reg)) = val; 14 | } 15 | 16 | uint32_t fpga_dma_read_bit(void* addr, uint32_t reg, uint32_t bit) 17 | { 18 | return (bit & fpga_dma_read_reg(addr, reg)); 19 | } 20 | 21 | void fpga_dma_write_bit(void* addr, uint32_t reg, uint32_t bit, uint32_t val) 22 | { 23 | uint32_t old = fpga_dma_read_reg(addr, reg); 24 | if(val == 0) 25 | { 26 | fpga_dma_write_reg(addr, reg, (old & (~bit))); 27 | } 28 | else if(val == 1) 29 | { 30 | fpga_dma_write_reg(addr, reg, (old | bit)); 31 | } 32 | return; 33 | } 34 | 35 | //------------Some specific functions-------------------// 36 | void fpga_dma_init(void* addr, uint32_t control_reg_val) 37 | { 38 | fpga_dma_write_reg( addr, FPGA_DMA_CONTROL, control_reg_val); 39 | } 40 | 41 | void fpga_dma_config_transfer(void* addr, void* src, void* dst, unsigned int size) 42 | { 43 | fpga_dma_write_bit( addr,//clean go bit 44 | FPGA_DMA_CONTROL, 45 | FPGA_DMA_GO, 46 | 0); 47 | fpga_dma_write_bit( addr, //clean the done bit 48 | FPGA_DMA_STATUS, 49 | FPGA_DMA_DONE, 50 | 0); 51 | fpga_dma_write_reg( addr, //set source address 52 | FPGA_DMA_READADDRESS, 53 | (uint32_t) src); 54 | fpga_dma_write_reg( addr, //set destiny address 55 | FPGA_DMA_WRITEADDRESS, 56 | (uint32_t) dst); 57 | fpga_dma_write_reg( addr, //set transfer size 58 | FPGA_DMA_LENGTH, 59 | (uint32_t) size); 60 | //Wait a small time. Needed for the read from HPS to work. 61 | int counter=0; 62 | int j; 63 | for(j=0; j<10; j++) counter++; 64 | } 65 | 66 | void fpga_dma_start_transfer(void* addr) 67 | { 68 | fpga_dma_write_bit( addr, 69 | FPGA_DMA_CONTROL, 70 | FPGA_DMA_GO, 71 | 1);//start transfer 72 | } 73 | 74 | //this function returns a 1 if the DMA transfer is finished, 0 otherwise 75 | uint32_t fpga_dma_transfer_done(void* addr) 76 | { 77 | return fpga_dma_read_bit(addr, FPGA_DMA_STATUS, FPGA_DMA_DONE); 78 | } 79 | 80 | //alligned allocation to the transfer size is needed for reading HPS from FPGA 81 | 82 | void* align_malloc (size_t size, void** unaligned_addr) 83 | { 84 | char* Buffer_8 = (char*) malloc(size*2); 85 | *unaligned_addr = (void*) Buffer_8; 86 | uint8_t* Buffer_8_ptr; 87 | Buffer_8_ptr = (uint8_t*)Buffer_8; 88 | int k; 89 | for(k=0; k<(size); k++) 90 | { 91 | if ((((unsigned long int)Buffer_8_ptr) % ((unsigned long int)size))==0) 92 | { 93 | return (void*)Buffer_8_ptr; 94 | } 95 | else 96 | { 97 | Buffer_8_ptr++; 98 | } 99 | } 100 | return 0; 101 | } 102 | -------------------------------------------------------------------------------- /Linux-applications/DMA_transfer_FPGA_DMAC_driver/fpga_dmac_api.h: -------------------------------------------------------------------------------- 1 | //API for the Qsys DMA Controller 2 | 3 | #ifndef __FPGA_DMAC_API__ 4 | #define __FPGA_DMAC_API__ 5 | 6 | #include 7 | #include 8 | 9 | //REGISTER MAP 10 | #define FPGA_DMA_STATUS 0 11 | #define FPGA_DMA_READADDRESS 1 12 | #define FPGA_DMA_WRITEADDRESS 2 13 | #define FPGA_DMA_LENGTH 3 14 | //RESERVED 4 15 | //RESERVED 5 16 | #define FPGA_DMA_CONTROL 6 17 | //RESERVED 7 18 | 19 | //MACROS to more easily read the control status register bits 20 | #define FPGA_DMA_DONE 0b00001 //DONE 21 | #define FPGA_DMA_BUSY 0b00010 //BUSY 22 | #define FPGA_DMA_REOP 0b00100 //REOP 23 | #define FPGA_DMA_WEOP 0b01000 //WEOP 24 | #define FPGA_DMA_LEN 0b10000 //LEN 25 | 26 | //MACROS to more easily program the control register 27 | #define FPGA_DMA_BYTE_TRANSFERS 0b0000000000001 //BYTE 28 | #define FPGA_DMA_HALFWORD_TRANSFERS 0b0000000000010 //HW 29 | #define FPGA_DMA_WORD_TRANSFERS 0b0000000000100 //WORD 30 | #define FPGA_DMA_GO 0b0000000001000 //GO 31 | #define FPGA_DMA_INTERRUPT_ENABLE 0b0000000010000 //I_EN 32 | #define FPGA_DMA_END_RD_END_OF_PACKET 0b0000000100000 //REEN 33 | #define FPGA_DMA_END_WR_END_OF_PACKET 0b0000001000000 //WEEN 34 | #define FPGA_DMA_END_WHEN_LENGHT_ZERO 0b0000010000000 //LEEN 35 | #define FPGA_DMA_READ_CONSTANT_ADDR 0b0000100000000 //RCON 36 | #define FPGA_DMA_WRITE_CONSTANT_ADDR 0b0001000000000 //WCON 37 | #define FPGA_DMA_DOUBLEWORD_TRANSFERS 0b0010000000000 //DOUBLEWORD 38 | #define FPGA_DMA_QUADWORD_TRANSFERS 0b0100000000000 //QUADWORD 39 | #define FPGA_DMA_SOFTWARE_RESET 0b1000000000000 //SOFTWARE_RESET 40 | 41 | //-----------------Generic functions--------------------// 42 | uint32_t fpga_dma_read_reg(void* addr, uint32_t reg); 43 | void fpga_dma_write_reg(void* addr, uint32_t reg, uint32_t val); 44 | uint32_t fpga_dma_read_bit(void* addr, uint32_t reg, uint32_t bit); 45 | void fpga_dma_write_bit(void* addr, uint32_t reg, uint32_t bit, uint32_t val); 46 | 47 | //------------Some specific functions-------------------// 48 | void fpga_dma_init(); 49 | void fpga_dma_config_transfer(void* addr, void* src, void* dst, unsigned int size); 50 | void fpga_dma_start_transfer(void* addr); 51 | uint32_t fpga_dma_transfer_done(void* addr); 52 | void* align_malloc (size_t size, void** unaligned_addr); 53 | 54 | #endif // __FPGA_DMAC_API__ 55 | -------------------------------------------------------------------------------- /Linux-applications/Test_DMA_PL330_LKM/Makefile: -------------------------------------------------------------------------------- 1 | # 2 | TARGET = test_DMA_PL330_LKM 3 | 4 | #Compile with the toolchain from Angstrom 2013.12 compilation 5 | CROSS_COMPILE := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/sysroots/x86_64-linux/usr/bin/armv7ahf-vfp-neon-angstrom-linux-gnueabi/arm-angstrom-linux-gnueabi- 6 | #Compile from SOC EDS toolchain (from Altera Embedded Command Shell ) 7 | #CROSS_COMPILE := arm-linux-gnueabihf- 8 | 9 | CFLAGS = -g -Wall -I ${SOCEDS_DEST_ROOT}/ip/altera/hps/altera_hps/hwlib/include 10 | LDFLAGS = -g -Wall 11 | CC = $(CROSS_COMPILE)gcc 12 | ARCH= arm 13 | 14 | build: $(TARGET) 15 | 16 | $(TARGET): test_DMA_PL330_LKM.o 17 | $(CC) $(LDFLAGS) $^ -o $@ 18 | 19 | %.o : %.c 20 | $(CC) $(CFLAGS) -c $< -o $@ 21 | 22 | .PHONY: clean 23 | clean: 24 | rm -f $(TARGET) *.a *.o *~ 25 | -------------------------------------------------------------------------------- /Linux-applications/Test_DMA_PL330_LKM/README.md: -------------------------------------------------------------------------------- 1 | Test_DMA_PL330_LKM 2 | =============== 3 | 4 | Introduction 5 | ------------- 6 | This application tests the [DMA_PL330_LKM](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM) kernel module and also shows how to use it. DMA_PL330_LKM is a module that permits application-FPGA transfers using the DMA controller PL330 available in HPS. It uses character driver interface to communicate to application space. The entry /dev/dma_pl330 is created when the driver is inserted and afterwards the FPGA can be accessed as a file with the regular functions open(), read(), write() and close(). 7 | 8 | In the FPGA should be a memory with space enough for the transfers. For this purpose the [FPGA_OCR_256K](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC/FPGA_OCR_256K) project in this repository can be used. 9 | 10 | Description of the code 11 | ------------------------ 12 | Test_DMA_PL330_LKM first generates a virtual address to access FPGA from application space, using mmap(). This is needed to check if the transfers done by the driver are being done in proper way. After that the driver is configured using a sysfs entry in /sys/dma_pl330/. Lastly the program copies a buffer from application to the FPGA using write() and copies back the content in the FPGA to the application using the read() function. Both operations are checked and a error message is shown if the transfer went wrong. 13 | 14 | The configuration of the module can be controlled with 4 macros on the top of the program: 15 | 16 | * DMA_TRANSFER_SIZE: Size of the DMA transfer in Bytes. Only used when PREPARE_MICROCODE_WHEN_OPEN = 1. Otherwise the size of the DMA transfer is the size passed as argument in read() and write() functions. 17 | 18 | * USE_ACP: When 0 the PL330 DMAC will copy data from/to FPGA to/from an un-cached buffer in processor memory using the port connecting L3 and SDRAMC. When 1 the access is through ACP port using a cached buffer. 19 | 20 | * DMA_BUFF_PADD: This is the physical address in the FPGA were the module is going to copy data from the application space. When using the [FPGA_OCR_256K](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC/FPGA_OCR_256K) project this address is 0xC0000000 (0xC0000000 in the processor address space 0x00000000 in the HPS-FPGA bridge address space). 21 | 22 | * PREPARE_MICROCODE_WHEN_OPEN: PL330 DMA Controller executes a microcode defining the DMA transfer to be done. When PREPARE_MICROCODE_WHEN_OPEN = 0, the microcode is prepared before every transfer when entering the write() or read() function. When PREPARE_MICROCODE_WHEN_OPEN = 1 the microcode is prepared when calling the open() function (two microcodes are generated: one for read FPGA and another for write to FPGA). Later when using read() or write() the prepared microcodes are used. This saves the microcode preparation time when doing the transfer. This is important since DMA microcode preparation time goes from DMAC 10% of the transfer time (for data sizes between 128kB and 2MB) to 75% (for data sizes between 2B and 8kB). 23 | 24 | Contents in the folder 25 | ---------------------- 26 | * test_DMA_PL330_LKM.c: all code of the program is here. 27 | * Makefile: describes compilation process. 28 | 29 | Compilation 30 | ----------- 31 | If you wanna use the compiler used to compile the [DMA_PL330_LKM](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM) driver, just open a Linux Terminal, navigate until the folder of the project and type **_make_**. 32 | 33 | If you are in Windows or you do not have available the toolchain used to compile [DMA_PL330_LKM](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM) driver you can compile with the compiler in Intel FPGA SoC EDS. Modify the makefile to point to the correct toolchain (comment the toolchain used to compile the driver and uncomment the SoC EDS toolchain). Then open *SoC EDS Command Shell* (*Intel FPGA SoC EDS* needs to be installed in your system), navigate to the folder of the example and type **_make_**. 34 | This program was tested with Intel *FPGA SoC EDS v16.1*. 35 | 36 | The compilation process generates the executable file *test_DMA_PL330_LKM* in both cases. 37 | 38 | How to test 39 | ------------ 40 | * Configure MSEL pins (only if FPGA is used): 41 | * MSEL[5:0]="000000" position when FPGA will be configured from SD card. 42 | * MSEL[5:0]="110010" position when FPGA will be configured from EPCQ device or Quartus programmer. 43 | * Switch on the board. 44 | * Compile the FPGA hardware ([FPGA_OCR_256K](https://github.com/robertofem/CycloneVSoC-examples/tree/master/FPGA-hardware/DE1-SoC/FPGA_OCR_256K) in example) and load it in the FPGA (only if FPGA is used): 45 | * If MSEL[5:0]="000000" FPGA is loaded by the U-boot during start-up. Check the [tutorials to build a SD card with Operating System](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system) to learn how to configure the SD card so the FPGA is loaded from it. 46 | * If MSEL[5:0]="110010" use Quartus to load the FPGA: 47 | * Connect the USB cable (just next to the power connector). 48 | * Open Quartus programmer. 49 | * Click Autodetect -> Mode JTAG -> Select 5CSEMA5 (for DE1-SoC and DE0-nano-SoC) if asked -> Right click in the line representing the FPGA -> Change FIle -> Select the .sof file for the project you want to load -> tick Program/Configure -> Click Start. 50 | 51 | * Connect the serial console port (the mini-USB port in DE1-SoC) to the computer and open a session with a Seral Terminal (like Putty) at 115200 bauds. Now you have access to the board OS console. 52 | * Copy the [DMA_PL330_LKM](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM) module in the SD card and insert it into the kernel using _insmod_ command: 53 | ```bash 54 | $ insmod DMA_PL330.ko 55 | ``` 56 | > Remember. The version of the kernel for which the driver is compiled for should be the same running in the board. This implies that you have to compile the OS you are running in the board and compile the driver with the output files from that compilation. In the [tutorials to build a SD card with Operating System](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system) and in the [DMA_PL330_LKM folder](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM) you can find more information about compiling an Operating System and a Loadable Kernel Moduler (LKM) respectively. 57 | 58 | * Copy the executable into the SD card and run the application: 59 | ```bash 60 | $ chmod 777 Test_DMA_PL330_LKM 61 | $ ./Test_DMA_PL330_LKM 62 | ``` 63 | -------------------------------------------------------------------------------- /Linux-applications/Test_DMA_PL330_LKM/test_DMA_PL330_LKM.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include 9 | 10 | //Constants to do mmap and get access to FPGA peripherals 11 | #define HPS_FPGA_BRIDGE_BASE 0xC0000000 12 | #define HW_REGS_BASE ( HPS_FPGA_BRIDGE_BASE ) 13 | #define HW_REGS_SPAN ( 0x04000000 ) 14 | #define HW_REGS_MASK ( HW_REGS_SPAN - 1 ) 15 | #define ON_CHIP_MEMORY_BASE 0 //FPGA On-Chip RAM address relative to H2F bridge 16 | 17 | //MACROS TO CONTROL THE TRANSFER 18 | #define DMA_TRANSFER_SIZE 32 19 | #define USE_ACP 1 //0 do not use acp, 1 use acp 20 | //DMA_BUFF_PADD: 21 | //physical address of the buffer used when reading and writing using dma driver 22 | //in this case we set 0xC0000000, the beginning of the HPS-FPGA BRIDGE 23 | //In this address there should be a memory with enough space to do the transfer 24 | #define DMA_BUFF_PADD (HPS_FPGA_BRIDGE_BASE + ON_CHIP_MEMORY_BASE) 25 | //PREPARE_MICROCODE_WHEN_OPEN: 26 | //0 prepare microcode when write or read 27 | //1 prepare microcode when open. It saves microcode preparation time 28 | //later when calling read and write 29 | #define PREPARE_MICROCODE_WHEN_OPEN 0 30 | 31 | 32 | void printbuff(char* buff, int size) 33 | { 34 | int i; 35 | printf("["); 36 | for (i=0; i with n from 0 to 4. 11 | Using this entries each buffer can be accessed as a file. When using open() 12 | the buffer is allocated. When using read() and write() the buffer is read or written, respectively. When using close() the buffer is freed. 13 | 14 | To control the behaviour of the buffers there is a set of sysfs variables created in /sys/alloc_dmable_buffers/attributes that can be accessed from console or from an application (also using open(), write(), read() and close()): 15 | 16 | * buff_size[n] with n from 0 to 4. They define the size of the buffer. Use it before using open() in /dev/dmable_buff because thats the moment the buffer is allocated. 17 | It is 1024 by default. 18 | * buff_uncached[n] with n from 0 to 4. It defines if the buffer is cached (buff_uncached[n] = 0) or uncached (buff_uncached[n] = 1). Use cached to access through 19 | ACP and uncached to directly access the SDRAM controller (L3->SDRAMC or FPGA-SDRAMC ports). Use it before using open() in /dev/dmable_buff because thats the moment the buffer is allocated and its type defined. 0 by default. 20 | * phys_buff[n] with n from 0 to 4. It provides the physical address of the allocated buffer. Use it after using open() in /dev/dmable_buff. This address should be used 21 | by the hardware (i.e. a DMA COntroller in FPGA) to access the buffer. Remember to add 0x80000000 to this address if ACP is used. 22 | 23 | Description of the code 24 | ------------------------ 25 | 26 | The insertion and removal functions, available in every driver are: 27 | 28 | * dmable_buff_init: executed when the module is inserted using _insmod_. It: 29 | 30 | * exports the control variables using sysfs in /sys/alloc_dmable_buffers/attributes/, 31 | * creates the char device driver interfaces in /dev/dmable_buff/, 32 | * configures ACP so it can be used 33 | * Removes FPGA-to-SDRAM ports from reset so they can be used. 34 | * and enables PMU to be accessed from user space (the same performed by [Enable_PMU_user_space](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/Enable_PMU_user_space)). 35 | 36 | * dmable_buff_exit: executed when using _rmmod_. It reverts all what was done by dmable_buff_init so the system remains clean, just exactly the same as before the driver was inserted. 37 | 38 | The char device driver interface functions, to be used over /dev/dmable_buff are: 39 | * dmable_buff_open: called when open() is used. It allocates a buffer with the size and the cache behaviour (cached or uncached) defined by buff_size[n] buff_uncached[n]. 40 | 41 | * dmable_buff_write: executed when write() is used. It writes content in the buffer starting at the beginning always. 42 | 43 | * dmable_buff_read: executed when read() is used. It reads content from the buffer starting at the beginning always. 44 | 45 | * dev_release: executed when close() is used. It frees the buffer. 46 | 47 | Contents in the folder 48 | ---------------------- 49 | * alloc_dmable_buffer_LKM.c: main file containing the code just explained before. 50 | * alt_acpidmap.h, alt_address_space.c, alt_address_space.h, hwlib_socal_linux: code needed to enable the ACP. They were copied from [DMA_PL330_LKM](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-modules/DMA_PL330_LKM). More information in the README of that module. 51 | * Makefile: describes compilation process. 52 | 53 | Compilation 54 | ------------- 55 | To compile the driver you need to first compile the Operating System (OS) you will use to run the driver, otherwise the console will complain that it cannot insert the driver cause the tag of your module is different to the tag of the OS you are running. It does that to ensure that the driver will work. Therefore: 56 | 57 | * Compile the OS you will use. In [tutorials to build a SD card with Operating System](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system) there are examples on how to compile OS and how to prepare the environment to compile drivers. 58 | * Prepare the make file you will use to compile the module. The makefile provided in this example is prepared to compile using the output of the [Angstrom-v2013.12](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system/Angstrom-v2013.12) compilation process. CROSS_COMPILE contains the path of the compilers used to compile this driver. ROOTDIR is the path to the kernel compiled source. It is used by the driver to get access to the header files used in the compilation (linux/module.h or linux/kernel.h in example). 59 | * Open a regular terminal (I used Debian 8 to compile Angstrom-v2013.12 and its drivers), navigate until the driver folder and tipe _make_. 60 | 61 | The output of the compilation is the file _alloc_dmable_buffer.ko_. 62 | 63 | How to test 64 | ----------- 65 | The following example shows how to use the driver: [DMA_transfer_FPGA_DMAC_driver](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Linux-applications/DMA_transfer_FPGA_DMAC_driver). 66 | -------------------------------------------------------------------------------- /Linux-modules/Alloc_DMAble_buff_LKM/alloc_dmable_buffer.ko: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/Alloc_DMAble_buff_LKM/alloc_dmable_buffer.ko -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM/DMA_Data_Paths.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/DMA_PL330_LKM/DMA_Data_Paths.png -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM/DMA_PL330.ko: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/DMA_PL330_LKM/DMA_PL330.ko -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM/Makefile: -------------------------------------------------------------------------------- 1 | #Name of the module 2 | obj-m := DMA_PL330.o 3 | #Files composing the module 4 | DMA_PL330-objs := DMA_PL330_LKM.o alt_dma.o alt_dma_program.o alt_address_space.o 5 | 6 | #guest architecture 7 | ARCH := arm 8 | 9 | #compiler 10 | CROSS_COMPILE := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/sysroots/x86_64-linux/usr/bin/armv7ahf-vfp-neon-angstrom-linux-gnueabi/arm-angstrom-linux-gnueabi- 11 | 12 | #path to the compiled kernel 13 | ROOTDIR := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/work/socfpga_cyclone5-angstrom-linux-gnueabi/linux-altera-ltsi/3.10-r1/git 14 | 15 | MAKEARCH := $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) 16 | 17 | all: modules 18 | modules: 19 | $(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} modules 20 | clean: 21 | $(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} clean 22 | -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM/alt_dma_common.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2013 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. Neither the name of the copyright holder nor the names of its contributors 16 | * may be used to endorse or promote products derived from this software without 17 | * specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ******************************************************************************/ 32 | 33 | /* 34 | * $Id: //acds/rel/16.1/embedded/ip/hps/altera_hps/hwlib/include/alt_dma_common.h#1 $ 35 | */ 36 | 37 | #ifndef __ALT_DMA_COMMON_H__ 38 | #define __ALT_DMA_COMMON_H__ 39 | 40 | #include "alt_dma_periph_cv_av.h" 41 | 42 | #ifdef __cplusplus 43 | extern "C" 44 | { 45 | #endif /* __cplusplus */ 46 | 47 | /*! 48 | * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions 49 | * 50 | * This module contains the common definitions for the DMA controller related 51 | * APIs. 52 | * 53 | * @{ 54 | */ 55 | 56 | /*! 57 | * This type definition enumerates the DMA controller channel threads. 58 | */ 59 | typedef enum ALT_DMA_CHANNEL_e 60 | { 61 | ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */ 62 | ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */ 63 | ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */ 64 | ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */ 65 | ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */ 66 | ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */ 67 | ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */ 68 | ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */ 69 | } 70 | ALT_DMA_CHANNEL_t; 71 | 72 | /*! 73 | * This type enumerates the DMA security state options available. 74 | */ 75 | typedef enum ALT_DMA_SECURITY_e 76 | { 77 | ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ 78 | ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ 79 | ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ 80 | } 81 | ALT_DMA_SECURITY_t; 82 | 83 | /*! 84 | * This type definition enumerates the DMA event-interrupt resources. 85 | */ 86 | typedef enum ALT_DMA_EVENT_e 87 | { 88 | ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ 89 | ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ 90 | ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ 91 | ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ 92 | ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ 93 | ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ 94 | ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ 95 | ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ 96 | ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ 97 | } 98 | ALT_DMA_EVENT_t; 99 | 100 | /*! 101 | * @} 102 | */ 103 | 104 | #ifdef __cplusplus 105 | } 106 | #endif /* __cplusplus */ 107 | 108 | #endif /* __ALT_DMA_COMMON_H__ */ 109 | -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM/alt_dma_periph_cv_av.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2015 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. Neither the name of the copyright holder nor the names of its contributors 16 | * may be used to endorse or promote products derived from this software without 17 | * specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ******************************************************************************/ 32 | 33 | /* 34 | * $Id: //acds/rel/16.1/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_dma_periph.h#1 $ 35 | */ 36 | 37 | #ifndef __ALT_DMA_PERIPH_H__ 38 | #define __ALT_DMA_PERIPH_H__ 39 | 40 | #ifdef __cplusplus 41 | extern "C" 42 | { 43 | #endif 44 | 45 | /*! 46 | * This type definition enumerates the SoC system peripherals implementing the 47 | * required request interface that enables direct DMA transfers to/from the 48 | * device. 49 | * 50 | * FPGA soft IP interface to the DMA are required to comply with the Synopsys 51 | * protocol. 52 | * 53 | * Request interface numbers 4 through 7 are multiplexed between the CAN 54 | * controllers and soft logic implemented in the FPGA fabric. The selection 55 | * between the CAN controller and FPGA interfaces is determined at DMA 56 | * initialization. 57 | */ 58 | typedef enum ALT_DMA_PERIPH_e 59 | { 60 | ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */ 61 | ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */ 62 | ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */ 63 | ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */ 64 | 65 | ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */ 66 | ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */ 67 | ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */ 68 | ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */ 69 | 70 | ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ 71 | ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ 72 | ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ 73 | ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ 74 | 75 | ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ 76 | ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ 77 | ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ 78 | ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ 79 | 80 | ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I2C 0 TX */ 81 | ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ 82 | ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ 83 | ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ 84 | ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ 85 | ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ 86 | ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ 87 | ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ 88 | ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ 89 | ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ 90 | ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ 91 | ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ 92 | ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ 93 | ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ 94 | ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ 95 | ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ 96 | ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ 97 | ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ 98 | ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ 99 | ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ 100 | ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ 101 | ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ 102 | ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ 103 | ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ 104 | } 105 | ALT_DMA_PERIPH_t; 106 | 107 | #ifdef __cplusplus 108 | } 109 | #endif 110 | 111 | #endif /* __ALT_DMA_PERIPH_H__ */ 112 | -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM_basic/DMA_PL330_basic.ko: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/DMA_PL330_LKM_basic/DMA_PL330_basic.ko -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM_basic/Four-examples.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/DMA_PL330_LKM_basic/Four-examples.png -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM_basic/Makefile: -------------------------------------------------------------------------------- 1 | #Name of the module 2 | obj-m := DMA_PL330_basic.o 3 | #Files composing the module 4 | DMA_PL330_basic-objs := DMA_PL330_LKM_basic.o alt_dma.o alt_dma_program.o alt_address_space.o 5 | 6 | #guest architecture 7 | ARCH := arm 8 | 9 | #compiler 10 | CROSS_COMPILE := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/sysroots/x86_64-linux/usr/bin/armv7ahf-vfp-neon-angstrom-linux-gnueabi/arm-angstrom-linux-gnueabi- 11 | 12 | #path to the compiled kernel 13 | ROOTDIR := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/work/socfpga_cyclone5-angstrom-linux-gnueabi/linux-altera-ltsi/3.10-r1/git 14 | 15 | MAKEARCH := $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) 16 | 17 | all: modules 18 | modules: 19 | $(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} modules 20 | clean: 21 | $(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} clean 22 | -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM_basic/alt_dma_common.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2013 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. Neither the name of the copyright holder nor the names of its contributors 16 | * may be used to endorse or promote products derived from this software without 17 | * specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ******************************************************************************/ 32 | 33 | /* 34 | * $Id: //acds/rel/16.1/embedded/ip/hps/altera_hps/hwlib/include/alt_dma_common.h#1 $ 35 | */ 36 | 37 | #ifndef __ALT_DMA_COMMON_H__ 38 | #define __ALT_DMA_COMMON_H__ 39 | 40 | #include "alt_dma_periph_cv_av.h" 41 | 42 | #ifdef __cplusplus 43 | extern "C" 44 | { 45 | #endif /* __cplusplus */ 46 | 47 | /*! 48 | * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions 49 | * 50 | * This module contains the common definitions for the DMA controller related 51 | * APIs. 52 | * 53 | * @{ 54 | */ 55 | 56 | /*! 57 | * This type definition enumerates the DMA controller channel threads. 58 | */ 59 | typedef enum ALT_DMA_CHANNEL_e 60 | { 61 | ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */ 62 | ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */ 63 | ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */ 64 | ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */ 65 | ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */ 66 | ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */ 67 | ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */ 68 | ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */ 69 | } 70 | ALT_DMA_CHANNEL_t; 71 | 72 | /*! 73 | * This type enumerates the DMA security state options available. 74 | */ 75 | typedef enum ALT_DMA_SECURITY_e 76 | { 77 | ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */ 78 | ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */ 79 | ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */ 80 | } 81 | ALT_DMA_SECURITY_t; 82 | 83 | /*! 84 | * This type definition enumerates the DMA event-interrupt resources. 85 | */ 86 | typedef enum ALT_DMA_EVENT_e 87 | { 88 | ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */ 89 | ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */ 90 | ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */ 91 | ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */ 92 | ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */ 93 | ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */ 94 | ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */ 95 | ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */ 96 | ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */ 97 | } 98 | ALT_DMA_EVENT_t; 99 | 100 | /*! 101 | * @} 102 | */ 103 | 104 | #ifdef __cplusplus 105 | } 106 | #endif /* __cplusplus */ 107 | 108 | #endif /* __ALT_DMA_COMMON_H__ */ 109 | -------------------------------------------------------------------------------- /Linux-modules/DMA_PL330_LKM_basic/alt_dma_periph_cv_av.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * 3 | * Copyright 2015 Altera Corporation. All Rights Reserved. 4 | * 5 | * Redistribution and use in source and binary forms, with or without 6 | * modification, are permitted provided that the following conditions are met: 7 | * 8 | * 1. Redistributions of source code must retain the above copyright notice, 9 | * this list of conditions and the following disclaimer. 10 | * 11 | * 2. Redistributions in binary form must reproduce the above copyright notice, 12 | * this list of conditions and the following disclaimer in the documentation 13 | * and/or other materials provided with the distribution. 14 | * 15 | * 3. Neither the name of the copyright holder nor the names of its contributors 16 | * may be used to endorse or promote products derived from this software without 17 | * specific prior written permission. 18 | * 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 | * POSSIBILITY OF SUCH DAMAGE. 30 | * 31 | ******************************************************************************/ 32 | 33 | /* 34 | * $Id: //acds/rel/16.1/embedded/ip/hps/altera_hps/hwlib/include/soc_cv_av/alt_dma_periph.h#1 $ 35 | */ 36 | 37 | #ifndef __ALT_DMA_PERIPH_H__ 38 | #define __ALT_DMA_PERIPH_H__ 39 | 40 | #ifdef __cplusplus 41 | extern "C" 42 | { 43 | #endif 44 | 45 | /*! 46 | * This type definition enumerates the SoC system peripherals implementing the 47 | * required request interface that enables direct DMA transfers to/from the 48 | * device. 49 | * 50 | * FPGA soft IP interface to the DMA are required to comply with the Synopsys 51 | * protocol. 52 | * 53 | * Request interface numbers 4 through 7 are multiplexed between the CAN 54 | * controllers and soft logic implemented in the FPGA fabric. The selection 55 | * between the CAN controller and FPGA interfaces is determined at DMA 56 | * initialization. 57 | */ 58 | typedef enum ALT_DMA_PERIPH_e 59 | { 60 | ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */ 61 | ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */ 62 | ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */ 63 | ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */ 64 | 65 | ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */ 66 | ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */ 67 | ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */ 68 | ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */ 69 | 70 | ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ 71 | ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ 72 | ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ 73 | ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ 74 | 75 | ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */ 76 | ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */ 77 | ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */ 78 | ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */ 79 | 80 | ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I2C 0 TX */ 81 | ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I2C 0 RX */ 82 | ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I2C 1 TX */ 83 | ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I2C 1 RX */ 84 | ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I2C 2 TX */ 85 | ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I2C 2 RX */ 86 | ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I2C 3 TX */ 87 | ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I2C 3 RX */ 88 | ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */ 89 | ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */ 90 | ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */ 91 | ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */ 92 | ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */ 93 | ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */ 94 | ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */ 95 | ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */ 96 | ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */ 97 | ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */ 98 | ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */ 99 | ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */ 100 | ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */ 101 | ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */ 102 | ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */ 103 | ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */ 104 | } 105 | ALT_DMA_PERIPH_t; 106 | 107 | #ifdef __cplusplus 108 | } 109 | #endif 110 | 111 | #endif /* __ALT_DMA_PERIPH_H__ */ 112 | -------------------------------------------------------------------------------- /Linux-modules/Enable_PMU_user_space/Makefile: -------------------------------------------------------------------------------- 1 | MODULES := PMU_User_Space_EN.o 2 | 3 | #guest architecture 4 | ARCH := arm 5 | 6 | #compiler 7 | CROSS_COMPILE := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/sysroots/x86_64-linux/usr/bin/armv7ahf-vfp-neon-angstrom-linux-gnueabi/arm-angstrom-linux-gnueabi- 8 | 9 | obj-m := $(MODULES) 10 | 11 | #path to the compiled kernel 12 | ROOTDIR := ~/angstrom-socfpga/build/tmp-angstrom_v2013_12-eglibc/work/socfpga_cyclone5-angstrom-linux-gnueabi/linux-altera-ltsi/3.10-r1/git 13 | 14 | MAKEARCH := $(MAKE) ARCH=$(ARCH) CROSS_COMPILE=$(CROSS_COMPILE) 15 | 16 | all: modules 17 | modules: 18 | $(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} modules 19 | 20 | clean: 21 | $(MAKEARCH) -C $(ROOTDIR) M=${shell pwd} clean 22 | -------------------------------------------------------------------------------- /Linux-modules/Enable_PMU_user_space/PMU_User_Space_EN.c: -------------------------------------------------------------------------------- 1 | //file: PMU_User_Space_EN.c 2 | 3 | /*PMU is a coprocessor located very close to the processor in ARM 4 | Cortex-A9. It is in charge of gatheric statistics from the processor, 5 | i.e. the number of exceptions, divisions by 0, etc. Each processor 6 | core has its own PMU. In case of Cyclone V the processor has two 7 | cores and therefore two PMUs. PMU is not mapped in the address 8 | space of the processor. It is accessed through instructions like 9 | the mathematical cores Neon. 10 | The PMU has a CPU clock cycle counter that can be used to measure 11 | time. To measure time with PMU is not a good practice because 12 | PMU counts cycles from PMU clock, not time. Therefore if the clock 13 | rate of the CPU changes (i.e. it is reduced to save energy) the 14 | time measurement will be wrong. The advantage of using the PMU 15 | is that it measures time very precisely, more than any OS clock. 16 | Therefore if clock rate is stable and we know its rate we can 17 | measure time very precisely with PMU. A good practise is to use 18 | an OS timer together with PMU to verify that the PMU measurement 19 | is correct. 20 | When using OS, PMU is not accessible from user space by default. 21 | However setting the PMUSERENR.EN bit it can be accessed from 22 | user space. This module accesses from kernel space to the PMU 23 | and sets PMUSERENR.EN bit. After inserting this module therefore 24 | the PMU will be able to be accessed from any application running 25 | in user space. 26 | */ 27 | #include 28 | 29 | static int mod_init(void) 30 | { 31 | 32 | int var = 0; 33 | 34 | pr_info("Module initialization\n"); 35 | 36 | //Generic read and write demonstration using register r3 37 | //asm volatile ("mov r3, %[value]"::[value]"r" (var)); //write (var int) 38 | //asm volatile ("mov %[value], r3":[value]"+r" (var)); //read (var int) 39 | 40 | //Enable PMU from user space setting PMUSERENR.EN bit 41 | asm volatile("mrc p15, 0, %[value], c9, c14, 0":[value]"+r" (var));//read PMUSERENR 42 | pr_info("PMU User Enable register=%d\n", var);//print PMUSERENR 43 | 44 | var = 1; 45 | pr_info("Enabling PMU\n"); 46 | asm volatile("mcr p15, 0, %[value], c9, c14, 0"::[value]"r" (var));//Set PMUSERENR.EN 47 | 48 | var = 2; 49 | asm volatile("mrc p15, 0, %[value], c9, c14, 0":[value]"+r" (var));//read PMUSERENR 50 | pr_info("PMU User Enable register=%d\n", var);//print PMUSERENR 51 | 52 | return 0; 53 | } 54 | static void mod_exit(void) 55 | { 56 | pr_info("Module exit\n"); 57 | } 58 | 59 | module_init(mod_init); 60 | module_exit(mod_exit); 61 | 62 | MODULE_LICENSE("GPL"); 63 | MODULE_AUTHOR("Roberto Fernández "); 64 | MODULE_AUTHOR("Filipe Salgado "); 65 | MODULE_DESCRIPTION("Make PMU coprocessor registers accesible from user space"); 66 | MODULE_VERSION("1.0"); 67 | -------------------------------------------------------------------------------- /Linux-modules/Enable_PMU_user_space/PMU_User_Space_EN.ko: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/Enable_PMU_user_space/PMU_User_Space_EN.ko -------------------------------------------------------------------------------- /Linux-modules/Enable_PMU_user_space/README.md: -------------------------------------------------------------------------------- 1 | Enable_PMU_User_Space 2 | ===================== 3 | 4 | Introduction 5 | ------------- 6 | PMU (Performance Monitoring Unit) is a coprocessor tightly coupled with ARM CPUs. It is in charge of gathering statistics from the processor, i.e. the number of exceptions, divisions by 0, etc. Each processor core has its own PMU. In case of Cyclone V SoC the processor has two cores and therefore two PMUs. When using Operating System (OS) there are 2 options to use PMU extracted from [[1](http://neocontra.blogspot.com.es/2013/05/user-mode-performance-counters-for.html)] and [[2](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html)]: 7 | 8 | 1. Access from user space. By default PMU coprocessor is only accessible from kernel mode. To be able to use the PMU from user space a bit in PMU should be activated from kernel space using a kernel module. PMU knows from where it is accessed because there is a bit in the status word of the CPU that flags if the instructions being executed are from kernel or user space. 9 | 2. Access from kernel mode; that is, from a kernel module. 10 | 11 | Both options require writing a module for the Linux Kernel. We find that working from user space is faster (because there is no overhead added when calling kernel module functions), easier (writing applications is easier than writing kernel modules) and safer (from kernel space you have access to resources and memory positions that can crash the whole OS) than doing it from kernel space. For this reasons we decided to write this module that activates the correct bit and permits PMU to be accessed from user space. 12 | 13 | PMU is not mapped in the address space of the processor. It is accessed through instructions like the Neon coprocessors. Before writing this drivers we just tried to access PMU with the following program: 14 | 15 | ```c 16 | #include 17 | int main(){ 18 | 19 | //Read a register of the PMU 20 | asm volatile("mrc p15, 0, r0, c9, c12, 0"); 21 | 22 | return 0; 23 | } 24 | ``` 25 | 26 | And the result is: 27 | 28 | 29 |

30 | Cyclone V SoC simplified block diagram 31 |

32 | 33 | This completely proofs the need of this module. 34 | 35 | We used this module to perform accurate time measuremets from Linux applications. The baremetal project [Second_counter_PMU](https://github.com/robertofem/CycloneVSoC-examples/tree/master/Baremetal-applications/Second_counter_PMU) is an example on how to use the PMU to measure time. The same code can be compiled without changes into a Linux Application. 36 | 37 | Description of the code 38 | --------------------------- 39 | From section B6.1.81 of the [[2](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html)]: To access from user space to PMU registers it is needed to set to 1 the bit PMUSERENR.EN. 40 | 41 | This LKM only contains the two most basic functions: _init_ and _exit_ functions. They perform the followng tasks: 42 | 43 | * mod_init: executed when the module is inserted using _insmod_. It: 44 | 45 | * Reads the content of PMUSERENR.EN and prints it. 46 | * Sets to 1 PMUSERENR.EN to enable access from user space. 47 | * Reads the content again of PMUSERENR.EN and prints it. 48 | 49 | * mod_exit: executed when using _rmmod_. Does nothing. 50 | 51 | 52 | Contents in the folder 53 | ---------------------- 54 | * PMU_User_Space_EN.c: main file containing the code just explained before. 55 | * Makefile: describes compilation process. 56 | 57 | Compilation 58 | ------------- 59 | To compile the driver you need to first compile the Operating System (OS) you will use to run the driver, otherwise the console will complain that it cannot insert the driver cause the tag of your module is different to the tag of the OS you are running. It does that to ensure that the driver will work. Therefore: 60 | 61 | * Compile the OS you will use. In [tutorials to build a SD card with Operating System](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system) there are examples on how to compile OS and how to prepare the environment to compile drivers. 62 | * Prepare the make file you will use to compile the module. The makefile provided in this example is prepared to compile using the output of the [Angstrom-v2013.12](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system/Angstrom-v2013.12) compilation process. CROSS_COMPILE contains the path of the compilers used to compile this driver. ROOTDIR is the path to the kernel compiled source. It is used by the driver to get access to the header files used in the compilation (linux/module.h or linux/kernel.h in example). 63 | * Open a regular terminal (I used Debian 8 to compile Angstrom-v2013.12 and its drivers), navigate until the driver folder and type _make_. 64 | 65 | The output of the compilation is the file _PMU_User_Space_EN.ko_. 66 | 67 | How to test 68 | ------------ 69 | * Switch on the board. 70 | * Connect the serial console port (the mini-USB port in DE1-SoC) to the computer and open a session with a Serial Terminal (like Putty) at 115200 bauds. Now you have access to the board OS console. 71 | * Copy the _PMU_User_Space_EN.ko_ file in the SD card (using SSH or connecting it to a regular computer running Linux system) and insert it into the kernel using _insmod_ command: 72 | ```bash 73 | $ insmod PMU_User_Space_EN.ko 74 | ``` 75 | * The result is printed in the kernel log that should show say that the value of PMUSERENR.EN is 1. Depending on the configuration of your operating system the messages from the LKM will be directly printed in screen or you will need to use _dmesg_ to see them: 76 | ```bash 77 | $ dmesg 78 | ``` 79 | 80 | Inserting the module will activate the PMU of the processor where the code is running. If the application that later uses PMU accesses it runs in a different core the _illegal instruction_ message will appear again. In that case you can remove and insert the module several times until the CPU where the application is running gets enable. Other option is to use [taskset](http://xmodulo.com/run-program-process-specific-cpu-cores-linux.html) utility (not installed in [Angstrom-v2013.12](https://github.com/robertofem/CycloneVSoC-examples/tree/master/SD-operating-system/Angstrom-v2013.12)) to choose the CPU where you want to run the application. You can run the application in one core and if it does not run just try the other. -------------------------------------------------------------------------------- /Linux-modules/Enable_PMU_user_space/access_PMU_user.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/Linux-modules/Enable_PMU_user_space/access_PMU_user.png -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Cyclone V SoC examples 2 | ==================== 3 | Examples using the FPSoC chip [Cyclone V SoC](https://www.altera.com/products/soc/portfolio/cyclone-v-soc/overview.html). All these examples were tested on DE1-SoC board. However most of them are easily ported to other boards including Cyclone V SoC chips because they do not interact with the hardware in the board. 4 | 5 |

6 | Cyclone V SoC simplified block diagram 7 |

8 | 9 | This repository contains: 10 | 11 | * **Starting-guides**: guides on how to start with Cyclone V SoC boards. Currently 12 | only a guide for DE1-SoC board is available. However the process to 13 | start with any Cyclone V SoC board is similar and this guide can be used 14 | regardless the Cyclone V SoC board used. 15 | 16 | * **Baremetal-applications**: Stand-alone applications without Operating System. 17 | * DMA_transfer_FPGA_DMAC: This example shows how to use a DMA controller in the FPGA to read and write the HPS memories. Transfers can be done with cache switched ON through ACP and with cache switched OFF through the L3-to-SDRAMC port. 18 | * DMA_transfer_PL330_ACP: This is a complete example on moving data using the HPS Direct Memory Access Controller (DMAC) PL330. Data can be moved from a buffer in processor to another buffer in processor or to the FPGA. This example also shows how to switch on the cache memories L1 and L2 and how to configure the ACP port to access cache memories from L3 when caches are on. 19 | * Second_counter_PMU: This example uses a counter in the Performance Monitoring Unit (PMU) timer to measure seconds and build a second counter. It stands as an example on how to use PMU to measure time in baremetal. 20 | 21 | * **FPGA-hardware**: Quartus projects describing the FPGA hardware needed in some of the examples. 22 | * DE1-SoC: Hardware for Terasic´s DE1-SoC board. 23 | * FPGA_DMA: it implements a DMA controller in the FPGA and a 1kB on-chip memory. Using this DMA it is possible to move data between HPS and FPGA using the FPGA as master. 24 | * FPGA_OCR_256K: this hardware project includes a 256kB On-Chip memory in the FPGA, implemented using 10Mb memory blocks. This memory is hanging at the beginning of the address space of the HPS-to-FPGA bridge. 25 | 26 | * **Linux-applications**: 27 | * Test_DMA_PL330_LKM: it shows how to use the DMA\_PL330\_LKM module. 28 | * DMA_transfer_FPGA_DMAC: It transfers data from an On-Chip RAM in FPGA 29 | to On-Chip RAM in HPS and viceversa using a DMA Controller in FPGA. 30 | * DMA_transfer_FPGA_DMAC_driver: It transfers data from an On-Chip RAM in FPGA 31 | to a Buffer in the application using a DMA Controller in the FPGA and the 32 | Alloc_DMAble_buff_LKM module. 33 | 34 | * **Linux-modules**: Linux Loadable Kernel Modules (LKM). 35 | * Alloc_DMAble_buff_LKM: This driver allocates up to 5 physically contiguous 36 | buffers in kernel space and provides its physical addresses through sysfs and 37 | access to the buffer through character device interface. These 38 | buffers are intended to work as intermediate buffers in DMA transfers. 39 | Linux_applications/DMA_transfer_FPGA_DMAC_driver shows how to use it. 40 | * DMA_PL330_LKM_Basic: stand-alone module that makes a data transfer using the PL330 DMAC (available in HPS) when inserted into the operating system. It can be configured to move data between: FPGA memory, HPS On-chip RAM, uncached buffer in processor´s RAM and cached buffer in processor´s RAM (through APC). It is a complete example that can be used as starting point for developing a DMA module for a specific application. 41 | * DMA_PL330_LKM: module to make transfers between an application and the FPGA using PL330 DMAC. It uses char device driver interface to copy the data from application to a uncached or cached (through ACP) buffer in driver´s memory space. Later it uses PL330 DMAC to copy that buffer to FPGA. A /dev/dma_pl330 entry is created so writing in the FPGA is so easy as writing to a file. Linux_applications/Test_DMA_PL330_LKM shows how to use it. 42 | * Enable_PMU_user_space: this module permits access to the Performance Monitoring Unit (PMU) from user space. By default the access from user space is forbidden and a bit must be setting from kernel space to later have access from user space. This module accomplishes that task. 43 | 44 | * **Useful-scripts**: Linux shell scripts to ease configuration of the board. 45 | * fixed_mac_dhcp.sh: fixes MAC and asks IP using DHCP protocol. 46 | 47 | * **SD-baremetal**: This brief tutorial explains how to build a SD card to run the baremetal examples provided in this repository. 48 | 49 | * **SD-operating-system**: It explains how to build an SD card with Operating System from scratch. All the files needed are also provided to save time. Currently the OS that have been tested are: 50 | * Angstrom-v2013.12. 51 | * Angstrom-v2016.12. This tutorial also explains MAC spoofing (to set-up MAC on start-up), custom driver installation and running applications on start-up. 52 | -------------------------------------------------------------------------------- /SD-baremetal/FAT32-partition.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-baremetal/FAT32-partition.png -------------------------------------------------------------------------------- /SD-baremetal/README.md: -------------------------------------------------------------------------------- 1 | SD-baremetal 2 | ============= 3 | 4 | This brief tutorial explains how to build a SD card to run the baremetal examples provided in this repository. 5 | 6 | Ways to configure the FPGA and run the baremetal application 7 | ------------------------------------------------------------ 8 | I have tested two ways to run a baremetal application: 9 | * Using only preloader: the board powers up, loads the preloader from SD card and the preloader directly loads the baremetal application in RAM and runs it. The problem with this approach is that the FPGA configuration cannot be loaded from the SD card before baremetal application runs. The FPGA can be configured later inside the application using the FPGA configuration Manager or easier from EQCP device or directly loading it from Quartus. 10 | * Using the U-boot: the board powers up, loads preloader from SD card and the preloader loads the U-boot. A U-boot script then tells the u-boot to load the FPGA hardware and later jumps into the baremetal application. This way is better because the FPGA is automatically configured before the baremetal application is executed. 11 | 12 | Each way needs its own type of file containing the baremetal app. Thats why the baremetal compilation of all examples generates always two output files: 13 | * baremetalapp.bin.img: to be loaded directly from preloader. 14 | * baremetalapp.bin: to be loaded by the u-boot. 15 | 16 | Steps to build the SD card 17 | -------------------------- 18 | * Create partitions: Create an SD card with the same partitions needed when using Operating System explained in www.rocketboards.com. The partitions are: 19 | * Partition 1. FAT 32 partition containing: 20 | * baremetalapp.bin or baremetalapp.bin.img depending on the boot process. 21 | * soc_system.rbf: FPGA image to be loaded by the u-boot. Only needed when using the U-boot. 22 | * u-boot.img: U-boot image. In most tutorials this image goes in Partition 3. In this case I placed it in FAT32 partition (this way we can change u-boot from a Windows PC). 23 | * u-boot.scr: U-boot script. It is executed by the u-boot. It can change the default behaviour of u-boot. When U-boot finds this file it executes the instructions inside. Otherwise it executes the default behaviour. We use it to load the FPGA configuration and later run the baremetal application. 24 | 25 | * Partition 2: EXT3 partition to store the root file system when using OS (not used in baremetal). 26 | 27 | * Partition 3. RAW (no format) partition containing the preloader image. In most tutorials u-boot image is located in this partition too. 28 | 29 | * Create a preloader: Create a preloader pointing to the next step in the boot process and write it into the partition 3. Remember to remove watchdog otherwise after few seconds the execution of the baremetal application will stop. The preloader is generated using the preloader generator as explained in www.rocketboards.com. When generating the preloader specify: 30 | * "baremetalapp.bin.img" in partition 1 as next step in the boot process when using only preloader boot process. 31 | * "u-boot.img" in partition 1 as next step in the boot process when using U-boot in the boot process. In the current folder a preloader with these characteristics is provided with the name preloader-mkpimage_baremetal_watchdogOFF.bin. 32 | 33 | * Create U-boot (only needed when using u-boot during the boot process): compile U-boot as explained in www.rocketboards.com. For more information visit the u-boot website: http://www.denx.de/wiki/U-Boot/WebHome. The output of the compilation is "u-boot.img." Save it in partition 1. We provide "u-boot.img" in this folder. 34 | * Create U-boot script (only needed when using u-boot during boot process): First create a u-boot script in human readable form describing the U-boot console instructions that should be executed by the u-boot. We do this in a file named u-boot.script. We configure the FPGA with a file named "soc_system.rbf", enable bridges between FPGA and HPS, copy the baremetal app described in a file called "baremetalapp.bin" to RAM memory and then jump the processor to the address where the baremetal app starts. This script file is compiled into a u-boot.src (visit www. rocketboards.com to lear how) and copied in partition 1. We provide both u-boot.src and u-boot.script in this folder. 35 | * Create FPGA bitstream (only needed when using u-boot during boot process): The typical Quartus compilation outputs a .sof file with the FPGA hardware. To load it from the SD card we first need to convert the .sof file into .rbf file. This is done in Quartus->File->Convert Programming Files. The output should be called soc_system.rbf" to match the name used u-boot script for the FPGA configuration file so the u-boot can find it. 36 | * Copy "baremetalapp.bin.img" or "baremetalapp.bin" to the partition 1, depending on the boot process selected (with preloader or with u-boot). 37 | 38 | The following figure shows the aspect of the FAT32 partition when using u-boot: 39 |

40 | Cyclone V SoC simplified block diagram 41 |

42 | 43 | 44 | How to run 45 | ---------- 46 | * Put the SD card in the board. 47 | * Set the MSEL switches: 48 | * into MSEL[5:0]="000000" position when using u-boot so the FPGA can be configured from SD card. 49 | * into MSEL[5:0]="110010" position when using only preloader so the FPGA can be configured by EPCQ device or Quartus programmer. 50 | * Connect the board USB UART into the computer and Open a Serial Terminal session (using Putty or other program) at 115200bauds. 51 | * Switch on the board. -------------------------------------------------------------------------------- /SD-baremetal/preloader-mkpimage_baremetal_watchdogOFF.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-baremetal/preloader-mkpimage_baremetal_watchdogOFF.bin -------------------------------------------------------------------------------- /SD-baremetal/u-boot.img: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-baremetal/u-boot.img -------------------------------------------------------------------------------- /SD-baremetal/u-boot.scr: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-baremetal/u-boot.scr -------------------------------------------------------------------------------- /SD-baremetal/u-boot.script: -------------------------------------------------------------------------------- 1 | fatload mmc 0:1 $fpgadata soc_system.rbf; 2 | fpga load 0 $fpgadata $filesize; 3 | run bridge_enable_handoff; 4 | fatload mmc 0:1 0x00100040 baremetalapp.bin; 5 | go 0x00100040; -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/Angstrom-console-rootfs.tar.gz: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/Angstrom-console-rootfs.tar.gz -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from Terasic/README_terasic.txt: -------------------------------------------------------------------------------- 1 | hps_common_board_info.xml from a guy in rocketboards that ask Terasic for the DE1-SOC .xml files. Terasic gave him this 2 | soc_system_board_info.xml from a guy in rocketboards that ask Terasic for the DE1-SOC .xml files. Terasic gave him this 3 | socfpga.dtb is the obtained dtb with these xmls(to save you time) -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from Terasic/soc_system_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | altr,socfpga-cyclone5 6 | altr,socfpga 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from Terasic/socfpga.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from Terasic/socfpga.dtb -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from WS2/README.txt: -------------------------------------------------------------------------------- 1 | hps_common_board_info.xml from DE0nano folder in Workshop 2 of Altera Workshops 2 | soc_system_board_info.xml drom DE1-SoC GHRD in DE1-SOC CD-ROM 3 | socfpga.dtb is the obtained dtb (to save you time) -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from WS2/hps_common_board_info.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 1 16 | 1 17 | 1 18 | 19 | 20 | 2 21 | 1 22 | 1 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 0 34 | 176 35 | 4 36 | 0 37 | 177 38 | 4 39 | 40 | 41 | 42 | 43 | 44 | 45 | 0xff118000 46 | 0x1000 47 | 48 | 49 | 50 | 51 | 52 | 0xff119000 53 | 0x1000 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 0xffb00000 77 | 0x40000 78 | 79 | 80 | 81 | 0xffb40000 82 | 0x40000 83 | 84 | 85 | 86 | 87 | 88 | -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from WS2/socfpga.dtb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/Files from WS2/socfpga.dtb -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/DTB/README.txt: -------------------------------------------------------------------------------- 1 | Use the files inside one of this folders to build a .dtb that works with Angstrom v2013.12 2 | kernel 3.10lts compiled as in 3 | http://rocketboards.org/foswiki/view/Documentation/AngstromOnSoCFPGA_1 4 | 5 | To build it you will need to have a .sopcinfo file. We used the one in DE1-SoC GHRD previous 6 | Quartus II 14.1 compilation. 7 | 8 | To compile use the following: 9 | sopc2dts --input socsystem.sopcinfo --output socfpga.dtb --type dtb --board hps_common_board_info.xml --board soc_system_board_info.xml --bridge-removal all --clocks -v 10 | -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/README.txt: -------------------------------------------------------------------------------- 1 | ####Files to build an Angstrom 2013.12 SDCard for DE1-SoC board 2 | 3 | * put preloader-mkpimage.bin (using dd) in partition 3. It searches for 4 | * u-boot in FAT32 partition (partition 1), not in partition 3. 5 | * u-boot.img->u-boot image. Just copy it in FAT32 partition (partition 1). 6 | * u-boot.script (loads fpga files, enables bridges and loads OS) 7 | * u-boot.src->compiled u-boot.script. Copy it in n FAT32 partition (partition 1) 8 | * soc_system.rbf->FPGA configuration file. Obtained transforming .sof 9 | (obtained after DE1-SOC GHRD compilation using Quartus 14.1). Copy it 10 | in n FAT32 partition (partition 1). 11 | * zImages-> COntain 3.10lts and 3.18 kernel images of Linux (Obtained 12 | cross-compiling Angstrom 2013.12 in Debian 8 computer. Copy one of the 13 | in n FAT32 partition (partition 1). 14 | * DTB: 2 .dtb files that properly work with 3.10ltsi kernel. They also 15 | work with 3.18 kernel but Ethernet is not detected (this is a problem). 16 | Copy a dtb in n FAT32 partition (partition 1). 17 | * Angstrom-console-image-eglibc-ipk-v2013.12-socfpga_cyclone5.rootfs.targz: 18 | it is the file system fo partition 2 (EXT 3 partition). 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/SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/u-boot.script: -------------------------------------------------------------------------------- 1 | fatload mmc 0:1 $fpgadata soc_system.rbf; 2 | fpga load 0 $fpgadata $filesize; 3 | run bridge_enable_handoff; 4 | run mmcload; 5 | run mmcboot; -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/zImages/3.10ltsi/zImage: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/robertofem/CycloneVSoC-examples/fdee1720fea38249eb1173337f5d7d303a0c0ab8/SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/zImages/3.10ltsi/zImage -------------------------------------------------------------------------------- /SD-operating-system/Angstrom-v2013.12/Files_to_build_SD_DE1-SoC/zImages/3.18/zImage: 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In the lab each MAC has its own IP 4 | #assigned. Since DE1-SoC board generates a new one 5 | #every time it boots, this script fixes a MAC in order 6 | #DHCP running in router can assign a valid IP. 7 | #To watch MAC before and after the change use 8 | #ip link show eth0 9 | 10 | #before changing MAC bring interface down 11 | ip link set dev eth0 down 12 | #change MAC 13 | ip link set dev eth0 address ba:11:24:7d:fd:75 14 | #bring the interface up again 15 | ip link set dev eth0 up 16 | 17 | #Now ask router a new IP 18 | udhcpc 19 | 20 | 21 | 22 | --------------------------------------------------------------------------------