├── .gitignore ├── README.md ├── Sheet1.pdf └── project └── CH32V307VCT6 ├── .cproject ├── .project ├── .settings ├── language.settings.xml └── org.eclipse.core.resources.prefs ├── .template ├── CH32V307VCT6.launch ├── CH32V307VCT6.wvproj ├── Core ├── core_riscv.c └── core_riscv.h ├── Debug ├── debug.c └── debug.h ├── FOC ├── ekf.c ├── ekf.h ├── fast_math.c ├── fast_math.h ├── foc.c ├── foc.h └── rtwtypes.h ├── Ld └── Link.ld ├── Peripheral ├── inc │ ├── ch32v30x.h │ ├── ch32v30x_adc.h │ ├── ch32v30x_bkp.h │ ├── ch32v30x_can.h │ ├── ch32v30x_crc.h │ ├── ch32v30x_dac.h │ ├── ch32v30x_dbgmcu.h │ ├── ch32v30x_dma.h │ ├── ch32v30x_dvp.h │ ├── ch32v30x_eth.h │ ├── ch32v30x_exti.h │ ├── ch32v30x_flash.h │ ├── ch32v30x_fsmc.h │ ├── ch32v30x_gpio.h │ ├── ch32v30x_i2c.h │ ├── ch32v30x_iwdg.h │ ├── ch32v30x_misc.h │ ├── ch32v30x_opa.h │ ├── ch32v30x_pwr.h │ ├── ch32v30x_rcc.h │ ├── ch32v30x_rng.h │ ├── ch32v30x_rtc.h │ ├── ch32v30x_sdio.h │ ├── ch32v30x_spi.h │ ├── ch32v30x_tim.h │ ├── ch32v30x_usart.h │ └── ch32v30x_wwdg.h └── src │ ├── ch32v30x_adc.c │ ├── ch32v30x_bkp.c │ ├── ch32v30x_can.c │ ├── ch32v30x_crc.c │ ├── ch32v30x_dac.c │ ├── ch32v30x_dbgmcu.c │ ├── ch32v30x_dma.c │ ├── ch32v30x_dvp.c │ ├── ch32v30x_eth.c │ ├── ch32v30x_exti.c │ ├── ch32v30x_flash.c │ ├── ch32v30x_fsmc.c │ ├── ch32v30x_gpio.c │ ├── ch32v30x_i2c.c │ ├── ch32v30x_iwdg.c │ ├── ch32v30x_misc.c │ ├── ch32v30x_opa.c │ ├── ch32v30x_pwr.c │ ├── ch32v30x_rcc.c │ ├── ch32v30x_rng.c │ ├── ch32v30x_rtc.c │ ├── ch32v30x_sdio.c │ ├── ch32v30x_spi.c │ ├── ch32v30x_tim.c │ ├── ch32v30x_usart.c │ └── ch32v30x_wwdg.c ├── Startup ├── startup_ch32v30x_D8.S └── startup_ch32v30x_D8C.S ├── User ├── adc.c ├── adc.h ├── ch32v30x_conf.h ├── ch32v30x_it.c ├── ch32v30x_it.h ├── led.c ├── led.h ├── main.c ├── spi.c ├── spi.h ├── system_ch32v30x.c ├── system_ch32v30x.h ├── tim.c └── tim.h └── obj ├── CH32V307VCT6.lst ├── Core └── subdir.mk ├── Debug └── subdir.mk ├── FOC └── subdir.mk ├── Peripheral └── src │ └── subdir.mk ├── Startup └── subdir.mk ├── User └── subdir.mk ├── makefile ├── objects.mk └── sources.mk /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # FOC-EKF 2 | 基于ch32v307vct6芯片的无感FOC代码加无刷驱动板原理图 3 | -------------------------------------------------------------------------------- /Sheet1.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/Sheet1.pdf -------------------------------------------------------------------------------- /project/CH32V307VCT6/.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | CH32V307VCT6 4 | 5 | 6 | 7 | 8 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 9 | clean,full,incremental, 10 | 11 | 12 | 13 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 14 | full,incremental, 15 | 16 | 17 | 18 | 19 | org.eclipse.cdt.core.cnature 20 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 21 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 22 | 23 | 24 | 25 | 1595986042669 26 | 27 | 22 28 | 29 | org.eclipse.ui.ide.multiFilter 30 | 1.0-name-matches-false-false-*.wvproj 31 | 32 | 33 | 34 | 35 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/.settings/org.eclipse.core.resources.prefs: -------------------------------------------------------------------------------- 1 | eclipse.preferences.version=1 2 | encoding//FOC/ekf.c=UTF-8 3 | encoding//FOC/ekf.h=UTF-8 4 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/.template: -------------------------------------------------------------------------------- 1 | Mcu Type=CH32V30x 2 | Target Path=obj\CH32V307VCT6.hex 3 | Address=0x08000000 4 | Erase All=true 5 | Program=true 6 | Verify=true 7 | Reset=true 8 | 9 | Vendor=WCH 10 | Link=WCH-Link 11 | Toolchain=RISC-V 12 | Series=CH32V307 13 | RTOS=NoneOS 14 | Description=Website: http://www.wch.cn/products/CH32V307.html?\nROM(byte): 288K, SRAM(byte): 32K, CHIP PINS: 100, GPIO PORTS: 80.\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. 15 | 16 | PeripheralVersion=2.0 17 | MCU=CH32V307VCT6 18 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/CH32V307VCT6.launch: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/CH32V307VCT6.wvproj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/CH32V307VCT6.wvproj -------------------------------------------------------------------------------- /project/CH32V307VCT6/Core/core_riscv.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : RISC-V Core Peripheral Access Layer Source File 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include 11 | 12 | /* define compiler specific symbols */ 13 | #if defined ( __CC_ARM ) 14 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ 15 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 16 | 17 | #elif defined ( __ICCARM__ ) 18 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ 19 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ 20 | 21 | #elif defined ( __GNUC__ ) 22 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ 23 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ 24 | 25 | #elif defined ( __TASKING__ ) 26 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 27 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 28 | 29 | #endif 30 | 31 | 32 | /********************************************************************* 33 | * @fn __get_FFLAGS 34 | * 35 | * @brief Return the Floating-Point Accrued Exceptions 36 | * 37 | * @return fflags value 38 | */ 39 | uint32_t __get_FFLAGS(void) 40 | { 41 | uint32_t result; 42 | 43 | __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); 44 | return (result); 45 | } 46 | 47 | /********************************************************************* 48 | * @fn __set_FFLAGS 49 | * 50 | * @brief Set the Floating-Point Accrued Exceptions 51 | * 52 | * @param value - set FFLAGS value 53 | * 54 | * @return none 55 | */ 56 | void __set_FFLAGS(uint32_t value) 57 | { 58 | __ASM volatile ("csrw fflags, %0" : : "r" (value) ); 59 | } 60 | 61 | /********************************************************************* 62 | * @fn __get_FRM 63 | * 64 | * @brief Return the Floating-Point Dynamic Rounding Mode 65 | * 66 | * @return frm value 67 | */ 68 | uint32_t __get_FRM(void) 69 | { 70 | uint32_t result; 71 | 72 | __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); 73 | return (result); 74 | } 75 | 76 | /********************************************************************* 77 | * @fn __set_FRM 78 | * 79 | * @brief Set the Floating-Point Dynamic Rounding Mode 80 | * 81 | * @param value - set frm value 82 | * 83 | * @return none 84 | */ 85 | void __set_FRM(uint32_t value) 86 | { 87 | __ASM volatile ("csrw frm, %0" : : "r" (value) ); 88 | } 89 | 90 | /********************************************************************* 91 | * @fn __get_FCSR 92 | * 93 | * @brief Return the Floating-Point Control and Status Register 94 | * 95 | * @return fcsr value 96 | */ 97 | uint32_t __get_FCSR(void) 98 | { 99 | uint32_t result; 100 | 101 | __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); 102 | return (result); 103 | } 104 | 105 | /********************************************************************* 106 | * @fn __set_FCSR 107 | * 108 | * @brief Set the Floating-Point Dynamic Rounding Mode 109 | * 110 | * @param value - set fcsr value 111 | * 112 | * @return none 113 | */ 114 | void __set_FCSR(uint32_t value) 115 | { 116 | __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); 117 | } 118 | 119 | /********************************************************************* 120 | * @fn __get_MSTATUS 121 | * 122 | * @brief Return the Machine Status Register 123 | * 124 | * @return mstatus value 125 | */ 126 | uint32_t __get_MSTATUS(void) 127 | { 128 | uint32_t result; 129 | 130 | __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); 131 | return (result); 132 | } 133 | 134 | /********************************************************************* 135 | * @fn __set_MSTATUS 136 | * 137 | * @brief Set the Machine Status Register 138 | * 139 | * @param value - set mstatus value 140 | * 141 | * @return none 142 | */ 143 | void __set_MSTATUS(uint32_t value) 144 | { 145 | __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); 146 | } 147 | 148 | /********************************************************************* 149 | * @fn __get_MISA 150 | * 151 | * @brief Return the Machine ISA Register 152 | * 153 | * @return misa value 154 | */ 155 | uint32_t __get_MISA(void) 156 | { 157 | uint32_t result; 158 | 159 | __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); 160 | return (result); 161 | } 162 | 163 | /********************************************************************* 164 | * @fn __set_MISA 165 | * 166 | * @brief Set the Machine ISA Register 167 | * 168 | * @param value - set misa value 169 | * 170 | * @return none 171 | */ 172 | void __set_MISA(uint32_t value) 173 | { 174 | __ASM volatile ("csrw misa, %0" : : "r" (value) ); 175 | } 176 | 177 | /********************************************************************* 178 | * @fn __get_MTVEC 179 | * 180 | * @brief Return the Machine Trap-Vector Base-Address Register 181 | * 182 | * @return mtvec value 183 | */ 184 | uint32_t __get_MTVEC(void) 185 | { 186 | uint32_t result; 187 | 188 | __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); 189 | return (result); 190 | } 191 | 192 | /********************************************************************* 193 | * @fn __set_MTVEC 194 | * 195 | * @brief Set the Machine Trap-Vector Base-Address Register 196 | * 197 | * @param value - set mtvec value 198 | * 199 | * @return none 200 | */ 201 | void __set_MTVEC(uint32_t value) 202 | { 203 | __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); 204 | } 205 | 206 | /********************************************************************* 207 | * @fn __get_MSCRATCH 208 | * 209 | * @brief Return the Machine Seratch Register 210 | * 211 | * @return mscratch value 212 | */ 213 | uint32_t __get_MSCRATCH(void) 214 | { 215 | uint32_t result; 216 | 217 | __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); 218 | return (result); 219 | } 220 | 221 | /********************************************************************* 222 | * @fn __set_MSCRATCH 223 | * 224 | * @brief Set the Machine Seratch Register 225 | * 226 | * @param value - set mscratch value 227 | * 228 | * @return none 229 | */ 230 | void __set_MSCRATCH(uint32_t value) 231 | { 232 | __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); 233 | } 234 | 235 | /********************************************************************* 236 | * @fn __get_MEPC 237 | * 238 | * @brief Return the Machine Exception Program Register 239 | * 240 | * @return mepc value 241 | */ 242 | uint32_t __get_MEPC(void) 243 | { 244 | uint32_t result; 245 | 246 | __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); 247 | return (result); 248 | } 249 | 250 | /********************************************************************* 251 | * @fn __set_MEPC 252 | * 253 | * @brief Set the Machine Exception Program Register 254 | * 255 | * @return mepc value 256 | */ 257 | void __set_MEPC(uint32_t value) 258 | { 259 | __ASM volatile ("csrw mepc, %0" : : "r" (value) ); 260 | } 261 | 262 | /********************************************************************* 263 | * @fn __get_MCAUSE 264 | * 265 | * @brief Return the Machine Cause Register 266 | * 267 | * @return mcause value 268 | */ 269 | uint32_t __get_MCAUSE(void) 270 | { 271 | uint32_t result; 272 | 273 | __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); 274 | return (result); 275 | } 276 | 277 | /********************************************************************* 278 | * @fn __set_MEPC 279 | * 280 | * @brief Set the Machine Cause Register 281 | * 282 | * @return mcause value 283 | */ 284 | void __set_MCAUSE(uint32_t value) 285 | { 286 | __ASM volatile ("csrw mcause, %0" : : "r" (value) ); 287 | } 288 | 289 | /********************************************************************* 290 | * @fn __get_MTVAL 291 | * 292 | * @brief Return the Machine Trap Value Register 293 | * 294 | * @return mtval value 295 | */ 296 | uint32_t __get_MTVAL(void) 297 | { 298 | uint32_t result; 299 | 300 | __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); 301 | return (result); 302 | } 303 | 304 | /********************************************************************* 305 | * @fn __set_MTVAL 306 | * 307 | * @brief Set the Machine Trap Value Register 308 | * 309 | * @return mtval value 310 | */ 311 | void __set_MTVAL(uint32_t value) 312 | { 313 | __ASM volatile ("csrw mtval, %0" : : "r" (value) ); 314 | } 315 | 316 | /********************************************************************* 317 | * @fn __get_MVENDORID 318 | * 319 | * @brief Return Vendor ID Register 320 | * 321 | * @return mvendorid value 322 | */ 323 | uint32_t __get_MVENDORID(void) 324 | { 325 | uint32_t result; 326 | 327 | __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); 328 | return (result); 329 | } 330 | 331 | /********************************************************************* 332 | * @fn __get_MARCHID 333 | * 334 | * @brief Return Machine Architecture ID Register 335 | * 336 | * @return marchid value 337 | */ 338 | uint32_t __get_MARCHID(void) 339 | { 340 | uint32_t result; 341 | 342 | __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); 343 | return (result); 344 | } 345 | 346 | /********************************************************************* 347 | * @fn __get_MIMPID 348 | * 349 | * @brief Return Machine Implementation ID Register 350 | * 351 | * @return mimpid value 352 | */ 353 | uint32_t __get_MIMPID(void) 354 | { 355 | uint32_t result; 356 | 357 | __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); 358 | return (result); 359 | } 360 | 361 | /********************************************************************* 362 | * @fn __get_MHARTID 363 | * 364 | * @brief Return Hart ID Register 365 | * 366 | * @return mhartid value 367 | */ 368 | uint32_t __get_MHARTID(void) 369 | { 370 | uint32_t result; 371 | 372 | __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); 373 | return (result); 374 | } 375 | 376 | /********************************************************************* 377 | * @fn __get_SP 378 | * 379 | * @brief Return SP Register 380 | * 381 | * @return SP value 382 | */ 383 | uint32_t __get_SP(void) 384 | { 385 | uint32_t result; 386 | 387 | __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); 388 | return (result); 389 | } 390 | 391 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Core/core_riscv.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : core_riscv.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : RISC-V Core Peripheral Access Layer Header File for CH32V30x 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #ifndef __CORE_RISCV_H__ 11 | #define __CORE_RISCV_H__ 12 | 13 | #ifdef __cplusplus 14 | extern "C" { 15 | #endif 16 | 17 | /* IO definitions */ 18 | #ifdef __cplusplus 19 | #define __I volatile /* defines 'read only' permissions */ 20 | #else 21 | #define __I volatile const /* defines 'read only' permissions */ 22 | #endif 23 | #define __O volatile /* defines 'write only' permissions */ 24 | #define __IO volatile /* defines 'read / write' permissions */ 25 | 26 | /* Standard Peripheral Library old types (maintained for legacy purpose) */ 27 | typedef __I uint64_t vuc64; /* Read Only */ 28 | typedef __I uint32_t vuc32; /* Read Only */ 29 | typedef __I uint16_t vuc16; /* Read Only */ 30 | typedef __I uint8_t vuc8; /* Read Only */ 31 | 32 | typedef const uint64_t uc64; /* Read Only */ 33 | typedef const uint32_t uc32; /* Read Only */ 34 | typedef const uint16_t uc16; /* Read Only */ 35 | typedef const uint8_t uc8; /* Read Only */ 36 | 37 | typedef __I int64_t vsc64; /* Read Only */ 38 | typedef __I int32_t vsc32; /* Read Only */ 39 | typedef __I int16_t vsc16; /* Read Only */ 40 | typedef __I int8_t vsc8; /* Read Only */ 41 | 42 | typedef const int64_t sc64; /* Read Only */ 43 | typedef const int32_t sc32; /* Read Only */ 44 | typedef const int16_t sc16; /* Read Only */ 45 | typedef const int8_t sc8; /* Read Only */ 46 | 47 | typedef __IO uint64_t vu64; 48 | typedef __IO uint32_t vu32; 49 | typedef __IO uint16_t vu16; 50 | typedef __IO uint8_t vu8; 51 | 52 | typedef uint64_t u64; 53 | typedef uint32_t u32; 54 | typedef uint16_t u16; 55 | typedef uint8_t u8; 56 | 57 | typedef __IO int64_t vs64; 58 | typedef __IO int32_t vs32; 59 | typedef __IO int16_t vs16; 60 | typedef __IO int8_t vs8; 61 | 62 | typedef int64_t s64; 63 | typedef int32_t s32; 64 | typedef int16_t s16; 65 | typedef int8_t s8; 66 | 67 | typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; 68 | 69 | typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; 70 | 71 | typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; 72 | 73 | #define RV_STATIC_INLINE static inline 74 | 75 | /* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ 76 | typedef struct{ 77 | __I uint32_t ISR[8]; 78 | __I uint32_t IPR[8]; 79 | __IO uint32_t ITHRESDR; 80 | __IO uint32_t RESERVED; 81 | __IO uint32_t CFGR; 82 | __I uint32_t GISR; 83 | __IO uint8_t VTFIDR[4]; 84 | uint8_t RESERVED0[12]; 85 | __IO uint32_t VTFADDR[4]; 86 | uint8_t RESERVED1[0x90]; 87 | __O uint32_t IENR[8]; 88 | uint8_t RESERVED2[0x60]; 89 | __O uint32_t IRER[8]; 90 | uint8_t RESERVED3[0x60]; 91 | __O uint32_t IPSR[8]; 92 | uint8_t RESERVED4[0x60]; 93 | __O uint32_t IPRR[8]; 94 | uint8_t RESERVED5[0x60]; 95 | __IO uint32_t IACTR[8]; 96 | uint8_t RESERVED6[0xE0]; 97 | __IO uint8_t IPRIOR[256]; 98 | uint8_t RESERVED7[0x810]; 99 | __IO uint32_t SCTLR; 100 | }PFIC_Type; 101 | 102 | /* memory mapped structure for SysTick */ 103 | typedef struct 104 | { 105 | __IO u32 CTLR; 106 | __IO u32 SR; 107 | __IO u64 CNT; 108 | __IO u64 CMP; 109 | }SysTick_Type; 110 | 111 | 112 | #define PFIC ((PFIC_Type *) 0xE000E000 ) 113 | #define NVIC PFIC 114 | #define NVIC_KEY1 ((uint32_t)0xFA050000) 115 | #define NVIC_KEY2 ((uint32_t)0xBCAF0000) 116 | #define NVIC_KEY3 ((uint32_t)0xBEEF0000) 117 | 118 | #define SysTick ((SysTick_Type *) 0xE000F000) 119 | 120 | /********************************************************************* 121 | * @fn __enable_irq 122 | * 123 | * @brief Enable Global Interrupt 124 | * 125 | * @return none 126 | */ 127 | RV_STATIC_INLINE void __enable_irq() 128 | { 129 | __asm volatile ("csrw 0x800, %0" : : "r" (0x6088) ); 130 | } 131 | 132 | /********************************************************************* 133 | * @fn __disable_irq 134 | * 135 | * @brief Disable Global Interrupt 136 | * 137 | * @return none 138 | */ 139 | RV_STATIC_INLINE void __disable_irq() 140 | { 141 | __asm volatile ("csrw 0x800, %0" : : "r" (0x6000) ); 142 | } 143 | 144 | /********************************************************************* 145 | * @fn __NOP 146 | * 147 | * @brief nop 148 | * 149 | * @return none 150 | */ 151 | RV_STATIC_INLINE void __NOP() 152 | { 153 | __asm volatile ("nop"); 154 | } 155 | 156 | /********************************************************************* 157 | * @fn NVIC_EnableIRQ 158 | * 159 | * @brief Enable Interrupt 160 | * 161 | * @param IRQn: Interrupt Numbers 162 | * 163 | * @return none 164 | */ 165 | RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 166 | { 167 | NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 168 | } 169 | 170 | /********************************************************************* 171 | * @fn NVIC_DisableIRQ 172 | * 173 | * @brief Disable Interrupt 174 | * 175 | * @param IRQn: Interrupt Numbers 176 | * 177 | * @return none 178 | */ 179 | RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 180 | { 181 | NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 182 | } 183 | 184 | /********************************************************************* 185 | * @fn NVIC_GetStatusIRQ 186 | * 187 | * @brief Get Interrupt Enable State 188 | * 189 | * @param IRQn: Interrupt Numbers 190 | * 191 | * @return 1 - Interrupt Enable 192 | * 0 - Interrupt Disable 193 | */ 194 | RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) 195 | { 196 | return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 197 | } 198 | 199 | /********************************************************************* 200 | * @fn NVIC_GetPendingIRQ 201 | * 202 | * @brief Get Interrupt Pending State 203 | * 204 | * @param IRQn: Interrupt Numbers 205 | * 206 | * @return 1 - Interrupt Pending Enable 207 | * 0 - Interrupt Pending Disable 208 | */ 209 | RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 210 | { 211 | return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 212 | } 213 | 214 | /********************************************************************* 215 | * @fn NVIC_SetPendingIRQ 216 | * 217 | * @brief Set Interrupt Pending 218 | * 219 | * @param IRQn: Interrupt Numbers 220 | * 221 | * @return None 222 | */ 223 | RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 224 | { 225 | NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 226 | } 227 | 228 | /********************************************************************* 229 | * @fn NVIC_ClearPendingIRQ 230 | * 231 | * @brief Clear Interrupt Pending 232 | * 233 | * @param IRQn: Interrupt Numbers 234 | * 235 | * @return None 236 | */ 237 | RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 238 | { 239 | NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); 240 | } 241 | 242 | /********************************************************************* 243 | * @fn NVIC_GetActive 244 | * 245 | * @brief Get Interrupt Active State 246 | * 247 | * @param IRQn: Interrupt Numbers 248 | * 249 | * @return 1 - Interrupt Active 250 | * 0 - Interrupt No Active 251 | */ 252 | RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 253 | { 254 | return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 255 | } 256 | 257 | /********************************************************************* 258 | * @fn NVIC_SetPriority 259 | * 260 | * @brief Set Interrupt Priority 261 | * 262 | * @param IRQn - Interrupt Numbers 263 | * priority - 264 | * bit7 - pre-emption priority 265 | * bit6~bit4 - subpriority 266 | * @return None 267 | */ 268 | RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) 269 | { 270 | NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; 271 | } 272 | 273 | /********************************************************************* 274 | * @fn __WFI 275 | * 276 | * @brief Wait for Interrupt 277 | * 278 | * @return None 279 | */ 280 | __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) 281 | { 282 | NVIC->SCTLR &= ~(1<<3); // wfi 283 | asm volatile ("wfi"); 284 | } 285 | 286 | /********************************************************************* 287 | * @fn __WFE 288 | * 289 | * @brief Wait for Events 290 | * 291 | * @return None 292 | */ 293 | __attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) 294 | { 295 | uint32_t t; 296 | 297 | t = NVIC->SCTLR; 298 | NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev) 299 | NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); 300 | asm volatile ("wfi"); 301 | asm volatile ("wfi"); 302 | } 303 | 304 | /********************************************************************* 305 | * @fn SetVTFIRQ 306 | * 307 | * @brief Set VTF Interrupt 308 | * 309 | * @param add - VTF interrupt service function base address. 310 | * IRQn -Interrupt Numbers 311 | * num - VTF Interrupt Numbers 312 | * NewState - DISABLE or ENABLE 313 | * @return None 314 | */ 315 | RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){ 316 | if(num > 3) return ; 317 | 318 | if (NewState != DISABLE) 319 | { 320 | NVIC->VTFIDR[num] = IRQn; 321 | NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); 322 | } 323 | else{ 324 | NVIC->VTFIDR[num] = IRQn; 325 | NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); 326 | } 327 | } 328 | 329 | /********************************************************************* 330 | * @fn NVIC_SystemReset 331 | * 332 | * @brief Initiate a system reset request 333 | * 334 | * @return None 335 | */ 336 | RV_STATIC_INLINE void NVIC_SystemReset(void) 337 | { 338 | NVIC->CFGR = NVIC_KEY3|(1<<7); 339 | } 340 | 341 | 342 | /* Core_Exported_Functions */ 343 | extern uint32_t __get_FFLAGS(void); 344 | extern void __set_FFLAGS(uint32_t value); 345 | extern uint32_t __get_FRM(void); 346 | extern void __set_FRM(uint32_t value); 347 | extern uint32_t __get_FCSR(void); 348 | extern void __set_FCSR(uint32_t value); 349 | extern uint32_t __get_MSTATUS(void); 350 | extern void __set_MSTATUS(uint32_t value); 351 | extern uint32_t __get_MISA(void); 352 | extern void __set_MISA(uint32_t value); 353 | extern uint32_t __get_MTVEC(void); 354 | extern void __set_MTVEC(uint32_t value); 355 | extern uint32_t __get_MSCRATCH(void); 356 | extern void __set_MSCRATCH(uint32_t value); 357 | extern uint32_t __get_MEPC(void); 358 | extern void __set_MEPC(uint32_t value); 359 | extern uint32_t __get_MCAUSE(void); 360 | extern void __set_MCAUSE(uint32_t value); 361 | extern uint32_t __get_MTVAL(void); 362 | extern void __set_MTVAL(uint32_t value); 363 | extern uint32_t __get_MVENDORID(void); 364 | extern uint32_t __get_MARCHID(void); 365 | extern uint32_t __get_MIMPID(void); 366 | extern uint32_t __get_MHARTID(void); 367 | extern uint32_t __get_SP(void); 368 | 369 | #ifdef __cplusplus 370 | } 371 | #endif 372 | 373 | #endif 374 | 375 | 376 | 377 | 378 | 379 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Debug/debug.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : debug.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for UART 7 | * Printf , Delay functions. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #include "debug.h" 12 | 13 | static uint8_t p_us = 0; 14 | static uint16_t p_ms = 0; 15 | 16 | /********************************************************************* 17 | * @fn Delay_Init 18 | * 19 | * @brief Initializes Delay Funcation. 20 | * 21 | * @return none 22 | */ 23 | void Delay_Init(void) 24 | { 25 | p_us = SystemCoreClock / 8000000; 26 | p_ms = (uint16_t)p_us * 1000; 27 | } 28 | 29 | /********************************************************************* 30 | * @fn Delay_Us 31 | * 32 | * @brief Microsecond Delay Time. 33 | * 34 | * @param n - Microsecond number. 35 | * 36 | * @return None 37 | */ 38 | void Delay_Us(uint32_t n) 39 | { 40 | uint32_t i; 41 | 42 | SysTick->SR &= ~(1 << 0); 43 | i = (uint32_t)n * p_us; 44 | 45 | SysTick->CMP = i; 46 | SysTick->CTLR |= (1 << 4); 47 | SysTick->CTLR |= (1 << 5) | (1 << 0); 48 | 49 | while((SysTick->SR & (1 << 0)) != (1 << 0)) 50 | ; 51 | SysTick->CTLR &= ~(1 << 0); 52 | } 53 | 54 | /********************************************************************* 55 | * @fn Delay_Ms 56 | * 57 | * @brief Millisecond Delay Time. 58 | * 59 | * @param n - Millisecond number. 60 | * 61 | * @return None 62 | */ 63 | void Delay_Ms(uint32_t n) 64 | { 65 | uint32_t i; 66 | 67 | SysTick->SR &= ~(1 << 0); 68 | i = (uint32_t)n * p_ms; 69 | 70 | SysTick->CMP = i; 71 | SysTick->CTLR |= (1 << 4); 72 | SysTick->CTLR |= (1 << 5) | (1 << 0); 73 | 74 | while((SysTick->SR & (1 << 0)) != (1 << 0)) 75 | ; 76 | SysTick->CTLR &= ~(1 << 0); 77 | } 78 | 79 | /********************************************************************* 80 | * @fn USART_Printf_Init 81 | * 82 | * @brief Initializes the USARTx peripheral. 83 | * 84 | * @param baudrate - USART communication baud rate. 85 | * 86 | * @return None 87 | */ 88 | void USART_Printf_Init(uint32_t baudrate) 89 | { 90 | GPIO_InitTypeDef GPIO_InitStructure; 91 | USART_InitTypeDef USART_InitStructure; 92 | 93 | #if(DEBUG == DEBUG_UART1) 94 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); 95 | 96 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; 97 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 98 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 99 | GPIO_Init(GPIOA, &GPIO_InitStructure); 100 | 101 | #elif(DEBUG == DEBUG_UART2) 102 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); 103 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 104 | 105 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; 106 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 107 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 108 | GPIO_Init(GPIOA, &GPIO_InitStructure); 109 | 110 | #elif(DEBUG == DEBUG_UART3) 111 | RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); 112 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); 113 | 114 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; 115 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 116 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 117 | GPIO_Init(GPIOB, &GPIO_InitStructure); 118 | 119 | #endif 120 | 121 | USART_InitStructure.USART_BaudRate = baudrate; 122 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 123 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 124 | USART_InitStructure.USART_Parity = USART_Parity_No; 125 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 126 | USART_InitStructure.USART_Mode = USART_Mode_Tx; 127 | 128 | #if(DEBUG == DEBUG_UART1) 129 | USART_Init(USART1, &USART_InitStructure); 130 | USART_Cmd(USART1, ENABLE); 131 | 132 | #elif(DEBUG == DEBUG_UART2) 133 | USART_Init(USART2, &USART_InitStructure); 134 | USART_Cmd(USART2, ENABLE); 135 | 136 | #elif(DEBUG == DEBUG_UART3) 137 | USART_Init(USART3, &USART_InitStructure); 138 | USART_Cmd(USART3, ENABLE); 139 | 140 | #endif 141 | } 142 | 143 | /********************************************************************* 144 | * @fn _write 145 | * 146 | * @brief Support Printf Function 147 | * 148 | * @param *buf - UART send Data. 149 | * size - Data length 150 | * 151 | * @return size: Data length 152 | */ 153 | __attribute__((used)) int _write(int fd, char *buf, int size) 154 | { 155 | int i; 156 | 157 | for(i = 0; i < size; i++) 158 | { 159 | #if(DEBUG == DEBUG_UART1) 160 | while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); 161 | USART_SendData(USART1, *buf++); 162 | #elif(DEBUG == DEBUG_UART2) 163 | while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); 164 | USART_SendData(USART2, *buf++); 165 | #elif(DEBUG == DEBUG_UART3) 166 | while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); 167 | USART_SendData(USART3, *buf++); 168 | #endif 169 | } 170 | 171 | return size; 172 | } 173 | 174 | /********************************************************************* 175 | * @fn _sbrk 176 | * 177 | * @brief Change the spatial position of data segment. 178 | * 179 | * @return size: Data length 180 | */ 181 | void *_sbrk(ptrdiff_t incr) 182 | { 183 | extern char _end[]; 184 | extern char _heap_end[]; 185 | static char *curbrk = _end; 186 | 187 | if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) 188 | return NULL - 1; 189 | 190 | curbrk += incr; 191 | return curbrk - incr; 192 | } 193 | 194 | 195 | 196 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Debug/debug.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : debug.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for UART 7 | * Printf , Delay functions. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __DEBUG_H 12 | #define __DEBUG_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "stdio.h" 19 | #include "ch32v30x.h" 20 | 21 | /* UART Printf Definition */ 22 | #define DEBUG_UART1 1 23 | #define DEBUG_UART2 2 24 | #define DEBUG_UART3 3 25 | 26 | /* DEBUG UATR Definition */ 27 | //#define DEBUG DEBUG_UART1 28 | //#define DEBUG DEBUG_UART2 29 | #define DEBUG DEBUG_UART3 30 | 31 | 32 | void Delay_Init(void); 33 | void Delay_Us (uint32_t n); 34 | void Delay_Ms (uint32_t n); 35 | void USART_Printf_Init(uint32_t baudrate); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif 42 | 43 | 44 | 45 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/FOC/ekf.h: -------------------------------------------------------------------------------- 1 | #ifndef __EKF_H 2 | #define __EKF_H 3 | 4 | 5 | #define RS_PARAMETER 0.4f//电阻 6 | #define LS_PARAMETER 0.0014f//电感 7 | #define FLUX_PARAMETER 0.002210119f//磁链 8 | typedef struct 9 | { 10 | float ekf_input[7]; //输入参数 11 | float ekf_states[4]; //状态变量 12 | 13 | }EKF_DATA_DEF; 14 | extern float Ts; 15 | void Apt_Ekf_Init(void); 16 | void Apt_Ekf_Update(const float *u, float *xD); 17 | 18 | #endif /*__EKF_H*/ 19 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/FOC/fast_math.c: -------------------------------------------------------------------------------- 1 | #include "fast_math.h" 2 | 3 | /*! 4 | \brief fast sine function lookup table 5 | */ 6 | const float sin_tab[] = { 7 | 0, 0.012296f, 0.024589f, 0.036879f, 0.049164f, 0.061441f, 0.073708f, 0.085965f, 0.098208f, 0.11044f, 0.12265f, 8 | 0.13484f, 0.14702f, 0.15917f, 0.17129f, 0.18339f, 0.19547f, 0.20751f, 0.21952f, 0.2315f, 0.24345f, 0.25535f, 9 | 0.26722f, 0.27905f, 0.29084f, 0.30258f, 0.31427f, 0.32592f, 0.33752f, 0.34907f, 0.36057f, 0.37201f, 0.38339f, 10 | 0.39472f, 0.40599f, 0.41719f, 0.42834f, 0.43941f, 0.45043f, 0.46137f, 0.47224f, 0.48305f, 0.49378f, 0.50443f, 11 | 0.51501f, 0.52551f, 0.53593f, 0.54627f, 0.55653f, 0.5667f, 0.57679f, 0.58679f, 0.5967f, 0.60652f, 0.61625f, 12 | 0.62589f, 0.63543f, 0.64488f, 0.65423f, 0.66348f, 0.67263f, 0.68167f, 0.69062f, 0.69946f, 0.70819f, 0.71682f, 13 | 0.72534f, 0.73375f, 0.74205f, 0.75023f, 0.75831f, 0.76626f, 0.77411f, 0.78183f, 0.78944f, 0.79693f, 0.80429f, 14 | 0.81154f, 0.81866f, 0.82566f, 0.83254f, 0.83928f, 0.84591f, 0.8524f, 0.85876f, 0.865f, 0.8711f, 0.87708f, 0.88292f, 15 | 0.88862f, 0.89419f, 0.89963f, 0.90493f, 0.9101f, 0.91512f, 0.92001f, 0.92476f, 0.92937f, 0.93384f, 0.93816f, 16 | 0.94235f, 0.94639f, 0.95029f, 0.95405f, 0.95766f, 0.96113f, 0.96445f, 0.96763f, 0.97066f, 0.97354f, 0.97628f, 17 | 0.97887f, 0.98131f, 0.9836f, 0.98574f, 0.98774f, 0.98958f, 0.99128f, 0.99282f, 0.99422f, 0.99546f, 0.99656f, 18 | 0.9975f, 0.99829f, 0.99894f, 0.99943f, 0.99977f, 0.99996f, 1.0f, 0.99988f, 0.99962f, 0.9992f, 0.99863f, 0.99792f, 19 | 0.99705f, 0.99603f, 0.99486f, 0.99354f, 0.99207f, 0.99045f, 0.98868f, 0.98676f, 0.98469f, 0.98247f, 0.9801f, 20 | 0.97759f, 0.97493f, 0.97212f, 0.96916f, 0.96606f, 0.96281f, 0.95941f, 0.95587f, 0.95219f, 0.94836f, 0.94439f, 21 | 0.94028f, 0.93602f, 0.93162f, 0.92708f, 0.9224f, 0.91758f, 0.91263f, 0.90753f, 0.9023f, 0.89693f, 0.89142f, 22 | 0.88579f, 0.88001f, 0.87411f, 0.86807f, 0.8619f, 0.8556f, 0.84917f, 0.84261f, 0.83593f, 0.82911f, 0.82218f, 23 | 0.81512f, 0.80793f, 0.80062f, 0.7932f, 0.78565f, 0.77798f, 0.7702f, 0.7623f, 0.75428f, 0.74615f, 0.73791f, 0.72956f, 24 | 0.72109f, 0.71252f, 0.70384f, 0.69505f, 0.68616f, 0.67716f, 0.66806f, 0.65886f, 0.64956f, 0.64017f, 0.63067f, 25 | 0.62108f, 0.6114f, 0.60162f, 0.59176f, 0.5818f, 0.57176f, 0.56163f, 0.55141f, 0.54111f, 0.53073f, 0.52027f, 26 | 0.50973f, 0.49911f, 0.48842f, 0.47765f, 0.46682f, 0.45591f, 0.44493f, 0.43388f, 0.42277f, 0.4116f, 0.40036f, 27 | 0.38906f, 0.37771f, 0.36629f, 0.35483f, 0.3433f, 0.33173f, 0.32011f, 0.30843f, 0.29671f, 0.28495f, 0.27314f, 28 | 0.26129f, 0.2494f, 0.23748f, 0.22552f, 0.21352f, 0.20149f, 0.18943f, 0.17735f, 0.16523f, 0.15309f, 0.14093f, 29 | 0.12875f, 0.11655f, 0.10432f, 0.092088f, 0.079838f, 0.067576f, 0.055303f, 0.043022f, 0.030735f, 0.018443f, 30 | 0.0061479f, -0.0061479f, -0.018443f, -0.030735f, -0.043022f, -0.055303f, -0.067576f, -0.079838f, -0.092088f, 31 | -0.10432f, -0.11655f, -0.12875f, -0.14093f, -0.15309f, -0.16523f, -0.17735f, -0.18943f, -0.20149f, -0.21352f, 32 | -0.22552f, -0.23748f, -0.2494f, -0.26129f, -0.27314f, -0.28495f, -0.29671f, -0.30843f, -0.32011f, -0.33173f, 33 | -0.3433f, -0.35483f, -0.36629f, -0.37771f, -0.38906f, -0.40036f, -0.4116f, -0.42277f, -0.43388f, -0.44493f, 34 | -0.45591f, -0.46682f, -0.47765f, -0.48842f, -0.49911f, -0.50973f, -0.52027f, -0.53073f, -0.54111f, -0.55141f, 35 | -0.56163f, -0.57176f, -0.5818f, -0.59176f, -0.60162f, -0.6114f, -0.62108f, -0.63067f, -0.64017f, -0.64956f, 36 | -0.65886f, -0.66806f, -0.67716f, -0.68616f, -0.69505f, -0.70384f, -0.71252f, -0.72109f, -0.72956f, -0.73791f, 37 | -0.74615f, -0.75428f, -0.7623f, -0.7702f, -0.77798f, -0.78565f, -0.7932f, -0.80062f, -0.80793f, -0.81512f, 38 | -0.82218f, -0.82911f, -0.83593f, -0.84261f, -0.84917f, -0.8556f, -0.8619f, -0.86807f, -0.87411f, -0.88001f, 39 | -0.88579f, -0.89142f, -0.89693f, -0.9023f, -0.90753f, -0.91263f, -0.91758f, -0.9224f, -0.92708f, -0.93162f, 40 | -0.93602f, -0.94028f, -0.94439f, -0.94836f, -0.95219f, -0.95587f, -0.95941f, -0.96281f, -0.96606f, -0.96916f, 41 | -0.97212f, -0.97493f, -0.97759f, -0.9801f, -0.98247f, -0.98469f, -0.98676f, -0.98868f, -0.99045f, -0.99207f, 42 | -0.99354f, -0.99486f, -0.99603f, -0.99705f, -0.99792f, -0.99863f, -0.9992f, -0.99962f, -0.99988f, -1.0f, -0.99996f, 43 | -0.99977f, -0.99943f, -0.99894f, -0.99829f, -0.9975f, -0.99656f, -0.99546f, -0.99422f, -0.99282f, -0.99128f, 44 | -0.98958f, -0.98774f, -0.98574f, -0.9836f, -0.98131f, -0.97887f, -0.97628f, -0.97354f, -0.97066f, -0.96763f, 45 | -0.96445f, -0.96113f, -0.95766f, -0.95405f, -0.95029f, -0.94639f, -0.94235f, -0.93816f, -0.93384f, -0.92937f, 46 | -0.92476f, -0.92001f, -0.91512f, -0.9101f, -0.90493f, -0.89963f, -0.89419f, -0.88862f, -0.88292f, -0.87708f, 47 | -0.8711f, -0.865f, -0.85876f, -0.8524f, -0.84591f, -0.83928f, -0.83254f, -0.82566f, -0.81866f, -0.81154f, -0.80429f, 48 | -0.79693f, -0.78944f, -0.78183f, -0.77411f, -0.76626f, -0.75831f, -0.75023f, -0.74205f, -0.73375f, -0.72534f, 49 | -0.71682f, -0.70819f, -0.69946f, -0.69062f, -0.68167f, -0.67263f, -0.66348f, -0.65423f, -0.64488f, -0.63543f, 50 | -0.62589f, -0.61625f, -0.60652f, -0.5967f, -0.58679f, -0.57679f, -0.5667f, -0.55653f, -0.54627f, -0.53593f, 51 | -0.52551f, -0.51501f, -0.50443f, -0.49378f, -0.48305f, -0.47224f, -0.46137f, -0.45043f, -0.43941f, -0.42834f, 52 | -0.41719f, -0.40599f, -0.39472f, -0.38339f, -0.37201f, -0.36057f, -0.34907f, -0.33752f, -0.32592f, -0.31427f, 53 | -0.30258f, -0.29084f, -0.27905f, -0.26722f, -0.25535f, -0.24345f, -0.2315f, -0.21952f, -0.20751f, -0.19547f, 54 | -0.18339f, -0.17129f, -0.15917f, -0.14702f, -0.13484f, -0.12265f, -0.11044f, -0.098208f, -0.085965f, -0.073708f, 55 | -0.061441f, -0.049164f, -0.036879f, -0.024589f, -0.012296f, 0 56 | }; 57 | 58 | /*! 59 | \brief fast calculation of sine 60 | \param[in] theta: angle to be calculated 61 | \retval sine value of angle theta 62 | */ 63 | float fast_sin(float theta) { 64 | /* congruence of angle theta to 2pi */ 65 | while (1) { 66 | if (theta > 6.2831854f && theta > 0) 67 | theta = theta - 6.2831854f; 68 | else if (theta < 0) 69 | theta = theta + 6.2831854f; 70 | else 71 | break; 72 | } 73 | /* look up the table to obtain the sine value */ 74 | return sin_tab[(int) (81.4873308f * theta)]; 75 | } 76 | 77 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/FOC/fast_math.h: -------------------------------------------------------------------------------- 1 | #ifndef FAST_MATH_H_ 2 | #define FAST_MATH_H_ 3 | 4 | /*! 5 | \brief fast clipping algorithm 6 | \param[in] x: number of to be clipped 7 | \param[in] low: minimum number 8 | \param[in] high: maximum number 9 | \retval input value after clipping 10 | */ 11 | #define fast_constrain(x, low, high) ((x)<(low)?(low):((x) >(high)?(high):(x))) 12 | 13 | /*! 14 | \brief fast calculation of cosine 15 | \param[in] x: angle to be calculated 16 | \retval cosine value of angle theta 17 | */ 18 | #define fast_cos(x) fast_sin(1.5707963f - x); 19 | 20 | float fast_sin(float theta); 21 | 22 | #endif /*FAST_MATH_H_*/ 23 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/FOC/foc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/FOC/foc.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/FOC/foc.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: foc.h 3 | * 4 | * Code generated for Simulink model 'foc'. 5 | * 6 | * Model version : 1.39 7 | * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 8 | * C/C++ source code generated on : Tue Jan 11 15:22:36 2022 9 | * 10 | * Target selection: ert.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_foc_h_ 19 | #define RTW_HEADER_foc_h_ 20 | #include 21 | #ifndef foc_COMMON_INCLUDES_ 22 | #define foc_COMMON_INCLUDES_ 23 | #include "rtwtypes.h" 24 | #include "stdint.h" 25 | #include "fast_math.h" 26 | #include "adc.h" 27 | #include "ekf.h" 28 | #endif /* foc_COMMON_INCLUDES_ */ 29 | 30 | /* Model Code Variants */ 31 | 32 | /* Macros for accessing real-time model data structure */ 33 | #ifndef rtmGetErrorStatus 34 | #define rtmGetErrorStatus(rtm) ((rtm)->errorStatus) 35 | #endif 36 | 37 | #ifndef rtmSetErrorStatus 38 | #define rtmSetErrorStatus(rtm, val) ((rtm)->errorStatus = (val)) 39 | #endif 40 | 41 | 42 | 43 | #define pi 3.1415926f 44 | 45 | /* Forward declaration for rtModel */ 46 | typedef struct tag_RTM RT_MODEL; 47 | 48 | /* External inputs (root inport signals with default storage) */ 49 | typedef struct { 50 | real32_T ud; /* '/ud' */ 51 | real32_T uq; /* '/uq' */ 52 | real32_T theta; /* '/theta' */ 53 | real32_T angle_speed; 54 | real32_T udc; /* '/udc' */ 55 | real32_T Tpwm; //arr /* '/Tpwm' */ 56 | real32_T iq; 57 | real32_T id; 58 | real32_T ialpha; 59 | real32_T ibeta; 60 | real32_T ualpha; 61 | real32_T ubeta; 62 | } ExtU; 63 | 64 | /* External outputs (root outports fed by signals with default storage) */ 65 | typedef struct { 66 | real32_T Tcmp1; /* '/Tcmp1' */ 67 | real32_T Tcmp2; /* '/Tcmp2' */ 68 | real32_T Tcmp3; /* '/Tcmp3' */ 69 | real32_T sector; /* '/sector' */ 70 | real32_T iq; 71 | real32_T id; 72 | real32_T ia; 73 | real32_T ib; 74 | real32_T ialpha; 75 | real32_T ibeta; 76 | } ExtY; 77 | 78 | typedef struct { 79 | real32_T kp; 80 | real32_T ki; 81 | real32_T out_max; 82 | real32_T iout_max; 83 | real32_T out; 84 | real32_T sum_err; 85 | } PI; 86 | typedef struct { 87 | real32_T es_f; 88 | }smo; 89 | /* Real-time Model Data Structure */ 90 | struct tag_RTM { 91 | const char_T * volatile errorStatus; 92 | }; 93 | 94 | /* External inputs (root inport signals with default storage) */ 95 | extern ExtU rtU; 96 | 97 | /* External outputs (root outports fed by signals with default storage) */ 98 | extern ExtY rtY; 99 | 100 | 101 | 102 | 103 | /* Model entry point functions */ 104 | 105 | void foc_step(void); 106 | void All_foc_init(void); 107 | /* Real-time Model object */ 108 | extern RT_MODEL *const rtM; 109 | 110 | 111 | 112 | /*- 113 | * The generated code includes comments that allow you to trace directly 114 | * back to the appropriate location in the model. The basic format 115 | * is /block_name, where system is the system number (uniquely 116 | * assigned by Simulink) and block_name is the name of the block. 117 | * 118 | * Note that this particular code originates from a subsystem build, 119 | * and has its own system numbers different from the parent model. 120 | * Refer to the system hierarchy for this subsystem below, and use the 121 | * MATLAB hilite_system command to trace the generated code back 122 | * to the parent model. For example, 123 | * 124 | * hilite_system('re_park_alpha/foc') - opens subsystem re_park_alpha/foc 125 | * hilite_system('re_park_alpha/foc/Kp') - opens and selects block Kp 126 | * 127 | * Here is the system hierarchy for this model 128 | * 129 | * '' : 're_park_alpha' 130 | * '' : 're_park_alpha/foc' 131 | * '' : 're_park_alpha/foc/SVPWM MATLAB Function' 132 | * '' : 're_park_alpha/foc/rePark' 133 | */ 134 | #endif /* RTW_HEADER_foc_h_ */ 135 | 136 | /* 137 | * File trailer for generated code. 138 | * 139 | * [EOF] 140 | */ 141 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/FOC/rtwtypes.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: rtwtypes.h 3 | * 4 | * Code generated for Simulink model 'foc'. 5 | * 6 | * Model version : 1.39 7 | * Simulink Coder version : 9.5 (R2021a) 14-Nov-2020 8 | * C/C++ source code generated on : Tue Jan 11 15:22:36 2022 9 | * 10 | * Target selection: ert.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTWTYPES_H 19 | #define RTWTYPES_H 20 | 21 | /* Logical type definitions */ 22 | #if (!defined(__cplusplus)) 23 | #ifndef false 24 | #define false (0U) 25 | #endif 26 | 27 | #ifndef true 28 | #define true (1U) 29 | #endif 30 | #endif 31 | 32 | /*=======================================================================* 33 | * Target hardware information 34 | * Device type: Intel->x86-64 (Windows64) 35 | * Number of bits: char: 8 short: 16 int: 32 36 | * long: 32 long long: 64 37 | * native word size: 64 38 | * Byte ordering: LittleEndian 39 | * Signed integer division rounds to: Zero 40 | * Shift right on a signed integer as arithmetic shift: on 41 | *=======================================================================*/ 42 | 43 | /*=======================================================================* 44 | * Fixed width word size data types: * 45 | * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * 46 | * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * 47 | * real32_T, real64_T - 32 and 64 bit floating point numbers * 48 | *=======================================================================*/ 49 | typedef signed char int8_T; 50 | typedef unsigned char uint8_T; 51 | typedef short int16_T; 52 | typedef unsigned short uint16_T; 53 | typedef int int32_T; 54 | typedef unsigned int uint32_T; 55 | typedef long long int64_T; 56 | typedef unsigned long long uint64_T; 57 | typedef float real32_T; 58 | typedef double real64_T; 59 | 60 | /*===========================================================================* 61 | * Generic type definitions: boolean_T, char_T, byte_T, int_T, uint_T, * 62 | * real_T, time_T, ulong_T, ulonglong_T. * 63 | *===========================================================================*/ 64 | typedef double real_T; 65 | typedef double time_T; 66 | typedef unsigned char boolean_T; 67 | typedef int int_T; 68 | typedef unsigned int uint_T; 69 | typedef unsigned long ulong_T; 70 | typedef unsigned long long ulonglong_T; 71 | typedef char char_T; 72 | typedef unsigned char uchar_T; 73 | typedef char_T byte_T; 74 | 75 | /*=======================================================================* 76 | * Min and Max: * 77 | * int8_T, int16_T, int32_T - signed 8, 16, or 32 bit integers * 78 | * uint8_T, uint16_T, uint32_T - unsigned 8, 16, or 32 bit integers * 79 | *=======================================================================*/ 80 | #define MAX_int8_T ((int8_T)(127)) 81 | #define MIN_int8_T ((int8_T)(-128)) 82 | #define MAX_uint8_T ((uint8_T)(255U)) 83 | #define MAX_int16_T ((int16_T)(32767)) 84 | #define MIN_int16_T ((int16_T)(-32768)) 85 | #define MAX_uint16_T ((uint16_T)(65535U)) 86 | #define MAX_int32_T ((int32_T)(2147483647)) 87 | #define MIN_int32_T ((int32_T)(-2147483647-1)) 88 | #define MAX_uint32_T ((uint32_T)(0xFFFFFFFFU)) 89 | #define MAX_int64_T ((int64_T)(9223372036854775807LL)) 90 | #define MIN_int64_T ((int64_T)(-9223372036854775807LL-1LL)) 91 | #define MAX_uint64_T ((uint64_T)(0xFFFFFFFFFFFFFFFFULL)) 92 | 93 | /* Block D-Work pointer type */ 94 | typedef void * pointer_T; 95 | 96 | #endif /* RTWTYPES_H */ 97 | 98 | /* 99 | * File trailer for generated code. 100 | * 101 | * [EOF] 102 | */ 103 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Ld/Link.ld: -------------------------------------------------------------------------------- 1 | ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V30x_D8C - CH32V305RB-CH32V305FB CH32V30x_D8 - CH32V303CB-CH32V303RB */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ /* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC CH32V30x_D8 - CH32V303VC-CH32V303RC FLASH + RAM supports the following configuration FLASH-192K + RAM-128K FLASH-224K + RAM-96K FLASH-256K + RAM-64K FLASH-288K + RAM-32K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_bkp.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_bkp.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * BKP firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_BKP_H 12 | #define __CH32V30x_BKP_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* Tamper_Pin_active_level */ 21 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 22 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 23 | 24 | /* RTC_output_source_to_output_on_the_Tamper_pin */ 25 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 26 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 27 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 28 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 29 | 30 | /* Data_Backup_Register */ 31 | #define BKP_DR1 ((uint16_t)0x0004) 32 | #define BKP_DR2 ((uint16_t)0x0008) 33 | #define BKP_DR3 ((uint16_t)0x000C) 34 | #define BKP_DR4 ((uint16_t)0x0010) 35 | #define BKP_DR5 ((uint16_t)0x0014) 36 | #define BKP_DR6 ((uint16_t)0x0018) 37 | #define BKP_DR7 ((uint16_t)0x001C) 38 | #define BKP_DR8 ((uint16_t)0x0020) 39 | #define BKP_DR9 ((uint16_t)0x0024) 40 | #define BKP_DR10 ((uint16_t)0x0028) 41 | #define BKP_DR11 ((uint16_t)0x0040) 42 | #define BKP_DR12 ((uint16_t)0x0044) 43 | #define BKP_DR13 ((uint16_t)0x0048) 44 | #define BKP_DR14 ((uint16_t)0x004C) 45 | #define BKP_DR15 ((uint16_t)0x0050) 46 | #define BKP_DR16 ((uint16_t)0x0054) 47 | #define BKP_DR17 ((uint16_t)0x0058) 48 | #define BKP_DR18 ((uint16_t)0x005C) 49 | #define BKP_DR19 ((uint16_t)0x0060) 50 | #define BKP_DR20 ((uint16_t)0x0064) 51 | #define BKP_DR21 ((uint16_t)0x0068) 52 | #define BKP_DR22 ((uint16_t)0x006C) 53 | #define BKP_DR23 ((uint16_t)0x0070) 54 | #define BKP_DR24 ((uint16_t)0x0074) 55 | #define BKP_DR25 ((uint16_t)0x0078) 56 | #define BKP_DR26 ((uint16_t)0x007C) 57 | #define BKP_DR27 ((uint16_t)0x0080) 58 | #define BKP_DR28 ((uint16_t)0x0084) 59 | #define BKP_DR29 ((uint16_t)0x0088) 60 | #define BKP_DR30 ((uint16_t)0x008C) 61 | #define BKP_DR31 ((uint16_t)0x0090) 62 | #define BKP_DR32 ((uint16_t)0x0094) 63 | #define BKP_DR33 ((uint16_t)0x0098) 64 | #define BKP_DR34 ((uint16_t)0x009C) 65 | #define BKP_DR35 ((uint16_t)0x00A0) 66 | #define BKP_DR36 ((uint16_t)0x00A4) 67 | #define BKP_DR37 ((uint16_t)0x00A8) 68 | #define BKP_DR38 ((uint16_t)0x00AC) 69 | #define BKP_DR39 ((uint16_t)0x00B0) 70 | #define BKP_DR40 ((uint16_t)0x00B4) 71 | #define BKP_DR41 ((uint16_t)0x00B8) 72 | #define BKP_DR42 ((uint16_t)0x00BC) 73 | 74 | 75 | void BKP_DeInit(void); 76 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 77 | void BKP_TamperPinCmd(FunctionalState NewState); 78 | void BKP_ITConfig(FunctionalState NewState); 79 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 80 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 81 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 82 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 83 | FlagStatus BKP_GetFlagStatus(void); 84 | void BKP_ClearFlag(void); 85 | ITStatus BKP_GetITStatus(void); 86 | void BKP_ClearITPendingBit(void); 87 | 88 | #ifdef __cplusplus 89 | } 90 | #endif 91 | 92 | #endif 93 | 94 | 95 | 96 | 97 | 98 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_crc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_crc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * CRC firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_CRC_H 12 | #define __CH32V30x_CRC_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | 21 | void CRC_ResetDR(void); 22 | uint32_t CRC_CalcCRC(uint32_t Data); 23 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 24 | uint32_t CRC_GetCRC(void); 25 | void CRC_SetIDRegister(uint8_t IDValue); 26 | uint8_t CRC_GetIDRegister(void); 27 | 28 | #ifdef __cplusplus 29 | } 30 | #endif 31 | 32 | #endif 33 | 34 | 35 | 36 | 37 | 38 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_dac.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_dac.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DAC firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_DAC_H 12 | #define __CH32V30x_DAC_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* DAC Init structure definition */ 21 | typedef struct 22 | { 23 | uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel. 24 | This parameter can be a value of @ref DAC_trigger_selection */ 25 | 26 | uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves 27 | are generated, or whether no wave is generated. 28 | This parameter can be a value of @ref DAC_wave_generation */ 29 | 30 | uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or 31 | the maximum amplitude triangle generation for the DAC channel. 32 | This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ 33 | 34 | uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled. 35 | This parameter can be a value of @ref DAC_output_buffer */ 36 | }DAC_InitTypeDef; 37 | 38 | 39 | /* DAC_trigger_selection */ 40 | #define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register 41 | has been loaded, and not by external trigger */ 42 | #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ 43 | #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel 44 | only in High-density devices*/ 45 | #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ 46 | #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ 47 | #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ 48 | #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ 49 | #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ 50 | #define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ 51 | 52 | /* DAC_wave_generation */ 53 | #define DAC_WaveGeneration_None ((uint32_t)0x00000000) 54 | #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) 55 | #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) 56 | 57 | 58 | /* DAC_lfsrunmask_triangleamplitude */ 59 | #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ 60 | #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ 61 | #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ 62 | #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ 63 | #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ 64 | #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ 65 | #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ 66 | #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ 67 | #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ 68 | #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ 69 | #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ 70 | #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ 71 | #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ 72 | #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ 73 | #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ 74 | #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ 75 | #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ 76 | #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ 77 | #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ 78 | #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ 79 | #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ 80 | #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ 81 | #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ 82 | #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ 83 | 84 | /* DAC_output_buffer */ 85 | #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) 86 | #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) 87 | 88 | /* DAC_Channel_selection */ 89 | #define DAC_Channel_1 ((uint32_t)0x00000000) 90 | #define DAC_Channel_2 ((uint32_t)0x00000010) 91 | 92 | /* DAC_data_alignment */ 93 | #define DAC_Align_12b_R ((uint32_t)0x00000000) 94 | #define DAC_Align_12b_L ((uint32_t)0x00000004) 95 | #define DAC_Align_8b_R ((uint32_t)0x00000008) 96 | 97 | /* DAC_wave_generation */ 98 | #define DAC_Wave_Noise ((uint32_t)0x00000040) 99 | #define DAC_Wave_Triangle ((uint32_t)0x00000080) 100 | 101 | 102 | void DAC_DeInit(void); 103 | void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); 104 | void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); 105 | void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); 106 | void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); 107 | void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); 108 | void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); 109 | void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); 110 | void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); 111 | void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); 112 | void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); 113 | uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); 114 | 115 | #ifdef __cplusplus 116 | } 117 | #endif 118 | 119 | #endif 120 | 121 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_dbgmcu.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DBGMCU firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_DBGMCU_H 12 | #define __CH32V30x_DBGMCU_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 21 | #define DBGMCU_STOP ((uint32_t)0x00000002) 22 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 23 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 24 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 25 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) 26 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) 27 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) 28 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) 29 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) 30 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) 31 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) 32 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) 33 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) 34 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) 35 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) 36 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 37 | #define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) 38 | #define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) 39 | 40 | uint32_t DBGMCU_GetREVID(void); 41 | uint32_t DBGMCU_GetDEVID(void); 42 | uint32_t __get_DEBUG_CR(void); 43 | void __set_DEBUG_CR(uint32_t value); 44 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 45 | 46 | #ifdef __cplusplus 47 | } 48 | #endif 49 | 50 | #endif 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_dvp.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_dvp.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * DVP firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_DVP_H 12 | #define __CH32V30x_DVP_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* DVP Data Mode */ 21 | typedef enum 22 | { 23 | Video_Mode = 0, 24 | JPEG_Mode, 25 | }DVP_Data_ModeTypeDef; 26 | 27 | 28 | /* DVP DMA */ 29 | typedef enum 30 | { 31 | DVP_DMA_Disable = 0, 32 | DVP_DMA_Enable, 33 | }DVP_DMATypeDef; 34 | 35 | /* DVP FLAG and FIFO Reset */ 36 | typedef enum 37 | { 38 | DVP_FLAG_FIFO_RESET_Disable = 0, 39 | DVP_FLAG_FIFO_RESET_Enable, 40 | }DVP_FLAG_FIFO_RESETTypeDef; 41 | 42 | /* DVP RX Reset */ 43 | typedef enum 44 | { 45 | DVP_RX_RESET_Disable = 0, 46 | DVP_RX_RESET_Enable, 47 | }DVP_RX_RESETTypeDef; 48 | 49 | 50 | 51 | void DVP_INTCfg( uint8_t s, uint8_t i ); 52 | void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i); 53 | void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); 54 | 55 | 56 | 57 | #ifdef __cplusplus 58 | } 59 | #endif 60 | 61 | #endif 62 | 63 | 64 | 65 | 66 | 67 | 68 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_exti.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_exti.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * EXTI firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_EXTI_H 12 | #define __CH32V30x_EXTI_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* EXTI mode enumeration */ 21 | typedef enum 22 | { 23 | EXTI_Mode_Interrupt = 0x00, 24 | EXTI_Mode_Event = 0x04 25 | }EXTIMode_TypeDef; 26 | 27 | /* EXTI Trigger enumeration */ 28 | typedef enum 29 | { 30 | EXTI_Trigger_Rising = 0x08, 31 | EXTI_Trigger_Falling = 0x0C, 32 | EXTI_Trigger_Rising_Falling = 0x10 33 | }EXTITrigger_TypeDef; 34 | 35 | /* EXTI Init Structure definition */ 36 | typedef struct 37 | { 38 | uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. 39 | This parameter can be any combination of @ref EXTI_Lines */ 40 | 41 | EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. 42 | This parameter can be a value of @ref EXTIMode_TypeDef */ 43 | 44 | EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. 45 | This parameter can be a value of @ref EXTIMode_TypeDef */ 46 | 47 | FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. 48 | This parameter can be set either to ENABLE or DISABLE */ 49 | }EXTI_InitTypeDef; 50 | 51 | 52 | /* EXTI_Lines */ 53 | #define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ 54 | #define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ 55 | #define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ 56 | #define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ 57 | #define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ 58 | #define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ 59 | #define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ 60 | #define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ 61 | #define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ 62 | #define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ 63 | #define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ 64 | #define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ 65 | #define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ 66 | #define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ 67 | #define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ 68 | #define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ 69 | #define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ 70 | #define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ 71 | #define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG 72 | Wakeup from suspend event */ 73 | #define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ 74 | #define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */ 75 | 76 | void EXTI_DeInit(void); 77 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 78 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 79 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 80 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 81 | void EXTI_ClearFlag(uint32_t EXTI_Line); 82 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 83 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif 90 | 91 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_flash.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_flash.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the FLASH 7 | * firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_FLASH_H 12 | #define __CH32V30x_FLASH_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* FLASH Status */ 21 | typedef enum 22 | { 23 | FLASH_BUSY = 1, 24 | FLASH_ERROR_PG, 25 | FLASH_ERROR_WRP, 26 | FLASH_COMPLETE, 27 | FLASH_TIMEOUT 28 | }FLASH_Status; 29 | 30 | 31 | /* Write Protect */ 32 | #define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */ 33 | #define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */ 34 | #define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 0 */ 35 | #define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 0 */ 36 | #define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 0 */ 37 | #define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 0 */ 38 | #define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 0 */ 39 | #define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 0 */ 40 | #define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 0 */ 41 | #define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 0 */ 42 | #define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 0 */ 43 | #define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 0 */ 44 | #define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 0 */ 45 | #define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 0 */ 46 | #define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 0 */ 47 | #define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 0 */ 48 | #define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 0 */ 49 | #define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 0 */ 50 | #define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 0 */ 51 | #define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 0 */ 52 | #define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 0 */ 53 | #define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 0 */ 54 | #define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 0 */ 55 | #define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 0 */ 56 | #define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 0 */ 57 | #define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 0 */ 58 | #define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 0 */ 59 | #define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 0 */ 60 | #define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 0 */ 61 | #define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 0 */ 62 | #define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 0 */ 63 | #define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */ 64 | 65 | #define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ 66 | 67 | /* Option_Bytes_IWatchdog */ 68 | #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ 69 | #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ 70 | 71 | /* Option_Bytes_nRST_STOP */ 72 | #define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ 73 | #define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ 74 | 75 | /* Option_Bytes_nRST_STDBY */ 76 | #define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ 77 | #define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ 78 | 79 | /* FLASH_Interrupts */ 80 | #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ 81 | #define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ 82 | #define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ 83 | #define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ 84 | 85 | /* FLASH_Flags */ 86 | #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ 87 | #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ 88 | #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ 89 | #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ 90 | 91 | #define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ 92 | #define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ 93 | #define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ 94 | 95 | /* FLASH_Access_CLK */ 96 | #define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */ 97 | #define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */ 98 | 99 | 100 | /*Functions used for all devices*/ 101 | void FLASH_Unlock(void); 102 | void FLASH_Lock(void); 103 | FLASH_Status FLASH_ErasePage(uint32_t Page_Address); 104 | FLASH_Status FLASH_EraseAllPages(void); 105 | FLASH_Status FLASH_EraseOptionBytes(void); 106 | FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); 107 | FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); 108 | FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); 109 | FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); 110 | FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); 111 | FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); 112 | uint32_t FLASH_GetUserOptionByte(void); 113 | uint32_t FLASH_GetWriteProtectionOptionByte(void); 114 | FlagStatus FLASH_GetReadOutProtectionStatus(void); 115 | void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); 116 | FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); 117 | void FLASH_ClearFlag(uint32_t FLASH_FLAG); 118 | FLASH_Status FLASH_GetStatus(void); 119 | FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); 120 | void FLASH_Unlock_Fast(void); 121 | void FLASH_Lock_Fast(void); 122 | void FLASH_ErasePage_Fast(uint32_t Page_Address); 123 | void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); 124 | void FLASH_EraseBlock_64K_Fast(uint32_t Block_Address); 125 | void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf); 126 | void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); 127 | void FLASH_Enhance_Mode(FunctionalState NewState); 128 | 129 | /* New function used for all devices */ 130 | void FLASH_UnlockBank1(void); 131 | void FLASH_LockBank1(void); 132 | FLASH_Status FLASH_EraseAllBank1Pages(void); 133 | FLASH_Status FLASH_GetBank1Status(void); 134 | FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); 135 | 136 | #ifdef __cplusplus 137 | } 138 | #endif 139 | 140 | 141 | #endif 142 | 143 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_gpio.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_gpio.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * GPIO firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_GPIO_H 12 | #define __CH32V30x_GPIO_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* Output Maximum frequency selection */ 21 | typedef enum 22 | { 23 | GPIO_Speed_10MHz = 1, 24 | GPIO_Speed_2MHz, 25 | GPIO_Speed_50MHz 26 | }GPIOSpeed_TypeDef; 27 | 28 | /* Configuration Mode enumeration */ 29 | typedef enum 30 | { GPIO_Mode_AIN = 0x0, 31 | GPIO_Mode_IN_FLOATING = 0x04, 32 | GPIO_Mode_IPD = 0x28, 33 | GPIO_Mode_IPU = 0x48, 34 | GPIO_Mode_Out_OD = 0x14, 35 | GPIO_Mode_Out_PP = 0x10, 36 | GPIO_Mode_AF_OD = 0x1C, 37 | GPIO_Mode_AF_PP = 0x18 38 | }GPIOMode_TypeDef; 39 | 40 | /* GPIO Init structure definition */ 41 | typedef struct 42 | { 43 | uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. 44 | This parameter can be any value of @ref GPIO_pins_define */ 45 | 46 | GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. 47 | This parameter can be a value of @ref GPIOSpeed_TypeDef */ 48 | 49 | GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. 50 | This parameter can be a value of @ref GPIOMode_TypeDef */ 51 | }GPIO_InitTypeDef; 52 | 53 | /* Bit_SET and Bit_RESET enumeration */ 54 | typedef enum 55 | { 56 | Bit_RESET = 0, 57 | Bit_SET 58 | }BitAction; 59 | 60 | /* GPIO_pins_define */ 61 | #define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ 62 | #define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ 63 | #define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ 64 | #define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ 65 | #define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ 66 | #define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ 67 | #define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ 68 | #define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ 69 | #define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ 70 | #define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ 71 | #define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ 72 | #define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ 73 | #define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ 74 | #define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ 75 | #define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ 76 | #define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ 77 | #define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ 78 | 79 | /* GPIO_Remap_define */ 80 | /* PCFR1 */ 81 | #define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ 82 | #define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ 83 | #define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ 84 | #define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ 85 | #define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ 86 | #define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ 87 | #define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ 88 | #define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ 89 | #define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ 90 | #define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ 91 | #define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ 92 | #define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ 93 | #define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ 94 | #define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ 95 | #define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ 96 | #define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ 97 | #define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */ 98 | #define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ 99 | #define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ 100 | #define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ 101 | #define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ 102 | #define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ 103 | #define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ 104 | #define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ 105 | #define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ 106 | #define GPIO_Remap_SWJ_NoJTRST ((uint32_t)0x00300100) /* Full SWJ Enabled (JTAG-DP + SW-DP) but without JTRST */ 107 | #define GPIO_Remap_SWJ_JTAGDisable ((uint32_t)0x00300200) /* JTAG-DP Disabled and SW-DP Enabled */ 108 | #define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */ 109 | #define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ 110 | #define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected 111 | to TIM2 Internal Trigger 1 for calibration 112 | (only for Connectivity line devices) */ 113 | #define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ 114 | 115 | /* PCFR2 */ 116 | #define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ 117 | #define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ 118 | #define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ 119 | #define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ 120 | #define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ 121 | #define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ 122 | #define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ 123 | #define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ 124 | #define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ 125 | #define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ 126 | #define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ 127 | #define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ 128 | #define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ 129 | #define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ 130 | #define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ 131 | #define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ 132 | #define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ 133 | 134 | 135 | /* GPIO_Port_Sources */ 136 | #define GPIO_PortSourceGPIOA ((uint8_t)0x00) 137 | #define GPIO_PortSourceGPIOB ((uint8_t)0x01) 138 | #define GPIO_PortSourceGPIOC ((uint8_t)0x02) 139 | #define GPIO_PortSourceGPIOD ((uint8_t)0x03) 140 | #define GPIO_PortSourceGPIOE ((uint8_t)0x04) 141 | #define GPIO_PortSourceGPIOF ((uint8_t)0x05) 142 | #define GPIO_PortSourceGPIOG ((uint8_t)0x06) 143 | 144 | /* GPIO_Pin_sources */ 145 | #define GPIO_PinSource0 ((uint8_t)0x00) 146 | #define GPIO_PinSource1 ((uint8_t)0x01) 147 | #define GPIO_PinSource2 ((uint8_t)0x02) 148 | #define GPIO_PinSource3 ((uint8_t)0x03) 149 | #define GPIO_PinSource4 ((uint8_t)0x04) 150 | #define GPIO_PinSource5 ((uint8_t)0x05) 151 | #define GPIO_PinSource6 ((uint8_t)0x06) 152 | #define GPIO_PinSource7 ((uint8_t)0x07) 153 | #define GPIO_PinSource8 ((uint8_t)0x08) 154 | #define GPIO_PinSource9 ((uint8_t)0x09) 155 | #define GPIO_PinSource10 ((uint8_t)0x0A) 156 | #define GPIO_PinSource11 ((uint8_t)0x0B) 157 | #define GPIO_PinSource12 ((uint8_t)0x0C) 158 | #define GPIO_PinSource13 ((uint8_t)0x0D) 159 | #define GPIO_PinSource14 ((uint8_t)0x0E) 160 | #define GPIO_PinSource15 ((uint8_t)0x0F) 161 | 162 | /* Ethernet_Media_Interface */ 163 | #define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) 164 | #define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) 165 | 166 | 167 | void GPIO_DeInit(GPIO_TypeDef* GPIOx); 168 | void GPIO_AFIODeInit(void); 169 | void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); 170 | void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); 171 | uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 172 | uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); 173 | uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 174 | uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); 175 | void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 176 | void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 177 | void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); 178 | void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); 179 | void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); 180 | void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 181 | void GPIO_EventOutputCmd(FunctionalState NewState); 182 | void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); 183 | void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); 184 | void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); 185 | 186 | #ifdef __cplusplus 187 | } 188 | #endif 189 | 190 | #endif 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_i2c.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_i2c.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * I2C firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_I2C_H 12 | #define __CH32V30x_I2C_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* I2C Init structure definition */ 21 | typedef struct 22 | { 23 | uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. 24 | This parameter must be set to a value lower than 400kHz */ 25 | 26 | uint16_t I2C_Mode; /* Specifies the I2C mode. 27 | This parameter can be a value of @ref I2C_mode */ 28 | 29 | uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. 30 | This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ 31 | 32 | uint16_t I2C_OwnAddress1; /* Specifies the first device own address. 33 | This parameter can be a 7-bit or 10-bit address. */ 34 | 35 | uint16_t I2C_Ack; /* Enables or disables the acknowledgement. 36 | This parameter can be a value of @ref I2C_acknowledgement */ 37 | 38 | uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. 39 | This parameter can be a value of @ref I2C_acknowledged_address */ 40 | }I2C_InitTypeDef; 41 | 42 | /* I2C_mode */ 43 | #define I2C_Mode_I2C ((uint16_t)0x0000) 44 | #define I2C_Mode_SMBusDevice ((uint16_t)0x0002) 45 | #define I2C_Mode_SMBusHost ((uint16_t)0x000A) 46 | 47 | /* I2C_duty_cycle_in_fast_mode */ 48 | #define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ 49 | #define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ 50 | 51 | /* I2C_acknowledgement */ 52 | #define I2C_Ack_Enable ((uint16_t)0x0400) 53 | #define I2C_Ack_Disable ((uint16_t)0x0000) 54 | 55 | /* I2C_transfer_direction */ 56 | #define I2C_Direction_Transmitter ((uint8_t)0x00) 57 | #define I2C_Direction_Receiver ((uint8_t)0x01) 58 | 59 | /* I2C_acknowledged_address */ 60 | #define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) 61 | #define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) 62 | 63 | /* I2C_registers */ 64 | #define I2C_Register_CTLR1 ((uint8_t)0x00) 65 | #define I2C_Register_CTLR2 ((uint8_t)0x04) 66 | #define I2C_Register_OADDR1 ((uint8_t)0x08) 67 | #define I2C_Register_OADDR2 ((uint8_t)0x0C) 68 | #define I2C_Register_DATAR ((uint8_t)0x10) 69 | #define I2C_Register_STAR1 ((uint8_t)0x14) 70 | #define I2C_Register_STAR2 ((uint8_t)0x18) 71 | #define I2C_Register_CKCFGR ((uint8_t)0x1C) 72 | #define I2C_Register_RTR ((uint8_t)0x20) 73 | 74 | /* I2C_SMBus_alert_pin_level */ 75 | #define I2C_SMBusAlert_Low ((uint16_t)0x2000) 76 | #define I2C_SMBusAlert_High ((uint16_t)0xDFFF) 77 | 78 | /* I2C_PEC_position */ 79 | #define I2C_PECPosition_Next ((uint16_t)0x0800) 80 | #define I2C_PECPosition_Current ((uint16_t)0xF7FF) 81 | 82 | /* I2C_NACK_position */ 83 | #define I2C_NACKPosition_Next ((uint16_t)0x0800) 84 | #define I2C_NACKPosition_Current ((uint16_t)0xF7FF) 85 | 86 | /* I2C_interrupts_definition */ 87 | #define I2C_IT_BUF ((uint16_t)0x0400) 88 | #define I2C_IT_EVT ((uint16_t)0x0200) 89 | #define I2C_IT_ERR ((uint16_t)0x0100) 90 | 91 | /* I2C_interrupts_definition */ 92 | #define I2C_IT_SMBALERT ((uint32_t)0x01008000) 93 | #define I2C_IT_TIMEOUT ((uint32_t)0x01004000) 94 | #define I2C_IT_PECERR ((uint32_t)0x01001000) 95 | #define I2C_IT_OVR ((uint32_t)0x01000800) 96 | #define I2C_IT_AF ((uint32_t)0x01000400) 97 | #define I2C_IT_ARLO ((uint32_t)0x01000200) 98 | #define I2C_IT_BERR ((uint32_t)0x01000100) 99 | #define I2C_IT_TXE ((uint32_t)0x06000080) 100 | #define I2C_IT_RXNE ((uint32_t)0x06000040) 101 | #define I2C_IT_STOPF ((uint32_t)0x02000010) 102 | #define I2C_IT_ADD10 ((uint32_t)0x02000008) 103 | #define I2C_IT_BTF ((uint32_t)0x02000004) 104 | #define I2C_IT_ADDR ((uint32_t)0x02000002) 105 | #define I2C_IT_SB ((uint32_t)0x02000001) 106 | 107 | /* SR2 register flags */ 108 | #define I2C_FLAG_DUALF ((uint32_t)0x00800000) 109 | #define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) 110 | #define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) 111 | #define I2C_FLAG_GENCALL ((uint32_t)0x00100000) 112 | #define I2C_FLAG_TRA ((uint32_t)0x00040000) 113 | #define I2C_FLAG_BUSY ((uint32_t)0x00020000) 114 | #define I2C_FLAG_MSL ((uint32_t)0x00010000) 115 | 116 | /* SR1 register flags */ 117 | #define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) 118 | #define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) 119 | #define I2C_FLAG_PECERR ((uint32_t)0x10001000) 120 | #define I2C_FLAG_OVR ((uint32_t)0x10000800) 121 | #define I2C_FLAG_AF ((uint32_t)0x10000400) 122 | #define I2C_FLAG_ARLO ((uint32_t)0x10000200) 123 | #define I2C_FLAG_BERR ((uint32_t)0x10000100) 124 | #define I2C_FLAG_TXE ((uint32_t)0x10000080) 125 | #define I2C_FLAG_RXNE ((uint32_t)0x10000040) 126 | #define I2C_FLAG_STOPF ((uint32_t)0x10000010) 127 | #define I2C_FLAG_ADD10 ((uint32_t)0x10000008) 128 | #define I2C_FLAG_BTF ((uint32_t)0x10000004) 129 | #define I2C_FLAG_ADDR ((uint32_t)0x10000002) 130 | #define I2C_FLAG_SB ((uint32_t)0x10000001) 131 | 132 | 133 | /****************I2C Master Events (Events grouped in order of communication)********************/ 134 | 135 | #define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ 136 | #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ 137 | #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ 138 | #define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ 139 | #define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ 140 | #define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ 141 | #define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ 142 | 143 | 144 | /******************I2C Slave Events (Events grouped in order of communication)******************/ 145 | 146 | #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ 147 | #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ 148 | #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ 149 | #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ 150 | #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ 151 | #define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ 152 | #define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ 153 | #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ 154 | #define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ 155 | #define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ 156 | 157 | 158 | void I2C_DeInit(I2C_TypeDef* I2Cx); 159 | void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); 160 | void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); 161 | void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 162 | void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 163 | void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 164 | void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); 165 | void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); 166 | void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); 167 | void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); 168 | void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 169 | void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 170 | void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); 171 | void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); 172 | uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); 173 | void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); 174 | uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); 175 | void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 176 | void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); 177 | void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); 178 | void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); 179 | void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); 180 | void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); 181 | uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); 182 | void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 183 | void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); 184 | void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); 185 | 186 | 187 | /**************************************************************************************** 188 | * I2C State Monitoring Functions 189 | ****************************************************************************************/ 190 | 191 | ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); 192 | uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); 193 | FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); 194 | 195 | void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); 196 | ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); 197 | void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); 198 | 199 | #ifdef __cplusplus 200 | } 201 | #endif 202 | 203 | #endif 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_iwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_iwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * IWDG firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_IWDG_H 12 | #define __CH32V30x_IWDG_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* IWDG_WriteAccess */ 21 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 22 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 23 | 24 | /* IWDG_prescaler */ 25 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 26 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 27 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 28 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 29 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 30 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 31 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 32 | 33 | /* IWDG_Flag */ 34 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 35 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 36 | 37 | 38 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 39 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 40 | void IWDG_SetReload(uint16_t Reload); 41 | void IWDG_ReloadCounter(void); 42 | void IWDG_Enable(void); 43 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 44 | 45 | #ifdef __cplusplus 46 | } 47 | #endif 48 | 49 | #endif 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_misc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_misc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * miscellaneous firmware library functions. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30X_MISC_H 12 | #define __CH32V30X_MISC_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* NVIC Init Structure definition */ 21 | typedef struct 22 | { 23 | uint8_t NVIC_IRQChannel; 24 | uint8_t NVIC_IRQChannelPreemptionPriority; 25 | uint8_t NVIC_IRQChannelSubPriority; 26 | FunctionalState NVIC_IRQChannelCmd; 27 | } NVIC_InitTypeDef; 28 | 29 | 30 | /* Preemption_Priority_Group */ 31 | #define NVIC_PriorityGroup_0 ((uint32_t)0x00) 32 | #define NVIC_PriorityGroup_1 ((uint32_t)0x01) 33 | #define NVIC_PriorityGroup_2 ((uint32_t)0x02) 34 | #define NVIC_PriorityGroup_3 ((uint32_t)0x03) 35 | #define NVIC_PriorityGroup_4 ((uint32_t)0x04) 36 | 37 | 38 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 39 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 40 | 41 | #ifdef __cplusplus 42 | } 43 | #endif 44 | 45 | #endif 46 | 47 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_opa.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_opa.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * OPA firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_OPA_H 12 | #define __CH32V30x_OPA_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | #define OPA_PSEL_OFFSET 3 21 | #define OPA_NSEL_OFFSET 2 22 | #define OPA_MODE_OFFSET 1 23 | 24 | 25 | /* OPA member enumeration */ 26 | typedef enum 27 | { 28 | OPA1=0, 29 | OPA2, 30 | OPA3, 31 | OPA4 32 | }OPA_Num_TypeDef; 33 | 34 | /* OPA PSEL enumeration */ 35 | typedef enum 36 | { 37 | CHP0=0, 38 | CHP1 39 | }OPA_PSEL_TypeDef; 40 | 41 | /* OPA NSEL enumeration */ 42 | typedef enum 43 | { 44 | CHN0=0, 45 | CHN1 46 | }OPA_NSEL_TypeDef; 47 | 48 | /* OPA out channel enumeration */ 49 | typedef enum 50 | { 51 | OUT_IO_OUT0=0, 52 | OUT_IO_OUT1 53 | }OPA_Mode_TypeDef; 54 | 55 | /* OPA Init Structure definition */ 56 | typedef struct 57 | { 58 | OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ 59 | OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ 60 | OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ 61 | OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ 62 | }OPA_InitTypeDef; 63 | 64 | 65 | void OPA_DeInit(void); 66 | void OPA_Init(OPA_InitTypeDef* OPA_InitStruct); 67 | void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); 68 | void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif 73 | 74 | #endif 75 | 76 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_pwr.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_pwr.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the PWR 7 | * firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_PWR_H 12 | #define __CH32V30x_PWR_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* PVD_detection_level */ 21 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 22 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 23 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 24 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 25 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 26 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 27 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 28 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 29 | 30 | /* Regulator_state_is_STOP_mode */ 31 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 32 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 33 | 34 | /* STOP_mode_entry */ 35 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 36 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 37 | 38 | /* PWR_Flag */ 39 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 40 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 41 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 42 | 43 | 44 | void PWR_DeInit(void); 45 | void PWR_BackupAccessCmd(FunctionalState NewState); 46 | void PWR_PVDCmd(FunctionalState NewState); 47 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 48 | void PWR_WakeUpPinCmd(FunctionalState NewState); 49 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 50 | void PWR_EnterSTANDBYMode(void); 51 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 52 | void PWR_ClearFlag(uint32_t PWR_FLAG); 53 | void PWR_EnterSTANDBYMode_RAM(void); 54 | void PWR_EnterSTANDBYMode_RAM_LV(void); 55 | void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); 56 | void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); 57 | void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 58 | 59 | #ifdef __cplusplus 60 | } 61 | #endif 62 | 63 | #endif 64 | 65 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_rng.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_rng.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * RNG firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_RNG_H 12 | #define __CH32V30x_RNG_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | #include "ch32v30x.h" 18 | 19 | /* RNG_flags_definition*/ 20 | #define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ 21 | #define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ 22 | #define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ 23 | 24 | /* RNG_interrupts_definition */ 25 | #define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ 26 | #define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ 27 | 28 | 29 | void RNG_Cmd(FunctionalState NewState); 30 | uint32_t RNG_GetRandomNumber(void); 31 | void RNG_ITConfig(FunctionalState NewState); 32 | FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); 33 | void RNG_ClearFlag(uint8_t RNG_FLAG); 34 | ITStatus RNG_GetITStatus(uint8_t RNG_IT); 35 | void RNG_ClearITPendingBit(uint8_t RNG_IT); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_rtc.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_rtc.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the RTC 7 | * firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_RTC_H 12 | #define __CH32V30x_RTC_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | 21 | /* RTC_interrupts_define */ 22 | #define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ 23 | #define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ 24 | #define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ 25 | 26 | /* RTC_interrupts_flags */ 27 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ 28 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ 29 | #define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ 30 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ 31 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ 32 | 33 | 34 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 35 | void RTC_EnterConfigMode(void); 36 | void RTC_ExitConfigMode(void); 37 | uint32_t RTC_GetCounter(void); 38 | void RTC_SetCounter(uint32_t CounterValue); 39 | void RTC_SetPrescaler(uint32_t PrescalerValue); 40 | void RTC_SetAlarm(uint32_t AlarmValue); 41 | uint32_t RTC_GetDivider(void); 42 | void RTC_WaitForLastTask(void); 43 | void RTC_WaitForSynchro(void); 44 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 45 | void RTC_ClearFlag(uint16_t RTC_FLAG); 46 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 47 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 48 | 49 | #ifdef __cplusplus 50 | } 51 | #endif 52 | 53 | #endif 54 | 55 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_spi.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_spi.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * SPI firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_SPI_H 12 | #define __CH32V30x_SPI_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | /* SPI Init structure definition */ 21 | typedef struct 22 | { 23 | uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. 24 | This parameter can be a value of @ref SPI_data_direction */ 25 | 26 | uint16_t SPI_Mode; /* Specifies the SPI operating mode. 27 | This parameter can be a value of @ref SPI_mode */ 28 | 29 | uint16_t SPI_DataSize; /* Specifies the SPI data size. 30 | This parameter can be a value of @ref SPI_data_size */ 31 | 32 | uint16_t SPI_CPOL; /* Specifies the serial clock steady state. 33 | This parameter can be a value of @ref SPI_Clock_Polarity */ 34 | 35 | uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. 36 | This parameter can be a value of @ref SPI_Clock_Phase */ 37 | 38 | uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by 39 | hardware (NSS pin) or by software using the SSI bit. 40 | This parameter can be a value of @ref SPI_Slave_Select_management */ 41 | 42 | uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be 43 | used to configure the transmit and receive SCK clock. 44 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. 45 | @note The communication clock is derived from the master 46 | clock. The slave clock does not need to be set. */ 47 | 48 | uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. 49 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 50 | 51 | uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ 52 | }SPI_InitTypeDef; 53 | 54 | /* I2S Init structure definition */ 55 | typedef struct 56 | { 57 | 58 | uint16_t I2S_Mode; /* Specifies the I2S operating mode. 59 | This parameter can be a value of @ref I2S_Mode */ 60 | 61 | uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. 62 | This parameter can be a value of @ref I2S_Standard */ 63 | 64 | uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. 65 | This parameter can be a value of @ref I2S_Data_Format */ 66 | 67 | uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. 68 | This parameter can be a value of @ref I2S_MCLK_Output */ 69 | 70 | uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. 71 | This parameter can be a value of @ref I2S_Audio_Frequency */ 72 | 73 | uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. 74 | This parameter can be a value of @ref I2S_Clock_Polarity */ 75 | }I2S_InitTypeDef; 76 | 77 | /* SPI_data_direction */ 78 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 79 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 80 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 81 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 82 | 83 | /* SPI_mode */ 84 | #define SPI_Mode_Master ((uint16_t)0x0104) 85 | #define SPI_Mode_Slave ((uint16_t)0x0000) 86 | 87 | /* SPI_data_size */ 88 | #define SPI_DataSize_16b ((uint16_t)0x0800) 89 | #define SPI_DataSize_8b ((uint16_t)0x0000) 90 | 91 | /* SPI_Clock_Polarity */ 92 | #define SPI_CPOL_Low ((uint16_t)0x0000) 93 | #define SPI_CPOL_High ((uint16_t)0x0002) 94 | 95 | /* SPI_Clock_Phase */ 96 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) 97 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) 98 | 99 | /* SPI_Slave_Select_management */ 100 | #define SPI_NSS_Soft ((uint16_t)0x0200) 101 | #define SPI_NSS_Hard ((uint16_t)0x0000) 102 | 103 | /* SPI_BaudRate_Prescaler */ 104 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 105 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 106 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 107 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 108 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 109 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 110 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 111 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 112 | 113 | /* SPI_MSB_LSB_transmission */ 114 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) 115 | #define SPI_FirstBit_LSB ((uint16_t)0x0080) 116 | 117 | /* I2S_Mode */ 118 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 119 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 120 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) 121 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) 122 | 123 | /* I2S_Standard */ 124 | #define I2S_Standard_Phillips ((uint16_t)0x0000) 125 | #define I2S_Standard_MSB ((uint16_t)0x0010) 126 | #define I2S_Standard_LSB ((uint16_t)0x0020) 127 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) 128 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 129 | 130 | /* I2S_Data_Format */ 131 | #define I2S_DataFormat_16b ((uint16_t)0x0000) 132 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 133 | #define I2S_DataFormat_24b ((uint16_t)0x0003) 134 | #define I2S_DataFormat_32b ((uint16_t)0x0005) 135 | 136 | /* I2S_MCLK_Output */ 137 | #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 138 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 139 | 140 | /* I2S_Audio_Frequency */ 141 | #define I2S_AudioFreq_192k ((uint32_t)192000) 142 | #define I2S_AudioFreq_96k ((uint32_t)96000) 143 | #define I2S_AudioFreq_48k ((uint32_t)48000) 144 | #define I2S_AudioFreq_44k ((uint32_t)44100) 145 | #define I2S_AudioFreq_32k ((uint32_t)32000) 146 | #define I2S_AudioFreq_22k ((uint32_t)22050) 147 | #define I2S_AudioFreq_16k ((uint32_t)16000) 148 | #define I2S_AudioFreq_11k ((uint32_t)11025) 149 | #define I2S_AudioFreq_8k ((uint32_t)8000) 150 | #define I2S_AudioFreq_Default ((uint32_t)2) 151 | 152 | /* I2S_Clock_Polarity */ 153 | #define I2S_CPOL_Low ((uint16_t)0x0000) 154 | #define I2S_CPOL_High ((uint16_t)0x0008) 155 | 156 | /* SPI_I2S_DMA_transfer_requests */ 157 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 158 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 159 | 160 | /* SPI_NSS_internal_software_management */ 161 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 162 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 163 | 164 | /* SPI_CRC_Transmit_Receive */ 165 | #define SPI_CRC_Tx ((uint8_t)0x00) 166 | #define SPI_CRC_Rx ((uint8_t)0x01) 167 | 168 | /* SPI_direction_transmit_receive */ 169 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) 170 | #define SPI_Direction_Tx ((uint16_t)0x4000) 171 | 172 | /* SPI_I2S_interrupts_definition */ 173 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) 174 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 175 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) 176 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) 177 | #define SPI_IT_MODF ((uint8_t)0x55) 178 | #define SPI_IT_CRCERR ((uint8_t)0x54) 179 | #define I2S_IT_UDR ((uint8_t)0x53) 180 | 181 | /* SPI_I2S_flags_definition */ 182 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 183 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 184 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 185 | #define I2S_FLAG_UDR ((uint16_t)0x0008) 186 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 187 | #define SPI_FLAG_MODF ((uint16_t)0x0020) 188 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 189 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 190 | 191 | 192 | void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 193 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 194 | void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); 195 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 196 | void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); 197 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 198 | void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 199 | void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 200 | void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 201 | void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); 202 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); 203 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 204 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 205 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 206 | void SPI_TransmitCRC(SPI_TypeDef* SPIx); 207 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 208 | uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 209 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 210 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 211 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 212 | void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 213 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 214 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 215 | 216 | #ifdef __cplusplus 217 | } 218 | #endif 219 | 220 | #endif 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_usart.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_usart.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the 7 | * USART firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_USART_H 12 | #define __CH32V30x_USART_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | 21 | /* USART Init Structure definition */ 22 | typedef struct 23 | { 24 | uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. 25 | The baud rate is computed using the following formula: 26 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) 27 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ 28 | 29 | uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. 30 | This parameter can be a value of @ref USART_Word_Length */ 31 | 32 | uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. 33 | This parameter can be a value of @ref USART_Stop_Bits */ 34 | 35 | uint16_t USART_Parity; /* Specifies the parity mode. 36 | This parameter can be a value of @ref USART_Parity 37 | @note When parity is enabled, the computed parity is inserted 38 | at the MSB position of the transmitted data (9th bit when 39 | the word length is set to 9 data bits; 8th bit when the 40 | word length is set to 8 data bits). */ 41 | 42 | uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. 43 | This parameter can be a value of @ref USART_Mode */ 44 | 45 | uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled 46 | or disabled. 47 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ 48 | } USART_InitTypeDef; 49 | 50 | /* USART Clock Init Structure definition */ 51 | typedef struct 52 | { 53 | 54 | uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. 55 | This parameter can be a value of @ref USART_Clock */ 56 | 57 | uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. 58 | This parameter can be a value of @ref USART_Clock_Polarity */ 59 | 60 | uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. 61 | This parameter can be a value of @ref USART_Clock_Phase */ 62 | 63 | uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted 64 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. 65 | This parameter can be a value of @ref USART_Last_Bit */ 66 | } USART_ClockInitTypeDef; 67 | 68 | /* USART_Word_Length */ 69 | #define USART_WordLength_8b ((uint16_t)0x0000) 70 | #define USART_WordLength_9b ((uint16_t)0x1000) 71 | 72 | /* USART_Stop_Bits */ 73 | #define USART_StopBits_1 ((uint16_t)0x0000) 74 | #define USART_StopBits_0_5 ((uint16_t)0x1000) 75 | #define USART_StopBits_2 ((uint16_t)0x2000) 76 | #define USART_StopBits_1_5 ((uint16_t)0x3000) 77 | 78 | /* USART_Parity */ 79 | #define USART_Parity_No ((uint16_t)0x0000) 80 | #define USART_Parity_Even ((uint16_t)0x0400) 81 | #define USART_Parity_Odd ((uint16_t)0x0600) 82 | 83 | /* USART_Mode */ 84 | #define USART_Mode_Rx ((uint16_t)0x0004) 85 | #define USART_Mode_Tx ((uint16_t)0x0008) 86 | 87 | /* USART_Hardware_Flow_Control */ 88 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) 89 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) 90 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) 91 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) 92 | 93 | /* USART_Clock */ 94 | #define USART_Clock_Disable ((uint16_t)0x0000) 95 | #define USART_Clock_Enable ((uint16_t)0x0800) 96 | 97 | /* USART_Clock_Polarity */ 98 | #define USART_CPOL_Low ((uint16_t)0x0000) 99 | #define USART_CPOL_High ((uint16_t)0x0400) 100 | 101 | /* USART_Clock_Phase */ 102 | #define USART_CPHA_1Edge ((uint16_t)0x0000) 103 | #define USART_CPHA_2Edge ((uint16_t)0x0200) 104 | 105 | /* USART_Last_Bit */ 106 | #define USART_LastBit_Disable ((uint16_t)0x0000) 107 | #define USART_LastBit_Enable ((uint16_t)0x0100) 108 | 109 | /* USART_Interrupt_definition */ 110 | #define USART_IT_PE ((uint16_t)0x0028) 111 | #define USART_IT_TXE ((uint16_t)0x0727) 112 | #define USART_IT_TC ((uint16_t)0x0626) 113 | #define USART_IT_RXNE ((uint16_t)0x0525) 114 | #define USART_IT_ORE_RX ((uint16_t)0x0325) 115 | #define USART_IT_IDLE ((uint16_t)0x0424) 116 | #define USART_IT_LBD ((uint16_t)0x0846) 117 | #define USART_IT_CTS ((uint16_t)0x096A) 118 | #define USART_IT_ERR ((uint16_t)0x0060) 119 | #define USART_IT_ORE_ER ((uint16_t)0x0360) 120 | #define USART_IT_NE ((uint16_t)0x0260) 121 | #define USART_IT_FE ((uint16_t)0x0160) 122 | 123 | #define USART_IT_ORE USART_IT_ORE_ER 124 | 125 | /* USART_DMA_Requests */ 126 | #define USART_DMAReq_Tx ((uint16_t)0x0080) 127 | #define USART_DMAReq_Rx ((uint16_t)0x0040) 128 | 129 | /* USART_WakeUp_methods */ 130 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) 131 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) 132 | 133 | /* USART_LIN_Break_Detection_Length */ 134 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) 135 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) 136 | 137 | /* USART_IrDA_Low_Power */ 138 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) 139 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) 140 | 141 | /* USART_Flags */ 142 | #define USART_FLAG_CTS ((uint16_t)0x0200) 143 | #define USART_FLAG_LBD ((uint16_t)0x0100) 144 | #define USART_FLAG_TXE ((uint16_t)0x0080) 145 | #define USART_FLAG_TC ((uint16_t)0x0040) 146 | #define USART_FLAG_RXNE ((uint16_t)0x0020) 147 | #define USART_FLAG_IDLE ((uint16_t)0x0010) 148 | #define USART_FLAG_ORE ((uint16_t)0x0008) 149 | #define USART_FLAG_NE ((uint16_t)0x0004) 150 | #define USART_FLAG_FE ((uint16_t)0x0002) 151 | #define USART_FLAG_PE ((uint16_t)0x0001) 152 | 153 | 154 | void USART_DeInit(USART_TypeDef* USARTx); 155 | void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); 156 | void USART_StructInit(USART_InitTypeDef* USART_InitStruct); 157 | void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); 158 | void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); 159 | void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 160 | void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); 161 | void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); 162 | void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); 163 | void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); 164 | void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); 165 | void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); 166 | void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); 167 | void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); 168 | uint16_t USART_ReceiveData(USART_TypeDef* USARTx); 169 | void USART_SendBreak(USART_TypeDef* USARTx); 170 | void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); 171 | void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); 172 | void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); 173 | void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); 174 | void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); 175 | void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 176 | void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); 177 | void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); 178 | void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); 179 | FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); 180 | void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); 181 | ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); 182 | void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); 183 | 184 | #ifdef __cplusplus 185 | } 186 | #endif 187 | 188 | #endif 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/inc/ch32v30x_wwdg.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_wwdg.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains all the functions prototypes for the WWDG 7 | * firmware library. 8 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 9 | * SPDX-License-Identifier: Apache-2.0 10 | *******************************************************************************/ 11 | #ifndef __CH32V30x_WWDG_H 12 | #define __CH32V30x_WWDG_H 13 | 14 | #ifdef __cplusplus 15 | extern "C" { 16 | #endif 17 | 18 | #include "ch32v30x.h" 19 | 20 | 21 | /* WWDG_Prescaler */ 22 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 23 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 24 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 25 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 26 | 27 | 28 | void WWDG_DeInit(void); 29 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 30 | void WWDG_SetWindowValue(uint8_t WindowValue); 31 | void WWDG_EnableIT(void); 32 | void WWDG_SetCounter(uint8_t Counter); 33 | void WWDG_Enable(uint8_t Counter); 34 | FlagStatus WWDG_GetFlagStatus(void); 35 | void WWDG_ClearFlag(void); 36 | 37 | #ifdef __cplusplus 38 | } 39 | #endif 40 | 41 | #endif 42 | 43 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_bkp.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_bkp.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the BKP firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include "ch32v30x_bkp.h" 11 | #include "ch32v30x_rcc.h" 12 | 13 | /* BKP registers bit mask */ 14 | 15 | /* OCTLR register bit mask */ 16 | #define OCTLR_CAL_MASK ((uint16_t)0xFF80) 17 | #define OCTLR_MASK ((uint16_t)0xFC7F) 18 | 19 | /********************************************************************* 20 | * @fn BKP_DeInit 21 | * 22 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 23 | * 24 | * @return none 25 | */ 26 | void BKP_DeInit(void) 27 | { 28 | RCC_BackupResetCmd(ENABLE); 29 | RCC_BackupResetCmd(DISABLE); 30 | } 31 | 32 | /********************************************************************* 33 | * @fn BKP_TamperPinLevelConfig 34 | * 35 | * @brief Configures the Tamper Pin active level. 36 | * 37 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 38 | * BKP_TamperPinLevel_High - Tamper pin active on high level. 39 | * BKP_TamperPinLevel_Low - Tamper pin active on low level. 40 | * 41 | * @return none 42 | */ 43 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 44 | { 45 | if(BKP_TamperPinLevel) 46 | { 47 | BKP->TPCTLR |= (1 << 1); 48 | } 49 | else 50 | { 51 | BKP->TPCTLR &= ~(1 << 1); 52 | } 53 | } 54 | 55 | /********************************************************************* 56 | * @fn BKP_TamperPinCmd 57 | * 58 | * @brief Enables or disables the Tamper Pin activation. 59 | * 60 | * @param NewState - ENABLE or DISABLE. 61 | * 62 | * @return none 63 | */ 64 | void BKP_TamperPinCmd(FunctionalState NewState) 65 | { 66 | if(NewState) 67 | { 68 | BKP->TPCTLR |= (1 << 0); 69 | } 70 | else 71 | { 72 | BKP->TPCTLR &= ~(1 << 0); 73 | } 74 | } 75 | 76 | /********************************************************************* 77 | * @fn BKP_ITConfig 78 | * 79 | * @brief Enables or disables the Tamper Pin Interrupt. 80 | * 81 | * @param NewState - ENABLE or DISABLE. 82 | * 83 | * @return none 84 | */ 85 | void BKP_ITConfig(FunctionalState NewState) 86 | { 87 | if(NewState) 88 | { 89 | BKP->TPCSR |= (1 << 2); 90 | } 91 | else 92 | { 93 | BKP->TPCSR &= ~(1 << 2); 94 | } 95 | } 96 | 97 | /********************************************************************* 98 | * @fn BKP_RTCOutputConfig 99 | * 100 | * @brief Select the RTC output source to output on the Tamper pin. 101 | * 102 | * @param BKP_RTCOutputSource - specifies the RTC output source. 103 | * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. 104 | * BKP_RTCOutputSource_CalibClock - output the RTC clock with 105 | * frequency divided by 64 on the Tamper pin. 106 | * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal 107 | * on the Tamper pin. 108 | * BKP_RTCOutputSource_Second - output the RTC Second pulse 109 | * signal on the Tamper pin. 110 | * 111 | * @return none 112 | */ 113 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 114 | { 115 | uint16_t tmpreg = 0; 116 | 117 | tmpreg = BKP->OCTLR; 118 | tmpreg &= OCTLR_MASK; 119 | tmpreg |= BKP_RTCOutputSource; 120 | BKP->OCTLR = tmpreg; 121 | } 122 | 123 | /********************************************************************* 124 | * @fn BKP_SetRTCCalibrationValue 125 | * 126 | * @brief Sets RTC Clock Calibration value. 127 | * 128 | * @param CalibrationValue - specifies the RTC Clock Calibration value. 129 | * This parameter must be a number between 0 and 0x1F. 130 | * 131 | * @return none 132 | */ 133 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 134 | { 135 | uint16_t tmpreg = 0; 136 | 137 | tmpreg = BKP->OCTLR; 138 | tmpreg &= OCTLR_CAL_MASK; 139 | tmpreg |= CalibrationValue; 140 | BKP->OCTLR = tmpreg; 141 | } 142 | 143 | /********************************************************************* 144 | * @fn BKP_WriteBackupRegister 145 | * 146 | * @brief Writes user data to the specified Data Backup Register. 147 | * 148 | * @param BKP_DR - specifies the Data Backup Register. 149 | * Data - data to write. 150 | * 151 | * @return none 152 | */ 153 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 154 | { 155 | __IO uint32_t tmp = 0; 156 | 157 | tmp = (uint32_t)BKP_BASE; 158 | tmp += BKP_DR; 159 | *(__IO uint32_t *)tmp = Data; 160 | } 161 | 162 | /********************************************************************* 163 | * @fn BKP_ReadBackupRegister 164 | * 165 | * @brief Reads data from the specified Data Backup Register. 166 | * 167 | * @param BKP_DR - specifies the Data Backup Register. 168 | * This parameter can be BKP_DRx where x=[1, 42]. 169 | * 170 | * @return none 171 | */ 172 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 173 | { 174 | __IO uint32_t tmp = 0; 175 | 176 | tmp = (uint32_t)BKP_BASE; 177 | tmp += BKP_DR; 178 | 179 | return (*(__IO uint16_t *)tmp); 180 | } 181 | 182 | /********************************************************************* 183 | * @fn BKP_GetFlagStatus 184 | * 185 | * @brief Checks whether the Tamper Pin Event flag is set or not. 186 | * 187 | * @return FlagStatus - SET or RESET. 188 | */ 189 | FlagStatus BKP_GetFlagStatus(void) 190 | { 191 | if(BKP->TPCSR & (1 << 8)) 192 | { 193 | return SET; 194 | } 195 | else 196 | { 197 | return RESET; 198 | } 199 | } 200 | 201 | /********************************************************************* 202 | * @fn BKP_ClearFlag 203 | * 204 | * @brief Clears Tamper Pin Event pending flag. 205 | * 206 | * @return none 207 | */ 208 | void BKP_ClearFlag(void) 209 | { 210 | BKP->TPCSR |= BKP_CTE; 211 | } 212 | 213 | /********************************************************************* 214 | * @fn BKP_GetITStatus 215 | * 216 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 217 | * 218 | * @return ITStatus - SET or RESET. 219 | */ 220 | ITStatus BKP_GetITStatus(void) 221 | { 222 | if(BKP->TPCSR & (1 << 9)) 223 | { 224 | return SET; 225 | } 226 | else 227 | { 228 | return RESET; 229 | } 230 | } 231 | 232 | /********************************************************************* 233 | * @fn BKP_ClearITPendingBit 234 | * 235 | * @brief Clears Tamper Pin Interrupt pending bit. 236 | * 237 | * @return none 238 | */ 239 | void BKP_ClearITPendingBit(void) 240 | { 241 | BKP->TPCSR |= BKP_CTI; 242 | } 243 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_crc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_crc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the CRC firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include "ch32v30x_crc.h" 11 | 12 | /********************************************************************* 13 | * @fn CRC_ResetDR 14 | * 15 | * @brief Resets the CRC Data register (DR). 16 | * 17 | * @return none 18 | */ 19 | void CRC_ResetDR(void) 20 | { 21 | CRC->CTLR = CRC_CTLR_RESET; 22 | } 23 | 24 | /********************************************************************* 25 | * @fn CRC_CalcCRC 26 | * 27 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 28 | * 29 | * @param Data - data word(32-bit) to compute its CRC. 30 | * 31 | * @return 32-bit CRC. 32 | */ 33 | uint32_t CRC_CalcCRC(uint32_t Data) 34 | { 35 | CRC->DATAR = Data; 36 | 37 | return (CRC->DATAR); 38 | } 39 | 40 | /********************************************************************* 41 | * @fn CRC_CalcBlockCRC 42 | * 43 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 44 | * 45 | * @param pBuffer - pointer to the buffer containing the data to be computed. 46 | * BufferLength - length of the buffer to be computed. 47 | * 48 | * @return 32-bit CRC. 49 | */ 50 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 51 | { 52 | uint32_t index = 0; 53 | 54 | for(index = 0; index < BufferLength; index++) 55 | { 56 | CRC->DATAR = pBuffer[index]; 57 | } 58 | 59 | return (CRC->DATAR); 60 | } 61 | 62 | /********************************************************************* 63 | * @fn CRC_GetCRC 64 | * 65 | * @brief Returns the current CRC value. 66 | * 67 | * @return 32-bit CRC. 68 | */ 69 | uint32_t CRC_GetCRC(void) 70 | { 71 | return (CRC->DATAR); 72 | } 73 | 74 | /********************************************************************* 75 | * @fn CRC_SetIDRegister 76 | * 77 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 78 | * 79 | * @param IDValue - 8-bit value to be stored in the ID register. 80 | * 81 | * @return none 82 | */ 83 | void CRC_SetIDRegister(uint8_t IDValue) 84 | { 85 | CRC->IDATAR = IDValue; 86 | } 87 | 88 | /********************************************************************* 89 | * @fn CRC_GetIDRegister 90 | * 91 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register. 92 | * 93 | * @return 8-bit value of the ID register. 94 | */ 95 | uint8_t CRC_GetIDRegister(void) 96 | { 97 | return (CRC->IDATAR); 98 | } 99 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_dac.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_dac.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the DAC firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | ****************************************************************************************/ 10 | #include "ch32v30x_dac.h" 11 | #include "ch32v30x_rcc.h" 12 | 13 | /* CTLR register Mask */ 14 | #define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) 15 | 16 | /* DAC Dual Channels SWTR masks */ 17 | #define DUAL_SWTR_SET ((uint32_t)0x00000003) 18 | #define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) 19 | 20 | /* DHR registers offsets */ 21 | #define DHR12R1_OFFSET ((uint32_t)0x00000008) 22 | #define DHR12R2_OFFSET ((uint32_t)0x00000014) 23 | #define DHR12RD_OFFSET ((uint32_t)0x00000020) 24 | 25 | /* DOR register offset */ 26 | #define DOR_OFFSET ((uint32_t)0x0000002C) 27 | 28 | /********************************************************************* 29 | * @fn DAC_DeInit 30 | * 31 | * @brief Deinitializes the DAC peripheral registers to their default reset values. 32 | * 33 | * @return none 34 | */ 35 | void DAC_DeInit(void) 36 | { 37 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); 38 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); 39 | } 40 | 41 | /********************************************************************* 42 | * @fn DAC_Init 43 | * 44 | * @brief Initializes the DAC peripheral according to the specified parameters in 45 | * the DAC_InitStruct. 46 | * 47 | * @param DAC_Channel - the selected DAC channel. 48 | * DAC_Channel_1 - DAC Channel1 selected 49 | * DAC_Channel_2 - DAC Channel2 selected 50 | * DAC_InitStruct - pointer to a DAC_InitTypeDef structure. 51 | * 52 | * @return none 53 | */ 54 | void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct) 55 | { 56 | uint32_t tmpreg1 = 0, tmpreg2 = 0; 57 | 58 | tmpreg1 = DAC->CTLR; 59 | tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel); 60 | tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | 61 | DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); 62 | tmpreg1 |= tmpreg2 << DAC_Channel; 63 | DAC->CTLR = tmpreg1; 64 | } 65 | 66 | /********************************************************************* 67 | * @fn DAC_StructInit 68 | * 69 | * @brief Fills each DAC_InitStruct member with its default value. 70 | * 71 | * @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized. 72 | * 73 | * @return none 74 | */ 75 | void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct) 76 | { 77 | DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; 78 | DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; 79 | DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; 80 | DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; 81 | } 82 | 83 | /********************************************************************* 84 | * @fn DAC_Cmd 85 | * 86 | * @brief Enables or disables the specified DAC channel. 87 | * 88 | * @param DAC_Channel - the selected DAC channel. 89 | * DAC_Channel_1 - DAC Channel1 selected 90 | * DAC_Channel_2 - DAC Channel2 selected 91 | * NewState - new state of the DAC channel(ENABLE or DISABLE). 92 | * 93 | * @return none 94 | */ 95 | void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) 96 | { 97 | if(NewState != DISABLE) 98 | { 99 | DAC->CTLR |= (DAC_EN1 << DAC_Channel); 100 | } 101 | else 102 | { 103 | DAC->CTLR &= ~(DAC_EN1 << DAC_Channel); 104 | } 105 | } 106 | 107 | /********************************************************************* 108 | * @fn DAC_DMACmd 109 | * 110 | * @brief Enables or disables the specified DAC channel DMA request. 111 | * 112 | * @param DAC_Channel - the selected DAC channel. 113 | * DAC_Channel_1 - DAC Channel1 selected 114 | * DAC_Channel_2 - DAC Channel2 selected 115 | * NewState - new state of the DAC channel(ENABLE or DISABLE). 116 | * 117 | * @return none 118 | */ 119 | void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) 120 | { 121 | if(NewState != DISABLE) 122 | { 123 | DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel); 124 | } 125 | else 126 | { 127 | DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel); 128 | } 129 | } 130 | 131 | /********************************************************************* 132 | * @fn DAC_SoftwareTriggerCmd 133 | * 134 | * @brief Enables or disables the selected DAC channel software trigger. 135 | * 136 | * @param DAC_Channel - the selected DAC channel. 137 | * DAC_Channel_1 - DAC Channel1 selected 138 | * DAC_Channel_2 - DAC Channel2 selected 139 | * NewState - new state of the DAC channel(ENABLE or DISABLE). 140 | * 141 | * @return none 142 | */ 143 | void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) 144 | { 145 | if(NewState != DISABLE) 146 | { 147 | DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4); 148 | } 149 | else 150 | { 151 | DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4)); 152 | } 153 | } 154 | 155 | /********************************************************************* 156 | * @fn DAC_DualSoftwareTriggerCmd 157 | * 158 | * @brief Enables or disables the two DAC channel software trigger. 159 | * 160 | * @param NewState - new state of the DAC channel(ENABLE or DISABLE). 161 | * 162 | * @return none 163 | */ 164 | void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) 165 | { 166 | if(NewState != DISABLE) 167 | { 168 | DAC->SWTR |= DUAL_SWTR_SET; 169 | } 170 | else 171 | { 172 | DAC->SWTR &= DUAL_SWTR_RESET; 173 | } 174 | } 175 | 176 | /********************************************************************* 177 | * @fn DAC_WaveGenerationCmd 178 | * 179 | * @brief Enables or disables the selected DAC channel wave generation. 180 | * 181 | * @param DAC_Channel - the selected DAC channel. 182 | * DAC_Channel_1 - DAC Channel1 selected 183 | * DAC_Channel_2 - DAC Channel2 selected 184 | * DAC_Wave - Specifies the wave type to enable or disable. 185 | * DAC_Wave_Noise - noise wave generation 186 | * DAC_Wave_Triangle - triangle wave generation 187 | * NewState - new state of the DAC channel(ENABLE or DISABLE). 188 | * 189 | * @return none 190 | */ 191 | void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) 192 | { 193 | if(NewState != DISABLE) 194 | { 195 | DAC->CTLR |= DAC_Wave << DAC_Channel; 196 | } 197 | else 198 | { 199 | DAC->CTLR &= ~(DAC_Wave << DAC_Channel); 200 | } 201 | } 202 | 203 | /********************************************************************* 204 | * @fn DAC_SetChannel1Data 205 | * 206 | * @brief Set the specified data holding register value for DAC channel1. 207 | * 208 | * @param DAC_Align - Specifies the data alignment for DAC channel1. 209 | * DAC_Align_8b_R - 8bit right data alignment selected 210 | * DAC_Align_12b_L - 12bit left data alignment selected 211 | * DAC_Align_12b_R - 12bit right data alignment selected 212 | * Data - Data to be loaded in the selected data holding register. 213 | * 214 | * @return none 215 | */ 216 | void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) 217 | { 218 | __IO uint32_t tmp = 0; 219 | 220 | tmp = (uint32_t)DAC_BASE; 221 | tmp += DHR12R1_OFFSET + DAC_Align; 222 | 223 | *(__IO uint32_t *)tmp = Data; 224 | } 225 | 226 | /********************************************************************* 227 | * @fn DAC_SetChannel2Data 228 | * 229 | * @brief Set the specified data holding register value for DAC channel2. 230 | * 231 | * @param DAC_Align - Specifies the data alignment for DAC channel1. 232 | * DAC_Align_8b_R - 8bit right data alignment selected 233 | * DAC_Align_12b_L - 12bit left data alignment selected 234 | * DAC_Align_12b_R - 12bit right data alignment selected 235 | * Data - Data to be loaded in the selected data holding register. 236 | * 237 | * @return none 238 | */ 239 | void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) 240 | { 241 | __IO uint32_t tmp = 0; 242 | 243 | tmp = (uint32_t)DAC_BASE; 244 | tmp += DHR12R2_OFFSET + DAC_Align; 245 | 246 | *(__IO uint32_t *)tmp = Data; 247 | } 248 | 249 | /********************************************************************* 250 | * @fn DAC_SetDualChannelData 251 | * 252 | * @brief Set the specified data holding register value for two DAC. 253 | * 254 | * @param DAC_Align - Specifies the data alignment for DAC channel1. 255 | * DAC_Align_8b_R - 8bit right data alignment selected 256 | * DAC_Align_12b_L - 12bit left data alignment selected 257 | * DAC_Align_12b_R - 12bit right data alignment selected 258 | * Data - Data to be loaded in the selected data holding register. 259 | * Data1 - Data for DAC Channel1. 260 | * Data2 - Data for DAC Channel2 261 | * 262 | * @return none 263 | */ 264 | void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) 265 | { 266 | uint32_t data = 0, tmp = 0; 267 | 268 | if(DAC_Align == DAC_Align_8b_R) 269 | { 270 | data = ((uint32_t)Data2 << 8) | Data1; 271 | } 272 | else 273 | { 274 | data = ((uint32_t)Data2 << 16) | Data1; 275 | } 276 | 277 | tmp = (uint32_t)DAC_BASE; 278 | tmp += DHR12RD_OFFSET + DAC_Align; 279 | 280 | *(__IO uint32_t *)tmp = data; 281 | } 282 | 283 | /********************************************************************* 284 | * @fn DAC_GetDataOutputValue 285 | * 286 | * @brief Returns the last data output value of the selected DAC channel. 287 | * 288 | * @param DAC_Channel - the selected DAC channel. 289 | * DAC_Channel_1 - DAC Channel1 selected 290 | * DAC_Channel_2 - DAC Channel2 selected 291 | * 292 | * @return none 293 | */ 294 | uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) 295 | { 296 | __IO uint32_t tmp = 0; 297 | 298 | tmp = (uint32_t)DAC_BASE; 299 | tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); 300 | 301 | return (uint16_t)(*(__IO uint32_t *)tmp); 302 | } 303 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_dbgmcu.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the DBGMCU firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | ****************************************************************************************/ 10 | #include "ch32v30x_dbgmcu.h" 11 | 12 | #define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) 13 | 14 | /********************************************************************* 15 | * @fn DBGMCU_GetREVID 16 | * 17 | * @brief Returns the device revision identifier. 18 | * 19 | * @return Revision identifier. 20 | */ 21 | uint32_t DBGMCU_GetREVID(void) 22 | { 23 | return ((*(uint32_t *)0x1FFFF704) >> 16); 24 | } 25 | 26 | /********************************************************************* 27 | * @fn DBGMCU_GetDEVID 28 | * 29 | * @brief Returns the device identifier. 30 | * 31 | * @return Device identifier. 32 | */ 33 | uint32_t DBGMCU_GetDEVID(void) 34 | { 35 | return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); 36 | } 37 | 38 | /********************************************************************* 39 | * @fn __get_DEBUG_CR 40 | * 41 | * @brief Return the DEBUGE Control Register 42 | * 43 | * @return DEBUGE Control value 44 | */ 45 | uint32_t __get_DEBUG_CR(void) 46 | { 47 | uint32_t result; 48 | 49 | __asm volatile("csrr %0,""0x7C0" : "=r"(result)); 50 | return (result); 51 | } 52 | 53 | /********************************************************************* 54 | * @fn __set_DEBUG_CR 55 | * 56 | * @brief Set the DEBUGE Control Register 57 | * 58 | * @param value - set DEBUGE Control value 59 | * 60 | * @return none 61 | */ 62 | void __set_DEBUG_CR(uint32_t value) 63 | { 64 | __asm volatile("csrw 0x7C0, %0" : : "r"(value)); 65 | } 66 | 67 | 68 | /********************************************************************* 69 | * @fn DBGMCU_Config 70 | * 71 | * @brief Configures the specified peripheral and low power mode behavior 72 | * when the MCU under Debug mode. 73 | * 74 | * @param DBGMCU_Periph - specifies the peripheral and low power mode. 75 | * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted 76 | * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted 77 | * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted 78 | * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted 79 | * NewState - ENABLE or DISABLE. 80 | * 81 | * @return none 82 | */ 83 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 84 | { 85 | uint32_t val; 86 | 87 | if(NewState != DISABLE) 88 | { 89 | __set_DEBUG_CR(DBGMCU_Periph); 90 | } 91 | else 92 | { 93 | val = __get_DEBUG_CR(); 94 | val &= ~(uint32_t)DBGMCU_Periph; 95 | __set_DEBUG_CR(val); 96 | } 97 | 98 | } 99 | 100 | 101 | 102 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_dvp.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_dvp.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the DVP firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include "ch32v30x_dvp.h" 11 | 12 | /********************************************************************* 13 | * @fn DVP_INTCfg 14 | * 15 | * @brief DVP interrupt configuration 16 | * 17 | * @param s - interrupt enable 18 | * ENABLE 19 | * DISABLE 20 | * i - interrupt type 21 | * RB_DVP_IE_STP_FRM 22 | * RB_DVP_IE_FIFO_OV 23 | * RB_DVP_IE_FRM_DONE 24 | * RB_DVP_IE_ROW_DONE 25 | * RB_DVP_IE_STR_FRM 26 | * 27 | * @return none 28 | */ 29 | void DVP_INTCfg(uint8_t s, uint8_t i) 30 | { 31 | if(s) 32 | { 33 | DVP->IER |= i; 34 | } 35 | else 36 | { 37 | DVP->IER &= ~i; 38 | } 39 | } 40 | 41 | /********************************************************************* 42 | * @fn DVP_Mode 43 | * 44 | * @brief DVP mode 45 | * 46 | * @param s - data bit width 47 | * RB_DVP_D8_MOD 48 | * RB_DVP_D10_MOD 49 | * RB_DVP_D12_MOD 50 | * i - interrupt type 51 | * Video_Mode 52 | * JPEG_Mode 53 | * 54 | * @return none 55 | */ 56 | void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i) 57 | { 58 | DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD; 59 | 60 | if(s) 61 | { 62 | DVP->CR0 |= s; 63 | } 64 | else 65 | { 66 | DVP->CR0 &= ~(3 << 4); 67 | } 68 | 69 | if(i) 70 | { 71 | DVP->CR0 |= RB_DVP_JPEG; 72 | } 73 | else 74 | { 75 | DVP->CR0 &= ~RB_DVP_JPEG; 76 | } 77 | } 78 | 79 | /********************************************************************* 80 | * @fn DVP_Cfg 81 | * 82 | * @brief DVP configuration 83 | * 84 | * @param s - DMA enable control 85 | * DVP_DMA_Enable 86 | * DVP_DMA_Disable 87 | * i - DVP all clear 88 | * DVP_FLAG_FIFO_RESET_Enable 89 | * DVP_FLAG_FIFO_RESET_Disable 90 | * j - receive reset enable 91 | * DVP_RX_RESET_Enable 92 | * DVP_RX_RESET_Disable 93 | * 94 | * @return none 95 | */ 96 | void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) 97 | { 98 | switch(s) 99 | { 100 | case DVP_DMA_Enable: 101 | DVP->CR1 |= RB_DVP_DMA_EN; 102 | break; 103 | case DVP_DMA_Disable: 104 | DVP->CR1 &= ~RB_DVP_DMA_EN; 105 | break; 106 | default: 107 | break; 108 | } 109 | 110 | switch(i) 111 | { 112 | case DVP_RX_RESET_Enable: 113 | DVP->CR1 |= RB_DVP_ALL_CLR; 114 | break; 115 | case DVP_RX_RESET_Disable: 116 | DVP->CR1 &= ~RB_DVP_ALL_CLR; 117 | break; 118 | default: 119 | break; 120 | } 121 | 122 | switch(j) 123 | { 124 | case DVP_RX_RESET_Enable: 125 | DVP->CR1 |= RB_DVP_RCV_CLR; 126 | break; 127 | case DVP_RX_RESET_Disable: 128 | DVP->CR1 &= ~RB_DVP_RCV_CLR; 129 | break; 130 | default: 131 | break; 132 | } 133 | } 134 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_eth.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/Peripheral/src/ch32v30x_eth.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_exti.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_exti.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the EXTI firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | ***************************************************************************************/ 10 | #include "ch32v30x_exti.h" 11 | 12 | /* No interrupt selected */ 13 | #define EXTI_LINENONE ((uint32_t)0x00000) 14 | 15 | /********************************************************************* 16 | * @fn EXTI_DeInit 17 | * 18 | * @brief Deinitializes the EXTI peripheral registers to their default 19 | * reset values. 20 | * 21 | * @return none. 22 | */ 23 | void EXTI_DeInit(void) 24 | { 25 | EXTI->INTENR = 0x00000000; 26 | EXTI->EVENR = 0x00000000; 27 | EXTI->RTENR = 0x00000000; 28 | EXTI->FTENR = 0x00000000; 29 | EXTI->INTFR = 0x000FFFFF; 30 | } 31 | 32 | /********************************************************************* 33 | * @fn EXTI_Init 34 | * 35 | * @brief Initializes the EXTI peripheral according to the specified 36 | * parameters in the EXTI_InitStruct. 37 | * 38 | * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure 39 | * 40 | * @return none. 41 | */ 42 | void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) 43 | { 44 | uint32_t tmp = 0; 45 | 46 | tmp = (uint32_t)EXTI_BASE; 47 | if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) 48 | { 49 | EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; 50 | EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; 51 | tmp += EXTI_InitStruct->EXTI_Mode; 52 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 53 | EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; 54 | EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; 55 | if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 56 | { 57 | EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; 58 | EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; 59 | } 60 | else 61 | { 62 | tmp = (uint32_t)EXTI_BASE; 63 | tmp += EXTI_InitStruct->EXTI_Trigger; 64 | *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; 65 | } 66 | } 67 | else 68 | { 69 | tmp += EXTI_InitStruct->EXTI_Mode; 70 | *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; 71 | } 72 | } 73 | 74 | /********************************************************************* 75 | * @fn EXTI_StructInit 76 | * 77 | * @brief Fills each EXTI_InitStruct member with its reset value. 78 | * 79 | * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure 80 | * 81 | * @return none. 82 | */ 83 | void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) 84 | { 85 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 86 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 87 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 88 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 89 | } 90 | 91 | /********************************************************************* 92 | * @fn EXTI_GenerateSWInterrupt 93 | * 94 | * @brief Generates a Software interrupt. 95 | * 96 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 97 | * 98 | * @return none. 99 | */ 100 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 101 | { 102 | EXTI->SWIEVR |= EXTI_Line; 103 | } 104 | 105 | /********************************************************************* 106 | * @fn EXTI_GetFlagStatus 107 | * 108 | * @brief Checks whether the specified EXTI line flag is set or not. 109 | * 110 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 111 | * 112 | * @return The new state of EXTI_Line (SET or RESET). 113 | */ 114 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 115 | { 116 | FlagStatus bitstatus = RESET; 117 | if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) 118 | { 119 | bitstatus = SET; 120 | } 121 | else 122 | { 123 | bitstatus = RESET; 124 | } 125 | return bitstatus; 126 | } 127 | 128 | /********************************************************************* 129 | * @fn EXTI_ClearFlag 130 | * 131 | * @brief Clears the EXTI's line pending flags. 132 | * 133 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 134 | * 135 | * @return None 136 | */ 137 | void EXTI_ClearFlag(uint32_t EXTI_Line) 138 | { 139 | EXTI->INTFR = EXTI_Line; 140 | } 141 | 142 | /********************************************************************* 143 | * @fn EXTI_GetITStatus 144 | * 145 | * @brief Checks whether the specified EXTI line is asserted or not. 146 | * 147 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 148 | * 149 | * @return The new state of EXTI_Line (SET or RESET). 150 | */ 151 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 152 | { 153 | ITStatus bitstatus = RESET; 154 | uint32_t enablestatus = 0; 155 | 156 | enablestatus = EXTI->INTENR & EXTI_Line; 157 | if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) 158 | { 159 | bitstatus = SET; 160 | } 161 | else 162 | { 163 | bitstatus = RESET; 164 | } 165 | return bitstatus; 166 | } 167 | 168 | /********************************************************************* 169 | * @fn EXTI_ClearITPendingBit 170 | * 171 | * @brief Clears the EXTI's line pending bits. 172 | * 173 | * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. 174 | * 175 | * @return none 176 | */ 177 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 178 | { 179 | EXTI->INTFR = EXTI_Line; 180 | } 181 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_fsmc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/Peripheral/src/ch32v30x_fsmc.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_iwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_iwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the IWDG firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include "ch32v30x_iwdg.h" 11 | 12 | /* CTLR register bit mask */ 13 | #define CTLR_KEY_Reload ((uint16_t)0xAAAA) 14 | #define CTLR_KEY_Enable ((uint16_t)0xCCCC) 15 | 16 | /********************************************************************* 17 | * @fn IWDG_WriteAccessCmd 18 | * 19 | * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. 20 | * 21 | * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and 22 | * IWDG_RLDR registers. 23 | * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and 24 | * IWDG_RLDR registers. 25 | * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR 26 | * and IWDG_RLDR registers. 27 | * 28 | * @return none 29 | */ 30 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 31 | { 32 | IWDG->CTLR = IWDG_WriteAccess; 33 | } 34 | 35 | /********************************************************************* 36 | * @fn IWDG_SetPrescaler 37 | * 38 | * @brief Sets IWDG Prescaler value. 39 | * 40 | * @param IWDG_Prescaler - specifies the IWDG Prescaler value. 41 | * IWDG_Prescaler_4 - IWDG prescaler set to 4. 42 | * IWDG_Prescaler_8 - IWDG prescaler set to 8. 43 | * IWDG_Prescaler_16 - IWDG prescaler set to 16. 44 | * IWDG_Prescaler_32 - IWDG prescaler set to 32. 45 | * IWDG_Prescaler_64 - IWDG prescaler set to 64. 46 | * IWDG_Prescaler_128 - IWDG prescaler set to 128. 47 | * IWDG_Prescaler_256 - IWDG prescaler set to 256. 48 | * 49 | * @return none 50 | */ 51 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 52 | { 53 | IWDG->PSCR = IWDG_Prescaler; 54 | } 55 | 56 | /********************************************************************* 57 | * @fn IWDG_SetReload 58 | * 59 | * @brief Sets IWDG Reload value. 60 | * 61 | * @param Reload - specifies the IWDG Reload value. 62 | * This parameter must be a number between 0 and 0x0FFF. 63 | * 64 | * @return none 65 | */ 66 | void IWDG_SetReload(uint16_t Reload) 67 | { 68 | IWDG->RLDR = Reload; 69 | } 70 | 71 | /********************************************************************* 72 | * @fn IWDG_ReloadCounter 73 | * 74 | * @brief Reloads IWDG counter with value defined in the reload register. 75 | * 76 | * @return none 77 | */ 78 | void IWDG_ReloadCounter(void) 79 | { 80 | IWDG->CTLR = CTLR_KEY_Reload; 81 | } 82 | 83 | /********************************************************************* 84 | * @fn IWDG_Enable 85 | * 86 | * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). 87 | * 88 | * @return none 89 | */ 90 | void IWDG_Enable(void) 91 | { 92 | IWDG->CTLR = CTLR_KEY_Enable; 93 | } 94 | 95 | /********************************************************************* 96 | * @fn IWDG_GetFlagStatus 97 | * 98 | * @brief Checks whether the specified IWDG flag is set or not. 99 | * 100 | * @param IWDG_FLAG - specifies the flag to check. 101 | * IWDG_FLAG_PVU - Prescaler Value Update on going. 102 | * IWDG_FLAG_RVU - Reload Value Update on going. 103 | * 104 | * @return none 105 | */ 106 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 107 | { 108 | FlagStatus bitstatus = RESET; 109 | 110 | if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) 111 | { 112 | bitstatus = SET; 113 | } 114 | else 115 | { 116 | bitstatus = RESET; 117 | } 118 | 119 | return bitstatus; 120 | } 121 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_misc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_misc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the miscellaneous firmware functions . 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *********************************************************************************/ 10 | #include "ch32v30x_misc.h" 11 | 12 | __IO uint32_t NVIC_Priority_Group = 0; 13 | 14 | /********************************************************************* 15 | * @fn NVIC_PriorityGroupConfig 16 | * 17 | * @brief Configures the priority grouping - pre-emption priority and subpriority. 18 | * 19 | * @param NVIC_PriorityGroup - specifies the priority grouping bits length. 20 | * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority 21 | * 4 bits for subpriority 22 | * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority 23 | * 3 bits for subpriority 24 | * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority 25 | * 2 bits for subpriority 26 | * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority 27 | * 1 bits for subpriority 28 | * NVIC_PriorityGroup_4 - 4 bits for pre-emption priority 29 | * 0 bits for subpriority 30 | * 31 | * @return none 32 | */ 33 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 34 | { 35 | NVIC_Priority_Group = NVIC_PriorityGroup; 36 | } 37 | 38 | /********************************************************************* 39 | * @fn NVIC_Init 40 | * 41 | * @brief Initializes the NVIC peripheral according to the specified parameters in 42 | * the NVIC_InitStruct. 43 | * 44 | * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the 45 | * configuration information for the specified NVIC peripheral. 46 | * 47 | * @return none 48 | */ 49 | void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) 50 | { 51 | uint8_t tmppre = 0; 52 | 53 | if(NVIC_Priority_Group == NVIC_PriorityGroup_0) 54 | { 55 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); 56 | } 57 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_1) 58 | { 59 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) 60 | { 61 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 62 | } 63 | else 64 | { 65 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); 66 | } 67 | } 68 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_2) 69 | { 70 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 1) 71 | { 72 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 73 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 74 | } 75 | else 76 | { 77 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (4 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 2)); 78 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 79 | } 80 | } 81 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_3) 82 | { 83 | if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority <= 3) 84 | { 85 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority); 86 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (tmppre << 4)); 87 | } 88 | else 89 | { 90 | tmppre = NVIC_InitStruct->NVIC_IRQChannelSubPriority + (2 * (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority - 4)); 91 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (tmppre << 4)); 92 | } 93 | } 94 | else if(NVIC_Priority_Group == NVIC_PriorityGroup_4) 95 | { 96 | NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 4); 97 | } 98 | 99 | if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 100 | { 101 | NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 102 | } 103 | else 104 | { 105 | NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); 106 | } 107 | } 108 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_opa.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_opa.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the OPA firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | ***************************************************************************************/ 10 | #include "ch32v30x_opa.h" 11 | 12 | #define OPA_MASK ((uint32_t)0x000F) 13 | #define OPA_Total_NUM 4 14 | 15 | /********************************************************************* 16 | * @fn OPA_DeInit 17 | * 18 | * @brief Deinitializes the OPA peripheral registers to their default 19 | * reset values. 20 | * 21 | * @return none 22 | */ 23 | void OPA_DeInit(void) 24 | { 25 | OPA->CR = 0; 26 | } 27 | 28 | /********************************************************************* 29 | * @fn OPA_Init 30 | * 31 | * @brief Initializes the OPA peripheral according to the specified 32 | * parameters in the OPA_InitStruct. 33 | * 34 | * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure 35 | * 36 | * @return none 37 | */ 38 | void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) 39 | { 40 | uint32_t tmp = 0; 41 | tmp = OPA->CR; 42 | tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); 43 | tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); 44 | OPA->CR = tmp; 45 | } 46 | 47 | /********************************************************************* 48 | * @fn OPA_StructInit 49 | * 50 | * @brief Fills each OPA_StructInit member with its reset value. 51 | * 52 | * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure 53 | * 54 | * @return none 55 | */ 56 | void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) 57 | { 58 | OPA_InitStruct->Mode = OUT_IO_OUT1; 59 | OPA_InitStruct->PSEL = CHP0; 60 | OPA_InitStruct->NSEL = CHN0; 61 | OPA_InitStruct->OPA_NUM = OPA1; 62 | } 63 | 64 | /********************************************************************* 65 | * @fn OPA_Cmd 66 | * 67 | * @brief Enables or disables the specified OPA peripheral. 68 | * 69 | * @param OPA_NUM - Select OPA 70 | * NewState - ENABLE or DISABLE. 71 | * 72 | * @return none 73 | */ 74 | void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) 75 | { 76 | if(NewState == ENABLE) 77 | { 78 | OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); 79 | } 80 | else 81 | { 82 | OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); 83 | } 84 | } 85 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_pwr.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_pwr.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the PWR firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | ********************************************************************************/ 10 | #include "ch32v30x_pwr.h" 11 | #include "ch32v30x_rcc.h" 12 | 13 | /* PWR registers bit mask */ 14 | /* CTLR register bit mask */ 15 | #define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) 16 | #define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) 17 | 18 | /********************************************************************* 19 | * @fn PWR_DeInit 20 | * 21 | * @brief Deinitializes the PWR peripheral registers to their default 22 | * reset values. 23 | * 24 | * @return none 25 | */ 26 | void PWR_DeInit(void) 27 | { 28 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 29 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 30 | } 31 | 32 | /********************************************************************* 33 | * @fn PWR_BackupAccessCmd 34 | * 35 | * @brief Enables or disables access to the RTC and backup registers. 36 | * 37 | * @param NewState - new state of the access to the RTC and backup registers, 38 | * This parameter can be: ENABLE or DISABLE. 39 | * 40 | * @return none 41 | */ 42 | void PWR_BackupAccessCmd(FunctionalState NewState) 43 | { 44 | if(NewState) 45 | { 46 | PWR->CTLR |= (1 << 8); 47 | } 48 | else 49 | { 50 | PWR->CTLR &= ~(1 << 8); 51 | } 52 | } 53 | 54 | /********************************************************************* 55 | * @fn PWR_PVDCmd 56 | * 57 | * @brief Enables or disables the Power Voltage Detector(PVD). 58 | * 59 | * @param NewState - new state of the PVD(ENABLE or DISABLE). 60 | * 61 | * @return none 62 | */ 63 | void PWR_PVDCmd(FunctionalState NewState) 64 | { 65 | if(NewState) 66 | { 67 | PWR->CTLR |= (1 << 4); 68 | } 69 | else 70 | { 71 | PWR->CTLR &= ~(1 << 4); 72 | } 73 | } 74 | 75 | /********************************************************************* 76 | * @fn PWR_PVDLevelConfig 77 | * 78 | * @brief Configures the voltage threshold detected by the Power Voltage 79 | * Detector(PVD). 80 | * 81 | * @param PWR_PVDLevel - specifies the PVD detection level 82 | * PWR_PVDLevel_2V2 - PVD detection level set to 2.2V 83 | * PWR_PVDLevel_2V3 - PVD detection level set to 2.3V 84 | * PWR_PVDLevel_2V4 - PVD detection level set to 2.4V 85 | * PWR_PVDLevel_2V5 - PVD detection level set to 2.5V 86 | * PWR_PVDLevel_2V6 - PVD detection level set to 2.6V 87 | * PWR_PVDLevel_2V7 - PVD detection level set to 2.7V 88 | * PWR_PVDLevel_2V8 - PVD detection level set to 2.8V 89 | * PWR_PVDLevel_2V9 - PVD detection level set to 2.9V 90 | * 91 | * @return none 92 | */ 93 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 94 | { 95 | uint32_t tmpreg = 0; 96 | tmpreg = PWR->CTLR; 97 | tmpreg &= CTLR_PLS_MASK; 98 | tmpreg |= PWR_PVDLevel; 99 | PWR->CTLR = tmpreg; 100 | } 101 | 102 | /********************************************************************* 103 | * @fn PWR_WakeUpPinCmd 104 | * 105 | * @brief Enables or disables the WakeUp Pin functionality. 106 | * 107 | * @param NewState - new state of the WakeUp Pin functionality 108 | * (ENABLE or DISABLE). 109 | * 110 | * @return none 111 | */ 112 | void PWR_WakeUpPinCmd(FunctionalState NewState) 113 | { 114 | if(NewState) 115 | { 116 | PWR->CSR |= (1 << 8); 117 | } 118 | else 119 | { 120 | PWR->CSR &= ~(1 << 8); 121 | } 122 | } 123 | 124 | /********************************************************************* 125 | * @fn PWR_EnterSTOPMode 126 | * 127 | * @brief Enters STOP mode. 128 | * 129 | * @param PWR_Regulator - specifies the regulator state in STOP mode. 130 | * PWR_Regulator_ON - STOP mode with regulator ON 131 | * PWR_Regulator_LowPower - STOP mode with regulator in low power mode 132 | * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. 133 | * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction 134 | * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction 135 | * 136 | * @return none 137 | */ 138 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 139 | { 140 | uint32_t tmpreg = 0; 141 | tmpreg = PWR->CTLR; 142 | tmpreg &= CTLR_DS_MASK; 143 | tmpreg |= PWR_Regulator; 144 | PWR->CTLR = tmpreg; 145 | 146 | NVIC->SCTLR |= (1 << 2); 147 | 148 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 149 | { 150 | __WFI(); 151 | } 152 | else 153 | { 154 | __WFE(); 155 | } 156 | 157 | NVIC->SCTLR &= ~(1 << 2); 158 | } 159 | 160 | /********************************************************************* 161 | * @fn PWR_EnterSTANDBYMode 162 | * 163 | * @brief Enters STANDBY mode. 164 | * 165 | * @return none 166 | */ 167 | void PWR_EnterSTANDBYMode(void) 168 | { 169 | PWR->CTLR |= PWR_CTLR_CWUF; 170 | PWR->CTLR |= PWR_CTLR_PDDS; 171 | NVIC->SCTLR |= (1 << 2); 172 | 173 | __WFI(); 174 | } 175 | 176 | /********************************************************************* 177 | * @fn PWR_GetFlagStatus 178 | * 179 | * @brief Checks whether the specified PWR flag is set or not. 180 | * 181 | * @param PWR_FLAG - specifies the flag to check. 182 | * PWR_FLAG_WU - Wake Up flag 183 | * PWR_FLAG_SB - StandBy flag 184 | * PWR_FLAG_PVDO - PVD Output 185 | * 186 | * @return none 187 | */ 188 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 189 | { 190 | FlagStatus bitstatus = RESET; 191 | 192 | if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 193 | { 194 | bitstatus = SET; 195 | } 196 | else 197 | { 198 | bitstatus = RESET; 199 | } 200 | return bitstatus; 201 | } 202 | 203 | /********************************************************************* 204 | * @fn PWR_ClearFlag 205 | * 206 | * @brief Clears the PWR's pending flags. 207 | * 208 | * @param PWR_FLAG - specifies the flag to clear. 209 | * PWR_FLAG_WU - Wake Up flag 210 | * PWR_FLAG_SB - StandBy flag 211 | * 212 | * @return none 213 | */ 214 | void PWR_ClearFlag(uint32_t PWR_FLAG) 215 | { 216 | PWR->CTLR |= PWR_FLAG << 2; 217 | } 218 | 219 | /********************************************************************* 220 | * @fn PWR_EnterSTANDBYMode_RAM 221 | * 222 | * @brief Enters STANDBY mode with RAM data retention function on. 223 | * 224 | * @return none 225 | */ 226 | void PWR_EnterSTANDBYMode_RAM(void) 227 | { 228 | uint32_t tmpreg = 0; 229 | tmpreg = PWR->CTLR; 230 | 231 | tmpreg |= PWR_CTLR_CWUF; 232 | tmpreg |= PWR_CTLR_PDDS; 233 | 234 | //2K+30K in standby w power. 235 | tmpreg |= (0x1 << 16) | (0x1 << 17); 236 | 237 | PWR->CTLR = tmpreg; 238 | 239 | NVIC->SCTLR |= (1 << 2); 240 | 241 | __WFI(); 242 | } 243 | 244 | /********************************************************************* 245 | * @fn PWR_EnterSTANDBYMode_RAM_LV 246 | * 247 | * @brief Enters STANDBY mode with RAM data retention function and LV mode on. 248 | * 249 | * @return none 250 | */ 251 | void PWR_EnterSTANDBYMode_RAM_LV(void) 252 | { 253 | uint32_t tmpreg = 0; 254 | tmpreg = PWR->CTLR; 255 | 256 | tmpreg |= PWR_CTLR_CWUF; 257 | tmpreg |= PWR_CTLR_PDDS; 258 | 259 | //2K+30K in standby power. 260 | tmpreg |= (0x1 << 16) | (0x1 << 17); 261 | //2K+30K in standby LV . 262 | tmpreg |= (0x1 << 20); 263 | 264 | PWR->CTLR = tmpreg; 265 | 266 | NVIC->SCTLR |= (1 << 2); 267 | 268 | __WFI(); 269 | } 270 | 271 | /********************************************************************* 272 | * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN 273 | * 274 | * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). 275 | * 276 | * @return none 277 | */ 278 | void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) 279 | { 280 | uint32_t tmpreg = 0; 281 | tmpreg = PWR->CTLR; 282 | 283 | tmpreg |= PWR_CTLR_CWUF; 284 | tmpreg |= PWR_CTLR_PDDS; 285 | 286 | //2K+30K in standby power (VBAT Enable). 287 | tmpreg |= (0x1 << 18) | (0x1 << 19); 288 | 289 | PWR->CTLR = tmpreg; 290 | 291 | NVIC->SCTLR |= (1 << 2); 292 | 293 | __WFI(); 294 | } 295 | 296 | /********************************************************************* 297 | * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN 298 | * 299 | * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). 300 | * 301 | * @return none 302 | */ 303 | void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) 304 | { 305 | uint32_t tmpreg = 0; 306 | tmpreg = PWR->CTLR; 307 | 308 | tmpreg |= PWR_CTLR_CWUF; 309 | tmpreg |= PWR_CTLR_PDDS; 310 | 311 | //2K+30K in standby power (VBAT Enable). 312 | tmpreg |= (0x1 << 18) | (0x1 << 19); 313 | //2K+30K in standby LV . 314 | tmpreg |= (0x1 << 20); 315 | 316 | PWR->CTLR = tmpreg; 317 | 318 | NVIC->SCTLR |= (1 << 2); 319 | 320 | __WFI(); 321 | } 322 | 323 | 324 | /********************************************************************* 325 | * @fn PWR_EnterSTOPMode_RAM_LV 326 | * 327 | * @brief Enters STOP mode with RAM data retention function and LV mode on. 328 | * 329 | * @param PWR_Regulator - specifies the regulator state in STOP mode. 330 | * PWR_Regulator_ON - STOP mode with regulator ON 331 | * PWR_Regulator_LowPower - STOP mode with regulator in low power mode 332 | * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. 333 | * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction 334 | * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction 335 | * 336 | * @return none 337 | */ 338 | void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 339 | { 340 | uint32_t tmpreg = 0; 341 | tmpreg = PWR->CTLR; 342 | tmpreg &= CTLR_DS_MASK; 343 | tmpreg |= PWR_Regulator; 344 | 345 | //2K+30K in standby power. 346 | tmpreg |= (0x1 << 16) | (0x1 << 17); 347 | //2K+30K in standby LV . 348 | tmpreg |= (0x1 << 20); 349 | PWR->CTLR = tmpreg; 350 | 351 | NVIC->SCTLR |= (1 << 2); 352 | 353 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 354 | { 355 | __WFI(); 356 | } 357 | else 358 | { 359 | __WFE(); 360 | } 361 | 362 | NVIC->SCTLR &= ~(1 << 2); 363 | } 364 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_rng.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/Peripheral/src/ch32v30x_rng.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_rtc.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_rtc.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the RTC firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | ********************************************************************************/ 10 | #include "ch32v30x_rtc.h" 11 | 12 | /* RTC_Private_Defines */ 13 | #define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ 14 | #define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ 15 | 16 | /********************************************************************* 17 | * @fn RTC_ITConfig 18 | * 19 | * @brief Enables or disables the specified RTC interrupts. 20 | * 21 | * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. 22 | * RTC_IT_OW - Overflow interrupt 23 | * RTC_IT_ALR - Alarm interrupt 24 | * RTC_IT_SEC - Second interrupt 25 | * 26 | * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). 27 | */ 28 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) 29 | { 30 | if(NewState != DISABLE) 31 | { 32 | RTC->CTLRH |= RTC_IT; 33 | } 34 | else 35 | { 36 | RTC->CTLRH &= (uint16_t)~RTC_IT; 37 | } 38 | } 39 | 40 | /********************************************************************* 41 | * @fn RTC_EnterConfigMode 42 | * 43 | * @brief Enters the RTC configuration mode. 44 | * 45 | * @return none 46 | */ 47 | void RTC_EnterConfigMode(void) 48 | { 49 | RTC->CTLRL |= RTC_CTLRL_CNF; 50 | } 51 | 52 | /********************************************************************* 53 | * @fn RTC_ExitConfigMode 54 | * 55 | * @brief Exits from the RTC configuration mode. 56 | * 57 | * @return none 58 | */ 59 | void RTC_ExitConfigMode(void) 60 | { 61 | RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); 62 | } 63 | 64 | /********************************************************************* 65 | * @fn RTC_GetCounter 66 | * 67 | * @brief Gets the RTC counter value 68 | * 69 | * @return RTC counter value 70 | */ 71 | uint32_t RTC_GetCounter(void) 72 | { 73 | uint16_t high1 = 0, high2 = 0, low = 0; 74 | 75 | high1 = RTC->CNTH; 76 | low = RTC->CNTL; 77 | high2 = RTC->CNTH; 78 | 79 | if(high1 != high2) 80 | { 81 | return (((uint32_t)high2 << 16) | RTC->CNTL); 82 | } 83 | else 84 | { 85 | return (((uint32_t)high1 << 16) | low); 86 | } 87 | } 88 | 89 | /********************************************************************* 90 | * @fn RTC_SetCounter 91 | * 92 | * @brief Sets the RTC counter value. 93 | * 94 | * @param CounterValue - RTC counter new value. 95 | * 96 | * @return RTC counter value 97 | */ 98 | void RTC_SetCounter(uint32_t CounterValue) 99 | { 100 | RTC_EnterConfigMode(); 101 | RTC->CNTH = CounterValue >> 16; 102 | RTC->CNTL = (CounterValue & RTC_LSB_MASK); 103 | RTC_ExitConfigMode(); 104 | } 105 | 106 | /********************************************************************* 107 | * @fn RTC_SetPrescaler 108 | * 109 | * @brief Sets the RTC prescaler value 110 | * 111 | * @param PrescalerValue - RTC prescaler new value 112 | * 113 | * @return none 114 | */ 115 | void RTC_SetPrescaler(uint32_t PrescalerValue) 116 | { 117 | RTC_EnterConfigMode(); 118 | RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; 119 | RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); 120 | RTC_ExitConfigMode(); 121 | } 122 | 123 | /********************************************************************* 124 | * @fn RTC_SetAlarm 125 | * 126 | * @brief Sets the RTC alarm value 127 | * 128 | * @param AlarmValue - RTC alarm new value 129 | * 130 | * @return none 131 | */ 132 | void RTC_SetAlarm(uint32_t AlarmValue) 133 | { 134 | RTC_EnterConfigMode(); 135 | RTC->ALRMH = AlarmValue >> 16; 136 | RTC->ALRML = (AlarmValue & RTC_LSB_MASK); 137 | RTC_ExitConfigMode(); 138 | } 139 | 140 | /********************************************************************* 141 | * @fn RTC_GetDivider 142 | * 143 | * @brief Gets the RTC divider value 144 | * 145 | * @return RTC Divider value 146 | */ 147 | uint32_t RTC_GetDivider(void) 148 | { 149 | uint32_t tmp = 0x00; 150 | tmp = ((uint32_t)RTC->DIVH & (uint32_t)0x000F) << 16; 151 | tmp |= RTC->DIVL; 152 | return tmp; 153 | } 154 | 155 | /********************************************************************* 156 | * @fn RTC_WaitForLastTask 157 | * 158 | * @brief Waits until last write operation on RTC registers has finished 159 | * 160 | * @return none 161 | */ 162 | void RTC_WaitForLastTask(void) 163 | { 164 | while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) 165 | { 166 | } 167 | } 168 | 169 | /********************************************************************* 170 | * @fn RTC_WaitForSynchro 171 | * 172 | * @brief Waits until the RTC registers are synchronized with RTC APB clock 173 | * 174 | * @return none 175 | */ 176 | void RTC_WaitForSynchro(void) 177 | { 178 | RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; 179 | while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) 180 | { 181 | } 182 | } 183 | 184 | /********************************************************************* 185 | * @fn RTC_GetFlagStatus 186 | * 187 | * @brief Checks whether the specified RTC flag is set or not 188 | * 189 | * @param RTC_FLAG- specifies the flag to check 190 | * RTC_FLAG_RTOFF - RTC Operation OFF flag 191 | * RTC_FLAG_RSF - Registers Synchronized flag 192 | * RTC_FLAG_OW - Overflow flag 193 | * RTC_FLAG_ALR - Alarm flag 194 | * RTC_FLAG_SEC - Second flag 195 | * 196 | * @return none 197 | */ 198 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) 199 | { 200 | FlagStatus bitstatus = RESET; 201 | if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) 202 | { 203 | bitstatus = SET; 204 | } 205 | else 206 | { 207 | bitstatus = RESET; 208 | } 209 | return bitstatus; 210 | } 211 | 212 | /********************************************************************* 213 | * @fn RTC_ClearFlag 214 | * 215 | * @brief Clears the RTC's pending flags 216 | * 217 | * @param RTC_FLAG - specifies the flag to clear 218 | * RTC_FLAG_RSF - Registers Synchronized flag 219 | * RTC_FLAG_OW - Overflow flag 220 | * RTC_FLAG_ALR - Alarm flag 221 | * RTC_FLAG_SEC - Second flag 222 | * 223 | * @return none 224 | */ 225 | void RTC_ClearFlag(uint16_t RTC_FLAG) 226 | { 227 | RTC->CTLRL &= (uint16_t)~RTC_FLAG; 228 | } 229 | 230 | /********************************************************************* 231 | * @fn RTC_GetITStatus 232 | * 233 | * @brief Checks whether the specified RTC interrupt has occurred or not 234 | * 235 | * @param RTC_IT - specifies the RTC interrupts sources to check 236 | * RTC_FLAG_OW - Overflow interrupt 237 | * RTC_FLAG_ALR - Alarm interrupt 238 | * RTC_FLAG_SEC - Second interrupt 239 | * 240 | * @return The new state of the RTC_IT (SET or RESET) 241 | */ 242 | ITStatus RTC_GetITStatus(uint16_t RTC_IT) 243 | { 244 | ITStatus bitstatus = RESET; 245 | 246 | bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); 247 | if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) 248 | { 249 | bitstatus = SET; 250 | } 251 | else 252 | { 253 | bitstatus = RESET; 254 | } 255 | return bitstatus; 256 | } 257 | 258 | /********************************************************************* 259 | * @fn RTC_ClearITPendingBit 260 | * 261 | * @brief Clears the RTC's interrupt pending bits 262 | * 263 | * @param RTC_IT - specifies the interrupt pending bit to clear 264 | * RTC_FLAG_OW - Overflow interrupt 265 | * RTC_FLAG_ALR - Alarm interrupt 266 | * RTC_FLAG_SEC - Second interrupt 267 | * 268 | * @return none 269 | */ 270 | void RTC_ClearITPendingBit(uint16_t RTC_IT) 271 | { 272 | RTC->CTLRL &= (uint16_t)~RTC_IT; 273 | } 274 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_sdio.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/Peripheral/src/ch32v30x_sdio.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/Peripheral/src/ch32v30x_wwdg.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_wwdg.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file provides all the WWDG firmware functions. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | **********************************************************************************/ 10 | #include "ch32v30x_wwdg.h" 11 | #include "ch32v30x_rcc.h" 12 | 13 | /* CTLR register bit mask */ 14 | #define CTLR_WDGA_Set ((uint32_t)0x00000080) 15 | 16 | /* CFGR register bit mask */ 17 | #define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 18 | #define CFGR_W_Mask ((uint32_t)0xFFFFFF80) 19 | #define BIT_Mask ((uint8_t)0x7F) 20 | 21 | /********************************************************************* 22 | * @fn WWDG_DeInit 23 | * 24 | * @brief Deinitializes the WWDG peripheral registers to their default reset values 25 | * 26 | * @return none 27 | */ 28 | void WWDG_DeInit(void) 29 | { 30 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 31 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 32 | } 33 | 34 | /********************************************************************* 35 | * @fn WWDG_SetPrescaler 36 | * 37 | * @brief Sets the WWDG Prescaler 38 | * 39 | * @param WWDG_Prescaler - specifies the WWDG Prescaler 40 | * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 41 | * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 42 | * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 43 | * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 44 | * 45 | * @return none 46 | */ 47 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 48 | { 49 | uint32_t tmpreg = 0; 50 | tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; 51 | tmpreg |= WWDG_Prescaler; 52 | WWDG->CFGR = tmpreg; 53 | } 54 | 55 | /********************************************************************* 56 | * @fn WWDG_SetWindowValue 57 | * 58 | * @brief Sets the WWDG window value 59 | * 60 | * @param WindowValue - specifies the window value to be compared to the 61 | * downcounter,which must be lower than 0x80 62 | * 63 | * @return none 64 | */ 65 | void WWDG_SetWindowValue(uint8_t WindowValue) 66 | { 67 | __IO uint32_t tmpreg = 0; 68 | 69 | tmpreg = WWDG->CFGR & CFGR_W_Mask; 70 | 71 | tmpreg |= WindowValue & (uint32_t)BIT_Mask; 72 | 73 | WWDG->CFGR = tmpreg; 74 | } 75 | 76 | /********************************************************************* 77 | * @fn WWDG_EnableIT 78 | * 79 | * @brief Enables the WWDG Early Wakeup interrupt(EWI) 80 | * 81 | * @return none 82 | */ 83 | void WWDG_EnableIT(void) 84 | { 85 | WWDG->CFGR |= (1 << 9); 86 | } 87 | 88 | /********************************************************************* 89 | * @fn WWDG_SetCounter 90 | * 91 | * @brief Sets the WWDG counter value 92 | * 93 | * @param Counter - specifies the watchdog counter value,which must be a 94 | * number between 0x40 and 0x7F 95 | * 96 | * @return none 97 | */ 98 | void WWDG_SetCounter(uint8_t Counter) 99 | { 100 | WWDG->CTLR = Counter & BIT_Mask; 101 | } 102 | 103 | /********************************************************************* 104 | * @fn WWDG_Enable 105 | * 106 | * @brief Enables WWDG and load the counter value 107 | * 108 | * @param Counter - specifies the watchdog counter value,which must be a 109 | * number between 0x40 and 0x7F 110 | * @return none 111 | */ 112 | void WWDG_Enable(uint8_t Counter) 113 | { 114 | WWDG->CTLR = CTLR_WDGA_Set | Counter; 115 | } 116 | 117 | /********************************************************************* 118 | * @fn WWDG_GetFlagStatus 119 | * 120 | * @brief Checks whether the Early Wakeup interrupt flag is set or not 121 | * 122 | * @return The new state of the Early Wakeup interrupt flag (SET or RESET) 123 | */ 124 | FlagStatus WWDG_GetFlagStatus(void) 125 | { 126 | return (FlagStatus)(WWDG->STATR); 127 | } 128 | 129 | /********************************************************************* 130 | * @fn WWDG_ClearFlag 131 | * 132 | * @brief Clears Early Wakeup interrupt flag 133 | * 134 | * @return none 135 | */ 136 | void WWDG_ClearFlag(void) 137 | { 138 | WWDG->STATR = (uint32_t)RESET; 139 | } 140 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/adc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/adc.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/adc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/adc.h -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/ch32v30x_conf.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_conf.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : Library configuration file. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #ifndef __CH32V30x_CONF_H 11 | #define __CH32V30x_CONF_H 12 | 13 | #include "ch32v30x_adc.h" 14 | #include "ch32v30x_bkp.h" 15 | #include "ch32v30x_can.h" 16 | #include "ch32v30x_crc.h" 17 | #include "ch32v30x_dac.h" 18 | #include "ch32v30x_dbgmcu.h" 19 | #include "ch32v30x_dma.h" 20 | #include "ch32v30x_exti.h" 21 | #include "ch32v30x_flash.h" 22 | #include "ch32v30x_fsmc.h" 23 | #include "ch32v30x_gpio.h" 24 | #include "ch32v30x_i2c.h" 25 | #include "ch32v30x_iwdg.h" 26 | #include "ch32v30x_pwr.h" 27 | #include "ch32v30x_rcc.h" 28 | #include "ch32v30x_rtc.h" 29 | #include "ch32v30x_sdio.h" 30 | #include "ch32v30x_spi.h" 31 | #include "ch32v30x_tim.h" 32 | #include "ch32v30x_usart.h" 33 | #include "ch32v30x_wwdg.h" 34 | #include "ch32v30x_it.h" 35 | #include "ch32v30x_misc.h" 36 | 37 | 38 | #endif /* __CH32V30x_CONF_H */ 39 | 40 | 41 | 42 | 43 | 44 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/ch32v30x_it.c: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_it.c 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : Main Interrupt Service Routines. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #include "ch32v30x_it.h" 11 | 12 | void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 13 | void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); 14 | 15 | /********************************************************************* 16 | * @fn NMI_Handler 17 | * 18 | * @brief This function handles NMI exception. 19 | * 20 | * @return none 21 | */ 22 | void NMI_Handler(void) 23 | { 24 | } 25 | 26 | /********************************************************************* 27 | * @fn HardFault_Handler 28 | * 29 | * @brief This function handles Hard Fault exception. 30 | * 31 | * @return none 32 | */ 33 | void HardFault_Handler(void) 34 | { 35 | while (1) 36 | { 37 | } 38 | } 39 | 40 | 41 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/ch32v30x_it.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : ch32v30x_it.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : This file contains the headers of the interrupt handlers. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #ifndef __CH32V30x_IT_H 11 | #define __CH32V30x_IT_H 12 | 13 | #include "debug.h" 14 | 15 | 16 | #endif /* __CH32V30x_IT_H */ 17 | 18 | 19 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/led.c: -------------------------------------------------------------------------------- 1 | #include "led.h" 2 | 3 | 4 | void GPIO_Toggle_INIT(void) 5 | { 6 | GPIO_InitTypeDef GPIO_InitStructure = {0}; 7 | 8 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); 9 | GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15; 10 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; 11 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 12 | GPIO_Init(GPIOA, &GPIO_InitStructure); 13 | } 14 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/led.h: -------------------------------------------------------------------------------- 1 | #ifndef __LED_H 2 | #define __LED_H 3 | 4 | #include "ch32v30x.h" 5 | 6 | void GPIO_Toggle_INIT(void); 7 | #endif 8 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/main.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/spi.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/spi.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/spi.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/spi.h -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/system_ch32v30x.h: -------------------------------------------------------------------------------- 1 | /********************************** (C) COPYRIGHT ******************************* 2 | * File Name : system_ch32v30x.h 3 | * Author : WCH 4 | * Version : V1.0.0 5 | * Date : 2021/06/06 6 | * Description : CH32V30x Device Peripheral Access Layer System Header File. 7 | * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. 8 | * SPDX-License-Identifier: Apache-2.0 9 | *******************************************************************************/ 10 | #ifndef __SYSTEM_CH32V30x_H 11 | #define __SYSTEM_CH32V30x_H 12 | 13 | #ifdef __cplusplus 14 | extern "C" { 15 | #endif 16 | 17 | extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ 18 | 19 | /* System_Exported_Functions */ 20 | extern void SystemInit(void); 21 | extern void SystemCoreClockUpdate(void); 22 | 23 | #ifdef __cplusplus 24 | } 25 | #endif 26 | 27 | #endif /*__CH32V30x_SYSTEM_H */ 28 | 29 | 30 | 31 | -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/tim.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/tim.c -------------------------------------------------------------------------------- /project/CH32V307VCT6/User/tim.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/User/tim.h -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/Core/subdir.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/Core/subdir.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/Debug/subdir.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/Debug/subdir.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/FOC/subdir.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/FOC/subdir.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/Peripheral/src/subdir.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/Peripheral/src/subdir.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/Startup/subdir.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/Startup/subdir.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/User/subdir.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/User/subdir.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/makefile -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/objects.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/objects.mk -------------------------------------------------------------------------------- /project/CH32V307VCT6/obj/sources.mk: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboman-ly/FOC-EKF/f73eac5f86ea6f877dde5e002f62ee7362b3299d/project/CH32V307VCT6/obj/sources.mk --------------------------------------------------------------------------------