├── PID_controller ├── PID_controller.sim │ └── sim_1 │ │ └── behav │ │ └── xsim │ │ ├── xsim.dir │ │ ├── pid_tb_behav │ │ │ ├── xsimcrash.log │ │ │ ├── xsim.type │ │ │ ├── TempBreakPointFile.txt │ │ │ ├── xsim.dbg │ │ │ ├── xsim.mem │ │ │ ├── xsim.reloc │ │ │ ├── xsim.rtti │ │ │ ├── xsim.xdbg │ │ │ ├── xsimk.exe │ │ │ ├── xsim.svtype │ │ │ ├── obj │ │ │ │ ├── xsim_0.win64.obj │ │ │ │ ├── xsim_1.win64.obj │ │ │ │ └── xsim_1.c │ │ │ ├── Compile_Options.txt │ │ │ ├── xsimkernel.log │ │ │ ├── xsim.rlx │ │ │ ├── webtalk │ │ │ │ ├── usage_statistics_ext_xsim.wdm │ │ │ │ └── xsim_webtalk.tcl │ │ │ └── xsimSettings.ini │ │ └── xil_defaultlib │ │ │ ├── glbl.sdb │ │ │ ├── pid_tb.sdb │ │ │ ├── pid_controller.sdb │ │ │ └── xil_defaultlib.rlx │ │ ├── xsim.ini │ │ ├── xelab.pb │ │ ├── xvlog.pb │ │ ├── pid_tb_behav.wdb │ │ ├── pid_tb_vlog.prj │ │ ├── xvlog.log │ │ ├── pid_tb.tcl │ │ ├── simulate.log │ │ ├── webtalk.jou │ │ ├── elaborate.log │ │ ├── webtalk_916.backup.jou │ │ ├── webtalk.log │ │ ├── webtalk_916.backup.log │ │ ├── compile.bat │ │ ├── simulate.bat │ │ ├── elaborate.bat │ │ ├── glbl.v │ │ └── dump.vcd ├── PID_controller.cache │ └── wt │ │ ├── project.wpc │ │ ├── xsim.wdf │ │ ├── java_command_handlers.wdf │ │ ├── gui_handlers.wdf │ │ └── webtalk_pa.xml ├── PID_controller.ip_user_files │ └── README.txt ├── PID_controller.hw │ └── PID_controller.lpr ├── PID_controller.srcs │ ├── sim_1 │ │ └── new │ │ │ └── pid_tb.v │ └── sources_1 │ │ └── new │ │ └── pid.v └── PID_controller.xpr ├── LICENSE └── README.md /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsimcrash.log: -------------------------------------------------------------------------------- 1 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.ini: -------------------------------------------------------------------------------- 1 | xil_defaultlib=xsim.dir/xil_defaultlib 2 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsim.type: -------------------------------------------------------------------------------- 1 |  -------------------------------------------------------------------------------- /PID_controller/PID_controller.cache/wt/project.wpc: -------------------------------------------------------------------------------- 1 | version:1 2 | 6d6f64655f636f756e7465727c4755494d6f6465:2 3 | eof: 4 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/TempBreakPointFile.txt: -------------------------------------------------------------------------------- 1 | Breakpoint File Version 1.0 2 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.ip_user_files/README.txt: -------------------------------------------------------------------------------- 1 | The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended. 2 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xelab.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xelab.pb -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xvlog.pb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xvlog.pb -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/pid_tb_behav.wdb: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsim.svtype: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsim.svtype -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pid_tb.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pid_tb.sdb -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/obj/xsim_0.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/obj/xsim_0.win64.obj -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/obj/xsim_1.win64.obj: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/obj/xsim_1.win64.obj -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pid_controller.sdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roboticvedant/Verilog-PID-Controller/HEAD/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pid_controller.sdb -------------------------------------------------------------------------------- /PID_controller/PID_controller.cache/wt/xsim.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f6d6f6465:6265686176696f72616c:00:00 3 | 7873696d:7873696d5c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73696d5f74797065:64656661756c743a3a:00:00 4 | eof:2427094519 5 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/Compile_Options.txt: -------------------------------------------------------------------------------- 1 | -wto "38821344c33747f7aec362d2014b3869" --incr --debug "typical" --relax --mt "2" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "pid_tb_behav" "xil_defaultlib.pid_tb" "xil_defaultlib.glbl" -log "elaborate.log" 2 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.hw/PID_controller.lpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/pid_tb_vlog.prj: -------------------------------------------------------------------------------- 1 | # compile verilog/system verilog design source files 2 | verilog xil_defaultlib \ 3 | "../../../../PID_controller.srcs/sources_1/new/pid.v" \ 4 | "../../../../PID_controller.srcs/sim_1/new/pid_tb.v" \ 5 | 6 | # compile glbl module 7 | verilog xil_defaultlib "glbl.v" 8 | 9 | # Do not sort compile order 10 | nosort 11 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsimkernel.log: -------------------------------------------------------------------------------- 1 | Running: xsim.dir/pid_tb_behav/xsimk.exe -simmode gui -wdb pid_tb_behav.wdb -simrunnum 0 -socket 51778 2 | Design successfully loaded 3 | Design Loading Memory Usage: 7072 KB (Peak: 7072 KB) 4 | Design Loading CPU Usage: 15 ms 5 | Simulation completed 6 | Simulation Memory Usage: 7760 KB (Peak: 7760 KB) 7 | Simulation CPU Usage: 15 ms 8 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xvlog.log: -------------------------------------------------------------------------------- 1 | INFO: [VRFC 10-2263] Analyzing Verilog file "M:/My Documents/PID_controller/PID_controller.srcs/sources_1/new/pid.v" into library xil_defaultlib 2 | INFO: [VRFC 10-311] analyzing module pid_controller 3 | INFO: [VRFC 10-2263] Analyzing Verilog file "M:/My Documents/PID_controller/PID_controller.srcs/sim_1/new/pid_tb.v" into library xil_defaultlib 4 | INFO: [VRFC 10-311] analyzing module pid_tb 5 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx: -------------------------------------------------------------------------------- 1 | 0.7 2 | 2020.2 3 | Nov 18 2020 4 | 09:47:47 5 | M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/glbl.v,1605673889,verilog,,,,glbl,,,,,,,, 6 | M:/My Documents/PID_controller/PID_controller.srcs/sim_1/new/pid_tb.v,1698004503,verilog,,,,pid_tb,,,,,,,, 7 | M:/My Documents/PID_controller/PID_controller.srcs/sources_1/new/pid.v,1698004430,verilog,,M:/My Documents/PID_controller/PID_controller.srcs/sim_1/new/pid_tb.v,,pid_controller,,,,,,,, 8 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/pid_tb.tcl: -------------------------------------------------------------------------------- 1 | set curr_wave [current_wave_config] 2 | if { [string length $curr_wave] == 0 } { 3 | if { [llength [get_objects]] > 0} { 4 | add_wave / 5 | set_property needs_save false [current_wave_config] 6 | } else { 7 | send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." 8 | } 9 | } 10 | 11 | run 1000ns 12 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/simulate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2020.2 2 | Time resolution is 1 ps 3 | Control signal is x 4 | Integral is 0 5 | Control signal is 95 6 | Integral is 38 7 | Control signal is 132 8 | Integral is 68 9 | Control signal is 124 10 | Integral is 92 11 | Control signal is 139 12 | Integral is 112 13 | Control signal is 145 14 | Integral is 126 15 | Control signal is 158 16 | Integral is 140 17 | Control signal is 165 18 | Integral is 150 19 | Control signal is 168 20 | Integral is 158 21 | Control signal is 132 22 | Integral is 148 23 | Control signal is 114 24 | $finish called at time : 150 ns : File "M:/My Documents/PID_controller/PID_controller.srcs/sim_1/new/pid_tb.v" Line 38 25 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Oct 22 14:42:30 2023 6 | # Process ID: 14972 7 | # Current directory: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source M:/My -notrace 13 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/elaborate.log: -------------------------------------------------------------------------------- 1 | Vivado Simulator 2020.2 2 | Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved. 3 | Running: C:/Programs/Xilinx/Vivado/2020.2/bin/unwrapped/win64.o/xelab.exe -wto 38821344c33747f7aec362d2014b3869 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pid_tb_behav xil_defaultlib.pid_tb xil_defaultlib.glbl -log elaborate.log 4 | Using 2 slave threads. 5 | Starting static elaboration 6 | Pass Through NonSizing Optimizer 7 | Completed static elaboration 8 | Starting simulation data flow analysis 9 | Completed simulation data flow analysis 10 | Time Resolution for simulation is 1ps 11 | Compiling module xil_defaultlib.pid_controller 12 | Compiling module xil_defaultlib.pid_tb 13 | Compiling module xil_defaultlib.glbl 14 | Built simulation snapshot pid_tb_behav 15 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk_916.backup.jou: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Oct 22 14:42:01 2023 6 | # Process ID: 916 7 | # Current directory: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source M:/My -notrace 13 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsim.rlx: -------------------------------------------------------------------------------- 1 | 2 | { 3 | crc : 15188359901487347338 , 4 | ccp_crc : 0 , 5 | cmdline : " -wto 38821344c33747f7aec362d2014b3869 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pid_tb_behav xil_defaultlib.pid_tb xil_defaultlib.glbl" , 6 | buildDate : "Nov 18 2020" , 7 | buildTime : "09:47:47" , 8 | linkCmd : "C:\\Programs\\Xilinx\\Vivado\\2020.2\\data\\..\\tps\\mingw\\6.2.0\\win64.o\\nt\\bin\\gcc.exe -Wa,-W -O -Wl,--stack,104857600 -o \"xsim.dir/pid_tb_behav/xsimk.exe\" \"xsim.dir/pid_tb_behav/obj/xsim_0.win64.obj\" \"xsim.dir/pid_tb_behav/obj/xsim_1.win64.obj\" -L\"C:\\Programs\\Xilinx\\Vivado\\2020.2\\lib\\win64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" , 9 | aggregate_nets : 10 | [ 11 | ] 12 | } -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Oct 22 14:42:30 2023 6 | # Process ID: 14972 7 | # Current directory: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source M:/My -notrace 13 | couldn't read file "M:/My": permission denied 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Oct 22 14:42:30 2023... 15 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk_916.backup.log: -------------------------------------------------------------------------------- 1 | #----------------------------------------------------------- 2 | # Webtalk v2020.2 (64-bit) 3 | # SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 4 | # IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020 5 | # Start of session at: Sun Oct 22 14:42:01 2023 6 | # Process ID: 916 7 | # Current directory: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim 8 | # Command line: wbtcv.exe -mode batch -source M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/xsim_webtalk.tcl -notrace 9 | # Log file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/webtalk.log 10 | # Journal file: M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim\webtalk.jou 11 | #----------------------------------------------------------- 12 | source M:/My -notrace 13 | couldn't read file "M:/My": permission denied 14 | INFO: [Common 17-206] Exiting Webtalk at Sun Oct 22 14:42:01 2023... 15 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/compile.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2020.2 (64-bit) 4 | REM 5 | REM Filename : compile.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for compiling the simulation design source files 8 | REM 9 | REM Generated by Vivado on Sun Oct 22 15:55:11 -0400 2023 10 | REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 11 | REM 12 | REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: compile.bat 15 | REM 16 | REM **************************************************************************** 17 | REM compile Verilog/System Verilog design sources 18 | echo "xvlog --incr --relax -prj pid_tb_vlog.prj" 19 | call xvlog --incr --relax -prj pid_tb_vlog.prj -log xvlog.log 20 | call type xvlog.log > compile.log 21 | if "%errorlevel%"=="1" goto END 22 | if "%errorlevel%"=="0" goto SUCCESS 23 | :END 24 | exit 1 25 | :SUCCESS 26 | exit 0 27 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/simulate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2020.2 (64-bit) 4 | REM 5 | REM Filename : simulate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for simulating the design by launching the simulator 8 | REM 9 | REM Generated by Vivado on Sun Oct 22 15:21:34 -0400 2023 10 | REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 11 | REM 12 | REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: simulate.bat 15 | REM 16 | REM **************************************************************************** 17 | REM simulate design 18 | echo "xsim pid_tb_behav -key {Behavioral:sim_1:Functional:pid_tb} -tclbatch pid_tb.tcl -log simulate.log" 19 | call xsim pid_tb_behav -key {Behavioral:sim_1:Functional:pid_tb} -tclbatch pid_tb.tcl -log simulate.log 20 | if "%errorlevel%"=="0" goto SUCCESS 21 | if "%errorlevel%"=="1" goto END 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2023 Vedant K. Naik 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.cache/wt/java_command_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:616464736f7572636573:32:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:636c6f736570726f6a656374:32:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65646974756e646f:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:65786974617070:31:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:6e657770726f6a656374:31:00:00 7 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72656c61756e6368:3633:00:00 8 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:73696d756c6174696f6e72756e:32:00:00 9 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:746f6f6c7373657474696e6773:31:00:00 10 | 70726f6a656374:76697661646f5f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:77617665666f726d73617665636f6e66696775726174696f6e:31:00:00 11 | eof:3153772152 12 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.srcs/sim_1/new/pid_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module pid_tb( ); 4 | reg clk = 0; 5 | reg rst_n = 0; 6 | reg [15:0] setpoint = 0; 7 | reg [15:0] feedback = 0; 8 | reg [15:0] Kp = 0; 9 | reg [15:0] Ki = 0; 10 | reg [15:0] Kd = 0; 11 | reg [15:0] clk_prescaler = 0; 12 | wire [15:0] control_signal; 13 | 14 | pid_controller DUT(.clk(clk),.rst_n(rst_n),.setpoint(setpoint),.feedback(feedback),.Kp(Kp),.Ki(Ki),.Kd(Kd),.clk_prescaler(clk_prescaler),.control_signal(control_signal)); 15 | 16 | initial begin 17 | rst_n <= 0; // Assert reset 18 | clk_prescaler <= 5; 19 | setpoint <= 20; 20 | Kp <= 5; 21 | Ki <= 2; 22 | Kd <= 1; 23 | #20 rst_n <= 1; // Deassert reset 24 | end 25 | 26 | always #1 clk = ~clk; 27 | 28 | always begin 29 | $monitor("Control signal is %d",control_signal); 30 | #20 feedback <= 1; 31 | #15 feedback <= 5; 32 | #15 feedback <= 8; 33 | #15 feedback <= 10; 34 | #15 feedback <= 13; 35 | #15 feedback <= 15; 36 | #15 feedback <= 16; 37 | #15 feedback <=25; 38 | #25 $finish; 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/elaborate.bat: -------------------------------------------------------------------------------- 1 | @echo off 2 | REM **************************************************************************** 3 | REM Vivado (TM) v2020.2 (64-bit) 4 | REM 5 | REM Filename : elaborate.bat 6 | REM Simulator : Xilinx Vivado Simulator 7 | REM Description : Script for elaborating the compiled design 8 | REM 9 | REM Generated by Vivado on Sun Oct 22 15:55:13 -0400 2023 10 | REM SW Build 3064766 on Wed Nov 18 09:12:45 MST 2020 11 | REM 12 | REM Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. 13 | REM 14 | REM usage: elaborate.bat 15 | REM 16 | REM **************************************************************************** 17 | REM elaborate design 18 | echo "xelab -wto 38821344c33747f7aec362d2014b3869 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pid_tb_behav xil_defaultlib.pid_tb xil_defaultlib.glbl -log elaborate.log" 19 | call xelab -wto 38821344c33747f7aec362d2014b3869 --incr --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot pid_tb_behav xil_defaultlib.pid_tb xil_defaultlib.glbl -log elaborate.log 20 | if "%errorlevel%"=="0" goto SUCCESS 21 | if "%errorlevel%"=="1" goto END 22 | :END 23 | exit 1 24 | :SUCCESS 25 | exit 0 26 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/usage_statistics_ext_xsim.wdm: -------------------------------------------------------------------------------- 1 | version = "1.0"; 2 | clients = 3 | ( 4 | { client_name = "project"; 5 | rules = ( 6 | { 7 | context="software_version_and_target_device"; 8 | xml_map="software_version_and_target_device"; 9 | html_map="software_version_and_target_device"; 10 | html_format="UserEnvStyle"; 11 | }, 12 | { 13 | context="user_environment"; 14 | xml_map="user_environment"; 15 | html_map="user_environment"; 16 | html_format="UserEnvStyle"; 17 | } 18 | ); 19 | }, 20 | 21 | { client_name = "xsim"; 22 | rules = ( 23 | { 24 | context="xsim\\command_line_options"; 25 | xml_map="xsim\\command_line_options"; 26 | html_map="xsim\\command_line_options"; 27 | html_format="UnisimStatsStyle"; 28 | }, 29 | { 30 | context="xsim\\usage"; 31 | xml_map="xsim\\usage"; 32 | html_map="xsim\\usage"; 33 | html_format="UnisimStatsStyle"; 34 | } 35 | ); 36 | } 37 | ); 38 | 39 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/xsimSettings.ini: -------------------------------------------------------------------------------- 1 | [General] 2 | ARRAY_DISPLAY_LIMIT=512 3 | RADIX=hex 4 | TIME_UNIT=ns 5 | TRACE_LIMIT=2147483647 6 | VHDL_ENTITY_SCOPE_FILTER=true 7 | VHDL_PACKAGE_SCOPE_FILTER=false 8 | VHDL_BLOCK_SCOPE_FILTER=true 9 | VHDL_PROCESS_SCOPE_FILTER=false 10 | VHDL_PROCEDURE_SCOPE_FILTER=false 11 | VERILOG_MODULE_SCOPE_FILTER=true 12 | VERILOG_PACKAGE_SCOPE_FILTER=false 13 | VERILOG_BLOCK_SCOPE_FILTER=false 14 | VERILOG_TASK_SCOPE_FILTER=false 15 | VERILOG_PROCESS_SCOPE_FILTER=false 16 | INPUT_OBJECT_FILTER=true 17 | OUTPUT_OBJECT_FILTER=true 18 | INOUT_OBJECT_FILTER=true 19 | INTERNAL_OBJECT_FILTER=true 20 | CONSTANT_OBJECT_FILTER=true 21 | VARIABLE_OBJECT_FILTER=true 22 | INPUT_PROTOINST_FILTER=true 23 | OUTPUT_PROTOINST_FILTER=true 24 | INOUT_PROTOINST_FILTER=true 25 | INTERNAL_PROTOINST_FILTER=true 26 | CONSTANT_PROTOINST_FILTER=true 27 | VARIABLE_PROTOINST_FILTER=true 28 | SCOPE_NAME_COLUMN_WIDTH=75 29 | SCOPE_DESIGN_UNIT_COLUMN_WIDTH=75 30 | SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75 31 | OBJECT_NAME_COLUMN_WIDTH=109 32 | OBJECT_VALUE_COLUMN_WIDTH=75 33 | OBJECT_DATA_TYPE_COLUMN_WIDTH=75 34 | PROCESS_NAME_COLUMN_WIDTH=75 35 | PROCESS_TYPE_COLUMN_WIDTH=75 36 | FRAME_INDEX_COLUMN_WIDTH=75 37 | FRAME_NAME_COLUMN_WIDTH=75 38 | FRAME_FILE_NAME_COLUMN_WIDTH=75 39 | FRAME_LINE_NUM_COLUMN_WIDTH=109 40 | LOCAL_NAME_COLUMN_WIDTH=75 41 | LOCAL_VALUE_COLUMN_WIDTH=75 42 | LOCAL_DATA_TYPE_COLUMN_WIDTH=0 43 | PROTO_NAME_COLUMN_WIDTH=0 44 | PROTO_VALUE_COLUMN_WIDTH=0 45 | INPUT_LOCAL_FILTER=1 46 | OUTPUT_LOCAL_FILTER=1 47 | INOUT_LOCAL_FILTER=1 48 | INTERNAL_LOCAL_FILTER=1 49 | CONSTANT_LOCAL_FILTER=1 50 | VARIABLE_LOCAL_FILTER=1 51 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.srcs/sources_1/new/pid.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module pid_controller( 4 | input clk, 5 | input rst_n, 6 | input [15:0] setpoint, 7 | input [15:0] feedback, 8 | input [15:0] Kp, 9 | input [15:0] Ki, 10 | input [15:0] Kd, 11 | input [15:0] clk_prescaler, 12 | output reg [15:0] control_signal 13 | ); 14 | 15 | // Internal signals 16 | 17 | reg [15:0] prev_error = 16'h0000; 18 | reg [15:0] integral = 32'h00000000; 19 | reg [15:0] derivative = 16'h0000; 20 | 21 | // Clock divider for sampling rate 22 | reg [15:0] clk_divider = 0; 23 | reg sampling_flag = 0; 24 | 25 | always @(posedge clk or negedge rst_n) begin 26 | //$display("Clock trigered"); 27 | if (~rst_n) 28 | clk_divider <= 16'h0000; 29 | else if (clk_divider == clk_prescaler) begin // clk_prescaler determines the sampling rate, thus sampling rate would be clk freq/clk_prescaler 30 | clk_divider <= 16'h0000; 31 | 32 | sampling_flag <= 1; 33 | end else begin 34 | clk_divider <= clk_divider + 1; 35 | sampling_flag <= 0; 36 | end 37 | end 38 | 39 | always @(posedge clk or negedge rst_n) begin 40 | 41 | if (~rst_n) begin 42 | // Reset logic generally specific to application 43 | end 44 | else if (sampling_flag) begin 45 | 46 | // PID Calculation 47 | integral <= integral + (Ki * (setpoint - feedback)); 48 | $display("Integral is %d",integral); 49 | derivative <= Kd * ((setpoint - feedback) - prev_error); 50 | // Calculate control signal 51 | control_signal = (Kp * (setpoint - feedback)) + integral + derivative; 52 | prev_error <= (setpoint - feedback);// Update previous error term to feed it for derrivative term. 53 | end 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/glbl.v: -------------------------------------------------------------------------------- 1 | // $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ 2 | `ifndef GLBL 3 | `define GLBL 4 | `timescale 1 ps / 1 ps 5 | 6 | module glbl (); 7 | 8 | parameter ROC_WIDTH = 100000; 9 | parameter TOC_WIDTH = 0; 10 | parameter GRES_WIDTH = 10000; 11 | parameter GRES_START = 10000; 12 | 13 | //-------- STARTUP Globals -------------- 14 | wire GSR; 15 | wire GTS; 16 | wire GWE; 17 | wire PRLD; 18 | wire GRESTORE; 19 | tri1 p_up_tmp; 20 | tri (weak1, strong0) PLL_LOCKG = p_up_tmp; 21 | 22 | wire PROGB_GLBL; 23 | wire CCLKO_GLBL; 24 | wire FCSBO_GLBL; 25 | wire [3:0] DO_GLBL; 26 | wire [3:0] DI_GLBL; 27 | 28 | reg GSR_int; 29 | reg GTS_int; 30 | reg PRLD_int; 31 | reg GRESTORE_int; 32 | 33 | //-------- JTAG Globals -------------- 34 | wire JTAG_TDO_GLBL; 35 | wire JTAG_TCK_GLBL; 36 | wire JTAG_TDI_GLBL; 37 | wire JTAG_TMS_GLBL; 38 | wire JTAG_TRST_GLBL; 39 | 40 | reg JTAG_CAPTURE_GLBL; 41 | reg JTAG_RESET_GLBL; 42 | reg JTAG_SHIFT_GLBL; 43 | reg JTAG_UPDATE_GLBL; 44 | reg JTAG_RUNTEST_GLBL; 45 | 46 | reg JTAG_SEL1_GLBL = 0; 47 | reg JTAG_SEL2_GLBL = 0 ; 48 | reg JTAG_SEL3_GLBL = 0; 49 | reg JTAG_SEL4_GLBL = 0; 50 | 51 | reg JTAG_USER_TDO1_GLBL = 1'bz; 52 | reg JTAG_USER_TDO2_GLBL = 1'bz; 53 | reg JTAG_USER_TDO3_GLBL = 1'bz; 54 | reg JTAG_USER_TDO4_GLBL = 1'bz; 55 | 56 | assign (strong1, weak0) GSR = GSR_int; 57 | assign (strong1, weak0) GTS = GTS_int; 58 | assign (weak1, weak0) PRLD = PRLD_int; 59 | assign (strong1, weak0) GRESTORE = GRESTORE_int; 60 | 61 | initial begin 62 | GSR_int = 1'b1; 63 | PRLD_int = 1'b1; 64 | #(ROC_WIDTH) 65 | GSR_int = 1'b0; 66 | PRLD_int = 1'b0; 67 | end 68 | 69 | initial begin 70 | GTS_int = 1'b1; 71 | #(TOC_WIDTH) 72 | GTS_int = 1'b0; 73 | end 74 | 75 | initial begin 76 | GRESTORE_int = 1'b0; 77 | #(GRES_START); 78 | GRESTORE_int = 1'b1; 79 | #(GRES_WIDTH); 80 | GRESTORE_int = 1'b0; 81 | end 82 | 83 | endmodule 84 | `endif 85 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PID Controller in Verilog for FPGA and ASIC Applications 2 | 3 | ## Overview 4 | 5 | This repository houses a PID (Proportional-Integral-Derivative) controller, implemented in Verilog, suitable for FPGA and ASIC applications. PID controllers are pivotal in control theory, and they are used in myriad applications, including those that are time-sensitive. The project aims to serve as a basis for sophisticated control systems where fine-grained control and real-time operation are essential. 6 | 7 | ## Features 8 | 9 | - 16-bit arithmetic for high-precision control. 10 | - Configurable `Kp`, `Ki`, `Kd` coefficients to adapt to various systems. 11 | - Clock prescaling feature to adjust the controller's sampling rate. 12 | - Includes a testbench simulating a generic linear system for validation. 13 | 14 | ## Current Areas of Focus 15 | 16 | 1. **Robustness**: Ongoing efforts are focused on making the PID controller more robust to cater to different environmental conditions and systems. 17 | 18 | 2. **Model Predictive Control**: An additional layer of Model Predictive Control (MPC) is under development, aiming to provide optimal control in complex systems. 19 | 20 | 3. **Standardized Test Stimulus**: Work is in progress to create a standardized testbench stimulus that simulates a common linear system for more rigorous testing and validation. 21 | 22 | ## Code Structure 23 | 24 | The main Verilog module `pid_controller` takes care of the PID calculations: 25 | 26 | - `clk`, `rst_n`: Clock and Reset signals. 27 | - `setpoint`, `feedback`: Control variables. 28 | - `Kp`, `Ki`, `Kd`: PID coefficients. 29 | - `clk_prescaler`: Clock prescaler for adjustable sampling rate. 30 | - `control_signal`: Output control signal. 31 | 32 | The `pid_tb` (testbench) module provides a simulated environment to validate the PID controller. It includes the feedback system and allows for adjustments to the `Kp`, `Ki`, `Kd` coefficients and `clk_prescaler` to test the controller in different scenarios. 33 | 34 | ## Applications in Time-Sensitive Systems 35 | 36 | 1. **Automated Manufacturing**: In industrial settings where machinery needs to respond in real-time. 37 | 2. **Telecommunications**: For latency-critical applications such as real-time packet routing. 38 | 3. **Robotics and Drones**: Where fast and precise control is necessary for stabilization and movement. 39 | 4. **Healthcare Devices**: In medical instruments like infusion pumps and ventilators where precision and speed are critical. 40 | 41 | ## Getting Started 42 | 43 | ### Dependencies 44 | 45 | - Xilinx Vivado for synthesizing the design (optional for FPGA deployment) 46 | - A Verilog simulator like ModelSim for simulation and testing 47 | 48 | ### Running the Project 49 | 50 | 1. Clone this repository. 51 | 2. Open the `.xpr` file in Xilinx Vivado if you are planning to synthesize for FPGA. 52 | 3. To run the simulation, open the project in a Verilog simulator and execute the testbench. 53 | 54 | ## Contributing 55 | 56 | Contributions to enhance the functionality are most welcome. Fork this repository and create a pull request or open an issue for discussion. 57 | 58 | ## License 59 | 60 | This project is licensed under the MIT License. For more information, see [LICENSE.md](https://github.com/roboticvedant/Verilog-PID-Controller/blob/main/LICENSE). 61 | 62 | 63 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/xsim_webtalk.tcl: -------------------------------------------------------------------------------- 1 | webtalk_init -webtalk_dir M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/ 2 | webtalk_register_client -client project 3 | webtalk_add_data -client project -key date_generated -value "Sun Oct 22 16:04:47 2023" -context "software_version_and_target_device" 4 | webtalk_add_data -client project -key product_version -value "XSIM v2020.2 (64-bit)" -context "software_version_and_target_device" 5 | webtalk_add_data -client project -key build_version -value "3064766" -context "software_version_and_target_device" 6 | webtalk_add_data -client project -key os_platform -value "WIN64" -context "software_version_and_target_device" 7 | webtalk_add_data -client project -key registration_id -value "" -context "software_version_and_target_device" 8 | webtalk_add_data -client project -key tool_flow -value "xsim_vivado" -context "software_version_and_target_device" 9 | webtalk_add_data -client project -key beta -value "FALSE" -context "software_version_and_target_device" 10 | webtalk_add_data -client project -key route_design -value "FALSE" -context "software_version_and_target_device" 11 | webtalk_add_data -client project -key target_family -value "not_applicable" -context "software_version_and_target_device" 12 | webtalk_add_data -client project -key target_device -value "not_applicable" -context "software_version_and_target_device" 13 | webtalk_add_data -client project -key target_package -value "not_applicable" -context "software_version_and_target_device" 14 | webtalk_add_data -client project -key target_speed -value "not_applicable" -context "software_version_and_target_device" 15 | webtalk_add_data -client project -key random_id -value "f2f76243-a17e-43b2-a010-107529976e44" -context "software_version_and_target_device" 16 | webtalk_add_data -client project -key project_id -value "38821344c33747f7aec362d2014b3869" -context "software_version_and_target_device" 17 | webtalk_add_data -client project -key project_iteration -value "123" -context "software_version_and_target_device" 18 | webtalk_add_data -client project -key os_name -value "Windows Server 2016 or Windows 10" -context "user_environment" 19 | webtalk_add_data -client project -key os_release -value "major release (build 9200)" -context "user_environment" 20 | webtalk_add_data -client project -key cpu_name -value "11th Gen Intel(R) Core(TM) i7-11700T @ 1.40GHz" -context "user_environment" 21 | webtalk_add_data -client project -key cpu_speed -value "1392 MHz" -context "user_environment" 22 | webtalk_add_data -client project -key total_processors -value "1" -context "user_environment" 23 | webtalk_add_data -client project -key system_ram -value "16.000 GB" -context "user_environment" 24 | webtalk_register_client -client xsim 25 | webtalk_add_data -client xsim -key Command -value "xsim" -context "xsim\\command_line_options" 26 | webtalk_add_data -client xsim -key trace_waveform -value "true" -context "xsim\\usage" 27 | webtalk_add_data -client xsim -key runtime -value "150 ns" -context "xsim\\usage" 28 | webtalk_add_data -client xsim -key iteration -value "0" -context "xsim\\usage" 29 | webtalk_add_data -client xsim -key Simulation_Time -value "0.01_sec" -context "xsim\\usage" 30 | webtalk_add_data -client xsim -key Simulation_Memory -value "7760_KB" -context "xsim\\usage" 31 | webtalk_transmit -clientid 2777689321 -regid "" -xml M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/usage_statistics_ext_xsim.xml -html M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/usage_statistics_ext_xsim.html -wdm M:/My Documents/PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/webtalk/usage_statistics_ext_xsim.wdm -intro "

XSIM Usage Report


" 32 | webtalk_terminate 33 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.cache/wt/gui_handlers.wdf: -------------------------------------------------------------------------------- 1 | version:1 2 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:61646473726377697a6172645f737065636966795f73696d756c6174696f6e5f73706563696669635f68646c5f66696c6573:31:00:00 3 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626173656469616c6f675f6f6b:3232:00:00 4 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:626f61726463686f6f7365725f626f6172645f7461626c65:31:00:00 5 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:636d646d73676469616c6f675f6f6b:31:00:00 6 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:63726561746573726366696c656469616c6f675f66696c655f6e616d65:32:00:00 7 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:3133:00:00 8 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:666c6f776e6176696761746f727472656570616e656c5f666c6f775f6e6176696761746f725f74726565:34:00:00 9 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f666974:3230:00:00 10 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:67726170686963616c766965775f7a6f6f6d5f696e:34:00:00 11 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f636c6f7365:31:00:00 12 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:68636f6465656469746f725f7365617263685f746578745f636f6d626f5f626f78:34:00:00 13 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f636865636b706f696e74:31:00:00 14 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f66696c65:34:00:00 15 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f6970:31:00:00 16 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f70726f6a656374:33:00:00 17 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f73696d756c6174696f6e5f77617665666f726d:31:00:00 18 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:6d61696e6d656e756d67725f746578745f656469746f72:31:00:00 19 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f6e65775f70726f6a656374:31:00:00 20 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72656c61756e6368:3732:00:00 21 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f73696d756c6174696f6e5f72756e5f6265686176696f72616c:32:00:00 22 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f70726f6a6563745f73756d6d617279:32:00:00 23 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a6563746e616d6563686f6f7365725f70726f6a6563745f6e616d65:32:00:00 24 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:70726f6a65637473657474696e67736761646765745f656469745f70726f6a6563745f73657474696e6773:31:00:00 25 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:726469636f6d6d616e64735f736176655f66696c65:36:00:00 26 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:72646976696577735f77617665666f726d5f766965776572:3938:00:00 27 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6c69766572756e666f72636f6d705f737065636966795f74696d655f616e645f756e697473:33:00:00 28 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d756c6174696f6e6f626a6563747370616e656c5f73696d756c6174696f6e5f6f626a656374735f747265655f7461626c65:3133:00:00 29 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73726363686f6f73657270616e656c5f6372656174655f66696c65:32:00:00 30 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73796e7468657469636167657474696e6773746172746564766965775f726563656e745f70726f6a65637473:31:00:00 31 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:3231:00:00 32 | 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:77617665666f726d6e616d65747265655f77617665666f726d5f6e616d655f74726565:3131:00:00 33 | eof:3079328145 34 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.cache/wt/webtalk_pa.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 6 | 7 |
8 | 9 | 10 |
11 |
12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 |
69 | 70 | 71 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/xsim.dir/pid_tb_behav/obj/xsim_1.c: -------------------------------------------------------------------------------- 1 | /**********************************************************************/ 2 | /* ____ ____ */ 3 | /* / /\/ / */ 4 | /* /___/ \ / */ 5 | /* \ \ \/ */ 6 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 7 | /* / / All Right Reserved. */ 8 | /* /---/ /\ */ 9 | /* \ \ / \ */ 10 | /* \___\/\___\ */ 11 | /**********************************************************************/ 12 | 13 | #if defined(_WIN32) 14 | #include "stdio.h" 15 | #define IKI_DLLESPEC __declspec(dllimport) 16 | #else 17 | #define IKI_DLLESPEC 18 | #endif 19 | #include "iki.h" 20 | #include 21 | #include 22 | #ifdef __GNUC__ 23 | #include 24 | #else 25 | #include 26 | #define alloca _alloca 27 | #endif 28 | /**********************************************************************/ 29 | /* ____ ____ */ 30 | /* / /\/ / */ 31 | /* /___/ \ / */ 32 | /* \ \ \/ */ 33 | /* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */ 34 | /* / / All Right Reserved. */ 35 | /* /---/ /\ */ 36 | /* \ \ / \ */ 37 | /* \___\/\___\ */ 38 | /**********************************************************************/ 39 | 40 | #if defined(_WIN32) 41 | #include "stdio.h" 42 | #define IKI_DLLESPEC __declspec(dllimport) 43 | #else 44 | #define IKI_DLLESPEC 45 | #endif 46 | #include "iki.h" 47 | #include 48 | #include 49 | #ifdef __GNUC__ 50 | #include 51 | #else 52 | #include 53 | #define alloca _alloca 54 | #endif 55 | typedef void (*funcp)(char *, char *); 56 | extern int main(int, char**); 57 | IKI_DLLESPEC extern void execute_6(char*, char *); 58 | IKI_DLLESPEC extern void execute_7(char*, char *); 59 | IKI_DLLESPEC extern void execute_8(char*, char *); 60 | IKI_DLLESPEC extern void execute_9(char*, char *); 61 | IKI_DLLESPEC extern void execute_15(char*, char *); 62 | IKI_DLLESPEC extern void execute_16(char*, char *); 63 | IKI_DLLESPEC extern void execute_17(char*, char *); 64 | IKI_DLLESPEC extern void execute_18(char*, char *); 65 | IKI_DLLESPEC extern void execute_19(char*, char *); 66 | IKI_DLLESPEC extern void execute_20(char*, char *); 67 | IKI_DLLESPEC extern void execute_21(char*, char *); 68 | IKI_DLLESPEC extern void execute_22(char*, char *); 69 | IKI_DLLESPEC extern void execute_23(char*, char *); 70 | IKI_DLLESPEC extern void execute_24(char*, char *); 71 | IKI_DLLESPEC extern void execute_3(char*, char *); 72 | IKI_DLLESPEC extern void execute_4(char*, char *); 73 | IKI_DLLESPEC extern void execute_5(char*, char *); 74 | IKI_DLLESPEC extern void execute_11(char*, char *); 75 | IKI_DLLESPEC extern void execute_12(char*, char *); 76 | IKI_DLLESPEC extern void execute_13(char*, char *); 77 | IKI_DLLESPEC extern void execute_14(char*, char *); 78 | IKI_DLLESPEC extern void execute_25(char*, char *); 79 | IKI_DLLESPEC extern void execute_26(char*, char *); 80 | IKI_DLLESPEC extern void execute_27(char*, char *); 81 | IKI_DLLESPEC extern void execute_28(char*, char *); 82 | IKI_DLLESPEC extern void execute_29(char*, char *); 83 | IKI_DLLESPEC extern void execute_30(char*, char *); 84 | IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *); 85 | funcp funcTab[28] = {(funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_15, (funcp)execute_16, (funcp)execute_17, (funcp)execute_18, (funcp)execute_19, (funcp)execute_20, (funcp)execute_21, (funcp)execute_22, (funcp)execute_23, (funcp)execute_24, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_11, (funcp)execute_12, (funcp)execute_13, (funcp)execute_14, (funcp)execute_25, (funcp)execute_26, (funcp)execute_27, (funcp)execute_28, (funcp)execute_29, (funcp)execute_30, (funcp)vlog_transfunc_eventcallback}; 86 | const int NumRelocateId= 28; 87 | 88 | void relocate(char *dp) 89 | { 90 | iki_relocate(dp, "xsim.dir/pid_tb_behav/xsim.reloc", (void **)funcTab, 28); 91 | 92 | /*Populate the transaction function pointer field in the whole net structure */ 93 | } 94 | 95 | void sensitize(char *dp) 96 | { 97 | iki_sensitize(dp, "xsim.dir/pid_tb_behav/xsim.reloc"); 98 | } 99 | 100 | void simulate(char *dp) 101 | { 102 | iki_schedule_processes_at_time_zero(dp, "xsim.dir/pid_tb_behav/xsim.reloc"); 103 | // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net 104 | iki_execute_processes(); 105 | 106 | // Schedule resolution functions for the multiply driven Verilog nets that have strength 107 | // Schedule transaction functions for the singly driven Verilog nets that have strength 108 | 109 | } 110 | #include "iki_bridge.h" 111 | void relocate(char *); 112 | 113 | void sensitize(char *); 114 | 115 | void simulate(char *); 116 | 117 | extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*); 118 | extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ; 119 | extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ; 120 | 121 | int main(int argc, char **argv) 122 | { 123 | iki_heap_initialize("ms", "isimmm", 0, 2147483648) ; 124 | iki_set_sv_type_file_path_name("xsim.dir/pid_tb_behav/xsim.svtype"); 125 | iki_set_crvs_dump_file_path_name("xsim.dir/pid_tb_behav/xsim.crvsdump"); 126 | void* design_handle = iki_create_design("xsim.dir/pid_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv); 127 | iki_set_rc_trial_count(100); 128 | (void) design_handle; 129 | return iki_simulate_design(); 130 | } 131 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.xpr: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 90 | 91 | 92 | 93 | 94 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 120 | 121 | 122 | 123 | 124 | 126 | 127 | 128 | 129 | 130 | 133 | 134 | 136 | 137 | 139 | 140 | 142 | 143 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | default_dashboard 204 | 205 | 206 | 207 | -------------------------------------------------------------------------------- /PID_controller/PID_controller.sim/sim_1/behav/xsim/dump.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Oct 22 15:12:23 2023 3 | $end 4 | $version 5 | 2020.2 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module pid_tb $end 11 | $var reg 1 ! clk $end 12 | $var reg 1 " rst_n $end 13 | $var reg 16 # setpoint [15:0] $end 14 | $var reg 16 $ feedback [15:0] $end 15 | $var reg 16 % Kp [15:0] $end 16 | $var reg 16 & Ki [15:0] $end 17 | $var reg 16 ' Kd [15:0] $end 18 | $var reg 16 ( clk_prescaler [15:0] $end 19 | $var wire 16 ) control_signal [15:0] $end 20 | $scope module DUT $end 21 | $var wire 1 * clk $end 22 | $var wire 1 + rst_n $end 23 | $var wire 16 , setpoint [15:0] $end 24 | $var wire 16 - feedback [15:0] $end 25 | $var wire 16 . Kp [15:0] $end 26 | $var wire 16 / Ki [15:0] $end 27 | $var wire 16 0 Kd [15:0] $end 28 | $var wire 16 1 clk_prescaler [15:0] $end 29 | $var reg 16 2 control_signal [15:0] $end 30 | $var reg 16 3 error [15:0] $end 31 | $var reg 16 4 prev_error [15:0] $end 32 | $var reg 32 5 integral [31:0] $end 33 | $var reg 16 6 derivative [15:0] $end 34 | $var reg 16 7 clk_divider [15:0] $end 35 | $var reg 1 8 sampling_flag $end 36 | $upscope $end 37 | $upscope $end 38 | $enddefinitions $end 39 | #0 40 | $dumpvars 41 | 0! 42 | 0" 43 | b110010 # 44 | b0 $ 45 | b101 % 46 | b1 & 47 | b0 ' 48 | b1 ( 49 | bx ) 50 | 0* 51 | 0+ 52 | b110010 , 53 | b0 - 54 | b101 . 55 | b1 / 56 | b0 0 57 | b1 1 58 | bx 2 59 | b0 3 60 | b0 4 61 | b0 5 62 | b0 6 63 | b0 7 64 | 08 65 | $end 66 | #1000 67 | 1! 68 | 1* 69 | b0 7 70 | #2000 71 | 0! 72 | 0* 73 | #3000 74 | 1! 75 | 1* 76 | b0 7 77 | #4000 78 | 0! 79 | 0* 80 | #5000 81 | 1! 82 | 1* 83 | b0 7 84 | #6000 85 | 0! 86 | 0* 87 | #7000 88 | 1! 89 | 1* 90 | b0 7 91 | #8000 92 | 0! 93 | 0* 94 | #9000 95 | 1! 96 | 1* 97 | b0 7 98 | #10000 99 | 0! 100 | 0* 101 | #11000 102 | 1! 103 | 1* 104 | b0 7 105 | #12000 106 | 0! 107 | 0* 108 | #13000 109 | 1! 110 | 1* 111 | b0 7 112 | #14000 113 | 0! 114 | 0* 115 | #15000 116 | 1! 117 | 1* 118 | b0 7 119 | #16000 120 | 0! 121 | 0* 122 | #17000 123 | 1! 124 | 1* 125 | b0 7 126 | #18000 127 | 0! 128 | 0* 129 | #19000 130 | 1! 131 | 1* 132 | b0 7 133 | #20000 134 | 0! 135 | 1" 136 | 0* 137 | 1+ 138 | #21000 139 | 1! 140 | 1* 141 | b1 7 142 | 08 143 | #22000 144 | 0! 145 | 0* 146 | #23000 147 | 1! 148 | 1* 149 | b0 7 150 | 18 151 | #24000 152 | 0! 153 | 0* 154 | #25000 155 | 1! 156 | b0 ) 157 | 1* 158 | b0 2 159 | b110010 3 160 | b0 4 161 | b0 5 162 | b0 6 163 | b1 7 164 | 08 165 | #26000 166 | 0! 167 | 0* 168 | #27000 169 | 1! 170 | 1* 171 | b0 7 172 | 18 173 | #28000 174 | 0! 175 | 0* 176 | #29000 177 | 1! 178 | b11111010 ) 179 | 1* 180 | b11111010 2 181 | b110010 3 182 | b110010 4 183 | b110010 5 184 | b0 6 185 | b1 7 186 | 08 187 | #30000 188 | 0! 189 | 0* 190 | #31000 191 | 1! 192 | 1* 193 | b0 7 194 | 18 195 | #32000 196 | 0! 197 | 0* 198 | #33000 199 | 1! 200 | 1* 201 | b11111010 2 202 | b110010 3 203 | b110010 4 204 | b1100100 5 205 | b0 6 206 | b1 7 207 | 08 208 | #34000 209 | 0! 210 | 0* 211 | #35000 212 | 1! 213 | 1* 214 | b0 7 215 | 18 216 | #36000 217 | 0! 218 | 0* 219 | #37000 220 | 1! 221 | 1* 222 | b11111010 2 223 | b110010 3 224 | b110010 4 225 | b10010110 5 226 | b0 6 227 | b1 7 228 | 08 229 | #38000 230 | 0! 231 | 0* 232 | #39000 233 | 1! 234 | 1* 235 | b0 7 236 | 18 237 | #40000 238 | 0! 239 | 0* 240 | #41000 241 | 1! 242 | 1* 243 | b11111010 2 244 | b110010 3 245 | b110010 4 246 | b11001000 5 247 | b0 6 248 | b1 7 249 | 08 250 | #42000 251 | 0! 252 | 0* 253 | #43000 254 | 1! 255 | 1* 256 | b0 7 257 | 18 258 | #44000 259 | 0! 260 | 0* 261 | #45000 262 | 1! 263 | 1* 264 | b11111010 2 265 | b110010 3 266 | b110010 4 267 | b11111010 5 268 | b0 6 269 | b1 7 270 | 08 271 | #46000 272 | 0! 273 | 0* 274 | #47000 275 | 1! 276 | 1* 277 | b0 7 278 | 18 279 | #48000 280 | 0! 281 | 0* 282 | #49000 283 | 1! 284 | 1* 285 | b11111010 2 286 | b110010 3 287 | b110010 4 288 | b100101100 5 289 | b0 6 290 | b1 7 291 | 08 292 | #50000 293 | 0! 294 | 0* 295 | #51000 296 | 1! 297 | 1* 298 | b0 7 299 | 18 300 | #52000 301 | 0! 302 | 0* 303 | #53000 304 | 1! 305 | 1* 306 | b11111010 2 307 | b110010 3 308 | b110010 4 309 | b101011110 5 310 | b0 6 311 | b1 7 312 | 08 313 | #54000 314 | 0! 315 | 0* 316 | #55000 317 | 1! 318 | 1* 319 | b0 7 320 | 18 321 | #56000 322 | 0! 323 | 0* 324 | #57000 325 | 1! 326 | 1* 327 | b11111010 2 328 | b110010 3 329 | b110010 4 330 | b110010000 5 331 | b0 6 332 | b1 7 333 | 08 334 | #58000 335 | 0! 336 | 0* 337 | #59000 338 | 1! 339 | 1* 340 | b0 7 341 | 18 342 | #60000 343 | 0! 344 | 0* 345 | #61000 346 | 1! 347 | 1* 348 | b11111010 2 349 | b110010 3 350 | b110010 4 351 | b111000010 5 352 | b0 6 353 | b1 7 354 | 08 355 | #62000 356 | 0! 357 | 0* 358 | #63000 359 | 1! 360 | 1* 361 | b0 7 362 | 18 363 | #64000 364 | 0! 365 | 0* 366 | #65000 367 | 1! 368 | 1* 369 | b11111010 2 370 | b110010 3 371 | b110010 4 372 | b111110100 5 373 | b0 6 374 | b1 7 375 | 08 376 | #66000 377 | 0! 378 | 0* 379 | #67000 380 | 1! 381 | 1* 382 | b0 7 383 | 18 384 | #68000 385 | 0! 386 | 0* 387 | #69000 388 | 1! 389 | 1* 390 | b11111010 2 391 | b110010 3 392 | b110010 4 393 | b1000100110 5 394 | b0 6 395 | b1 7 396 | 08 397 | #70000 398 | 0! 399 | 0* 400 | #71000 401 | 1! 402 | 1* 403 | b0 7 404 | 18 405 | #72000 406 | 0! 407 | 0* 408 | #73000 409 | 1! 410 | 1* 411 | b11111010 2 412 | b110010 3 413 | b110010 4 414 | b1001011000 5 415 | b0 6 416 | b1 7 417 | 08 418 | #74000 419 | 0! 420 | 0* 421 | #75000 422 | 1! 423 | 1* 424 | b0 7 425 | 18 426 | #76000 427 | 0! 428 | 0* 429 | #77000 430 | 1! 431 | 1* 432 | b11111010 2 433 | b110010 3 434 | b110010 4 435 | b1010001010 5 436 | b0 6 437 | b1 7 438 | 08 439 | #78000 440 | 0! 441 | 0* 442 | #79000 443 | 1! 444 | 1* 445 | b0 7 446 | 18 447 | #80000 448 | 0! 449 | 0* 450 | #81000 451 | 1! 452 | 1* 453 | b11111010 2 454 | b110010 3 455 | b110010 4 456 | b1010111100 5 457 | b0 6 458 | b1 7 459 | 08 460 | #82000 461 | 0! 462 | 0* 463 | #83000 464 | 1! 465 | 1* 466 | b0 7 467 | 18 468 | #84000 469 | 0! 470 | 0* 471 | #85000 472 | 1! 473 | 1* 474 | b11111010 2 475 | b110010 3 476 | b110010 4 477 | b1011101110 5 478 | b0 6 479 | b1 7 480 | 08 481 | #86000 482 | 0! 483 | 0* 484 | #87000 485 | 1! 486 | 1* 487 | b0 7 488 | 18 489 | #88000 490 | 0! 491 | 0* 492 | #89000 493 | 1! 494 | 1* 495 | b11111010 2 496 | b110010 3 497 | b110010 4 498 | b1100100000 5 499 | b0 6 500 | b1 7 501 | 08 502 | #90000 503 | 0! 504 | 0* 505 | #91000 506 | 1! 507 | 1* 508 | b0 7 509 | 18 510 | #92000 511 | 0! 512 | 0* 513 | #93000 514 | 1! 515 | 1* 516 | b11111010 2 517 | b110010 3 518 | b110010 4 519 | b1101010010 5 520 | b0 6 521 | b1 7 522 | 08 523 | #94000 524 | 0! 525 | 0* 526 | #95000 527 | 1! 528 | 1* 529 | b0 7 530 | 18 531 | #96000 532 | 0! 533 | 0* 534 | #97000 535 | 1! 536 | 1* 537 | b11111010 2 538 | b110010 3 539 | b110010 4 540 | b1110000100 5 541 | b0 6 542 | b1 7 543 | 08 544 | #98000 545 | 0! 546 | 0* 547 | #99000 548 | 1! 549 | 1* 550 | b0 7 551 | 18 552 | #100000 553 | 0! 554 | 0* 555 | #101000 556 | 1! 557 | 1* 558 | b11111010 2 559 | b110010 3 560 | b110010 4 561 | b1110110110 5 562 | b0 6 563 | b1 7 564 | 08 565 | #102000 566 | 0! 567 | 0* 568 | #103000 569 | 1! 570 | 1* 571 | b0 7 572 | 18 573 | #104000 574 | 0! 575 | 0* 576 | #105000 577 | 1! 578 | 1* 579 | b11111010 2 580 | b110010 3 581 | b110010 4 582 | b1111101000 5 583 | b0 6 584 | b1 7 585 | 08 586 | #106000 587 | 0! 588 | 0* 589 | #107000 590 | 1! 591 | 1* 592 | b0 7 593 | 18 594 | #108000 595 | 0! 596 | 0* 597 | #109000 598 | 1! 599 | 1* 600 | b11111010 2 601 | b110010 3 602 | b110010 4 603 | b10000011010 5 604 | b0 6 605 | b1 7 606 | 08 607 | #110000 608 | 0! 609 | 0* 610 | #111000 611 | 1! 612 | 1* 613 | b0 7 614 | 18 615 | #112000 616 | 0! 617 | 0* 618 | #113000 619 | 1! 620 | 1* 621 | b11111010 2 622 | b110010 3 623 | b110010 4 624 | b10001001100 5 625 | b0 6 626 | b1 7 627 | 08 628 | #114000 629 | 0! 630 | 0* 631 | #115000 632 | 1! 633 | 1* 634 | b0 7 635 | 18 636 | #116000 637 | 0! 638 | 0* 639 | #117000 640 | 1! 641 | 1* 642 | b11111010 2 643 | b110010 3 644 | b110010 4 645 | b10001111110 5 646 | b0 6 647 | b1 7 648 | 08 649 | #118000 650 | 0! 651 | 0* 652 | #119000 653 | 1! 654 | 1* 655 | b0 7 656 | 18 657 | #120000 658 | 0! 659 | 0* 660 | #121000 661 | 1! 662 | 1* 663 | b11111010 2 664 | b110010 3 665 | b110010 4 666 | b10010110000 5 667 | b0 6 668 | b1 7 669 | 08 670 | #122000 671 | 0! 672 | 0* 673 | #123000 674 | 1! 675 | 1* 676 | b0 7 677 | 18 678 | #124000 679 | 0! 680 | 0* 681 | #125000 682 | 1! 683 | 1* 684 | b11111010 2 685 | b110010 3 686 | b110010 4 687 | b10011100010 5 688 | b0 6 689 | b1 7 690 | 08 691 | #126000 692 | 0! 693 | 0* 694 | #127000 695 | 1! 696 | 1* 697 | b0 7 698 | 18 699 | #128000 700 | 0! 701 | 0* 702 | #129000 703 | 1! 704 | 1* 705 | b11111010 2 706 | b110010 3 707 | b110010 4 708 | b10100010100 5 709 | b0 6 710 | b1 7 711 | 08 712 | #130000 713 | 0! 714 | 0* 715 | #131000 716 | 1! 717 | 1* 718 | b0 7 719 | 18 720 | #132000 721 | 0! 722 | 0* 723 | #133000 724 | 1! 725 | 1* 726 | b11111010 2 727 | b110010 3 728 | b110010 4 729 | b10101000110 5 730 | b0 6 731 | b1 7 732 | 08 733 | #134000 734 | 0! 735 | 0* 736 | #135000 737 | 1! 738 | 1* 739 | b0 7 740 | 18 741 | #136000 742 | 0! 743 | 0* 744 | #137000 745 | 1! 746 | 1* 747 | b11111010 2 748 | b110010 3 749 | b110010 4 750 | b10101111000 5 751 | b0 6 752 | b1 7 753 | 08 754 | #138000 755 | 0! 756 | 0* 757 | #139000 758 | 1! 759 | 1* 760 | b0 7 761 | 18 762 | #140000 763 | 0! 764 | 0* 765 | #141000 766 | 1! 767 | 1* 768 | b11111010 2 769 | b110010 3 770 | b110010 4 771 | b10110101010 5 772 | b0 6 773 | b1 7 774 | 08 775 | #142000 776 | 0! 777 | 0* 778 | #143000 779 | 1! 780 | 1* 781 | b0 7 782 | 18 783 | #144000 784 | 0! 785 | 0* 786 | #145000 787 | 1! 788 | 1* 789 | b11111010 2 790 | b110010 3 791 | b110010 4 792 | b10111011100 5 793 | b0 6 794 | b1 7 795 | 08 796 | #146000 797 | 0! 798 | 0* 799 | #147000 800 | 1! 801 | 1* 802 | b0 7 803 | 18 804 | #148000 805 | 0! 806 | 0* 807 | #149000 808 | 1! 809 | 1* 810 | b11111010 2 811 | b110010 3 812 | b110010 4 813 | b11000001110 5 814 | b0 6 815 | b1 7 816 | 08 817 | #150000 818 | 0! 819 | 0* 820 | #151000 821 | 1! 822 | 1* 823 | b0 7 824 | 18 825 | #152000 826 | 0! 827 | 0* 828 | #153000 829 | 1! 830 | 1* 831 | b11111010 2 832 | b110010 3 833 | b110010 4 834 | b11001000000 5 835 | b0 6 836 | b1 7 837 | 08 838 | #154000 839 | 0! 840 | 0* 841 | #155000 842 | 1! 843 | 1* 844 | b0 7 845 | 18 846 | #156000 847 | 0! 848 | 0* 849 | #157000 850 | 1! 851 | 1* 852 | b11111010 2 853 | b110010 3 854 | b110010 4 855 | b11001110010 5 856 | b0 6 857 | b1 7 858 | 08 859 | #158000 860 | 0! 861 | 0* 862 | #159000 863 | 1! 864 | 1* 865 | b0 7 866 | 18 867 | #160000 868 | 0! 869 | 0* 870 | #161000 871 | 1! 872 | 1* 873 | b11111010 2 874 | b110010 3 875 | b110010 4 876 | b11010100100 5 877 | b0 6 878 | b1 7 879 | 08 880 | #162000 881 | 0! 882 | 0* 883 | #163000 884 | 1! 885 | 1* 886 | b0 7 887 | 18 888 | #164000 889 | 0! 890 | 0* 891 | #165000 892 | 1! 893 | 1* 894 | b11111010 2 895 | b110010 3 896 | b110010 4 897 | b11011010110 5 898 | b0 6 899 | b1 7 900 | 08 901 | #166000 902 | 0! 903 | 0* 904 | #167000 905 | 1! 906 | 1* 907 | b0 7 908 | 18 909 | #168000 910 | 0! 911 | 0* 912 | #169000 913 | 1! 914 | 1* 915 | b11111010 2 916 | b110010 3 917 | b110010 4 918 | b11100001000 5 919 | b0 6 920 | b1 7 921 | 08 922 | #170000 923 | 0! 924 | 0* 925 | #171000 926 | 1! 927 | 1* 928 | b0 7 929 | 18 930 | #172000 931 | 0! 932 | 0* 933 | #173000 934 | 1! 935 | 1* 936 | b11111010 2 937 | b110010 3 938 | b110010 4 939 | b11100111010 5 940 | b0 6 941 | b1 7 942 | 08 943 | #174000 944 | 0! 945 | 0* 946 | #175000 947 | 1! 948 | 1* 949 | b0 7 950 | 18 951 | #176000 952 | 0! 953 | 0* 954 | #177000 955 | 1! 956 | 1* 957 | b11111010 2 958 | b110010 3 959 | b110010 4 960 | b11101101100 5 961 | b0 6 962 | b1 7 963 | 08 964 | #178000 965 | 0! 966 | 0* 967 | #179000 968 | 1! 969 | 1* 970 | b0 7 971 | 18 972 | #180000 973 | 0! 974 | 0* 975 | #181000 976 | 1! 977 | 1* 978 | b11111010 2 979 | b110010 3 980 | b110010 4 981 | b11110011110 5 982 | b0 6 983 | b1 7 984 | 08 985 | #182000 986 | 0! 987 | 0* 988 | #183000 989 | 1! 990 | 1* 991 | b0 7 992 | 18 993 | #184000 994 | 0! 995 | 0* 996 | #185000 997 | 1! 998 | 1* 999 | b11111010 2 1000 | b110010 3 1001 | b110010 4 1002 | b11111010000 5 1003 | b0 6 1004 | b1 7 1005 | 08 1006 | #186000 1007 | 0! 1008 | 0* 1009 | #187000 1010 | 1! 1011 | 1* 1012 | b0 7 1013 | 18 1014 | #188000 1015 | 0! 1016 | 0* 1017 | #189000 1018 | 1! 1019 | 1* 1020 | b11111010 2 1021 | b110010 3 1022 | b110010 4 1023 | b100000000010 5 1024 | b0 6 1025 | b1 7 1026 | 08 1027 | #190000 1028 | 0! 1029 | 0* 1030 | #191000 1031 | 1! 1032 | 1* 1033 | b0 7 1034 | 18 1035 | #192000 1036 | 0! 1037 | 0* 1038 | #193000 1039 | 1! 1040 | 1* 1041 | b11111010 2 1042 | b110010 3 1043 | b110010 4 1044 | b100000110100 5 1045 | b0 6 1046 | b1 7 1047 | 08 1048 | #194000 1049 | 0! 1050 | 0* 1051 | #195000 1052 | 1! 1053 | 1* 1054 | b0 7 1055 | 18 1056 | #196000 1057 | 0! 1058 | 0* 1059 | #197000 1060 | 1! 1061 | 1* 1062 | b11111010 2 1063 | b110010 3 1064 | b110010 4 1065 | b100001100110 5 1066 | b0 6 1067 | b1 7 1068 | 08 1069 | #198000 1070 | 0! 1071 | 0* 1072 | #199000 1073 | 1! 1074 | 1* 1075 | b0 7 1076 | 18 1077 | #200000 1078 | 0! 1079 | b1 $ 1080 | 0* 1081 | b1 - 1082 | #201000 1083 | 1! 1084 | 1* 1085 | b11111010 2 1086 | b110001 3 1087 | b110010 4 1088 | b100010011000 5 1089 | b0 6 1090 | b1 7 1091 | 08 1092 | #202000 1093 | 0! 1094 | 0* 1095 | #203000 1096 | 1! 1097 | 1* 1098 | b0 7 1099 | 18 1100 | #204000 1101 | 0! 1102 | 0* 1103 | #205000 1104 | 1! 1105 | b11110101 ) 1106 | 1* 1107 | b11110101 2 1108 | b110001 3 1109 | b110001 4 1110 | b100011001001 5 1111 | b0 6 1112 | b1 7 1113 | 08 1114 | #206000 1115 | 0! 1116 | 0* 1117 | #207000 1118 | 1! 1119 | 1* 1120 | b0 7 1121 | 18 1122 | #208000 1123 | 0! 1124 | 0* 1125 | #209000 1126 | 1! 1127 | 1* 1128 | b11110101 2 1129 | b110001 3 1130 | b110001 4 1131 | b100011111010 5 1132 | b0 6 1133 | b1 7 1134 | 08 1135 | #210000 1136 | 0! 1137 | 0* 1138 | #211000 1139 | 1! 1140 | 1* 1141 | b0 7 1142 | 18 1143 | #212000 1144 | 0! 1145 | 0* 1146 | #213000 1147 | 1! 1148 | 1* 1149 | b11110101 2 1150 | b110001 3 1151 | b110001 4 1152 | b100100101011 5 1153 | b0 6 1154 | b1 7 1155 | 08 1156 | #214000 1157 | 0! 1158 | 0* 1159 | #215000 1160 | 1! 1161 | 1* 1162 | b0 7 1163 | 18 1164 | #216000 1165 | 0! 1166 | 0* 1167 | #217000 1168 | 1! 1169 | 1* 1170 | b11110101 2 1171 | b110001 3 1172 | b110001 4 1173 | b100101011100 5 1174 | b0 6 1175 | b1 7 1176 | 08 1177 | #218000 1178 | 0! 1179 | 0* 1180 | #219000 1181 | 1! 1182 | 1* 1183 | b0 7 1184 | 18 1185 | #220000 1186 | 0! 1187 | 0* 1188 | #221000 1189 | 1! 1190 | 1* 1191 | b11110101 2 1192 | b110001 3 1193 | b110001 4 1194 | b100110001101 5 1195 | b0 6 1196 | b1 7 1197 | 08 1198 | #222000 1199 | 0! 1200 | 0* 1201 | #223000 1202 | 1! 1203 | 1* 1204 | b0 7 1205 | 18 1206 | #224000 1207 | 0! 1208 | 0* 1209 | #225000 1210 | 1! 1211 | 1* 1212 | b11110101 2 1213 | b110001 3 1214 | b110001 4 1215 | b100110111110 5 1216 | b0 6 1217 | b1 7 1218 | 08 1219 | #226000 1220 | 0! 1221 | 0* 1222 | #227000 1223 | 1! 1224 | 1* 1225 | b0 7 1226 | 18 1227 | #228000 1228 | 0! 1229 | 0* 1230 | #229000 1231 | 1! 1232 | 1* 1233 | b11110101 2 1234 | b110001 3 1235 | b110001 4 1236 | b100111101111 5 1237 | b0 6 1238 | b1 7 1239 | 08 1240 | #230000 1241 | 0! 1242 | 0* 1243 | #231000 1244 | 1! 1245 | 1* 1246 | b0 7 1247 | 18 1248 | #232000 1249 | 0! 1250 | 0* 1251 | #233000 1252 | 1! 1253 | 1* 1254 | b11110101 2 1255 | b110001 3 1256 | b110001 4 1257 | b101000100000 5 1258 | b0 6 1259 | b1 7 1260 | 08 1261 | #234000 1262 | 0! 1263 | 0* 1264 | #235000 1265 | 1! 1266 | 1* 1267 | b0 7 1268 | 18 1269 | #236000 1270 | 0! 1271 | 0* 1272 | #237000 1273 | 1! 1274 | 1* 1275 | b11110101 2 1276 | b110001 3 1277 | b110001 4 1278 | b101001010001 5 1279 | b0 6 1280 | b1 7 1281 | 08 1282 | #238000 1283 | 0! 1284 | 0* 1285 | #239000 1286 | 1! 1287 | 1* 1288 | b0 7 1289 | 18 1290 | #240000 1291 | 0! 1292 | 0* 1293 | #241000 1294 | 1! 1295 | 1* 1296 | b11110101 2 1297 | b110001 3 1298 | b110001 4 1299 | b101010000010 5 1300 | b0 6 1301 | b1 7 1302 | 08 1303 | #242000 1304 | 0! 1305 | 0* 1306 | #243000 1307 | 1! 1308 | 1* 1309 | b0 7 1310 | 18 1311 | #244000 1312 | 0! 1313 | 0* 1314 | #245000 1315 | 1! 1316 | 1* 1317 | b11110101 2 1318 | b110001 3 1319 | b110001 4 1320 | b101010110011 5 1321 | b0 6 1322 | b1 7 1323 | 08 1324 | #246000 1325 | 0! 1326 | 0* 1327 | #247000 1328 | 1! 1329 | 1* 1330 | b0 7 1331 | 18 1332 | #248000 1333 | 0! 1334 | 0* 1335 | #249000 1336 | 1! 1337 | 1* 1338 | b11110101 2 1339 | b110001 3 1340 | b110001 4 1341 | b101011100100 5 1342 | b0 6 1343 | b1 7 1344 | 08 1345 | #250000 1346 | 0! 1347 | 0* 1348 | #251000 1349 | 1! 1350 | 1* 1351 | b0 7 1352 | 18 1353 | #252000 1354 | 0! 1355 | 0* 1356 | #253000 1357 | 1! 1358 | 1* 1359 | b11110101 2 1360 | b110001 3 1361 | b110001 4 1362 | b101100010101 5 1363 | b0 6 1364 | b1 7 1365 | 08 1366 | #254000 1367 | 0! 1368 | 0* 1369 | #255000 1370 | 1! 1371 | 1* 1372 | b0 7 1373 | 18 1374 | #256000 1375 | 0! 1376 | 0* 1377 | #257000 1378 | 1! 1379 | 1* 1380 | b11110101 2 1381 | b110001 3 1382 | b110001 4 1383 | b101101000110 5 1384 | b0 6 1385 | b1 7 1386 | 08 1387 | #258000 1388 | 0! 1389 | 0* 1390 | #259000 1391 | 1! 1392 | 1* 1393 | b0 7 1394 | 18 1395 | #260000 1396 | 0! 1397 | 0* 1398 | #261000 1399 | 1! 1400 | 1* 1401 | b11110101 2 1402 | b110001 3 1403 | b110001 4 1404 | b101101110111 5 1405 | b0 6 1406 | b1 7 1407 | 08 1408 | #262000 1409 | 0! 1410 | 0* 1411 | #263000 1412 | 1! 1413 | 1* 1414 | b0 7 1415 | 18 1416 | #264000 1417 | 0! 1418 | 0* 1419 | #265000 1420 | 1! 1421 | 1* 1422 | b11110101 2 1423 | b110001 3 1424 | b110001 4 1425 | b101110101000 5 1426 | b0 6 1427 | b1 7 1428 | 08 1429 | #266000 1430 | 0! 1431 | 0* 1432 | #267000 1433 | 1! 1434 | 1* 1435 | b0 7 1436 | 18 1437 | #268000 1438 | 0! 1439 | 0* 1440 | #269000 1441 | 1! 1442 | 1* 1443 | b11110101 2 1444 | b110001 3 1445 | b110001 4 1446 | b101111011001 5 1447 | b0 6 1448 | b1 7 1449 | 08 1450 | #270000 1451 | 0! 1452 | 0* 1453 | #271000 1454 | 1! 1455 | 1* 1456 | b0 7 1457 | 18 1458 | #272000 1459 | 0! 1460 | 0* 1461 | #273000 1462 | 1! 1463 | 1* 1464 | b11110101 2 1465 | b110001 3 1466 | b110001 4 1467 | b110000001010 5 1468 | b0 6 1469 | b1 7 1470 | 08 1471 | #274000 1472 | 0! 1473 | 0* 1474 | #275000 1475 | 1! 1476 | 1* 1477 | b0 7 1478 | 18 1479 | #276000 1480 | 0! 1481 | 0* 1482 | #277000 1483 | 1! 1484 | 1* 1485 | b11110101 2 1486 | b110001 3 1487 | b110001 4 1488 | b110000111011 5 1489 | b0 6 1490 | b1 7 1491 | 08 1492 | #278000 1493 | 0! 1494 | 0* 1495 | #279000 1496 | 1! 1497 | 1* 1498 | b0 7 1499 | 18 1500 | #280000 1501 | 0! 1502 | 0* 1503 | #281000 1504 | 1! 1505 | 1* 1506 | b11110101 2 1507 | b110001 3 1508 | b110001 4 1509 | b110001101100 5 1510 | b0 6 1511 | b1 7 1512 | 08 1513 | #282000 1514 | 0! 1515 | 0* 1516 | #283000 1517 | 1! 1518 | 1* 1519 | b0 7 1520 | 18 1521 | #284000 1522 | 0! 1523 | 0* 1524 | #285000 1525 | 1! 1526 | 1* 1527 | b11110101 2 1528 | b110001 3 1529 | b110001 4 1530 | b110010011101 5 1531 | b0 6 1532 | b1 7 1533 | 08 1534 | #286000 1535 | 0! 1536 | 0* 1537 | #287000 1538 | 1! 1539 | 1* 1540 | b0 7 1541 | 18 1542 | #288000 1543 | 0! 1544 | 0* 1545 | #289000 1546 | 1! 1547 | 1* 1548 | b11110101 2 1549 | b110001 3 1550 | b110001 4 1551 | b110011001110 5 1552 | b0 6 1553 | b1 7 1554 | 08 1555 | #290000 1556 | 0! 1557 | 0* 1558 | #291000 1559 | 1! 1560 | 1* 1561 | b0 7 1562 | 18 1563 | #292000 1564 | 0! 1565 | 0* 1566 | #293000 1567 | 1! 1568 | 1* 1569 | b11110101 2 1570 | b110001 3 1571 | b110001 4 1572 | b110011111111 5 1573 | b0 6 1574 | b1 7 1575 | 08 1576 | #294000 1577 | 0! 1578 | 0* 1579 | #295000 1580 | 1! 1581 | 1* 1582 | b0 7 1583 | 18 1584 | #296000 1585 | 0! 1586 | 0* 1587 | #297000 1588 | 1! 1589 | 1* 1590 | b11110101 2 1591 | b110001 3 1592 | b110001 4 1593 | b110100110000 5 1594 | b0 6 1595 | b1 7 1596 | 08 1597 | #298000 1598 | 0! 1599 | 0* 1600 | #299000 1601 | 1! 1602 | 1* 1603 | b0 7 1604 | 18 1605 | #300000 1606 | 0! 1607 | 0* 1608 | #301000 1609 | 1! 1610 | 1* 1611 | b11110101 2 1612 | b110001 3 1613 | b110001 4 1614 | b110101100001 5 1615 | b0 6 1616 | b1 7 1617 | 08 1618 | #302000 1619 | 0! 1620 | 0* 1621 | #303000 1622 | 1! 1623 | 1* 1624 | b0 7 1625 | 18 1626 | #304000 1627 | 0! 1628 | 0* 1629 | #305000 1630 | 1! 1631 | 1* 1632 | b11110101 2 1633 | b110001 3 1634 | b110001 4 1635 | b110110010010 5 1636 | b0 6 1637 | b1 7 1638 | 08 1639 | #306000 1640 | 0! 1641 | 0* 1642 | #307000 1643 | 1! 1644 | 1* 1645 | b0 7 1646 | 18 1647 | #308000 1648 | 0! 1649 | 0* 1650 | #309000 1651 | 1! 1652 | 1* 1653 | b11110101 2 1654 | b110001 3 1655 | b110001 4 1656 | b110111000011 5 1657 | b0 6 1658 | b1 7 1659 | 08 1660 | #310000 1661 | 0! 1662 | 0* 1663 | #311000 1664 | 1! 1665 | 1* 1666 | b0 7 1667 | 18 1668 | #312000 1669 | 0! 1670 | 0* 1671 | #313000 1672 | 1! 1673 | 1* 1674 | b11110101 2 1675 | b110001 3 1676 | b110001 4 1677 | b110111110100 5 1678 | b0 6 1679 | b1 7 1680 | 08 1681 | #314000 1682 | 0! 1683 | 0* 1684 | #315000 1685 | 1! 1686 | 1* 1687 | b0 7 1688 | 18 1689 | #316000 1690 | 0! 1691 | 0* 1692 | #317000 1693 | 1! 1694 | 1* 1695 | b11110101 2 1696 | b110001 3 1697 | b110001 4 1698 | b111000100101 5 1699 | b0 6 1700 | b1 7 1701 | 08 1702 | #318000 1703 | 0! 1704 | 0* 1705 | #319000 1706 | 1! 1707 | 1* 1708 | b0 7 1709 | 18 1710 | #320000 1711 | 0! 1712 | 0* 1713 | #321000 1714 | 1! 1715 | 1* 1716 | b11110101 2 1717 | b110001 3 1718 | b110001 4 1719 | b111001010110 5 1720 | b0 6 1721 | b1 7 1722 | 08 1723 | #322000 1724 | 0! 1725 | 0* 1726 | #323000 1727 | 1! 1728 | 1* 1729 | b0 7 1730 | 18 1731 | #324000 1732 | 0! 1733 | 0* 1734 | #325000 1735 | 1! 1736 | 1* 1737 | b11110101 2 1738 | b110001 3 1739 | b110001 4 1740 | b111010000111 5 1741 | b0 6 1742 | b1 7 1743 | 08 1744 | #326000 1745 | 0! 1746 | 0* 1747 | #327000 1748 | 1! 1749 | 1* 1750 | b0 7 1751 | 18 1752 | #328000 1753 | 0! 1754 | 0* 1755 | #329000 1756 | 1! 1757 | 1* 1758 | b11110101 2 1759 | b110001 3 1760 | b110001 4 1761 | b111010111000 5 1762 | b0 6 1763 | b1 7 1764 | 08 1765 | #330000 1766 | 0! 1767 | 0* 1768 | #331000 1769 | 1! 1770 | 1* 1771 | b0 7 1772 | 18 1773 | #332000 1774 | 0! 1775 | 0* 1776 | #333000 1777 | 1! 1778 | 1* 1779 | b11110101 2 1780 | b110001 3 1781 | b110001 4 1782 | b111011101001 5 1783 | b0 6 1784 | b1 7 1785 | 08 1786 | #334000 1787 | 0! 1788 | 0* 1789 | #335000 1790 | 1! 1791 | 1* 1792 | b0 7 1793 | 18 1794 | #336000 1795 | 0! 1796 | 0* 1797 | #337000 1798 | 1! 1799 | 1* 1800 | b11110101 2 1801 | b110001 3 1802 | b110001 4 1803 | b111100011010 5 1804 | b0 6 1805 | b1 7 1806 | 08 1807 | #338000 1808 | 0! 1809 | 0* 1810 | #339000 1811 | 1! 1812 | 1* 1813 | b0 7 1814 | 18 1815 | #340000 1816 | 0! 1817 | 0* 1818 | #341000 1819 | 1! 1820 | 1* 1821 | b11110101 2 1822 | b110001 3 1823 | b110001 4 1824 | b111101001011 5 1825 | b0 6 1826 | b1 7 1827 | 08 1828 | #342000 1829 | 0! 1830 | 0* 1831 | #343000 1832 | 1! 1833 | 1* 1834 | b0 7 1835 | 18 1836 | #344000 1837 | 0! 1838 | 0* 1839 | #345000 1840 | 1! 1841 | 1* 1842 | b11110101 2 1843 | b110001 3 1844 | b110001 4 1845 | b111101111100 5 1846 | b0 6 1847 | b1 7 1848 | 08 1849 | #346000 1850 | 0! 1851 | 0* 1852 | #347000 1853 | 1! 1854 | 1* 1855 | b0 7 1856 | 18 1857 | #348000 1858 | 0! 1859 | 0* 1860 | #349000 1861 | 1! 1862 | 1* 1863 | b11110101 2 1864 | b110001 3 1865 | b110001 4 1866 | b111110101101 5 1867 | b0 6 1868 | b1 7 1869 | 08 1870 | #350000 1871 | 0! 1872 | 0* 1873 | #351000 1874 | 1! 1875 | 1* 1876 | b0 7 1877 | 18 1878 | #352000 1879 | 0! 1880 | 0* 1881 | #353000 1882 | 1! 1883 | 1* 1884 | b11110101 2 1885 | b110001 3 1886 | b110001 4 1887 | b111111011110 5 1888 | b0 6 1889 | b1 7 1890 | 08 1891 | #354000 1892 | 0! 1893 | 0* 1894 | #355000 1895 | 1! 1896 | 1* 1897 | b0 7 1898 | 18 1899 | #356000 1900 | 0! 1901 | 0* 1902 | #357000 1903 | 1! 1904 | 1* 1905 | b11110101 2 1906 | b110001 3 1907 | b110001 4 1908 | b1000000001111 5 1909 | b0 6 1910 | b1 7 1911 | 08 1912 | #358000 1913 | 0! 1914 | 0* 1915 | #359000 1916 | 1! 1917 | 1* 1918 | b0 7 1919 | 18 1920 | #360000 1921 | 0! 1922 | 0* 1923 | #361000 1924 | 1! 1925 | 1* 1926 | b11110101 2 1927 | b110001 3 1928 | b110001 4 1929 | b1000001000000 5 1930 | b0 6 1931 | b1 7 1932 | 08 1933 | #362000 1934 | 0! 1935 | 0* 1936 | #363000 1937 | 1! 1938 | 1* 1939 | b0 7 1940 | 18 1941 | #364000 1942 | 0! 1943 | 0* 1944 | #365000 1945 | 1! 1946 | 1* 1947 | b11110101 2 1948 | b110001 3 1949 | b110001 4 1950 | b1000001110001 5 1951 | b0 6 1952 | b1 7 1953 | 08 1954 | #366000 1955 | 0! 1956 | 0* 1957 | #367000 1958 | 1! 1959 | 1* 1960 | b0 7 1961 | 18 1962 | #368000 1963 | 0! 1964 | 0* 1965 | #369000 1966 | 1! 1967 | 1* 1968 | b11110101 2 1969 | b110001 3 1970 | b110001 4 1971 | b1000010100010 5 1972 | b0 6 1973 | b1 7 1974 | 08 1975 | #370000 1976 | 0! 1977 | 0* 1978 | #371000 1979 | 1! 1980 | 1* 1981 | b0 7 1982 | 18 1983 | #372000 1984 | 0! 1985 | 0* 1986 | #373000 1987 | 1! 1988 | 1* 1989 | b11110101 2 1990 | b110001 3 1991 | b110001 4 1992 | b1000011010011 5 1993 | b0 6 1994 | b1 7 1995 | 08 1996 | #374000 1997 | 0! 1998 | 0* 1999 | #375000 2000 | 1! 2001 | 1* 2002 | b0 7 2003 | 18 2004 | #376000 2005 | 0! 2006 | 0* 2007 | #377000 2008 | 1! 2009 | 1* 2010 | b11110101 2 2011 | b110001 3 2012 | b110001 4 2013 | b1000100000100 5 2014 | b0 6 2015 | b1 7 2016 | 08 2017 | #378000 2018 | 0! 2019 | 0* 2020 | #379000 2021 | 1! 2022 | 1* 2023 | b0 7 2024 | 18 2025 | #380000 2026 | 0! 2027 | 0* 2028 | #381000 2029 | 1! 2030 | 1* 2031 | b11110101 2 2032 | b110001 3 2033 | b110001 4 2034 | b1000100110101 5 2035 | b0 6 2036 | b1 7 2037 | 08 2038 | #382000 2039 | 0! 2040 | 0* 2041 | #383000 2042 | 1! 2043 | 1* 2044 | b0 7 2045 | 18 2046 | #384000 2047 | 0! 2048 | 0* 2049 | #385000 2050 | 1! 2051 | 1* 2052 | b11110101 2 2053 | b110001 3 2054 | b110001 4 2055 | b1000101100110 5 2056 | b0 6 2057 | b1 7 2058 | 08 2059 | #386000 2060 | 0! 2061 | 0* 2062 | #387000 2063 | 1! 2064 | 1* 2065 | b0 7 2066 | 18 2067 | #388000 2068 | 0! 2069 | 0* 2070 | #389000 2071 | 1! 2072 | 1* 2073 | b11110101 2 2074 | b110001 3 2075 | b110001 4 2076 | b1000110010111 5 2077 | b0 6 2078 | b1 7 2079 | 08 2080 | #390000 2081 | 0! 2082 | 0* 2083 | #391000 2084 | 1! 2085 | 1* 2086 | b0 7 2087 | 18 2088 | #392000 2089 | 0! 2090 | 0* 2091 | #393000 2092 | 1! 2093 | 1* 2094 | b11110101 2 2095 | b110001 3 2096 | b110001 4 2097 | b1000111001000 5 2098 | b0 6 2099 | b1 7 2100 | 08 2101 | #394000 2102 | 0! 2103 | 0* 2104 | #395000 2105 | 1! 2106 | 1* 2107 | b0 7 2108 | 18 2109 | #396000 2110 | 0! 2111 | 0* 2112 | #397000 2113 | 1! 2114 | 1* 2115 | b11110101 2 2116 | b110001 3 2117 | b110001 4 2118 | b1000111111001 5 2119 | b0 6 2120 | b1 7 2121 | 08 2122 | #398000 2123 | 0! 2124 | 0* 2125 | #399000 2126 | 1! 2127 | 1* 2128 | b0 7 2129 | 18 2130 | #400000 2131 | 0! 2132 | b101 $ 2133 | 0* 2134 | b101 - 2135 | #401000 2136 | 1! 2137 | 1* 2138 | b11110101 2 2139 | b101101 3 2140 | b110001 4 2141 | b1001000101010 5 2142 | b0 6 2143 | b1 7 2144 | 08 2145 | #402000 2146 | 0! 2147 | 0* 2148 | #403000 2149 | 1! 2150 | 1* 2151 | b0 7 2152 | 18 2153 | #404000 2154 | 0! 2155 | 0* 2156 | #405000 2157 | 1! 2158 | b11100001 ) 2159 | 1* 2160 | b11100001 2 2161 | b101101 3 2162 | b101101 4 2163 | b1001001010111 5 2164 | b0 6 2165 | b1 7 2166 | 08 2167 | #406000 2168 | 0! 2169 | 0* 2170 | #407000 2171 | 1! 2172 | 1* 2173 | b0 7 2174 | 18 2175 | #408000 2176 | 0! 2177 | 0* 2178 | #409000 2179 | 1! 2180 | 1* 2181 | b11100001 2 2182 | b101101 3 2183 | b101101 4 2184 | b1001010000100 5 2185 | b0 6 2186 | b1 7 2187 | 08 2188 | #410000 2189 | 0! 2190 | 0* 2191 | #411000 2192 | 1! 2193 | 1* 2194 | b0 7 2195 | 18 2196 | #412000 2197 | 0! 2198 | 0* 2199 | #413000 2200 | 1! 2201 | 1* 2202 | b11100001 2 2203 | b101101 3 2204 | b101101 4 2205 | b1001010110001 5 2206 | b0 6 2207 | b1 7 2208 | 08 2209 | #414000 2210 | 0! 2211 | 0* 2212 | #415000 2213 | 1! 2214 | 1* 2215 | b0 7 2216 | 18 2217 | #416000 2218 | 0! 2219 | 0* 2220 | #417000 2221 | 1! 2222 | 1* 2223 | b11100001 2 2224 | b101101 3 2225 | b101101 4 2226 | b1001011011110 5 2227 | b0 6 2228 | b1 7 2229 | 08 2230 | #418000 2231 | 0! 2232 | 0* 2233 | #419000 2234 | 1! 2235 | 1* 2236 | b0 7 2237 | 18 2238 | #420000 2239 | 0! 2240 | 0* 2241 | #421000 2242 | 1! 2243 | 1* 2244 | b11100001 2 2245 | b101101 3 2246 | b101101 4 2247 | b1001100001011 5 2248 | b0 6 2249 | b1 7 2250 | 08 2251 | #422000 2252 | 0! 2253 | 0* 2254 | #423000 2255 | 1! 2256 | 1* 2257 | b0 7 2258 | 18 2259 | #424000 2260 | 0! 2261 | 0* 2262 | #425000 2263 | 1! 2264 | 1* 2265 | b11100001 2 2266 | b101101 3 2267 | b101101 4 2268 | b1001100111000 5 2269 | b0 6 2270 | b1 7 2271 | 08 2272 | #426000 2273 | 0! 2274 | 0* 2275 | #427000 2276 | 1! 2277 | 1* 2278 | b0 7 2279 | 18 2280 | #428000 2281 | 0! 2282 | 0* 2283 | #429000 2284 | 1! 2285 | 1* 2286 | b11100001 2 2287 | b101101 3 2288 | b101101 4 2289 | b1001101100101 5 2290 | b0 6 2291 | b1 7 2292 | 08 2293 | #430000 2294 | 0! 2295 | 0* 2296 | #431000 2297 | 1! 2298 | 1* 2299 | b0 7 2300 | 18 2301 | #432000 2302 | 0! 2303 | 0* 2304 | #433000 2305 | 1! 2306 | 1* 2307 | b11100001 2 2308 | b101101 3 2309 | b101101 4 2310 | b1001110010010 5 2311 | b0 6 2312 | b1 7 2313 | 08 2314 | #434000 2315 | 0! 2316 | 0* 2317 | #435000 2318 | 1! 2319 | 1* 2320 | b0 7 2321 | 18 2322 | #436000 2323 | 0! 2324 | 0* 2325 | #437000 2326 | 1! 2327 | 1* 2328 | b11100001 2 2329 | b101101 3 2330 | b101101 4 2331 | b1001110111111 5 2332 | b0 6 2333 | b1 7 2334 | 08 2335 | #438000 2336 | 0! 2337 | 0* 2338 | #439000 2339 | 1! 2340 | 1* 2341 | b0 7 2342 | 18 2343 | #440000 2344 | 0! 2345 | 0* 2346 | #441000 2347 | 1! 2348 | 1* 2349 | b11100001 2 2350 | b101101 3 2351 | b101101 4 2352 | b1001111101100 5 2353 | b0 6 2354 | b1 7 2355 | 08 2356 | #442000 2357 | 0! 2358 | 0* 2359 | #443000 2360 | 1! 2361 | 1* 2362 | b0 7 2363 | 18 2364 | #444000 2365 | 0! 2366 | 0* 2367 | #445000 2368 | 1! 2369 | 1* 2370 | b11100001 2 2371 | b101101 3 2372 | b101101 4 2373 | b1010000011001 5 2374 | b0 6 2375 | b1 7 2376 | 08 2377 | #446000 2378 | 0! 2379 | 0* 2380 | #447000 2381 | 1! 2382 | 1* 2383 | b0 7 2384 | 18 2385 | #448000 2386 | 0! 2387 | 0* 2388 | #449000 2389 | 1! 2390 | 1* 2391 | b11100001 2 2392 | b101101 3 2393 | b101101 4 2394 | b1010001000110 5 2395 | b0 6 2396 | b1 7 2397 | 08 2398 | #450000 2399 | 0! 2400 | 0* 2401 | #451000 2402 | 1! 2403 | 1* 2404 | b0 7 2405 | 18 2406 | #452000 2407 | 0! 2408 | 0* 2409 | #453000 2410 | 1! 2411 | 1* 2412 | b11100001 2 2413 | b101101 3 2414 | b101101 4 2415 | b1010001110011 5 2416 | b0 6 2417 | b1 7 2418 | 08 2419 | #454000 2420 | 0! 2421 | 0* 2422 | #455000 2423 | 1! 2424 | 1* 2425 | b0 7 2426 | 18 2427 | #456000 2428 | 0! 2429 | 0* 2430 | #457000 2431 | 1! 2432 | 1* 2433 | b11100001 2 2434 | b101101 3 2435 | b101101 4 2436 | b1010010100000 5 2437 | b0 6 2438 | b1 7 2439 | 08 2440 | #458000 2441 | 0! 2442 | 0* 2443 | #459000 2444 | 1! 2445 | 1* 2446 | b0 7 2447 | 18 2448 | #460000 2449 | 0! 2450 | 0* 2451 | #461000 2452 | 1! 2453 | 1* 2454 | b11100001 2 2455 | b101101 3 2456 | b101101 4 2457 | b1010011001101 5 2458 | b0 6 2459 | b1 7 2460 | 08 2461 | #462000 2462 | 0! 2463 | 0* 2464 | #463000 2465 | 1! 2466 | 1* 2467 | b0 7 2468 | 18 2469 | #464000 2470 | 0! 2471 | 0* 2472 | #465000 2473 | 1! 2474 | 1* 2475 | b11100001 2 2476 | b101101 3 2477 | b101101 4 2478 | b1010011111010 5 2479 | b0 6 2480 | b1 7 2481 | 08 2482 | #466000 2483 | 0! 2484 | 0* 2485 | #467000 2486 | 1! 2487 | 1* 2488 | b0 7 2489 | 18 2490 | #468000 2491 | 0! 2492 | 0* 2493 | #469000 2494 | 1! 2495 | 1* 2496 | b11100001 2 2497 | b101101 3 2498 | b101101 4 2499 | b1010100100111 5 2500 | b0 6 2501 | b1 7 2502 | 08 2503 | #470000 2504 | 0! 2505 | 0* 2506 | #471000 2507 | 1! 2508 | 1* 2509 | b0 7 2510 | 18 2511 | #472000 2512 | 0! 2513 | 0* 2514 | #473000 2515 | 1! 2516 | 1* 2517 | b11100001 2 2518 | b101101 3 2519 | b101101 4 2520 | b1010101010100 5 2521 | b0 6 2522 | b1 7 2523 | 08 2524 | #474000 2525 | 0! 2526 | 0* 2527 | #475000 2528 | 1! 2529 | 1* 2530 | b0 7 2531 | 18 2532 | #476000 2533 | 0! 2534 | 0* 2535 | #477000 2536 | 1! 2537 | 1* 2538 | b11100001 2 2539 | b101101 3 2540 | b101101 4 2541 | b1010110000001 5 2542 | b0 6 2543 | b1 7 2544 | 08 2545 | #478000 2546 | 0! 2547 | 0* 2548 | #479000 2549 | 1! 2550 | 1* 2551 | b0 7 2552 | 18 2553 | #480000 2554 | 0! 2555 | 0* 2556 | #481000 2557 | 1! 2558 | 1* 2559 | b11100001 2 2560 | b101101 3 2561 | b101101 4 2562 | b1010110101110 5 2563 | b0 6 2564 | b1 7 2565 | 08 2566 | #482000 2567 | 0! 2568 | 0* 2569 | #483000 2570 | 1! 2571 | 1* 2572 | b0 7 2573 | 18 2574 | #484000 2575 | 0! 2576 | 0* 2577 | #485000 2578 | 1! 2579 | 1* 2580 | b11100001 2 2581 | b101101 3 2582 | b101101 4 2583 | b1010111011011 5 2584 | b0 6 2585 | b1 7 2586 | 08 2587 | #486000 2588 | 0! 2589 | 0* 2590 | #487000 2591 | 1! 2592 | 1* 2593 | b0 7 2594 | 18 2595 | #488000 2596 | 0! 2597 | 0* 2598 | #489000 2599 | 1! 2600 | 1* 2601 | b11100001 2 2602 | b101101 3 2603 | b101101 4 2604 | b1011000001000 5 2605 | b0 6 2606 | b1 7 2607 | 08 2608 | #490000 2609 | 0! 2610 | 0* 2611 | #491000 2612 | 1! 2613 | 1* 2614 | b0 7 2615 | 18 2616 | #492000 2617 | 0! 2618 | 0* 2619 | #493000 2620 | 1! 2621 | 1* 2622 | b11100001 2 2623 | b101101 3 2624 | b101101 4 2625 | b1011000110101 5 2626 | b0 6 2627 | b1 7 2628 | 08 2629 | #494000 2630 | 0! 2631 | 0* 2632 | #495000 2633 | 1! 2634 | 1* 2635 | b0 7 2636 | 18 2637 | #496000 2638 | 0! 2639 | 0* 2640 | #497000 2641 | 1! 2642 | 1* 2643 | b11100001 2 2644 | b101101 3 2645 | b101101 4 2646 | b1011001100010 5 2647 | b0 6 2648 | b1 7 2649 | 08 2650 | #498000 2651 | 0! 2652 | 0* 2653 | #499000 2654 | 1! 2655 | 1* 2656 | b0 7 2657 | 18 2658 | #500000 2659 | 0! 2660 | 0* 2661 | #501000 2662 | 1! 2663 | 1* 2664 | b11100001 2 2665 | b101101 3 2666 | b101101 4 2667 | b1011010001111 5 2668 | b0 6 2669 | b1 7 2670 | 08 2671 | #502000 2672 | 0! 2673 | 0* 2674 | #503000 2675 | 1! 2676 | 1* 2677 | b0 7 2678 | 18 2679 | #504000 2680 | 0! 2681 | 0* 2682 | #505000 2683 | 1! 2684 | 1* 2685 | b11100001 2 2686 | b101101 3 2687 | b101101 4 2688 | b1011010111100 5 2689 | b0 6 2690 | b1 7 2691 | 08 2692 | #506000 2693 | 0! 2694 | 0* 2695 | #507000 2696 | 1! 2697 | 1* 2698 | b0 7 2699 | 18 2700 | #508000 2701 | 0! 2702 | 0* 2703 | #509000 2704 | 1! 2705 | 1* 2706 | b11100001 2 2707 | b101101 3 2708 | b101101 4 2709 | b1011011101001 5 2710 | b0 6 2711 | b1 7 2712 | 08 2713 | #510000 2714 | 0! 2715 | 0* 2716 | #511000 2717 | 1! 2718 | 1* 2719 | b0 7 2720 | 18 2721 | #512000 2722 | 0! 2723 | 0* 2724 | #513000 2725 | 1! 2726 | 1* 2727 | b11100001 2 2728 | b101101 3 2729 | b101101 4 2730 | b1011100010110 5 2731 | b0 6 2732 | b1 7 2733 | 08 2734 | #514000 2735 | 0! 2736 | 0* 2737 | #515000 2738 | 1! 2739 | 1* 2740 | b0 7 2741 | 18 2742 | #516000 2743 | 0! 2744 | 0* 2745 | #517000 2746 | 1! 2747 | 1* 2748 | b11100001 2 2749 | b101101 3 2750 | b101101 4 2751 | b1011101000011 5 2752 | b0 6 2753 | b1 7 2754 | 08 2755 | #518000 2756 | 0! 2757 | 0* 2758 | #519000 2759 | 1! 2760 | 1* 2761 | b0 7 2762 | 18 2763 | #520000 2764 | 0! 2765 | 0* 2766 | #521000 2767 | 1! 2768 | 1* 2769 | b11100001 2 2770 | b101101 3 2771 | b101101 4 2772 | b1011101110000 5 2773 | b0 6 2774 | b1 7 2775 | 08 2776 | #522000 2777 | 0! 2778 | 0* 2779 | #523000 2780 | 1! 2781 | 1* 2782 | b0 7 2783 | 18 2784 | #524000 2785 | 0! 2786 | 0* 2787 | #525000 2788 | 1! 2789 | 1* 2790 | b11100001 2 2791 | b101101 3 2792 | b101101 4 2793 | b1011110011101 5 2794 | b0 6 2795 | b1 7 2796 | 08 2797 | #526000 2798 | 0! 2799 | 0* 2800 | #527000 2801 | 1! 2802 | 1* 2803 | b0 7 2804 | 18 2805 | #528000 2806 | 0! 2807 | 0* 2808 | #529000 2809 | 1! 2810 | 1* 2811 | b11100001 2 2812 | b101101 3 2813 | b101101 4 2814 | b1011111001010 5 2815 | b0 6 2816 | b1 7 2817 | 08 2818 | #530000 2819 | 0! 2820 | 0* 2821 | #531000 2822 | 1! 2823 | 1* 2824 | b0 7 2825 | 18 2826 | #532000 2827 | 0! 2828 | 0* 2829 | #533000 2830 | 1! 2831 | 1* 2832 | b11100001 2 2833 | b101101 3 2834 | b101101 4 2835 | b1011111110111 5 2836 | b0 6 2837 | b1 7 2838 | 08 2839 | #534000 2840 | 0! 2841 | 0* 2842 | #535000 2843 | 1! 2844 | 1* 2845 | b0 7 2846 | 18 2847 | #536000 2848 | 0! 2849 | 0* 2850 | #537000 2851 | 1! 2852 | 1* 2853 | b11100001 2 2854 | b101101 3 2855 | b101101 4 2856 | b1100000100100 5 2857 | b0 6 2858 | b1 7 2859 | 08 2860 | #538000 2861 | 0! 2862 | 0* 2863 | #539000 2864 | 1! 2865 | 1* 2866 | b0 7 2867 | 18 2868 | #540000 2869 | 0! 2870 | 0* 2871 | #541000 2872 | 1! 2873 | 1* 2874 | b11100001 2 2875 | b101101 3 2876 | b101101 4 2877 | b1100001010001 5 2878 | b0 6 2879 | b1 7 2880 | 08 2881 | #542000 2882 | 0! 2883 | 0* 2884 | #543000 2885 | 1! 2886 | 1* 2887 | b0 7 2888 | 18 2889 | #544000 2890 | 0! 2891 | 0* 2892 | #545000 2893 | 1! 2894 | 1* 2895 | b11100001 2 2896 | b101101 3 2897 | b101101 4 2898 | b1100001111110 5 2899 | b0 6 2900 | b1 7 2901 | 08 2902 | #546000 2903 | 0! 2904 | 0* 2905 | #547000 2906 | 1! 2907 | 1* 2908 | b0 7 2909 | 18 2910 | #548000 2911 | 0! 2912 | 0* 2913 | #549000 2914 | 1! 2915 | 1* 2916 | b11100001 2 2917 | b101101 3 2918 | b101101 4 2919 | b1100010101011 5 2920 | b0 6 2921 | b1 7 2922 | 08 2923 | #550000 2924 | 0! 2925 | 0* 2926 | #551000 2927 | 1! 2928 | 1* 2929 | b0 7 2930 | 18 2931 | #552000 2932 | 0! 2933 | 0* 2934 | #553000 2935 | 1! 2936 | 1* 2937 | b11100001 2 2938 | b101101 3 2939 | b101101 4 2940 | b1100011011000 5 2941 | b0 6 2942 | b1 7 2943 | 08 2944 | #554000 2945 | 0! 2946 | 0* 2947 | #555000 2948 | 1! 2949 | 1* 2950 | b0 7 2951 | 18 2952 | #556000 2953 | 0! 2954 | 0* 2955 | #557000 2956 | 1! 2957 | 1* 2958 | b11100001 2 2959 | b101101 3 2960 | b101101 4 2961 | b1100100000101 5 2962 | b0 6 2963 | b1 7 2964 | 08 2965 | #558000 2966 | 0! 2967 | 0* 2968 | #559000 2969 | 1! 2970 | 1* 2971 | b0 7 2972 | 18 2973 | #560000 2974 | 0! 2975 | 0* 2976 | #561000 2977 | 1! 2978 | 1* 2979 | b11100001 2 2980 | b101101 3 2981 | b101101 4 2982 | b1100100110010 5 2983 | b0 6 2984 | b1 7 2985 | 08 2986 | #562000 2987 | 0! 2988 | 0* 2989 | #563000 2990 | 1! 2991 | 1* 2992 | b0 7 2993 | 18 2994 | #564000 2995 | 0! 2996 | 0* 2997 | #565000 2998 | 1! 2999 | 1* 3000 | b11100001 2 3001 | b101101 3 3002 | b101101 4 3003 | b1100101011111 5 3004 | b0 6 3005 | b1 7 3006 | 08 3007 | #566000 3008 | 0! 3009 | 0* 3010 | #567000 3011 | 1! 3012 | 1* 3013 | b0 7 3014 | 18 3015 | #568000 3016 | 0! 3017 | 0* 3018 | #569000 3019 | 1! 3020 | 1* 3021 | b11100001 2 3022 | b101101 3 3023 | b101101 4 3024 | b1100110001100 5 3025 | b0 6 3026 | b1 7 3027 | 08 3028 | #570000 3029 | 0! 3030 | 0* 3031 | #571000 3032 | 1! 3033 | 1* 3034 | b0 7 3035 | 18 3036 | #572000 3037 | 0! 3038 | 0* 3039 | #573000 3040 | 1! 3041 | 1* 3042 | b11100001 2 3043 | b101101 3 3044 | b101101 4 3045 | b1100110111001 5 3046 | b0 6 3047 | b1 7 3048 | 08 3049 | #574000 3050 | 0! 3051 | 0* 3052 | #575000 3053 | 1! 3054 | 1* 3055 | b0 7 3056 | 18 3057 | #576000 3058 | 0! 3059 | 0* 3060 | #577000 3061 | 1! 3062 | 1* 3063 | b11100001 2 3064 | b101101 3 3065 | b101101 4 3066 | b1100111100110 5 3067 | b0 6 3068 | b1 7 3069 | 08 3070 | #578000 3071 | 0! 3072 | 0* 3073 | #579000 3074 | 1! 3075 | 1* 3076 | b0 7 3077 | 18 3078 | #580000 3079 | 0! 3080 | 0* 3081 | #581000 3082 | 1! 3083 | 1* 3084 | b11100001 2 3085 | b101101 3 3086 | b101101 4 3087 | b1101000010011 5 3088 | b0 6 3089 | b1 7 3090 | 08 3091 | #582000 3092 | 0! 3093 | 0* 3094 | #583000 3095 | 1! 3096 | 1* 3097 | b0 7 3098 | 18 3099 | #584000 3100 | 0! 3101 | 0* 3102 | #585000 3103 | 1! 3104 | 1* 3105 | b11100001 2 3106 | b101101 3 3107 | b101101 4 3108 | b1101001000000 5 3109 | b0 6 3110 | b1 7 3111 | 08 3112 | #586000 3113 | 0! 3114 | 0* 3115 | #587000 3116 | 1! 3117 | 1* 3118 | b0 7 3119 | 18 3120 | #588000 3121 | 0! 3122 | 0* 3123 | #589000 3124 | 1! 3125 | 1* 3126 | b11100001 2 3127 | b101101 3 3128 | b101101 4 3129 | b1101001101101 5 3130 | b0 6 3131 | b1 7 3132 | 08 3133 | #590000 3134 | 0! 3135 | 0* 3136 | #591000 3137 | 1! 3138 | 1* 3139 | b0 7 3140 | 18 3141 | #592000 3142 | 0! 3143 | 0* 3144 | #593000 3145 | 1! 3146 | 1* 3147 | b11100001 2 3148 | b101101 3 3149 | b101101 4 3150 | b1101010011010 5 3151 | b0 6 3152 | b1 7 3153 | 08 3154 | #594000 3155 | 0! 3156 | 0* 3157 | #595000 3158 | 1! 3159 | 1* 3160 | b0 7 3161 | 18 3162 | #596000 3163 | 0! 3164 | 0* 3165 | #597000 3166 | 1! 3167 | 1* 3168 | b11100001 2 3169 | b101101 3 3170 | b101101 4 3171 | b1101011000111 5 3172 | b0 6 3173 | b1 7 3174 | 08 3175 | #598000 3176 | 0! 3177 | 0* 3178 | #599000 3179 | 1! 3180 | 1* 3181 | b0 7 3182 | 18 3183 | #600000 3184 | 0! 3185 | b1000 $ 3186 | 0* 3187 | b1000 - 3188 | #601000 3189 | 1! 3190 | 1* 3191 | b11100001 2 3192 | b101010 3 3193 | b101101 4 3194 | b1101011110100 5 3195 | b0 6 3196 | b1 7 3197 | 08 3198 | #602000 3199 | 0! 3200 | 0* 3201 | #603000 3202 | 1! 3203 | 1* 3204 | b0 7 3205 | 18 3206 | #604000 3207 | 0! 3208 | 0* 3209 | #605000 3210 | 1! 3211 | b11010010 ) 3212 | 1* 3213 | b11010010 2 3214 | b101010 3 3215 | b101010 4 3216 | b1101100011110 5 3217 | b0 6 3218 | b1 7 3219 | 08 3220 | #606000 3221 | 0! 3222 | 0* 3223 | #607000 3224 | 1! 3225 | 1* 3226 | b0 7 3227 | 18 3228 | #608000 3229 | 0! 3230 | 0* 3231 | #609000 3232 | 1! 3233 | 1* 3234 | b11010010 2 3235 | b101010 3 3236 | b101010 4 3237 | b1101101001000 5 3238 | b0 6 3239 | b1 7 3240 | 08 3241 | #610000 3242 | 0! 3243 | 0* 3244 | #611000 3245 | 1! 3246 | 1* 3247 | b0 7 3248 | 18 3249 | #612000 3250 | 0! 3251 | 0* 3252 | #613000 3253 | 1! 3254 | 1* 3255 | b11010010 2 3256 | b101010 3 3257 | b101010 4 3258 | b1101101110010 5 3259 | b0 6 3260 | b1 7 3261 | 08 3262 | #614000 3263 | 0! 3264 | 0* 3265 | #615000 3266 | 1! 3267 | 1* 3268 | b0 7 3269 | 18 3270 | #616000 3271 | 0! 3272 | 0* 3273 | #617000 3274 | 1! 3275 | 1* 3276 | b11010010 2 3277 | b101010 3 3278 | b101010 4 3279 | b1101110011100 5 3280 | b0 6 3281 | b1 7 3282 | 08 3283 | #618000 3284 | 0! 3285 | 0* 3286 | #619000 3287 | 1! 3288 | 1* 3289 | b0 7 3290 | 18 3291 | #620000 3292 | 0! 3293 | 0* 3294 | #621000 3295 | 1! 3296 | 1* 3297 | b11010010 2 3298 | b101010 3 3299 | b101010 4 3300 | b1101111000110 5 3301 | b0 6 3302 | b1 7 3303 | 08 3304 | #622000 3305 | 0! 3306 | 0* 3307 | #623000 3308 | 1! 3309 | 1* 3310 | b0 7 3311 | 18 3312 | #624000 3313 | 0! 3314 | 0* 3315 | #625000 3316 | 1! 3317 | 1* 3318 | b11010010 2 3319 | b101010 3 3320 | b101010 4 3321 | b1101111110000 5 3322 | b0 6 3323 | b1 7 3324 | 08 3325 | #626000 3326 | 0! 3327 | 0* 3328 | #627000 3329 | 1! 3330 | 1* 3331 | b0 7 3332 | 18 3333 | #628000 3334 | 0! 3335 | 0* 3336 | #629000 3337 | 1! 3338 | 1* 3339 | b11010010 2 3340 | b101010 3 3341 | b101010 4 3342 | b1110000011010 5 3343 | b0 6 3344 | b1 7 3345 | 08 3346 | #630000 3347 | 0! 3348 | 0* 3349 | #631000 3350 | 1! 3351 | 1* 3352 | b0 7 3353 | 18 3354 | #632000 3355 | 0! 3356 | 0* 3357 | #633000 3358 | 1! 3359 | 1* 3360 | b11010010 2 3361 | b101010 3 3362 | b101010 4 3363 | b1110001000100 5 3364 | b0 6 3365 | b1 7 3366 | 08 3367 | #634000 3368 | 0! 3369 | 0* 3370 | #635000 3371 | 1! 3372 | 1* 3373 | b0 7 3374 | 18 3375 | #636000 3376 | 0! 3377 | 0* 3378 | #637000 3379 | 1! 3380 | 1* 3381 | b11010010 2 3382 | b101010 3 3383 | b101010 4 3384 | b1110001101110 5 3385 | b0 6 3386 | b1 7 3387 | 08 3388 | #638000 3389 | 0! 3390 | 0* 3391 | #639000 3392 | 1! 3393 | 1* 3394 | b0 7 3395 | 18 3396 | #640000 3397 | 0! 3398 | 0* 3399 | #641000 3400 | 1! 3401 | 1* 3402 | b11010010 2 3403 | b101010 3 3404 | b101010 4 3405 | b1110010011000 5 3406 | b0 6 3407 | b1 7 3408 | 08 3409 | #642000 3410 | 0! 3411 | 0* 3412 | #643000 3413 | 1! 3414 | 1* 3415 | b0 7 3416 | 18 3417 | #644000 3418 | 0! 3419 | 0* 3420 | #645000 3421 | 1! 3422 | 1* 3423 | b11010010 2 3424 | b101010 3 3425 | b101010 4 3426 | b1110011000010 5 3427 | b0 6 3428 | b1 7 3429 | 08 3430 | #646000 3431 | 0! 3432 | 0* 3433 | #647000 3434 | 1! 3435 | 1* 3436 | b0 7 3437 | 18 3438 | #648000 3439 | 0! 3440 | 0* 3441 | #649000 3442 | 1! 3443 | 1* 3444 | b11010010 2 3445 | b101010 3 3446 | b101010 4 3447 | b1110011101100 5 3448 | b0 6 3449 | b1 7 3450 | 08 3451 | #650000 3452 | 0! 3453 | 0* 3454 | #651000 3455 | 1! 3456 | 1* 3457 | b0 7 3458 | 18 3459 | #652000 3460 | 0! 3461 | 0* 3462 | #653000 3463 | 1! 3464 | 1* 3465 | b11010010 2 3466 | b101010 3 3467 | b101010 4 3468 | b1110100010110 5 3469 | b0 6 3470 | b1 7 3471 | 08 3472 | #654000 3473 | 0! 3474 | 0* 3475 | #655000 3476 | 1! 3477 | 1* 3478 | b0 7 3479 | 18 3480 | #656000 3481 | 0! 3482 | 0* 3483 | #657000 3484 | 1! 3485 | 1* 3486 | b11010010 2 3487 | b101010 3 3488 | b101010 4 3489 | b1110101000000 5 3490 | b0 6 3491 | b1 7 3492 | 08 3493 | #658000 3494 | 0! 3495 | 0* 3496 | #659000 3497 | 1! 3498 | 1* 3499 | b0 7 3500 | 18 3501 | #660000 3502 | 0! 3503 | 0* 3504 | #661000 3505 | 1! 3506 | 1* 3507 | b11010010 2 3508 | b101010 3 3509 | b101010 4 3510 | b1110101101010 5 3511 | b0 6 3512 | b1 7 3513 | 08 3514 | #662000 3515 | 0! 3516 | 0* 3517 | #663000 3518 | 1! 3519 | 1* 3520 | b0 7 3521 | 18 3522 | #664000 3523 | 0! 3524 | 0* 3525 | #665000 3526 | 1! 3527 | 1* 3528 | b11010010 2 3529 | b101010 3 3530 | b101010 4 3531 | b1110110010100 5 3532 | b0 6 3533 | b1 7 3534 | 08 3535 | #666000 3536 | 0! 3537 | 0* 3538 | #667000 3539 | 1! 3540 | 1* 3541 | b0 7 3542 | 18 3543 | #668000 3544 | 0! 3545 | 0* 3546 | #669000 3547 | 1! 3548 | 1* 3549 | b11010010 2 3550 | b101010 3 3551 | b101010 4 3552 | b1110110111110 5 3553 | b0 6 3554 | b1 7 3555 | 08 3556 | #670000 3557 | 0! 3558 | 0* 3559 | #671000 3560 | 1! 3561 | 1* 3562 | b0 7 3563 | 18 3564 | #672000 3565 | 0! 3566 | 0* 3567 | #673000 3568 | 1! 3569 | 1* 3570 | b11010010 2 3571 | b101010 3 3572 | b101010 4 3573 | b1110111101000 5 3574 | b0 6 3575 | b1 7 3576 | 08 3577 | #674000 3578 | 0! 3579 | 0* 3580 | #675000 3581 | 1! 3582 | 1* 3583 | b0 7 3584 | 18 3585 | #676000 3586 | 0! 3587 | 0* 3588 | #677000 3589 | 1! 3590 | 1* 3591 | b11010010 2 3592 | b101010 3 3593 | b101010 4 3594 | b1111000010010 5 3595 | b0 6 3596 | b1 7 3597 | 08 3598 | #678000 3599 | 0! 3600 | 0* 3601 | #679000 3602 | 1! 3603 | 1* 3604 | b0 7 3605 | 18 3606 | #680000 3607 | 0! 3608 | 0* 3609 | #681000 3610 | 1! 3611 | 1* 3612 | b11010010 2 3613 | b101010 3 3614 | b101010 4 3615 | b1111000111100 5 3616 | b0 6 3617 | b1 7 3618 | 08 3619 | #682000 3620 | 0! 3621 | 0* 3622 | #683000 3623 | 1! 3624 | 1* 3625 | b0 7 3626 | 18 3627 | #684000 3628 | 0! 3629 | 0* 3630 | #685000 3631 | 1! 3632 | 1* 3633 | b11010010 2 3634 | b101010 3 3635 | b101010 4 3636 | b1111001100110 5 3637 | b0 6 3638 | b1 7 3639 | 08 3640 | #686000 3641 | 0! 3642 | 0* 3643 | #687000 3644 | 1! 3645 | 1* 3646 | b0 7 3647 | 18 3648 | #688000 3649 | 0! 3650 | 0* 3651 | #689000 3652 | 1! 3653 | 1* 3654 | b11010010 2 3655 | b101010 3 3656 | b101010 4 3657 | b1111010010000 5 3658 | b0 6 3659 | b1 7 3660 | 08 3661 | #690000 3662 | 0! 3663 | 0* 3664 | #691000 3665 | 1! 3666 | 1* 3667 | b0 7 3668 | 18 3669 | #692000 3670 | 0! 3671 | 0* 3672 | #693000 3673 | 1! 3674 | 1* 3675 | b11010010 2 3676 | b101010 3 3677 | b101010 4 3678 | b1111010111010 5 3679 | b0 6 3680 | b1 7 3681 | 08 3682 | #694000 3683 | 0! 3684 | 0* 3685 | #695000 3686 | 1! 3687 | 1* 3688 | b0 7 3689 | 18 3690 | #696000 3691 | 0! 3692 | 0* 3693 | #697000 3694 | 1! 3695 | 1* 3696 | b11010010 2 3697 | b101010 3 3698 | b101010 4 3699 | b1111011100100 5 3700 | b0 6 3701 | b1 7 3702 | 08 3703 | #698000 3704 | 0! 3705 | 0* 3706 | #699000 3707 | 1! 3708 | 1* 3709 | b0 7 3710 | 18 3711 | #700000 3712 | 0! 3713 | 0* 3714 | #701000 3715 | 1! 3716 | 1* 3717 | b11010010 2 3718 | b101010 3 3719 | b101010 4 3720 | b1111100001110 5 3721 | b0 6 3722 | b1 7 3723 | 08 3724 | #702000 3725 | 0! 3726 | 0* 3727 | #703000 3728 | 1! 3729 | 1* 3730 | b0 7 3731 | 18 3732 | #704000 3733 | 0! 3734 | 0* 3735 | #705000 3736 | 1! 3737 | 1* 3738 | b11010010 2 3739 | b101010 3 3740 | b101010 4 3741 | b1111100111000 5 3742 | b0 6 3743 | b1 7 3744 | 08 3745 | #706000 3746 | 0! 3747 | 0* 3748 | #707000 3749 | 1! 3750 | 1* 3751 | b0 7 3752 | 18 3753 | #708000 3754 | 0! 3755 | 0* 3756 | #709000 3757 | 1! 3758 | 1* 3759 | b11010010 2 3760 | b101010 3 3761 | b101010 4 3762 | b1111101100010 5 3763 | b0 6 3764 | b1 7 3765 | 08 3766 | #710000 3767 | 0! 3768 | 0* 3769 | #711000 3770 | 1! 3771 | 1* 3772 | b0 7 3773 | 18 3774 | #712000 3775 | 0! 3776 | 0* 3777 | #713000 3778 | 1! 3779 | 1* 3780 | b11010010 2 3781 | b101010 3 3782 | b101010 4 3783 | b1111110001100 5 3784 | b0 6 3785 | b1 7 3786 | 08 3787 | #714000 3788 | 0! 3789 | 0* 3790 | #715000 3791 | 1! 3792 | 1* 3793 | b0 7 3794 | 18 3795 | #716000 3796 | 0! 3797 | 0* 3798 | #717000 3799 | 1! 3800 | 1* 3801 | b11010010 2 3802 | b101010 3 3803 | b101010 4 3804 | b1111110110110 5 3805 | b0 6 3806 | b1 7 3807 | 08 3808 | #718000 3809 | 0! 3810 | 0* 3811 | #719000 3812 | 1! 3813 | 1* 3814 | b0 7 3815 | 18 3816 | #720000 3817 | 0! 3818 | 0* 3819 | #721000 3820 | 1! 3821 | 1* 3822 | b11010010 2 3823 | b101010 3 3824 | b101010 4 3825 | b1111111100000 5 3826 | b0 6 3827 | b1 7 3828 | 08 3829 | #722000 3830 | 0! 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