├── .github └── workflows │ ├── ghdl-yosys.yaml │ ├── ghdl.yaml │ └── yosys.yaml ├── .gitignore ├── Dockerfile ├── FPGADesignElements ├── Makefile └── README.md ├── LICENSE ├── Makefile ├── README.md ├── helpers ├── docker_run.sh ├── getcomp.py └── ghdl.sh ├── issues.md └── xilinx ├── Makefile ├── Makeghdl ├── Makeyosys ├── README.md └── support ├── EvenSymTranspConvFIR.diff ├── OddSymTranspConvFIR.diff ├── blackboxes.v ├── blackboxes.vhd ├── fileread_endfile.diff ├── nonlrm_bufferout.diff ├── nonlrm_outbuffer.diff ├── ram_protected_sharedvar.diff ├── rams_20c.diff ├── rams_init_file.diff └── roms_1.diff /.github/workflows/ghdl-yosys.yaml: -------------------------------------------------------------------------------- 1 | name: ghdl-yosys-plugin 2 | 3 | on: 4 | push: 5 | schedule: 6 | - cron: '0 0 * * 0' 7 | 8 | jobs: 9 | 10 | synth: 11 | runs-on: ubuntu-latest 12 | steps: 13 | - uses: actions/checkout@v2 14 | - name: Build 15 | run: make build 16 | - name: Prepare 17 | run: make -C xilinx prepare 18 | - name: Verifying ghdl-yosys-plugin with examples from Xilinx 19 | run: bash helpers/docker_run.sh make -C xilinx verify-ghdl-yosys 20 | -------------------------------------------------------------------------------- /.github/workflows/ghdl.yaml: -------------------------------------------------------------------------------- 1 | name: ghdl 2 | 3 | on: 4 | push: 5 | schedule: 6 | - cron: '0 0 * * 0' 7 | 8 | jobs: 9 | 10 | synth: 11 | runs-on: ubuntu-latest 12 | steps: 13 | - uses: actions/checkout@v2 14 | - name: Build 15 | run: make build 16 | - name: Prepare 17 | run: make -C xilinx prepare 18 | - name: Verifying ghdl with examples from Xilinx 19 | run: bash helpers/docker_run.sh make -C xilinx verify-ghdl 20 | -------------------------------------------------------------------------------- /.github/workflows/yosys.yaml: -------------------------------------------------------------------------------- 1 | name: yosys 2 | 3 | on: 4 | push: 5 | schedule: 6 | - cron: '0 0 * * 0' 7 | 8 | jobs: 9 | 10 | synth: 11 | runs-on: ubuntu-latest 12 | steps: 13 | - uses: actions/checkout@v2 14 | - name: Build 15 | run: make build 16 | - name: Prepare 17 | run: make prepare 18 | - name: Verifying yosys with examples from Xilinx 19 | run: bash helpers/docker_run.sh make -C xilinx verify-yosys 20 | - name: Verifying yosys with examples from FPGADesignElements 21 | run: bash helpers/docker_run.sh make -C FPGADesignElements verify-yosys 22 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | a.out 2 | downloads 3 | examples 4 | reports 5 | temp 6 | ignore* 7 | -------------------------------------------------------------------------------- /Dockerfile: -------------------------------------------------------------------------------- 1 | ARG IMAGE="ghdl/synth:beta" 2 | 3 | FROM $IMAGE AS base 4 | 5 | RUN apt-get update -qq \ 6 | && DEBIAN_FRONTEND=noninteractive apt-get -y install --no-install-recommends \ 7 | git \ 8 | iverilog \ 9 | python3 \ 10 | python3-pip \ 11 | python3-setuptools \ 12 | verilator \ 13 | && apt-get autoclean && apt-get clean && apt-get -y autoremove \ 14 | && rm -rf /var/lib/apt/lists 15 | 16 | RUN pip3 install -e 'git+https://gitlab.com/rodrigomelo9/pyfpga#egg=pyfpga' 17 | -------------------------------------------------------------------------------- /FPGADesignElements/Makefile: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | TASK=syn 4 | 5 | all: prepare 6 | 7 | # 8 | # Prepare 9 | # 10 | 11 | prepare: 12 | git clone https://github.com/laforest/FPGADesignElements.git examples 13 | sed -i -E "s/parameter\s+ADDR_WIDTH\s*=\s*0/parameter ADDR_WIDTH = 8/g" examples/*.v 14 | sed -i -E "s/parameter\s+BINARY_WIDTH\s*=\s*0/parameter BINARY_WIDTH = 8/g" examples/*.v 15 | sed -i -E "s/parameter\s+COUNT_WIDTH\s*=\s*0/parameter COUNT_WIDTH = 8/g" examples/*.v 16 | sed -i -E "s/parameter\s+DEPTH\s*=\s*0/parameter DEPTH = 256/g" examples/*.v 17 | sed -i -E "s/parameter\s+IMPLEMENTATION\s*=\s*\"\"/parameter IMPLEMENTATION = \"MUX\"/g" examples/*.v 18 | sed -i -E "s/parameter\s+INPUT_ADDR_BASE\s*=\s*0/parameter INPUT_ADDR_BASE = 3/g" examples/*.v 19 | sed -i -E "s/parameter\s+INPUT_COUNT\s*=\s*0/parameter INPUT_COUNT = 8/g" examples/*.v 20 | sed -i -E "s/parameter\s+OUTPUT_ADDR_WIDTH\s*=\s*0/parameter OUTPUT_ADDR_WIDTH = 3/g" examples/*.v 21 | sed -i -E "s/parameter\s+OUTPUT_COUNT\s*=\s*0/parameter OUTPUT_COUNT = 8/g" examples/*.v 22 | sed -i -E "s/parameter\s+OUTPUT_WIDTH\s*=\s*0/parameter OUTPUT_WIDTH = 8/g" examples/*.v 23 | sed -i -E "s/parameter\s+PIPE_DEPTH\s*=\s*0/parameter PIPE_DEPTH = 2/g" examples/*.v 24 | sed -i -E "s/parameter\s+PULSE_LENGTH\s*=\s*0/parameter PULSE_LENGTH = 2/g" examples/*.v 25 | sed -i -E "s/parameter\s+WORD_COUNT\s*=\s*0/parameter WORD_COUNT = 2/g" examples/*.v 26 | sed -i -E "s/parameter\s+WORD_WIDTH\s*=\s*0/parameter WORD_WIDTH = 8/g" examples/*.v 27 | sed -i -E "s/parameter\s+WORD_WIDTH_A\s*=\s*0/parameter WORD_WIDTH_A = 8/g" examples/*.v 28 | sed -i -E "s/parameter\s+WORD_WIDTH_B\s*=\s*0/parameter WORD_WIDTH_B = 8/g" examples/*.v 29 | sed -i -E "s/parameter\s+WORD_WIDTH_IN\s*=\s*0/parameter WORD_WIDTH_IN = 8/g" examples/*.v 30 | sed -i -E "s/parameter\s+WORD_WIDTH_OUT\s*=\s*0/parameter WORD_WIDTH_OUT = 8/g" examples/*.v 31 | sed -i -E "s/NonExistentModuleForErrorChecking.*();//g" examples/*.v 32 | 33 | # 34 | # Collecting Verilog files 35 | # 36 | 37 | VERILOGS = $(shell find examples/ -type f -name '*.v' | sort) 38 | 39 | # Filtering Files 40 | ## Not synthesizable 41 | VERILOGS_TO_FILTER = examples/Simulation_Clock.v 42 | ## ERRORs 43 | VERILOGS_TO_FILTER += examples/Pipeline_FIFO_Buffer.v 44 | 45 | 46 | VERILOGS := $(filter-out $(VERILOGS_TO_FILTER), $(VERILOGS)) 47 | 48 | NO_OF_VERILOGS = $(words $(VERILOGS)) 49 | 50 | DEPS_TO_FILTER = \ 51 | examples/Adder_Subtractor_Binary.v \ 52 | examples/Address_Decoder_Behavioural.v \ 53 | examples/Adder_Subtractor_Binary_Saturating.v \ 54 | examples/Annuller.v \ 55 | examples/Arithmetic_Predicates_Binary.v \ 56 | examples/Binary_to_One_Hot.v \ 57 | examples/Bit_Reducer.v \ 58 | examples/Bit_Shifter.v \ 59 | examples/Bitmask_Isolate_Rightmost_1_Bit.v \ 60 | examples/Bitmask_Thermometer_to_Rightmost_1_Bit.v \ 61 | examples/CarryIn_Binary.v \ 62 | examples/CDC_Bit_Synchronizer.v \ 63 | examples/CDC_Word_Synchronizer.v \ 64 | examples/Counter_Binary.v \ 65 | examples/Debouncer_Low_Latency.v \ 66 | examples/Demultiplexer_One_Hot.v \ 67 | examples/Duty_Cycle_Generator.v \ 68 | examples/Dyadic_Boolean_Operator.v \ 69 | examples/Hamming_Distance.v \ 70 | examples/Logarithm_of_Powers_of_Two.v \ 71 | examples/Multiplexer_Binary_Behavioural.v \ 72 | examples/Multiplexer_One_Hot.v \ 73 | examples/Multiplexer_Bitwise_2to1.v \ 74 | examples/Number_of_Trailing_Zeros.v \ 75 | examples/Population_Count.v \ 76 | examples/Priority_Arbiter.v \ 77 | examples/Pulse_Divider.v \ 78 | examples/Pulse_Generator.v \ 79 | examples/Pulse_Latch.v \ 80 | examples/Register.v \ 81 | examples/Register_Toggle.v \ 82 | examples/Register_Pipeline.v \ 83 | examples/Round_Robin_Arbiter.v \ 84 | examples/Pipeline_Fork_Lazy.v \ 85 | examples/Pipeline_Merge_Round_Robin.v \ 86 | examples/Pipeline_Skid_Buffer.v \ 87 | examples/Width_Adjuster.v \ 88 | examples/Word_Reducer.v \ 89 | examples/Word_Reverser.v 90 | 91 | VERILOGS := $(filter-out $(DEPS_TO_FILTER), $(VERILOGS)) 92 | DEPS = $(addprefix -f , $(DEPS_TO_FILTER)) 93 | 94 | # 95 | # analyze 96 | # 97 | 98 | analyze: iverilog verilator 99 | 100 | iverilog: 101 | @echo "Analysing $(NO_OF_VERILOGS) files with iVerilog" 102 | @$(foreach FILE, $(VERILOGS), \ 103 | echo "* $(FILE)"; \ 104 | iverilog -Iexamples -yexamples $(FILE); \ 105 | ) 106 | @echo "DONE" 107 | 108 | verilator: 109 | @echo "Analysing $(NO_OF_VERILOGS) files with Verilator" 110 | @$(foreach FILE, $(VERILOGS), \ 111 | echo "* $(FILE)"; \ 112 | verilator --lint-only -Iexamples $(FILE); \ 113 | ) 114 | @echo "DONE" 115 | 116 | # 117 | # Synthesis with Yosys 118 | # 119 | 120 | yosys-vivado: 121 | mkdir -p reports/$@ 122 | @echo "Analysing $(NO_OF_VERILOGS) files with $@" 123 | @$(foreach FILE, $(VERILOGS), \ 124 | echo "* Analizyng $(FILE)"; \ 125 | fpga-hdl2bit --outdir temp/yosys --tool $@ --run $(TASK) $(DEPS) $(FILE) > \ 126 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 127 | ) 128 | @echo "DONE" 129 | 130 | # 131 | # Synthesis with vendor tools 132 | # 133 | 134 | ise vivado quartus: 135 | mkdir -p reports/$@ 136 | @echo "Analysing $(NO_OF_VERILOGS) files with $@" 137 | @$(foreach FILE, $(VERILOGS), \ 138 | echo "* Analizyng $(FILE)"; \ 139 | fpga-hdl2bit --outdir temp/$@ --tool $@ --run $(TASK) $(DEPS) $(FILE) > \ 140 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 141 | ) 142 | @echo "DONE" 143 | 144 | # 145 | # Report 146 | # 147 | 148 | report-errors: 149 | @$(foreach DIR,$(wildcard reports/*), \ 150 | echo "*\n* $(DIR)\n*"; \ 151 | grep -rnE "ERROR|error:" $(DIR); \ 152 | grep -rin "Aborted" $(DIR); \ 153 | ) 154 | 155 | # 156 | # Clean 157 | # 158 | 159 | clean: 160 | rm -fr a.out temp 161 | 162 | clean-all: clean 163 | rm -fr examples reports 164 | 165 | # 166 | # Verification 167 | # 168 | 169 | verify-yosys: 170 | @$(foreach FILE, $(VERILOGS), \ 171 | fpga-hdl2bit --tool yosys-vivado --run $(TASK) $(DEPS) $(FILE) || exit 1; \ 172 | ) 173 | -------------------------------------------------------------------------------- /FPGADesignElements/README.md: -------------------------------------------------------------------------------- 1 | # Yosys vs FPGA Design Elements (online book) 2 | 3 | Here, verilog examples of this online book are downloaded and synthesized/implemented with 4 | Yosys/Vivado. 5 | 6 | ## Instructions 7 | 8 | * Prepare the examples with `make` or `make prepare`. 9 | * Analyze the examples with `make analyze`, or: 10 | * `make iverilog`. 11 | * `make verilator`. 12 | * Run synthesis with `make `, where `` can be: 13 | * `yosys-vivado`: Yosis synthesis with Vivado as backend. 14 | * `ise`: synthesis with ISE (xst). 15 | * `vivado`: synthesis with Vivado. 16 | * `quartus`: synthesis with Quartus. 17 | * Report erros with `make report-erros` (there must be reports). 18 | * Remove with `make clean` and `make clean-all`. 19 | * The default operation is synthesis (`syn`) but can be changed to implementation (`imp`) using 20 | `make TASK=imp `. 21 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Copyright (c) 2019, Rodrigo A. Melo 2 | 3 | Permission to use, copy, modify, and/or distribute this software for any 4 | purpose with or without fee is hereby granted, provided that the above 5 | copyright notice and this permission notice appear in all copies. 6 | 7 | THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 8 | WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 9 | MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 10 | ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 11 | WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 12 | ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 13 | OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 14 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | build: 4 | docker build -t verifying-foss-hdl-synthesizers -f Dockerfile . 5 | 6 | prepare: 7 | make -C xilinx prepare 8 | make -C FPGADesignElements prepare 9 | 10 | verify-yosys: 11 | make -C xilinx $@ 12 | make -C FPGADesignElements $@ 13 | 14 | verify-ghdl: 15 | make -C xilinx $@ 16 | 17 | verify-ghdl-yosys: 18 | make -C xilinx $@ 19 | 20 | clean-all: 21 | make -C xilinx $@ 22 | make -C FPGADesignElements $@ 23 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Verifying FOSS HDL-synthesizers 2 | 3 | ![Yosys Verification](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers/workflows/yosys/badge.svg) 4 | ![GHDL Verification](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers/workflows/ghdl/badge.svg) 5 | ![ghdl-yosys-plugin Verification](https://github.com/rodrigomelo9/verifying-foss-hdl-synthesizers/workflows/ghdl-yosys-plugin/badge.svg) 6 | 7 | The aim of this project is to provide feedback about things supported by the vendor EDA tools, which presents [issues](issues.md) for [Yosys](https://github.com/YosysHQ/yosys), [GHDL](https://github.com/ghdl/ghdl) or [ghdl-yosys-plugin](https://github.com/ghdl/ghdl-yosys-plugin). This is performed, running the tools against several examples from different sources: 8 | * [xilinx](xilinx): Verilog and VHDL examples for ISE and Vivado, provided by Xilinx. 9 | * [FPGADesignElements](FPGADesignElements): a [online book](https://github.com/laforest/FPGADesignElements) containing a library of FPGA Verilog design modules. 10 | 11 | Firstly, the examples are checked with commercial tools such as ISE, Vivado and Quartus, to check if they are synthesizable. 12 | Secondly, they are analyzed with tools like iVerilog and GHDL to detect non-standard constructions. 13 | Then, the tools under test are employed. If an issue is detected, it is reported and the file is ignored until fixed. 14 | To simplify tools and options handling, `fpga-hdl2bit` from the [PyFPGA](https://gitlab.com/rodrigomelo9/pyfpga) project is used (when supported). 15 | 16 | A Dockerfile, based on `ghdl/synth:beta` from the [ghdl/docker](https://github.com/ghdl/docker) project (which supports the three tools under test), is provided. 17 | It is employed for the CI of the repository and can be used to run in any GNU/Linux with [Docker installed](https://docs.docker.com/install) on: 18 | * `make build` creates the needed Docker image. 19 | * `bash helpers/docker_run.sh make clean-all` to clean the generated files of a previous run. 20 | * `make prepare` downloads the examples (they are not part of the repository). 21 | * `bash helpers/docker_run.sh make verify-yosys` to verify `yosys`. 22 | * `bash helpers/docker_run.sh make verify-ghdl` to verify `ghdl --synth`. 23 | * `bash helpers/docker_run.sh make verify-ghdl-yosys` to verify `ghdl-yosys-plugin`. 24 | 25 | ## License 26 | 27 | This project is distributed under [ISC](LICENSE) license. 28 | -------------------------------------------------------------------------------- /helpers/docker_run.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | APP=${@:-/bin/bash} 4 | 5 | IMAGE=verifying-foss-hdl-synthesizers 6 | 7 | docker run --rm \ 8 | -v $HOME:$HOME -v /tmp:/tmp -v /opt:/opt \ 9 | -w $PWD $IMAGE $APP 10 | -------------------------------------------------------------------------------- /helpers/getcomp.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env python3 2 | # 3 | # Copyright (C) 2020 INTI 4 | # Copyright (C) 2020 Rodrigo A. Melo 5 | # 6 | # This program is free software: you can redistribute it and/or modify 7 | # it under the terms of the GNU General Public License as published by 8 | # the Free Software Foundation, either version 3 of the License, or 9 | # (at your option) any later version. 10 | # 11 | # This program is distributed in the hope that it will be useful, 12 | # but WITHOUT ANY WARRANTY; without even the implied warranty of 13 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 | # GNU General Public License for more details. 15 | # 16 | # You should have received a copy of the GNU General Public License 17 | # along with this program. If not, see . 18 | # 19 | """A CLI helper to get the ENTITY name.""" 20 | 21 | import argparse 22 | import re 23 | import sys 24 | 25 | 26 | parser = argparse.ArgumentParser() 27 | parser.add_argument('top') 28 | args = parser.parse_args() 29 | 30 | hdl = open(args.top, 'r').read() 31 | matches = re.findall(r'entity\s+(\w+)\s+is', hdl) 32 | if len(matches) > 0: 33 | top = matches[-1] 34 | else: 35 | sys.exit('ERROR: top-level not found.') 36 | 37 | print(top) 38 | -------------------------------------------------------------------------------- /helpers/ghdl.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | set -e 4 | 5 | STD=$1 6 | FILE=$2 7 | NAME=$3 8 | 9 | FLAGS="-fsynopsys -fexplicit -frelaxed --std=$STD" 10 | 11 | echo "# Analysis with 'ghdl -a'" 12 | ghdl -a $FLAGS $FILE 13 | echo "# Elaboration with 'ghdl -e'" 14 | ghdl -e $FLAGS $NAME 15 | echo "# Runnig with 'ghdl -r'" 16 | ghdl -r $FLAGS $NAME 17 | 18 | echo "# Synthesis with 'ghdl --synth'" 19 | ghdl --synth $FLAGS $NAME 20 | 21 | echo "# Synthesis with ghdl-yosys-plugin" 22 | YOSYS_CMD="'ghdl $FLAGS $NAME; synth_xilinx -family xc7; write_edif -pvector bra yosys.edif'" 23 | eval yosys -Q -m ghdl -p $YOSYS_CMD 24 | -------------------------------------------------------------------------------- /issues.md: -------------------------------------------------------------------------------- 1 | # Reported issues 2 | 3 | ## Yosys 4 | * [YosysHQ/yosys#1583](https://github.com/YosysHQ/yosys/issues/1583) 5 | * [YosysHQ/yosys#1670](https://github.com/YosysHQ/yosys/pull/1670) - Solved (was directly a PR) 6 | * [YosysHQ/yosys#1799](https://github.com/YosysHQ/yosys/issues/1799) 7 | * [YosysHQ/yosys#1800](https://github.com/YosysHQ/yosys/issues/1800) - Closed (non-standard feature) 8 | * [YosysHQ/yosys#1801](https://github.com/YosysHQ/yosys/issues/1801) - Closed (repeted) 9 | * See [YosysHQ/yosys#1688](https://github.com/YosysHQ/yosys/issues/1688) 10 | * [YosysHQ/yosys#1802](https://github.com/YosysHQ/yosys/issues/1802) 11 | * [YosysHQ/yosys#1807](https://github.com/YosysHQ/yosys/issues/1807) - Solved 12 | * [YosysHQ/yosys#1809](https://github.com/YosysHQ/yosys/issues/1809) 13 | * [YosysHQ/yosys#1810](https://github.com/YosysHQ/yosys/issues/1810) 14 | 15 | ## GHDL 16 | * [ghdl/ghdl#1190](https://github.com/ghdl/ghdl/issues/1190) - Solved 17 | * [ghdl/ghdl#1193](https://github.com/ghdl/ghdl/issues/1193) - Solved 18 | * [ghdl/ghdl#1197](https://github.com/ghdl/ghdl/issues/1197) - Solved 19 | * [ghdl/ghdl#1198](https://github.com/ghdl/ghdl/issues/1198) - Solved 20 | * [ghdl/ghdl#1207](https://github.com/ghdl/ghdl/issues/1207) - Solved 21 | * [ghdl/ghdl#1208](https://github.com/ghdl/ghdl/issues/1208) - Solved 22 | * [ghdl/ghdl#1209](https://github.com/ghdl/ghdl/issues/1209) - Solved 23 | * [ghdl/ghdl#1212](https://github.com/ghdl/ghdl/issues/1212) - Solved 24 | * [ghdl/ghdl#1230](https://github.com/ghdl/ghdl/issues/1230) - Solved 25 | * [ghdl/ghdl#1231](https://github.com/ghdl/ghdl/issues/1231) - Solved 26 | * [ghdl/ghdl#1238](https://github.com/ghdl/ghdl/issues/1238) - Solved 27 | * [ghdl/ghdl#1244](https://github.com/ghdl/ghdl/issues/1244) - Solved 28 | * [ghdl/ghdl#1245](https://github.com/ghdl/ghdl/issues/1245) - Closed (incorrect models) 29 | * [ghdl/ghdl#1477](https://github.com/ghdl/ghdl/issues/1477) 30 | 31 | ## ghdl-yosys-plugin 32 | * [ghdl/ghdl-yosys-plugin#95](https://github.com/ghdl/ghdl-yosys-plugin/issues/95) - Solved 33 | * [ghdl/ghdl-yosys-plugin#99](https://github.com/ghdl/ghdl-yosys-plugin/issues/99) - Closed (repeted) 34 | * [ghdl/ghdl#938](https://github.com/ghdl/ghdl/issues/938) 35 | * [ghdl/ghdl-yosys-plugin#101](https://github.com/ghdl/ghdl-yosys-plugin/issues/101) - Solved 36 | * [ghdl/ghdl-yosys-plugin#102](https://github.com/ghdl/ghdl-yosys-plugin/issues/102) - Solved 37 | * [ghdl/ghdl-yosys-plugin#109](https://github.com/ghdl/ghdl-yosys-plugin/issues/109) - Solved 38 | * [ghdl/ghdl-yosys-plugin#110](https://github.com/ghdl/ghdl-yosys-plugin/issues/110) - Solved 39 | * [ghdl/ghdl-yosys-plugin#111](https://github.com/ghdl/ghdl-yosys-plugin/issues/111) - Solved 40 | * [ghdl/ghdl-yosys-plugin#114](https://github.com/ghdl/ghdl-yosys-plugin/issues/114) 41 | 42 | ## FPGADesignElements 43 | * [laforest/FPGADesignElements#4](https://github.com/laforest/FPGADesignElements/issues/4) - Closed (but notice added) 44 | * [laforest/FPGADesignElements#5](https://github.com/laforest/FPGADesignElements/issues/5) - Solved 45 | * [laforest/FPGADesignElements#7](https://github.com/laforest/FPGADesignElements/issues/7) - Solved 46 | * [laforest/FPGADesignElements#8](https://github.com/laforest/FPGADesignElements/issues/8) - Solved 47 | 48 | ## TODO (to report) 49 | * FPGADesignElements/Pipeline_FIFO_Buffer.v 50 | -------------------------------------------------------------------------------- /xilinx/Makefile: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | TASK=syn 4 | 5 | include Makeyosys 6 | include Makeghdl 7 | 8 | all: prepare 9 | 10 | prepare: 11 | # xstug_examples.zip at disappeared in 2020 12 | #wget -P examples -c www.xilinx.com/txpatches/pub/documentation/misc/xstug_examples.zip 13 | #unzip -o -d examples examples/xstug_examples.zip 14 | #rm -fr examples/ise 15 | #mv examples/xstug_examples examples/ise 16 | wget -P examples -c www.xilinx.com/support/documentation/sw_manuals/xilinx2018_3/ug901-vivado-synthesis-examples.zip 17 | unzip -o -d examples/vivado examples/ug901-vivado-synthesis-examples.zip 18 | # diff -u ORIGINAL UPDATED > support/patch.diff 19 | @echo "Applying patches to solve errors" 20 | # Verilogs 21 | #patch examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog/EvenSymTranspConvFIR.v < support/EvenSymTranspConvFIR.diff 22 | #patch examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR_verilog/OddSymTranspConvFIR.v < support/OddSymTranspConvFIR.diff 23 | # VHDLs 24 | #patch examples/ise/VHDL_Language_Support/file_type_support/fileread_endfile.vhd < support/fileread_endfile.diff 25 | #patch examples/ise/HDL_Coding_Techniques/rams/rams_20c.vhd < support/rams_20c.diff 26 | #patch examples/ise/HDL_Coding_Techniques/rams/ram_protected_sharedvar.vhd < support/ram_protected_sharedvar.diff 27 | #patch examples/ise/VHDL_Language_Support/nonlrm_supported/nonlrm_bufferout.vhd < support/nonlrm_bufferout.diff 28 | #patch examples/ise/VHDL_Language_Support/nonlrm_supported/nonlrm_outbuffer.vhd < support/nonlrm_outbuffer.diff 29 | patch examples/vivado/rams_init_file.vhd < support/rams_init_file.diff 30 | patch examples/vivado/roms_1.vhd < support/roms_1.diff 31 | 32 | analyze: analyze-verilog analyze-vhdl 33 | 34 | report-errors: 35 | @$(foreach DIR,$(wildcard reports/*), \ 36 | echo "*\n* $(DIR)\n*"; \ 37 | grep -rnE "ERROR|error:" $(DIR); \ 38 | grep -rin "Aborted" $(DIR); \ 39 | ) 40 | 41 | clean: 42 | rm -fr a.out temp core *.edif 43 | 44 | clean-all: clean 45 | rm -fr examples reports 46 | -------------------------------------------------------------------------------- /xilinx/Makeghdl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | # 4 | # Collecting VHDL files 5 | # 6 | 7 | VHDLS = $(shell find examples/ -type f -name '*.vhd' | sort) 8 | 9 | 10 | # Filtering duplicated Files 11 | ## find -name '*.vhd' -type f -printf '%p %f\n' | sort -t ' ' -k 2,2 | uniq -f 1 --all-repeated=separate | cut -d' ' -f1 12 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/black_box/black_box_1.vhd 13 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/AddrDelay.vhd 14 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/DataDelay.vhd 15 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dynamic_shift_registers/dynamic_shift_registers_1.vhd 16 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/rams/bytewrite_ram_1b.vhd 17 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/registers/registers_1.vhd 18 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/shift_registers/shift_registers_0.vhd 19 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/shift_registers/shift_registers_1.vhd 20 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/tristates/tristates_1.vhd 21 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/tristates/tristates_2.vhd 22 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/tristates/tristates_3.vhd 23 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/combinatorial/concurrent_conditional_assignment.vhd 24 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/combinatorial/concurrent_selected_assignment.vhd 25 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/file_type_support/filewrite_explicitopen.vhd 26 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/file_type_support/filewrite_implicitopen.vhd 27 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/combinatorial/for_generate.vhd 28 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/combinatorial/for_loop.vhd 29 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/functions_procedures/function_package_1.vhd 30 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/generics/generics_1.vhd 31 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/combinatorial/if_for_generate.vhd 32 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/initial/initial_1.vhd 33 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/instantiation/instantiation_recursive.vhd 34 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/instantiation/instantiation_simple.vhd 35 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/functions_procedures/procedure_package_1.vhd 36 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/signals_variables/signal_in_process.vhd 37 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/signals_variables/variable_in_process.vhd 38 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/file_type_support/filewrite_explicitopen.vhd 39 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/file_type_support/filewrite_implicitopen.vhd 40 | # Filtering testbenches 41 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymSystFIR/EvenSymSystFIR_tb.vhd 42 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymSystFIR/TestImpulsePkg.vhd 43 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymSystFIR/TestPkg.vhd 44 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymSystFIR/TestSinePkg.vhd 45 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymSystFIR/OddSymSystFIR_tb.vhd 46 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymSystFIR/TestImpulsePkg.vhd 47 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymSystFIR/TestPkg.vhd 48 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymSystFIR/TestSinePkg.vhd 49 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/PolyDecFilter_tb.vhd 50 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/TestPkg.vhd 51 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/PolyIntrpFilter_tb.vhd 52 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/TestPkg.vhd 53 | # Filtering packages 54 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/PolyDecFilterPkg.vhd 55 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/PolyIntrpFilterPkg.vhd 56 | # Filtering included components 57 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymSystFIR/DelayLine.vhd 58 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR/DelayLine.vhd 59 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymSystFIR/DelayLine.vhd 60 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd 61 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymSystFIR/FilterStage.vhd 62 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR/FilterStage.vhd 63 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymSystFIR/FilterStage.vhd 64 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 65 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/CoefRom.vhd 66 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/DataDelay.vhd 67 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/CoefRom.vhd 68 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/DataDelay.vhd 69 | # Some descriptions of two complex design, where instantiated modules whith same name but 70 | # slightly different ports than others, were used. 71 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/DelayLine.vhd 72 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/FilterStage.vhd 73 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/PolyDecFilterPkg.vhd 74 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyDecFilter/PolyDecFilter.vhd 75 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/AddrDelay.vhd 76 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/AddrGen.vhd 77 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/CoefRom.vhd 78 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/DataDelay.vhd 79 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/DelayLine.vhd 80 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/FilterStage.vhd 81 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/PolyIntrpFilterPkg.vhd 82 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/PolyIntrpFilter.vhd 83 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/PolyIntrpFilter/SyncDelay.vhd 84 | # Not synthesizable 85 | VHDLS_TO_FILTER += examples/ise/HDL_Coding_Techniques/rams/ram_protected_sharedvar.vhd 86 | # Can't be implemented and unuseful for synthesis 87 | VHDLS_TO_FILTER += examples/vivado/black_box_1.vhd 88 | VHDLS_TO_FILTER += examples/ise/VHDL_Language_Support/asserts/asserts_1.vhd 89 | 90 | 91 | VHDLS := $(filter-out $(VHDLS_TO_FILTER), $(VHDLS)) 92 | 93 | NO_OF_VHDLS = $(words $(VHDLS)) 94 | 95 | # 96 | # ghdl analysis 97 | # 98 | 99 | GHDL_FLAGS = \ 100 | --std=08 -fsynopsys -fexplicit -frelaxed \ 101 | --warn-no-hide --warn-no-shared --warn-no-library \ 102 | -Ptemp/ghdl --workdir=temp/ghdl 103 | 104 | GETCOMP = python3 ../helpers/getcomp.py 105 | 106 | analyze-vhdl: 107 | @mkdir -p temp/ghdl 108 | ghdl -a --work=unisim $(GHDL_FLAGS) support/blackboxes.vhd 109 | #TODO: XSTUG 110 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd 111 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 112 | @echo "Checking the syntax of $(NO_OF_VHDLS) files with ghdl" 113 | @$(foreach FILE, $(VHDLS), \ 114 | echo "* $(FILE)"; \ 115 | ghdl -s $(GHDL_FLAGS) $(FILE); \ 116 | ) 117 | @echo "DONE" 118 | 119 | # 120 | # Synthesis with GHDL 121 | # 122 | 123 | # Filtering Files unsupported by the GHDL synthesis 124 | ## Filtering files with write operations 125 | TO_FILTER_IN_GHDL += examples/vivado/filewrite_explicitopen.vhd 126 | TO_FILTER_IN_GHDL += examples/vivado/filewrite_implicitopen.vhd 127 | 128 | # Files filtered with an open issue 129 | ## https://github.com/ghdl/ghdl/issues/1245 130 | TO_FILTER_IN_GHDL += examples/vivado/asym_ram_tdp_read_first.vhd 131 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/rams/rams_16a.vhd 132 | TO_FILTER_IN_GHDL += examples/vivado/rams_tdp_record.vhd 133 | TO_FILTER_IN_GHDL += examples/vivado/asym_ram_tdp_write_first.vhd 134 | ## https://github.com/ghdl/ghdl-yosys-plugin/issues/99 135 | TO_FILTER_IN_GHDL += examples/vivado/latches.vhd 136 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/latches/latches_cp.vhd 137 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/latches/latches_0.vhd 138 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/latches/latches_1.vhd 139 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/latches/latches_2.vhd 140 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/latches/latches_3.vhd 141 | TO_FILTER_IN_GHDL += examples/ise/HDL_Coding_Techniques/multiplexers/multiplexers_4.vhd 142 | ## https://github.com/ghdl/ghdl-yosys-plugin/issues/114 143 | TO_FILTER_IN_GHDL += examples/ise/FPGA_Optimization/primitive_support/primitive_2.vhd 144 | 145 | 146 | VHDLS_FOR_GHDL = $(filter-out $(TO_FILTER_IN_GHDL), $(VHDLS)) 147 | 148 | NO_OF_VHDLS_FOR_GHDL = $(words $(VHDLS_FOR_GHDL)) 149 | 150 | ghdl: 151 | @mkdir -p temp/ghdl reports/$@ 152 | ghdl -a --work=unisim $(GHDL_FLAGS) support/blackboxes.vhd 153 | # TODO: XSTUG 154 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd 155 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 156 | @echo "Analysing $(NO_OF_VHDLS_FOR_GHDL) files with ghdl --synth" 157 | @$(foreach FILE, $(VHDLS_FOR_GHDL), \ 158 | echo "* $(FILE)"; \ 159 | echo " * Analysis"; \ 160 | ghdl -a $(GHDL_FLAGS) $(FILE); \ 161 | echo " * Synthesis"; \ 162 | ghdl --synth $(GHDL_FLAGS) $(shell $(GETCOMP) $(FILE)) > \ 163 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 164 | ) 165 | @echo "DONE" 166 | 167 | ghdl-yosys: 168 | @mkdir -p temp/ghdl reports/$@ 169 | ghdl -a --work=unisim $(GHDL_FLAGS) support/blackboxes.vhd 170 | # TODO: XSTUG 171 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd 172 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 173 | @echo "Analysing $(NO_OF_VHDLS_FOR_GHDL) files with ghdl-yosys-plugin" 174 | @$(foreach FILE, $(VHDLS_FOR_GHDL), \ 175 | echo "* $(FILE)"; \ 176 | echo " * Analysis"; \ 177 | ghdl -a $(GHDL_FLAGS) $(FILE); \ 178 | echo " * Elaboration"; \ 179 | yosys -Q -m ghdl -p 'ghdl $(GHDL_FLAGS) $(shell $(GETCOMP) $(FILE)); synth_xilinx -family xc7; write_edif -pvector bra yosys.edif' > \ 180 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 181 | ) 182 | @echo "DONE" 183 | 184 | # 185 | # Synthesis with Xilinx tools 186 | # 187 | 188 | VHDL_DEPS = \ 189 | -f support/blackboxes.vhd 190 | # TODO: XSTUG 191 | # \ 192 | #-f examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd \ 193 | #-f examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 194 | 195 | 196 | # Filtering Files with ISE complains 197 | ## Shared variable needed 198 | TO_FILTER_IN_ISE += examples/vivado/asym_ram_tdp_read_first.vhd 199 | TO_FILTER_IN_ISE += examples/vivado/asym_ram_tdp_write_first.vhd 200 | TO_FILTER_IN_ISE += examples/ise/HDL_Coding_Techniques/rams/rams_16a.vhd 201 | ## The INIT value is specified with an attribute, which is rejected by XST 202 | TO_FILTER_IN_ISE += examples/ise/FPGA_Optimization/primitive_support/primitive_1.vhd 203 | ## Needs VHDL 2008 (unsupported) 204 | TO_FILTER_IN_ISE += examples/vivado/rams_sp_3d.vhd 205 | TO_FILTER_IN_ISE += examples/vivado/rams_sdp_3d.vhd 206 | ## RAM using records seems unsupported 207 | TO_FILTER_IN_ISE += examples/vivado/rams_tdp_record.vhd 208 | 209 | VHDLS_FOR_ISE = $(filter-out $(TO_FILTER_IN_ISE), $(VHDLS)) 210 | 211 | NO_OF_VHDLS_FOR_ISE = $(words $(VHDLS_FOR_ISE)) 212 | 213 | 214 | ise-vhdl: 215 | mkdir -p reports/$@ 216 | @echo "Analysing $(NO_OF_VHDLS_FOR_ISE) files with $@" 217 | @$(foreach FILE, $(VHDLS_FOR_ISE), \ 218 | echo "* Analizyng $(FILE)"; \ 219 | fpga-hdl2bit --outdir temp/$@ --tool ise --run $(TASK) $(VHDL_DEPS) $(FILE) > \ 220 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 221 | ) 222 | @echo "DONE" 223 | 224 | # Filtering Files with Vivado complains 225 | ## Unsupported Asymmetric RAM pattern 226 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2d.vhd 227 | ## illegal syntax for subtype indication 228 | TO_FILTER_IN_VIVADO += examples/vivado/rams_sp_3d.vhd 229 | TO_FILTER_IN_VIVADO += examples/vivado/rams_sdp_3d.vhd 230 | 231 | 232 | VHDLS_FOR_VIVADO = $(filter-out $(TO_FILTER_IN_VIVADO), $(VHDLS)) 233 | 234 | NO_OF_VHDLS_FOR_VIVADO = $(words $(VHDLS_FOR_VIVADO)) 235 | 236 | vivado-vhdl: 237 | mkdir -p reports/$@ 238 | @echo "Analysing $(NO_OF_VHDLS_FOR_VIVADO) files with $@" 239 | @$(foreach FILE, $(VHDLS_FOR_VIVADO), \ 240 | echo "* Analizyng $(FILE)"; \ 241 | fpga-hdl2bit --outdir temp/$@ --tool vivado --run $(TASK) $(VHDL_DEPS) $(FILE) > \ 242 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 243 | ) 244 | @echo "DONE" 245 | 246 | # 247 | # Verification 248 | # 249 | 250 | verify-ghdl: 251 | @mkdir -p temp/ghdl 252 | ghdl -a --work=unisim $(GHDL_FLAGS) support/blackboxes.vhd 253 | # TODO: XSTUG 254 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd 255 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 256 | @$(foreach FILE, $(VHDLS_FOR_GHDL), \ 257 | ghdl -a $(GHDL_FLAGS) $(FILE); \ 258 | ghdl --synth $(GHDL_FLAGS) $(shell $(GETCOMP) $(FILE)) || exit 1; \ 259 | echo "ghdl -a $(GHDL_FLAGS) $(FILE);ghdl --synth $(GHDL_FLAGS) $(shell $(GETCOMP) $(FILE)) || exit 1;"; \ 260 | ) 261 | 262 | verify-ghdl-yosys: 263 | @mkdir -p temp/ghdl 264 | ghdl -a --work=unisim $(GHDL_FLAGS) support/blackboxes.vhd 265 | # TODO: XSTUG 266 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/DelayLine.vhd 267 | #ghdl -a $(GHDL_FLAGS) examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR/FilterStage.vhd 268 | @$(foreach FILE, $(VHDLS_FOR_GHDL), \ 269 | ghdl -a $(GHDL_FLAGS) $(FILE); \ 270 | yosys -Q -m ghdl -p 'ghdl $(GHDL_FLAGS) $(shell $(GETCOMP) $(FILE)); synth_xilinx -family xc7; write_edif -pvector bra yosys.edif' || exit 1; \ 271 | ) 272 | -------------------------------------------------------------------------------- /xilinx/Makeyosys: -------------------------------------------------------------------------------- 1 | #!/usr/bin/make 2 | 3 | # 4 | # Collecting Verilog files 5 | # 6 | 7 | VERILOGS = $(shell find examples/ -type f -name '*.v' | sort) 8 | 9 | 10 | # Filtering duplicated Files 11 | ## find -name '*.v' -type f -printf '%p %f\n' | sort -t ' ' -k 2,2 | uniq -f 1 --all-repeated=separate | cut -d' ' -f1 12 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/black_box/black_box_1.v 13 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/rams/bytewrite_ram_1a.v 14 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/rams/bytewrite_ram_1b.v 15 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR_verilog/DelayLine.v 16 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR_verilog/FilterStage.v 17 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dynamic_shift_registers/dynamic_shift_registers_1.v 18 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/system_tasks/finish_ignored_1.v 19 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/system_tasks/finish_supported_1.v 20 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/functions_tasks/functions_1.v 21 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/functions_tasks/functions_constant.v 22 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/parameter/parameter_1.v 23 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/parameter/parameter_generate_for_1.v 24 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/registers/registers_1.v 25 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/shift_registers/shift_registers_0.v 26 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/shift_registers/shift_registers_1.v 27 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/functions_tasks/tasks_1.v 28 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/tristates/tristates_1.v 29 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/tristates/tristates_2.v 30 | # Filtering Files with iverilog complains 31 | ## Syntax errors in ports declarations 32 | VERILOGS_TO_FILTER += examples/vivado/xor_top.v 33 | VERILOGS_TO_FILTER += examples/vivado/sfir_even_symmetric_systolic_top.v 34 | VERILOGS_TO_FILTER += examples/vivado/sfir_shifter.v 35 | ## Is a VHDL package with stranger things 36 | VERILOGS_TO_FILTER += examples/vivado/procedure_package_1.v 37 | ## Is a zip file 38 | VERILOGS_TO_FILTER += examples/vivado/tristates_3.v 39 | ### Invalid code (missing generate statement), well solved in bytewrite_writefirst.v 40 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/rams/bytewrite_writefirst_test2.v 41 | ## 24: error: Array RAM needs an array index here. 42 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/rams/rams_25.v 43 | # Filtering Files with unsupported Yosys features 44 | ## The primitive keyword is unsupported 45 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/user_defined_primitives/udp_sequential_1.v 46 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/user_defined_primitives/udp_sequential_2.v 47 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/user_defined_primitives/udp_combinatorial_1.v 48 | ## Filtering others not synthesizable 49 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/assign_deassign/assign_deassign_good.v 50 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/assign_deassign/assign_deassign_reject_2.v 51 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/assign_deassign/assign_deassign_reject_1.v 52 | VERILOGS_TO_FILTER += examples/ise/Verilog_Language_Support/assign_deassign/assign_deassign_reject_3.v 53 | # Filtering files which are anyway analyzed because are included 54 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog/DelayLine.v 55 | VERILOGS_TO_FILTER += examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog/FilterStage.v 56 | # Filtering examples with $finish 57 | ## It is supported by all the tools (and fails) 58 | VERILOGS_TO_FILTER += examples/vivado/finish_supported_1.v 59 | ## Yosys abort and ISE/Vivado ignore it 60 | VERILOGS_TO_FILTER += examples/vivado/finish_ignored_1.v 61 | # Can't be implemented and unuseful for synthesis 62 | VERILOGS_TO_FILTER += examples/vivado/black_box_1.v 63 | 64 | 65 | VERILOGS := $(filter-out $(VERILOGS_TO_FILTER), $(VERILOGS)) 66 | 67 | NO_OF_VERILOGS = $(words $(VERILOGS)) 68 | 69 | # 70 | # iVerilog analysis 71 | # 72 | 73 | IVERILOG_EXTRA = \ 74 | support/blackboxes.v \ 75 | -yexamples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog 76 | 77 | analyze-verilog: 78 | @echo "Analysing $(NO_OF_VERILOGS) files with iVerilog" 79 | @$(foreach FILE, $(VERILOGS), \ 80 | echo "* $(FILE)"; \ 81 | iverilog $(IVERILOG_EXTRA) $(FILE); \ 82 | ) 83 | @echo "DONE" 84 | 85 | # 86 | # Synthesis with Yosys 87 | # 88 | 89 | # Filtering Files with Yosys complains 90 | ## Unsupported by Yosys and seems not standard (https://github.com/YosysHQ/yosys/issues/1800) 91 | TO_FILTER_IN_YOSYS += examples/vivado/parameter_1.v 92 | 93 | 94 | # Files filtered with an open issue 95 | ## https://github.com/YosysHQ/yosys/issues/1799 96 | TO_FILTER_IN_YOSYS += examples/vivado/functions_constant.v 97 | ## True dual-port memories are not yet supported (https://github.com/YosysHQ/yosys/issues/1802) 98 | TO_FILTER_IN_YOSYS += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2c.v 99 | TO_FILTER_IN_YOSYS += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2d.v 100 | TO_FILTER_IN_YOSYS += examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_1.v 101 | TO_FILTER_IN_YOSYS += examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_2.v 102 | TO_FILTER_IN_YOSYS += examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_3.v 103 | TO_FILTER_IN_YOSYS += examples/ise/HDL_Coding_Techniques/rams/rams_16.v 104 | TO_FILTER_IN_YOSYS += examples/vivado/bytewrite_tdp_ram_rf.v 105 | TO_FILTER_IN_YOSYS += examples/vivado/bytewrite_tdp_ram_readfirst2.v 106 | TO_FILTER_IN_YOSYS += examples/vivado/bytewrite_tdp_ram_wf.v 107 | TO_FILTER_IN_YOSYS += examples/vivado/bytewrite_tdp_ram_nc.v 108 | TO_FILTER_IN_YOSYS += examples/vivado/rams_tdp_rf_rf.v 109 | TO_FILTER_IN_YOSYS += examples/vivado/asym_ram_tdp_read_first.v 110 | ### This in particular never ends 111 | TO_FILTER_IN_YOSYS += examples/vivado/asym_ram_tdp_write_first.v 112 | 113 | 114 | VERILOGS_FOR_YOSYS = $(filter-out $(TO_FILTER_IN_YOSYS), $(VERILOGS)) 115 | 116 | NO_OF_VERILOGS_FOR_YOSYS = $(words $(VERILOGS_FOR_YOSYS)) 117 | 118 | VERILOG_DEPS = \ 119 | -f examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog/DelayLine.v \ 120 | -f examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog/FilterStage.v 121 | 122 | YOSYS_DEPS = $(VERILOG_DEPS) -f support/blackboxes.v 123 | 124 | yosys yosys-ise yosys-vivado: 125 | mkdir -p reports/$@ 126 | @echo "Analysing $(NO_OF_VERILOGS_FOR_YOSYS) files with $@" 127 | @$(foreach FILE, $(VERILOGS_FOR_YOSYS), \ 128 | echo "* Analizyng $(FILE)"; \ 129 | fpga-hdl2bit --outdir temp/$@ --tool $@ $(YOSYS_DEPS) --run $(TASK) $(FILE) > \ 130 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 131 | ) 132 | @echo "DONE" 133 | 134 | # 135 | # Synthesis with Xilinx tools 136 | # 137 | 138 | # Filtering Files with ISE complains 139 | ## Rejected by ISE: 140 | ## Mix of blocking and non-blocking assignments to variable is not a recommended coding practice. 141 | ## INFO - You can change the severity of this error message to warning using switch -change_error_to_warning "HDLCompiler:1511" 142 | TO_FILTER_IN_ISE += examples/ise/Verilog_Language_Support/rejected/blockingmix1.v 143 | TO_FILTER_IN_ISE += examples/ise/Verilog_Language_Support/rejected/blockingmix2.v 144 | ## The INIT value is specified with an attribute, which is rejected by XST 145 | TO_FILTER_IN_ISE += examples/ise/FPGA_Optimization/primitive_support/primitive_1.v 146 | 147 | 148 | VERILOGS_FOR_ISE = $(filter-out $(TO_FILTER_IN_ISE), $(VERILOGS)) 149 | 150 | NO_OF_VERILOGS_FOR_ISE = $(words $(VERILOGS_FOR_ISE)) 151 | 152 | ise-verilog: 153 | mkdir -p reports/$@ 154 | @echo "Analysing $(NO_OF_VERILOGS_FOR_ISE) files with $@" 155 | @$(foreach FILE, $(VERILOGS_FOR_ISE), \ 156 | echo "* Analizyng $(FILE)"; \ 157 | fpga-hdl2bit --outdir temp/$@ --tool ise --run $(TASK) $(VERILOG_DEPS) $(FILE) > \ 158 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 159 | ) 160 | @echo "DONE" 161 | 162 | # Filtering Files with Vivado complains 163 | ## Unsupported RAM template 164 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_3.v 165 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_1.v 166 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2d.v 167 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_3.v 168 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_4.v 169 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2c.v 170 | TO_FILTER_IN_VIVADO += examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_2.v 171 | # ISE attribute unsupported on Vivado 172 | ## CRITICAL WARNING: [Synth 8-5397] Deprecated attribute BUFFER_TYPE found on pin clk. 173 | ## Please use IO_BUFFER_TYPE or CLOCK_BUFFER_TYPE. BUFFER_TYPE will not be supported in future releases. 174 | TO_FILTER_IN_VIVADO += examples/ise/Verilog_Language_Support/attributes/vlgattrib2001_1.v 175 | 176 | 177 | VERILOGS_FOR_VIVADO = $(filter-out $(TO_FILTER_IN_VIVADO), $(VERILOGS)) 178 | 179 | NO_OF_VERILOGS_FOR_VIVADO = $(words $(VERILOGS_FOR_VIVADO)) 180 | 181 | vivado-verilog: 182 | mkdir -p reports/$@ 183 | @echo "Analysing $(NO_OF_VERILOGS_FOR_VIVADO) files with $@" 184 | @$(foreach FILE, $(VERILOGS_FOR_VIVADO), \ 185 | echo "* Analizyng $(FILE)"; \ 186 | fpga-hdl2bit --outdir temp/$@ --tool vivado --run $(TASK) $(VERILOG_DEPS) $(FILE) > \ 187 | $(addprefix reports/$@/, $(addsuffix .txt, $(notdir $(basename $(FILE))))); \ 188 | ) 189 | @echo "DONE" 190 | 191 | # 192 | # Verification 193 | # 194 | 195 | verify-yosys: 196 | @$(foreach FILE, $(VERILOGS_FOR_YOSYS), \ 197 | fpga-hdl2bit --tool yosys-vivado --run $(TASK) $(YOSYS_DEPS) $(FILE) || exit 1; \ 198 | ) 199 | -------------------------------------------------------------------------------- /xilinx/README.md: -------------------------------------------------------------------------------- 1 | # Yosys and GHDL vs the Xilinx tools (ISE/Vivado) 2 | 3 | Here, synthesizable examples for ISE and Vivado, provided by Xilinx, are downloaded, unzipped, 4 | patched (in some cases), filtered (some files with problems or duplicated are removed from the 5 | list) and synthesized/implemented with Yosys, ISE and Vivado. 6 | 7 | ## Instructions 8 | 9 | * Prepare the examples with `make` or `make prepare`. 10 | * Analyze the examples with `make analyze`, or: 11 | * `make analyze-verilog` for Verilog files. 12 | * `make analyze-vhdl` for VHDL files. 13 | * Run synthesis with `make `, where `` can be: 14 | * `yosys`: generic Yosys synthesis. 15 | * `yosys-ise`: Yosis synthesis with ISE as backend. 16 | * `yosys-vivado`: Yosis synthesis with Vivado as backend. 17 | * `ise-verilog`: synthesis with ISE (xst). 18 | * `vivado-verilog`: synthesis with Vivado. 19 | * `ghdl-synth`: generic GHDL synthesis. 20 | * `ghdl-yosys`: synthesis using the ghdl-yosys-plugin. 21 | * `ise-vhdl`: synthesis with ISE (xst). 22 | * `vivado-vhdl`: synthesis with Vivado. 23 | * Report erros with `make report-erros` (there must be reports). 24 | * Remove with `make clean` and `make clean-all`. 25 | * The default operation is synthesis (`syn`) but can be changed to implementation (`imp`) using 26 | `make TASK=imp `. 27 | 28 | ## Yosys remarks 29 | 30 | * Unsupported non-standard things in Yosys (vs ISE/Vivado): 31 | * Specification of parameters without parenthesis in module instantiation. 32 | * Use of semicolon after an `end`/`endmodule`. 33 | * Several asymmetric TDP rams which are supported by ISE are not supported by Vivado: 34 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_3.v 35 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_1.v 36 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2d.v 37 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_3.v 38 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_4.v 39 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_ram_2c.v 40 | * examples/ise/HDL_Coding_Techniques/rams/asymmetric_write_first_2.v 41 | * Yosys don't supports TDP rams with more than one write port. 42 | -------------------------------------------------------------------------------- /xilinx/support/EvenSymTranspConvFIR.diff: -------------------------------------------------------------------------------- 1 | --- ../examples/ise/HDL_Coding_Techniques/dsp/EvenSymTranspConvFIR_verilog/EvenSymTranspConvFIR.v 2010-02-17 12:09:32.000000000 -0300 2 | +++ EvenSymTranspConvFIR.v 2020-03-19 23:21:05.476342366 -0300 3 | @@ -88,7 +88,7 @@ 4 | .dout(dout_bus[i+1]) 5 | ); 6 | 7 | - end; 8 | - endgenerate; 9 | + end 10 | + endgenerate 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /xilinx/support/OddSymTranspConvFIR.diff: -------------------------------------------------------------------------------- 1 | --- ../examples/ise/HDL_Coding_Techniques/dsp/OddSymTranspConvFIR_verilog/OddSymTranspConvFIR.v 2010-02-16 12:12:32.000000000 -0300 2 | +++ OddSymTranspConvFIR.v 2020-03-19 23:21:14.720531140 -0300 3 | @@ -122,7 +122,7 @@ 4 | .dout(dout_bus[i+1]) 5 | ); 6 | 7 | - end; 8 | - endgenerate; 9 | + end 10 | + endgenerate 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /xilinx/support/blackboxes.v: -------------------------------------------------------------------------------- 1 | (* blackbox *) 2 | module LUT2 (O, I0, I1); 3 | parameter [3:0] INIT = 4'h0; 4 | output O; 5 | input I0; 6 | input I1; 7 | endmodule 8 | 9 | (* blackbox *) 10 | module FDR (Q, C, D, R); 11 | parameter [0:0] INIT = 1'b0; 12 | output Q; 13 | input C, D, R; 14 | wire Q; 15 | endmodule 16 | 17 | (* blackbox *) 18 | module FDS (Q, C, D, S); 19 | parameter [0:0] INIT = 1'b1; 20 | output Q; 21 | input C, D, S; 22 | wire Q; 23 | endmodule 24 | 25 | (* blackbox *) 26 | module FD (Q, C, D); 27 | parameter [0:0] INIT = 1'b0; 28 | output Q; 29 | input C, D; 30 | wire Q; 31 | endmodule 32 | -------------------------------------------------------------------------------- /xilinx/support/blackboxes.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.all; 3 | use IEEE.NUMERIC_STD.all; 4 | 5 | package VCOMPONENTS is 6 | 7 | attribute BOX_TYPE : string; 8 | 9 | component LUT2 10 | generic ( 11 | INIT : bit_vector := X"0" 12 | ); 13 | port ( 14 | O : out std_ulogic; 15 | I0 : in std_ulogic; 16 | I1 : in std_ulogic 17 | ); 18 | end component; 19 | attribute BOX_TYPE of LUT2 : component is "PRIMITIVE"; 20 | 21 | component FD 22 | generic ( 23 | INIT : bit := '0' 24 | ); 25 | port ( 26 | Q : out std_ulogic; 27 | C : in std_ulogic; 28 | D : in std_ulogic 29 | ); 30 | end component; 31 | attribute BOX_TYPE of FD : component is "PRIMITIVE"; 32 | 33 | end VCOMPONENTS; 34 | -------------------------------------------------------------------------------- /xilinx/support/fileread_endfile.diff: -------------------------------------------------------------------------------- 1 | --- examples/ise/VHDL_Language_Support/file_type_support/fileread_endfile.vhd 2009-10-09 10:04:52.000000000 -0300 2 | +++ support/fileread_endfile.vhd 2020-03-26 14:04:05.125727765 -0300 3 | @@ -22,7 +22,7 @@ 4 | type RamType is array(0 to 63) of bit_vector(31 downto 0); 5 | 6 | impure function InitRamFromFile (RamFileName : in string) return RamType is 7 | - FILE RamFile : text is in RamFileName; 8 | + FILE RamFile : text is RamFileName; 9 | variable RamFileLine : line; 10 | variable RAM : RamType; 11 | variable I : integer; 12 | -------------------------------------------------------------------------------- /xilinx/support/nonlrm_bufferout.diff: -------------------------------------------------------------------------------- 1 | --- examples/ise/VHDL_Language_Support/nonlrm_supported/nonlrm_bufferout.vhd 2009-10-09 14:35:42.000000000 -0300 2 | +++ support/nonlrm_bufferout.vhd 2020-04-03 16:24:21.353112426 -0300 3 | @@ -40,7 +40,7 @@ 4 | end top; 5 | 6 | architecture behavioral of top is 7 | - component sub is 8 | + component nonlrm_bufferout is 9 | port ( 10 | clk : in std_logic; 11 | A : in std_logic; 12 | @@ -48,7 +48,7 @@ 13 | O : buffer std_logic); 14 | end component; 15 | begin 16 | - isub : sub 17 | + isub : nonlrm_bufferout 18 | port map ( 19 | clk => clk, 20 | A => A, 21 | -------------------------------------------------------------------------------- /xilinx/support/nonlrm_outbuffer.diff: -------------------------------------------------------------------------------- 1 | --- examples/ise/VHDL_Language_Support/nonlrm_supported/nonlrm_outbuffer.vhd 2009-10-09 14:35:18.000000000 -0300 2 | +++ support/nonlrm_outbuffer.vhd 2020-04-03 16:24:33.433319707 -0300 3 | @@ -41,7 +41,7 @@ 4 | end top; 5 | 6 | architecture behavioral of top is 7 | - component sub is 8 | + component nonlrm_outbuffer is 9 | port ( 10 | clk : in std_logic; 11 | A : in std_logic; 12 | @@ -50,7 +50,7 @@ 13 | end component; 14 | begin 15 | 16 | - isub : sub 17 | + isub : nonlrm_outbuffer 18 | port map ( 19 | clk => clk, 20 | A => A, 21 | -------------------------------------------------------------------------------- /xilinx/support/ram_protected_sharedvar.diff: -------------------------------------------------------------------------------- 1 | --- examples/ise/HDL_Coding_Techniques/rams/ram_protected_sharedvar.vhd 2010-07-15 18:05:22.000000000 -0300 2 | +++ support/ram_protected_sharedvar.vhd 2020-03-26 14:26:13.650792563 -0300 3 | @@ -96,7 +96,7 @@ 4 | begin 5 | if rising_edge(clka) then 6 | if ENA = '1' then 7 | - doa <= myram.read(addra); 8 | + doa <= RAM.read(addra); 9 | if WEA = '1' then 10 | RAM.write(addra, dia); 11 | end if; 12 | @@ -108,7 +108,7 @@ 13 | begin 14 | if rising_edge(clkb) then 15 | if ENB = '1' then 16 | - dob <= myram.read(addrb); 17 | + dob <= RAM.read(addrb); 18 | if WEB = '1' then 19 | RAM.write(addrb, dib); 20 | end if; 21 | -------------------------------------------------------------------------------- /xilinx/support/rams_20c.diff: -------------------------------------------------------------------------------- 1 | --- examples/ise/HDL_Coding_Techniques/rams/rams_20c.vhd 2009-11-20 14:45:14.000000000 -0300 2 | +++ support/rams_20c.vhd 2020-03-26 14:04:16.453933637 -0300 3 | @@ -22,7 +22,7 @@ 4 | type RamType is array(0 to 63) of bit_vector(31 downto 0); 5 | 6 | impure function InitRamFromFile (RamFileName : in string) return RamType is 7 | - FILE RamFile : text is in RamFileName; 8 | + FILE RamFile : text is RamFileName; 9 | variable RamFileLine : line; 10 | variable RAM : RamType; 11 | begin 12 | -------------------------------------------------------------------------------- /xilinx/support/rams_init_file.diff: -------------------------------------------------------------------------------- 1 | --- examples/vivado/rams_init_file.vhd 2018-03-21 09:50:34.000000000 -0300 2 | +++ support/rams_init_file.vhd 2020-03-26 14:04:27.742138801 -0300 3 | @@ -20,7 +20,7 @@ 4 | type RamType is array (0 to 63) of bit_vector(31 downto 0); 5 | 6 | impure function InitRamFromFile(RamFileName : in string) return RamType is 7 | - FILE RamFile : text is in RamFileName; 8 | + FILE RamFile : text is RamFileName; 9 | variable RamFileLine : line; 10 | variable RAM : RamType; 11 | begin 12 | -------------------------------------------------------------------------------- /xilinx/support/roms_1.diff: -------------------------------------------------------------------------------- 1 | --- examples/vivado/roms_1.vhd 2017-01-20 14:53:54.000000000 -0300 2 | +++ support/roms_1.vhd 2020-03-26 14:05:37.087399527 -0300 3 | @@ -17,7 +17,7 @@ 4 | type rom_type is array (63 downto 0) of std_logic_vector(19 downto 0); 5 | signal ROM : rom_type := (X"0200A", X"00300", X"08101", X"04000", X"08601", X"0233A", 6 | X"00300", X"08602", X"02310", X"0203B", X"08300", X"04002", 7 | - X"08201", X"00500", X"04001", X"02500", X"00340", X"00241", X"04002", X"08300", X"08201", X"00500" X"08101", X"00602", X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021", X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B", X"00900", X"00302", X"00102", X"04002", X"00900", X"08201", X"02023", X"00303", X"02433", X"00301", X"04004" X"00301",X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",X"0030D", X"02341", X"08201", X"0400D"); 8 | + X"08201", X"00500", X"04001", X"02500", X"00340", X"00241", X"04002", X"08300", X"08201", X"00500", X"08101", X"00602", X"04003", X"0241E", X"00301", X"00102", X"02122", X"02021", X"00301", X"00102", X"02222", X"04001", X"00342", X"0232B", X"00900", X"00302", X"00102", X"04002", X"00900", X"08201", X"02023", X"00303", X"02433", X"00301", X"04004", X"00301",X"00102", X"02137", X"02036", X"00301", X"00102", X"02237",X"04004", X"00304", X"04040", X"02500", X"02500", X"02500",X"0030D", X"02341", X"08201", X"0400D"); 9 | attribute rom_style : string; 10 | attribute rom_style of ROM : signal is "block"; 11 | 12 | @@ -31,4 +31,4 @@ 13 | end if; 14 | end process; 15 | 16 | -end behavioral; 17 | \ No hay ningún carácter de nueva línea al final del fichero 18 | +end behavioral; 19 | --------------------------------------------------------------------------------