├── work ├── _vmake ├── _lib.qdb ├── _lib1_0.qpg ├── _lib1_0.qtl ├── _lib1_3.qpg ├── _lib1_3.qtl ├── _lib1_6.qdb ├── _lib1_6.qpg ├── _lib1_6.qtl └── _info ├── LAB4.pdf ├── vsim.wlf ├── README.md ├── out_answer.txt ├── mac.cr.mti ├── LICENSE ├── mac_tb.v ├── mac.v ├── pattern_in.txt ├── mac.vcd └── mac.mpf /work/_vmake: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z0 4 | cModel Technology 5 | -------------------------------------------------------------------------------- /LAB4.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/LAB4.pdf -------------------------------------------------------------------------------- /vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/vsim.wlf -------------------------------------------------------------------------------- /work/_lib.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib.qdb -------------------------------------------------------------------------------- /work/_lib1_0.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_0.qpg -------------------------------------------------------------------------------- /work/_lib1_0.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_0.qtl -------------------------------------------------------------------------------- /work/_lib1_3.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_3.qpg -------------------------------------------------------------------------------- /work/_lib1_3.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_3.qtl -------------------------------------------------------------------------------- /work/_lib1_6.qdb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_6.qdb -------------------------------------------------------------------------------- /work/_lib1_6.qpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_6.qpg -------------------------------------------------------------------------------- /work/_lib1_6.qtl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/roo16kie/MAC_Verilog/HEAD/work/_lib1_6.qtl -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # MAC_Verilog 2 | Using verilog to implement MAC (Multiply Accumulate) . Verifying it by testbench . 3 | -------------------------------------------------------------------------------- /out_answer.txt: -------------------------------------------------------------------------------- 1 | 000_0001_0101 2 | 000_0000_0111 3 | 000_0000_1000 4 | 111_1010_1101 5 | 111_1111_0001 6 | 111_1100_1111 7 | 111_1111_0010 8 | 000_0001_0000 9 | 111_1101_1100 10 | 000_0011_0111 -------------------------------------------------------------------------------- /mac.cr.mti: -------------------------------------------------------------------------------- 1 | C:/Users/user/Desktop/MAC_verilog/mac.v {2 {vlog -work work -stats=none C:/Users/user/Desktop/MAC_verilog/mac.v 2 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 3 | -- Compiling module mac 4 | ** Warning: C:/Users/user/Desktop/MAC_verilog/mac.v(13): (vlog-2600) [RDGN] - Redundant digits in numeric literal. 5 | 6 | ** Warning: C:/Users/user/Desktop/MAC_verilog/mac.v(14): (vlog-2600) [RDGN] - Redundant digits in numeric literal. 7 | 8 | ** Warning: C:/Users/user/Desktop/MAC_verilog/mac.v(15): (vlog-2600) [RDGN] - Redundant digits in numeric literal. 9 | 10 | ** Warning: C:/Users/user/Desktop/MAC_verilog/mac.v(16): (vlog-2600) [RDGN] - Redundant digits in numeric literal. 11 | 12 | 13 | Top level modules: 14 | mac 15 | 16 | } {} {}} C:/Users/user/Desktop/MAC_verilog/mac_tb.v {1 {vlog -work work -stats=none C:/Users/user/Desktop/MAC_verilog/mac_tb.v 17 | Model Technology ModelSim PE Student Edition vlog 10.4a Compiler 2015.03 Apr 7 2015 18 | -- Compiling module mac_tb 19 | 20 | Top level modules: 21 | mac_tb 22 | 23 | } {} {}} 24 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 roo16kie 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /work/_info: -------------------------------------------------------------------------------- 1 | m255 2 | K4 3 | z2 4 | 13 5 | !s112 1.1 6 | !i10d 8192 7 | !i10e 25 8 | !i10f 100 9 | cModel Technology 10 | dC:/Users/user/Desktop/pregraduate/IC training/2017/B_ICC2017_preliminary_grad_cell-based 11 | vmac 12 | Z0 !s110 1550412914 13 | !i10b 1 14 | !s100 1jLUfj4g98bUdc9eHW8@62 15 | I`e7Ll?YU`O7NgFF@>PZPn0 16 | Z1 VDg1SIo80bB@j0V0VzS_@n1 17 | Z2 dC:/Users/user/Desktop/MAC_verilog 18 | w1550412910 19 | 8C:/Users/user/Desktop/MAC_verilog/mac.v 20 | FC:/Users/user/Desktop/MAC_verilog/mac.v 21 | L0 1 22 | Z3 OP;L;10.4a;61 23 | r1 24 | !s85 0 25 | 31 26 | Z4 !s108 1550412914.000000 27 | !s107 C:/Users/user/Desktop/MAC_verilog/mac.v| 28 | !s90 -reportprogress|300|-work|work|-stats=none|C:/Users/user/Desktop/MAC_verilog/mac.v| 29 | !s101 -O0 30 | !i113 1 31 | Z5 o-work work -L mtiAvm -L mtiRnm -L mtiOvm -L mtiUvm -L mtiUPF -L infact -O0 32 | vmac_tb 33 | R0 34 | !i10b 1 35 | !s100 W6BnfYQRC`l`P_XAeGeda0 36 | IZ:AH<;_j0S1J^abTHTVe00 37 | R1 38 | R2 39 | w1547786811 40 | 8C:/Users/user/Desktop/MAC_verilog/mac_tb.v 41 | FC:/Users/user/Desktop/MAC_verilog/mac_tb.v 42 | L0 8 43 | R3 44 | r1 45 | !s85 0 46 | 31 47 | R4 48 | !s107 C:/Users/user/Desktop/MAC_verilog/mac_tb.v| 49 | !s90 -reportprogress|300|-work|work|-stats=none|C:/Users/user/Desktop/MAC_verilog/mac_tb.v| 50 | !s101 -O0 51 | !i113 1 52 | R5 53 | -------------------------------------------------------------------------------- /mac_tb.v: -------------------------------------------------------------------------------- 1 | 2 | `define DATA_NUM 249 3 | `define CYCLE 10 4 | `define PATTERN "pattern_in.txt" 5 | `define EXPECT "out_answer.txt" 6 | `timescale 1ns/10ps 7 | 8 | module mac_tb ; 9 | 10 | reg [3:0] in_a ,in_b ; 11 | reg in_valid_a,in_valid_b; 12 | reg clk,reset ; 13 | reg [3:0]count; 14 | wire [10:0] mac_out ; 15 | 16 | wire out_valid ; 17 | 18 | reg [9:0]pattern_in[0:`DATA_NUM-1] ; 19 | 20 | reg [10:0]ans[0:9] ; 21 | 22 | /* 23 | reg out_valid_exp ; 24 | 25 | reg [10:0] mac_out_exp ; */ 26 | 27 | mac u_mac ( .mac_out(mac_out), 28 | .out_valid(out_valid), 29 | .in_a(in_a), 30 | .in_b(in_b), 31 | .in_valid_a(in_valid_a), 32 | .in_valid_b(in_valid_b), 33 | .clk(clk), 34 | .reset(reset) 35 | ) ; 36 | 37 | always begin #(`CYCLE/2) clk=~clk ; end //clock generation 38 | 39 | initial begin 40 | $readmemb(`PATTERN,pattern_in) ; 41 | $readmemb(`EXPECT,ans) ; 42 | end 43 | 44 | 45 | integer i ,err ,check; 46 | 47 | initial begin 48 | clk=1'b0 ; 49 | err=0 ; 50 | check=0; 51 | count=0; 52 | @(negedge clk) reset=1'b1 ; 53 | #(`CYCLE*2) reset=1'b0 ; 54 | 55 | @(negedge clk) ; 56 | 57 | for(i=0;i<`DATA_NUM;i=i+1) begin 58 | {in_a,in_b,in_valid_a,in_valid_b}=pattern_in[i] ; 59 | // {mac_out_exp,out_valid_exp}=ans[i] ; 60 | @(negedge clk) ; 61 | //@(posedge clk) ; 62 | if(out_valid) 63 | begin 64 | 65 | if(mac_out==ans[count]) 66 | 67 | check=check+1; 68 | 69 | else begin 70 | err=err+1; 71 | $display($time,"Error at in_a=%b, in_b=%b, in_valid_a=%b, in_valid_b=%b",in_a,in_b,in_valid_a,in_valid_b) ; 72 | $display($time,"Expect : mac_out=%b",ans[count]) ; 73 | $display($time,"Your ans : mac_out=%b\n\n",mac_out) ; 74 | end 75 | count = count+1; 76 | end 77 | end 78 | end 79 | 80 | 81 | initial 82 | begin 83 | $dumpfile("mac.vcd"); 84 | $dumpvars; 85 | end 86 | 87 | 88 | initial begin 89 | 90 | #(`CYCLE*255) ; 91 | if(err==0&&check==10) 92 | begin 93 | $display("------------------- mac check successfully -------------------"); 94 | $display(" $$ "); 95 | $display(" $ $"); 96 | $display(" $ $"); 97 | $display(" $ $"); 98 | $display(" $ $"); 99 | $display("$$$$$$$$$ $$$$$$$$"); 100 | $display("$$$$$$$ $"); 101 | $display("$$$$$$$ $"); 102 | $display("$$$$$$$ $"); 103 | $display("$$$$$$$ $"); 104 | $display("$$$$$$$ $"); 105 | $display("$$$$$$$$$$$$ $$"); 106 | $display("$$$$$ $$$$$$$$$$"); 107 | end 108 | else if((err==0)&&(check!=10)) begin 109 | $display("----------- Oops! Something wrong with your code! ------------"); 110 | end 111 | else $display("------------------- There are %d errors -------------------", err); 112 | 113 | $finish ; 114 | 115 | end 116 | 117 | endmodule 118 | 119 | 120 | 121 | 122 | -------------------------------------------------------------------------------- /mac.v: -------------------------------------------------------------------------------- 1 | module mac(in_a, in_b, in_valid_a, in_valid_b, clk, 2 | reset, mac_out, out_valid); 3 | 4 | //input output declartion 5 | input signed [3:0] in_a, in_b; 6 | input in_valid_a, in_valid_b; 7 | input clk, reset; 8 | output reg signed [10:0] mac_out; 9 | output reg out_valid; 10 | 11 | 12 | ////////////////////////////////////////////////////////////////////////// 13 | parameter IDLE = 2'b000 ; 14 | parameter WAIT_A = 2'b001 ; 15 | parameter WAIT_B = 2'b010 ; 16 | parameter MAC = 2'b011 ; 17 | 18 | reg out_sig ; 19 | reg [3:0] counter ; 20 | reg [1:0] state_Next , state ; 21 | reg signed [3:0] reg_a , reg_b ; 22 | reg signed [10:0] reg_c , temp_out; 23 | 24 | always@(negedge clk) 25 | begin 26 | if(reset) 27 | counter <= 4'd0 ; 28 | else if(counter==4'd8) 29 | if(in_valid_a&in_valid_b) 30 | counter <= 4'd1 ; 31 | else 32 | counter <= 4'd0 ; 33 | else if(state==MAC) 34 | counter <= counter + 4'd1 ; 35 | end 36 | 37 | always@(posedge clk ) 38 | begin 39 | if(reset) 40 | state <= IDLE ; 41 | else 42 | state <= state_Next ; 43 | end 44 | 45 | always@(*) 46 | begin 47 | case(state) 48 | IDLE : if(in_valid_a&in_valid_b) 49 | state_Next = MAC ; 50 | else if(in_valid_a) 51 | state_Next = WAIT_B ; 52 | else if(in_valid_b) 53 | state_Next = WAIT_A ; 54 | else state_Next = IDLE ; 55 | 56 | WAIT_A : if(in_valid_a) 57 | state_Next = MAC ; 58 | else state_Next = WAIT_A ; 59 | 60 | WAIT_B : if(in_valid_b) 61 | state_Next = MAC ; 62 | else state_Next = WAIT_B ; 63 | 64 | MAC : if(in_valid_a&in_valid_b) 65 | state_Next = MAC ; 66 | else if(in_valid_a) 67 | state_Next = WAIT_B ; 68 | else if(in_valid_b) 69 | state_Next = WAIT_A ; 70 | else state_Next = IDLE ; 71 | default : state_Next = IDLE ; 72 | endcase 73 | end 74 | 75 | always@(posedge clk) 76 | begin 77 | if(in_valid_a) 78 | reg_a <= in_a ; 79 | end 80 | 81 | always@(posedge clk) 82 | begin 83 | if(in_valid_b) 84 | reg_b <= in_b ; 85 | end 86 | 87 | always@(negedge clk) 88 | begin 89 | if(reset) 90 | reg_c <= 11'd0 ; 91 | else if(counter==4'd8) 92 | if(in_valid_a&in_valid_b) 93 | reg_c <= reg_a*reg_b ; 94 | else 95 | reg_c <= 11'd0 ; 96 | else if(state==MAC) 97 | reg_c <= reg_c + (reg_a*reg_b) ; 98 | 99 | end 100 | 101 | always@(posedge clk) 102 | begin 103 | if(counter>=4'd1&&counter<=4'd8) 104 | temp_out <= reg_c ; 105 | end 106 | 107 | always@(posedge clk) 108 | begin 109 | if(counter==4'd8) 110 | out_sig <= 1 ; 111 | else 112 | out_sig <= 0 ; 113 | end 114 | 115 | always@(posedge clk) 116 | begin 117 | if(out_sig) 118 | out_valid <= 1 ; 119 | else 120 | out_valid <= 0 ; 121 | end 122 | 123 | always@(posedge clk) 124 | begin 125 | if(out_sig) 126 | mac_out <= temp_out ; 127 | 128 | end 129 | 130 | endmodule -------------------------------------------------------------------------------- /pattern_in.txt: -------------------------------------------------------------------------------- 1 | 0110_0001_0_0 2 | 1001_0001_0_1 3 | 1110_0010_0_0 4 | 0010_0100_0_0 5 | 1010_0110_1_0 6 | 0100_0000_0_1 7 | 1001_0111_1_0 8 | 1100_0010_0_0 9 | 0010_0100_0_0 10 | 0111_0011_1_1 11 | 0010_0010_1_1 12 | 0010_0100_0_0 13 | 0011_0001_0_0 14 | 0001_0100_0_0 15 | 1010_0101_0_0 16 | 0011_0101_1_0 17 | 0011_0000_0_1 18 | 0100_0011_1_0 19 | 0011_0100_0_1 20 | 1111_1111_1_0 21 | 1111_0000_0_1 22 | 0011_0011_0_0 23 | 0100_0100_0_0 24 | 0111_0111_0_1 25 | 1110_0001_1_0 26 | 0000_1111_1_1 27 | 0010_0110_0_0 28 | 0101_1111_0_1 29 | 1000_0111_1_0 30 | 1001_0011_0_0 31 | 0011_0000_0_0 32 | 0100_0011_1_0 33 | 1011_1111_0_0 34 | 1110_1111_0_0 35 | 1110_0001_0_1 36 | 1010_0010_0_0 37 | 1110_0000_1_0 38 | 0001_0011_0_1 39 | 0111_0011_0_0 40 | 0010_0000_0_0 41 | 1010_0110_0_1 42 | 1011_0101_1_0 43 | 0010_0000_0_0 44 | 0110_0010_0_0 45 | 0101_0101_1_1 46 | 0110_0011_0_1 47 | 0010_0100_1_0 48 | 1010_0110_0_1 49 | 0000_0111_1_0 50 | 0101_0110_1_1 51 | 0111_0000_0_0 52 | 1000_0110_0_0 53 | 0100_0011_0_0 54 | 0010_0000_0_0 55 | 1110_1111_0_0 56 | 1000_0010_0_0 57 | 1110_0111_0_0 58 | 1101_0101_0_0 59 | 0111_0001_0_0 60 | 1100_1111_0_1 61 | 1101_0010_1_0 62 | 0000_0100_0_0 63 | 1101_0101_0_0 64 | 0011_0011_1_1 65 | 1100_0100_0_1 66 | 1001_1111_1_0 67 | 0101_0000_0_0 68 | 0011_0011_0_0 69 | 1100_0101_0_0 70 | 0110_1111_0_0 71 | 0001_0111_0_0 72 | 0010_0100_1_1 73 | 0101_0100_1_1 74 | 1001_0111_0_0 75 | 1010_0011_1_0 76 | 1001_0110_0_0 77 | 0011_0100_0_0 78 | 0101_0011_0_1 79 | 1100_0101_0_0 80 | 1100_0100_1_1 81 | 1011_0010_1_0 82 | 1111_0001_0_0 83 | 1110_0111_0_0 84 | 1011_0000_0_0 85 | 0011_0100_0_1 86 | 0100_0011_0_1 87 | 0000_0101_1_0 88 | 1000_0111_1_1 89 | 1011_0111_0_0 90 | 0100_0001_0_0 91 | 0100_0001_0_1 92 | 0110_0001_0_0 93 | 1100_0011_0_0 94 | 1000_0001_0_0 95 | 1110_0110_0_0 96 | 0010_0100_1_0 97 | 1011_0001_0_1 98 | 0111_0010_1_0 99 | 1110_0010_0_1 100 | 0001_0111_1_0 101 | 1111_0010_0_1 102 | 0101_0101_1_0 103 | 0101_0111_0_0 104 | 1100_0001_0_0 105 | 1111_0011_0_0 106 | 1101_0001_0_0 107 | 1001_0001_0_0 108 | 0110_0100_0_0 109 | 0000_0100_0_1 110 | 0111_0000_0_0 111 | 0011_0101_0_0 112 | 1001_0011_1_0 113 | 0100_0010_1_1 114 | 0110_0101_1_1 115 | 0000_0000_0_0 116 | 1010_0110_1_0 117 | 0101_0111_0_1 118 | 0110_0000_1_1 119 | 0010_0000_1_1 120 | 1101_0010_0_1 121 | 1000_0100_1_0 122 | 1111_0010_1_0 123 | 1111_0011_0_0 124 | 1001_0011_0_0 125 | 1100_0010_0_1 126 | 0000_0000_0_0 127 | 1011_0010_0_0 128 | 1001_0110_1_0 129 | 0111_1111_0_1 130 | 0011_0011_0_0 131 | 0010_0011_0_1 132 | 1000_0010_1_0 133 | 0001_1111_1_0 134 | 1110_0110_0_0 135 | 0110_0111_0_1 136 | 1111_0111_0_0 137 | 1101_0001_0_0 138 | 0011_0001_0_0 139 | 0111_1111_0_1 140 | 1111_0000_1_0 141 | 1001_0101_0_0 142 | 0000_0101_0_0 143 | 1010_0111_0_1 144 | 1001_0101_0_0 145 | 0110_0010_0_0 146 | 1100_0010_1_0 147 | 1100_0010_1_1 148 | 0000_0010_1_1 149 | 1001_0000_1_1 150 | 0001_0110_0_0 151 | 1110_0110_0_0 152 | 1101_0010_0_0 153 | 1100_1111_0_1 154 | 1101_0011_1_0 155 | 1101_0111_1_0 156 | 0111_1111_0_0 157 | 1000_0110_0_1 158 | 1111_0110_1_1 159 | 1001_0110_0_1 160 | 0010_0110_1_0 161 | 1010_0010_1_0 162 | 1011_0100_0_1 163 | 0110_0111_1_0 164 | 0101_0011_0_1 165 | 1010_0000_1_0 166 | 0011_0001_0_1 167 | 0110_1111_0_1 168 | 1100_0000_1_0 169 | 0100_0011_0_1 170 | 0010_0101_1_0 171 | 0110_0101_0_1 172 | 0101_0110_1_0 173 | 0101_0011_0_0 174 | 1110_0010_0_0 175 | 1110_0101_0_0 176 | 0101_0110_1_1 177 | 1011_0001_0_0 178 | 1101_0110_1_1 179 | 1000_0110_1_1 180 | 1110_0010_0_1 181 | 1100_0101_1_0 182 | 0111_0010_0_0 183 | 0110_0000_1_0 184 | 1011_0011_0_0 185 | 1010_0101_0_1 186 | 0110_0010_0_0 187 | 0000_0000_1_0 188 | 0010_0011_0_0 189 | 0001_0100_0_1 190 | 0110_0101_0_0 191 | 0101_0000_1_0 192 | 1011_0010_0_0 193 | 1101_0001_0_1 194 | 0000_0100_0_1 195 | 0110_0011_0_0 196 | 1000_0010_1_0 197 | 1100_0111_0_0 198 | 0000_0000_0_0 199 | 0010_0011_1_0 200 | 0011_0101_0_1 201 | 0010_0110_1_0 202 | 1111_0111_0_1 203 | 1010_0110_0_0 204 | 1010_0011_1_1 205 | 0111_0111_0_1 206 | 1001_0100_1_0 207 | 0101_0001_0_0 208 | 0000_0110_0_0 209 | 1111_1111_0_0 210 | 0000_0101_0_1 211 | 0111_0100_1_0 212 | 1101_0000_0_0 213 | 1101_0011_0_0 214 | 1011_0101_0_0 215 | 0110_0000_0_1 216 | 1000_0100_1_0 217 | 0001_0100_1_1 218 | 0110_0010_1_1 219 | 0110_0101_0_1 220 | 0110_0100_1_0 221 | 1100_1111_0_0 222 | 1111_0101_0_0 223 | 1111_0110_0_0 224 | 1101_0000_1_1 225 | 0011_0010_1_0 226 | 1001_1111_0_0 227 | 1000_0001_0_0 228 | 1110_1111_0_1 229 | 1110_0111_0_0 230 | 1001_0010_1_0 231 | 0000_0010_0_1 232 | 0011_0101_1_1 233 | 1110_0011_0_1 234 | 0111_0000_0_0 235 | 0101_1111_1_0 236 | 0011_0011_0_0 237 | 1011_0101_0_0 238 | 0000_0100_1_0 239 | 0011_0010_0_0 240 | 0101_0011_0_1 241 | 0000_0000_0_0 242 | 0000_0000_0_0 243 | 0000_0000_0_0 244 | 0000_0000_0_0 245 | 0000_0000_0_0 246 | 0000_0000_0_0 247 | 0000_0000_0_0 248 | 0000_0000_0_0 249 | 0000_0000_0_0 -------------------------------------------------------------------------------- /mac.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun Feb 17 22:15:20 2019 3 | $end 4 | $version 5 | ModelSim Version 10.4a 6 | $end 7 | $timescale 8 | 10ps 9 | $end 10 | 11 | $scope module mac_tb $end 12 | $var reg 4 ! in_a [3:0] $end 13 | $var reg 4 " in_b [3:0] $end 14 | $var reg 1 # in_valid_a $end 15 | $var reg 1 $ in_valid_b $end 16 | $var reg 1 % clk $end 17 | $var reg 1 & reset $end 18 | $var reg 4 ' count [3:0] $end 19 | $var wire 1 ( mac_out [10] $end 20 | $var wire 1 ) mac_out [9] $end 21 | $var wire 1 * mac_out [8] $end 22 | $var wire 1 + mac_out [7] $end 23 | $var wire 1 , mac_out [6] $end 24 | $var wire 1 - mac_out [5] $end 25 | $var wire 1 . mac_out [4] $end 26 | $var wire 1 / mac_out [3] $end 27 | $var wire 1 0 mac_out [2] $end 28 | $var wire 1 1 mac_out [1] $end 29 | $var wire 1 2 mac_out [0] $end 30 | $var wire 1 3 out_valid $end 31 | $var integer 32 4 i $end 32 | $var integer 32 5 err $end 33 | $var integer 32 6 check $end 34 | 35 | $scope module u_mac $end 36 | $var parameter 2 7 IDLE $end 37 | $var parameter 2 8 WAIT_A $end 38 | $var parameter 2 9 WAIT_B $end 39 | $var parameter 2 : MAC $end 40 | $var wire 1 ; in_a [3] $end 41 | $var wire 1 < in_a [2] $end 42 | $var wire 1 = in_a [1] $end 43 | $var wire 1 > in_a [0] $end 44 | $var wire 1 ? in_b [3] $end 45 | $var wire 1 @ in_b [2] $end 46 | $var wire 1 A in_b [1] $end 47 | $var wire 1 B in_b [0] $end 48 | $var wire 1 C in_valid_a $end 49 | $var wire 1 D in_valid_b $end 50 | $var wire 1 E clk $end 51 | $var wire 1 F reset $end 52 | $var reg 11 G mac_out [10:0] $end 53 | $var reg 1 H out_valid $end 54 | $var reg 1 I out_sig $end 55 | $var reg 4 J counter [3:0] $end 56 | $var reg 2 K state_Next [1:0] $end 57 | $var reg 2 L state [1:0] $end 58 | $var reg 4 M reg_a [3:0] $end 59 | $var reg 4 N reg_b [3:0] $end 60 | $var reg 11 O reg_c [10:0] $end 61 | $var reg 11 P temp_out [10:0] $end 62 | $upscope $end 63 | $upscope $end 64 | $enddefinitions $end 65 | #0 66 | $dumpvars 67 | bx ! 68 | bx " 69 | x# 70 | x$ 71 | 0% 72 | x& 73 | b0 ' 74 | bx G 75 | xH 76 | xI 77 | bx J 78 | bx K 79 | bx L 80 | bx M 81 | bx N 82 | bx O 83 | bx P 84 | b0 7 85 | b1 8 86 | b10 9 87 | b11 : 88 | bx 4 89 | b0 5 90 | b0 6 91 | x2 92 | x1 93 | x0 94 | x/ 95 | x. 96 | x- 97 | x, 98 | x+ 99 | x* 100 | x) 101 | x( 102 | x3 103 | xF 104 | 0E 105 | xD 106 | xC 107 | xB 108 | xA 109 | x@ 110 | x? 111 | x> 112 | x= 113 | x< 114 | x; 115 | $end 116 | #500 117 | 1% 118 | 1E 119 | 0I 120 | 0H 121 | 03 122 | #1000 123 | 0% 124 | 0E 125 | 1& 126 | 1F 127 | #1500 128 | 1% 129 | 1E 130 | b0 L 131 | b0 K 132 | #2000 133 | 0% 134 | 0E 135 | b0 J 136 | b0 O 137 | #2500 138 | 1% 139 | 1E 140 | #3000 141 | 0& 142 | 0% 143 | 0F 144 | 0E 145 | b0 4 146 | 0$ 147 | 0# 148 | b1 " 149 | b110 ! 150 | 0> 151 | 1= 152 | 1< 153 | 0; 154 | 1B 155 | 0A 156 | 0@ 157 | 0? 158 | 0D 159 | 0C 160 | #3500 161 | 1% 162 | 1E 163 | #4000 164 | 0% 165 | 0E 166 | b1 4 167 | 1$ 168 | b1001 ! 169 | 1> 170 | 0= 171 | 0< 172 | 1; 173 | 1D 174 | b1 K 175 | #4500 176 | 1% 177 | 1E 178 | b1 L 179 | b1 N 180 | #5000 181 | 0% 182 | 0E 183 | b10 4 184 | 0$ 185 | b10 " 186 | b1110 ! 187 | 0> 188 | 1= 189 | 1< 190 | 0B 191 | 1A 192 | 0D 193 | #5500 194 | 1% 195 | 1E 196 | #6000 197 | 0% 198 | 0E 199 | b11 4 200 | b100 " 201 | b10 ! 202 | 0< 203 | 0; 204 | 0A 205 | 1@ 206 | #6500 207 | 1% 208 | 1E 209 | #7000 210 | 0% 211 | 0E 212 | b100 4 213 | 1# 214 | b110 " 215 | b1010 ! 216 | 1; 217 | 1A 218 | 1C 219 | b11 K 220 | #7500 221 | 1% 222 | 1E 223 | b11 L 224 | b1010 M 225 | b10 K 226 | #8000 227 | 0% 228 | 0E 229 | b101 4 230 | 1$ 231 | 0# 232 | b0 " 233 | b100 ! 234 | 0= 235 | 1< 236 | 0; 237 | 0A 238 | 0@ 239 | 1D 240 | 0C 241 | b1 K 242 | b1 J 243 | b11111111010 O 244 | #8500 245 | 1% 246 | 1E 247 | b1 L 248 | b0 N 249 | b11111111010 P 250 | #9000 251 | 0% 252 | 0E 253 | b110 4 254 | 0$ 255 | 1# 256 | b111 " 257 | b1001 ! 258 | 1> 259 | 0< 260 | 1; 261 | 1B 262 | 1A 263 | 1@ 264 | 0D 265 | 1C 266 | b11 K 267 | #9500 268 | 1% 269 | 1E 270 | b11 L 271 | b1001 M 272 | b10 K 273 | #10000 274 | 0% 275 | 0E 276 | b111 4 277 | 0# 278 | b10 " 279 | b1100 ! 280 | 0> 281 | 1< 282 | 0B 283 | 0@ 284 | 0C 285 | b0 K 286 | b10 J 287 | #10500 288 | 1% 289 | 1E 290 | b0 L 291 | #11000 292 | 0% 293 | 0E 294 | b1000 4 295 | b100 " 296 | b10 ! 297 | 1= 298 | 0< 299 | 0; 300 | 0A 301 | 1@ 302 | #11500 303 | 1% 304 | 1E 305 | #12000 306 | 0% 307 | 0E 308 | b1001 4 309 | 1$ 310 | 1# 311 | b11 " 312 | b111 ! 313 | 1> 314 | 1< 315 | 1B 316 | 1A 317 | 0@ 318 | 1D 319 | 1C 320 | b11 K 321 | #12500 322 | 1% 323 | 1E 324 | b11 L 325 | b111 M 326 | b11 N 327 | #13000 328 | 0% 329 | 0E 330 | b1010 4 331 | b10 " 332 | b10 ! 333 | 0> 334 | 0< 335 | 0B 336 | b11 J 337 | b1111 O 338 | #13500 339 | 1% 340 | 1E 341 | b10 M 342 | b10 N 343 | b1111 P 344 | #14000 345 | 0% 346 | 0E 347 | b1011 4 348 | 0$ 349 | 0# 350 | b100 " 351 | 0A 352 | 1@ 353 | 0D 354 | 0C 355 | b0 K 356 | b100 J 357 | b10011 O 358 | #14500 359 | 1% 360 | 1E 361 | b0 L 362 | b10011 P 363 | #15000 364 | 0% 365 | 0E 366 | b1100 4 367 | b1 " 368 | b11 ! 369 | 1> 370 | 1B 371 | 0@ 372 | #15500 373 | 1% 374 | 1E 375 | #16000 376 | 0% 377 | 0E 378 | b1101 4 379 | b100 " 380 | b1 ! 381 | 0= 382 | 0B 383 | 1@ 384 | #16500 385 | 1% 386 | 1E 387 | #17000 388 | 0% 389 | 0E 390 | b1110 4 391 | b101 " 392 | b1010 ! 393 | 0> 394 | 1= 395 | 1; 396 | 1B 397 | #17500 398 | 1% 399 | 1E 400 | #18000 401 | 0% 402 | 0E 403 | b1111 4 404 | 1# 405 | b11 ! 406 | 1> 407 | 0; 408 | 1C 409 | b10 K 410 | #18500 411 | 1% 412 | 1E 413 | b10 L 414 | b11 M 415 | #19000 416 | 0% 417 | 0E 418 | b10000 4 419 | 1$ 420 | 0# 421 | b0 " 422 | 0B 423 | 0@ 424 | 1D 425 | 0C 426 | b11 K 427 | #19500 428 | 1% 429 | 1E 430 | b11 L 431 | b0 N 432 | b1 K 433 | #20000 434 | 0% 435 | 0E 436 | b10001 4 437 | 0$ 438 | 1# 439 | b11 " 440 | b100 ! 441 | 0> 442 | 0= 443 | 1< 444 | 1B 445 | 1A 446 | 0D 447 | 1C 448 | b10 K 449 | b101 J 450 | #20500 451 | 1% 452 | 1E 453 | b10 L 454 | b100 M 455 | #21000 456 | 0% 457 | 0E 458 | b10010 4 459 | 1$ 460 | 0# 461 | b100 " 462 | b11 ! 463 | 1> 464 | 1= 465 | 0< 466 | 0B 467 | 0A 468 | 1@ 469 | 1D 470 | 0C 471 | b11 K 472 | #21500 473 | 1% 474 | 1E 475 | b11 L 476 | b100 N 477 | b1 K 478 | #22000 479 | 0% 480 | 0E 481 | b10011 4 482 | 0$ 483 | 1# 484 | b1111 " 485 | b1111 ! 486 | 1< 487 | 1; 488 | 1B 489 | 1A 490 | 1? 491 | 0D 492 | 1C 493 | b10 K 494 | b110 J 495 | b100011 O 496 | #22500 497 | 1% 498 | 1E 499 | b10 L 500 | b1111 M 501 | b100011 P 502 | #23000 503 | 0% 504 | 0E 505 | b10100 4 506 | 1$ 507 | 0# 508 | b0 " 509 | 0B 510 | 0A 511 | 0@ 512 | 0? 513 | 1D 514 | 0C 515 | b11 K 516 | #23500 517 | 1% 518 | 1E 519 | b11 L 520 | b0 N 521 | b1 K 522 | #24000 523 | 0% 524 | 0E 525 | b10101 4 526 | 0$ 527 | b11 " 528 | b11 ! 529 | 0< 530 | 0; 531 | 1B 532 | 1A 533 | 0D 534 | b0 K 535 | b111 J 536 | #24500 537 | 1% 538 | 1E 539 | b0 L 540 | #25000 541 | 0% 542 | 0E 543 | b10110 4 544 | b100 " 545 | b100 ! 546 | 0> 547 | 0= 548 | 1< 549 | 0B 550 | 0A 551 | 1@ 552 | #25500 553 | 1% 554 | 1E 555 | #26000 556 | 0% 557 | 0E 558 | b10111 4 559 | 1$ 560 | b111 " 561 | b111 ! 562 | 1> 563 | 1= 564 | 1B 565 | 1A 566 | 1D 567 | b1 K 568 | #26500 569 | 1% 570 | 1E 571 | b1 L 572 | b111 N 573 | #27000 574 | 0% 575 | 0E 576 | b11000 4 577 | 0$ 578 | 1# 579 | b1 " 580 | b1110 ! 581 | 0> 582 | 1; 583 | 0A 584 | 0@ 585 | 0D 586 | 1C 587 | b11 K 588 | #27500 589 | 1% 590 | 1E 591 | b11 L 592 | b1110 M 593 | b10 K 594 | #28000 595 | 0% 596 | 0E 597 | b11001 4 598 | 1$ 599 | b1111 " 600 | b0 ! 601 | 0= 602 | 0< 603 | 0; 604 | 1A 605 | 1@ 606 | 1? 607 | 1D 608 | b11 K 609 | b1000 J 610 | b10101 O 611 | #28500 612 | 1% 613 | 1E 614 | b0 M 615 | b1111 N 616 | b10101 P 617 | 1I 618 | #29000 619 | 0% 620 | 0E 621 | b11010 4 622 | 0$ 623 | 0# 624 | b110 " 625 | b10 ! 626 | 1= 627 | 0B 628 | 0? 629 | 0D 630 | 0C 631 | b0 K 632 | b1 J 633 | b0 O 634 | #29500 635 | 1% 636 | 1E 637 | b0 L 638 | b0 P 639 | 0I 640 | 1H 641 | b10101 G 642 | 13 643 | 12 644 | 01 645 | 10 646 | 0/ 647 | 1. 648 | 0- 649 | 0, 650 | 0+ 651 | 0* 652 | 0) 653 | 0( 654 | #30000 655 | 0% 656 | 0E 657 | b1 6 658 | b1 ' 659 | b11011 4 660 | 1$ 661 | b1111 " 662 | b101 ! 663 | 1> 664 | 0= 665 | 1< 666 | 1B 667 | 1? 668 | 1D 669 | b1 K 670 | #30500 671 | 1% 672 | 1E 673 | b1 L 674 | 0H 675 | 03 676 | #31000 677 | 0% 678 | 0E 679 | b11100 4 680 | 0$ 681 | 1# 682 | b111 " 683 | b1000 ! 684 | 0> 685 | 0< 686 | 1; 687 | 0? 688 | 0D 689 | 1C 690 | b11 K 691 | #31500 692 | 1% 693 | 1E 694 | b11 L 695 | b1000 M 696 | b10 K 697 | #32000 698 | 0% 699 | 0E 700 | b11101 4 701 | 0# 702 | b11 " 703 | b1001 ! 704 | 1> 705 | 0@ 706 | 0C 707 | b0 K 708 | b10 J 709 | b1000 O 710 | #32500 711 | 1% 712 | 1E 713 | b0 L 714 | b1000 P 715 | #33000 716 | 0% 717 | 0E 718 | b11110 4 719 | b0 " 720 | b11 ! 721 | 1= 722 | 0; 723 | 0B 724 | 0A 725 | #33500 726 | 1% 727 | 1E 728 | #34000 729 | 0% 730 | 0E 731 | b11111 4 732 | 1# 733 | b11 " 734 | b100 ! 735 | 0> 736 | 0= 737 | 1< 738 | 1B 739 | 1A 740 | 1C 741 | b10 K 742 | #34500 743 | 1% 744 | 1E 745 | b10 L 746 | b100 M 747 | #35000 748 | 0% 749 | 0E 750 | b100000 4 751 | 0# 752 | b1111 " 753 | b1011 ! 754 | 1> 755 | 1= 756 | 0< 757 | 1; 758 | 1@ 759 | 1? 760 | 0C 761 | #35500 762 | 1% 763 | 1E 764 | #36000 765 | 0% 766 | 0E 767 | b100001 4 768 | b1110 ! 769 | 0> 770 | 1< 771 | #36500 772 | 1% 773 | 1E 774 | #37000 775 | 0% 776 | 0E 777 | b100010 4 778 | 1$ 779 | b1 " 780 | 0A 781 | 0@ 782 | 0? 783 | 1D 784 | b11 K 785 | #37500 786 | 1% 787 | 1E 788 | b11 L 789 | b1 N 790 | b1 K 791 | #38000 792 | 0% 793 | 0E 794 | b100011 4 795 | 0$ 796 | b10 " 797 | b1010 ! 798 | 0< 799 | 0B 800 | 1A 801 | 0D 802 | b0 K 803 | b11 J 804 | b1100 O 805 | #38500 806 | 1% 807 | 1E 808 | b0 L 809 | b1100 P 810 | #39000 811 | 0% 812 | 0E 813 | b100100 4 814 | 1# 815 | b0 " 816 | b1110 ! 817 | 1< 818 | 0A 819 | 1C 820 | b10 K 821 | #39500 822 | 1% 823 | 1E 824 | b10 L 825 | b1110 M 826 | #40000 827 | 0% 828 | 0E 829 | b100101 4 830 | 1$ 831 | 0# 832 | b11 " 833 | b1 ! 834 | 1> 835 | 0= 836 | 0< 837 | 0; 838 | 1B 839 | 1A 840 | 1D 841 | 0C 842 | b11 K 843 | #40500 844 | 1% 845 | 1E 846 | b11 L 847 | b11 N 848 | b1 K 849 | #41000 850 | 0% 851 | 0E 852 | b100110 4 853 | 0$ 854 | b111 ! 855 | 1= 856 | 1< 857 | 0D 858 | b0 K 859 | b100 J 860 | b110 O 861 | #41500 862 | 1% 863 | 1E 864 | b0 L 865 | b110 P 866 | #42000 867 | 0% 868 | 0E 869 | b100111 4 870 | b0 " 871 | b10 ! 872 | 0> 873 | 0< 874 | 0B 875 | 0A 876 | #42500 877 | 1% 878 | 1E 879 | #43000 880 | 0% 881 | 0E 882 | b101000 4 883 | 1$ 884 | b110 " 885 | b1010 ! 886 | 1; 887 | 1A 888 | 1@ 889 | 1D 890 | b1 K 891 | #43500 892 | 1% 893 | 1E 894 | b1 L 895 | b110 N 896 | #44000 897 | 0% 898 | 0E 899 | b101001 4 900 | 0$ 901 | 1# 902 | b101 " 903 | b1011 ! 904 | 1> 905 | 1B 906 | 0A 907 | 0D 908 | 1C 909 | b11 K 910 | #44500 911 | 1% 912 | 1E 913 | b11 L 914 | b1011 M 915 | b10 K 916 | #45000 917 | 0% 918 | 0E 919 | b101010 4 920 | 0# 921 | b0 " 922 | b10 ! 923 | 0> 924 | 0; 925 | 0B 926 | 0@ 927 | 0C 928 | b0 K 929 | b101 J 930 | b11111101000 O 931 | #45500 932 | 1% 933 | 1E 934 | b0 L 935 | b11111101000 P 936 | #46000 937 | 0% 938 | 0E 939 | b101011 4 940 | b10 " 941 | b110 ! 942 | 1< 943 | 1A 944 | #46500 945 | 1% 946 | 1E 947 | #47000 948 | 0% 949 | 0E 950 | b101100 4 951 | 1$ 952 | 1# 953 | b101 " 954 | b101 ! 955 | 1> 956 | 0= 957 | 1B 958 | 0A 959 | 1@ 960 | 1D 961 | 1C 962 | b11 K 963 | #47500 964 | 1% 965 | 1E 966 | b11 L 967 | b101 M 968 | b101 N 969 | #48000 970 | 0% 971 | 0E 972 | b101101 4 973 | 0# 974 | b11 " 975 | b110 ! 976 | 0> 977 | 1= 978 | 1A 979 | 0@ 980 | 0C 981 | b1 K 982 | b110 J 983 | b1 O 984 | #48500 985 | 1% 986 | 1E 987 | b1 L 988 | b11 N 989 | b1 P 990 | #49000 991 | 0% 992 | 0E 993 | b101110 4 994 | 0$ 995 | 1# 996 | b100 " 997 | b10 ! 998 | 0< 999 | 0B 1000 | 0A 1001 | 1@ 1002 | 0D 1003 | 1C 1004 | b11 K 1005 | #49500 1006 | 1% 1007 | 1E 1008 | b11 L 1009 | b10 M 1010 | b10 K 1011 | #50000 1012 | 0% 1013 | 0E 1014 | b101111 4 1015 | 1$ 1016 | 0# 1017 | b110 " 1018 | b1010 ! 1019 | 1; 1020 | 1A 1021 | 1D 1022 | 0C 1023 | b1 K 1024 | b111 J 1025 | b111 O 1026 | #50500 1027 | 1% 1028 | 1E 1029 | b1 L 1030 | b110 N 1031 | b111 P 1032 | #51000 1033 | 0% 1034 | 0E 1035 | b110000 4 1036 | 0$ 1037 | 1# 1038 | b111 " 1039 | b0 ! 1040 | 0= 1041 | 0; 1042 | 1B 1043 | 0D 1044 | 1C 1045 | b11 K 1046 | #51500 1047 | 1% 1048 | 1E 1049 | b11 L 1050 | b0 M 1051 | b10 K 1052 | #52000 1053 | 0% 1054 | 0E 1055 | b110001 4 1056 | 1$ 1057 | b110 " 1058 | b101 ! 1059 | 1> 1060 | 1< 1061 | 0B 1062 | 1D 1063 | b11 K 1064 | b1000 J 1065 | #52500 1066 | 1% 1067 | 1E 1068 | b101 M 1069 | 1I 1070 | #53000 1071 | 0% 1072 | 0E 1073 | b110010 4 1074 | 0$ 1075 | 0# 1076 | b0 " 1077 | b111 ! 1078 | 1= 1079 | 0A 1080 | 0@ 1081 | 0D 1082 | 0C 1083 | b0 K 1084 | b1 J 1085 | b11110 O 1086 | #53500 1087 | 1% 1088 | 1E 1089 | b0 L 1090 | b11110 P 1091 | 0I 1092 | 1H 1093 | b111 G 1094 | 13 1095 | 11 1096 | 0. 1097 | #54000 1098 | 0% 1099 | 0E 1100 | b10 6 1101 | b10 ' 1102 | b110011 4 1103 | b110 " 1104 | b1000 ! 1105 | 0> 1106 | 0= 1107 | 0< 1108 | 1; 1109 | 1A 1110 | 1@ 1111 | #54500 1112 | 1% 1113 | 1E 1114 | 0H 1115 | 03 1116 | #55000 1117 | 0% 1118 | 0E 1119 | b110100 4 1120 | b11 " 1121 | b100 ! 1122 | 1< 1123 | 0; 1124 | 1B 1125 | 0@ 1126 | #55500 1127 | 1% 1128 | 1E 1129 | #56000 1130 | 0% 1131 | 0E 1132 | b110101 4 1133 | b0 " 1134 | b10 ! 1135 | 1= 1136 | 0< 1137 | 0B 1138 | 0A 1139 | #56500 1140 | 1% 1141 | 1E 1142 | #57000 1143 | 0% 1144 | 0E 1145 | b110110 4 1146 | b1111 " 1147 | b1110 ! 1148 | 1< 1149 | 1; 1150 | 1B 1151 | 1A 1152 | 1@ 1153 | 1? 1154 | #57500 1155 | 1% 1156 | 1E 1157 | #58000 1158 | 0% 1159 | 0E 1160 | b110111 4 1161 | b10 " 1162 | b1000 ! 1163 | 0= 1164 | 0< 1165 | 0B 1166 | 0@ 1167 | 0? 1168 | #58500 1169 | 1% 1170 | 1E 1171 | #59000 1172 | 0% 1173 | 0E 1174 | b111000 4 1175 | b111 " 1176 | b1110 ! 1177 | 1= 1178 | 1< 1179 | 1B 1180 | 1@ 1181 | #59500 1182 | 1% 1183 | 1E 1184 | #60000 1185 | 0% 1186 | 0E 1187 | b111001 4 1188 | b101 " 1189 | b1101 ! 1190 | 1> 1191 | 0= 1192 | 0A 1193 | #60500 1194 | 1% 1195 | 1E 1196 | #61000 1197 | 0% 1198 | 0E 1199 | b111010 4 1200 | b1 " 1201 | b111 ! 1202 | 1= 1203 | 0; 1204 | 0@ 1205 | #61500 1206 | 1% 1207 | 1E 1208 | #62000 1209 | 0% 1210 | 0E 1211 | b111011 4 1212 | 1$ 1213 | b1111 " 1214 | b1100 ! 1215 | 0> 1216 | 0= 1217 | 1; 1218 | 1A 1219 | 1@ 1220 | 1? 1221 | 1D 1222 | b1 K 1223 | #62500 1224 | 1% 1225 | 1E 1226 | b1 L 1227 | b1111 N 1228 | #63000 1229 | 0% 1230 | 0E 1231 | b111100 4 1232 | 0$ 1233 | 1# 1234 | b10 " 1235 | b1101 ! 1236 | 1> 1237 | 0B 1238 | 0@ 1239 | 0? 1240 | 0D 1241 | 1C 1242 | b11 K 1243 | #63500 1244 | 1% 1245 | 1E 1246 | b11 L 1247 | b1101 M 1248 | b10 K 1249 | #64000 1250 | 0% 1251 | 0E 1252 | b111101 4 1253 | 0# 1254 | b100 " 1255 | b0 ! 1256 | 0> 1257 | 0< 1258 | 0; 1259 | 0A 1260 | 1@ 1261 | 0C 1262 | b0 K 1263 | b10 J 1264 | b100001 O 1265 | #64500 1266 | 1% 1267 | 1E 1268 | b0 L 1269 | b100001 P 1270 | #65000 1271 | 0% 1272 | 0E 1273 | b111110 4 1274 | b101 " 1275 | b1101 ! 1276 | 1> 1277 | 1< 1278 | 1; 1279 | 1B 1280 | #65500 1281 | 1% 1282 | 1E 1283 | #66000 1284 | 0% 1285 | 0E 1286 | b111111 4 1287 | 1$ 1288 | 1# 1289 | b11 " 1290 | b11 ! 1291 | 1= 1292 | 0< 1293 | 0; 1294 | 1A 1295 | 0@ 1296 | 1D 1297 | 1C 1298 | b11 K 1299 | #66500 1300 | 1% 1301 | 1E 1302 | b11 L 1303 | b11 M 1304 | b11 N 1305 | #67000 1306 | 0% 1307 | 0E 1308 | b1000000 4 1309 | 0# 1310 | b100 " 1311 | b1100 ! 1312 | 0> 1313 | 0= 1314 | 1< 1315 | 1; 1316 | 0B 1317 | 0A 1318 | 1@ 1319 | 0C 1320 | b1 K 1321 | b11 J 1322 | b101010 O 1323 | #67500 1324 | 1% 1325 | 1E 1326 | b1 L 1327 | b100 N 1328 | b101010 P 1329 | #68000 1330 | 0% 1331 | 0E 1332 | b1000001 4 1333 | 0$ 1334 | 1# 1335 | b1111 " 1336 | b1001 ! 1337 | 1> 1338 | 0< 1339 | 1B 1340 | 1A 1341 | 1? 1342 | 0D 1343 | 1C 1344 | b11 K 1345 | #68500 1346 | 1% 1347 | 1E 1348 | b11 L 1349 | b1001 M 1350 | b10 K 1351 | #69000 1352 | 0% 1353 | 0E 1354 | b1000010 4 1355 | 0# 1356 | b0 " 1357 | b101 ! 1358 | 1< 1359 | 0; 1360 | 0B 1361 | 0A 1362 | 0@ 1363 | 0? 1364 | 0C 1365 | b0 K 1366 | b100 J 1367 | b1110 O 1368 | #69500 1369 | 1% 1370 | 1E 1371 | b0 L 1372 | b1110 P 1373 | #70000 1374 | 0% 1375 | 0E 1376 | b1000011 4 1377 | b11 " 1378 | b11 ! 1379 | 1= 1380 | 0< 1381 | 1B 1382 | 1A 1383 | #70500 1384 | 1% 1385 | 1E 1386 | #71000 1387 | 0% 1388 | 0E 1389 | b1000100 4 1390 | b101 " 1391 | b1100 ! 1392 | 0> 1393 | 0= 1394 | 1< 1395 | 1; 1396 | 0A 1397 | 1@ 1398 | #71500 1399 | 1% 1400 | 1E 1401 | #72000 1402 | 0% 1403 | 0E 1404 | b1000101 4 1405 | b1111 " 1406 | b110 ! 1407 | 1= 1408 | 0; 1409 | 1A 1410 | 1? 1411 | #72500 1412 | 1% 1413 | 1E 1414 | #73000 1415 | 0% 1416 | 0E 1417 | b1000110 4 1418 | b111 " 1419 | b1 ! 1420 | 1> 1421 | 0= 1422 | 0< 1423 | 0? 1424 | #73500 1425 | 1% 1426 | 1E 1427 | #74000 1428 | 0% 1429 | 0E 1430 | b1000111 4 1431 | 1$ 1432 | 1# 1433 | b100 " 1434 | b10 ! 1435 | 0> 1436 | 1= 1437 | 0B 1438 | 0A 1439 | 1D 1440 | 1C 1441 | b11 K 1442 | #74500 1443 | 1% 1444 | 1E 1445 | b11 L 1446 | b10 M 1447 | #75000 1448 | 0% 1449 | 0E 1450 | b1001000 4 1451 | b101 ! 1452 | 1> 1453 | 0= 1454 | 1< 1455 | b101 J 1456 | b10110 O 1457 | #75500 1458 | 1% 1459 | 1E 1460 | b101 M 1461 | b10110 P 1462 | #76000 1463 | 0% 1464 | 0E 1465 | b1001001 4 1466 | 0$ 1467 | 0# 1468 | b111 " 1469 | b1001 ! 1470 | 0< 1471 | 1; 1472 | 1B 1473 | 1A 1474 | 0D 1475 | 0C 1476 | b0 K 1477 | b110 J 1478 | b101010 O 1479 | #76500 1480 | 1% 1481 | 1E 1482 | b0 L 1483 | b101010 P 1484 | #77000 1485 | 0% 1486 | 0E 1487 | b1001010 4 1488 | 1# 1489 | b11 " 1490 | b1010 ! 1491 | 0> 1492 | 1= 1493 | 0@ 1494 | 1C 1495 | b10 K 1496 | #77500 1497 | 1% 1498 | 1E 1499 | b10 L 1500 | b1010 M 1501 | #78000 1502 | 0% 1503 | 0E 1504 | b1001011 4 1505 | 0# 1506 | b110 " 1507 | b1001 ! 1508 | 1> 1509 | 0= 1510 | 0B 1511 | 1@ 1512 | 0C 1513 | #78500 1514 | 1% 1515 | 1E 1516 | #79000 1517 | 0% 1518 | 0E 1519 | b1001100 4 1520 | b100 " 1521 | b11 ! 1522 | 1= 1523 | 0; 1524 | 0A 1525 | #79500 1526 | 1% 1527 | 1E 1528 | #80000 1529 | 0% 1530 | 0E 1531 | b1001101 4 1532 | 1$ 1533 | b11 " 1534 | b101 ! 1535 | 0= 1536 | 1< 1537 | 1B 1538 | 1A 1539 | 0@ 1540 | 1D 1541 | b11 K 1542 | #80500 1543 | 1% 1544 | 1E 1545 | b11 L 1546 | b11 N 1547 | b1 K 1548 | #81000 1549 | 0% 1550 | 0E 1551 | b1001110 4 1552 | 0$ 1553 | b101 " 1554 | b1100 ! 1555 | 0> 1556 | 1; 1557 | 0A 1558 | 1@ 1559 | 0D 1560 | b0 K 1561 | b111 J 1562 | b11000 O 1563 | #81500 1564 | 1% 1565 | 1E 1566 | b0 L 1567 | b11000 P 1568 | #82000 1569 | 0% 1570 | 0E 1571 | b1001111 4 1572 | 1$ 1573 | 1# 1574 | b100 " 1575 | 0B 1576 | 1D 1577 | 1C 1578 | b11 K 1579 | #82500 1580 | 1% 1581 | 1E 1582 | b11 L 1583 | b1100 M 1584 | b100 N 1585 | #83000 1586 | 0% 1587 | 0E 1588 | b1010000 4 1589 | 0$ 1590 | b10 " 1591 | b1011 ! 1592 | 1> 1593 | 1= 1594 | 0< 1595 | 1A 1596 | 0@ 1597 | 0D 1598 | b10 K 1599 | b1000 J 1600 | b1000 O 1601 | #83500 1602 | 1% 1603 | 1E 1604 | b10 L 1605 | b1011 M 1606 | b1000 P 1607 | 1I 1608 | #84000 1609 | 0% 1610 | 0E 1611 | b1010001 4 1612 | 0# 1613 | b1 " 1614 | b1111 ! 1615 | 1< 1616 | 1B 1617 | 0A 1618 | 0C 1619 | b0 J 1620 | b0 O 1621 | #84500 1622 | 1% 1623 | 1E 1624 | 0I 1625 | 1H 1626 | b1000 G 1627 | 13 1628 | 02 1629 | 01 1630 | 00 1631 | 1/ 1632 | #85000 1633 | 0% 1634 | 0E 1635 | b11 6 1636 | b11 ' 1637 | b1010010 4 1638 | b111 " 1639 | b1110 ! 1640 | 0> 1641 | 1A 1642 | 1@ 1643 | #85500 1644 | 1% 1645 | 1E 1646 | 0H 1647 | 03 1648 | #86000 1649 | 0% 1650 | 0E 1651 | b1010011 4 1652 | b0 " 1653 | b1011 ! 1654 | 1> 1655 | 0< 1656 | 0B 1657 | 0A 1658 | 0@ 1659 | #86500 1660 | 1% 1661 | 1E 1662 | #87000 1663 | 0% 1664 | 0E 1665 | b1010100 4 1666 | 1$ 1667 | b100 " 1668 | b11 ! 1669 | 0; 1670 | 1@ 1671 | 1D 1672 | b11 K 1673 | #87500 1674 | 1% 1675 | 1E 1676 | b11 L 1677 | b1 K 1678 | #88000 1679 | 0% 1680 | 0E 1681 | b1010101 4 1682 | b11 " 1683 | b100 ! 1684 | 0> 1685 | 0= 1686 | 1< 1687 | 1B 1688 | 1A 1689 | 0@ 1690 | b1 J 1691 | b11111101100 O 1692 | #88500 1693 | 1% 1694 | 1E 1695 | b1 L 1696 | b11 N 1697 | b11111101100 P 1698 | #89000 1699 | 0% 1700 | 0E 1701 | b1010110 4 1702 | 0$ 1703 | 1# 1704 | b101 " 1705 | b0 ! 1706 | 0< 1707 | 0A 1708 | 1@ 1709 | 0D 1710 | 1C 1711 | b11 K 1712 | #89500 1713 | 1% 1714 | 1E 1715 | b11 L 1716 | b0 M 1717 | b10 K 1718 | #90000 1719 | 0% 1720 | 0E 1721 | b1010111 4 1722 | 1$ 1723 | b111 " 1724 | b1000 ! 1725 | 1; 1726 | 1A 1727 | 1D 1728 | b11 K 1729 | b10 J 1730 | #90500 1731 | 1% 1732 | 1E 1733 | b1000 M 1734 | b111 N 1735 | #91000 1736 | 0% 1737 | 0E 1738 | b1011000 4 1739 | 0$ 1740 | 0# 1741 | b1011 ! 1742 | 1> 1743 | 1= 1744 | 0D 1745 | 0C 1746 | b0 K 1747 | b11 J 1748 | b11110110100 O 1749 | #91500 1750 | 1% 1751 | 1E 1752 | b0 L 1753 | b11110110100 P 1754 | #92000 1755 | 0% 1756 | 0E 1757 | b1011001 4 1758 | b1 " 1759 | b100 ! 1760 | 0> 1761 | 0= 1762 | 1< 1763 | 0; 1764 | 0A 1765 | 0@ 1766 | #92500 1767 | 1% 1768 | 1E 1769 | #93000 1770 | 0% 1771 | 0E 1772 | b1011010 4 1773 | 1$ 1774 | 1D 1775 | b1 K 1776 | #93500 1777 | 1% 1778 | 1E 1779 | b1 L 1780 | b1 N 1781 | #94000 1782 | 0% 1783 | 0E 1784 | b1011011 4 1785 | 0$ 1786 | b110 ! 1787 | 1= 1788 | 0D 1789 | #94500 1790 | 1% 1791 | 1E 1792 | #95000 1793 | 0% 1794 | 0E 1795 | b1011100 4 1796 | b11 " 1797 | b1100 ! 1798 | 0= 1799 | 1; 1800 | 1A 1801 | #95500 1802 | 1% 1803 | 1E 1804 | #96000 1805 | 0% 1806 | 0E 1807 | b1011101 4 1808 | b1 " 1809 | b1000 ! 1810 | 0< 1811 | 0A 1812 | #96500 1813 | 1% 1814 | 1E 1815 | #97000 1816 | 0% 1817 | 0E 1818 | b1011110 4 1819 | b110 " 1820 | b1110 ! 1821 | 1= 1822 | 1< 1823 | 0B 1824 | 1A 1825 | 1@ 1826 | #97500 1827 | 1% 1828 | 1E 1829 | #98000 1830 | 0% 1831 | 0E 1832 | b1011111 4 1833 | 1# 1834 | b100 " 1835 | b10 ! 1836 | 0< 1837 | 0; 1838 | 0A 1839 | 1C 1840 | b11 K 1841 | #98500 1842 | 1% 1843 | 1E 1844 | b11 L 1845 | b10 M 1846 | b10 K 1847 | #99000 1848 | 0% 1849 | 0E 1850 | b1100000 4 1851 | 1$ 1852 | 0# 1853 | b1 " 1854 | b1011 ! 1855 | 1> 1856 | 1; 1857 | 1B 1858 | 0@ 1859 | 1D 1860 | 0C 1861 | b1 K 1862 | b100 J 1863 | b11110110110 O 1864 | #99500 1865 | 1% 1866 | 1E 1867 | b1 L 1868 | b11110110110 P 1869 | #100000 1870 | 0% 1871 | 0E 1872 | b1100001 4 1873 | 0$ 1874 | 1# 1875 | b10 " 1876 | b111 ! 1877 | 1< 1878 | 0; 1879 | 0B 1880 | 1A 1881 | 0D 1882 | 1C 1883 | b11 K 1884 | #100500 1885 | 1% 1886 | 1E 1887 | b11 L 1888 | b111 M 1889 | b10 K 1890 | #101000 1891 | 0% 1892 | 0E 1893 | b1100010 4 1894 | 1$ 1895 | 0# 1896 | b1110 ! 1897 | 0> 1898 | 1; 1899 | 1D 1900 | 0C 1901 | b1 K 1902 | b101 J 1903 | b11110111101 O 1904 | #101500 1905 | 1% 1906 | 1E 1907 | b1 L 1908 | b10 N 1909 | b11110111101 P 1910 | #102000 1911 | 0% 1912 | 0E 1913 | b1100011 4 1914 | 0$ 1915 | 1# 1916 | b111 " 1917 | b1 ! 1918 | 1> 1919 | 0= 1920 | 0< 1921 | 0; 1922 | 1B 1923 | 1@ 1924 | 0D 1925 | 1C 1926 | b11 K 1927 | #102500 1928 | 1% 1929 | 1E 1930 | b11 L 1931 | b1 M 1932 | b10 K 1933 | #103000 1934 | 0% 1935 | 0E 1936 | b1100100 4 1937 | 1$ 1938 | 0# 1939 | b10 " 1940 | b1111 ! 1941 | 1= 1942 | 1< 1943 | 1; 1944 | 0B 1945 | 0@ 1946 | 1D 1947 | 0C 1948 | b1 K 1949 | b110 J 1950 | b11110111111 O 1951 | #103500 1952 | 1% 1953 | 1E 1954 | b1 L 1955 | b11110111111 P 1956 | #104000 1957 | 0% 1958 | 0E 1959 | b1100101 4 1960 | 0$ 1961 | 1# 1962 | b101 " 1963 | b101 ! 1964 | 0= 1965 | 0; 1966 | 1B 1967 | 0A 1968 | 1@ 1969 | 0D 1970 | 1C 1971 | b11 K 1972 | #104500 1973 | 1% 1974 | 1E 1975 | b11 L 1976 | b101 M 1977 | b10 K 1978 | #105000 1979 | 0% 1980 | 0E 1981 | b1100110 4 1982 | 0# 1983 | b111 " 1984 | 1A 1985 | 0C 1986 | b0 K 1987 | b111 J 1988 | b11111001001 O 1989 | #105500 1990 | 1% 1991 | 1E 1992 | b0 L 1993 | b11111001001 P 1994 | #106000 1995 | 0% 1996 | 0E 1997 | b1100111 4 1998 | b1 " 1999 | b1100 ! 2000 | 0> 2001 | 1; 2002 | 0A 2003 | 0@ 2004 | #106500 2005 | 1% 2006 | 1E 2007 | #107000 2008 | 0% 2009 | 0E 2010 | b1101000 4 2011 | b11 " 2012 | b1111 ! 2013 | 1> 2014 | 1= 2015 | 1A 2016 | #107500 2017 | 1% 2018 | 1E 2019 | #108000 2020 | 0% 2021 | 0E 2022 | b1101001 4 2023 | b1 " 2024 | b1101 ! 2025 | 0= 2026 | 0A 2027 | #108500 2028 | 1% 2029 | 1E 2030 | #109000 2031 | 0% 2032 | 0E 2033 | b1101010 4 2034 | b1001 ! 2035 | 0< 2036 | #109500 2037 | 1% 2038 | 1E 2039 | #110000 2040 | 0% 2041 | 0E 2042 | b1101011 4 2043 | b100 " 2044 | b110 ! 2045 | 0> 2046 | 1= 2047 | 1< 2048 | 0; 2049 | 0B 2050 | 1@ 2051 | #110500 2052 | 1% 2053 | 1E 2054 | #111000 2055 | 0% 2056 | 0E 2057 | b1101100 4 2058 | 1$ 2059 | b0 ! 2060 | 0= 2061 | 0< 2062 | 1D 2063 | b1 K 2064 | #111500 2065 | 1% 2066 | 1E 2067 | b1 L 2068 | b100 N 2069 | #112000 2070 | 0% 2071 | 0E 2072 | b1101101 4 2073 | 0$ 2074 | b0 " 2075 | b111 ! 2076 | 1> 2077 | 1= 2078 | 1< 2079 | 0@ 2080 | 0D 2081 | #112500 2082 | 1% 2083 | 1E 2084 | #113000 2085 | 0% 2086 | 0E 2087 | b1101110 4 2088 | b101 " 2089 | b11 ! 2090 | 0< 2091 | 1B 2092 | 1@ 2093 | #113500 2094 | 1% 2095 | 1E 2096 | #114000 2097 | 0% 2098 | 0E 2099 | b1101111 4 2100 | 1# 2101 | b11 " 2102 | b1001 ! 2103 | 0= 2104 | 1; 2105 | 1A 2106 | 0@ 2107 | 1C 2108 | b11 K 2109 | #114500 2110 | 1% 2111 | 1E 2112 | b11 L 2113 | b1001 M 2114 | b10 K 2115 | #115000 2116 | 0% 2117 | 0E 2118 | b1110000 4 2119 | 1$ 2120 | b10 " 2121 | b100 ! 2122 | 0> 2123 | 1< 2124 | 0; 2125 | 0B 2126 | 1D 2127 | b11 K 2128 | b1000 J 2129 | b11110101101 O 2130 | #115500 2131 | 1% 2132 | 1E 2133 | b100 M 2134 | b10 N 2135 | b11110101101 P 2136 | 1I 2137 | #116000 2138 | 0% 2139 | 0E 2140 | b1110001 4 2141 | b101 " 2142 | b110 ! 2143 | 1= 2144 | 1B 2145 | 0A 2146 | 1@ 2147 | b1 J 2148 | b1000 O 2149 | #116500 2150 | 1% 2151 | 1E 2152 | b110 M 2153 | b101 N 2154 | b1000 P 2155 | 0I 2156 | 1H 2157 | b11110101101 G 2158 | 13 2159 | 12 2160 | 10 2161 | 1- 2162 | 1+ 2163 | 1* 2164 | 1) 2165 | 1( 2166 | #117000 2167 | 0% 2168 | 0E 2169 | b100 6 2170 | b100 ' 2171 | b1110010 4 2172 | 0$ 2173 | 0# 2174 | b0 " 2175 | b0 ! 2176 | 0= 2177 | 0< 2178 | 0B 2179 | 0@ 2180 | 0D 2181 | 0C 2182 | b0 K 2183 | b10 J 2184 | b100110 O 2185 | #117500 2186 | 1% 2187 | 1E 2188 | b0 L 2189 | b100110 P 2190 | 0H 2191 | 03 2192 | #118000 2193 | 0% 2194 | 0E 2195 | b1110011 4 2196 | 1# 2197 | b110 " 2198 | b1010 ! 2199 | 1= 2200 | 1; 2201 | 1A 2202 | 1@ 2203 | 1C 2204 | b10 K 2205 | #118500 2206 | 1% 2207 | 1E 2208 | b10 L 2209 | b1010 M 2210 | #119000 2211 | 0% 2212 | 0E 2213 | b1110100 4 2214 | 1$ 2215 | 0# 2216 | b111 " 2217 | b101 ! 2218 | 1> 2219 | 0= 2220 | 1< 2221 | 0; 2222 | 1B 2223 | 1D 2224 | 0C 2225 | b11 K 2226 | #119500 2227 | 1% 2228 | 1E 2229 | b11 L 2230 | b111 N 2231 | b1 K 2232 | #120000 2233 | 0% 2234 | 0E 2235 | b1110101 4 2236 | 1# 2237 | b0 " 2238 | b110 ! 2239 | 0> 2240 | 1= 2241 | 0B 2242 | 0A 2243 | 0@ 2244 | 1C 2245 | b11 K 2246 | b11 J 2247 | b11111111100 O 2248 | #120500 2249 | 1% 2250 | 1E 2251 | b110 M 2252 | b0 N 2253 | b11111111100 P 2254 | #121000 2255 | 0% 2256 | 0E 2257 | b1110110 4 2258 | b10 ! 2259 | 0< 2260 | b100 J 2261 | #121500 2262 | 1% 2263 | 1E 2264 | b10 M 2265 | #122000 2266 | 0% 2267 | 0E 2268 | b1110111 4 2269 | 0# 2270 | b10 " 2271 | b1101 ! 2272 | 1> 2273 | 0= 2274 | 1< 2275 | 1; 2276 | 1A 2277 | 0C 2278 | b1 K 2279 | b101 J 2280 | #122500 2281 | 1% 2282 | 1E 2283 | b1 L 2284 | b10 N 2285 | #123000 2286 | 0% 2287 | 0E 2288 | b1111000 4 2289 | 0$ 2290 | 1# 2291 | b100 " 2292 | b1000 ! 2293 | 0> 2294 | 0< 2295 | 0A 2296 | 1@ 2297 | 0D 2298 | 1C 2299 | b11 K 2300 | #123500 2301 | 1% 2302 | 1E 2303 | b11 L 2304 | b1000 M 2305 | b10 K 2306 | #124000 2307 | 0% 2308 | 0E 2309 | b1111001 4 2310 | b10 " 2311 | b1111 ! 2312 | 1> 2313 | 1= 2314 | 1< 2315 | 1A 2316 | 0@ 2317 | b110 J 2318 | b11111101100 O 2319 | #124500 2320 | 1% 2321 | 1E 2322 | b10 L 2323 | b1111 M 2324 | b11111101100 P 2325 | #125000 2326 | 0% 2327 | 0E 2328 | b1111010 4 2329 | 0# 2330 | b11 " 2331 | 1B 2332 | 0C 2333 | #125500 2334 | 1% 2335 | 1E 2336 | #126000 2337 | 0% 2338 | 0E 2339 | b1111011 4 2340 | b1001 ! 2341 | 0= 2342 | 0< 2343 | #126500 2344 | 1% 2345 | 1E 2346 | #127000 2347 | 0% 2348 | 0E 2349 | b1111100 4 2350 | 1$ 2351 | b10 " 2352 | b1100 ! 2353 | 0> 2354 | 1< 2355 | 0B 2356 | 1D 2357 | b11 K 2358 | #127500 2359 | 1% 2360 | 1E 2361 | b11 L 2362 | b1 K 2363 | #128000 2364 | 0% 2365 | 0E 2366 | b1111101 4 2367 | 0$ 2368 | b0 " 2369 | b0 ! 2370 | 0< 2371 | 0; 2372 | 0A 2373 | 0D 2374 | b0 K 2375 | b111 J 2376 | b11111101010 O 2377 | #128500 2378 | 1% 2379 | 1E 2380 | b0 L 2381 | b11111101010 P 2382 | #129000 2383 | 0% 2384 | 0E 2385 | b1111110 4 2386 | b10 " 2387 | b1011 ! 2388 | 1> 2389 | 1= 2390 | 1; 2391 | 1A 2392 | #129500 2393 | 1% 2394 | 1E 2395 | #130000 2396 | 0% 2397 | 0E 2398 | b1111111 4 2399 | 1# 2400 | b110 " 2401 | b1001 ! 2402 | 0= 2403 | 1@ 2404 | 1C 2405 | b10 K 2406 | #130500 2407 | 1% 2408 | 1E 2409 | b10 L 2410 | b1001 M 2411 | #131000 2412 | 0% 2413 | 0E 2414 | b10000000 4 2415 | 1$ 2416 | 0# 2417 | b1111 " 2418 | b111 ! 2419 | 1= 2420 | 1< 2421 | 0; 2422 | 1B 2423 | 1? 2424 | 1D 2425 | 0C 2426 | b11 K 2427 | #131500 2428 | 1% 2429 | 1E 2430 | b11 L 2431 | b1111 N 2432 | b1 K 2433 | #132000 2434 | 0% 2435 | 0E 2436 | b10000001 4 2437 | 0$ 2438 | b11 " 2439 | b11 ! 2440 | 0< 2441 | 0@ 2442 | 0? 2443 | 0D 2444 | b0 K 2445 | b1000 J 2446 | b11111110001 O 2447 | #132500 2448 | 1% 2449 | 1E 2450 | b0 L 2451 | b11111110001 P 2452 | 1I 2453 | #133000 2454 | 0% 2455 | 0E 2456 | b10000010 4 2457 | 1$ 2458 | b10 ! 2459 | 0> 2460 | 1D 2461 | b1 K 2462 | b0 J 2463 | b0 O 2464 | #133500 2465 | 1% 2466 | 1E 2467 | b1 L 2468 | b11 N 2469 | 0I 2470 | 1H 2471 | b11111110001 G 2472 | 13 2473 | 00 2474 | 0/ 2475 | 1. 2476 | 1, 2477 | #134000 2478 | 0% 2479 | 0E 2480 | b101 6 2481 | b101 ' 2482 | b10000011 4 2483 | 0$ 2484 | 1# 2485 | b10 " 2486 | b1000 ! 2487 | 0= 2488 | 1; 2489 | 0B 2490 | 0D 2491 | 1C 2492 | b11 K 2493 | #134500 2494 | 1% 2495 | 1E 2496 | b11 L 2497 | b1000 M 2498 | 0H 2499 | 03 2500 | b10 K 2501 | #135000 2502 | 0% 2503 | 0E 2504 | b10000100 4 2505 | b1111 " 2506 | b1 ! 2507 | 1> 2508 | 0; 2509 | 1B 2510 | 1@ 2511 | 1? 2512 | b1 J 2513 | b11111101000 O 2514 | #135500 2515 | 1% 2516 | 1E 2517 | b10 L 2518 | b1 M 2519 | b11111101000 P 2520 | #136000 2521 | 0% 2522 | 0E 2523 | b10000101 4 2524 | 0# 2525 | b110 " 2526 | b1110 ! 2527 | 0> 2528 | 1= 2529 | 1< 2530 | 1; 2531 | 0B 2532 | 0? 2533 | 0C 2534 | #136500 2535 | 1% 2536 | 1E 2537 | #137000 2538 | 0% 2539 | 0E 2540 | b10000110 4 2541 | 1$ 2542 | b111 " 2543 | b110 ! 2544 | 0; 2545 | 1B 2546 | 1D 2547 | b11 K 2548 | #137500 2549 | 1% 2550 | 1E 2551 | b11 L 2552 | b111 N 2553 | b1 K 2554 | #138000 2555 | 0% 2556 | 0E 2557 | b10000111 4 2558 | 0$ 2559 | b1111 ! 2560 | 1> 2561 | 1; 2562 | 0D 2563 | b0 K 2564 | b10 J 2565 | b11111101111 O 2566 | #138500 2567 | 1% 2568 | 1E 2569 | b0 L 2570 | b11111101111 P 2571 | #139000 2572 | 0% 2573 | 0E 2574 | b10001000 4 2575 | b1 " 2576 | b1101 ! 2577 | 0= 2578 | 0A 2579 | 0@ 2580 | #139500 2581 | 1% 2582 | 1E 2583 | #140000 2584 | 0% 2585 | 0E 2586 | b10001001 4 2587 | b11 ! 2588 | 1= 2589 | 0< 2590 | 0; 2591 | #140500 2592 | 1% 2593 | 1E 2594 | #141000 2595 | 0% 2596 | 0E 2597 | b10001010 4 2598 | 1$ 2599 | b1111 " 2600 | b111 ! 2601 | 1< 2602 | 1A 2603 | 1@ 2604 | 1? 2605 | 1D 2606 | b1 K 2607 | #141500 2608 | 1% 2609 | 1E 2610 | b1 L 2611 | b1111 N 2612 | #142000 2613 | 0% 2614 | 0E 2615 | b10001011 4 2616 | 0$ 2617 | 1# 2618 | b0 " 2619 | b1111 ! 2620 | 1; 2621 | 0B 2622 | 0A 2623 | 0@ 2624 | 0? 2625 | 0D 2626 | 1C 2627 | b11 K 2628 | #142500 2629 | 1% 2630 | 1E 2631 | b11 L 2632 | b1111 M 2633 | b10 K 2634 | #143000 2635 | 0% 2636 | 0E 2637 | b10001100 4 2638 | 0# 2639 | b101 " 2640 | b1001 ! 2641 | 0= 2642 | 0< 2643 | 1B 2644 | 1@ 2645 | 0C 2646 | b0 K 2647 | b11 J 2648 | b11111110000 O 2649 | #143500 2650 | 1% 2651 | 1E 2652 | b0 L 2653 | b11111110000 P 2654 | #144000 2655 | 0% 2656 | 0E 2657 | b10001101 4 2658 | b0 ! 2659 | 0> 2660 | 0; 2661 | #144500 2662 | 1% 2663 | 1E 2664 | #145000 2665 | 0% 2666 | 0E 2667 | b10001110 4 2668 | 1$ 2669 | b111 " 2670 | b1010 ! 2671 | 1= 2672 | 1; 2673 | 1A 2674 | 1D 2675 | b1 K 2676 | #145500 2677 | 1% 2678 | 1E 2679 | b1 L 2680 | b111 N 2681 | #146000 2682 | 0% 2683 | 0E 2684 | b10001111 4 2685 | 0$ 2686 | b101 " 2687 | b1001 ! 2688 | 1> 2689 | 0= 2690 | 0A 2691 | 0D 2692 | #146500 2693 | 1% 2694 | 1E 2695 | #147000 2696 | 0% 2697 | 0E 2698 | b10010000 4 2699 | b10 " 2700 | b110 ! 2701 | 0> 2702 | 1= 2703 | 1< 2704 | 0; 2705 | 0B 2706 | 1A 2707 | 0@ 2708 | #147500 2709 | 1% 2710 | 1E 2711 | #148000 2712 | 0% 2713 | 0E 2714 | b10010001 4 2715 | 1# 2716 | b1100 ! 2717 | 0= 2718 | 1; 2719 | 1C 2720 | b11 K 2721 | #148500 2722 | 1% 2723 | 1E 2724 | b11 L 2725 | b1100 M 2726 | b10 K 2727 | #149000 2728 | 0% 2729 | 0E 2730 | b10010010 4 2731 | 1$ 2732 | 1D 2733 | b11 K 2734 | b100 J 2735 | b11111010100 O 2736 | #149500 2737 | 1% 2738 | 1E 2739 | b10 N 2740 | b11111010100 P 2741 | #150000 2742 | 0% 2743 | 0E 2744 | b10010011 4 2745 | b0 ! 2746 | 0< 2747 | 0; 2748 | b101 J 2749 | b11111001100 O 2750 | #150500 2751 | 1% 2752 | 1E 2753 | b0 M 2754 | b11111001100 P 2755 | #151000 2756 | 0% 2757 | 0E 2758 | b10010100 4 2759 | b0 " 2760 | b1001 ! 2761 | 1> 2762 | 1; 2763 | 0A 2764 | b110 J 2765 | #151500 2766 | 1% 2767 | 1E 2768 | b1001 M 2769 | b0 N 2770 | #152000 2771 | 0% 2772 | 0E 2773 | b10010101 4 2774 | 0$ 2775 | 0# 2776 | b110 " 2777 | b1 ! 2778 | 0; 2779 | 1A 2780 | 1@ 2781 | 0D 2782 | 0C 2783 | b0 K 2784 | b111 J 2785 | #152500 2786 | 1% 2787 | 1E 2788 | b0 L 2789 | #153000 2790 | 0% 2791 | 0E 2792 | b10010110 4 2793 | b1110 ! 2794 | 0> 2795 | 1= 2796 | 1< 2797 | 1; 2798 | #153500 2799 | 1% 2800 | 1E 2801 | #154000 2802 | 0% 2803 | 0E 2804 | b10010111 4 2805 | b10 " 2806 | b1101 ! 2807 | 1> 2808 | 0= 2809 | 0@ 2810 | #154500 2811 | 1% 2812 | 1E 2813 | #155000 2814 | 0% 2815 | 0E 2816 | b10011000 4 2817 | 1$ 2818 | b1111 " 2819 | b1100 ! 2820 | 0> 2821 | 1B 2822 | 1@ 2823 | 1? 2824 | 1D 2825 | b1 K 2826 | #155500 2827 | 1% 2828 | 1E 2829 | b1 L 2830 | b1111 N 2831 | #156000 2832 | 0% 2833 | 0E 2834 | b10011001 4 2835 | 0$ 2836 | 1# 2837 | b11 " 2838 | b1101 ! 2839 | 1> 2840 | 0@ 2841 | 0? 2842 | 0D 2843 | 1C 2844 | b11 K 2845 | #156500 2846 | 1% 2847 | 1E 2848 | b11 L 2849 | b1101 M 2850 | b10 K 2851 | #157000 2852 | 0% 2853 | 0E 2854 | b10011010 4 2855 | b111 " 2856 | 1@ 2857 | b1000 J 2858 | b11111001111 O 2859 | #157500 2860 | 1% 2861 | 1E 2862 | b10 L 2863 | b11111001111 P 2864 | 1I 2865 | #158000 2866 | 0% 2867 | 0E 2868 | b10011011 4 2869 | 0# 2870 | b1111 " 2871 | b111 ! 2872 | 1= 2873 | 0; 2874 | 1? 2875 | 0C 2876 | b0 J 2877 | b0 O 2878 | #158500 2879 | 1% 2880 | 1E 2881 | 0I 2882 | 1H 2883 | b11111001111 G 2884 | 13 2885 | 11 2886 | 10 2887 | 1/ 2888 | 0. 2889 | 0- 2890 | #159000 2891 | 0% 2892 | 0E 2893 | b110 6 2894 | b110 ' 2895 | b10011100 4 2896 | 1$ 2897 | b110 " 2898 | b1000 ! 2899 | 0> 2900 | 0= 2901 | 0< 2902 | 1; 2903 | 0B 2904 | 0? 2905 | 1D 2906 | b11 K 2907 | #159500 2908 | 1% 2909 | 1E 2910 | b11 L 2911 | b110 N 2912 | 0H 2913 | 03 2914 | b1 K 2915 | #160000 2916 | 0% 2917 | 0E 2918 | b10011101 4 2919 | 1# 2920 | b1111 ! 2921 | 1> 2922 | 1= 2923 | 1< 2924 | 1C 2925 | b11 K 2926 | b1 J 2927 | b11111101110 O 2928 | #160500 2929 | 1% 2930 | 1E 2931 | b1111 M 2932 | b11111101110 P 2933 | #161000 2934 | 0% 2935 | 0E 2936 | b10011110 4 2937 | 0# 2938 | b1001 ! 2939 | 0= 2940 | 0< 2941 | 0C 2942 | b1 K 2943 | b10 J 2944 | b11111101000 O 2945 | #161500 2946 | 1% 2947 | 1E 2948 | b1 L 2949 | b11111101000 P 2950 | #162000 2951 | 0% 2952 | 0E 2953 | b10011111 4 2954 | 0$ 2955 | 1# 2956 | b10 ! 2957 | 0> 2958 | 1= 2959 | 0; 2960 | 0D 2961 | 1C 2962 | b11 K 2963 | #162500 2964 | 1% 2965 | 1E 2966 | b11 L 2967 | b10 M 2968 | b10 K 2969 | #163000 2970 | 0% 2971 | 0E 2972 | b10100000 4 2973 | b10 " 2974 | b1010 ! 2975 | 1; 2976 | 0@ 2977 | b11 J 2978 | b11111110100 O 2979 | #163500 2980 | 1% 2981 | 1E 2982 | b10 L 2983 | b1010 M 2984 | b11111110100 P 2985 | #164000 2986 | 0% 2987 | 0E 2988 | b10100001 4 2989 | 1$ 2990 | 0# 2991 | b100 " 2992 | b1011 ! 2993 | 1> 2994 | 0A 2995 | 1@ 2996 | 1D 2997 | 0C 2998 | b11 K 2999 | #164500 3000 | 1% 3001 | 1E 3002 | b11 L 3003 | b100 N 3004 | b1 K 3005 | #165000 3006 | 0% 3007 | 0E 3008 | b10100010 4 3009 | 0$ 3010 | 1# 3011 | b111 " 3012 | b110 ! 3013 | 0> 3014 | 1< 3015 | 0; 3016 | 1B 3017 | 1A 3018 | 0D 3019 | 1C 3020 | b10 K 3021 | b100 J 3022 | b11111011100 O 3023 | #165500 3024 | 1% 3025 | 1E 3026 | b10 L 3027 | b110 M 3028 | b11111011100 P 3029 | #166000 3030 | 0% 3031 | 0E 3032 | b10100011 4 3033 | 1$ 3034 | 0# 3035 | b11 " 3036 | b101 ! 3037 | 1> 3038 | 0= 3039 | 0@ 3040 | 1D 3041 | 0C 3042 | b11 K 3043 | #166500 3044 | 1% 3045 | 1E 3046 | b11 L 3047 | b11 N 3048 | b1 K 3049 | #167000 3050 | 0% 3051 | 0E 3052 | b10100100 4 3053 | 0$ 3054 | 1# 3055 | b0 " 3056 | b1010 ! 3057 | 0> 3058 | 1= 3059 | 0< 3060 | 1; 3061 | 0B 3062 | 0A 3063 | 0D 3064 | 1C 3065 | b10 K 3066 | b101 J 3067 | b11111101110 O 3068 | #167500 3069 | 1% 3070 | 1E 3071 | b10 L 3072 | b1010 M 3073 | b11111101110 P 3074 | #168000 3075 | 0% 3076 | 0E 3077 | b10100101 4 3078 | 1$ 3079 | 0# 3080 | b1 " 3081 | b11 ! 3082 | 1> 3083 | 0; 3084 | 1B 3085 | 1D 3086 | 0C 3087 | b11 K 3088 | #168500 3089 | 1% 3090 | 1E 3091 | b11 L 3092 | b1 N 3093 | b1 K 3094 | #169000 3095 | 0% 3096 | 0E 3097 | b10100110 4 3098 | b1111 " 3099 | b110 ! 3100 | 0> 3101 | 1< 3102 | 1A 3103 | 1@ 3104 | 1? 3105 | b110 J 3106 | b11111101000 O 3107 | #169500 3108 | 1% 3109 | 1E 3110 | b1 L 3111 | b1111 N 3112 | b11111101000 P 3113 | #170000 3114 | 0% 3115 | 0E 3116 | b10100111 4 3117 | 0$ 3118 | 1# 3119 | b0 " 3120 | b1100 ! 3121 | 0= 3122 | 1; 3123 | 0B 3124 | 0A 3125 | 0@ 3126 | 0? 3127 | 0D 3128 | 1C 3129 | b11 K 3130 | #170500 3131 | 1% 3132 | 1E 3133 | b11 L 3134 | b1100 M 3135 | b10 K 3136 | #171000 3137 | 0% 3138 | 0E 3139 | b10101000 4 3140 | 1$ 3141 | 0# 3142 | b11 " 3143 | b100 ! 3144 | 0; 3145 | 1B 3146 | 1A 3147 | 1D 3148 | 0C 3149 | b1 K 3150 | b111 J 3151 | b11111101100 O 3152 | #171500 3153 | 1% 3154 | 1E 3155 | b1 L 3156 | b11 N 3157 | b11111101100 P 3158 | #172000 3159 | 0% 3160 | 0E 3161 | b10101001 4 3162 | 0$ 3163 | 1# 3164 | b101 " 3165 | b10 ! 3166 | 1= 3167 | 0< 3168 | 0A 3169 | 1@ 3170 | 0D 3171 | 1C 3172 | b11 K 3173 | #172500 3174 | 1% 3175 | 1E 3176 | b11 L 3177 | b10 M 3178 | b10 K 3179 | #173000 3180 | 0% 3181 | 0E 3182 | b10101010 4 3183 | 1$ 3184 | 0# 3185 | b110 ! 3186 | 1< 3187 | 1D 3188 | 0C 3189 | b1 K 3190 | b1000 J 3191 | b11111110010 O 3192 | #173500 3193 | 1% 3194 | 1E 3195 | b1 L 3196 | b101 N 3197 | b11111110010 P 3198 | 1I 3199 | #174000 3200 | 0% 3201 | 0E 3202 | b10101011 4 3203 | 0$ 3204 | 1# 3205 | b110 " 3206 | b101 ! 3207 | 1> 3208 | 0= 3209 | 0B 3210 | 1A 3211 | 0D 3212 | 1C 3213 | b11 K 3214 | b0 J 3215 | b0 O 3216 | #174500 3217 | 1% 3218 | 1E 3219 | b11 L 3220 | b101 M 3221 | 0I 3222 | 1H 3223 | b11111110010 G 3224 | 13 3225 | 02 3226 | 00 3227 | 0/ 3228 | 1. 3229 | 1- 3230 | b10 K 3231 | #175000 3232 | 0% 3233 | 0E 3234 | b111 6 3235 | b111 ' 3236 | b10101100 4 3237 | 0# 3238 | b11 " 3239 | 1B 3240 | 0@ 3241 | 0C 3242 | b0 K 3243 | b1 J 3244 | b11001 O 3245 | #175500 3246 | 1% 3247 | 1E 3248 | b0 L 3249 | b11001 P 3250 | 0H 3251 | 03 3252 | #176000 3253 | 0% 3254 | 0E 3255 | b10101101 4 3256 | b10 " 3257 | b1110 ! 3258 | 0> 3259 | 1= 3260 | 1; 3261 | 0B 3262 | #176500 3263 | 1% 3264 | 1E 3265 | #177000 3266 | 0% 3267 | 0E 3268 | b10101110 4 3269 | b101 " 3270 | 1B 3271 | 0A 3272 | 1@ 3273 | #177500 3274 | 1% 3275 | 1E 3276 | #178000 3277 | 0% 3278 | 0E 3279 | b10101111 4 3280 | 1$ 3281 | 1# 3282 | b110 " 3283 | b101 ! 3284 | 1> 3285 | 0= 3286 | 0; 3287 | 0B 3288 | 1A 3289 | 1D 3290 | 1C 3291 | b11 K 3292 | #178500 3293 | 1% 3294 | 1E 3295 | b11 L 3296 | b110 N 3297 | #179000 3298 | 0% 3299 | 0E 3300 | b10110000 4 3301 | 0$ 3302 | 0# 3303 | b1 " 3304 | b1011 ! 3305 | 1= 3306 | 0< 3307 | 1; 3308 | 1B 3309 | 0A 3310 | 0@ 3311 | 0D 3312 | 0C 3313 | b0 K 3314 | b10 J 3315 | b110111 O 3316 | #179500 3317 | 1% 3318 | 1E 3319 | b0 L 3320 | b110111 P 3321 | #180000 3322 | 0% 3323 | 0E 3324 | b10110001 4 3325 | 1$ 3326 | 1# 3327 | b110 " 3328 | b1101 ! 3329 | 0= 3330 | 1< 3331 | 0B 3332 | 1A 3333 | 1@ 3334 | 1D 3335 | 1C 3336 | b11 K 3337 | #180500 3338 | 1% 3339 | 1E 3340 | b11 L 3341 | b1101 M 3342 | #181000 3343 | 0% 3344 | 0E 3345 | b10110010 4 3346 | b1000 ! 3347 | 0> 3348 | 0< 3349 | b11 J 3350 | b100101 O 3351 | #181500 3352 | 1% 3353 | 1E 3354 | b1000 M 3355 | b100101 P 3356 | #182000 3357 | 0% 3358 | 0E 3359 | b10110011 4 3360 | 0# 3361 | b10 " 3362 | b1110 ! 3363 | 1= 3364 | 1< 3365 | 0@ 3366 | 0C 3367 | b1 K 3368 | b100 J 3369 | b11111110101 O 3370 | #182500 3371 | 1% 3372 | 1E 3373 | b1 L 3374 | b10 N 3375 | b11111110101 P 3376 | #183000 3377 | 0% 3378 | 0E 3379 | b10110100 4 3380 | 0$ 3381 | 1# 3382 | b101 " 3383 | b1100 ! 3384 | 0= 3385 | 1B 3386 | 0A 3387 | 1@ 3388 | 0D 3389 | 1C 3390 | b11 K 3391 | #183500 3392 | 1% 3393 | 1E 3394 | b11 L 3395 | b1100 M 3396 | b10 K 3397 | #184000 3398 | 0% 3399 | 0E 3400 | b10110101 4 3401 | 0# 3402 | b10 " 3403 | b111 ! 3404 | 1> 3405 | 1= 3406 | 0; 3407 | 0B 3408 | 1A 3409 | 0@ 3410 | 0C 3411 | b0 K 3412 | b101 J 3413 | b11111101101 O 3414 | #184500 3415 | 1% 3416 | 1E 3417 | b0 L 3418 | b11111101101 P 3419 | #185000 3420 | 0% 3421 | 0E 3422 | b10110110 4 3423 | 1# 3424 | b0 " 3425 | b110 ! 3426 | 0> 3427 | 0A 3428 | 1C 3429 | b10 K 3430 | #185500 3431 | 1% 3432 | 1E 3433 | b10 L 3434 | b110 M 3435 | #186000 3436 | 0% 3437 | 0E 3438 | b10110111 4 3439 | 0# 3440 | b11 " 3441 | b1011 ! 3442 | 1> 3443 | 0< 3444 | 1; 3445 | 1B 3446 | 1A 3447 | 0C 3448 | #186500 3449 | 1% 3450 | 1E 3451 | #187000 3452 | 0% 3453 | 0E 3454 | b10111000 4 3455 | 1$ 3456 | b101 " 3457 | b1010 ! 3458 | 0> 3459 | 0A 3460 | 1@ 3461 | 1D 3462 | b11 K 3463 | #187500 3464 | 1% 3465 | 1E 3466 | b11 L 3467 | b101 N 3468 | b1 K 3469 | #188000 3470 | 0% 3471 | 0E 3472 | b10111001 4 3473 | 0$ 3474 | b10 " 3475 | b110 ! 3476 | 1< 3477 | 0; 3478 | 0B 3479 | 1A 3480 | 0@ 3481 | 0D 3482 | b0 K 3483 | b110 J 3484 | b1011 O 3485 | #188500 3486 | 1% 3487 | 1E 3488 | b0 L 3489 | b1011 P 3490 | #189000 3491 | 0% 3492 | 0E 3493 | b10111010 4 3494 | 1# 3495 | b0 " 3496 | b0 ! 3497 | 0= 3498 | 0< 3499 | 0A 3500 | 1C 3501 | b10 K 3502 | #189500 3503 | 1% 3504 | 1E 3505 | b10 L 3506 | b0 M 3507 | #190000 3508 | 0% 3509 | 0E 3510 | b10111011 4 3511 | 0# 3512 | b11 " 3513 | b10 ! 3514 | 1= 3515 | 1B 3516 | 1A 3517 | 0C 3518 | #190500 3519 | 1% 3520 | 1E 3521 | #191000 3522 | 0% 3523 | 0E 3524 | b10111100 4 3525 | 1$ 3526 | b100 " 3527 | b1 ! 3528 | 1> 3529 | 0= 3530 | 0B 3531 | 0A 3532 | 1@ 3533 | 1D 3534 | b11 K 3535 | #191500 3536 | 1% 3537 | 1E 3538 | b11 L 3539 | b100 N 3540 | b1 K 3541 | #192000 3542 | 0% 3543 | 0E 3544 | b10111101 4 3545 | 0$ 3546 | b101 " 3547 | b110 ! 3548 | 0> 3549 | 1= 3550 | 1< 3551 | 1B 3552 | 0D 3553 | b0 K 3554 | b111 J 3555 | #192500 3556 | 1% 3557 | 1E 3558 | b0 L 3559 | #193000 3560 | 0% 3561 | 0E 3562 | b10111110 4 3563 | 1# 3564 | b0 " 3565 | b101 ! 3566 | 1> 3567 | 0= 3568 | 0B 3569 | 0@ 3570 | 1C 3571 | b10 K 3572 | #193500 3573 | 1% 3574 | 1E 3575 | b10 L 3576 | b101 M 3577 | #194000 3578 | 0% 3579 | 0E 3580 | b10111111 4 3581 | 0# 3582 | b10 " 3583 | b1011 ! 3584 | 1= 3585 | 0< 3586 | 1; 3587 | 1A 3588 | 0C 3589 | #194500 3590 | 1% 3591 | 1E 3592 | #195000 3593 | 0% 3594 | 0E 3595 | b11000000 4 3596 | 1$ 3597 | b1 " 3598 | b1101 ! 3599 | 0= 3600 | 1< 3601 | 1B 3602 | 0A 3603 | 1D 3604 | b11 K 3605 | #195500 3606 | 1% 3607 | 1E 3608 | b11 L 3609 | b1 N 3610 | b1 K 3611 | #196000 3612 | 0% 3613 | 0E 3614 | b11000001 4 3615 | b100 " 3616 | b0 ! 3617 | 0> 3618 | 0< 3619 | 0; 3620 | 0B 3621 | 1@ 3622 | b1000 J 3623 | b10000 O 3624 | #196500 3625 | 1% 3626 | 1E 3627 | b1 L 3628 | b100 N 3629 | b10000 P 3630 | 1I 3631 | #197000 3632 | 0% 3633 | 0E 3634 | b11000010 4 3635 | 0$ 3636 | b11 " 3637 | b110 ! 3638 | 1= 3639 | 1< 3640 | 1B 3641 | 1A 3642 | 0@ 3643 | 0D 3644 | b0 J 3645 | b0 O 3646 | #197500 3647 | 1% 3648 | 1E 3649 | 0I 3650 | 1H 3651 | b10000 G 3652 | 13 3653 | 01 3654 | 0- 3655 | 0, 3656 | 0+ 3657 | 0* 3658 | 0) 3659 | 0( 3660 | #198000 3661 | 0% 3662 | 0E 3663 | b1000 6 3664 | b1000 ' 3665 | b11000011 4 3666 | 1# 3667 | b10 " 3668 | b1000 ! 3669 | 0= 3670 | 0< 3671 | 1; 3672 | 0B 3673 | 1C 3674 | b11 K 3675 | #198500 3676 | 1% 3677 | 1E 3678 | b11 L 3679 | b1000 M 3680 | 0H 3681 | 03 3682 | b10 K 3683 | #199000 3684 | 0% 3685 | 0E 3686 | b11000100 4 3687 | 0# 3688 | b111 " 3689 | b1100 ! 3690 | 1< 3691 | 1B 3692 | 1@ 3693 | 0C 3694 | b0 K 3695 | b1 J 3696 | b11111100000 O 3697 | #199500 3698 | 1% 3699 | 1E 3700 | b0 L 3701 | b11111100000 P 3702 | #200000 3703 | 0% 3704 | 0E 3705 | b11000101 4 3706 | b0 " 3707 | b0 ! 3708 | 0< 3709 | 0; 3710 | 0B 3711 | 0A 3712 | 0@ 3713 | #200500 3714 | 1% 3715 | 1E 3716 | #201000 3717 | 0% 3718 | 0E 3719 | b11000110 4 3720 | 1# 3721 | b11 " 3722 | b10 ! 3723 | 1= 3724 | 1B 3725 | 1A 3726 | 1C 3727 | b10 K 3728 | #201500 3729 | 1% 3730 | 1E 3731 | b10 L 3732 | b10 M 3733 | #202000 3734 | 0% 3735 | 0E 3736 | b11000111 4 3737 | 1$ 3738 | 0# 3739 | b101 " 3740 | b11 ! 3741 | 1> 3742 | 0A 3743 | 1@ 3744 | 1D 3745 | 0C 3746 | b11 K 3747 | #202500 3748 | 1% 3749 | 1E 3750 | b11 L 3751 | b101 N 3752 | b1 K 3753 | #203000 3754 | 0% 3755 | 0E 3756 | b11001000 4 3757 | 0$ 3758 | 1# 3759 | b110 " 3760 | b10 ! 3761 | 0> 3762 | 0B 3763 | 1A 3764 | 0D 3765 | 1C 3766 | b10 K 3767 | b10 J 3768 | b11111101010 O 3769 | #203500 3770 | 1% 3771 | 1E 3772 | b10 L 3773 | b11111101010 P 3774 | #204000 3775 | 0% 3776 | 0E 3777 | b11001001 4 3778 | 1$ 3779 | 0# 3780 | b111 " 3781 | b1111 ! 3782 | 1> 3783 | 1< 3784 | 1; 3785 | 1B 3786 | 1D 3787 | 0C 3788 | b11 K 3789 | #204500 3790 | 1% 3791 | 1E 3792 | b11 L 3793 | b111 N 3794 | b1 K 3795 | #205000 3796 | 0% 3797 | 0E 3798 | b11001010 4 3799 | 0$ 3800 | b110 " 3801 | b1010 ! 3802 | 0> 3803 | 0< 3804 | 0B 3805 | 0D 3806 | b0 K 3807 | b11 J 3808 | b11111111000 O 3809 | #205500 3810 | 1% 3811 | 1E 3812 | b0 L 3813 | b11111111000 P 3814 | #206000 3815 | 0% 3816 | 0E 3817 | b11001011 4 3818 | 1$ 3819 | 1# 3820 | b11 " 3821 | 1B 3822 | 0@ 3823 | 1D 3824 | 1C 3825 | b11 K 3826 | #206500 3827 | 1% 3828 | 1E 3829 | b11 L 3830 | b1010 M 3831 | b11 N 3832 | #207000 3833 | 0% 3834 | 0E 3835 | b11001100 4 3836 | 0# 3837 | b111 " 3838 | b111 ! 3839 | 1> 3840 | 1< 3841 | 0; 3842 | 1@ 3843 | 0C 3844 | b1 K 3845 | b100 J 3846 | b11111100110 O 3847 | #207500 3848 | 1% 3849 | 1E 3850 | b1 L 3851 | b111 N 3852 | b11111100110 P 3853 | #208000 3854 | 0% 3855 | 0E 3856 | b11001101 4 3857 | 0$ 3858 | 1# 3859 | b100 " 3860 | b1001 ! 3861 | 0= 3862 | 0< 3863 | 1; 3864 | 0B 3865 | 0A 3866 | 0D 3867 | 1C 3868 | b11 K 3869 | #208500 3870 | 1% 3871 | 1E 3872 | b11 L 3873 | b1001 M 3874 | b10 K 3875 | #209000 3876 | 0% 3877 | 0E 3878 | b11001110 4 3879 | 0# 3880 | b1 " 3881 | b101 ! 3882 | 1< 3883 | 0; 3884 | 1B 3885 | 0@ 3886 | 0C 3887 | b0 K 3888 | b101 J 3889 | b11110110101 O 3890 | #209500 3891 | 1% 3892 | 1E 3893 | b0 L 3894 | b11110110101 P 3895 | #210000 3896 | 0% 3897 | 0E 3898 | b11001111 4 3899 | b110 " 3900 | b0 ! 3901 | 0> 3902 | 0< 3903 | 0B 3904 | 1A 3905 | 1@ 3906 | #210500 3907 | 1% 3908 | 1E 3909 | #211000 3910 | 0% 3911 | 0E 3912 | b11010000 4 3913 | b1111 " 3914 | b1111 ! 3915 | 1> 3916 | 1= 3917 | 1< 3918 | 1; 3919 | 1B 3920 | 1? 3921 | #211500 3922 | 1% 3923 | 1E 3924 | #212000 3925 | 0% 3926 | 0E 3927 | b11010001 4 3928 | 1$ 3929 | b101 " 3930 | b0 ! 3931 | 0> 3932 | 0= 3933 | 0< 3934 | 0; 3935 | 0A 3936 | 0? 3937 | 1D 3938 | b1 K 3939 | #212500 3940 | 1% 3941 | 1E 3942 | b1 L 3943 | b101 N 3944 | #213000 3945 | 0% 3946 | 0E 3947 | b11010010 4 3948 | 0$ 3949 | 1# 3950 | b100 " 3951 | b111 ! 3952 | 1> 3953 | 1= 3954 | 1< 3955 | 0B 3956 | 0D 3957 | 1C 3958 | b11 K 3959 | #213500 3960 | 1% 3961 | 1E 3962 | b11 L 3963 | b111 M 3964 | b10 K 3965 | #214000 3966 | 0% 3967 | 0E 3968 | b11010011 4 3969 | 0# 3970 | b0 " 3971 | b1101 ! 3972 | 0= 3973 | 1; 3974 | 0@ 3975 | 0C 3976 | b0 K 3977 | b110 J 3978 | b11111011000 O 3979 | #214500 3980 | 1% 3981 | 1E 3982 | b0 L 3983 | b11111011000 P 3984 | #215000 3985 | 0% 3986 | 0E 3987 | b11010100 4 3988 | b11 " 3989 | 1B 3990 | 1A 3991 | #215500 3992 | 1% 3993 | 1E 3994 | #216000 3995 | 0% 3996 | 0E 3997 | b11010101 4 3998 | b101 " 3999 | b1011 ! 4000 | 1= 4001 | 0< 4002 | 0A 4003 | 1@ 4004 | #216500 4005 | 1% 4006 | 1E 4007 | #217000 4008 | 0% 4009 | 0E 4010 | b11010110 4 4011 | 1$ 4012 | b0 " 4013 | b110 ! 4014 | 0> 4015 | 1< 4016 | 0; 4017 | 0B 4018 | 0@ 4019 | 1D 4020 | b1 K 4021 | #217500 4022 | 1% 4023 | 1E 4024 | b1 L 4025 | b0 N 4026 | #218000 4027 | 0% 4028 | 0E 4029 | b11010111 4 4030 | 0$ 4031 | 1# 4032 | b100 " 4033 | b1000 ! 4034 | 0= 4035 | 0< 4036 | 1; 4037 | 1@ 4038 | 0D 4039 | 1C 4040 | b11 K 4041 | #218500 4042 | 1% 4043 | 1E 4044 | b11 L 4045 | b1000 M 4046 | b10 K 4047 | #219000 4048 | 0% 4049 | 0E 4050 | b11011000 4 4051 | 1$ 4052 | b1 ! 4053 | 1> 4054 | 0; 4055 | 1D 4056 | b11 K 4057 | b111 J 4058 | #219500 4059 | 1% 4060 | 1E 4061 | b1 M 4062 | b100 N 4063 | #220000 4064 | 0% 4065 | 0E 4066 | b11011001 4 4067 | b10 " 4068 | b110 ! 4069 | 0> 4070 | 1= 4071 | 1< 4072 | 1A 4073 | 0@ 4074 | b1000 J 4075 | b11111011100 O 4076 | #220500 4077 | 1% 4078 | 1E 4079 | b110 M 4080 | b10 N 4081 | b11111011100 P 4082 | 1I 4083 | #221000 4084 | 0% 4085 | 0E 4086 | b11011010 4 4087 | 0# 4088 | b101 " 4089 | 1B 4090 | 0A 4091 | 1@ 4092 | 0C 4093 | b1 K 4094 | b1 J 4095 | b1100 O 4096 | #221500 4097 | 1% 4098 | 1E 4099 | b1 L 4100 | b101 N 4101 | b1100 P 4102 | 0I 4103 | 1H 4104 | b11111011100 G 4105 | 13 4106 | 10 4107 | 1/ 4108 | 1, 4109 | 1+ 4110 | 1* 4111 | 1) 4112 | 1( 4113 | #222000 4114 | 0% 4115 | 0E 4116 | b1001 6 4117 | b1001 ' 4118 | b11011011 4 4119 | 0$ 4120 | 1# 4121 | b100 " 4122 | 0B 4123 | 0D 4124 | 1C 4125 | b11 K 4126 | #222500 4127 | 1% 4128 | 1E 4129 | b11 L 4130 | 0H 4131 | 03 4132 | b10 K 4133 | #223000 4134 | 0% 4135 | 0E 4136 | b11011100 4 4137 | 0# 4138 | b1111 " 4139 | b1100 ! 4140 | 0= 4141 | 1; 4142 | 1B 4143 | 1A 4144 | 1? 4145 | 0C 4146 | b0 K 4147 | b10 J 4148 | b101010 O 4149 | #223500 4150 | 1% 4151 | 1E 4152 | b0 L 4153 | b101010 P 4154 | #224000 4155 | 0% 4156 | 0E 4157 | b11011101 4 4158 | b101 " 4159 | b1111 ! 4160 | 1> 4161 | 1= 4162 | 0A 4163 | 0? 4164 | #224500 4165 | 1% 4166 | 1E 4167 | #225000 4168 | 0% 4169 | 0E 4170 | b11011110 4 4171 | b110 " 4172 | 0B 4173 | 1A 4174 | #225500 4175 | 1% 4176 | 1E 4177 | #226000 4178 | 0% 4179 | 0E 4180 | b11011111 4 4181 | 1$ 4182 | 1# 4183 | b0 " 4184 | b1101 ! 4185 | 0= 4186 | 0A 4187 | 0@ 4188 | 1D 4189 | 1C 4190 | b11 K 4191 | #226500 4192 | 1% 4193 | 1E 4194 | b11 L 4195 | b1101 M 4196 | b0 N 4197 | #227000 4198 | 0% 4199 | 0E 4200 | b11100000 4 4201 | 0$ 4202 | b10 " 4203 | b11 ! 4204 | 1= 4205 | 0< 4206 | 0; 4207 | 1A 4208 | 0D 4209 | b10 K 4210 | b11 J 4211 | #227500 4212 | 1% 4213 | 1E 4214 | b10 L 4215 | b11 M 4216 | #228000 4217 | 0% 4218 | 0E 4219 | b11100001 4 4220 | 0# 4221 | b1111 " 4222 | b1001 ! 4223 | 0= 4224 | 1; 4225 | 1B 4226 | 1@ 4227 | 1? 4228 | 0C 4229 | #228500 4230 | 1% 4231 | 1E 4232 | #229000 4233 | 0% 4234 | 0E 4235 | b11100010 4 4236 | b1 " 4237 | b1000 ! 4238 | 0> 4239 | 0A 4240 | 0@ 4241 | 0? 4242 | #229500 4243 | 1% 4244 | 1E 4245 | #230000 4246 | 0% 4247 | 0E 4248 | b11100011 4 4249 | 1$ 4250 | b1111 " 4251 | b1110 ! 4252 | 1= 4253 | 1< 4254 | 1A 4255 | 1@ 4256 | 1? 4257 | 1D 4258 | b11 K 4259 | #230500 4260 | 1% 4261 | 1E 4262 | b11 L 4263 | b1111 N 4264 | b1 K 4265 | #231000 4266 | 0% 4267 | 0E 4268 | b11100100 4 4269 | 0$ 4270 | b111 " 4271 | 0? 4272 | 0D 4273 | b0 K 4274 | b100 J 4275 | b100111 O 4276 | #231500 4277 | 1% 4278 | 1E 4279 | b0 L 4280 | b100111 P 4281 | #232000 4282 | 0% 4283 | 0E 4284 | b11100101 4 4285 | 1# 4286 | b10 " 4287 | b1001 ! 4288 | 1> 4289 | 0= 4290 | 0< 4291 | 0B 4292 | 0@ 4293 | 1C 4294 | b10 K 4295 | #232500 4296 | 1% 4297 | 1E 4298 | b10 L 4299 | b1001 M 4300 | #233000 4301 | 0% 4302 | 0E 4303 | b11100110 4 4304 | 1$ 4305 | 0# 4306 | b0 ! 4307 | 0> 4308 | 0; 4309 | 1D 4310 | 0C 4311 | b11 K 4312 | #233500 4313 | 1% 4314 | 1E 4315 | b11 L 4316 | b10 N 4317 | b1 K 4318 | #234000 4319 | 0% 4320 | 0E 4321 | b11100111 4 4322 | 1# 4323 | b101 " 4324 | b11 ! 4325 | 1> 4326 | 1= 4327 | 1B 4328 | 0A 4329 | 1@ 4330 | 1C 4331 | b11 K 4332 | b101 J 4333 | b11001 O 4334 | #234500 4335 | 1% 4336 | 1E 4337 | b11 M 4338 | b101 N 4339 | b11001 P 4340 | #235000 4341 | 0% 4342 | 0E 4343 | b11101000 4 4344 | 0# 4345 | b11 " 4346 | b1110 ! 4347 | 0> 4348 | 1< 4349 | 1; 4350 | 1A 4351 | 0@ 4352 | 0C 4353 | b1 K 4354 | b110 J 4355 | b101000 O 4356 | #235500 4357 | 1% 4358 | 1E 4359 | b1 L 4360 | b11 N 4361 | b101000 P 4362 | #236000 4363 | 0% 4364 | 0E 4365 | b11101001 4 4366 | 0$ 4367 | b0 " 4368 | b111 ! 4369 | 1> 4370 | 0; 4371 | 0B 4372 | 0A 4373 | 0D 4374 | #236500 4375 | 1% 4376 | 1E 4377 | #237000 4378 | 0% 4379 | 0E 4380 | b11101010 4 4381 | 1# 4382 | b1111 " 4383 | b101 ! 4384 | 0= 4385 | 1B 4386 | 1A 4387 | 1@ 4388 | 1? 4389 | 1C 4390 | b11 K 4391 | #237500 4392 | 1% 4393 | 1E 4394 | b11 L 4395 | b101 M 4396 | b10 K 4397 | #238000 4398 | 0% 4399 | 0E 4400 | b11101011 4 4401 | 0# 4402 | b11 " 4403 | b11 ! 4404 | 1= 4405 | 0< 4406 | 0@ 4407 | 0? 4408 | 0C 4409 | b0 K 4410 | b111 J 4411 | b110111 O 4412 | #238500 4413 | 1% 4414 | 1E 4415 | b0 L 4416 | b110111 P 4417 | #239000 4418 | 0% 4419 | 0E 4420 | b11101100 4 4421 | b101 " 4422 | b1011 ! 4423 | 1; 4424 | 0A 4425 | 1@ 4426 | #239500 4427 | 1% 4428 | 1E 4429 | #240000 4430 | 0% 4431 | 0E 4432 | b11101101 4 4433 | 1# 4434 | b100 " 4435 | b0 ! 4436 | 0> 4437 | 0= 4438 | 0; 4439 | 0B 4440 | 1C 4441 | b10 K 4442 | #240500 4443 | 1% 4444 | 1E 4445 | b10 L 4446 | b0 M 4447 | #241000 4448 | 0% 4449 | 0E 4450 | b11101110 4 4451 | 0# 4452 | b10 " 4453 | b11 ! 4454 | 1> 4455 | 1= 4456 | 1A 4457 | 0@ 4458 | 0C 4459 | #241500 4460 | 1% 4461 | 1E 4462 | #242000 4463 | 0% 4464 | 0E 4465 | b11101111 4 4466 | 1$ 4467 | b11 " 4468 | b101 ! 4469 | 0= 4470 | 1< 4471 | 1B 4472 | 1D 4473 | b11 K 4474 | #242500 4475 | 1% 4476 | 1E 4477 | b11 L 4478 | b1 K 4479 | #243000 4480 | 0% 4481 | 0E 4482 | b11110000 4 4483 | 0$ 4484 | b0 " 4485 | b0 ! 4486 | 0> 4487 | 0< 4488 | 0B 4489 | 0A 4490 | 0D 4491 | b0 K 4492 | b1000 J 4493 | #243500 4494 | 1% 4495 | 1E 4496 | b0 L 4497 | 1I 4498 | #244000 4499 | 0% 4500 | 0E 4501 | b11110001 4 4502 | b0 J 4503 | b0 O 4504 | #244500 4505 | 1% 4506 | 1E 4507 | 0I 4508 | 1H 4509 | b110111 G 4510 | 13 4511 | 12 4512 | 11 4513 | 0/ 4514 | 1- 4515 | 0, 4516 | 0+ 4517 | 0* 4518 | 0) 4519 | 0( 4520 | #245000 4521 | 0% 4522 | 0E 4523 | b1010 6 4524 | b1010 ' 4525 | b11110010 4 4526 | #245500 4527 | 1% 4528 | 1E 4529 | 0H 4530 | 03 4531 | #246000 4532 | 0% 4533 | 0E 4534 | b11110011 4 4535 | #246500 4536 | 1% 4537 | 1E 4538 | #247000 4539 | 0% 4540 | 0E 4541 | b11110100 4 4542 | #247500 4543 | 1% 4544 | 1E 4545 | #248000 4546 | 0% 4547 | 0E 4548 | b11110101 4 4549 | #248500 4550 | 1% 4551 | 1E 4552 | #249000 4553 | 0% 4554 | 0E 4555 | b11110110 4 4556 | #249500 4557 | 1% 4558 | 1E 4559 | #250000 4560 | 0% 4561 | 0E 4562 | b11110111 4 4563 | #250500 4564 | 1% 4565 | 1E 4566 | #251000 4567 | 0% 4568 | 0E 4569 | b11111000 4 4570 | #251500 4571 | 1% 4572 | 1E 4573 | #252000 4574 | 0% 4575 | 0E 4576 | b11111001 4 4577 | #252500 4578 | 1% 4579 | 1E 4580 | #253000 4581 | 0% 4582 | 0E 4583 | #253500 4584 | 1% 4585 | 1E 4586 | #254000 4587 | 0% 4588 | 0E 4589 | #254500 4590 | 1% 4591 | 1E 4592 | -------------------------------------------------------------------------------- /mac.mpf: -------------------------------------------------------------------------------- 1 | ; vsim modelsim.ini file, version 10.4 2 | [Version] 3 | INIVersion = "10.4a" 4 | 5 | ; Copyright 1991-2015 Mentor Graphics Corporation 6 | ; 7 | ; All Rights Reserved. 8 | ; 9 | ; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF 10 | ; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS. 11 | ; 12 | 13 | [Library] 14 | std = $MODEL_TECH/../std 15 | ieee = $MODEL_TECH/../ieee 16 | vital2000 = $MODEL_TECH/../vital2000 17 | ; 18 | ; VITAL concerns: 19 | ; 20 | ; The library ieee contains (among other packages) the packages of the 21 | ; VITAL 2000 standard. When a design uses VITAL 2000 exclusively, it should use 22 | ; the physical library ieee (recommended), or use the physical library 23 | ; vital2000, but not both. The design can use logical library ieee and/or 24 | ; vital2000 as long as each of these maps to the same physical library, either 25 | ; ieee or vital2000. 26 | ; 27 | ; A design using the 1995 version of the VITAL packages, whether or not 28 | ; it also uses the 2000 version of the VITAL packages, must have logical library 29 | ; name ieee mapped to physical library vital1995. (A design cannot use library 30 | ; vital1995 directly because some packages in this library use logical name ieee 31 | ; when referring to the other packages in the library.) The design source 32 | ; should use logical name ieee when referring to any packages there except the 33 | ; VITAL 2000 packages. Any VITAL 2000 present in the design must use logical 34 | ; name vital2000 (mapped to physical library vital2000) to refer to those 35 | ; packages. 36 | ; ieee = $MODEL_TECH/../vital1995 37 | ; 38 | ; For compatiblity with previous releases, logical library name vital2000 maps 39 | ; to library vital2000 (a different library than library ieee, containing the 40 | ; same packages). 41 | ; A design should not reference VITAL from both the ieee library and the 42 | ; vital2000 library because the vital packages are effectively different. 43 | ; A design that references both the ieee and vital2000 libraries must have 44 | ; both logical names ieee and vital2000 mapped to the same library, either of 45 | ; these: 46 | ; $MODEL_TECH/../ieee 47 | ; $MODEL_TECH/../vital2000 48 | ; 49 | verilog = $MODEL_TECH/../verilog 50 | std_developerskit = $MODEL_TECH/../std_developerskit 51 | synopsys = $MODEL_TECH/../synopsys 52 | modelsim_lib = $MODEL_TECH/../modelsim_lib 53 | sv_std = $MODEL_TECH/../sv_std 54 | mtiAvm = $MODEL_TECH/../avm 55 | mtiRnm = $MODEL_TECH/../rnm 56 | mtiOvm = $MODEL_TECH/../ovm-2.1.2 57 | mtiUvm = $MODEL_TECH/../uvm-1.1d 58 | mtiUPF = $MODEL_TECH/../upf_lib 59 | mtiPA = $MODEL_TECH/../pa_lib 60 | floatfixlib = $MODEL_TECH/../floatfixlib 61 | mc2_lib = $MODEL_TECH/../mc2_lib 62 | osvvm = $MODEL_TECH/../osvvm 63 | 64 | ; added mapping for ADMS 65 | mgc_ams = $MODEL_TECH/../mgc_ams 66 | ieee_env = $MODEL_TECH/../ieee_env 67 | 68 | ;vhdl_psl_checkers = $MODEL_TECH/../vhdl_psl_checkers // Source files only for this release 69 | ;verilog_psl_checkers = $MODEL_TECH/../verilog_psl_checkers // Source files only for this release 70 | ;mvc_lib = $MODEL_TECH/../mvc_lib 71 | infact = $MODEL_TECH/../infact 72 | 73 | 74 | vhdlopt_lib = $MODEL_TECH/../vhdlopt_lib 75 | work = work 76 | [DefineOptionset] 77 | ; Define optionset entries for the various compilers, vmake, and vsim. 78 | ; These option sets can be used with the "-optionset " syntax. 79 | ; i.e. 80 | ; vlog -optionset COMPILEDEBUG top.sv 81 | ; vsim -optionset UVMDEBUG my_top 82 | ; 83 | ; Following are some useful examples. 84 | 85 | ; define a vsim optionset for uvm debugging 86 | UVMDEBUG = -uvmcontrol=all -msgmode both -displaymsgmode both -classdebug -onfinish stop 87 | 88 | ; define a vopt optionset for debugging 89 | VOPTDEBUG = +acc -debugdb 90 | 91 | 92 | [vcom] 93 | ; VHDL93 variable selects language version as the default. 94 | ; Default is VHDL-2002. 95 | ; Value of 0 or 1987 for VHDL-1987. 96 | ; Value of 1 or 1993 for VHDL-1993. 97 | ; Default or value of 2 or 2002 for VHDL-2002. 98 | ; Value of 3 or 2008 for VHDL-2008 99 | ; Value of 4 or ams99 for VHDL-AMS-1999 100 | ; Value of 5 or ams07 for VHDL-AMS-2007 101 | VHDL93 = 2002 102 | 103 | ; Ignore VHDL-2008 declaration of REAL_VECTOR in package STANDARD. Default is off. 104 | ; ignoreStandardRealVector = 1 105 | 106 | ; Show source line containing error. Default is off. 107 | ; Show_source = 1 108 | 109 | ; Turn off unbound-component warnings. Default is on. 110 | ; Show_Warning1 = 0 111 | 112 | ; Turn off process-without-a-wait-statement warnings. Default is on. 113 | ; Show_Warning2 = 0 114 | 115 | ; Turn off null-range warnings. Default is on. 116 | ; Show_Warning3 = 0 117 | 118 | ; Turn off no-space-in-time-literal warnings. Default is on. 119 | ; Show_Warning4 = 0 120 | 121 | ; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on. 122 | ; Show_Warning5 = 0 123 | 124 | ; Turn off optimization for IEEE std_logic_1164 package. Default is on. 125 | ; Optimize_1164 = 0 126 | 127 | ; Enable compiler statistics. Specify one or more arguments: 128 | ; [all,none,time,cmd,msg,perf,verbose,list] 129 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 130 | ; Stats = time,cmd,msg 131 | 132 | ; Turn on resolving of ambiguous function overloading in favor of the 133 | ; "explicit" function declaration (not the one automatically created by 134 | ; the compiler for each type declaration). Default is off. 135 | ; The .ini file has Explicit enabled so that std_logic_signed/unsigned 136 | ; will match the behavior of synthesis tools. 137 | Explicit = 1 138 | 139 | ; Turn off acceleration of the VITAL packages. Default is to accelerate. 140 | ; NoVital = 1 141 | 142 | ; Turn off VITAL compliance checking. Default is checking on. 143 | ; NoVitalCheck = 1 144 | 145 | ; Ignore VITAL compliance checking errors. Default is to not ignore. 146 | ; IgnoreVitalErrors = 1 147 | 148 | ; Turn off VITAL compliance checking warnings. Default is to show warnings. 149 | ; Show_VitalChecksWarnings = 0 150 | 151 | ; Turn off PSL assertion warning messages. Default is to show warnings. 152 | ; Show_PslChecksWarnings = 0 153 | 154 | ; Enable parsing of embedded PSL assertions. Default is enabled. 155 | ; EmbeddedPsl = 0 156 | 157 | ; Keep silent about case statement static warnings. 158 | ; Default is to give a warning. 159 | ; NoCaseStaticError = 1 160 | 161 | ; Keep silent about warnings caused by aggregates that are not locally static. 162 | ; Default is to give a warning. 163 | ; NoOthersStaticError = 1 164 | 165 | ; Treat as errors: 166 | ; case statement static warnings 167 | ; warnings caused by aggregates that are not locally static 168 | ; Overrides NoCaseStaticError, NoOthersStaticError settings. 169 | ; PedanticErrors = 1 170 | 171 | ; Turn off inclusion of debugging info within design units. 172 | ; Default is to include debugging info. 173 | ; NoDebug = 1 174 | 175 | ; Turn off "Loading..." messages. Default is messages on. 176 | ; Quiet = 1 177 | 178 | ; Turn on some limited synthesis rule compliance checking. Checks only: 179 | ; -- signals used (read) by a process must be in the sensitivity list 180 | ; CheckSynthesis = 1 181 | 182 | ; Activate optimizations on expressions that do not involve signals, 183 | ; waits, or function/procedure/task invocations. Default is off. 184 | ; ScalarOpts = 1 185 | 186 | ; Turns on lint-style checking. 187 | ; Show_Lint = 1 188 | 189 | ; Require the user to specify a configuration for all bindings, 190 | ; and do not generate a compile time default binding for the 191 | ; component. This will result in an elaboration error of 192 | ; 'component not bound' if the user fails to do so. Avoids the rare 193 | ; issue of a false dependency upon the unused default binding. 194 | ; RequireConfigForAllDefaultBinding = 1 195 | 196 | ; Perform default binding at compile time. 197 | ; Default is to do default binding at load time. 198 | ; BindAtCompile = 1; 199 | 200 | ; Inhibit range checking on subscripts of arrays. Range checking on 201 | ; scalars defined with subtypes is inhibited by default. 202 | ; NoIndexCheck = 1 203 | 204 | ; Inhibit range checks on all (implicit and explicit) assignments to 205 | ; scalar objects defined with subtypes. 206 | ; NoRangeCheck = 1 207 | 208 | ; Set the prefix to be honored for synthesis/coverage pragma recognition. 209 | ; Default is "". 210 | ; AddPragmaPrefix = "" 211 | 212 | ; Ignore synthesis and coverage pragmas with this prefix. 213 | ; Default is "". 214 | ; IgnorePragmaPrefix = "" 215 | 216 | ; Turn on code coverage in VHDL design units. Default is off. 217 | ; Coverage = sbceft 218 | 219 | ; Turn off code coverage in VHDL subprograms. Default is on. 220 | ; CoverSub = 0 221 | 222 | ; Automatically exclude VHDL case statement OTHERS choice branches. 223 | ; This includes OTHERS choices in selected signal assigment statements. 224 | ; Default is to not exclude. 225 | ; CoverExcludeDefault = 1 226 | 227 | ; Control compiler and VOPT optimizations that are allowed when 228 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 229 | ; CoverOpt = 3 230 | 231 | ; Turn on or off clkOpt optimization for code coverage. Default is on. 232 | ; CoverClkOpt = 1 233 | 234 | ; Turn on or off clkOpt optimization builtins for code coverage. Default is on. 235 | ; CoverClkOptBuiltins = 0 236 | 237 | ; Inform code coverage optimizations to respect VHDL 'H' and 'L' 238 | ; values on signals in conditions and expressions, and to not automatically 239 | ; convert them to '1' and '0'. Default is to not convert. 240 | ; CoverRespectHandL = 0 241 | 242 | ; Increase or decrease the maximum number of rows allowed in a UDP table 243 | ; implementing a VHDL condition coverage or expression coverage expression. 244 | ; More rows leads to a longer compile time, but more expressions covered. 245 | ; CoverMaxUDPRows = 192 246 | 247 | ; Increase or decrease the maximum number of input patterns that are present 248 | ; in FEC table. This leads to a longer compile time with more expressions 249 | ; covered with FEC metric. 250 | ; CoverMaxFECRows = 192 251 | 252 | ; Increase or decrease the limit on the size of expressions and conditions 253 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 254 | ; to higher compile, optimize and simulation time, but more expressions and 255 | ; conditions are considered for coverage in the design. FecUdpEffort can 256 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 257 | ; 1 - (low) Only small expressions and conditions considered for coverage. 258 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 259 | ; 3 - (high) Very large expressions and conditions considered for coverage. 260 | ; The default setting is 1 (low). 261 | ; FecUdpEffort = 1 262 | 263 | ; Enable or disable Focused Expression Coverage analysis for conditions and 264 | ; expressions. Focused Expression Coverage data is provided by default when 265 | ; expression and/or condition coverage is active. 266 | ; CoverFEC = 0 267 | 268 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 269 | ; UDP Coverage data is disabled by default when expression and/or condition 270 | ; coverage is active. 271 | ; CoverUDP = 1 272 | 273 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 274 | ; Disabling this would convert non-masking conditions in FEC tables to matching 275 | ; input patterns. 276 | ; CoverREC = 1 277 | 278 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 279 | ; for expression/condition coverage. 280 | ; NOTE: Enabling this may have a negative impact on simulation performance. 281 | ; CoverExpandReductionPrefix = 0 282 | 283 | ; Enable or disable short circuit evaluation of conditions and expressions when 284 | ; condition or expression coverage is active. Short circuit evaluation is enabled 285 | ; by default. 286 | ; CoverShortCircuit = 0 287 | 288 | ; Enable code coverage reporting of code that has been optimized away. 289 | ; The default is not to report. 290 | ; CoverReportCancelled = 1 291 | 292 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 293 | ; Default is no deglitching. 294 | ; CoverDeglitchOn = 1 295 | 296 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 297 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 298 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 299 | ; CoverDeglitchPeriod = 0 300 | 301 | ; Use this directory for compiler temporary files instead of "work/_temp" 302 | ; CompilerTempDir = /tmp 303 | 304 | ; Set this to cause the compilers to force data to be committed to disk 305 | ; when the files are closed. 306 | ; SyncCompilerFiles = 1 307 | 308 | ; Add VHDL-AMS declarations to package STANDARD 309 | ; Default is not to add 310 | ; AmsStandard = 1 311 | 312 | ; Range and length checking will be performed on array indices and discrete 313 | ; ranges, and when violations are found within subprograms, errors will be 314 | ; reported. Default is to issue warnings for violations, because subprograms 315 | ; may not be invoked. 316 | ; NoDeferSubpgmCheck = 0 317 | 318 | ; Turn ON detection of FSMs having single bit current state variable. 319 | ; FsmSingle = 1 320 | 321 | ; Turn off reset state transitions in FSM. 322 | ; FsmResetTrans = 0 323 | 324 | ; Turn ON detection of FSM Implicit Transitions. 325 | ; FsmImplicitTrans = 1 326 | 327 | ; Controls whether or not to show immediate assertions with constant expressions 328 | ; in GUI/report/UCDB etc. By default, immediate assertions with constant 329 | ; expressions are shown in GUI/report/UCDB etc. This does not affect 330 | ; evaluation of immediate assertions. 331 | ; ShowConstantImmediateAsserts = 0 332 | 333 | ; Controls how VHDL basic identifiers are stored with the design unit. 334 | ; Does not make the language case-sensitive, affects only how declarations 335 | ; declared with basic identifiers have their names stored and printed 336 | ; (in the GUI, examine, etc.). 337 | ; Default is to preserve the case as originally depicted in the VHDL source. 338 | ; Value of 0 indicates to change all basic identifiers to lower case. 339 | ; PreserveCase = 0 340 | 341 | ; For Configuration Declarations, controls the effect that USE clauses have 342 | ; on visibility inside the configuration items being configured. If 1 343 | ; (the default), then use pre-10.0 behavior. If 0, then for stricter LRM-compliance, 344 | ; extend the visibility of objects made visible through USE clauses into nested 345 | ; component configurations. 346 | ; OldVHDLConfigurationVisibility = 0 347 | 348 | ; Allows VHDL configuration declarations to be in a different library from 349 | ; the corresponding configured entity. Default is to not allow this for 350 | ; stricter LRM-compliance. 351 | ; SeparateConfigLibrary = 1; 352 | 353 | ; Determine how mode OUT subprogram parameters of type array and record are treated. 354 | ; If 0 (the default), then only VHDL 2008 will do this initialization. 355 | ; If 1, always initialize the mode OUT parameter to its default value. 356 | ; If 2, do not initialize the mode OUT out parameter. 357 | ; Note that prior to release 10.1, all language versions did not initialize mode 358 | ; OUT array and record type parameters, unless overridden here via this mechanism. 359 | ; In release 10.1 and later, only files compiled with VHDL 2008 will cause this 360 | ; initialization, unless overridden here. 361 | ; InitOutCompositeParam = 0 362 | 363 | ; Generate symbols debugging database in only some special cases to save on 364 | ; the number of files in the library. For other design-units, this database is 365 | ; generated on-demand in vsim. 366 | ; Default is to to generate debugging database for all design-units. 367 | ; SmartDbgSym = 1 368 | 369 | ; Enable or disable automatic creation of missing libraries. 370 | ; Default is 1 (enabled) 371 | ; CreateLib = 1 372 | 373 | [vlog] 374 | ; Turn off inclusion of debugging info within design units. 375 | ; Default is to include debugging info. 376 | ; NoDebug = 1 377 | 378 | ; Turn on `protect compiler directive processing. 379 | ; Default is to ignore `protect directives. 380 | ; Protect = 1 381 | 382 | ; Turn off "Loading..." messages. Default is messages on. 383 | ; Quiet = 1 384 | 385 | ; Turn on Verilog hazard checking (order-dependent accessing of global vars). 386 | ; Default is off. 387 | ; Hazard = 1 388 | 389 | ; Turn on converting regular Verilog identifiers to uppercase. Allows case 390 | ; insensitivity for module names. Default is no conversion. 391 | ; UpCase = 1 392 | 393 | ; Activate optimizations on expressions that do not involve signals, 394 | ; waits, or function/procedure/task invocations. Default is off. 395 | ; ScalarOpts = 1 396 | 397 | ; Turns on lint-style checking. 398 | ; Show_Lint = 1 399 | 400 | ; Show source line containing error. Default is off. 401 | ; Show_source = 1 402 | 403 | ; Turn on bad option warning. Default is off. 404 | ; Show_BadOptionWarning = 1 405 | 406 | ; Revert back to IEEE 1364-1995 syntax, default is 0 (off). 407 | ; vlog95compat = 1 408 | 409 | ; Turn off PSL warning messages. Default is to show warnings. 410 | ; Show_PslChecksWarnings = 0 411 | 412 | ; Enable parsing of embedded PSL assertions. Default is enabled. 413 | ; EmbeddedPsl = 0 414 | 415 | ; Enable compiler statistics. Specify one or more arguments: 416 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 417 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 418 | ; Stats = time,cmd,msg 419 | 420 | ; Set the threshold for automatically identifying sparse Verilog memories. 421 | ; A memory with depth equal to or more than the sparse memory threshold gets 422 | ; marked as sparse automatically, unless specified otherwise in source code 423 | ; or by +nosparse commandline option of vlog or vopt. 424 | ; The default is 1M. (i.e. memories with depth equal 425 | ; to or greater than 1M are marked as sparse) 426 | ; SparseMemThreshold = 1048576 427 | 428 | ; Set the prefix to be honored for synthesis and coverage pragma recognition. 429 | ; Default is "". 430 | ; AddPragmaPrefix = "" 431 | 432 | ; Ignore synthesis and coverage pragmas with this prefix. 433 | ; Default is "". 434 | ; IgnorePragmaPrefix = "" 435 | 436 | ; Set the option to treat all files specified in a vlog invocation as a 437 | ; single compilation unit. The default value is set to 0 which will treat 438 | ; each file as a separate compilation unit as specified in the P1800 draft standard. 439 | ; MultiFileCompilationUnit = 1 440 | 441 | ; Turn on code coverage in Verilog design units. Default is off. 442 | ; Coverage = sbceft 443 | 444 | ; Automatically exclude Verilog case statement default branches. 445 | ; Default is to not automatically exclude defaults. 446 | ; CoverExcludeDefault = 1 447 | 448 | ; Increase or decrease the maximum number of rows allowed in a UDP table 449 | ; implementing a VHDL condition coverage or expression coverage expression. 450 | ; More rows leads to a longer compile time, but more expressions covered. 451 | ; CoverMaxUDPRows = 192 452 | 453 | ; Increase or decrease the maximum number of input patterns that are present 454 | ; in FEC table. This leads to a longer compile time with more expressions 455 | ; covered with FEC metric. 456 | ; CoverMaxFECRows = 192 457 | 458 | ; Increase or decrease the limit on the size of expressions and conditions 459 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 460 | ; to higher compile, optimize and simulation time, but more expressions and 461 | ; conditions are considered for coverage in the design. FecUdpEffort can 462 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 463 | ; 1 - (low) Only small expressions and conditions considered for coverage. 464 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 465 | ; 3 - (high) Very large expressions and conditions considered for coverage. 466 | ; The default setting is 1 (low). 467 | ; FecUdpEffort = 1 468 | 469 | ; Enable or disable Focused Expression Coverage analysis for conditions and 470 | ; expressions. Focused Expression Coverage data is provided by default when 471 | ; expression and/or condition coverage is active. 472 | ; CoverFEC = 0 473 | 474 | ; Enable or disable UDP Coverage analysis for conditions and expressions. 475 | ; UDP Coverage data is disabled by default when expression and/or condition 476 | ; coverage is active. 477 | ; CoverUDP = 1 478 | 479 | ; Enable or disable Rapid Expression Coverage mode for conditions and expressions. 480 | ; Disabling this would convert non-masking conditions in FEC tables to matching 481 | ; input patterns. 482 | ; CoverREC = 1 483 | 484 | ; Enable or disable bit-blasting multi-bit operands of reduction prefix expressions 485 | ; for expression/condition coverage. 486 | ; NOTE: Enabling this may have a negative impact on simulation performance. 487 | ; CoverExpandReductionPrefix = 0 488 | 489 | ; Enable or disable short circuit evaluation of conditions and expressions when 490 | ; condition or expression coverage is active. Short circuit evaluation is enabled 491 | ; by default. 492 | ; CoverShortCircuit = 0 493 | 494 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 495 | ; Default is no deglitching. 496 | ; CoverDeglitchOn = 1 497 | 498 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 499 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 500 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 501 | ; CoverDeglitchPeriod = 0 502 | 503 | ; Turn on code coverage in VLOG `celldefine modules, modules containing 504 | ; specify blocks, and modules included using vlog -v and -y. Default is off. 505 | ; CoverCells = 1 506 | 507 | ; Enable code coverage reporting of code that has been optimized away. 508 | ; The default is not to report. 509 | ; CoverReportCancelled = 1 510 | 511 | ; Control compiler and VOPT optimizations that are allowed when 512 | ; code coverage is on. This is a number from 0 to 5, with the following 513 | ; meanings (the default is 3): 514 | ; 5 -- All allowable optimizations are on. 515 | ; 4 -- Turn off removing unreferenced code. 516 | ; 3 -- Turn off process, always block and if statement merging. 517 | ; 2 -- Turn off expression optimization, converting primitives 518 | ; to continuous assignments, VHDL subprogram inlining. 519 | ; and VHDL clkOpt (converting FF's to builtins). 520 | ; 1 -- Turn off continuous assignment optimizations and clock suppression. 521 | ; 0 -- Turn off Verilog module inlining and VHDL arch inlining. 522 | ; HOWEVER, if fsm coverage is turned on, optimizations will be forced to 523 | ; level 3, with also turning off converting primitives to continuous assigns. 524 | ; CoverOpt = 3 525 | 526 | ; Specify the override for the default value of "cross_num_print_missing" 527 | ; option for the Cross in Covergroups. If not specified then LRM default 528 | ; value of 0 (zero) is used. This is a compile time option. 529 | ; SVCrossNumPrintMissingDefault = 0 530 | 531 | ; Setting following to 1 would cause creation of variables which 532 | ; would represent the value of Coverpoint expressions. This is used 533 | ; in conjunction with "SVCoverpointExprVariablePrefix" option 534 | ; in the modelsim.ini 535 | ; EnableSVCoverpointExprVariable = 0 536 | 537 | ; Specify the override for the prefix used in forming the variable names 538 | ; which represent the Coverpoint expressions. This is used in conjunction with 539 | ; "EnableSVCoverpointExprVariable" option of the modelsim.ini 540 | ; The default prefix is "expr". 541 | ; The variable name is 542 | ; variable name => _ 543 | ; SVCoverpointExprVariablePrefix = expr 544 | 545 | ; Override for the default value of the SystemVerilog covergroup, 546 | ; coverpoint, and cross option.goal (defined to be 100 in the LRM). 547 | ; NOTE: It does not override specific assignments in SystemVerilog 548 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupGoal" 549 | ; in the [vsim] section can override this value. 550 | ; SVCovergroupGoalDefault = 100 551 | 552 | ; Override for the default value of the SystemVerilog covergroup, 553 | ; coverpoint, and cross type_option.goal (defined to be 100 in the LRM) 554 | ; NOTE: It does not override specific assignments in SystemVerilog 555 | ; source code. NOTE: The modelsim.ini variable "SVCovergroupTypeGoal" 556 | ; in the [vsim] section can override this value. 557 | ; SVCovergroupTypeGoalDefault = 100 558 | 559 | ; Specify the override for the default value of "strobe" option for the 560 | ; Covergroup Type. This is a compile time option which forces "strobe" to 561 | ; a user specified default value and supersedes SystemVerilog specified 562 | ; default value of '0'(zero). NOTE: This can be overriden by a runtime 563 | ; modelsim.ini variable "SVCovergroupStrobe" in the [vsim] section. 564 | ; SVCovergroupStrobeDefault = 0 565 | 566 | ; Specify the override for the default value of "per_instance" option for the 567 | ; Covergroup variables. This is a compile time option which forces "per_instance" 568 | ; to a user specified default value and supersedes SystemVerilog specified 569 | ; default value of '0'(zero). 570 | ; SVCovergroupPerInstanceDefault = 0 571 | 572 | ; Specify the override for the default value of "get_inst_coverage" option for the 573 | ; Covergroup variables. This is a compile time option which forces 574 | ; "get_inst_coverage" to a user specified default value and supersedes 575 | ; SystemVerilog specified default value of '0'(zero). 576 | ; SVCovergroupGetInstCoverageDefault = 0 577 | 578 | ; 579 | ; A space separated list of resource libraries that contain precompiled 580 | ; packages. The behavior is identical to using the "-L" switch. 581 | ; 582 | ; LibrarySearchPath = [ ...] 583 | LibrarySearchPath = mtiAvm mtiRnm mtiOvm mtiUvm mtiUPF infact 584 | 585 | ; The behavior is identical to the "-mixedansiports" switch. Default is off. 586 | ; MixedAnsiPorts = 1 587 | 588 | ; Enable SystemVerilog 3.1a $typeof() function. Default is off. 589 | ; EnableTypeOf = 1 590 | 591 | ; Only allow lower case pragmas. Default is disabled. 592 | ; AcceptLowerCasePragmaOnly = 1 593 | 594 | ; Set the maximum depth permitted for a recursive include file nesting. 595 | ; IncludeRecursionDepthMax = 5 596 | 597 | ; Turn ON detection of FSMs having single bit current state variable. 598 | ; FsmSingle = 1 599 | 600 | ; Turn off reset state transitions in FSM. 601 | ; FsmResetTrans = 0 602 | 603 | ; Turn off detections of FSMs having x-assignment. 604 | ; FsmXAssign = 0 605 | 606 | ; Turn ON detection of FSM Implicit Transitions. 607 | ; FsmImplicitTrans = 1 608 | 609 | ; List of file suffixes which will be read as SystemVerilog. White space 610 | ; in extensions can be specified with a back-slash: "\ ". Back-slashes 611 | ; can be specified with two consecutive back-slashes: "\\"; 612 | ; SvFileSuffixes = sv svp svh 613 | 614 | ; This setting is the same as the vlog -sv command line switch. 615 | ; Enables SystemVerilog features and keywords when true (1). 616 | ; When false (0), the rules of IEEE Std 1364-2001 are followed and 617 | ; SystemVerilog keywords are ignored. 618 | ; Svlog = 0 619 | 620 | ; Prints attribute placed upon SV packages during package import 621 | ; when true (1). The attribute will be ignored when this 622 | ; entry is false (0). The attribute name is "package_load_message". 623 | ; The value of this attribute is a string literal. 624 | ; Default is true (1). 625 | ; PrintSVPackageLoadingAttribute = 1 626 | 627 | ; Do not show immediate assertions with constant expressions in 628 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 629 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 630 | ; evaluation of immediate assertions. 631 | ; ShowConstantImmediateAsserts = 0 632 | 633 | ; Controls if untyped parameters that are initialized with values greater 634 | ; than 2147483647 are mapped to generics of type INTEGER or ignored. 635 | ; If mapped to VHDL Integers, values greater than 2147483647 636 | ; are mapped to negative values. 637 | ; Default is to map these parameter to generic of type INTEGER 638 | ; ForceUnsignedToVHDLInteger = 1 639 | 640 | ; Enable AMS wreal (wired real) extensions. Default is 0. 641 | ; WrealType = 1 642 | 643 | ; Controls SystemVerilog Language Extensions. These options enable 644 | ; some non-LRM compliant behavior. Valid extensions are: 645 | ; "acum", "atpi", "catx", "daoa", "feci", "fin0", "idcl", 646 | ; "iddp", "pae", "sccts", "spsl", "stop0", "udm0", and "uslt". 647 | ; SvExtensions = uslt,spsl,sccts 648 | 649 | ; Generate symbols debugging database in only some special cases to save on 650 | ; the number of files in the library. For other design-units, this database is 651 | ; generated on-demand in vsim. 652 | ; Default is to to generate debugging database for all design-units. 653 | ; SmartDbgSym = 1 654 | 655 | ; Controls how $unit library entries are named. Valid options are: 656 | ; "file" (generate name based on the first file on the command line) 657 | ; "du" (generate name based on first design unit following an item 658 | ; found in $unit scope) 659 | ; CUAutoName = file 660 | 661 | ; Enable or disable automatic creation of missing libraries. 662 | ; Default is 1 (enabled) 663 | ; CreateLib = 1 664 | 665 | [sccom] 666 | ; Enable use of SCV include files and library. Default is off. 667 | ; UseScv = 1 668 | 669 | ; Add C++ compiler options to the sccom command line by using this variable. 670 | ; CppOptions = -g 671 | 672 | ; Use custom C++ compiler located at this path rather than the default path. 673 | ; The path should point directly at a compiler executable. 674 | ; CppPath = /usr/bin/g++ 675 | 676 | ; Specify the compiler version from the list of support GNU compilers. 677 | ; examples 4.3.3, 4.5.0 678 | ; CppInstall = 4.5.0 679 | 680 | ; Enable verbose messages from sccom. Default is off. 681 | ; SccomVerbose = 1 682 | 683 | ; sccom logfile. Default is no logfile. 684 | ; SccomLogfile = sccom.log 685 | 686 | ; Enable use of SC_MS include files and library. Default is off. 687 | ; UseScMs = 1 688 | 689 | ; Use SystemC-2.2 instead of the default SystemC-2.3. Default is off. 690 | ; Sc22Mode = 1 691 | 692 | ; Enable compiler statistics. Specify one or more arguments: 693 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 694 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 695 | ; Stats = time,cmd,msg 696 | 697 | ; Enable or disable automatic creation of missing libraries. 698 | ; Default is 1 (enabled) 699 | ; CreateLib = 1 700 | 701 | [vopt] 702 | ; Turn on code coverage in vopt. Default is off. 703 | ; Coverage = sbceft 704 | 705 | ; Control compiler optimizations that are allowed when 706 | ; code coverage is on. Refer to the comment for this in the [vlog] area. 707 | ; CoverOpt = 3 708 | 709 | ; Increase or decrease the maximum number of rows allowed in a UDP table 710 | ; implementing a VHDL condition coverage or expression coverage expression. 711 | ; More rows leads to a longer compile time, but more expressions covered. 712 | ; CoverMaxUDPRows = 192 713 | 714 | ; Increase or decrease the maximum number of input patterns that are present 715 | ; in FEC table. This leads to a longer compile time with more expressions 716 | ; covered with FEC metric. 717 | ; CoverMaxFECRows = 192 718 | 719 | ; Increase or decrease the limit on the size of expressions and conditions 720 | ; considered for expression and condition coverages. Higher FecUdpEffort leads 721 | ; to higher compile, optimize and simulation time, but more expressions and 722 | ; conditions are considered for coverage in the design. FecUdpEffort can 723 | ; be set to a number ranging from 1 (low) to 3 (high), defined as: 724 | ; 1 - (low) Only small expressions and conditions considered for coverage. 725 | ; 2 - (medium) Bigger expressions and conditions considered for coverage. 726 | ; 3 - (high) Very large expressions and conditions considered for coverage. 727 | ; The default setting is 1 (low). 728 | ; FecUdpEffort = 1 729 | 730 | ; Enable code coverage reporting of code that has been optimized away. 731 | ; The default is not to report. 732 | ; CoverReportCancelled = 1 733 | 734 | ; Enable deglitching of code coverage in combinatorial, non-clocked, processes. 735 | ; Default is no deglitching. 736 | ; CoverDeglitchOn = 1 737 | 738 | ; Enable compiler statistics. Specify one or more arguments: 739 | ; [all,none,time,cmd,msg,perf,verbose,list,kb] 740 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 741 | ; Stats = time,cmd,msg 742 | 743 | ; Control the code coverage deglitching period. A period of 0, eliminates delta 744 | ; cycle glitches. The value of CoverDeglitchPeriod needs to be either be 0 or a 745 | ; time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 746 | ; CoverDeglitchPeriod = 0 747 | 748 | ; Do not show immediate assertions with constant expressions in 749 | ; GUI/reports/UCDB etc. By default immediate assertions with constant 750 | ; expressions are shown in GUI/reports/UCDB etc. This does not affect 751 | ; evaluation of immediate assertions. 752 | ; ShowConstantImmediateAsserts = 0 753 | 754 | ; Set the maximum number of iterations permitted for a generate loop. 755 | ; Restricting this permits the implementation to recognize infinite 756 | ; generate loops. 757 | ; GenerateLoopIterationMax = 100000 758 | 759 | ; Set the maximum depth permitted for a recursive generate instantiation. 760 | ; Restricting this permits the implementation to recognize infinite 761 | ; recursions. 762 | ; GenerateRecursionDepthMax = 200 763 | 764 | ; Set the number of processes created during the code generation phase. 765 | ; By default a heuristic is used to set this value. This may be set to 0 766 | ; to disable this feature completely. 767 | ; ParallelJobs = 0 768 | 769 | ; Controls SystemVerilog Language Extensions. These options enable 770 | ; some non-LRM compliant behavior. Valid extensions are "feci", 771 | ; "pae", "uslt", "spsl", "fin0" and "sccts". 772 | ; SvExtensions = uslt,spsl,sccts 773 | 774 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 775 | ; This gives global visibility to all symbols in the shared objects, 776 | ; meaning that subsequently loaded shared objects can bind to symbols 777 | ; in the global shared objects. The list of shared objects should 778 | ; be whitespace delimited. This option is not supported on the 779 | ; Windows or AIX platforms. 780 | ; GlobalSharedObjectList = example1.so example2.so example3.so 781 | 782 | ; Disable SystemVerilog elaboration system task messages 783 | ; IgnoreSVAInfo = 1 784 | ; IgnoreSVAWarning = 1 785 | ; IgnoreSVAError = 1 786 | ; IgnoreSVAFatal = 1 787 | 788 | ; Enable or disable automatic creation of missing libraries. 789 | ; Default is 1 (enabled) 790 | ; CreateLib = 1 791 | 792 | 793 | [vsim] 794 | ; vopt flow 795 | ; Set to turn on automatic optimization of a design. 796 | ; Default is on 797 | VoptFlow = 1 798 | 799 | ; Simulator resolution 800 | ; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100. 801 | Resolution = ns 802 | 803 | ; Disable certain code coverage exclusions automatically. 804 | ; Assertions and FSM are exluded from the code coverage by default 805 | ; Set AutoExclusionsDisable = fsm to enable code coverage for fsm 806 | ; Set AutoExclusionsDisable = assertions to enable code coverage for assertions 807 | ; Set AutoExclusionsDisable = all to enable code coverage for all the automatic exclusions 808 | ; Or specify comma or space separated list 809 | ;AutoExclusionsDisable = fsm,assertions 810 | 811 | ; User time unit for run commands 812 | ; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the 813 | ; unit specified for Resolution. For example, if Resolution is 100ps, 814 | ; then UserTimeUnit defaults to ps. 815 | ; Should generally be set to default. 816 | UserTimeUnit = default 817 | 818 | ; Default run length 819 | RunLength = 0 ps 820 | 821 | ; Maximum iterations that can be run without advancing simulation time 822 | IterationLimit = 10000000 823 | 824 | ; Specify libraries to be searched for precompiled modules 825 | ; LibrarySearchPath = [ ...] 826 | 827 | ; Set XPROP assertion fail limit. Default is 5. 828 | ; Any positive integer, -1 for infinity. 829 | ; XpropAssertionLimit = 5 830 | 831 | ; Control PSL and Verilog Assume directives during simulation 832 | ; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts 833 | ; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts 834 | ; SimulateAssumeDirectives = 1 835 | 836 | ; Control the simulation of PSL and SVA 837 | ; These switches can be overridden by the vsim command line switches: 838 | ; -psl, -nopsl, -sva, -nosva. 839 | ; Set SimulatePSL = 0 to disable PSL simulation 840 | ; Set SimulatePSL = 1 to enable PSL simulation (default) 841 | ; SimulatePSL = 1 842 | ; Set SimulateSVA = 0 to disable SVA simulation 843 | ; Set SimulateSVA = 1 to enable concurrent SVA simulation (default) 844 | ; SimulateSVA = 1 845 | 846 | ; Control SVA and VHDL immediate assertion directives during simulation 847 | ; Set SimulateImmedAsserts = 0 to disable simulation of immediate asserts 848 | ; Set SimulateImmedAsserts = 1 to enable simulation of immediate asserts 849 | ; SimulateImmedAsserts = 1 850 | 851 | ; License feature mappings for Verilog and VHDL 852 | ; qhsimvh Single language VHDL license 853 | ; qhsimvl Single language Verilog license 854 | ; msimhdlsim Language neutral license for either Verilog or VHDL 855 | ; msimhdlmix Second language only, language neutral license for either 856 | ; Verilog or VHDL 857 | ; 858 | ; Directives to license manager can be set either as single value or as 859 | ; space separated multi-values: 860 | ; vhdl Immediately checkout and hold a VHDL license (i.e., one of 861 | ; qhsimvh, msimhdlsim, or msimhdlmix) 862 | ; vlog Immediately checkout and hold a Verilog license (i.e., one of 863 | ; qhsimvl, msimhdlsim, or msimhdlmix) 864 | ; plus Immediately checkout and hold a VHDL license and a Verilog license 865 | ; noqueue Do not wait in the license queue when a license is not available 866 | ; viewsim Try for viewer license but accept simulator license(s) instead 867 | ; of queuing for viewer license (PE ONLY) 868 | ; noviewer Disable checkout of msimviewer license feature (PE ONLY) 869 | ; noslvhdl Disable checkout of qhsimvh license feature 870 | ; noslvlog Disable checkout of qhsimvl license feature 871 | ; nomix Disable checkout of msimhdlmix license feature 872 | ; nolnl Disable checkout of msimhdlsim license feature 873 | ; mixedonly Disable checkout of qhsimvh and qhsimvl license features 874 | ; lnlonly Disable checkout of qhsimvh,qhsimvl, and msimhdlmix license features 875 | ; 876 | ; Examples (remove ";" comment character to activate licensing directives): 877 | ; Single directive: 878 | ; License = plus 879 | ; Multi-directive (Note: space delimited directives): 880 | ; License = noqueue plus 881 | 882 | ; Severity level of a VHDL assertion message or of a SystemVerilog severity system task 883 | ; which will cause a running simulation to stop. 884 | ; VHDL assertions and SystemVerilog severity system task that occur with the 885 | ; given severity or higher will cause a running simulation to stop. 886 | ; This value is ignored during elaboration. 887 | ; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal 888 | BreakOnAssertion = 3 889 | 890 | ; Severity level of a tool message which will cause a running simulation to 891 | ; stop. This value is ignored during elaboration. Default is to not break. 892 | ; 0 = Note 1 = Warning 2 = Error 3 = Fatal 893 | ;BreakOnMessage = 2 894 | 895 | ; The class debug feature enables more visibility and tracking of class instances 896 | ; during simulation. By default this feature is disabled (0). To enable this 897 | ; feature set ClassDebug to 1. 898 | ; ClassDebug = 1 899 | 900 | ; Message Format conversion specifications: 901 | ; %S - Severity Level of message/assertion 902 | ; %R - Text of message 903 | ; %T - Time of message 904 | ; %D - Delta value (iteration number) of Time 905 | ; %K - Kind of path: Instance/Region/Signal/Process/Foreign Process/Unknown/Protected 906 | ; %i - Instance/Region/Signal pathname with Process name (if available) 907 | ; %I - shorthand for one of these: 908 | ; " %K: %i" 909 | ; " %K: %i File: %F" (when path is not Process or Signal) 910 | ; except that the %i in this case does not report the Process name 911 | ; %O - Process name 912 | ; %P - Instance/Region path without leaf process 913 | ; %F - File name 914 | ; %L - Line number; if assertion message, then line number of assertion or, if 915 | ; assertion is in a subprogram, line from which the call is made 916 | ; %u - Design unit name in form library.primary 917 | ; %U - Design unit name in form library.primary(secondary) 918 | ; %% - The '%' character itself 919 | ; 920 | ; If specific format for Severity Level is defined, use that format. 921 | ; Else, for a message that occurs during elaboration: 922 | ; -- Failure/Fatal message in VHDL region that is not a Process, and in 923 | ; certain non-VHDL regions, uses MessageFormatBreakLine; 924 | ; -- Failure/Fatal message otherwise uses MessageFormatBreak; 925 | ; -- Note/Warning/Error message uses MessageFormat. 926 | ; Else, for a message that occurs during runtime and triggers a breakpoint because 927 | ; of the BreakOnAssertion setting: 928 | ; -- if in a VHDL region that is not a Process, uses MessageFormatBreakLine; 929 | ; -- otherwise uses MessageFormatBreak. 930 | ; Else (a runtime message that does not trigger a breakpoint) uses MessageFormat. 931 | ; 932 | ; MessageFormatNote = "** %S: %R\n Time: %T Iteration: %D%I\n" 933 | ; MessageFormatWarning = "** %S: %R\n Time: %T Iteration: %D%I\n" 934 | ; MessageFormatError = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 935 | ; MessageFormatFail = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 936 | ; MessageFormatFatal = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 937 | ; MessageFormatBreakLine = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F Line: %L\n" 938 | ; MessageFormatBreak = "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n" 939 | ; MessageFormat = "** %S: %R\n Time: %T Iteration: %D%I\n" 940 | 941 | ; Error File - alternate file for storing error messages 942 | ; ErrorFile = error.log 943 | 944 | ; Simulation Breakpoint messages 945 | ; This flag controls the display of function names when reporting the location 946 | ; where the simulator stops because of a breakpoint or fatal error. 947 | ; Example with function name: # Break in Process ctr at counter.vhd line 44 948 | ; Example without function name: # Break at counter.vhd line 44 949 | ; Default value is 1. 950 | ShowFunctions = 1 951 | 952 | ; Default radix for all windows and commands. 953 | ; Radix may be one of: symbolic, ascii, binary, octal, decimal, hex, unsigned 954 | ; Flags may be one of: enumnumeric, showbase 955 | DefaultRadix = hexadecimal 956 | DefaultRadixFlags = showbase 957 | ; Set to 1 for make the signal_force VHDL and Verilog functions use the 958 | ; default radix when processing the force value. Prior to 10.2 signal_force 959 | ; used the default radix, now it always uses symbolic unless value explicitly indicates base 960 | ;SignalForceFunctionUseDefaultRadix = 0 961 | 962 | ; VSIM Startup command 963 | ; Startup = do startup.do 964 | 965 | ; VSIM Shutdown file 966 | ; Filename to save u/i formats and configurations. 967 | ; ShutdownFile = restart.do 968 | ; To explicitly disable auto save: 969 | ; ShutdownFile = --disable-auto-save 970 | 971 | ; Run simulator in batch mode as if -batch were specified on the command line if none of -c, -gui, or -i specified. 972 | ; Simulator runs in interactive mode as if -i were specified if this option is 0. Default is 0. 973 | ; BatchMode = 1 974 | 975 | ; File for saving command transcript when -batch option used 976 | ; This option is ignored when -c, -gui, or -i options are used or if BatchMode above is zero 977 | ; default is unset so command transcript only goes to stdout for better performance 978 | ; BatchTranscriptFile = transcript 979 | 980 | ; File for saving command transcript, this option is ignored when -batch option is used 981 | TranscriptFile = transcript 982 | 983 | ; File for saving command history 984 | ; CommandHistory = cmdhist.log 985 | 986 | ; Specify whether paths in simulator commands should be described 987 | ; in VHDL or Verilog format. 988 | ; For VHDL, PathSeparator = / 989 | ; For Verilog, PathSeparator = . 990 | ; Must not be the same character as DatasetSeparator. 991 | PathSeparator = / 992 | 993 | ; Specify the dataset separator for fully rooted contexts. 994 | ; The default is ':'. For example: sim:/top 995 | ; Must not be the same character as PathSeparator. 996 | DatasetSeparator = : 997 | 998 | ; Specify a unique path separator for the Signal Spy set of functions. 999 | ; The default will be to use the PathSeparator variable. 1000 | ; Must not be the same character as DatasetSeparator. 1001 | ; SignalSpyPathSeparator = / 1002 | 1003 | ; Used to control parsing of HDL identifiers input to the tool. 1004 | ; This includes CLI commands, vsim/vopt/vlog/vcom options, 1005 | ; string arguments to FLI/VPI/DPI calls, etc. 1006 | ; If set to 1, accept either Verilog escaped Id syntax or 1007 | ; VHDL extended id syntax, regardless of source language. 1008 | ; If set to 0, the syntax of the source language must be used. 1009 | ; Each identifier in a hierarchical name may need different syntax, 1010 | ; e.g. "/top/\vhdl*ext*id\/middle/\vlog*ext*id /bottom" or 1011 | ; "top.\vhdl*ext*id\.middle.\vlog*ext*id .bottom" 1012 | ; GenerousIdentifierParsing = 1 1013 | 1014 | ; Disable VHDL assertion messages 1015 | ; IgnoreNote = 1 1016 | ; IgnoreWarning = 1 1017 | ; IgnoreError = 1 1018 | ; IgnoreFailure = 1 1019 | 1020 | ; Disable SystemVerilog assertion messages 1021 | ; IgnoreSVAInfo = 1 1022 | ; IgnoreSVAWarning = 1 1023 | ; IgnoreSVAError = 1 1024 | ; IgnoreSVAFatal = 1 1025 | 1026 | ; Do not print any additional information from Severity System tasks. 1027 | ; Only the message provided by the user is printed along with severity 1028 | ; information. 1029 | ; SVAPrintOnlyUserMessage = 1; 1030 | 1031 | ; Default force kind. May be freeze, drive, deposit, or default 1032 | ; or in other terms, fixed, wired, or charged. 1033 | ; A value of "default" will use the signal kind to determine the 1034 | ; force kind, drive for resolved signals, freeze for unresolved signals 1035 | ; DefaultForceKind = freeze 1036 | 1037 | ; Control the iteration of events when a VHDL signal is forced to a value 1038 | ; This flag can be set to honour the signal update event in next iteration, 1039 | ; the default is to update and propagate in the same iteration. 1040 | ; ForceSigNextIter = 1 1041 | 1042 | ; Enable simulation statistics. Specify one or more arguments: 1043 | ; [all,none,time,cmd,msg,perf,verbose,list,kb,eor] 1044 | ; Add '-' to disable specific statistics. Default is [time,cmd,msg]. 1045 | ; Stats = time,cmd,msg 1046 | 1047 | ; If zero, open files when elaborated; otherwise, open files on 1048 | ; first read or write. Default is 0. 1049 | ; DelayFileOpen = 1 1050 | 1051 | ; Control VHDL files opened for write. 1052 | ; 0 = Buffered, 1 = Unbuffered 1053 | UnbufferedOutput = 0 1054 | 1055 | ; Control the number of VHDL files open concurrently. 1056 | ; This number should always be less than the current ulimit 1057 | ; setting for max file descriptors. 1058 | ; 0 = unlimited 1059 | ConcurrentFileLimit = 40 1060 | 1061 | ; If nonzero, close files as soon as there is either an explicit call to 1062 | ; file_close, or when the file variable's scope is closed. When zero, a 1063 | ; file opened in append mode is not closed in case it is immediately 1064 | ; reopened in append mode; otherwise, the file will be closed at the 1065 | ; point it is reopened. 1066 | ; AppendClose = 1 1067 | 1068 | ; Control the number of hierarchical regions displayed as 1069 | ; part of a signal name shown in the Wave window. 1070 | ; A value of zero tells VSIM to display the full name. 1071 | ; The default is 0. 1072 | ; WaveSignalNameWidth = 0 1073 | 1074 | ; Turn off warnings when changing VHDL constants and generics 1075 | ; Default is 1 to generate warning messages 1076 | ; WarnConstantChange = 0 1077 | 1078 | ; Turn off warnings from accelerated versions of the std_logic_arith, 1079 | ; std_logic_unsigned, and std_logic_signed packages. 1080 | ; StdArithNoWarnings = 1 1081 | 1082 | ; Turn off warnings from accelerated versions of the IEEE numeric_std 1083 | ; and numeric_bit packages. 1084 | ; NumericStdNoWarnings = 1 1085 | 1086 | ; Use old-style (pre-6.6) VHDL FOR GENERATE statement iteration names 1087 | ; in the design hierarchy. 1088 | ; This style is controlled by the value of the GenerateFormat 1089 | ; value described next. Default is to use new-style names, which 1090 | ; comprise the generate statement label, '(', the value of the generate 1091 | ; parameter, and a closing ')'. 1092 | ; Set this to 1 to use old-style names. 1093 | ; OldVhdlForGenNames = 1 1094 | 1095 | ; Control the format of the old-style VHDL FOR generate statement region 1096 | ; name for each iteration. Do not quote the value. 1097 | ; The format string here must contain the conversion codes %s and %d, 1098 | ; in that order, and no other conversion codes. The %s represents 1099 | ; the generate statement label; the %d represents the generate parameter value 1100 | ; at a particular iteration (this is the position number if the generate parameter 1101 | ; is of an enumeration type). Embedded whitespace is allowed (but discouraged); 1102 | ; leading and trailing whitespace is ignored. 1103 | ; Application of the format must result in a unique region name over all 1104 | ; loop iterations for a particular immediately enclosing scope so that name 1105 | ; lookup can function properly. The default is %s__%d. 1106 | ; GenerateFormat = %s__%d 1107 | 1108 | ; Enable more efficient logging of VHDL Variables. 1109 | ; Logging VHDL variables without this enabled, while possible, is very 1110 | ; inefficient. Enabling this will provide a more efficient logging methodology 1111 | ; at the expense of more memory usage. By default this feature is disabled (0). 1112 | ; To enabled this feature, set this variable to 1. 1113 | ; VhdlVariableLogging = 1 1114 | 1115 | ; Enable logging of VHDL access type variables and their designated objects. 1116 | ; This setting will allow both variables of an access type ("access variables") 1117 | ; and their designated objects ("access objects") to be logged. Logging a 1118 | ; variable of an access type will automatically also cause the designated 1119 | ; object(s) of that variable to be logged as the simulation progresses. 1120 | ; Further, enabling this allows access objects to be logged by name. By default 1121 | ; this feature is disabled (0). To enable this feature, set this variable to 1. 1122 | ; Enabling this will automatically enable the VhdlVariableLogging feature also. 1123 | ; AccessObjDebug = 1 1124 | 1125 | ; Make each VHDL package in a PDU has its own separate copy of the package instead 1126 | ; of sharing the package between PDUs. The default is to share packages. 1127 | ; To ensure that each PDU has its own set of packages, set this variable to 1. 1128 | ; VhdlSeparatePduPackage = 1 1129 | 1130 | ; Specify whether checkpoint files should be compressed. 1131 | ; The default is 1 (compressed). 1132 | ; CheckpointCompressMode = 0 1133 | 1134 | ; Specify gcc compiler used in the compilation of automatically generated DPI exportwrapper. 1135 | ; Use custom gcc compiler located at this path rather than the default path. 1136 | ; The path should point directly at a compiler executable. 1137 | ; DpiCppPath = /bin/gcc 1138 | 1139 | ; Specify whether to enable SystemVerilog DPI "out-of-the-blue" calls. 1140 | ; The term "out-of-the-blue" refers to SystemVerilog export function calls 1141 | ; made from C functions that don't have the proper context setup 1142 | ; (as is the case when running under "DPI-C" import functions). 1143 | ; When this is enabled, one can call a DPI export function 1144 | ; (but not task) from any C code. 1145 | ; the setting of this variable can be one of the following values: 1146 | ; 0 : dpioutoftheblue call is disabled (default) 1147 | ; 1 : dpioutoftheblue call is enabled, but export call debug support is not available. 1148 | ; 2 : dpioutoftheblue call is enabled, and limited export call debug support is available. 1149 | ; DpiOutOfTheBlue = 1 1150 | 1151 | ; Specify whether continuous assignments are run before other normal priority 1152 | ; processes scheduled in the same iteration. This event ordering minimizes race 1153 | ; differences between optimized and non-optimized designs, and is the default 1154 | ; behavior beginning with the 6.5 release. For pre-6.5 event ordering, set 1155 | ; ImmediateContinuousAssign to 0. 1156 | ; The default is 1 (enabled). 1157 | ; ImmediateContinuousAssign = 0 1158 | 1159 | ; List of dynamically loaded objects for Verilog PLI applications 1160 | ; Veriuser = veriuser.sl 1161 | 1162 | ; Which default VPI object model should the tool conform to? 1163 | ; The 1364 modes are Verilog-only, for backwards compatibility with older 1164 | ; libraries, and SystemVerilog objects are not available in these modes. 1165 | ; 1166 | ; In the absence of a user-specified default, the tool default is the 1167 | ; latest available LRM behavior. 1168 | ; Options for PliCompatDefault are: 1169 | ; VPI_COMPATIBILITY_VERSION_1364v1995 1170 | ; VPI_COMPATIBILITY_VERSION_1364v2001 1171 | ; VPI_COMPATIBILITY_VERSION_1364v2005 1172 | ; VPI_COMPATIBILITY_VERSION_1800v2005 1173 | ; VPI_COMPATIBILITY_VERSION_1800v2008 1174 | ; 1175 | ; Synonyms for each string are also recognized: 1176 | ; VPI_COMPATIBILITY_VERSION_1364v1995 (1995, 95, 1364v1995, 1364V1995, VL1995) 1177 | ; VPI_COMPATIBILITY_VERSION_1364v2001 (2001, 01, 1364v2001, 1364V2001, VL2001) 1178 | ; VPI_COMPATIBILITY_VERSION_1364v2005 (1364v2005, 1364V2005, VL2005) 1179 | ; VPI_COMPATIBILITY_VERSION_1800v2005 (2005, 05, 1800v2005, 1800V2005, SV2005) 1180 | ; VPI_COMPATIBILITY_VERSION_1800v2008 (2008, 08, 1800v2008, 1800V2008, SV2008) 1181 | 1182 | 1183 | ; PliCompatDefault = VPI_COMPATIBILITY_VERSION_1800v2005 1184 | 1185 | ; Specify whether the Verilog system task $fopen or vpi_mcd_open() 1186 | ; will create directories that do not exist when opening the file 1187 | ; in "a" or "w" mode. 1188 | ; The default is 0 (do not create non-existent directories) 1189 | ; CreateDirForFileAccess = 1 1190 | 1191 | ; Specify default options for the restart command. Options can be one 1192 | ; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions 1193 | ; DefaultRestartOptions = -force 1194 | 1195 | 1196 | ; Specify default UVM-aware debug options if the vsim -uvmcontrol switch is not used. 1197 | ; Valid options include: all, none, verbose, disable, struct, msglog, trlog, certe. 1198 | ; Options can be enabled by just adding the name, or disabled by prefixing the option with a "-". 1199 | ; The list of options must be delimited by commas, without spaces or tabs. 1200 | ; The default is UVMControl = struct 1201 | 1202 | ; Some examples 1203 | ; To turn on all available UVM-aware debug features: 1204 | ; UVMControl = all 1205 | ; To turn on the struct window, mesage logging, and transaction logging: 1206 | ; UVMControl = struct,msglog,trlog 1207 | ; To turn on all options except certe: 1208 | ; UVMControl = all,-certe 1209 | ; To completely disable all UVM-aware debug functionality: 1210 | ; UVMControl = disable 1211 | 1212 | ; Specify the WildcardFilter setting. 1213 | ; A space separated list of object types to be excluded when performing 1214 | ; wildcard matches with log, wave, etc commands. The default value for this variable is: 1215 | ; "Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile" 1216 | ; See "Using the WildcardFilter Preference Variable" in the documentation for 1217 | ; details on how to use this variable and for descriptions of the filter types. 1218 | WildcardFilter = Variable Constant Generic Parameter SpecParam Memory Assertion Cover Endpoint ScVariable CellInternal ImmediateAssert VHDLFile 1219 | 1220 | ; Specify the WildcardSizeThreshold setting. 1221 | ; This integer setting specifies the size at which objects will be excluded when 1222 | ; performing wildcard matches with log, wave, etc commands. Objects of size equal 1223 | ; to or greater than the WildcardSizeThreshold will be filtered out from the wildcard 1224 | ; matches. The size is a simple calculation of number of bits or items in the object. 1225 | ; The default value is 8k (8192). Setting this value to 0 will disable the checking 1226 | ; of object size against this threshold and allow all objects of any size to be logged. 1227 | WildcardSizeThreshold = 8192 1228 | 1229 | ; Specify whether warning messages are output when objects are filtered out due to the 1230 | ; WildcardSizeThreshold. The default is 0 (no messages generated). 1231 | WildcardSizeThresholdVerbose = 0 1232 | 1233 | ; Turn on (1) or off (0) WLF file compression. 1234 | ; The default is 1 (compress WLF file). 1235 | ; WLFCompress = 0 1236 | 1237 | ; Specify whether to save all design hierarchy (1) in the WLF file 1238 | ; or only regions containing logged signals (0). 1239 | ; The default is 0 (save only regions with logged signals). 1240 | ; WLFSaveAllRegions = 1 1241 | 1242 | ; WLF file time limit. Limit WLF file by time, as closely as possible, 1243 | ; to the specified amount of simulation time. When the limit is exceeded 1244 | ; the earliest times get truncated from the file. 1245 | ; If both time and size limits are specified the most restrictive is used. 1246 | ; UserTimeUnits are used if time units are not specified. 1247 | ; The default is 0 (no limit). Example: WLFTimeLimit = {100 ms} 1248 | ; WLFTimeLimit = 0 1249 | 1250 | ; WLF file size limit. Limit WLF file size, as closely as possible, 1251 | ; to the specified number of megabytes. If both time and size limits 1252 | ; are specified then the most restrictive is used. 1253 | ; The default is 0 (no limit). 1254 | ; WLFSizeLimit = 1000 1255 | 1256 | ; Specify whether or not a WLF file should be deleted when the 1257 | ; simulation ends. A value of 1 will cause the WLF file to be deleted. 1258 | ; The default is 0 (do not delete WLF file when simulation ends). 1259 | ; WLFDeleteOnQuit = 1 1260 | 1261 | ; Specify whether or not a WLF file should be optimized during 1262 | ; simulation. If set to 0, the WLF file will not be optimized. 1263 | ; The default is 1, optimize the WLF file. 1264 | ; WLFOptimize = 0 1265 | 1266 | ; Specify the name of the WLF file. 1267 | ; The default is vsim.wlf 1268 | ; WLFFilename = vsim.wlf 1269 | 1270 | ; Specify whether to lock the WLF file. 1271 | ; Locking the file prevents other invocations of ModelSim/Questa tools from 1272 | ; inadvertently overwriting the WLF file. 1273 | ; The default is 1, lock the WLF file. 1274 | ; WLFFileLock = 0 1275 | 1276 | ; Specify the update interval for the WLF file in live simulation. 1277 | ; The interval is given in seconds. 1278 | ; The value is the smallest interval between WLF file updates. The WLF file 1279 | ; will be flushed (updated) after (at least) the interval has elapsed, ensuring 1280 | ; that the data is correct when viewed from a separate viewer. 1281 | ; A value of 0 means that no updating will occur. 1282 | ; The default value is 10 seconds. 1283 | ; WLFUpdateInterval = 10 1284 | 1285 | ; Specify the WLF cache size limit for WLF files. 1286 | ; The value is given in megabytes. A value of 0 turns off the cache. 1287 | ; On non-Windows platforms the default WLFCacheSize setting is 2000 (megabytes). 1288 | ; On Windows, the default value is 1000 (megabytes) to help to avoid filling 1289 | ; process memory. 1290 | ; WLFSimCacheSize allows a different cache size to be set for a live simulation 1291 | ; WLF file, independent of post-simulation WLF file viewing. If WLFSimCacheSize 1292 | ; is not set, it defaults to the WLFCacheSize value. 1293 | ; WLFCacheSize = 2000 1294 | ; WLFSimCacheSize = 500 1295 | 1296 | ; Specify the WLF file event collapse mode. 1297 | ; 0 = Preserve all events and event order. (same as -wlfnocollapse) 1298 | ; 1 = Only record values of logged objects at the end of a simulator iteration. 1299 | ; (same as -wlfcollapsedelta) 1300 | ; 2 = Only record values of logged objects at the end of a simulator time step. 1301 | ; (same as -wlfcollapsetime) 1302 | ; The default is 1. 1303 | ; WLFCollapseMode = 0 1304 | 1305 | ; Specify whether WLF file logging can use threads on multi-processor machines. 1306 | ; If 0, no threads will be used; if 1, threads will be used if the system has 1307 | ; more than one processor. 1308 | ; WLFUseThreads = 1 1309 | 1310 | ; Specify the size of objects that will trigger "large object" messages 1311 | ; at log/wave/list time. The size calculation of the object is the same as that 1312 | ; used by the WildcardSizeThreshold. The default LargeObjectSize size is 500,000. 1313 | ; Setting LargeObjectSize to 0 will disable these messages. 1314 | ; LargeObjectSize = 500000 1315 | 1316 | ; Specify the depth of stack frames returned by $stacktrace([level]). 1317 | ; This depth will be picked up when the optional 'level' argument 1318 | ; is not specified or its value is not a positive integer. 1319 | ; StackTraceDepth = 100 1320 | 1321 | ; Turn on/off undebuggable SystemC type warnings. Default is on. 1322 | ; ShowUndebuggableScTypeWarning = 0 1323 | 1324 | ; Turn on/off unassociated SystemC name warnings. Default is off. 1325 | ; ShowUnassociatedScNameWarning = 1 1326 | 1327 | ; Turn on/off SystemC IEEE 1666 deprecation warnings. Default is off. 1328 | ; ScShowIeeeDeprecationWarnings = 1 1329 | 1330 | ; Turn on/off the check for multiple drivers on a SystemC sc_signal. Default is off. 1331 | ; ScEnableScSignalWriteCheck = 1 1332 | 1333 | ; Set SystemC default time unit. 1334 | ; Set to fs, ps, ns, us, ms, or sec with optional 1335 | ; prefix of 1, 10, or 100. The default is 1 ns. 1336 | ; The ScTimeUnit value is honored if it is coarser than Resolution. 1337 | ; If ScTimeUnit is finer than Resolution, it is set to the value 1338 | ; of Resolution. For example, if Resolution is 100ps and ScTimeUnit is ns, 1339 | ; then the default time unit will be 1 ns. However if Resolution 1340 | ; is 10 ns and ScTimeUnit is ns, then the default time unit will be 10 ns. 1341 | ScTimeUnit = ns 1342 | 1343 | ; Set SystemC sc_main stack size. The stack size is set as an integer 1344 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1345 | ; Gb(Giga-byte). Default is 10 Mb. The stack size for sc_main depends 1346 | ; on the amount of data on the sc_main() stack and the memory required 1347 | ; to succesfully execute the longest function call chain of sc_main(). 1348 | ScMainStackSize = 10 Mb 1349 | 1350 | ; Set SystemC thread stack size. The stack size is set as an integer 1351 | ; number followed by the unit which can be Kb(Kilo-byte), Mb(Mega-byte) or 1352 | ; Gb(Giga-byte). The stack size for sc_thread depends 1353 | ; on the amount of data on the sc_thread stack and the memory required 1354 | ; to succesfully execute the thread. 1355 | ; ScStackSize = 1 Mb 1356 | 1357 | ; Turn on/off execution of remainder of sc_main upon quitting the current 1358 | ; simulation session. If the cumulative length of sc_main() in terms of 1359 | ; simulation time units is less than the length of the current simulation 1360 | ; run upon quit or restart, sc_main() will be in the middle of execution. 1361 | ; This switch gives the option to execute the remainder of sc_main upon 1362 | ; quitting simulation. The drawback of not running sc_main till the end 1363 | ; is memory leaks for objects created by sc_main. If on, the remainder of 1364 | ; sc_main will be executed ignoring all delays. This may cause the simulator 1365 | ; to crash if the code in sc_main is dependent on some simulation state. 1366 | ; Default is on. 1367 | ScMainFinishOnQuit = 1 1368 | 1369 | ; Set the SCV relationship name that will be used to identify phase 1370 | ; relations. If the name given to a transactor relation matches this 1371 | ; name, the transactions involved will be treated as phase transactions 1372 | ScvPhaseRelationName = mti_phase 1373 | 1374 | ; Customize the vsim kernel shutdown behavior at the end of the simulation. 1375 | ; Some common causes of the end of simulation are $finish (implicit or explicit), 1376 | ; sc_stop(), tf_dofinish(), and assertion failures. 1377 | ; This should be set to "ask", "exit", or "stop". The default is "ask". 1378 | ; "ask" -- In batch mode, the vsim kernel will abruptly exit. 1379 | ; In GUI mode, a dialog box will pop up and ask for user confirmation 1380 | ; whether or not to quit the simulation. 1381 | ; "stop" -- Cause the simulation to stay loaded in memory. This can make some 1382 | ; post-simulation tasks easier. 1383 | ; "exit" -- The simulation will abruptly exit without asking for any confirmation. 1384 | ; "final" -- Run SystemVerilog final blocks then behave as "stop". 1385 | ; Note: This variable can be overridden with the vsim "-onfinish" command line switch. 1386 | OnFinish = ask 1387 | 1388 | ; Print pending deferred assertion messages. 1389 | ; Deferred assertion messages may be scheduled after the $finish in the same 1390 | ; time step. Deferred assertions scheduled to print after the $finish are 1391 | ; printed before exiting with severity level NOTE since it's not known whether 1392 | ; the assertion is still valid due to being printed in the active region 1393 | ; instead of the reactive region where they are normally printed. 1394 | ; OnFinishPendingAssert = 1; 1395 | 1396 | ; Print "simstats" result. Default is 0. 1397 | ; 0 == do not print simstats 1398 | ; 1 == print at end of simulation 1399 | ; 2 == print at end of each run command and end of simulation 1400 | ; PrintSimStats = 1 1401 | 1402 | ; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages 1403 | ; AssertFile = assert.log 1404 | 1405 | ; Enable assertion counts. Default is off. 1406 | ; AssertionCover = 1 1407 | 1408 | ; Run simulator in assertion debug mode. Default is off. 1409 | ; AssertionDebug = 1 1410 | 1411 | ; Turn on/off PSL/SVA/VHDL assertion enable. Default is on. 1412 | ; AssertionEnable = 0 1413 | 1414 | ; Set PSL/SVA/VHDL concurrent assertion fail limit. Default is -1. 1415 | ; Any positive integer, -1 for infinity. 1416 | ; AssertionLimit = 1 1417 | 1418 | ; Turn on/off concurrent assertion pass log. Default is off. 1419 | ; Assertion pass logging is only enabled when assertion is browseable 1420 | ; and assertion debug is enabled. 1421 | ; AssertionPassLog = 1 1422 | 1423 | ; Turn on/off PSL concurrent assertion fail log. Default is on. 1424 | ; The flag does not affect SVA 1425 | ; AssertionFailLog = 0 1426 | 1427 | ; Turn on/off SVA concurrent assertion local var printing in -assertdebug mode. Default is on. 1428 | ; AssertionFailLocalVarLog = 0 1429 | 1430 | ; Set action type for PSL/SVA concurrent assertion fail action. Default is continue. 1431 | ; 0 = Continue 1 = Break 2 = Exit 1432 | ; AssertionFailAction = 1 1433 | 1434 | ; Enable the active thread monitor in the waveform display when assertion debug is enabled. 1435 | ; AssertionActiveThreadMonitor = 1 1436 | 1437 | ; Control how many waveform rows will be used for displaying the active threads. Default is 5. 1438 | ; AssertionActiveThreadMonitorLimit = 5 1439 | 1440 | ; Assertion thread limit after which assertion would be killed/switched off. 1441 | ; The default is -1 (unlimited). If the number of threads for an assertion go 1442 | ; beyond this limit, the assertion would be either switched off or killed. This 1443 | ; limit applies to only assert directives. 1444 | ;AssertionThreadLimit = -1 1445 | 1446 | ; Action to be taken once the assertion thread limit is reached. Default 1447 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1448 | ; threads are terminated and no new attempts are started. In case of off, the 1449 | ; existing attempts keep on evaluating but no new attempts are started. This 1450 | ; variable applies to only assert directives. 1451 | ;AssertionThreadLimitAction = kill 1452 | 1453 | ; Cover thread limit after which cover would be killed/switched off. 1454 | ; The default is -1 (unlimited). If the number of threads for a cover go 1455 | ; beyond this limit, the cover would be either switched off or killed. This 1456 | ; limit applies to only cover directives. 1457 | ;CoverThreadLimit = -1 1458 | 1459 | ; Action to be taken once the cover thread limit is reached. Default 1460 | ; is kill. It can have a value of off or kill. In case of kill, all the existing 1461 | ; threads are terminated and no new attempts are started. In case of off, the 1462 | ; existing attempts keep on evaluating but no new attempts are started. This 1463 | ; variable applies to only cover directives. 1464 | ;CoverThreadLimitAction = kill 1465 | 1466 | 1467 | ; By default immediate assertions do not participate in Assertion Coverage calculations 1468 | ; unless they are executed. This switch causes all immediate assertions in the design 1469 | ; to participate in Assertion Coverage calculations, whether attempted or not. 1470 | ; UnattemptedImmediateAssertions = 0 1471 | 1472 | ; By default immediate covers participate in Coverage calculations 1473 | ; whether they are attempted or not. This switch causes all unattempted 1474 | ; immediate covers in the design to stop participating in Coverage 1475 | ; calculations. 1476 | ; UnattemptedImmediateCovers = 0 1477 | 1478 | ; By default pass action block is not executed for assertions on vacuous 1479 | ; success. The following variable is provided to enable execution of 1480 | ; pass action block on vacuous success. The following variable is only effective 1481 | ; if the user does not disable pass action block execution by using either 1482 | ; system tasks or CLI. Also there is a performance penalty for enabling 1483 | ; the following variable. 1484 | ;AssertionEnableVacuousPassActionBlock = 1 1485 | 1486 | ; As per strict 1850-2005 PSL LRM, an always property can either pass 1487 | ; or fail. However, by default, Questa reports multiple passes and 1488 | ; multiple fails on top always/never property (always/never operator 1489 | ; is the top operator under Verification Directive). The reason 1490 | ; being that Questa reports passes and fails on per attempt of the 1491 | ; top always/never property. Use the following flag to instruct 1492 | ; Questa to strictly follow LRM. With this flag, all assert/never 1493 | ; directives will start an attempt once at start of simulation. 1494 | ; The attempt can either fail, match or match vacuously. 1495 | ; For e.g. if always is the top operator under assert, the always will 1496 | ; keep on checking the property at every clock. If the property under 1497 | ; always fails, the directive will be considered failed and no more 1498 | ; checking will be done for that directive. A top always property, 1499 | ; if it does not fail, will show a pass at end of simulation. 1500 | ; The default value is '0' (i.e. zero is off). For example: 1501 | ; PslOneAttempt = 1 1502 | 1503 | ; Specify the number of clock ticks to represent infinite clock ticks. 1504 | ; This affects eventually!, until! and until_!. If at End of Simulation 1505 | ; (EOS) an active strong-property has not clocked this number of 1506 | ; clock ticks then neither pass or fail (vacuous match) is returned 1507 | ; else respective fail/pass is returned. The default value is '0' (zero) 1508 | ; which effectively does not check for clock tick condition. For example: 1509 | ; PslInfinityThreshold = 5000 1510 | 1511 | ; Control how many thread start times will be preserved for ATV viewing for a given assertion 1512 | ; instance. Default is -1 (ALL). 1513 | ; ATVStartTimeKeepCount = -1 1514 | 1515 | ; Turn on/off code coverage 1516 | ; CodeCoverage = 0 1517 | 1518 | ; This option applies to condition and expression coverage UDP tables. It 1519 | ; has no effect unless UDP is enabled for coverage with vcom/vlog/vopt -coverudp. 1520 | ; If this option is used and a match occurs in more than one row in the UDP table, 1521 | ; none of the counts for all matching rows is incremented. By default, counts are 1522 | ; incremented for all matching rows. 1523 | ; CoverCountAll = 1 1524 | 1525 | ; Turn off automatic inclusion of VHDL integers in toggle coverage. Default 1526 | ; is to include them. 1527 | ; ToggleNoIntegers = 1 1528 | 1529 | ; Set the maximum number of values that are collected for toggle coverage of 1530 | ; VHDL integers. Default is 100; 1531 | ; ToggleMaxIntValues = 100 1532 | 1533 | ; Set the maximum number of values that are collected for toggle coverage of 1534 | ; Verilog real. Default is 100; 1535 | ; ToggleMaxRealValues = 100 1536 | 1537 | ; Turn on automatic inclusion of Verilog integers in toggle coverage, except 1538 | ; for enumeration types. Default is to include them. 1539 | ; ToggleVlogIntegers = 0 1540 | 1541 | ; Turn on automatic inclusion of Verilog real type in toggle coverage, except 1542 | ; for shortreal types. Default is to not include them. 1543 | ; ToggleVlogReal = 1 1544 | 1545 | ; Turn on automatic inclusion of Verilog fixed-size unpacked arrays, VHDL multi-d arrays 1546 | ; and VHDL arrays-of-arrays in toggle coverage. 1547 | ; Default is to not include them. 1548 | ; ToggleFixedSizeArray = 1 1549 | 1550 | ; Increase or decrease the maximum size of Verilog unpacked fixed-size arrays, 1551 | ; VHDL multi-d arrays and VHDL arrays-of-arrays that are included for toggle coverage. 1552 | ; This leads to a longer simulation time with bigger arrays covered with toggle coverage. 1553 | ; Default is 1024. 1554 | ; ToggleMaxFixedSizeArray = 1024 1555 | 1556 | ; Treat Verilog multi-dimensional packed vectors and packed structures as equivalently sized 1557 | ; one-dimensional packed vectors for toggle coverage. Default is 0. 1558 | ; TogglePackedAsVec = 0 1559 | 1560 | ; Treat Verilog enumerated types as equivalently sized one-dimensional packed vectors for 1561 | ; toggle coverage. Default is 0. 1562 | ; ToggleVlogEnumBits = 0 1563 | 1564 | ; Turn off automatic inclusion of VHDL records in toggle coverage. 1565 | ; Default is to include them. 1566 | ; ToggleVHDLRecords = 0 1567 | 1568 | ; Limit the widths of registers automatically tracked for toggle coverage. Default is 128. 1569 | ; For unlimited width, set to 0. 1570 | ; ToggleWidthLimit = 128 1571 | 1572 | ; Limit the counts that are tracked for toggle coverage. When all edges for a bit have 1573 | ; reached this count, further activity on the bit is ignored. Default is 1. 1574 | ; For unlimited counts, set to 0. 1575 | ; ToggleCountLimit = 1 1576 | 1577 | ; Change the mode of extended toggle coverage. Default is 3. Valid modes are 1, 2 and 3. 1578 | ; Following is the toggle coverage calculation criteria based on extended toggle mode: 1579 | ; Mode 1: 0L->1H & 1H->0L & any one 'Z' transition (to/from 'Z'). 1580 | ; Mode 2: 0L->1H & 1H->0L & one transition to 'Z' & one transition from 'Z'. 1581 | ; Mode 3: 0L->1H & 1H->0L & all 'Z' transitions. 1582 | ; ExtendedToggleMode = 3 1583 | 1584 | ; Enable toggle statistics collection only for ports. Default is 0. 1585 | ; TogglePortsOnly = 1 1586 | 1587 | ; Limit the counts that are tracked for Focussed Expression Coverage. When a bin has 1588 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1589 | ; Default is 1. For unlimited counts, set to 0. 1590 | ; NOTE: Changing this value from its default value may affect simulation performance. 1591 | ; FecCountLimit = 1 1592 | 1593 | ; Limit the counts that are tracked for UDP Coverage. When a bin has 1594 | ; reached this count, further tracking of the input patterns linked to it is ignored. 1595 | ; Default is 1. For unlimited counts, set to 0. 1596 | ; NOTE: Changing this value from its default value may affect simulation performance. 1597 | ; UdpCountLimit = 1 1598 | 1599 | ; Control toggle coverage deglitching period. A period of 0, eliminates delta 1600 | ; cycle glitches. This is the default. The value of ToggleDeglitchPeriod needs to be either 1601 | ; 0 or a time string that includes time units. Examples: 0 or 10.0ps or "10.0 ps". 1602 | ; ToggleDeglitchPeriod = 10.0ps 1603 | 1604 | ; Turn on/off all PSL/SVA cover directive enables. Default is on. 1605 | ; CoverEnable = 0 1606 | 1607 | ; Turn on/off PSL/SVA cover log. Default is off "0". 1608 | ; CoverLog = 1 1609 | 1610 | ; Set "at_least" value for all PSL/SVA cover directives. Default is 1. 1611 | ; CoverAtLeast = 2 1612 | 1613 | ; Set "limit" value for all PSL/SVA cover directives. Default is -1. 1614 | ; Any positive integer, -1 for infinity. 1615 | ; CoverLimit = 1 1616 | 1617 | ; Specify the coverage database filename. 1618 | ; Default is "" (i.e. database is NOT automatically saved on close). 1619 | ; UCDBFilename = vsim.ucdb 1620 | 1621 | ; Specify the maximum limit for the number of Cross (bin) products reported 1622 | ; in XML and UCDB report against a Cross. A warning is issued if the limit 1623 | ; is crossed. Default is zero. vsim switch -cvgmaxrptrhscross can override this 1624 | ; setting. 1625 | ; MaxReportRhsSVCrossProducts = 1000 1626 | 1627 | ; Specify the override for the "auto_bin_max" option for the Covergroups. 1628 | ; If not specified then value from Covergroup "option" is used. 1629 | ; SVCoverpointAutoBinMax = 64 1630 | 1631 | ; Specify the override for the value of "cross_num_print_missing" 1632 | ; option for the Cross in Covergroups. If not specified then value 1633 | ; specified in the "option.cross_num_print_missing" is used. This 1634 | ; is a runtime option. NOTE: This overrides any "cross_num_print_missing" 1635 | ; value specified by user in source file and any SVCrossNumPrintMissingDefault 1636 | ; specified in modelsim.ini. 1637 | ; SVCrossNumPrintMissing = 0 1638 | 1639 | ; Specify whether to use the value of "cross_num_print_missing" 1640 | ; option in report and GUI for the Cross in Covergroups. If not specified then 1641 | ; cross_num_print_missing is ignored for creating reports and displaying 1642 | ; covergroups in GUI. Default is 0, which means ignore "cross_num_print_missing". 1643 | ; UseSVCrossNumPrintMissing = 0 1644 | 1645 | ; Specify the threshold of Coverpoint wildcard bin value range size, above which 1646 | ; a warning will be triggered. The default is 4K -- 12 wildcard bits. 1647 | ; SVCoverpointWildCardBinValueSizeWarn = 4096 1648 | 1649 | ; Specify the override for the value of "strobe" option for the 1650 | ; Covergroup Type. If not specified then value in "type_option.strobe" 1651 | ; will be used. This is runtime option which forces "strobe" to 1652 | ; user specified value and supersedes user specified values in the 1653 | ; SystemVerilog Code. NOTE: This also overrides the compile time 1654 | ; default value override specified using "SVCovergroupStrobeDefault" 1655 | ; SVCovergroupStrobe = 0 1656 | 1657 | ; Override for explicit assignments in source code to "option.goal" of 1658 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1659 | ; default value of "option.goal" (defined to be 100 in the SystemVerilog 1660 | ; LRM) and the value of modelsim.ini variable "SVCovergroupGoalDefault". 1661 | ; SVCovergroupGoal = 100 1662 | 1663 | ; Override for explicit assignments in source code to "type_option.goal" of 1664 | ; SystemVerilog covergroup, coverpoint, and cross. It also overrides the 1665 | ; default value of "type_option.goal" (defined to be 100 in the SystemVerilog 1666 | ; LRM) and the value of modelsim.ini variable "SVCovergroupTypeGoalDefault". 1667 | ; SVCovergroupTypeGoal = 100 1668 | 1669 | ; Enforce the 6.3 behavior of covergroup get_coverage() and get_inst_coverage() 1670 | ; builtin functions, and report. This setting changes the default values of 1671 | ; option.get_inst_coverage and type_option.merge_instances to ensure the 6.3 1672 | ; behavior if explicit assignments are not made on option.get_inst_coverage and 1673 | ; type_option.merge_instances by the user. There are two vsim command line 1674 | ; options, -cvg63 and -nocvg63 to override this setting from vsim command line. 1675 | ; The default value of this variable from release 6.6 onwards is 0. This default 1676 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1677 | ; SVCovergroup63Compatibility = 0 1678 | 1679 | ; Enforce the default behavior of covergroup get_coverage() builtin function, GUI 1680 | ; and report. This variable sets the default value of type_option.merge_instances. 1681 | ; There are two vsim command line options, -cvgmergeinstances and 1682 | ; -nocvgmergeinstances to override this setting from vsim command line. 1683 | ; The default value of this variable is 0. This default 1684 | ; drives compliance with the clarified behavior in the IEEE 1800-2009 standard. 1685 | ; SVCovergroupMergeInstancesDefault = 0 1686 | 1687 | ; Enable or disable generation of more detailed information about the sampling 1688 | ; of covergroup, cross, and coverpoints. It provides the details of the number 1689 | ; of times the covergroup instance and type were sampled, as well as details 1690 | ; about why covergroup, cross and coverpoint were not covered. A non-zero value 1691 | ; is to enable this feature. 0 is to disable this feature. Default is 0 1692 | ; SVCovergroupSampleInfo = 0 1693 | 1694 | ; Specify the maximum number of Coverpoint bins in whole design for 1695 | ; all Covergroups. 1696 | ; MaxSVCoverpointBinsDesign = 2147483648 1697 | 1698 | ; Specify maximum number of Coverpoint bins in any instance of a Covergroup, default is 2^10 bins 1699 | ; MaxSVCoverpointBinsInst = 1048576 1700 | 1701 | ; Specify the maximum number of Cross bins in whole design for 1702 | ; all Covergroups. 1703 | ; MaxSVCrossBinsDesign = 2147483648 1704 | 1705 | ; Specify maximum number of Cross bins in any instance of a Covergroup, default is 2^16 bins 1706 | ; MaxSVCrossBinsInst = 67108864 1707 | 1708 | ; Specify whether vsim will collect the coverage data of zero-weight coverage items or not. 1709 | ; By default, this variable is set 0, in which case option.no_collect setting will take effect. 1710 | ; If this variable is set to 1, all zero-weight coverage items will not be saved. 1711 | ; Note that the usage of vsim switch -cvgzwnocollect, if present, will override the setting 1712 | ; of this variable. 1713 | ; CvgZWNoCollect = 1 1714 | 1715 | ; Specify a space delimited list of double quoted TCL style 1716 | ; regular expressions which will be matched against the text of all messages. 1717 | ; If any regular expression is found to be contained within any message, the 1718 | ; status for that message will not be propagated to the UCDB TESTSTATUS. 1719 | ; If no match is detected, then the status will be propagated to the 1720 | ; UCDB TESTSTATUS. More than one such regular expression text is allowed, 1721 | ; and each message text is compared for each regular expression in the list. 1722 | ; UCDBTestStatusMessageFilter = "Done with Test Bench" "Ignore .* message" 1723 | 1724 | ; Set weight for all PSL/SVA cover directives. Default is 1. 1725 | ; CoverWeight = 2 1726 | 1727 | ; Check vsim plusargs. Default is 0 (off). 1728 | ; 0 = Don't check plusargs 1729 | ; 1 = Warning on unrecognized plusarg 1730 | ; 2 = Error and exit on unrecognized plusarg 1731 | ; CheckPlusargs = 1 1732 | 1733 | ; Load the specified shared objects with the RTLD_GLOBAL flag. 1734 | ; This gives global visibility to all symbols in the shared objects, 1735 | ; meaning that subsequently loaded shared objects can bind to symbols 1736 | ; in the global shared objects. The list of shared objects should 1737 | ; be whitespace delimited. This option is not supported on the 1738 | ; Windows or AIX platforms. 1739 | ; GlobalSharedObjectList = example1.so example2.so example3.so 1740 | 1741 | ; Generate the stub definitions for the undefined symbols in the shared libraries being 1742 | ; loaded in the simulation. When this flow is turned on, the undefined symbols will not 1743 | ; prevent vsim from loading. Calling undefined symbols at runtime will cause fatal error. 1744 | ; The valid arguments are: on, off, verbose. 1745 | ; on : turn on the automatic generation of stub definitions. 1746 | ; off: turn off the flow. The undefined symbols will trigger an immediate load failure. 1747 | ; verbose: Turn on the flow and report the undefined symbols for each shared library. 1748 | ; NOTE: This variable can be overriden with vsim switch "-undefsyms". 1749 | ; The default is off. 1750 | ; 1751 | ; UndefSyms = on 1752 | 1753 | ; Initial seed for the random number generator of the root thread (SystemVerilog). 1754 | ; NOTE: This variable can be overridden with the vsim "-sv_seed" command line switch. 1755 | ; The default value is 0. 1756 | ; Sv_Seed = 0 1757 | 1758 | ; Specify the solver "engine" that vsim will select for constrained random 1759 | ; generation. 1760 | ; Valid values are: 1761 | ; "auto" - automatically select the best engine for the current 1762 | ; constraint scenario 1763 | ; "bdd" - evaluate all constraint scenarios using the BDD solver engine 1764 | ; "act" - evaluate all constraint scenarios using the ACT solver engine 1765 | ; While the BDD solver engine is generally efficient with constraint scenarios 1766 | ; involving bitwise logical relationships, the ACT solver engine can exhibit 1767 | ; superior performance with constraint scenarios involving large numbers of 1768 | ; random variables related via arithmetic operators (+, *, etc). 1769 | ; NOTE: This variable can be overridden with the vsim "-solveengine" command 1770 | ; line switch. 1771 | ; The default value is "auto". 1772 | ; SolveEngine = auto 1773 | 1774 | ; Specify if the solver should attempt to ignore overflow/underflow semantics 1775 | ; for arithmetic constraints (multiply, addition, subtraction) in order to 1776 | ; improve performance. The "solveignoreoverflow" attribute can be specified on 1777 | ; a per-call basis to randomize() to override this setting. 1778 | ; The default value is 0 (overflow/underflow is not ignored). Set to 1 to 1779 | ; ignore overflow/underflow. 1780 | ; SolveIgnoreOverflow = 0 1781 | 1782 | ; Specifies the maximum size that a dynamic array may be resized to by the 1783 | ; solver. If the solver attempts to resize a dynamic array to a size greater 1784 | ; than the specified limit, the solver will abort with an error. 1785 | ; The default value is 10000. A value of 0 indicates no limit. 1786 | ; SolveArrayResizeMax = 10000 1787 | 1788 | ; Error message severity when randomize() failure is detected (SystemVerilog). 1789 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1790 | ; The default is 0 (no error). 1791 | ; SolveFailSeverity = 0 1792 | 1793 | ; Error message severity for suppressible errors that are detected in a 1794 | ; solve/before constraint. 1795 | ; NOTE: This variable can be overridden with the vsim "-solvebeforeerrorseverity" 1796 | ; command line switch. 1797 | ; 0 = No error 1 = Warning 2 = Error 3 = Failure 4 = Fatal 1798 | ; The default is 3 (failure). 1799 | ; SolveBeforeErrorSeverity = 3 1800 | 1801 | ; Enable/disable debug information for randomize() failures. 1802 | ; NOTE: This variable can be overridden with the vsim "-solvefaildebug" command 1803 | ; line switch. 1804 | ; The default is 0 (disabled). Set to 1 to enable basic debug (with no 1805 | ; performance penalty). Set to 2 for enhanced debug (will result in slower 1806 | ; runtime performance). 1807 | ; SolveFailDebug = 0 1808 | 1809 | ; Upon encountering a randomize() failure, generate a simplified testcase that 1810 | ; will reproduce the failure. Optionally output the testcase to a file. 1811 | ; Testcases for 'no-solution' failures will only be produced if SolveFailDebug 1812 | ; is enabled (see above). 1813 | ; NOTE: This variable can be overridden with the vsim "-solvefailtestcase" 1814 | ; command line switch. 1815 | ; The default is OFF (do not generate a testcase). To enable testcase 1816 | ; generation, uncomment this variable. To redirect testcase generation to a 1817 | ; file, specify the name of the output file. 1818 | ; SolveFailTestcase = 1819 | 1820 | ; Specify solver timeout threshold (in seconds). randomize() will fail if the 1821 | ; CPU time required to evaluate any randset exceeds the specified timeout. 1822 | ; The default value is 500. A value of 0 will disable timeout failures. 1823 | ; SolveTimeout = 500 1824 | 1825 | ; Specify the maximum size of the solution graph generated by the BDD solver. 1826 | ; This value can be used to force the BDD solver to abort the evaluation of a 1827 | ; complex constraint scenario that cannot be evaluated with finite memory. 1828 | ; This value is specified in 1000s of nodes. 1829 | ; The default value is 10000. A value of 0 indicates no limit. 1830 | ; SolveGraphMaxSize = 10000 1831 | 1832 | ; Specify the maximum number of evaluations that may be performed on the 1833 | ; solution graph by the BDD solver. This value can be used to force the BDD 1834 | ; solver to abort the evaluation of a complex constraint scenario that cannot 1835 | ; be evaluated in finite time. This value is specified in 10000s of evaluations. 1836 | ; The default value is 10000. A value of 0 indicates no limit. 1837 | ; SolveGraphMaxEval = 10000 1838 | 1839 | ; Specify the maximum number of tests that the ACT solver may evaluate before 1840 | ; abandoning an attempt to solve a particular constraint scenario. 1841 | ; The default value is 2000000. A value of 0 indicates no limit. 1842 | ; SolveACTMaxTests = 2000000 1843 | 1844 | ; Specify the maximum number of operations that the ACT solver may perform 1845 | ; before abandoning an attempt to solve a particular constraint scenario. The 1846 | ; value is specified in 1000000s of operations. 1847 | ; The default value is 10000. A value of 0 indicates no limit. 1848 | ; SolveACTMaxOps = 10000 1849 | 1850 | ; Specify the number of times the ACT solver will retry to evaluate a constraint 1851 | ; scenario that fails due to the SolveACTMax[Tests|Ops] threshold. 1852 | ; The default value is 0 (no retry). 1853 | ; SolveACTRetryCount = 0 1854 | 1855 | ; Specify random sequence compatiblity with a prior letter release. This 1856 | ; option is used to get the same random sequences during simulation as 1857 | ; as a prior letter release. Only prior letter releases (of the current 1858 | ; number release) are allowed. 1859 | ; NOTE: Only those random sequence changes due to solver optimizations are 1860 | ; reverted by this variable. Random sequence changes due to solver bugfixes 1861 | ; cannot be un-done. 1862 | ; NOTE: This variable can be overridden with the vsim "-solverev" command 1863 | ; line switch. 1864 | ; Default value set to "" (no compatibility). 1865 | ; SolveRev = 1866 | 1867 | ; Environment variable expansion of command line arguments has been depricated 1868 | ; in favor shell level expansion. Universal environment variable expansion 1869 | ; inside -f files is support and continued support for MGC Location Maps provide 1870 | ; alternative methods for handling flexible pathnames. 1871 | ; The following line may be uncommented and the value set to 1 to re-enable this 1872 | ; deprecated behavior. The default value is 0. 1873 | ; DeprecatedEnvironmentVariableExpansion = 0 1874 | 1875 | ; Specify the memory threshold for the System Verilog garbage collector. 1876 | ; The value is the number of megabytes of class objects that must accumulate 1877 | ; before the garbage collector is run. 1878 | ; The GCThreshold setting is used when class debug mode is disabled to allow 1879 | ; less frequent garbage collection and better simulation performance. 1880 | ; The GCThresholdClassDebug setting is used when class debug mode is enabled 1881 | ; to allow for more frequent garbage collection. 1882 | ; GCThreshold = 100 1883 | ; GCThresholdClassDebug = 5 1884 | 1885 | ; Turn on/off collapsing of bus ports in VCD dumpports output 1886 | DumpportsCollapse = 1 1887 | 1888 | ; Location of Multi-Level Verification Component (MVC) installation. 1889 | ; The default location is the product installation directory. 1890 | MvcHome = $MODEL_TECH/.. 1891 | 1892 | ; Location of InFact installation. The default is $MODEL_TECH/../../infact 1893 | ; 1894 | ; InFactHome = $MODEL_TECH/../../infact 1895 | 1896 | ; Initialize SystemVerilog enums using the base type's default value 1897 | ; instead of the leftmost value. 1898 | ; EnumBaseInit = 1 1899 | 1900 | ; Suppress file type registration. 1901 | ; SuppressFileTypeReg = 1 1902 | 1903 | ; Controls SystemVerilog Language Extensions. These options enable 1904 | ; some non-LRM compliant behavior. Valid extensions are "cfce", 1905 | ; SvExtensions = cfce 1906 | 1907 | ; Controls the formatting of '%p' and '%P' conversion specification, used in $display 1908 | ; and similar system tasks. 1909 | ; 1. SVPrettyPrintFlags=I use spaces(S) or tabs(T) per indentation level. 1910 | ; The 'I' flag when present causes relevant data types to be expanded and indented into 1911 | ; a more readable format. 1912 | ; (e.g. SVPrettyPrintFlags=I4S will cause 4 spaces to be used per indentation level). 1913 | ; 2. SVPrettyPrintFlags=L limits the output to lines. 1914 | ; (e.g. SVPrettyPrintFlags=L20 will limit the output to 20 lines). 1915 | ; 3. SVPrettyPrintFlags=C limits the output to characters. 1916 | ; (e.g. SVPrettyPrintFlags=C256 will limit the output to 256 characters). 1917 | ; 4. SVPrettyPrintFlags=F limits the output to of relevant datatypes 1918 | ; (e.g. SVPrettyPrintFlags=F4 will limit the output to 4 fields of a structure). 1919 | ; 5. SVPrettyPrintFlags=E limits the output to of relevant datatypes 1920 | ; (e.g. SVPrettyPrintFlags=E50 will limit the output to 50 elements of an array). 1921 | ; 6. SVPrettyPrintFlags=D suppresses the output of sub-elements below . 1922 | ; (e.g. SVPrettyPrintFlags=D5 will suppresses the output of sub elements below a depth of 5). 1923 | ; 7. Items 1-6 above can be combined as a comma separated list. 1924 | ; (e.g. SVPrettyPrintFlags=I4S,L20,C256,F4,E50,D5) 1925 | ; SVPrettyPrintFlags=I4S 1926 | 1927 | [lmc] 1928 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software 1929 | libsm = $MODEL_TECH/libsm.sl 1930 | ; The simulator's interface to Logic Modeling's SmartModel SWIFT software (Windows NT) 1931 | ; libsm = $MODEL_TECH/libsm.dll 1932 | ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) 1933 | ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl 1934 | ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) 1935 | ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o 1936 | ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) 1937 | ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so 1938 | ; Logic Modeling's SmartModel SWIFT software (Windows NT) 1939 | ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll 1940 | ; Logic Modeling's SmartModel SWIFT software (non-Enterprise versions of Linux) 1941 | ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so 1942 | ; Logic Modeling's SmartModel SWIFT software (Enterprise versions of Linux) 1943 | ; libswift = $LMC_HOME/lib/linux.lib/libswift.so 1944 | 1945 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software 1946 | libhm = $MODEL_TECH/libhm.sl 1947 | ; The simulator's interface to Logic Modeling's hardware modeler SFI software (Windows NT) 1948 | ; libhm = $MODEL_TECH/libhm.dll 1949 | ; Logic Modeling's hardware modeler SFI software (HP 9000 Series 700) 1950 | ; libsfi = /lib/hp700/libsfi.sl 1951 | ; Logic Modeling's hardware modeler SFI software (IBM RISC System/6000) 1952 | ; libsfi = /lib/rs6000/libsfi.a 1953 | ; Logic Modeling's hardware modeler SFI software (Sun4 Solaris) 1954 | ; libsfi = /lib/sun4.solaris/libsfi.so 1955 | ; Logic Modeling's hardware modeler SFI software (Windows NT) 1956 | ; libsfi = /lib/pcnt/lm_sfi.dll 1957 | ; Logic Modeling's hardware modeler SFI software (Linux) 1958 | ; libsfi = /lib/linux/libsfi.so 1959 | 1960 | [msg_system] 1961 | ; Change a message severity or suppress a message. 1962 | ; The format is: = [,...] 1963 | ; suppress can be used to achieve +nowarn functionality 1964 | ; The format is: suppress = ,,[,,...] 1965 | ; Examples: 1966 | suppress = 8780 ;an explanation can be had by running: verror 8780 1967 | ; note = 3009 1968 | ; warning = 3033 1969 | ; error = 3010,3016 1970 | ; fatal = 3016,3033 1971 | ; suppress = 3009,3016,3601 1972 | ; suppress = 3009,CNNODP,3601,TFMPC 1973 | ; suppress = 8683,8684 1974 | ; The command verror can be used to get the complete 1975 | ; description of a message. 1976 | 1977 | ; Control transcripting of Verilog display system task messages and 1978 | ; PLI/FLI print function call messages. The system tasks include 1979 | ; $display[bho], $strobe[bho], $monitor[bho], and $write[bho]. They 1980 | ; also include the analogous file I/O tasks that write to STDOUT 1981 | ; (i.e. $fwrite or $fdisplay). The PLI/FLI calls include io_printf, 1982 | ; vpi_printf, mti_PrintMessage, and mti_PrintFormatted. The default 1983 | ; is to have messages appear only in the transcript. The other 1984 | ; settings are to send messages to the wlf file only (messages that 1985 | ; are recorded in the wlf file can be viewed in the MsgViewer) or 1986 | ; to both the transcript and the wlf file. The valid values are 1987 | ; tran {transcript only (default)} 1988 | ; wlf {wlf file only} 1989 | ; both {transcript and wlf file} 1990 | ; displaymsgmode = tran 1991 | 1992 | ; Control transcripting of elaboration/runtime messages not 1993 | ; addressed by the displaymsgmode setting. The default is to 1994 | ; have messages appear only in the transcript. The other settings 1995 | ; are to send messages to the wlf file only (messages that are 1996 | ; recorded in the wlf file can be viewed in the MsgViewer) or to both 1997 | ; the transcript and the wlf file. The valid values are 1998 | ; tran {transcript only (default)} 1999 | ; wlf {wlf file only} 2000 | ; both {transcript and wlf file} 2001 | ; msgmode = tran 2002 | 2003 | ; Controls number of displays of a particluar message 2004 | ; default value is 5 2005 | ; MsgLimitCount = 5 2006 | 2007 | [utils] 2008 | ; Default Library Type (while creating a library with "vlib") 2009 | ; 0 - legacy library using subdirectories for design units 2010 | ; 2 - flat library 2011 | ; DefaultLibType = 2 2012 | 2013 | ; Flat Library Page Size (while creating a library with "vlib") 2014 | ; Set the size in bytes for flat library file pages. Libraries containing 2015 | ; very large files may benefit from a larger value. 2016 | ; FlatLibPageSize = 8192 2017 | 2018 | ; Flat Library Page Cleanup Percentage (while creating a library with "vlib") 2019 | ; Set the percentage of total pages deleted before library cleanup can occur. 2020 | ; This setting is applied together with FlatLibPageDeleteThreshold. 2021 | ; FlatLibPageDeletePercentage = 50 2022 | 2023 | ; Flat Library Page Cleanup Threshold (while creating a library with "vlib") 2024 | ; Set the number of pages deleted before library cleanup can occur. 2025 | ; This setting is applied together with FlatLibPageDeletePercentage. 2026 | ; FlatLibPageDeleteThreshold = 1000 2027 | 2028 | [Project] 2029 | ; Warning -- Do not edit the project properties directly. 2030 | ; Property names are dynamic in nature and property 2031 | ; values have special syntax. Changing property data directly 2032 | ; can result in a corrupt MPF file. All project properties 2033 | ; can be modified through project window dialogs. 2034 | Project_Version = 6 2035 | Project_DefaultLib = work 2036 | Project_SortMethod = unused 2037 | Project_Files_Count = 2 2038 | Project_File_0 = C:/Users/user/Desktop/MAC_verilog/mac.v 2039 | Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 vlog_noload 0 cover_branch 0 folder {Top Level} last_compile 1550412910 cover_fsm 0 cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 0 cover_expr 0 dont_compile 0 cover_stmt 0 2040 | Project_File_1 = C:/Users/user/Desktop/MAC_verilog/mac_tb.v 2041 | Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_nofec 0 cover_cond 0 vlog_1995compat 0 vlog_nodebug 0 cover_fsm 0 cover_branch 0 vlog_noload 0 last_compile 1547786811 folder {Top Level} cover_excludedefault 0 vlog_enable0In 0 vlog_disableopt 0 cover_covercells 0 voptflow 1 cover_optlevel 3 vlog_showsource 0 vlog_hazard 0 toggle - vlog_0InOptions {} ood 0 cover_noshort 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 cover_stmt 0 2042 | Project_Sim_Count = 0 2043 | Project_Folder_Count = 0 2044 | Echo_Compile_Output = 0 2045 | Save_Compile_Report = 1 2046 | Project_Opt_Count = 0 2047 | ForceSoftPaths = 0 2048 | ProjectStatusDelay = 5000 2049 | VERILOG_DoubleClick = Edit 2050 | VERILOG_CustomDoubleClick = 2051 | SYSTEMVERILOG_DoubleClick = Edit 2052 | SYSTEMVERILOG_CustomDoubleClick = 2053 | VHDL_DoubleClick = Edit 2054 | VHDL_CustomDoubleClick = 2055 | PSL_DoubleClick = Edit 2056 | PSL_CustomDoubleClick = 2057 | TEXT_DoubleClick = Edit 2058 | TEXT_CustomDoubleClick = 2059 | SYSTEMC_DoubleClick = Edit 2060 | SYSTEMC_CustomDoubleClick = 2061 | TCL_DoubleClick = Edit 2062 | TCL_CustomDoubleClick = 2063 | MACRO_DoubleClick = Edit 2064 | MACRO_CustomDoubleClick = 2065 | VCD_DoubleClick = Edit 2066 | VCD_CustomDoubleClick = 2067 | SDF_DoubleClick = Edit 2068 | SDF_CustomDoubleClick = 2069 | XML_DoubleClick = Edit 2070 | XML_CustomDoubleClick = 2071 | LOGFILE_DoubleClick = Edit 2072 | LOGFILE_CustomDoubleClick = 2073 | UCDB_DoubleClick = Edit 2074 | UCDB_CustomDoubleClick = 2075 | TDB_DoubleClick = Edit 2076 | TDB_CustomDoubleClick = 2077 | UPF_DoubleClick = Edit 2078 | UPF_CustomDoubleClick = 2079 | PCF_DoubleClick = Edit 2080 | PCF_CustomDoubleClick = 2081 | PROJECT_DoubleClick = Edit 2082 | PROJECT_CustomDoubleClick = 2083 | VRM_DoubleClick = Edit 2084 | VRM_CustomDoubleClick = 2085 | DEBUGDATABASE_DoubleClick = Edit 2086 | DEBUGDATABASE_CustomDoubleClick = 2087 | DEBUGARCHIVE_DoubleClick = Edit 2088 | DEBUGARCHIVE_CustomDoubleClick = 2089 | Project_Major_Version = 10 2090 | Project_Minor_Version = 4 2091 | --------------------------------------------------------------------------------