├── .gitignore ├── CREDITS.md ├── Docs └── Images │ ├── konata.gif │ ├── rsd.png │ └── rsd.pptx ├── LICENSE ├── Processor ├── Project │ ├── DesignCompiler │ │ ├── Makefile │ │ └── compile.tcl │ ├── Synplify │ │ ├── code.hex │ │ └── ver2017-03.prj │ ├── Vivado │ │ ├── ARM_Linux │ │ │ ├── ProgramLoader │ │ │ │ └── loader.c │ │ │ ├── boot.bif │ │ │ ├── linux-xlnx │ │ │ │ └── linux-xlnx.rsd.diff │ │ │ └── u-boot-xlnx │ │ │ │ └── u-boot-xlnx.rsd.diff │ │ └── TargetBoards │ │ │ └── Zedboard │ │ │ ├── project_src │ │ │ ├── run_simple.c │ │ │ └── zedboard.xdc │ │ │ ├── rsd_ip │ │ │ ├── Synplify │ │ │ │ ├── component.xml │ │ │ │ └── xgui │ │ │ │ │ ├── Main_v1_0.tcl │ │ │ │ │ └── RSD_v1_0.tcl │ │ │ └── Vivado │ │ │ │ └── xgui │ │ │ │ └── RSD_v1_0.tcl │ │ │ └── scripts │ │ │ ├── post_synthesis │ │ │ ├── create_project_for_questasim.tcl │ │ │ ├── create_project_for_vivadosim.tcl │ │ │ ├── run_implementation.tcl │ │ │ ├── run_synthesis.tcl │ │ │ └── sim_post_synthesis.tcl │ │ │ └── synthesis │ │ │ ├── create_project.tcl │ │ │ ├── create_project_using_synplify_netlist.tcl │ │ │ ├── design_1.tcl │ │ │ ├── generate_bitstream.tcl │ │ │ └── make_fsbl.tcl │ └── VivadoSim │ │ ├── .gitignore │ │ └── Src ├── Src │ ├── .svlint.toml │ ├── .svls.toml │ ├── .vscode │ │ ├── c_cpp_properties.json │ │ ├── launch.json │ │ ├── settings.json │ │ └── tasks.json │ ├── BasicMacros.sv │ ├── BasicTypes.sv │ ├── Cache │ │ ├── CacheFlushManager.sv │ │ ├── CacheFlushManagerIF.sv │ │ ├── CacheSystemIF.sv │ │ ├── CacheSystemTypes.sv │ │ ├── DCache.sv │ │ ├── DCacheIF.sv │ │ ├── ICache.sv │ │ └── MemoryAccessController.sv │ ├── Controller.sv │ ├── ControllerIF.sv │ ├── Core.sv │ ├── Debug │ │ ├── Debug.sv │ │ ├── DebugIF.sv │ │ ├── DebugTypes.sv │ │ ├── PerformanceCounter.sv │ │ └── PerformanceCounterIF.sv │ ├── Decoder │ │ ├── DecodedBranchResolver.sv │ │ ├── Decoder.sv │ │ ├── MicroOp.sv │ │ └── OpFormat.sv │ ├── ExecUnit │ │ ├── BitCounter.sv │ │ ├── DividerUnit.sv │ │ ├── IntALU.sv │ │ ├── MultiplierUnit.sv │ │ ├── PipelinedRefDivider.sv │ │ └── Shifter.sv │ ├── FetchUnit │ │ ├── BTB.sv │ │ ├── Bimodal.sv │ │ ├── BranchPredictor.sv │ │ ├── FetchUnitTypes.sv │ │ └── Gshare.sv │ ├── FloatingPointUnit │ │ ├── FP32DivSqrter.sv │ │ ├── FP32PipelinedAdder.sv │ │ ├── FP32PipelinedFMA.sv │ │ ├── FP32PipelinedMultiplier.sv │ │ ├── FP32PipelinedOther.sv │ │ ├── FPDivSqrtUnit.sv │ │ ├── FPDivSqrtUnitIF.sv │ │ └── FPUTypes.sv │ ├── IO │ │ ├── IO_Unit.sv │ │ ├── IO_UnitIF.sv │ │ └── IO_UnitTypes.sv │ ├── LoadStoreUnit │ │ ├── LoadQueue.sv │ │ ├── LoadStoreUnit.sv │ │ ├── LoadStoreUnitIF.sv │ │ ├── LoadStoreUnitTypes.sv │ │ ├── StoreCommitter.sv │ │ └── StoreQueue.sv │ ├── Main.sv │ ├── Main_Fpga.sv │ ├── Main_Vivado.v │ ├── Main_Zynq.sv │ ├── Main_Zynq_Wrapper.sv │ ├── Makefile │ ├── Makefile.inc │ ├── Makefile.synplify.mk │ ├── Makefile.verilator.mk │ ├── Makefile.vivado.mk │ ├── Makefiles │ │ ├── CoreSources.inc.mk │ │ ├── TestCommands.inc.mk │ │ └── Vivado.inc.mk │ ├── Memory │ │ ├── Axi4LiteControlMemoryIF.sv │ │ ├── Axi4LiteControlRegister.sv │ │ ├── Axi4LiteControlRegisterIF.sv │ │ ├── Axi4LiteMemory.sv │ │ ├── Axi4Memory.sv │ │ ├── Axi4MemoryIF.sv │ │ ├── ControlQueue.sv │ │ ├── Memory.sv │ │ ├── MemoryLatencySimulator.sv │ │ ├── MemoryMapTypes.sv │ │ ├── MemoryReadReqQueue.sv │ │ ├── MemoryTypes.sv │ │ └── MemoryWriteDataQueue.sv │ ├── MicroArchConf.sv │ ├── MulDivUnit │ │ ├── MulDivUnit.sv │ │ └── MulDivUnitIF.sv │ ├── Pipeline │ │ ├── CommitStage.sv │ │ ├── CommitStageIF.sv │ │ ├── ComplexIntegerBackEnd │ │ │ ├── ComplexIntegerExecutionStage.sv │ │ │ ├── ComplexIntegerExecutionStageIF.sv │ │ │ ├── ComplexIntegerIssueStage.sv │ │ │ ├── ComplexIntegerIssueStageIF.sv │ │ │ ├── ComplexIntegerRegisterReadStage.sv │ │ │ ├── ComplexIntegerRegisterReadStageIF.sv │ │ │ └── ComplexIntegerRegisterWriteStage.sv │ │ ├── DecodeStage.sv │ │ ├── DecodeStageIF.sv │ │ ├── DispatchStage.sv │ │ ├── DispatchStageIF.sv │ │ ├── FPBackEnd │ │ │ ├── FPExecutionStage.sv │ │ │ ├── FPExecutionStageIF.sv │ │ │ ├── FPIssueStage.sv │ │ │ ├── FPIssueStageIF.sv │ │ │ ├── FPRegisterReadStage.sv │ │ │ ├── FPRegisterReadStageIF.sv │ │ │ └── FPRegisterWriteStage.sv │ │ ├── FetchStage │ │ │ ├── FetchStage.sv │ │ │ ├── FetchStageIF.sv │ │ │ ├── NextPCStage.sv │ │ │ ├── NextPCStageIF.sv │ │ │ └── PC.sv │ │ ├── IntegerBackEnd │ │ │ ├── IntegerExecutionStage.sv │ │ │ ├── IntegerExecutionStageIF.sv │ │ │ ├── IntegerIssueStage.sv │ │ │ ├── IntegerIssueStageIF.sv │ │ │ ├── IntegerRegisterReadStage.sv │ │ │ ├── IntegerRegisterReadStageIF.sv │ │ │ ├── IntegerRegisterWriteStage.sv │ │ │ └── IntegerRegisterWriteStageIF.sv │ │ ├── MemoryBackEnd │ │ │ ├── MemoryAccessStage.sv │ │ │ ├── MemoryAccessStageIF.sv │ │ │ ├── MemoryExecutionStage.sv │ │ │ ├── MemoryExecutionStageIF.sv │ │ │ ├── MemoryIssueStage.sv │ │ │ ├── MemoryIssueStageIF.sv │ │ │ ├── MemoryRegisterReadStage.sv │ │ │ ├── MemoryRegisterReadStageIF.sv │ │ │ ├── MemoryRegisterWriteStage.sv │ │ │ ├── MemoryRegisterWriteStageIF.sv │ │ │ ├── MemoryTagAccessStage.sv │ │ │ └── MemoryTagAccessStageIF.sv │ │ ├── PipelineTypes.sv │ │ ├── PreDecodeStage.sv │ │ ├── PreDecodeStageIF.sv │ │ ├── RenameStage.sv │ │ ├── RenameStageIF.sv │ │ ├── ScheduleStage.sv │ │ └── ScheduleStageIF.sv │ ├── Primitives │ │ ├── Divider.sv │ │ ├── FlipFlop.sv │ │ ├── FreeList.sv │ │ ├── LRU_Counter.sv │ │ ├── Multiplier.sv │ │ ├── Picker.sv │ │ ├── Queue.sv │ │ ├── RAM.sv │ │ ├── RAM_Synplify.sv │ │ └── RAM_Vivado.sv │ ├── Privileged │ │ ├── CSR_Unit.sv │ │ ├── CSR_UnitIF.sv │ │ ├── CSR_UnitTypes.sv │ │ └── InterruptController.sv │ ├── Recovery │ │ ├── RecoveryManager.sv │ │ └── RecoveryManagerIF.sv │ ├── RegisterFile │ │ ├── BypassController.sv │ │ ├── BypassNetwork.sv │ │ ├── BypassNetworkIF.sv │ │ ├── BypassTypes.sv │ │ ├── RegisterFile.sv │ │ └── RegisterFileIF.sv │ ├── RenameLogic │ │ ├── ActiveList.sv │ │ ├── ActiveListIF.sv │ │ ├── ActiveListIndexTypes.sv │ │ ├── RMT.sv │ │ ├── RenameLogic.sv │ │ ├── RenameLogicCommitter.sv │ │ ├── RenameLogicIF.sv │ │ ├── RenameLogicTypes.sv │ │ └── RetirementRMT.sv │ ├── ResetController.sv │ ├── Scheduler │ │ ├── DestinationRAM.sv │ │ ├── IssueQueue.sv │ │ ├── MemoryDependencyPredictor.sv │ │ ├── ProducerMatrix.sv │ │ ├── ReadyBitTable.sv │ │ ├── ReplayQueue.sv │ │ ├── Scheduler.sv │ │ ├── SchedulerIF.sv │ │ ├── SchedulerTypes.sv │ │ ├── SelectLogic.sv │ │ ├── SourceCAM.sv │ │ ├── WakeupLogic.sv │ │ ├── WakeupPipelineRegister.sv │ │ └── WakeupSelectIF.sv │ ├── SynthesisMacros.sv │ ├── SysDeps │ │ ├── SynthesisMacros.svh │ │ ├── Verilator │ │ │ ├── Dumper.h │ │ │ ├── TestMain.cpp │ │ │ ├── VerilatorHelper.h │ │ │ └── VerilatorHelper.sv │ │ └── XilinxMacros.vh │ └── Verification │ │ ├── DummyData.hex │ │ ├── Dumper.sv │ │ ├── TestBenchClockGenerator.sv │ │ ├── TestCode │ │ ├── Asm │ │ │ ├── CSR │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── CacheFlush │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── ControlTransfer │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── ControlTransferZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── DividerTest │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ └── serial.ref.txt │ │ │ ├── DynamicRecovery │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── ENV │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── FP │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Fault │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Fence │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Gshare │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ └── code.s │ │ │ ├── IntDivZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── IntMulZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── IntRegImm │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── IntRegImmZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── IntRegReg │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── IntRegRegZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── LoadAndStore │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── LoadAndStoreZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── code.s.b2 │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Makefile │ │ │ ├── MemoryAccessZynq │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── code.s.b2 │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── MemoryDependencyPrediction │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ └── reg.ref.hex │ │ │ ├── MisalignedMemAccess │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── ReplayQueueTest │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── code.s.b2 │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Timer │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── UncachableLoadAndStore │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── ZeroRegister │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ └── rsd-asm-macros.h │ │ ├── C │ │ │ ├── BuildC.inc.mk │ │ │ ├── DCache │ │ │ │ ├── Makefile │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.c │ │ │ │ ├── code.hex │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Exception │ │ │ │ ├── Makefile │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.c │ │ │ │ ├── code.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── FP │ │ │ │ ├── Makefile │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.c │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Fibonacci │ │ │ │ ├── Makefile │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.c │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── HelloWorld │ │ │ │ ├── Makefile │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.c │ │ │ │ ├── code.hex │ │ │ │ ├── code.s │ │ │ │ ├── reg.ref.hex │ │ │ │ └── serial.ref.txt │ │ │ ├── Makefile │ │ │ ├── PerfromanceCounter │ │ │ │ ├── Makefile │ │ │ │ ├── cfg.xml │ │ │ │ ├── code.c │ │ │ │ ├── code.hex │ │ │ │ └── reg.ref.hex │ │ │ └── lib.c │ │ ├── Coremark │ │ │ └── Makefile │ │ ├── Dhrystone │ │ │ └── Makefile │ │ ├── Makefile │ │ ├── Makefile.inc │ │ ├── Zephyr │ │ │ └── Makefile │ │ ├── riscv-compliance │ │ │ └── Makefile │ │ ├── rsd-crt.s │ │ ├── rsd-ld.script │ │ └── rsd-loader.c │ │ ├── TestIntALU.sv │ │ ├── TestMain.sv │ │ └── UnitTest │ │ ├── BlockDualPortRAM │ │ ├── Makefile │ │ ├── TestBlockDualPortRAM.sv │ │ └── TestBlockDualPortRAM_Top.sv │ │ ├── BlockMultiPortRAM │ │ ├── Makefile │ │ ├── TestBlockMultiPortRAM.sv │ │ └── TestBlockMultiPortRAM_Top.sv │ │ ├── BlockTrueDualPortRAM │ │ └── TestBlockTrueDualPortRAM_Top.sv │ │ ├── CacheSystem │ │ ├── Makefile │ │ ├── TestCacheSystem.sv │ │ └── TestCacheSystemTop.sv │ │ ├── DCache │ │ ├── Makefile │ │ ├── TestDCache.sv │ │ └── TestDCacheTop.sv │ │ ├── DCacheFiller │ │ ├── Makefile │ │ ├── TestDCacheFiller.sv │ │ └── TestDCacheFillerTop.sv │ │ ├── DRAM_Controller │ │ ├── Makefile │ │ ├── TestDRAM_Controller.sv │ │ └── TestDRAM_ControllerTop.sv │ │ ├── DistributedDualPortRAM │ │ ├── DistributedDualPortRAM.ucf │ │ ├── Makefile │ │ ├── TestDistributedDualPortRAM.sv │ │ └── TestDistributedDualPortRAM_Top.sv │ │ ├── DistributedMultiBankRAM │ │ └── TestDistributedMultiBankRAM_Top.sv │ │ ├── DistributedMultiPortRAM │ │ ├── DistributedMultiPortRAM.ucf │ │ ├── Makefile │ │ ├── TestDistributedMultiPortRAM.sv │ │ └── TestDistributedMultiPortRAM_Top.sv │ │ ├── DistributedSharedMultiPortRAM │ │ └── TestDistributedSharedMultiPortRAM_Top.sv │ │ ├── DistributedSinglePortRAM │ │ └── TestDistributedSinglePortRAM_Top.sv │ │ ├── Divider │ │ ├── Makefile │ │ ├── RefDivider.sv │ │ ├── TestDivider.sv │ │ └── TestDividerTop.sv │ │ ├── ICache │ │ ├── Makefile │ │ ├── TestICache.sv │ │ └── TestICacheTop.sv │ │ ├── ICacheFiller │ │ ├── Makefile │ │ ├── TestICacheFiller.sv │ │ └── TestICacheFillerTop.sv │ │ ├── ICacheSystem │ │ ├── Makefile │ │ ├── TestICacheSystem.sv │ │ └── TestICacheSystemTop.sv │ │ ├── InitializedBlockRAM │ │ └── TestInitializedBlockRAM_Top.sv │ │ ├── LRU_Counter │ │ ├── Makefile │ │ ├── TestLRU_Counter.sv │ │ └── TestLRU_CounterTop.sv │ │ ├── Memory │ │ ├── Makefile │ │ ├── TestMemory.sv │ │ └── TestMemoryTop.sv │ │ ├── MultiWidthFreeList │ │ ├── Makefile │ │ ├── TestMultiWidthFreeList.sv │ │ └── TestMultiWidthFreeListTop.sv │ │ ├── MultiWidthQueuePointer │ │ ├── Makefile │ │ ├── TestMultiWidthQueuePointer.sv │ │ └── TestMultiWidthQueuePointerTop.sv │ │ ├── RegisterFile │ │ ├── Makefile │ │ ├── TestRegisterFile.sv │ │ └── TestRegisterFileTop.sv │ │ ├── RegisterMultiPortRAM │ │ └── TestRegisterMultiPortRAM_Top.sv │ │ └── SourceCAM │ │ ├── Makefile │ │ ├── TestSourceCAM.sv │ │ └── TestSourceCAM_Top.sv └── Tools │ ├── KanataConverter │ ├── .vscode │ │ ├── launch.json │ │ ├── settings.json │ │ └── tasks.json │ ├── ArchitectureStateConverter.py │ ├── KanataConverter.py │ ├── KanataGenerator.py │ ├── Makefile │ ├── RISCV_Disassembler.py │ ├── RSD_Event.py │ └── RSD_Parser.py │ ├── QEMU_SimDriver │ ├── GDB_CommandFileGenerator.py │ ├── Makefile │ └── logConverter.py │ ├── SetEnv │ ├── SetEnv.bat │ └── SetEnv.sh │ ├── TestDriver │ ├── .vscode │ │ ├── launch.json │ │ ├── settings.json │ │ └── tasks.json │ ├── BinaryToHex.py │ ├── Makefile │ ├── ObjectFileConverter.py │ ├── RunTest.py │ ├── TestCodeProcessor.py │ ├── TestDriver.pyproj │ └── TestDriver.sln │ ├── UnitTestHelper │ ├── ReplacePath.py │ ├── UnitTestHelper.pyproj │ └── UnitTestHelper.sln │ └── XilinxTools │ ├── IP_Generator.py │ ├── VivadoProjectCreator.py │ ├── ip_template.xml │ ├── project_template_footer.tcl │ └── project_template_header.tcl └── README.md /.gitignore: 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