├── PMSMfoc_DSP2812 ├── build │ ├── Debug.lkf │ ├── SVPMSM.CS_ │ │ ├── FILE.CDX │ │ ├── FILE.DBF │ │ ├── FILE.FPT │ │ ├── SYMBOL.CDX │ │ ├── SYMBOL.DBF │ │ └── SYMBOL.FPT │ ├── SVPMSM.map │ ├── SVPMSM.out │ ├── SVPMSM.paf2 │ ├── SVPMSM.pjt │ ├── SVPMSM.sbl │ ├── SVPMSM.wks │ ├── cc_build_Debug.log │ ├── studysvpwm.wks │ └── vssver2.scc ├── cmd │ ├── DSP281x_Headers_nonBIOS.cmd │ ├── F2812_EzDSP_RAM_lnk.cmd │ └── vssver2.scc ├── doc │ ├── Clarke & Park Transforms on c2000.pdf │ ├── MOTOR CONTROL OVERVIEW.pdf │ ├── TI Digital Motor Control Solutions.pdf │ ├── TMS320x281x DSP EV Guide.pdf │ ├── clarke.pdf │ ├── data_log.pdf │ ├── dmc_1500_tech.pdf │ ├── i_park.pdf │ ├── pmsm3_1_28xx.pdf │ ├── qep_theta_drv.pdf │ ├── ramp_gen.pdf │ ├── speed_frq.pdf │ ├── svgen_dq.pdf │ └── 说明.txt ├── include │ ├── DSP281x_Adc.h │ ├── DSP281x_CpuTimers.h │ ├── DSP281x_DefaultIsr.h │ ├── DSP281x_DevEmu.h │ ├── DSP281x_Device.h │ ├── DSP281x_ECan.h │ ├── DSP281x_Ev.h │ ├── DSP281x_Examples.h │ ├── DSP281x_GlobalPrototypes.h │ ├── DSP281x_Gpio.h │ ├── DSP281x_Mcbsp.h │ ├── DSP281x_PieCtrl.h │ ├── DSP281x_PieVect.h │ ├── DSP281x_SWPrioritizedIsrLevels.h │ ├── DSP281x_Sci.h │ ├── DSP281x_Spi.h │ ├── DSP281x_SysCtrl.h │ ├── DSP281x_XIntrupt.h │ ├── DSP281x_Xintf.h │ ├── IQmathLib.h │ ├── build.h │ ├── clarke.h │ ├── dlog4ch.h │ ├── dmctype.h │ ├── f281xbmsk.h │ ├── f281xileg_vdc.h │ ├── f281xpwm.h │ ├── f281xpwmdac.h │ ├── f281xqep.h │ ├── ipark.h │ ├── parameter.h │ ├── park.h │ ├── pid_reg3.h │ ├── pmsm3_1.h │ ├── rampgen.h │ ├── rmp_cntl.h │ ├── speed_fr.h │ ├── svgen_dq.h │ ├── target.h │ └── vssver2.scc ├── lib │ ├── IQmath.lib │ └── rts2800_ml.lib └── src │ ├── DLOG4CHC.asm │ ├── DSP281x_DefaultIsr.c │ ├── DSP281x_GlobalVariableDefs.c │ ├── DSP281x_PieCtrl.c │ ├── DSP281x_PieVect.c │ ├── DSP281x_SysCtrl.c │ ├── DSP281x_usDelay.asm │ ├── clarke.c │ ├── f281xileg_vdc.c │ ├── f281xpwm.c │ ├── f281xpwmdac.c │ ├── f281xqep.c │ ├── ipark.c │ ├── main.c │ ├── pid_reg3.c │ ├── rampgen.c │ ├── rmp_cntl.c │ ├── speed_fr.c │ ├── svgen_dq.c │ └── vssver2.scc └── README.md /PMSMfoc_DSP2812/build/Debug.lkf: -------------------------------------------------------------------------------- 1 | -z -c -m"./SVPMSM.map" -o"./SVPMSM.out" -stack0x50 -w -x -i"D:/CCStudio_v3.1/C2000/xdais/lib" -i"D:/CCStudio_v3.1/C2000/rtdx/lib" -i"D:/CCStudio_v3.1/c2000/bios/lib" -i"D:/CCStudio_v3.1/C2000/cgtools/lib" 2 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\cmd\DSP281x_Headers_nonBIOS.cmd" 3 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\cmd\F2812_EzDSP_RAM_lnk.cmd" 4 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\clarke.obj" 5 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DLOG4CHC.obj" 6 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DSP281x_DefaultIsr.obj" 7 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DSP281x_GlobalVariableDefs.obj" 8 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DSP281x_PieCtrl.obj" 9 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DSP281x_PieVect.obj" 10 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DSP281x_SysCtrl.obj" 11 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\DSP281x_usDelay.obj" 12 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\f281xileg_vdc.obj" 13 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\f281xpwm.obj" 14 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\f281xpwmdac.obj" 15 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\f281xqep.obj" 16 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\ipark.obj" 17 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\main.obj" 18 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\park.obj" 19 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\pid_reg3.obj" 20 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\rampgen.obj" 21 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\rmp_cntl.obj" 22 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\speed_fr.obj" 23 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\obj\svgen_dq.obj" 24 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\lib\IQmath.lib" 25 | "D:\CCStudio_v3.1\MyProjects\PMSMfoc\lib\rts2800_ml.lib" 26 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.CS_/FILE.CDX: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.CS_/FILE.CDX -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.CS_/FILE.DBF: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.CS_/FILE.DBF -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.CS_/FILE.FPT: -------------------------------------------------------------------------------- 1 | X!9.0..\include\build.h..\src\clarke.c..\include\clarke.h..\include\dlog4ch.h..\include\dmctype.h..\include\DSP281x_Adc.h..\include\DSP281x_CpuTimers.h..\src\DSP281x_DefaultIsr.c..\include\DSP281x_DefaultIsr.h..\include\DSP281x_DevEmu.h..\include\DSP281x_Device.h..\include\DSP281x_ECan.h..\include\DSP281x_Ev.h..\include\DSP281x_Examples.h%..\include\DSP281x_GlobalPrototypes.h#..\src\DSP281x_GlobalVariableDefs.c..\include\DSP281x_Gpio.h..\include\DSP281x_Mcbsp.h..\src\DSP281x_PieCtrl.c..\include\DSP281x_PieCtrl.h..\src\DSP281x_PieVect.c..\include\DSP281x_PieVect.h..\include\DSP281x_Sci.h..\include\DSP281x_Spi.h+..\include\DSP281x_SWPrioritizedIsrLevels.h..\src\DSP281x_SysCtrl.c..\include\DSP281x_SysCtrl.h..\include\DSP281x_Xintf.h..\include\DSP281x_XIntrupt.h..\include\f281xbmsk.h..\src\f281xileg_vdc.c..\include\f281xileg_vdc.h..\src\f281xpwm.c..\include\f281xpwm.h..\src\f281xpwmdac.c..\include\f281xpwmdac.h..\src\f281xqep.c..\include\f281xqep.h..\src\ipark.c..\include\ipark.h..\include\IQmathLib.h ..\src\main.c..\include\parameter.h ..\src\park.c..\include\park.h..\src\pid_reg3.c..\include\pid_reg3.h..\include\pmsm3_1.h..\src\rampgen.c..\include\rampgen.h..\src\rmp_cntl.c..\include\rmp_cntl.h..\src\speed_fr.c..\include\speed_fr.h..\src\svgen_dq.c..\include\svgen_dq.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.CS_/SYMBOL.CDX: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.CS_/SYMBOL.CDX -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.CS_/SYMBOL.DBF: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.CS_/SYMBOL.DBF -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.CS_/SYMBOL.FPT: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.CS_/SYMBOL.FPT -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.out: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.out -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.paf2: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.paf2 -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.pjt: -------------------------------------------------------------------------------- 1 | ; Code Composer Project File, Version 2.0 (do not modify or remove this line) 2 | 3 | [Project Settings] 4 | ProjectDir="D:\CCStudio_v3.1\MyProjects\PMSMfoc\build\" 5 | ProjectType=Executable 6 | CPUFamily=TMS320C28XX 7 | Tool="Compiler" 8 | Tool="CustomBuilder" 9 | Tool="DspBiosBuilder" 10 | Tool="Linker" 11 | Config="Debug" 12 | Config="Release" 13 | 14 | [Source Files] 15 | Source="..\doc\Clarke & Park Transforms on c2000.pdf" 16 | Source="..\doc\clarke.pdf" 17 | Source="..\doc\data_log.pdf" 18 | Source="..\doc\i_park.pdf" 19 | Source="..\doc\pmsm3_1_28xx.pdf" 20 | Source="..\doc\qep_theta_drv.pdf" 21 | Source="..\doc\ramp_gen.pdf" 22 | Source="..\doc\speed_frq.pdf" 23 | Source="..\doc\svgen_dq.pdf" 24 | Source="..\doc\TMS320x281x DSP EV Guide.pdf" 25 | Source="..\lib\IQmath.lib" 26 | Source="..\lib\rts2800_ml.lib" 27 | Source="..\src\clarke.c" 28 | Source="..\src\DLOG4CHC.asm" 29 | Source="..\src\DSP281x_DefaultIsr.c" 30 | Source="..\src\DSP281x_GlobalVariableDefs.c" 31 | Source="..\src\DSP281x_PieCtrl.c" 32 | Source="..\src\DSP281x_PieVect.c" 33 | Source="..\src\DSP281x_SysCtrl.c" 34 | Source="..\src\DSP281x_usDelay.asm" 35 | Source="..\src\f281xileg_vdc.c" 36 | Source="..\src\f281xpwm.c" 37 | Source="..\src\f281xpwmdac.c" 38 | Source="..\src\f281xqep.c" 39 | Source="..\src\ipark.c" 40 | Source="..\src\main.c" 41 | Source="..\src\park.c" 42 | Source="..\src\pid_reg3.c" 43 | Source="..\src\rampgen.c" 44 | Source="..\src\rmp_cntl.c" 45 | Source="..\src\speed_fr.c" 46 | Source="..\src\svgen_dq.c" 47 | Source="..\cmd\DSP281x_Headers_nonBIOS.cmd" 48 | Source="..\cmd\F2812_EzDSP_RAM_lnk.cmd" 49 | 50 | ["Compiler" Settings: "Debug"] 51 | Options=-g -fr"..\obj" -i"..\include" -d"_DEBUG" -d"LARGE_MODEL" -ml -v28 52 | 53 | ["Compiler" Settings: "Release"] 54 | Options=-o3 -fr"$(Proj_dir)\Release" -d"LARGE_MODEL" -ml -v28 55 | 56 | ["Linker" Settings: "Debug"] 57 | Options=-c -m".\SVPMSM.map" -o".\SVPMSM.out" -stack0x50 -w -x 58 | 59 | ["Linker" Settings: "Release"] 60 | Options=-c -m".\Release\SVPMSM.map" -o".\Release\SVPMSM.out" -w -x 61 | 62 | ["..\doc\Clarke & Park Transforms on c2000.pdf" Settings: "Debug"] 63 | ExcludeFromBuild=true 64 | 65 | ["..\doc\Clarke & Park Transforms on c2000.pdf" Settings: "Release"] 66 | ExcludeFromBuild=true 67 | 68 | ["..\doc\clarke.pdf" Settings: "Debug"] 69 | ExcludeFromBuild=true 70 | 71 | ["..\doc\clarke.pdf" Settings: "Release"] 72 | ExcludeFromBuild=true 73 | 74 | ["..\doc\data_log.pdf" Settings: "Debug"] 75 | ExcludeFromBuild=true 76 | 77 | ["..\doc\data_log.pdf" Settings: "Release"] 78 | ExcludeFromBuild=true 79 | 80 | ["..\doc\i_park.pdf" Settings: "Debug"] 81 | ExcludeFromBuild=true 82 | 83 | ["..\doc\i_park.pdf" Settings: "Release"] 84 | ExcludeFromBuild=true 85 | 86 | ["..\doc\pmsm3_1_28xx.pdf" Settings: "Debug"] 87 | ExcludeFromBuild=true 88 | 89 | ["..\doc\pmsm3_1_28xx.pdf" Settings: "Release"] 90 | ExcludeFromBuild=true 91 | 92 | ["..\doc\qep_theta_drv.pdf" Settings: "Debug"] 93 | ExcludeFromBuild=true 94 | 95 | ["..\doc\qep_theta_drv.pdf" Settings: "Release"] 96 | ExcludeFromBuild=true 97 | 98 | ["..\doc\ramp_gen.pdf" Settings: "Debug"] 99 | ExcludeFromBuild=true 100 | 101 | ["..\doc\ramp_gen.pdf" Settings: "Release"] 102 | ExcludeFromBuild=true 103 | 104 | ["..\doc\speed_frq.pdf" Settings: "Debug"] 105 | ExcludeFromBuild=true 106 | 107 | ["..\doc\speed_frq.pdf" Settings: "Release"] 108 | ExcludeFromBuild=true 109 | 110 | ["..\doc\svgen_dq.pdf" Settings: "Debug"] 111 | ExcludeFromBuild=true 112 | 113 | ["..\doc\svgen_dq.pdf" Settings: "Release"] 114 | ExcludeFromBuild=true 115 | 116 | ["..\doc\TMS320x281x DSP EV Guide.pdf" Settings: "Debug"] 117 | ExcludeFromBuild=true 118 | 119 | ["..\doc\TMS320x281x DSP EV Guide.pdf" Settings: "Release"] 120 | ExcludeFromBuild=true 121 | 122 | ["..\cmd\DSP281x_Headers_nonBIOS.cmd" Settings: "Debug"] 123 | LinkOrder=1 124 | 125 | ["..\cmd\DSP281x_Headers_nonBIOS.cmd" Settings: "Release"] 126 | LinkOrder=1 127 | 128 | ["..\cmd\F2812_EzDSP_RAM_lnk.cmd" Settings: "Debug"] 129 | LinkOrder=1 130 | 131 | ["..\cmd\F2812_EzDSP_RAM_lnk.cmd" Settings: "Release"] 132 | LinkOrder=1 133 | 134 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.sbl: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/SVPMSM.sbl -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/SVPMSM.wks: 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/studysvpwm.wks -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/build/vssver2.scc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/build/vssver2.scc -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/cmd/DSP281x_Headers_nonBIOS.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | //########################################################################### 3 | // 4 | // FILE: DSP281x_Headers_nonBIOS.cmd 5 | // 6 | // TITLE: DSP281x Peripheral registers linker command file 7 | // 8 | // DESCRIPTION: 9 | // 10 | // This file is for use in Non-BIOS applications. 11 | // 12 | // Linker command file to place the peripheral structures 13 | // used within the DSP28 headerfiles into the correct memory 14 | // mapped locations. 15 | // 16 | // This version of the file includes the PieVectorTable structure. 17 | // For BIOS applications, please use the DSP281x_Headers_BIOS.cmd file 18 | // which does not include the PieVectorTable structure. 19 | // 20 | //########################################################################### 21 | // 22 | // Ver | dd mmm yyyy | Who | Description of changes 23 | // =====|=============|======|=============================================== 24 | // | 05 Mar 2003 | D.A. | Original based on DSP28 v0.58 25 | // 1.00| 11 Sep 2003 | L.H. | Integrated into DSP28 header files 26 | // | | | Added missing eCAN file sections 27 | // -----|-------------|------|----------------------------------------------- 28 | //########################################################################### 29 | */ 30 | 31 | MEMORY 32 | { 33 | PAGE 0: /* Program Memory */ 34 | 35 | PAGE 1: /* Data Memory */ 36 | 37 | DEV_EMU : origin = 0x000880, length = 0x000180 /* device emulation registers */ 38 | PIE_VECT : origin = 0x000D00, length = 0x000100 /* PIE Vector Table */ 39 | FLASH_REGS : origin = 0x000A80, length = 0x000060 /* FLASH registers */ 40 | CSM : origin = 0x000AE0, length = 0x000010 /* code security module registers */ 41 | XINTF : origin = 0x000B20, length = 0x000020 /* external interface registers */ 42 | CPU_TIMER0 : origin = 0x000C00, length = 0x000008 /* CPU Timer0 registers (CPU Timer1 and Timer2 are reserved for BIOS)*/ 43 | PIE_CTRL : origin = 0x000CE0, length = 0x000020 /* PIE control registers */ 44 | ECANA : origin = 0x006000, length = 0x000040 /* eCAN control and status registers */ 45 | ECANA_LAM : origin = 0x006040, length = 0x000040 /* eCAN local acceptance masks */ 46 | ECANA_MOTS : origin = 0x006080, length = 0x000040 /* eCAN message object time stamps */ 47 | ECANA_MOTO : origin = 0x0060C0, length = 0x000040 /* eCAN object time-out registers */ 48 | ECANA_MBOX : origin = 0x006100, length = 0x000100 /* eCAN mailboxes */ 49 | SYSTEM : origin = 0x007010, length = 0x000020 /* System control registers */ 50 | SPIA : origin = 0x007040, length = 0x000010 /* SPI registers */ 51 | SCIA : origin = 0x007050, length = 0x000010 /* SCI-A registers */ 52 | XINTRUPT : origin = 0x007070, length = 0x000010 /* external interrupt registers */ 53 | GPIOMUX : origin = 0x0070C0, length = 0x000020 /* GPIO mux registers */ 54 | GPIODAT : origin = 0x0070E0, length = 0x000020 /* GPIO data registers */ 55 | ADC : origin = 0x007100, length = 0x000020 /* ADC registers */ 56 | EVA : origin = 0x007400, length = 0x000040 /* Event Manager A registers */ 57 | EVB : origin = 0x007500, length = 0x000040 /* Event Manager B registers */ 58 | SCIB : origin = 0x007750, length = 0x000010 /* SCI-B registers */ 59 | MCBSPA : origin = 0x007800, length = 0x000040 /* McBSP registers */ 60 | CSM_PWL : origin = 0x3F7FF8, length = 0x000008 /* Part of FLASHA. CSM password locations. */ 61 | } 62 | 63 | 64 | SECTIONS 65 | { 66 | PieVectTableFile : > PIE_VECT, PAGE = 1 67 | 68 | /*** Peripheral Frame 0 Register Structures ***/ 69 | DevEmuRegsFile : > DEV_EMU, PAGE = 1 70 | FlashRegsFile : > FLASH_REGS, PAGE = 1 71 | CsmRegsFile : > CSM, PAGE = 1 72 | XintfRegsFile : > XINTF, PAGE = 1 73 | CpuTimer0RegsFile : > CPU_TIMER0, PAGE = 1 74 | PieCtrlRegsFile : > PIE_CTRL, PAGE = 1 75 | 76 | /*** Peripheral Frame 1 Register Structures ***/ 77 | SysCtrlRegsFile : > SYSTEM, PAGE = 1 78 | SpiaRegsFile : > SPIA, PAGE = 1 79 | SciaRegsFile : > SCIA, PAGE = 1 80 | XIntruptRegsFile : > XINTRUPT, PAGE = 1 81 | GpioMuxRegsFile : > GPIOMUX, PAGE = 1 82 | GpioDataRegsFile : > GPIODAT PAGE = 1 83 | AdcRegsFile : > ADC, PAGE = 1 84 | EvaRegsFile : > EVA, PAGE = 1 85 | EvbRegsFile : > EVB, PAGE = 1 86 | ScibRegsFile : > SCIB, PAGE = 1 87 | McbspaRegsFile : > MCBSPA, PAGE = 1 88 | 89 | /*** Peripheral Frame 2 Register Structures ***/ 90 | ECanaRegsFile : > ECANA, PAGE = 1 91 | ECanaLAMRegsFile : > ECANA_LAM PAGE = 1 92 | ECanaMboxesFile : > ECANA_MBOX PAGE = 1 93 | ECanaMOTSRegsFile : > ECANA_MOTS PAGE = 1 94 | ECanaMOTORegsFile : > ECANA_MOTO PAGE = 1 95 | 96 | /*** Code Security Module Register Structures ***/ 97 | CsmPwlFile : > CSM_PWL, PAGE = 1 98 | } 99 | 100 | 101 | /******************* end of file ************************/ -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/cmd/F2812_EzDSP_RAM_lnk.cmd: -------------------------------------------------------------------------------- 1 | /* 2 | //########################################################################### 3 | // 4 | // FILE: F2812_EzDSP_RAM_lnk.cmd 5 | // 6 | // TITLE: Linker Command File For F2812 eZdsp examples that run out of RAM 7 | // This linker file assumes the user is booting up in Jump to H0 mode 8 | // 9 | //########################################################################### 10 | // 11 | // Ver | dd mmm yyyy | Who | Description of changes 12 | // =====|=============|======|=============================================== 13 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 14 | // | | | Added BEGIN section to the start of H0 15 | // | | | Removed .bss, .const and .sysmem 16 | // | | | These are for a small memory model. All examples 17 | // | | | use the large model. 18 | // | | | Added .esysmem section 19 | // | | | Changed ramfuncs section to load and run from RAM 20 | // | | | (previously this was type DSECT) 21 | // | | | Moved peripheral register files to DSP28_Headers_BIOS.cmd 22 | // | | | and DSP28_Headers_nonBIOS.cmd 23 | // | | | Added CSM_RSVD memory section in FLASHA - this region 24 | // | | | should be programmed with all 0x0000 when using the CSM 25 | // -----|-------------|------|----------------------------------------------- 26 | //########################################################################### 27 | */ 28 | 29 | /* ====================================================== 30 | // For Code Composer Studio V2.2 and later 31 | // --------------------------------------- 32 | // In addition to this memory linker command file, 33 | // add the header linker command file directly to the project. 34 | // The header linker command file is required to link the 35 | // peripheral structures to the proper locations within 36 | // the memory map. 37 | // 38 | // The header linker files are found in \DSP281x_Headers\cmd 39 | // 40 | // For BIOS applications add: DSP281x_Headers_nonBIOS.cmd 41 | // For nonBIOS applications add: DSP281x_Headers_nonBIOS.cmd 42 | ========================================================= */ 43 | 44 | /* ====================================================== 45 | // For Code Composer Studio prior to V2.2 46 | // -------------------------------------- 47 | // 1) Use one of the following -l statements to include the 48 | // header linker command file in the project. The header linker 49 | // file is required to link the peripheral structures to the proper 50 | // locations within the memory map */ 51 | 52 | /* Uncomment this line to include file only for non-BIOS applications */ 53 | /* -l DSP281x_Headers_nonBIOS.cmd */ 54 | 55 | /* Uncomment this line to include file only for BIOS applications */ 56 | /* -l DSP281x_Headers_BIOS.cmd */ 57 | 58 | /* 2) In your project add the path to \DSP281x_headers\cmd to the 59 | library search path under project->build options, linker tab, 60 | library search path (-i). 61 | /*========================================================= */ 62 | 63 | 64 | 65 | MEMORY 66 | { 67 | PAGE 0 : 68 | /* For this example, H0 is split between PAGE 0 and PAGE 1 */ 69 | /* BEGIN is used for the "boot to HO" bootloader mode */ 70 | /* RESET is loaded with the reset vector only if */ 71 | /* the boot is from XINTF Zone 7. Otherwise reset vector */ 72 | /* is fetched from boot ROM. See .reset section below */ 73 | 74 | RAMM0 : origin = 0x000000, length = 0x000400 75 | BEGIN : origin = 0x3F8000, length = 0x000002 76 | PRAMH0 : origin = 0x3F8002, length = 0x0011FE 77 | RESET : origin = 0x3FFFC0, length = 0x000002 78 | 79 | BOOTROM : origin = 0x3FF000, length = 0x000FC0 80 | 81 | PAGE 1 : 82 | 83 | /* For this example, H0 is split between PAGE 0 and PAGE 1 */ 84 | 85 | RAMM1 : origin = 0x000400, length = 0x000400 86 | DRAMH0 : origin = 0x3f9200, length = 0x000E00 87 | 88 | L0L1RAM : origin = 0x008000, length = 0x002000 89 | } 90 | 91 | 92 | SECTIONS 93 | { 94 | /* Setup for "boot to H0" mode: 95 | The codestart section (found in DSP28_CodeStartBranch.asm) 96 | re-directs execution to the start of user code. 97 | Place this section at the start of H0 */ 98 | 99 | codestart : > BEGIN, PAGE = 0 100 | ramfuncs : > PRAMH0 PAGE = 0 101 | .text : > PRAMH0, PAGE = 0 102 | .cinit : > PRAMH0, PAGE = 0 103 | .pinit : > PRAMH0, PAGE = 0 104 | .switch : > RAMM0, PAGE = 0 105 | .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ 106 | 107 | .stack : > RAMM1, PAGE = 1 108 | .ebss : > DRAMH0, PAGE = 1 109 | .econst : > DRAMH0, PAGE = 1 110 | .esysmem : > DRAMH0, PAGE = 1 111 | 112 | DLOG : >L0L1RAM, PAGE = 1 113 | IQmathTables : load = BOOTROM, type = NOLOAD, PAGE = 0 114 | IQmath : load = PRAMH0, PAGE = 0 115 | } 116 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/cmd/vssver2.scc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/cmd/vssver2.scc -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/doc/Clarke & Park Transforms on c2000.pdf: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Adc.h 4 | // 5 | // TITLE: DSP281x Device ADC Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Separated the MAX_CONV bit fields into two 13 | // | | | MAX_CONV1 // 3:0 14 | // | | | MAX_CONV2 // 6:4 15 | // | | | Added SEQ_OVRD bit to ADCTRL1 for RevC and after silicon 16 | //########################################################################### 17 | 18 | #ifndef DSP281x_ADC_H 19 | #define DSP281x_ADC_H 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | 26 | //--------------------------------------------------------------------------- 27 | // ADC Individual Register Bit Definitions: 28 | 29 | struct ADCTRL1_BITS { // bits description 30 | Uint16 rsvd1:4; // 3:0 reserved 31 | Uint16 SEQ_CASC:1; // 4 Cascaded sequencer mode 32 | Uint16 SEQ_OVRD:1; // 5 Sequencer override 33 | Uint16 CONT_RUN:1; // 6 Continuous run 34 | Uint16 CPS:1; // 7 ADC core clock pre-scalar 35 | Uint16 ACQ_PS:4; // 11:8 Acquisition window size 36 | Uint16 SUSMOD:2; // 13:12 Emulation suspend mode 37 | Uint16 RESET:1; // 14 ADC reset 38 | Uint16 rsvd2:1; // 15 reserved 39 | }; 40 | 41 | 42 | union ADCTRL1_REG { 43 | Uint16 all; 44 | struct ADCTRL1_BITS bit; 45 | }; 46 | 47 | 48 | struct ADCTRL2_BITS { // bits description 49 | Uint16 EVB_SOC_SEQ2:1; // 0 Event manager B SOC mask for SEQ2 50 | Uint16 rsvd1:1; // 1 reserved 51 | Uint16 INT_MOD_SEQ2:1; // 2 SEQ2 Interrupt mode 52 | Uint16 INT_ENA_SEQ2:1; // 3 SEQ2 Interrupt enable 53 | Uint16 rsvd2:1; // 4 reserved 54 | Uint16 SOC_SEQ2:1; // 5 Start of conversion for SEQ2 55 | Uint16 RST_SEQ2:1; // 6 Reset SEQ2 56 | Uint16 EXT_SOC_SEQ1:1; // 7 External start of conversion for SEQ1 57 | Uint16 EVA_SOC_SEQ1:1; // 8 Event manager A SOC mask for SEQ1 58 | Uint16 rsvd3:1; // 9 reserved 59 | Uint16 INT_MOD_SEQ1:1; // 10 SEQ1 Interrupt mode 60 | Uint16 INT_ENA_SEQ1:1; // 11 SEQ1 Interrupt enable 61 | Uint16 rsvd4:1; // 12 reserved 62 | Uint16 SOC_SEQ1:1; // 13 Start of conversion trigger for SEQ1 63 | Uint16 RST_SEQ1:1; // 14 Restart sequencer 1 64 | Uint16 EVB_SOC_SEQ:1; // 15 EVB SOC enable 65 | }; 66 | 67 | 68 | union ADCTRL2_REG { 69 | Uint16 all; 70 | struct ADCTRL2_BITS bit; 71 | }; 72 | 73 | 74 | struct ADCASEQSR_BITS { // bits description 75 | Uint16 SEQ1_STATE:4; // 3:0 SEQ1 state 76 | Uint16 SEQ2_STATE:3; // 6:4 SEQ2 state 77 | Uint16 rsvd1:1; // 7 reserved 78 | Uint16 SEQ_CNTR:4; // 11:8 Sequencing counter status 79 | Uint16 rsvd2:4; // 15:12 reserved 80 | }; 81 | 82 | union ADCASEQSR_REG { 83 | Uint16 all; 84 | struct ADCASEQSR_BITS bit; 85 | }; 86 | 87 | 88 | struct ADCMAXCONV_BITS { // bits description 89 | Uint16 MAX_CONV1:4; // 3:0 Max number of conversions 90 | Uint16 MAX_CONV2:3; // 6:4 Max number of conversions 91 | Uint16 rsvd1:9; // 15:7 reserved 92 | }; 93 | 94 | union ADCMAXCONV_REG { 95 | Uint16 all; 96 | struct ADCMAXCONV_BITS bit; 97 | }; 98 | 99 | 100 | struct ADCCHSELSEQ1_BITS { // bits description 101 | Uint16 CONV00:4; // 3:0 Conversion selection 00 102 | Uint16 CONV01:4; // 7:4 Conversion selection 01 103 | Uint16 CONV02:4; // 11:8 Conversion selection 02 104 | Uint16 CONV03:4; // 15:12 Conversion selection 03 105 | }; 106 | 107 | union ADCCHSELSEQ1_REG{ 108 | Uint16 all; 109 | struct ADCCHSELSEQ1_BITS bit; 110 | }; 111 | 112 | struct ADCCHSELSEQ2_BITS { // bits description 113 | Uint16 CONV04:4; // 3:0 Conversion selection 04 114 | Uint16 CONV05:4; // 7:4 Conversion selection 05 115 | Uint16 CONV06:4; // 11:8 Conversion selection 06 116 | Uint16 CONV07:4; // 15:12 Conversion selection 07 117 | }; 118 | 119 | union ADCCHSELSEQ2_REG{ 120 | Uint16 all; 121 | struct ADCCHSELSEQ2_BITS bit; 122 | }; 123 | 124 | struct ADCCHSELSEQ3_BITS { // bits description 125 | Uint16 CONV08:4; // 3:0 Conversion selection 08 126 | Uint16 CONV09:4; // 7:4 Conversion selection 09 127 | Uint16 CONV10:4; // 11:8 Conversion selection 10 128 | Uint16 CONV11:4; // 15:12 Conversion selection 11 129 | }; 130 | 131 | union ADCCHSELSEQ3_REG{ 132 | Uint16 all; 133 | struct ADCCHSELSEQ3_BITS bit; 134 | }; 135 | 136 | struct ADCCHSELSEQ4_BITS { // bits description 137 | Uint16 CONV12:4; // 3:0 Conversion selection 12 138 | Uint16 CONV13:4; // 7:4 Conversion selection 13 139 | Uint16 CONV14:4; // 11:8 Conversion selection 14 140 | Uint16 CONV15:4; // 15:12 Conversion selection 15 141 | }; 142 | 143 | union ADCCHSELSEQ4_REG { 144 | Uint16 all; 145 | struct ADCCHSELSEQ4_BITS bit; 146 | }; 147 | 148 | struct ADCTRL3_BITS { // bits description 149 | Uint16 SMODE_SEL:1; // 0 Sampling mode select 150 | Uint16 ADCCLKPS:4; // 4:1 ADC core clock divider 151 | Uint16 ADCPWDN:1; // 5 ADC powerdown 152 | Uint16 ADCBGRFDN:2; // 7:6 ADC bandgap/ref power down 153 | Uint16 rsvd1:8; // 15:8 reserved 154 | }; 155 | 156 | union ADCTRL3_REG { 157 | Uint16 all; 158 | struct ADCTRL3_BITS bit; 159 | }; 160 | 161 | 162 | struct ADCST_BITS { // bits description 163 | Uint16 INT_SEQ1:1; // 0 SEQ1 Interrupt flag 164 | Uint16 INT_SEQ2:1; // 1 SEQ2 Interrupt flag 165 | Uint16 SEQ1_BSY:1; // 2 SEQ1 busy status 166 | Uint16 SEQ2_BSY:1; // 3 SEQ2 busy status 167 | Uint16 INT_SEQ1_CLR:1; // 4 SEQ1 Interrupt clear 168 | Uint16 INT_SEQ2_CLR:1; // 5 SEQ2 Interrupt clear 169 | Uint16 EOS_BUF1:1; // 6 End of sequence buffer1 170 | Uint16 EOS_BUF2:1; // 7 End of sequence buffer2 171 | Uint16 rsvd1:8; // 15:8 reserved 172 | }; 173 | 174 | 175 | union ADCST_REG { 176 | Uint16 all; 177 | struct ADCST_BITS bit; 178 | }; 179 | 180 | 181 | struct ADC_REGS { 182 | union ADCTRL1_REG ADCTRL1; // ADC Control 1 183 | union ADCTRL2_REG ADCTRL2; // ADC Control 2 184 | union ADCMAXCONV_REG ADCMAXCONV; // Max conversions 185 | union ADCCHSELSEQ1_REG ADCCHSELSEQ1; // Channel select sequencing control 1 186 | union ADCCHSELSEQ2_REG ADCCHSELSEQ2; // Channel select sequencing control 2 187 | union ADCCHSELSEQ3_REG ADCCHSELSEQ3; // Channel select sequencing control 3 188 | union ADCCHSELSEQ4_REG ADCCHSELSEQ4; // Channel select sequencing control 4 189 | union ADCASEQSR_REG ADCASEQSR; // Autosequence status register 190 | Uint16 ADCRESULT0; // Conversion Result Buffer 0 191 | Uint16 ADCRESULT1; // Conversion Result Buffer 1 192 | Uint16 ADCRESULT2; // Conversion Result Buffer 2 193 | Uint16 ADCRESULT3; // Conversion Result Buffer 3 194 | Uint16 ADCRESULT4; // Conversion Result Buffer 4 195 | Uint16 ADCRESULT5; // Conversion Result Buffer 5 196 | Uint16 ADCRESULT6; // Conversion Result Buffer 6 197 | Uint16 ADCRESULT7; // Conversion Result Buffer 7 198 | Uint16 ADCRESULT8; // Conversion Result Buffer 8 199 | Uint16 ADCRESULT9; // Conversion Result Buffer 9 200 | Uint16 ADCRESULT10; // Conversion Result Buffer 10 201 | Uint16 ADCRESULT11; // Conversion Result Buffer 11 202 | Uint16 ADCRESULT12; // Conversion Result Buffer 12 203 | Uint16 ADCRESULT13; // Conversion Result Buffer 13 204 | Uint16 ADCRESULT14; // Conversion Result Buffer 14 205 | Uint16 ADCRESULT15; // Conversion Result Buffer 15 206 | union ADCTRL3_REG ADCTRL3; // ADC Control 3 207 | union ADCST_REG ADCST; // ADC Status Register 208 | }; 209 | 210 | 211 | //--------------------------------------------------------------------------- 212 | // ADC External References & Function Declarations: 213 | // 214 | extern volatile struct ADC_REGS AdcRegs; 215 | 216 | 217 | #ifdef __cplusplus 218 | } 219 | #endif /* extern "C" */ 220 | 221 | 222 | #endif // end of DSP281x_ADC_H definition 223 | 224 | //=========================================================================== 225 | // No more. 226 | //=========================================================================== 227 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_CpuTimers.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_CpuTimers.h 4 | // 5 | // TITLE: DSP281x CPU 32-bit Timers Register Definitions. 6 | // 7 | // NOTES: CpuTimer1 and CpuTimer2 are reserved for use with DSP BIOS and 8 | // other realtime operating systems. 9 | // 10 | // Do not use these two timers in your application if you ever plan 11 | // on integrating DSP-BIOS or another realtime OS. 12 | // 13 | // For this reason, the code to manipulate these two timers is 14 | // commented out and not used in these examples. 15 | // 16 | //########################################################################### 17 | // 18 | // Ver | dd mmm yyyy | Who | Description of changes 19 | // =====|=============|======|=============================================== 20 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 21 | // | | | Corrected the definition of the TCR register 22 | //########################################################################### 23 | 24 | #ifndef DSP281x_CPU_TIMERS_H 25 | #define DSP281x_CPU_TIMERS_H 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | //--------------------------------------------------------------------------- 32 | // CPU Timer Register Bit Definitions: 33 | // 34 | // 35 | // TCR: Control register bit definitions: 36 | struct TCR_BITS { // bits description 37 | Uint16 rsvd1:4; // 3:0 reserved 38 | Uint16 TSS:1; // 4 Timer Start/Stop 39 | Uint16 TRB:1; // 5 Timer reload 40 | Uint16 rsvd2:4; // 9:6 reserved 41 | Uint16 SOFT:1; // 10 Emulation modes 42 | Uint16 FREE:1; // 11 43 | Uint16 rsvd3:2; // 12:13 reserved 44 | Uint16 TIE:1; // 14 Output enable 45 | Uint16 TIF:1; // 15 Interrupt flag 46 | }; 47 | 48 | union TCR_REG { 49 | Uint16 all; 50 | struct TCR_BITS bit; 51 | }; 52 | 53 | // TPR: Pre-scale low bit definitions: 54 | struct TPR_BITS { // bits description 55 | Uint16 TDDR:8; // 7:0 Divide-down low 56 | Uint16 PSC:8; // 15:8 Prescale counter low 57 | }; 58 | 59 | union TPR_REG { 60 | Uint16 all; 61 | struct TPR_BITS bit; 62 | }; 63 | 64 | // TPRH: Pre-scale high bit definitions: 65 | struct TPRH_BITS { // bits description 66 | Uint16 TDDRH:8; // 7:0 Divide-down high 67 | Uint16 PSCH:8; // 15:8 Prescale counter high 68 | }; 69 | 70 | union TPRH_REG { 71 | Uint16 all; 72 | struct TPRH_BITS bit; 73 | }; 74 | 75 | // TIM, TIMH: Timer register definitions: 76 | struct TIM_REG { 77 | Uint16 LSW; 78 | Uint16 MSW; 79 | }; 80 | 81 | union TIM_GROUP { 82 | Uint32 all; 83 | struct TIM_REG half; 84 | }; 85 | 86 | // PRD, PRDH: Period register definitions: 87 | struct PRD_REG { 88 | Uint16 LSW; 89 | Uint16 MSW; 90 | }; 91 | 92 | union PRD_GROUP { 93 | Uint32 all; 94 | struct PRD_REG half; 95 | }; 96 | 97 | //--------------------------------------------------------------------------- 98 | // CPU Timer Register File: 99 | // 100 | struct CPUTIMER_REGS { 101 | union TIM_GROUP TIM; // Timer counter register 102 | union PRD_GROUP PRD; // Period register 103 | union TCR_REG TCR; // Timer control register 104 | Uint16 rsvd1; // reserved 105 | union TPR_REG TPR; // Timer pre-scale low 106 | union TPRH_REG TPRH; // Timer pre-scale high 107 | }; 108 | 109 | //--------------------------------------------------------------------------- 110 | // CPU Timer Support Variables: 111 | // 112 | struct CPUTIMER_VARS { 113 | volatile struct CPUTIMER_REGS *RegsAddr; 114 | Uint32 InterruptCount; 115 | float CPUFreqInMHz; 116 | float PeriodInUSec; 117 | }; 118 | 119 | //--------------------------------------------------------------------------- 120 | // Function prototypes and external definitions: 121 | // 122 | void InitCpuTimers(void); 123 | void ConfigCpuTimer(struct CPUTIMER_VARS *Timer, float Freq, float Period); 124 | 125 | extern volatile struct CPUTIMER_REGS CpuTimer0Regs; 126 | extern struct CPUTIMER_VARS CpuTimer0; 127 | 128 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 129 | //extern volatile struct CPUTIMER_REGS CpuTimer1Regs; 130 | //extern volatile struct CPUTIMER_REGS CpuTimer2Regs; 131 | 132 | //extern struct CPUTIMER_VARS CpuTimer1; 133 | //extern struct CPUTIMER_VARS CpuTimer2; 134 | 135 | //--------------------------------------------------------------------------- 136 | // Usefull Timer Operations: 137 | // 138 | // Start Timer: 139 | #define StartCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 0 140 | 141 | // Stop Timer: 142 | #define StopCpuTimer0() CpuTimer0Regs.TCR.bit.TSS = 1 143 | 144 | // Reload Timer With period Value: 145 | #define ReloadCpuTimer0() CpuTimer0Regs.TCR.bit.TRB = 1 146 | 147 | // Read 32-Bit Timer Value: 148 | #define ReadCpuTimer0Counter() CpuTimer0Regs.TIM.all 149 | 150 | // Read 32-Bit Period Value: 151 | #define ReadCpuTimer0Period() CpuTimer0Regs.PRD.all 152 | 153 | // CpuTimer 1 and CpuTimer2 are reserved for DSP BIOS & other RTOS 154 | // Do not use these two timers if you ever plan on integrating 155 | // DSP-BIOS or another realtime OS. 156 | // 157 | // For this reason, the code to manipulate these two timers is 158 | // commented out and not used in these examples. 159 | 160 | // Start Timer: 161 | //#define StartCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 0 162 | //#define StartCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 0 163 | 164 | // Stop Timer: 165 | //#define StopCpuTimer1() CpuTimer1Regs.TCR.bit.TSS = 1 166 | //#define StopCpuTimer2() CpuTimer2Regs.TCR.bit.TSS = 1 167 | 168 | // Reload Timer With period Value: 169 | //#define ReloadCpuTimer1() CpuTimer1Regs.TCR.bit.TRB = 1 170 | //#define ReloadCpuTimer2() CpuTimer2Regs.TCR.bit.TRB = 1 171 | 172 | // Read 32-Bit Timer Value: 173 | //#define ReadCpuTimer1Counter() CpuTimer1Regs.TIM.all 174 | //#define ReadCpuTimer2Counter() CpuTimer2Regs.TIM.all 175 | 176 | // Read 32-Bit Period Value: 177 | //#define ReadCpuTimer1Period() CpuTimer1Regs.PRD.all 178 | //#define ReadCpuTimer2Period() CpuTimer2Regs.PRD.all 179 | 180 | 181 | #ifdef __cplusplus 182 | } 183 | #endif /* extern "C" */ 184 | 185 | #endif // end of DSP281x_CPU_TIMERS_H definition 186 | 187 | 188 | //=========================================================================== 189 | // No more. 190 | //=========================================================================== 191 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_DefaultIsr.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_DefaultIsr.h 4 | // 5 | // TITLE: DSP281x Devices Default Interrupt Service Routines Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Changed USER0-USER11 to USER1-USER12 to match the CPU guide 13 | //########################################################################### 14 | 15 | #ifndef DSP281x_DEFAULT_ISR_H 16 | #define DSP281x_DEFAULT_ISR_H 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | //--------------------------------------------------------------------------- 24 | // Default Interrupt Service Routine Declarations: 25 | // 26 | // The following function prototypes are for the 27 | // default ISR routines used with the default PIE vector table. 28 | // This default vector table is found in the DSP281x_PieVect.h 29 | // file. 30 | // 31 | 32 | // Non-Peripheral Interrupts: 33 | interrupt void INT13_ISR(void); // XINT13 or CPU-Timer 1 34 | interrupt void INT14_ISR(void); // CPU-Timer2 35 | interrupt void DATALOG_ISR(void); // Datalogging interrupt 36 | interrupt void RTOSINT_ISR(void); // RTOS interrupt 37 | interrupt void EMUINT_ISR(void); // Emulation interrupt 38 | interrupt void NMI_ISR(void); // Non-maskable interrupt 39 | interrupt void ILLEGAL_ISR(void); // Illegal operation TRAP 40 | interrupt void USER1_ISR(void); // User Defined trap 1 41 | interrupt void USER2_ISR(void); // User Defined trap 2 42 | interrupt void USER3_ISR(void); // User Defined trap 3 43 | interrupt void USER4_ISR(void); // User Defined trap 4 44 | interrupt void USER5_ISR(void); // User Defined trap 5 45 | interrupt void USER6_ISR(void); // User Defined trap 6 46 | interrupt void USER7_ISR(void); // User Defined trap 7 47 | interrupt void USER8_ISR(void); // User Defined trap 8 48 | interrupt void USER9_ISR(void); // User Defined trap 9 49 | interrupt void USER10_ISR(void); // User Defined trap 10 50 | interrupt void USER11_ISR(void); // User Defined trap 11 51 | interrupt void USER12_ISR(void); // User Defined trap 12 52 | 53 | // Group 1 PIE Interrupt Service Routines: 54 | interrupt void PDPINTA_ISR(void); // EV-A 55 | interrupt void PDPINTB_ISR(void); // EV-B 56 | interrupt void XINT1_ISR(void); 57 | interrupt void XINT2_ISR(void); 58 | interrupt void ADCINT_ISR(void); // ADC 59 | interrupt void TINT0_ISR(void); // Timer 0 60 | interrupt void WAKEINT_ISR(void); // WD 61 | 62 | // Group 2 PIE Interrupt Service Routines: 63 | interrupt void CMP1INT_ISR(void); // EV-A 64 | interrupt void CMP2INT_ISR(void); // EV-A 65 | interrupt void CMP3INT_ISR(void); // EV-A 66 | interrupt void T1PINT_ISR(void); // EV-A 67 | interrupt void T1CINT_ISR(void); // EV-A 68 | interrupt void T1UFINT_ISR(void); // EV-A 69 | interrupt void T1OFINT_ISR(void); // EV-A 70 | 71 | // Group 3 PIE Interrupt Service Routines: 72 | interrupt void T2PINT_ISR(void); // EV-A 73 | interrupt void T2CINT_ISR(void); // EV-A 74 | interrupt void T2UFINT_ISR(void); // EV-A 75 | interrupt void T2OFINT_ISR(void); // EV-A 76 | interrupt void CAPINT1_ISR(void); // EV-A 77 | interrupt void CAPINT2_ISR(void); // EV-A 78 | interrupt void CAPINT3_ISR(void); // EV-A 79 | 80 | // Group 4 PIE Interrupt Service Routines: 81 | interrupt void CMP4INT_ISR(void); // EV-B 82 | interrupt void CMP5INT_ISR(void); // EV-B 83 | interrupt void CMP6INT_ISR(void); // EV-B 84 | interrupt void T3PINT_ISR(void); // EV-B 85 | interrupt void T3CINT_ISR(void); // EV-B 86 | interrupt void T3UFINT_ISR(void); // EV-B 87 | interrupt void T3OFINT_ISR(void); // EV-B 88 | 89 | // Group 5 PIE Interrupt Service Routines: 90 | interrupt void T4PINT_ISR(void); // EV-B 91 | interrupt void T4CINT_ISR(void); // EV-B 92 | interrupt void T4UFINT_ISR(void); // EV-B 93 | interrupt void T4OFINT_ISR(void); // EV-B 94 | interrupt void CAPINT4_ISR(void); // EV-B 95 | interrupt void CAPINT5_ISR(void); // EV-B 96 | interrupt void CAPINT6_ISR(void); // EV-B 97 | 98 | // Group 6 PIE Interrupt Service Routines: 99 | interrupt void SPIRXINTA_ISR(void); // SPI 100 | interrupt void SPITXINTA_ISR(void); // SPI 101 | interrupt void MRINTA_ISR(void); // McBSP 102 | interrupt void MXINTA_ISR(void); // McBSP 103 | 104 | 105 | // Group 9 PIE Interrupt Service Routines: 106 | interrupt void SCIRXINTA_ISR(void); // SCI-A 107 | interrupt void SCITXINTA_ISR(void); // SCI-A 108 | interrupt void SCIRXINTB_ISR(void); // SCI-B 109 | interrupt void SCITXINTB_ISR(void); // SCI-B 110 | interrupt void ECAN0INTA_ISR(void); // eCAN 111 | interrupt void ECAN1INTA_ISR(void); // eCAN 112 | 113 | 114 | // Catch-all for Reserved Locations For testing purposes: 115 | interrupt void PIE_RESERVED(void); // Reserved for test 116 | interrupt void rsvd_ISR(void); // for test 117 | 118 | 119 | #ifdef __cplusplus 120 | } 121 | #endif /* extern "C" */ 122 | 123 | #endif // end of DSP281x_DEFAULT_ISR_H definition 124 | 125 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_DevEmu.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_DevEmu.h 4 | // 5 | // TITLE: DSP281x Device Emulation Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | As of Rev C silicon, DEVICEID is a 16-bit 13 | // | | | register 14 | // | | | Commented out the DFT test registers. These 15 | // | | | are not needed as of Rev C silicon. 16 | //########################################################################### 17 | 18 | #ifndef DSP281x_DEV_EMU_H 19 | #define DSP281x_DEV_EMU_H 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | //--------------------------------------------------------------------------- 26 | // Device Emulation Register Bit Definitions: 27 | // 28 | // Device Configuration Register Bit Definitions 29 | struct DEVICECNF_BITS { // bits description 30 | Uint16 rsvd1:3; // 2:0 reserved 31 | Uint16 VMAPS:1; // 3 VMAP Status 32 | Uint16 rsvd2:1; // 4 reserved 33 | Uint16 XRSn:1; // 5 XRSn Signal Status 34 | Uint16 rsvd3:10; // 15:6 35 | Uint16 rsvd4:3; // 18:6 36 | Uint16 ENPROT:1; // 19 Enable/Disable pipeline protection 37 | Uint16 rsvd5:12; // 31:20 reserved 38 | }; 39 | 40 | union DEVICECNF_REG { 41 | Uint32 all; 42 | struct DEVICECNF_BITS bit; 43 | }; 44 | 45 | 46 | // Device ID Register Bit Definitions 47 | struct DEVICEID_BITS { // bits description 48 | Uint16 REVID:16; // 15:0 Silicon revision 49 | }; 50 | 51 | union DEVICEID_REG { 52 | Uint32 all; 53 | struct DEVICEID_BITS bit; 54 | }; 55 | 56 | struct DEV_EMU_REGS { 57 | union DEVICECNF_REG DEVICECNF; // device configuration 58 | Uint16 rsvd1:1; // reserved 59 | union DEVICEID_REG DEVICEID; // Device ID 60 | Uint16 PROTSTART; // Write-Read protection start 61 | Uint16 PROTRANGE; // Write-Read protection range 62 | Uint16 rsvd2[202]; 63 | // These registers are no longer needed for Rev C and beyond 64 | // Uint16 M0RAMDFT; 65 | // Uint16 M1RAMDFT; 66 | // Uint16 L0RAMDFT; 67 | // Uint16 L1RAMDFT; 68 | // Uint16 H0RAMDFT; 69 | }; 70 | 71 | //--------------------------------------------------------------------------- 72 | // Device Emulation Register References & Function Declarations: 73 | // 74 | extern volatile struct DEV_EMU_REGS DevEmuRegs; 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif /* extern "C" */ 79 | 80 | #endif // end of DSP281x_DEV_EMU_H definition 81 | 82 | //=========================================================================== 83 | // No more. 84 | //=========================================================================== 85 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_Device.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Device.h 4 | // 5 | // TITLE: DSP281x Device Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added symbols created by the linker 13 | // | | | cmd file for relocating code. 14 | // | | | Added float to the datatype typedefs 15 | // | | | Added #if DSP28_DATA_TYPES wrapper around the 16 | // | | | typedefs 17 | // | | | Added DSP28_BIOS and DSP28_NONBIOS switches 18 | // | | | to include or not include the default ISR's 19 | // | | | Moved files and info specific to the DSP28 examples 20 | // | | | to DSP28_common\include\DSP28_Examples.h 21 | // | | | Changed F2812 -> DSP28_F2812 22 | // | | | Changed F2810 -> DSP28_F2810 23 | //########################################################################### 24 | 25 | #ifndef DSP281x_DEVICE_H 26 | #define DSP281x_DEVICE_H 27 | 28 | 29 | #ifdef __cplusplus 30 | extern "C" { 31 | #endif 32 | 33 | 34 | #define TARGET 1 35 | //--------------------------------------------------------------------------- 36 | // User To Select Target Device: 37 | 38 | #define DSP28_F2812 TARGET 39 | #define DSP28_F2810 0 40 | 41 | //--------------------------------------------------------------------------- 42 | // Common CPU Definitions: 43 | // 44 | 45 | extern cregister volatile unsigned int IFR; 46 | extern cregister volatile unsigned int IER; 47 | 48 | #define EINT asm(" clrc INTM") 49 | #define DINT asm(" setc INTM") 50 | #define ERTM asm(" clrc DBGM") 51 | #define DRTM asm(" setc DBGM") 52 | #define EALLOW asm(" EALLOW") 53 | #define EDIS asm(" EDIS") 54 | #define ESTOP0 asm(" ESTOP0") 55 | 56 | #define M_INT1 0x0001 57 | #define M_INT2 0x0002 58 | #define M_INT3 0x0004 59 | #define M_INT4 0x0008 60 | #define M_INT5 0x0010 61 | #define M_INT6 0x0020 62 | #define M_INT7 0x0040 63 | #define M_INT8 0x0080 64 | #define M_INT9 0x0100 65 | #define M_INT10 0x0200 66 | #define M_INT11 0x0400 67 | #define M_INT12 0x0800 68 | #define M_INT13 0x1000 69 | #define M_INT14 0x2000 70 | #define M_DLOG 0x4000 71 | #define M_RTOS 0x8000 72 | 73 | #define BIT0 0x0001 74 | #define BIT1 0x0002 75 | #define BIT2 0x0004 76 | #define BIT3 0x0008 77 | #define BIT4 0x0010 78 | #define BIT5 0x0020 79 | #define BIT6 0x0040 80 | #define BIT7 0x0080 81 | #define BIT8 0x0100 82 | #define BIT9 0x0200 83 | #define BIT10 0x0400 84 | #define BIT11 0x0800 85 | #define BIT12 0x1000 86 | #define BIT13 0x2000 87 | #define BIT14 0x4000 88 | #define BIT15 0x8000 89 | 90 | 91 | 92 | //--------------------------------------------------------------------------- 93 | // For Portability, User Is Recommended To Use Following Data Type Size 94 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 95 | // 96 | 97 | #ifndef DSP28_DATA_TYPES 98 | #define DSP28_DATA_TYPES 99 | typedef int int16; 100 | typedef long int32; 101 | typedef unsigned int Uint16; 102 | typedef unsigned long Uint32; 103 | typedef float float32; 104 | typedef long double float64; 105 | #endif 106 | 107 | 108 | //--------------------------------------------------------------------------- 109 | // Include All Peripheral Header Files: 110 | // 111 | 112 | #include "DSP281x_SysCtrl.h" // System Control/Power Modes 113 | #include "DSP281x_DevEmu.h" // Device Emulation Registers 114 | #include "DSP281x_Xintf.h" // External Interface Registers 115 | #include "DSP281x_CpuTimers.h" // 32-bit CPU Timers 116 | #include "DSP281x_PieCtrl.h" // PIE Control Registers 117 | #include "DSP281x_PieVect.h" // PIE Vector Table 118 | #include "DSP281x_Spi.h" // SPI Registers 119 | #include "DSP281x_Sci.h" // SCI Registers 120 | #include "DSP281x_Mcbsp.h" // McBSP Registers 121 | #include "DSP281x_ECan.h" // Enhanced eCAN Registers 122 | #include "DSP281x_Gpio.h" // General Purpose I/O Registers 123 | #include "DSP281x_Ev.h" // Event Manager Registers 124 | #include "DSP281x_Adc.h" // ADC Registers 125 | #include "DSP281x_XIntrupt.h" // External Interrupts 126 | 127 | #ifdef __cplusplus 128 | } 129 | #endif /* extern "C" */ 130 | 131 | #endif // end of DSP281x_DEVICE_H definition 132 | 133 | 134 | //=========================================================================== 135 | // No more. 136 | //=========================================================================== 137 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_Ev.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Ev.h 4 | // 5 | // TITLE: DSP281x Device Event Manager Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | CAPCON, EXTCON and CAPFIFO register for EVA renamed CAPCONA 13 | // | | | EXTCONA and CAPFIFOA. This is to be consistant 14 | // | | | with other documentation. EVB was already correct. 15 | // | | | Corrected bit definitions for GPTCONA & GPTCONB registers 16 | // | | | T1CON and T2CON were using the same bit definitions. Split 17 | // | | | this so the reserved bits in T1CON would be correct 18 | // | | | T3CON and T4CON were using the same bit definitions. Split 19 | // | | | this so the reserved bits in T3CON would be correct 20 | // | | | Changed QEPIQEL to QEPIQUAL in EXTCONA/EXTCONB registers 21 | // | | | Added bits that are active only when EXTCONA.0 = 1 22 | // | | | to the COMCONA and COMCONB registers. 23 | // | | | Changed CAPQEPN to CAP12EN in the CAPCONA register 24 | // | | | Changed CAPQEPN to CAP45EN in the CAPCONB register 25 | //########################################################################### 26 | 27 | #ifndef DSP281x_EV_H 28 | #define DSP281x_EV_H 29 | 30 | 31 | #ifdef __cplusplus 32 | extern "C" { 33 | #endif 34 | 35 | /* --------------------------------------------------- */ 36 | /* F2810/12 Event Manager (EV) GP Timer Registers */ 37 | /* */ 38 | /* ----------------------------------------------------*/ 39 | 40 | /* Overall Timer Control Register */ 41 | 42 | struct GPTCONA_BITS { 43 | Uint16 T1PIN:2; // 1:0 Polarity of GP timer 1 compare 44 | Uint16 T2PIN:2; // 3:2 Polarity of GP timer 2 compare 45 | Uint16 T1CMPOE:1; // 4 Timer1 compare output 46 | Uint16 T2CMPOE:1; // 5 Timer2 compare output 47 | Uint16 TCMPOE:1; // 6 Compare output enable 48 | Uint16 T1TOADC:2; // 8:7 Start ADC with timer 1 event 49 | Uint16 T2TOADC:2; // 10:9 Start ADC with timer 2 event 50 | Uint16 T1CTRIPE:1; // 11 Enable Timer 1 compare trip 51 | Uint16 T2CTRIPE:1; // 12 Enable Timer 2 compare trip 52 | Uint16 T1STAT:1; // 13 GP Timer 1 status (read only) 53 | Uint16 T2STAT:1; // 14 GP Timer 2 status (read only) 54 | Uint16 rsvd:1; // 15 reserved 55 | }; 56 | 57 | /* Allow access to the bit fields or entire register */ 58 | union GPTCONA_REG { 59 | Uint16 all; 60 | struct GPTCONA_BITS bit; 61 | }; 62 | 63 | struct GPTCONB_BITS { 64 | Uint16 T3PIN:2; // 1:0 Polarity of GP timer 3 compare 65 | Uint16 T4PIN:2; // 3:2 Polarity of GP timer 4 compare 66 | Uint16 T3CMPOE:1; // 4 Timer3 compare output 67 | Uint16 T4CMPOE:1; // 5 Timer4 compare output 68 | Uint16 TCMPOE:1; // 6 Compare output enable 69 | Uint16 T3TOADC:2; // 8:7 Start ADC with timer 3 event 70 | Uint16 T4TOADC:2; // 10:9 Start ADC with timer 4 event 71 | Uint16 T3CTRIPE:1; // 11 Timer 3 trip enable 72 | Uint16 T4CTRIPE:1; // 12 Timer 4 trip enable 73 | Uint16 T3STAT:1; // 13 GP Timer 3 status (read only) 74 | Uint16 T4STAT:1; // 14 GP Timer 4 status (read only) 75 | Uint16 rsvd2:1; // 15 reserved 76 | }; 77 | 78 | /* Allow access to the bit fields or entire register */ 79 | union GPTCONB_REG { 80 | Uint16 all; 81 | struct GPTCONB_BITS bit; 82 | }; 83 | 84 | /* Timer 1 Control Register bit defintions */ 85 | struct T1CON_BITS { 86 | Uint16 rsvd1:1; // 0 reserved 87 | Uint16 TECMPR:1; // 1 Timer compare enable 88 | Uint16 TCLD10:2; // 3:2 Timer copare register reload 89 | Uint16 TCLKS10:2; // 5:4 Clock source select 90 | Uint16 TENABLE:1; // 6 Timer enable 91 | Uint16 rsvd2:1; // 7 reserved 92 | Uint16 TPS:3; // 10:8 Input clock prescaler 93 | Uint16 TMODE:2; // 12:11 Count mode selection 94 | Uint16 rsvd:1; // 13 reserved 95 | Uint16 FREE:1; // 14 Free emulation control 96 | Uint16 SOFT:1; // 15 Soft emulation control 97 | }; 98 | 99 | /* Allow access to the bit fields or entire register */ 100 | union T1CON_REG { 101 | Uint16 all; 102 | struct T1CON_BITS bit; 103 | }; 104 | 105 | 106 | /* Timer 2 Control Register bit defintions */ 107 | struct T2CON_BITS { 108 | Uint16 SET1PR:1; // 0 Period register select 109 | Uint16 TECMPR:1; // 1 Timer compare enable 110 | Uint16 TCLD10:2; // 3:2 Timer copare register reload 111 | Uint16 TCLKS10:2; // 5:4 Clock source select 112 | Uint16 TENABLE:1; // 6 Timer enable 113 | Uint16 T2SWT1:1; // 7 Start GP timer 2 with GP timer 1's enable 114 | Uint16 TPS:3; // 10:8 Input clock prescaler 115 | Uint16 TMODE:2; // 12:11 Count mode selection 116 | Uint16 rsvd:1; // 13 reserved 117 | Uint16 FREE:1; // 14 Free emulation control 118 | Uint16 SOFT:1; // 15 Soft emulation control 119 | }; 120 | 121 | /* Allow access to the bit fields or entire register */ 122 | union T2CON_REG { 123 | Uint16 all; 124 | struct T2CON_BITS bit; 125 | }; 126 | 127 | /* Timer 3 Control Register bit defintions */ 128 | struct T3CON_BITS { 129 | Uint16 rsvd1:1; // 0 reserved 130 | Uint16 TECMPR:1; // 1 Timer compare enable 131 | Uint16 TCLD10:2; // 3:2 Timer copare register reload 132 | Uint16 TCLKS10:2; // 5:4 Clock source select 133 | Uint16 TENABLE:1; // 6 Timer enable 134 | Uint16 rsvd2:1; // 7 reserved 135 | Uint16 TPS:3; // 10:8 Input clock prescaler 136 | Uint16 TMODE:2; // 12:11 Count mode selection 137 | Uint16 rsvd:1; // 13 reserved 138 | Uint16 FREE:1; // 14 Free emulation control 139 | Uint16 SOFT:1; // 15 Soft emulation control 140 | }; 141 | 142 | /* Allow access to the bit fields or entire register */ 143 | union T3CON_REG { 144 | Uint16 all; 145 | struct T3CON_BITS bit; 146 | }; 147 | 148 | /* Timer 4 Control Register bit defintions */ 149 | struct T4CON_BITS { 150 | Uint16 SET3PR:1; // 0 Period register select 151 | Uint16 TECMPR:1; // 1 Timer compare enable 152 | Uint16 TCLD10:2; // 3:2 Timer copare register reload 153 | Uint16 TCLKS10:2; // 5:4 Clock source select 154 | Uint16 TENABLE:1; // 6 Timer enable 155 | Uint16 T4SWT3:1; // 7 Start GP timer 2 with GP timer 1's enable 156 | Uint16 TPS:3; // 10:8 Input clock prescaler 157 | Uint16 TMODE:2; // 12:11 Count mode selection 158 | Uint16 rsvd:1; // 13 reserved 159 | Uint16 FREE:1; // 14 Free emulation control 160 | Uint16 SOFT:1; // 15 Soft emulation control 161 | }; 162 | 163 | /* Allow access to the bit fields or entire register */ 164 | union T4CON_REG { 165 | Uint16 all; 166 | struct T4CON_BITS bit; 167 | }; 168 | 169 | 170 | struct EXTCONA_BITS { 171 | Uint16 INDCOE:1; // 0 Independant compare output 172 | Uint16 QEPIQUAL:1; // 1 QEP/CAP3 Index Qual Mode 173 | Uint16 QEPIE:1; // 2 QEP index enable 174 | Uint16 EVSOCE:1; // 3 EvA start of conversion output enable 175 | Uint16 rsvd:12; // 15:4 reserved 176 | }; 177 | 178 | /* Allow access to the bit fields or entire register */ 179 | union EXTCONA_REG { 180 | Uint16 all; 181 | struct EXTCONA_BITS bit; 182 | }; 183 | 184 | 185 | struct EXTCONB_BITS { 186 | Uint16 INDCOE:1; // 0 Independant compare output 187 | Uint16 QEPIQUAL:1; // 1 QEP/CAP3 Index Qual Mode 188 | Uint16 QEPIE:1; // 2 QEP index enable 189 | Uint16 EVSOCE:1; // 3 EvB start of conversion output enable 190 | Uint16 rsvd:12; // 15:4 reserved 191 | }; 192 | 193 | /* Allow access to the bit fields or entire register */ 194 | union EXTCONB_REG { 195 | Uint16 all; 196 | struct EXTCONA_BITS bit; 197 | }; 198 | 199 | 200 | 201 | /* Compare Control Register */ 202 | struct COMCONA_BITS { 203 | Uint16 C1TRIPE:1; // 0 C1TRIP enable 204 | Uint16 C2TRIPE:1; // 1 C2TRIP enable 205 | Uint16 C3TRIPE:1; // 2 C3TRIP eanble 206 | Uint16 rsvd:2; // 4:3 reserved 207 | Uint16 FCMP1OE:1; // 5 Full compare 1 output enable 208 | Uint16 FCMP2OE:1; // 6 Full compare 2 output enable 209 | Uint16 FCMP3OE:1; // 7 Full compare 3 output enable 210 | Uint16 PDPINTASTATUS:1;// 8 Current status of the PDPINTA pin 211 | Uint16 FCOMPOE:1; // 9 Compare output enable 212 | Uint16 ACTRLD:2; // 11:10 Action control register reload 213 | Uint16 SVENABLE:1; // 12 Space vector PWM Mode enable 214 | Uint16 CLD:2; // 14:13 Compare register reload condition 215 | Uint16 CENABLE:1; // 15 Compare enable 216 | }; 217 | 218 | /* Allow access to the bit fields or entire register */ 219 | union COMCONA_REG { 220 | Uint16 all; 221 | struct COMCONA_BITS bit; 222 | }; 223 | 224 | struct COMCONB_BITS { 225 | Uint16 C4TRIPE:1; // 0 C4TRIP enable 226 | Uint16 C5TRIPE:1; // 1 C5TRIP enable 227 | Uint16 C6TRIPE:1; // 2 C6TRIP eanble 228 | Uint16 rsvd:2; // 4:3 reserved 229 | Uint16 FCMP4OE:1; // 5 Full compare 4 output enable 230 | Uint16 FCMP5OE:1; // 6 Full compare 5 output enable 231 | Uint16 FCMP6OE:1; // 7 Full compare 6 output enable 232 | Uint16 PDPINTBSTATUS:1;// 8 Current status of the PDPINTB pin 233 | Uint16 FCOMPOE:1; // 9 Compare output enable 234 | Uint16 ACTRLD:2; // 11:10 Action control register reload 235 | Uint16 SVENABLE:1; // 12 Space vector PWM Mode enable 236 | Uint16 CLD:2; // 14:13 Compare register reload condition 237 | Uint16 CENABLE:1; // 15 Compare enable 238 | }; 239 | 240 | /* Allow access to the bit fields or entire register */ 241 | union COMCONB_REG { 242 | Uint16 all; 243 | struct COMCONB_BITS bit; 244 | }; 245 | 246 | /* Compare Action Control Register bit definitions */ 247 | 248 | struct ACTRA_BITS { 249 | Uint16 CMP1ACT:2; // 1:0 Action on compare output pin 1 CMP1 250 | Uint16 CMP2ACT:2; // 3:2 Action on compare output pin 2 CMP2 251 | Uint16 CMP3ACT:2; // 5:4 Action on compare output pin 3 CMP3 252 | Uint16 CMP4ACT:2; // 7:6 Action on compare output pin 4 CMP4 253 | Uint16 CMP5ACT:2; // 9:8 Action on compare output pin 5 CMP5 254 | Uint16 CMP6ACT:2; // 11:10 Action on compare output pin 6 CMP6 255 | Uint16 D:3; // 14:12 Basic vector bits 256 | Uint16 SVRDIR:1; // 15 Space vecor PWM rotation dir 257 | }; 258 | 259 | /* Allow access to the bit fields or entire register */ 260 | union ACTRA_REG { 261 | Uint16 all; 262 | struct ACTRA_BITS bit; 263 | }; 264 | 265 | struct ACTRB_BITS { 266 | Uint16 CMP7ACT:2; // 1:0 Action on compare output pin 7 CMP7 267 | Uint16 CMP8ACT:2; // 3:2 Action on compare output pin 8 CMP8 268 | Uint16 CMP9ACT:2; // 5:4 Action on compare output pin 9 CMP9 269 | Uint16 CMP10ACT:2; // 7:6 Action on compare output pin 10 CMP10 270 | Uint16 CMP11ACT:2; // 9:8 Action on compare output pin 11 CMP11 271 | Uint16 CMP12ACT:2; // 11:10 Action on compare output pin 12 CMP12 272 | Uint16 D:3; // 14:12 Basic vector bits 273 | Uint16 SVRDIR:1; // 15 Space vecor PWM rotation dir 274 | }; 275 | 276 | /* Allow access to the bit fields or entire register */ 277 | union ACTRB_REG { 278 | Uint16 all; 279 | struct ACTRB_BITS bit; 280 | }; 281 | 282 | /* Dead-Band Timer Control register bit definitions */ 283 | struct DBTCON_BITS { 284 | Uint16 rsvd1:2; // 1:0 reserved 285 | Uint16 DBTPS:3; // 4:2 Dead-Band timer prescaler 286 | Uint16 EDBT1:1; // 5 Dead-Band timer 1 enable 287 | Uint16 EDBT2:1; // 6 Dead-Band timer 2 enable 288 | Uint16 EDBT3:1; // 7 Dead-Band timer 3 enable 289 | Uint16 DBT:4; // 11:8 Dead-Band timer period 290 | Uint16 rsvd2:4; // 15:12 reserved 291 | }; 292 | 293 | /* Allow access to the bit fields or entire register */ 294 | union DBTCON_REG { 295 | Uint16 all; 296 | struct DBTCON_BITS bit; 297 | }; 298 | 299 | 300 | /* Capture Control register bit definitions */ 301 | struct CAPCONA_BITS { 302 | Uint16 rsvd1:2; // 1:0 reserved 303 | Uint16 CAP3EDGE:2; // 3:2 Edge Detection for Unit 3 304 | Uint16 CAP2EDGE:2; // 5:4 Edge Detection for Unit 2 305 | Uint16 CAP1EDGE:2; // 7:6 Edge Detection for Unit 1 306 | Uint16 CAP3TOADC:1; // 8 Unit 3 starts the ADC 307 | Uint16 CAP12TSEL:1; // 9 GP Timer selection for Units 1 and 2 308 | Uint16 CAP3TSEL:1; // 10 GP Timer selection for Unit 3 309 | Uint16 rsvd2:1; // 11 reserved 310 | Uint16 CAP3EN:1; // 12 Capture Unit 3 enable 311 | Uint16 CAP12EN:2; // 14:13 Capture Unit 1 and 2 enable 312 | Uint16 CAPRES:1; // 15 Capture reset (always reads 0) 313 | }; 314 | 315 | /* Allow access to the bit fields or entire register */ 316 | union CAPCONA_REG { 317 | Uint16 all; 318 | struct CAPCONA_BITS bit; 319 | }; 320 | 321 | 322 | /* Control register bit definitions */ 323 | struct CAPCONB_BITS { 324 | Uint16 rsvd1:2; // 1:0 reserved 325 | Uint16 CAP6EDGE:2; // 3:2 Edge Detection for Unit 6 326 | Uint16 CAP5EDGE:2; // 5:4 Edge Detection for Unit 5 327 | Uint16 CAP4EDGE:2; // 7:6 Edge Detection for Unit 4 328 | Uint16 CAP6TOADC:1; // 8 Unit 6 starts the ADC 329 | Uint16 CAP45TSEL:1; // 9 GP Timer selection for Units 4 and 5 330 | Uint16 CAP6TSEL:1; // 10 GP Timer selection for Unit 6 331 | Uint16 rsvd2:1; // 11 reserved 332 | Uint16 CAP6EN:1; // 12 Capture Unit 6 control 333 | Uint16 CAP45EN:2; // 14:13 Capture Unit 4 and 5 control 334 | Uint16 CAPRES:1; // 15 Capture reset (always reads 0) 335 | }; 336 | 337 | /* Allow access to the bit fields or entire register */ 338 | union CAPCONB_REG { 339 | Uint16 all; 340 | struct CAPCONB_BITS bit; 341 | }; 342 | 343 | /* Capture FIFO Status Register bit definitions */ 344 | struct CAPFIFOA_BITS { 345 | Uint16 rsvd1:8; // 7:0 reserved 346 | Uint16 CAP1FIFO:2; // 9:8 CAP1 FIFO status 347 | Uint16 CAP2FIFO:2; // 11:10 CAP2 FIFO status 348 | Uint16 CAP3FIFO:2; // 13:12 CAP2 FIFO status 349 | Uint16 rsvd2:2; // 15:14 reserved 350 | }; 351 | 352 | /* Allow access to the bit fields or entire register */ 353 | union CAPFIFOA_REG { 354 | Uint16 all; 355 | struct CAPFIFOA_BITS bit; 356 | }; 357 | 358 | /* Capture FIFO Status Register bit definitions */ 359 | struct CAPFIFOB_BITS { 360 | Uint16 rsvd1:8; // 7:0 reserved 361 | Uint16 CAP4FIFO:2; // 9:8 CAP4 FIFO status 362 | Uint16 CAP5FIFO:2; // 11:10 CAP5 FIFO status 363 | Uint16 CAP6FIFO:2; // 13:12 CAP6 FIFO status 364 | Uint16 rsvd2:2; // 15:14 reserved 365 | }; 366 | 367 | /* Allow access to the bit fields or entire register */ 368 | union CAPFIFOB_REG { 369 | Uint16 all; 370 | struct CAPFIFOB_BITS bit; 371 | }; 372 | 373 | /* Interrupt Mask Register bit definitions */ 374 | struct EVAIMRA_BITS { 375 | Uint16 PDPINTA:1; // 0 Enable PDPINTA 376 | Uint16 CMP1INT:1; // 1 Enable 377 | Uint16 CMP2INT:1; // 2 Enable 378 | Uint16 CMP3INT:1; // 3 Enable 379 | Uint16 rsvd1:3; // 6:4 reserved 380 | Uint16 T1PINT:1; // 7 Enable 381 | Uint16 T1CINT:1; // 8 Enable 382 | Uint16 T1UFINT:1; // 9 Enable 383 | Uint16 T1OFINT:1; // 10 Enable 384 | Uint16 rsvd2:5; // 15:11 reserved 385 | }; 386 | 387 | /* Allow access to the bit fields or entire register */ 388 | union EVAIMRA_REG { 389 | Uint16 all; 390 | struct EVAIMRA_BITS bit; 391 | }; 392 | 393 | /* Interrupt Mask Register bit definitions */ 394 | struct EVBIMRA_BITS { 395 | Uint16 PDPINTB:1; // 0 Enable PDPINTB 396 | Uint16 CMP4INT:1; // 1 Enable 397 | Uint16 CMP5INT:1; // 2 Enable 398 | Uint16 CMP6INT:1; // 3 Enable 399 | Uint16 rsvd1:3; // 6:4 reserved 400 | Uint16 T3PINT:1; // 7 Enable 401 | Uint16 T3CINT:1; // 8 Enable 402 | Uint16 T3UFINT:1; // 9 Enable 403 | Uint16 T3OFINT:1; // 10 Enable 404 | Uint16 rsvd2:5; // 15:11 reserved 405 | }; 406 | 407 | /* Allow access to the bit fields or entire register */ 408 | union EVBIMRA_REG { 409 | Uint16 all; 410 | struct EVBIMRA_BITS bit; 411 | }; 412 | 413 | struct EVAIMRB_BITS { 414 | Uint16 T2PINT:1; // 0 Enable 415 | Uint16 T2CINT:1; // 1 Enable 416 | Uint16 T2UFINT:1; // 2 Enable 417 | Uint16 T2OFINT:1; // 3 Enable 418 | Uint16 rsvd1:12; // 15:4 reserved 419 | }; 420 | 421 | /* Allow access to the bit fields or entire register */ 422 | union EVAIMRB_REG { 423 | Uint16 all; 424 | struct EVAIMRB_BITS bit; 425 | }; 426 | 427 | struct EVBIMRB_BITS { 428 | Uint16 T4PINT:1; // 0 Enable 429 | Uint16 T4CINT:1; // 1 Enable 430 | Uint16 T4UFINT:1; // 2 Enable 431 | Uint16 T4OFINT:1; // 3 Enable 432 | Uint16 rsvd1:12; // 15:4 reserved 433 | }; 434 | 435 | /* Allow access to the bit fields or entire register */ 436 | union EVBIMRB_REG { 437 | Uint16 all; 438 | struct EVBIMRB_BITS bit; 439 | }; 440 | 441 | struct EVAIMRC_BITS { 442 | Uint16 CAP1INT:1; // 0 Enable 443 | Uint16 CAP2INT:1; // 1 Enable 444 | Uint16 CAP3INT:1; // 2 Enable 445 | Uint16 rsvd1:13; // 15:3 reserved 446 | }; 447 | 448 | /* Allow access to the bit fields or entire register */ 449 | union EVAIMRC_REG { 450 | Uint16 all; 451 | struct EVAIMRC_BITS bit; 452 | }; 453 | 454 | struct EVBIMRC_BITS { 455 | Uint16 CAP4INT:1; // 0 Enable 456 | Uint16 CAP5INT:1; // 1 Enable 457 | Uint16 CAP6INT:1; // 2 Enable 458 | Uint16 rsvd1:13; // 15:3 reserved 459 | }; 460 | 461 | /* Allow access to the bit fields or entire register */ 462 | union EVBIMRC_REG { 463 | Uint16 all; 464 | struct EVBIMRC_BITS bit; 465 | }; 466 | 467 | /* Interrupt Flag Register bit definitions */ 468 | struct EVAIFRA_BITS { 469 | Uint16 PDPINTA:1; // 0 Flag PDPINTA 470 | Uint16 CMP1INT:1; // 1 Flag 471 | Uint16 CMP2INT:1; // 2 Flag 472 | Uint16 CMP3INT:1; // 3 Flag 473 | Uint16 rsvd1:3; // 6:4 reserved 474 | Uint16 T1PINT:1; // 7 Flag 475 | Uint16 T1CINT:1; // 8 Flag 476 | Uint16 T1UFINT:1; // 9 Flag 477 | Uint16 T1OFINT:1; // 10 Flag 478 | Uint16 rsvd2:5; // 15:11 reserved 479 | }; 480 | 481 | /* Allow access to the bit fields or entire register */ 482 | union EVAIFRA_REG { 483 | Uint16 all; 484 | struct EVAIMRA_BITS bit; 485 | }; 486 | 487 | /* Interrupt Mask Register bit definitions */ 488 | struct EVBIFRA_BITS { 489 | Uint16 PDPINTB:1; // 0 Flag PDPINTB 490 | Uint16 CMP4INT:1; // 1 Flag 491 | Uint16 CMP5INT:1; // 2 Flag 492 | Uint16 CMP6INT:1; // 3 Flag 493 | Uint16 rsvd1:3; // 6:4 reserved 494 | Uint16 T3PINT:1; // 7 Flag 495 | Uint16 T3CINT:1; // 8 Flag 496 | Uint16 T3UFINT:1; // 9 Flag 497 | Uint16 T3OFINT:1; // 10 Flag 498 | Uint16 rsvd2:5; // 15:11 reserved 499 | }; 500 | 501 | /* Allow access to the bit fields or entire register */ 502 | union EVBIFRA_REG { 503 | Uint16 all; 504 | struct EVBIFRA_BITS bit; 505 | }; 506 | 507 | struct EVAIFRB_BITS { 508 | Uint16 T2PINT:1; // 0 Flag 509 | Uint16 T2CINT:1; // 1 Flag 510 | Uint16 T2UFINT:1; // 2 Flag 511 | Uint16 T2OFINT:1; // 3 Flag 512 | Uint16 rsvd1:12; // 15:4 reserved 513 | }; 514 | 515 | /* Allow access to the bit fields or entire register */ 516 | union EVAIFRB_REG { 517 | Uint16 all; 518 | struct EVAIFRB_BITS bit; 519 | }; 520 | 521 | struct EVBIFRB_BITS { 522 | Uint16 T4PINT:1; // 0 Flag 523 | Uint16 T4CINT:1; // 1 Flag 524 | Uint16 T4UFINT:1; // 2 Flag 525 | Uint16 T4OFINT:1; // 3 Flag 526 | Uint16 rsvd1:12; // 15:4 reserved 527 | }; 528 | 529 | /* Allow access to the bit fields or entire register */ 530 | union EVBIFRB_REG { 531 | Uint16 all; 532 | struct EVBIFRB_BITS bit; 533 | }; 534 | 535 | struct EVAIFRC_BITS { 536 | Uint16 CAP1INT:1; // 0 Flag 537 | Uint16 CAP2INT:1; // 1 Flag 538 | Uint16 CAP3INT:1; // 2 Flag 539 | Uint16 rsvd1:13; // 15:3 reserved 540 | }; 541 | 542 | /* Allow access to the bit fields or entire register */ 543 | union EVAIFRC_REG { 544 | Uint16 all; 545 | struct EVAIFRC_BITS bit; 546 | }; 547 | 548 | struct EVBIFRC_BITS { 549 | Uint16 CAP4INT:1; // 0 Flag 550 | Uint16 CAP5INT:1; // 1 Flag 551 | Uint16 CAP6INT:1; // 2 Flag 552 | Uint16 rsvd1:13; // 15:3 reserved 553 | }; 554 | 555 | /* Allow access to the bit fields or entire register */ 556 | union EVBIFRC_REG { 557 | Uint16 all; 558 | struct EVBIFRC_BITS bit; 559 | }; 560 | 561 | /* EVA Register File */ 562 | 563 | struct EVA_REGS { 564 | union GPTCONA_REG GPTCONA; //0x7400 565 | Uint16 T1CNT; //0x7401 566 | Uint16 T1CMPR; //0x7402 567 | Uint16 T1PR; //0x7403 568 | union T1CON_REG T1CON; //0x7404 569 | Uint16 T2CNT; //0x7405 570 | Uint16 T2CMPR; //0x7406 571 | Uint16 T2PR; //0x7407 572 | union T2CON_REG T2CON; //0x7408 573 | union EXTCONA_REG EXTCONA; //0x7409 574 | Uint16 rsvd1[7]; //0x740A-10 575 | union COMCONA_REG COMCONA; //0x7411 576 | Uint16 rsvd2; //0x7412 577 | union ACTRA_REG ACTRA; //0x7413 578 | Uint16 rsvd3; //0x7414 579 | union DBTCON_REG DBTCONA; //0x7415 580 | Uint16 rsvd4; //0x7416 581 | Uint16 CMPR1; //0x7417 582 | Uint16 CMPR2; //0x7418 583 | Uint16 CMPR3; //0x7419 584 | Uint16 rsvd5[6]; //0x741A-F 585 | union CAPCONA_REG CAPCONA; //0x7420 586 | Uint16 rsvd6; //0x7421 587 | union CAPFIFOA_REG CAPFIFOA; //0x7422 588 | Uint16 CAP1FIFO; //0x7423 589 | Uint16 CAP2FIFO; //0x7424 590 | Uint16 CAP3FIFO; //0x7425 591 | Uint16 rsvd7; //0x7426 592 | Uint16 CAP1FBOT; //0x7427 593 | Uint16 CAP2FBOT; //0x7428 594 | Uint16 CAP3FBOT; //0x7429 595 | Uint16 rsvd8[2]; //0x742A-B 596 | union EVAIMRA_REG EVAIMRA; //0x742C 597 | union EVAIMRB_REG EVAIMRB; //0x742D 598 | union EVAIMRC_REG EVAIMRC; //0x742E 599 | union EVAIFRA_REG EVAIFRA; //0x742F 600 | union EVAIFRB_REG EVAIFRB; //0x7430 601 | union EVAIFRC_REG EVAIFRC; //0x7431 602 | }; 603 | 604 | 605 | /* EVB Register File */ 606 | 607 | struct EVB_REGS { 608 | union GPTCONB_REG GPTCONB; //0x7500 609 | Uint16 T3CNT; //0x7501 610 | Uint16 T3CMPR; //0x7502 611 | Uint16 T3PR; //0x7503 612 | union T3CON_REG T3CON; //0x7504 613 | Uint16 T4CNT; //0x7505 614 | Uint16 T4CMPR; //0x7506 615 | Uint16 T4PR; //0x7507 616 | union T4CON_REG T4CON; //0x7508 617 | union EXTCONB_REG EXTCONB; //0x7509 618 | Uint16 rsvd1[7]; //0x750A-10 619 | union COMCONB_REG COMCONB; //0x7511 620 | Uint16 rsvd2; //0x7512 621 | union ACTRB_REG ACTRB; //0x7513 622 | Uint16 rsvd3; //0x7514 623 | union DBTCON_REG DBTCONB; //0x7515 624 | Uint16 rsvd4; //0x7516 625 | Uint16 CMPR4; //0x7517 626 | Uint16 CMPR5; //0x7518 627 | Uint16 CMPR6; //0x7519 628 | Uint16 rsvd5[6]; //0x751A-F 629 | union CAPCONB_REG CAPCONB; //0x7520 630 | Uint16 rsvd6; //0x7521 631 | union CAPFIFOB_REG CAPFIFOB; //0x7522 632 | Uint16 CAP4FIFO; //0x7523 633 | Uint16 CAP5FIFO; //0x7524 634 | Uint16 CAP6FIFO; //0x7525 635 | Uint16 rsvd7; //0x7526 636 | Uint16 CAP4FBOT; //0x7527 637 | Uint16 CAP5FBOT; //0x7528 638 | Uint16 CAP6FBOT; //0x7529 639 | Uint16 rsvd8[2]; //0x752A-B 640 | union EVBIMRA_REG EVBIMRA; //0x752C 641 | union EVBIMRB_REG EVBIMRB; //0x752D 642 | union EVBIMRC_REG EVBIMRC; //0x752E 643 | union EVBIFRA_REG EVBIFRA; //0x752F 644 | union EVBIFRB_REG EVBIFRB; //0x7530 645 | union EVBIFRC_REG EVBIFRC; //0x7531 646 | }; 647 | 648 | 649 | 650 | //--------------------------------------------------------------------------- 651 | // Function prototypes and external definitions: 652 | // 653 | 654 | extern volatile struct EVA_REGS EvaRegs; 655 | extern volatile struct EVB_REGS EvbRegs; 656 | 657 | #ifdef __cplusplus 658 | } 659 | #endif /* extern "C" */ 660 | 661 | #endif // end of DSP281x_EV.H definition 662 | 663 | 664 | //=========================================================================== 665 | // No more. 666 | //=========================================================================== 667 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_Examples.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/DSP281x_Examples.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_GlobalPrototypes.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_GlobalPrototypes.h 4 | // 5 | // TITLE: Global prototypes for DSP28 Examples 6 | //########################################################################### 7 | // 8 | // Ver | dd mmm yyyy | Who | Description of changes 9 | // =====|=============|======|=============================================== 10 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 11 | // | | | Corrected the filename and title in the 12 | // | | | header. 13 | // | | | Removed unused functions. Added InitPeripherals() 14 | //########################################################################### 15 | 16 | #ifndef DSP281x_GLOBALPROTOTYPES_H 17 | #define DSP281x_GLOBALPROTOTYPES_H 18 | 19 | 20 | #ifdef __cplusplus 21 | extern "C" { 22 | #endif 23 | 24 | /*---- shared global function prototypes -----------------------------------*/ 25 | extern void InitAdc(void); 26 | extern void InitPeripherals(void); 27 | extern void InitECan(void); 28 | extern void InitEv(void); 29 | extern void InitGpio(void); 30 | extern void InitMcbsp(void); 31 | extern void InitPieCtrl(void); 32 | extern void InitPieVectTable(void); 33 | extern void EnableInterrupts(void); 34 | extern void InitSci(void); 35 | extern void InitSpi(void); 36 | extern void InitSysCtrl(void); 37 | extern void InitXintf(void); 38 | extern void InitXIntrupt(void); 39 | extern void InitPll(Uint16 val); 40 | extern void InitPeripheralClocks(void); 41 | 42 | 43 | // Watchdog functions 44 | // DSP28_SysCtrl.c 45 | extern void KickDog(void); 46 | extern void DisableDog(void); 47 | 48 | // DSP28_DBGIER.asm 49 | extern void SetDBGIER(Uint16 dbgier); 50 | 51 | 52 | 53 | 54 | // CAUTION 55 | // This function MUST be executed out of RAM. Executing it 56 | // out of OTP/Flash will yield unpredictable results 57 | extern void InitFlash(void); 58 | 59 | 60 | void MemCopy(Uint16 *SourceAddr, Uint16* SourceEndAddr, Uint16* DestAddr); 61 | 62 | 63 | //--------------------------------------------------------------------------- 64 | // External symbols created by the linker cmd file 65 | // DSP28 examples will use these to relocate code from one LOAD location 66 | // in either Flash or XINTF to a different RUN location in internal 67 | // RAM 68 | extern Uint16 RamfuncsLoadStart; 69 | extern Uint16 RamfuncsLoadEnd; 70 | extern Uint16 RamfuncsRunStart; 71 | 72 | #ifdef __cplusplus 73 | } 74 | #endif /* extern "C" */ 75 | 76 | #endif // - end of DSP281x_GLOBALPROTOTYPES_H 77 | 78 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_PieCtrl.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieCtrl.h 4 | // 5 | // TITLE: DSP281x Device PIE Control Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | 15 | #ifndef DSP281x_PIE_CTRL_H 16 | #define DSP281x_PIE_CTRL_H 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | // PIE Control Register Bit Definitions: 24 | // 25 | // PIECTRL: Register bit definitions: 26 | struct PIECTRL_BITS { // bits description 27 | Uint16 ENPIE:1; // 0 Enable PIE block 28 | Uint16 PIEVECT:15; // 15:1 Fetched vector address 29 | }; 30 | 31 | union PIECTRL_REG { 32 | Uint16 all; 33 | struct PIECTRL_BITS bit; 34 | }; 35 | 36 | // PIEIER: Register bit definitions: 37 | struct PIEIER_BITS { // bits description 38 | Uint16 INTx1:1; // 0 INTx.1 39 | Uint16 INTx2:1; // 1 INTx.2 40 | Uint16 INTx3:1; // 2 INTx.3 41 | Uint16 INTx4:1; // 3 INTx.4 42 | Uint16 INTx5:1; // 4 INTx.5 43 | Uint16 INTx6:1; // 5 INTx.6 44 | Uint16 INTx7:1; // 6 INTx.7 45 | Uint16 INTx8:1; // 7 INTx.8 46 | Uint16 rsvd:8; // 15:8 reserved 47 | }; 48 | 49 | union PIEIER_REG { 50 | Uint16 all; 51 | struct PIEIER_BITS bit; 52 | }; 53 | 54 | // PIEIFR: Register bit definitions: 55 | struct PIEIFR_BITS { // bits description 56 | Uint16 INTx1:1; // 0 INTx.1 57 | Uint16 INTx2:1; // 1 INTx.2 58 | Uint16 INTx3:1; // 2 INTx.3 59 | Uint16 INTx4:1; // 3 INTx.4 60 | Uint16 INTx5:1; // 4 INTx.5 61 | Uint16 INTx6:1; // 5 INTx.6 62 | Uint16 INTx7:1; // 6 INTx.7 63 | Uint16 INTx8:1; // 7 INTx.8 64 | Uint16 rsvd:8; // 15:8 reserved 65 | }; 66 | 67 | union PIEIFR_REG { 68 | Uint16 all; 69 | struct PIEIFR_BITS bit; 70 | }; 71 | 72 | // PIEACK: Register bit definitions: 73 | struct PIEACK_BITS { // bits description 74 | Uint16 ACK1:1; // 0 Acknowledge PIE interrupt group 1 75 | Uint16 ACK2:1; // 1 Acknowledge PIE interrupt group 2 76 | Uint16 ACK3:1; // 2 Acknowledge PIE interrupt group 3 77 | Uint16 ACK4:1; // 3 Acknowledge PIE interrupt group 4 78 | Uint16 ACK5:1; // 4 Acknowledge PIE interrupt group 5 79 | Uint16 ACK6:1; // 5 Acknowledge PIE interrupt group 6 80 | Uint16 ACK7:1; // 6 Acknowledge PIE interrupt group 7 81 | Uint16 ACK8:1; // 7 Acknowledge PIE interrupt group 8 82 | Uint16 ACK9:1; // 8 Acknowledge PIE interrupt group 9 83 | Uint16 ACK10:1; // 9 Acknowledge PIE interrupt group 10 84 | Uint16 ACK11:1; // 10 Acknowledge PIE interrupt group 11 85 | Uint16 ACK12:1; // 11 Acknowledge PIE interrupt group 12 86 | Uint16 rsvd:4; // 15:12 reserved 87 | }; 88 | 89 | union PIEACK_REG { 90 | Uint16 all; 91 | struct PIEACK_BITS bit; 92 | }; 93 | 94 | //--------------------------------------------------------------------------- 95 | // PIE Control Register File: 96 | // 97 | struct PIE_CTRL_REGS { 98 | union PIECTRL_REG PIECRTL; // PIE control register 99 | union PIEACK_REG PIEACK; // PIE acknowledge 100 | union PIEIER_REG PIEIER1; // PIE INT1 IER register 101 | union PIEIFR_REG PIEIFR1; // PIE INT1 IFR register 102 | union PIEIER_REG PIEIER2; // PIE INT2 IER register 103 | union PIEIFR_REG PIEIFR2; // PIE INT2 IFR register 104 | union PIEIER_REG PIEIER3; // PIE INT3 IER register 105 | union PIEIFR_REG PIEIFR3; // PIE INT3 IFR register 106 | union PIEIER_REG PIEIER4; // PIE INT4 IER register 107 | union PIEIFR_REG PIEIFR4; // PIE INT4 IFR register 108 | union PIEIER_REG PIEIER5; // PIE INT5 IER register 109 | union PIEIFR_REG PIEIFR5; // PIE INT5 IFR register 110 | union PIEIER_REG PIEIER6; // PIE INT6 IER register 111 | union PIEIFR_REG PIEIFR6; // PIE INT6 IFR register 112 | union PIEIER_REG PIEIER7; // PIE INT7 IER register 113 | union PIEIFR_REG PIEIFR7; // PIE INT7 IFR register 114 | union PIEIER_REG PIEIER8; // PIE INT8 IER register 115 | union PIEIFR_REG PIEIFR8; // PIE INT8 IFR register 116 | union PIEIER_REG PIEIER9; // PIE INT9 IER register 117 | union PIEIFR_REG PIEIFR9; // PIE INT9 IFR register 118 | union PIEIER_REG PIEIER10; // PIE INT10 IER register 119 | union PIEIFR_REG PIEIFR10; // PIE INT10 IFR register 120 | union PIEIER_REG PIEIER11; // PIE INT11 IER register 121 | union PIEIFR_REG PIEIFR11; // PIE INT11 IFR register 122 | union PIEIER_REG PIEIER12; // PIE INT12 IER register 123 | union PIEIFR_REG PIEIFR12; // PIE INT12 IFR register 124 | }; 125 | 126 | #define PIEACK_GROUP1 0x0001; 127 | #define PIEACK_GROUP2 0x0002; 128 | #define PIEACK_GROUP3 0x0004; 129 | #define PIEACK_GROUP4 0x0008; 130 | #define PIEACK_GROUP5 0x0010; 131 | #define PIEACK_GROUP6 0x0020; 132 | #define PIEACK_GROUP7 0x0040; 133 | #define PIEACK_GROUP8 0x0080; 134 | #define PIEACK_GROUP9 0x0100; 135 | #define PIEACK_GROUP10 0x0200; 136 | #define PIEACK_GROUP11 0x0400; 137 | #define PIEACK_GROUP12 0x0800; 138 | 139 | //--------------------------------------------------------------------------- 140 | // PIE Control Registers External References & Function Declarations: 141 | // 142 | extern volatile struct PIE_CTRL_REGS PieCtrlRegs; 143 | 144 | 145 | #ifdef __cplusplus 146 | } 147 | #endif /* extern "C" */ 148 | 149 | #endif // end of DSP281x_PIE_CTRL_H definition 150 | 151 | //=========================================================================== 152 | // No more. 153 | //=========================================================================== 154 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_PieVect.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieVect.h 4 | // 5 | // TITLE: DSP281x Devices PIE Vector Table Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Changed USER0-USER11 to USER1-USER12 to match the CPU guide 13 | //########################################################################### 14 | 15 | #ifndef DSP281x_PIE_VECT_H 16 | #define DSP281x_PIE_VECT_H 17 | 18 | 19 | #ifdef __cplusplus 20 | extern "C" { 21 | #endif 22 | 23 | 24 | //--------------------------------------------------------------------------- 25 | // PIE Interrupt Vector Table Definition: 26 | // 27 | // Create a user type called PINT (pointer to interrupt): 28 | 29 | typedef interrupt void(*PINT)(void); 30 | 31 | // Define Vector Table: 32 | struct PIE_VECT_TABLE { 33 | 34 | // Reset is never fetched from this table. 35 | // It will always be fetched from 0x3FFFC0 in either 36 | // boot ROM or XINTF Zone 7 depending on the state of 37 | // the XMP/MC input signal. On the F2810 it is always 38 | // fetched from boot ROM. 39 | 40 | PINT PIE1_RESERVED; 41 | PINT PIE2_RESERVED; 42 | PINT PIE3_RESERVED; 43 | PINT PIE4_RESERVED; 44 | PINT PIE5_RESERVED; 45 | PINT PIE6_RESERVED; 46 | PINT PIE7_RESERVED; 47 | PINT PIE8_RESERVED; 48 | PINT PIE9_RESERVED; 49 | PINT PIE10_RESERVED; 50 | PINT PIE11_RESERVED; 51 | PINT PIE12_RESERVED; 52 | PINT PIE13_RESERVED; 53 | 54 | // Non-Peripheral Interrupts: 55 | PINT XINT13; // XINT13 56 | PINT TINT2; // CPU-Timer2 57 | PINT DATALOG; // Datalogging interrupt 58 | PINT RTOSINT; // RTOS interrupt 59 | PINT EMUINT; // Emulation interrupt 60 | PINT XNMI; // Non-maskable interrupt 61 | PINT ILLEGAL; // Illegal operation TRAP 62 | PINT USER1; // User Defined trap 1 63 | PINT USER2; // User Defined trap 2 64 | PINT USER3; // User Defined trap 3 65 | PINT USER4; // User Defined trap 4 66 | PINT USER5; // User Defined trap 5 67 | PINT USER6; // User Defined trap 6 68 | PINT USER7; // User Defined trap 7 69 | PINT USER8; // User Defined trap 8 70 | PINT USER9; // User Defined trap 9 71 | PINT USER10; // User Defined trap 10 72 | PINT USER11; // User Defined trap 11 73 | PINT USER12; // User Defined trap 12 74 | 75 | // Group 1 PIE Peripheral Vectors: 76 | PINT PDPINTA; // EV-A 77 | PINT PDPINTB; // EV-B 78 | PINT rsvd1_3; 79 | PINT XINT1; 80 | PINT XINT2; 81 | PINT ADCINT; // ADC 82 | PINT TINT0; // Timer 0 83 | PINT WAKEINT; // WD 84 | 85 | // Group 2 PIE Peripheral Vectors: 86 | PINT CMP1INT; // EV-A 87 | PINT CMP2INT; // EV-A 88 | PINT CMP3INT; // EV-A 89 | PINT T1PINT; // EV-A 90 | PINT T1CINT; // EV-A 91 | PINT T1UFINT; // EV-A 92 | PINT T1OFINT; // EV-A 93 | PINT rsvd2_8; 94 | 95 | // Group 3 PIE Peripheral Vectors: 96 | PINT T2PINT; // EV-A 97 | PINT T2CINT; // EV-A 98 | PINT T2UFINT; // EV-A 99 | PINT T2OFINT; // EV-A 100 | PINT CAPINT1; // EV-A 101 | PINT CAPINT2; // EV-A 102 | PINT CAPINT3; // EV-A 103 | PINT rsvd3_8; 104 | 105 | // Group 4 PIE Peripheral Vectors: 106 | PINT CMP4INT; // EV-B 107 | PINT CMP5INT; // EV-B 108 | PINT CMP6INT; // EV-B 109 | PINT T3PINT; // EV-B 110 | PINT T3CINT; // EV-B 111 | PINT T3UFINT; // EV-B 112 | PINT T3OFINT; // EV-B 113 | PINT rsvd4_8; 114 | 115 | // Group 5 PIE Peripheral Vectors: 116 | PINT T4PINT; // EV-B 117 | PINT T4CINT; // EV-B 118 | PINT T4UFINT; // EV-B 119 | PINT T4OFINT; // EV-B 120 | PINT CAPINT4; // EV-B 121 | PINT CAPINT5; // EV-B 122 | PINT CAPINT6; // EV-B 123 | PINT rsvd5_8; 124 | 125 | // Group 6 PIE Peripheral Vectors: 126 | PINT SPIRXINTA; // SPI-A 127 | PINT SPITXINTA; // SPI-A 128 | PINT rsvd6_3; 129 | PINT rsvd6_4; 130 | PINT MRINTA; // McBSP-A 131 | PINT MXINTA; // McBSP-A 132 | PINT rsvd6_7; 133 | PINT rsvd6_8; 134 | 135 | // Group 7 PIE Peripheral Vectors: 136 | PINT rsvd7_1; 137 | PINT rsvd7_2; 138 | PINT rsvd7_3; 139 | PINT rsvd7_4; 140 | PINT rsvd7_5; 141 | PINT rsvd7_6; 142 | PINT rsvd7_7; 143 | PINT rsvd7_8; 144 | 145 | // Group 8 PIE Peripheral Vectors: 146 | PINT rsvd8_1; 147 | PINT rsvd8_2; 148 | PINT rsvd8_3; 149 | PINT rsvd8_4; 150 | PINT rsvd8_5; 151 | PINT rsvd8_6; 152 | PINT rsvd8_7; 153 | PINT rsvd8_8; 154 | 155 | // Group 9 PIE Peripheral Vectors: 156 | PINT RXAINT; // SCI-A 157 | PINT TXAINT; // SCI-A 158 | PINT RXBINT; // SCI-B 159 | PINT TXBINT; // SCI-B 160 | PINT ECAN0INTA; // eCAN 161 | PINT ECAN1INTA; // eCAN 162 | PINT rsvd9_7; 163 | PINT rsvd9_8; 164 | 165 | // Group 10 PIE Peripheral Vectors: 166 | PINT rsvd10_1; 167 | PINT rsvd10_2; 168 | PINT rsvd10_3; 169 | PINT rsvd10_4; 170 | PINT rsvd10_5; 171 | PINT rsvd10_6; 172 | PINT rsvd10_7; 173 | PINT rsvd10_8; 174 | 175 | // Group 11 PIE Peripheral Vectors: 176 | PINT rsvd11_1; 177 | PINT rsvd11_2; 178 | PINT rsvd11_3; 179 | PINT rsvd11_4; 180 | PINT rsvd11_5; 181 | PINT rsvd11_6; 182 | PINT rsvd11_7; 183 | PINT rsvd11_8; 184 | 185 | // Group 12 PIE Peripheral Vectors: 186 | PINT rsvd12_1; 187 | PINT rsvd12_2; 188 | PINT rsvd12_3; 189 | PINT rsvd12_4; 190 | PINT rsvd12_5; 191 | PINT rsvd12_6; 192 | PINT rsvd12_7; 193 | PINT rsvd12_8; 194 | }; 195 | 196 | //--------------------------------------------------------------------------- 197 | // PIE Interrupt Vector Table External References & Function Declarations: 198 | // 199 | extern struct PIE_VECT_TABLE PieVectTable; 200 | 201 | 202 | #ifdef __cplusplus 203 | } 204 | #endif /* extern "C" */ 205 | 206 | #endif // end of DSP281x_PIE_VECT_H definition 207 | 208 | //=========================================================================== 209 | // No more. 210 | //=========================================================================== 211 | 212 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_Sci.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Sci.h 4 | // 5 | // TITLE: DSP281x Device SCI Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added SCIRST bit field to SCIFFTX register 13 | // | | | Renamed RXERR to RXERROR to match documentation 14 | // | | | Renamed RXOVF_CLR to RXFFOVRCLR to match user documentation 15 | //########################################################################### 16 | 17 | #ifndef DSP281x_SCI_H 18 | #define DSP281x_SCI_H 19 | 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | //--------------------------------------------------------------------------- 26 | // SCI Individual Register Bit Definitions 27 | 28 | //---------------------------------------------------------- 29 | // SCICCR communication control register bit definitions: 30 | // 31 | 32 | struct SCICCR_BITS { // bit description 33 | Uint16 SCICHAR:3; // 2:0 Character length control 34 | Uint16 ADDRIDLE_MODE:1; // 3 ADDR/IDLE Mode control 35 | Uint16 LOOPBKENA:1; // 4 Loop Back enable 36 | Uint16 PARITYENA:1; // 5 Parity enable 37 | Uint16 PARITY:1; // 6 Even or Odd Parity 38 | Uint16 STOPBITS:1; // 7 Number of Stop Bits 39 | Uint16 rsvd1:8; // 15:8 reserved 40 | }; 41 | 42 | 43 | union SCICCR_REG { 44 | Uint16 all; 45 | struct SCICCR_BITS bit; 46 | }; 47 | 48 | //------------------------------------------- 49 | // SCICTL1 control register 1 bit definitions: 50 | // 51 | 52 | struct SCICTL1_BITS { // bit description 53 | Uint16 RXENA:1; // 0 SCI receiver enable 54 | Uint16 TXENA:1; // 1 SCI transmitter enable 55 | Uint16 SLEEP:1; // 2 SCI sleep 56 | Uint16 TXWAKE:1; // 3 Transmitter wakeup method 57 | Uint16 rsvd:1; // 4 reserved 58 | Uint16 SWRESET:1; // 5 Software reset 59 | Uint16 RXERRINTENA:1; // 6 Recieve interrupt enable 60 | Uint16 rsvd1:9; // 15:7 reserved 61 | 62 | }; 63 | 64 | union SCICTL1_REG { 65 | Uint16 all; 66 | struct SCICTL1_BITS bit; 67 | }; 68 | 69 | //--------------------------------------------- 70 | // SCICTL2 control register 2 bit definitions: 71 | // 72 | 73 | struct SCICTL2_BITS { // bit description 74 | Uint16 TXINTENA:1; // 0 Transmit interrupt enable 75 | Uint16 RXBKINTENA:1; // 1 Receiver-buffer break enable 76 | Uint16 rsvd:4; // 5:2 reserved 77 | Uint16 TXEMPTY:1; // 6 Transmitter empty flag 78 | Uint16 TXRDY:1; // 7 Transmitter ready flag 79 | Uint16 rsvd1:8; // 15:8 reserved 80 | 81 | }; 82 | 83 | union SCICTL2_REG { 84 | Uint16 all; 85 | struct SCICTL2_BITS bit; 86 | }; 87 | 88 | //--------------------------------------------------- 89 | // SCIRXST Receiver status register bit definitions: 90 | // 91 | 92 | struct SCIRXST_BITS { // bit description 93 | Uint16 rsvd:1; // 0 reserved 94 | Uint16 RXWAKE:1; // 1 Receiver wakeup detect flag 95 | Uint16 PE:1; // 2 Parity error flag 96 | Uint16 OE:1; // 3 Overrun error flag 97 | Uint16 FE:1; // 4 Framing error flag 98 | Uint16 BRKDT:1; // 5 Break-detect flag 99 | Uint16 RXRDY:1; // 6 Receiver ready flag 100 | Uint16 RXERROR:1; // 7 Receiver error flag 101 | 102 | }; 103 | 104 | union SCIRXST_REG { 105 | Uint16 all; 106 | struct SCIRXST_BITS bit; 107 | }; 108 | 109 | //---------------------------------------------------- 110 | // SCIRXBUF Receiver Data Buffer with FIFO bit definitions: 111 | // 112 | 113 | struct SCIRXBUF_BITS { // bits description 114 | Uint16 RXDT:8; // 7:0 Receive word 115 | Uint16 rsvd:6; // 13:8 reserved 116 | Uint16 SCIFFPE:1; // 14 SCI PE error in FIFO mode 117 | Uint16 SCIFFFE:1; // 15 SCI FE error in FIFO mode 118 | }; 119 | 120 | union SCIRXBUF_REG { 121 | Uint16 all; 122 | struct SCIRXBUF_BITS bit; 123 | }; 124 | 125 | //-------------------------------------------------- 126 | // SCIPRI Priority control register bit definitions: 127 | // 128 | // 129 | 130 | struct SCIPRI_BITS { // bit description 131 | Uint16 rsvd:3; // 2:0 reserved 132 | Uint16 FREE:1; // 3 Free emulation suspend mode 133 | Uint16 SOFT:1; // 4 Soft emulation suspend mode 134 | Uint16 rsvd1:3; // 7:5 reserved 135 | }; 136 | 137 | union SCIPRI_REG { 138 | Uint16 all; 139 | struct SCIPRI_BITS bit; 140 | }; 141 | 142 | //------------------------------------------------- 143 | // SCI FIFO Transmit register bit definitions: 144 | // 145 | // 146 | 147 | struct SCIFFTX_BITS { // bit description 148 | Uint16 TXFFILIL:5; // 4:0 Interrupt level 149 | Uint16 TXFFIENA:1; // 5 Interrupt enable 150 | Uint16 TXINTCLR:1; // 6 Clear INT flag 151 | Uint16 TXFFINT:1; // 7 INT flag 152 | Uint16 TXFFST:5; // 12:8 FIFO status 153 | Uint16 TXFIFOXRESET:1; // 13 FIFO reset 154 | Uint16 SCIFFENA:1; // 14 Enhancement enable 155 | Uint16 SCIRST:1; // 15 SCI reset rx/tx channels 156 | 157 | }; 158 | 159 | union SCIFFTX_REG { 160 | Uint16 all; 161 | struct SCIFFTX_BITS bit; 162 | }; 163 | 164 | //------------------------------------------------ 165 | // SCI FIFO recieve register bit definitions: 166 | // 167 | // 168 | 169 | struct SCIFFRX_BITS { // bits description 170 | Uint16 RXFFIL:5; // 4:0 Interrupt level 171 | Uint16 RXFFIENA:1; // 5 Interrupt enable 172 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 173 | Uint16 RXFFINT:1; // 7 INT flag 174 | Uint16 RXFIFST:5; // 12:8 FIFO status 175 | Uint16 RXFIFORESET:1; // 13 FIFO reset 176 | Uint16 RXFFOVRCLR:1; // 14 Clear overflow 177 | Uint16 RXFFOVF:1; // 15 FIFO overflow 178 | 179 | }; 180 | 181 | union SCIFFRX_REG { 182 | Uint16 all; 183 | struct SCIFFRX_BITS bit; 184 | }; 185 | 186 | // SCI FIFO control register bit definitions: 187 | struct SCIFFCT_BITS { // bits description 188 | Uint16 FFTXDLY:8; // 7:0 FIFO transmit delay 189 | Uint16 rsvd:5; // 12:8 reserved 190 | Uint16 CDC:1; // 13 Auto baud mode enable 191 | Uint16 ABDCLR:1; // 14 Auto baud clear 192 | Uint16 ABD:1; // 15 Auto baud detect 193 | }; 194 | 195 | union SCIFFCT_REG { 196 | Uint16 all; 197 | struct SCIFFCT_BITS bit; 198 | }; 199 | 200 | //--------------------------------------------------------------------------- 201 | // SCI Register File: 202 | // 203 | struct SCI_REGS { 204 | union SCICCR_REG SCICCR; // Communications control register 205 | union SCICTL1_REG SCICTL1; // Control register 1 206 | Uint16 SCIHBAUD; // Baud rate (high) register 207 | Uint16 SCILBAUD; // Baud rate (low) register 208 | union SCICTL2_REG SCICTL2; // Control register 2 209 | union SCIRXST_REG SCIRXST; // Recieve status register 210 | Uint16 SCIRXEMU; // Recieve emulation buffer register 211 | union SCIRXBUF_REG SCIRXBUF; // Recieve data buffer 212 | Uint16 rsvd1; // reserved 213 | Uint16 SCITXBUF; // Transmit data buffer 214 | union SCIFFTX_REG SCIFFTX; // FIFO transmit register 215 | union SCIFFRX_REG SCIFFRX; // FIFO recieve register 216 | union SCIFFCT_REG SCIFFCT; // FIFO control register 217 | Uint16 rsvd2; // reserved 218 | Uint16 rsvd3; // reserved 219 | union SCIPRI_REG SCIPRI; // FIFO Priority control 220 | }; 221 | 222 | //--------------------------------------------------------------------------- 223 | // SCI External References & Function Declarations: 224 | // 225 | extern volatile struct SCI_REGS SciaRegs; 226 | extern volatile struct SCI_REGS ScibRegs; 227 | 228 | #ifdef __cplusplus 229 | } 230 | #endif /* extern "C" */ 231 | 232 | #endif // end of DSP281x_SCI_H definition 233 | 234 | //=========================================================================== 235 | // No more. 236 | //=========================================================================== 237 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_Spi.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Spi.h 4 | // 5 | // TITLE: DSP281x Device SPI Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Corrected SPIFFTX bit definitions. 13 | // | | | RESET renamed SPISWRESET to match documentation 14 | // | | | OVERRUN renamed OVERRUNINTENA to match documentation 15 | //########################################################################### 16 | 17 | #ifndef DSP281x_SPI_H 18 | #define DSP281x_SPI_H 19 | 20 | 21 | #ifdef __cplusplus 22 | extern "C" { 23 | #endif 24 | 25 | 26 | //--------------------------------------------------------------------------- 27 | // SPI Individual Register Bit Definitions: 28 | // 29 | // SPI FIFO Transmit register bit definitions: 30 | struct SPIFFTX_BITS { // bit description 31 | Uint16 TXFFIL:5; // 4:0 Interrupt level 32 | Uint16 TXFFIENA:1; // 5 Interrupt enable 33 | Uint16 TXFFINTCLR:1; // 6 Clear INT flag 34 | Uint16 TXFFINT:1; // 7 INT flag 35 | Uint16 TXFFST:5; // 12:8 FIFO status 36 | Uint16 TXFIFO:1; // 13 FIFO reset 37 | Uint16 SPIFFENA:1; // 14 Enhancement enable 38 | Uint16 SPIRST:1; // 15 Reset SPI 39 | }; 40 | 41 | union SPIFFTX_REG { 42 | Uint16 all; 43 | struct SPIFFTX_BITS bit; 44 | }; 45 | 46 | //-------------------------------------------- 47 | // SPI FIFO recieve register bit definitions: 48 | // 49 | // 50 | struct SPIFFRX_BITS { // bits description 51 | Uint16 RXFFIL:5; // 4:0 Interrupt level 52 | Uint16 RXFFIENA:1; // 5 Interrupt enable 53 | Uint16 RXFFINTCLR:1; // 6 Clear INT flag 54 | Uint16 RXFFINT:1; // 7 INT flag 55 | Uint16 RXFFST:5; // 12:8 FIFO status 56 | Uint16 RXFIFORESET:1; // 13 FIFO reset 57 | Uint16 RXFFOVFCLR:1; // 14 Clear overflow 58 | Uint16 RXFFOVF:1; // 15 FIFO overflow 59 | 60 | }; 61 | 62 | union SPIFFRX_REG { 63 | Uint16 all; 64 | struct SPIFFRX_BITS bit; 65 | }; 66 | 67 | //-------------------------------------------- 68 | // SPI FIFO control register bit definitions: 69 | // 70 | // 71 | struct SPIFFCT_BITS { // bits description 72 | Uint16 TXDLY:8; // 7:0 FIFO transmit delay 73 | Uint16 rsvd:8; // 15:8 reserved 74 | }; 75 | 76 | union SPIFFCT_REG { 77 | Uint16 all; 78 | struct SPIFFCT_BITS bit; 79 | }; 80 | 81 | //--------------------------------------------- 82 | // SPI configuration register bit definitions: 83 | // 84 | // 85 | struct SPICCR_BITS { // bits description 86 | Uint16 SPICHAR:4; // 3:0 Character length control 87 | Uint16 SPILBK:1; // 4 Loop-back enable/disable 88 | Uint16 rsvd1:1; // 5 reserved 89 | Uint16 CLKPOLARITY:1; // 6 Clock polarity 90 | Uint16 SPISWRESET:1; // 7 SPI SW Reset 91 | Uint16 rsvd2:8; // 15:8 reserved 92 | }; 93 | 94 | union SPICCR_REG { 95 | Uint16 all; 96 | struct SPICCR_BITS bit; 97 | }; 98 | 99 | //------------------------------------------------- 100 | // SPI operation control register bit definitions: 101 | // 102 | // 103 | struct SPICTL_BITS { // bits description 104 | Uint16 SPIINTENA:1; // 0 Interrupt enable 105 | Uint16 TALK:1; // 1 Master/Slave transmit enable 106 | Uint16 MASTER_SLAVE:1; // 2 Network control mode 107 | Uint16 CLK_PHASE:1; // 3 Clock phase select 108 | Uint16 OVERRUNINTENA:1; // 4 Overrun interrupt enable 109 | Uint16 rsvd:11; // 15:5 reserved 110 | }; 111 | 112 | union SPICTL_REG { 113 | Uint16 all; 114 | struct SPICTL_BITS bit; 115 | }; 116 | 117 | //-------------------------------------- 118 | // SPI status register bit definitions: 119 | // 120 | // 121 | struct SPISTS_BITS { // bits description 122 | Uint16 rsvd1:5; // 4:0 reserved 123 | Uint16 BUFFULL_FLAG:1; // 5 SPI transmit buffer full flag 124 | Uint16 INT_FLAG:1; // 6 SPI interrupt flag 125 | Uint16 OVERRUN_FLAG:1; // 7 SPI reciever overrun flag 126 | Uint16 rsvd2:8; // 15:8 reserved 127 | }; 128 | 129 | union SPISTS_REG { 130 | Uint16 all; 131 | struct SPISTS_BITS bit; 132 | }; 133 | 134 | //------------------------------------------------ 135 | // SPI priority control register bit definitions: 136 | // 137 | // 138 | struct SPIPRI_BITS { // bits description 139 | Uint16 rsvd1:4; // 3:0 reserved 140 | Uint16 FREE:1; // 4 Free emulation mode control 141 | Uint16 SOFT:1; // 5 Soft emulation mode control 142 | Uint16 PRIORITY:1; // 6 Interrupt priority select 143 | Uint16 rsvd2:9; // 15:7 reserved 144 | }; 145 | 146 | union SPIPRI_REG { 147 | Uint16 all; 148 | struct SPIPRI_BITS bit; 149 | }; 150 | 151 | //--------------------------------------------------------------------------- 152 | // SPI Register File: 153 | // 154 | struct SPI_REGS { 155 | union SPICCR_REG SPICCR; // Configuration register 156 | union SPICTL_REG SPICTL; // Operation control register 157 | union SPISTS_REG SPISTS; // Status register 158 | Uint16 rsvd1; // reserved 159 | Uint16 SPIBRR; // Baud Rate 160 | Uint16 rsvd2; // reserved 161 | Uint16 SPIRXEMU; // Emulation buffer 162 | Uint16 SPIRXBUF; // Serial input buffer 163 | Uint16 SPITXBUF; // Serial output buffer 164 | Uint16 SPIDAT; // Serial data 165 | union SPIFFTX_REG SPIFFTX; // FIFO transmit register 166 | union SPIFFRX_REG SPIFFRX; // FIFO recieve register 167 | union SPIFFCT_REG SPIFFCT; // FIFO control register 168 | Uint16 rsvd3[2]; // reserved 169 | union SPIPRI_REG SPIPRI; // FIFO Priority control 170 | }; 171 | 172 | //--------------------------------------------------------------------------- 173 | // SPI External References & Function Declarations: 174 | // 175 | extern volatile struct SPI_REGS SpiaRegs; 176 | 177 | 178 | #ifdef __cplusplus 179 | } 180 | #endif /* extern "C" */ 181 | 182 | #endif // end of DSP281x_SPI_H definition 183 | 184 | //=========================================================================== 185 | // No more. 186 | //=========================================================================== 187 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_SysCtrl.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_SysCtrl.h 4 | // 5 | // TITLE: DSP281x Device System Control Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added bit definitions for the PLLCR register, 13 | // | | | Low power mode LPMCR0 and LPMCR1 registers 14 | // | | | Corrected OTPWAIT bit field name in FOTPWAIT 15 | // | | | Changed SCIENCLKA to SCIAENCLK and SCIENCLKB to 16 | // | | | SCIBENCLK to match documentation 17 | // | | | Removed bit definition for SCSR register. This 18 | // | | | register should only be written to using a 19 | // | | | mask value else a read-modify-write will clear 20 | // | | | the WDOVERRIDE bit. 21 | //########################################################################### 22 | 23 | #ifndef DSP281x_SYS_CTRL_H 24 | #define DSP281x_SYS_CTRL_H 25 | 26 | 27 | #ifdef __cplusplus 28 | extern "C" { 29 | #endif 30 | 31 | 32 | //--------------------------------------------------------------------------- 33 | // System Control Individual Register Bit Definitions: 34 | // 35 | // High speed peripheral clock register bit definitions: 36 | struct HISPCP_BITS { // bits description 37 | Uint16 HSPCLK:3; // 2:0 Rate relative to SYSCLKOUT 38 | Uint16 rsvd1:13; // 15:3 reserved 39 | }; 40 | 41 | union HISPCP_REG { 42 | Uint16 all; 43 | struct HISPCP_BITS bit; 44 | }; 45 | 46 | // Low speed peripheral clock register bit definitions: 47 | struct LOSPCP_BITS { // bits description 48 | Uint16 LSPCLK:3; // 2:0 Rate relative to SYSCLKOUT 49 | Uint16 rsvd1:13; // 15:3 reserved 50 | }; 51 | 52 | union LOSPCP_REG { 53 | Uint16 all; 54 | struct LOSPCP_BITS bit; 55 | }; 56 | 57 | // Peripheral clock control register bit definitions: 58 | struct PCLKCR_BITS { // bits description 59 | Uint16 EVAENCLK:1; // 0 Enable high speed clk to EV-A 60 | Uint16 EVBENCLK:1; // 1 Enable high speed clk to EV-B 61 | Uint16 rsvd1:1; // 2 62 | Uint16 ADCENCLK:1; // 3 Enable high speed clk to ADC 63 | Uint16 rsvd2:4; // 7:4 reserved 64 | Uint16 SPIENCLK:1; // 8 Enable low speed clk to SPI 65 | Uint16 rsvd3:1; // 9 reserved 66 | Uint16 SCIAENCLK:1; // 10 Enable low speed clk to SCI-A 67 | Uint16 SCIBENCLK:1; // 11 Enable low speed clk to SCI-B 68 | Uint16 MCBSPENCLK:1; // 12 Enable low speed clk to McBSP 69 | Uint16 rsvd4:1; // 13 reserved 70 | Uint16 ECANENCLK:1; // 14 Enable system clk to eCAN 71 | }; 72 | 73 | union PCLKCR_REG { 74 | Uint16 all; 75 | struct PCLKCR_BITS bit; 76 | }; 77 | 78 | // PLL control register bit definitions: 79 | struct PLLCR_BITS { // bits description 80 | Uint16 DIV:4; // 3:0 Set clock ratio for the PLL 81 | Uint16 rsvd1:12; // 15:4 reserved 82 | }; 83 | 84 | union PLLCR_REG { 85 | Uint16 all; 86 | struct PLLCR_BITS bit; 87 | }; 88 | 89 | // Low Power Mode 0 control register bit definitions: 90 | struct LPMCR0_BITS { // bits description 91 | Uint16 LPM:2; // 1:0 Set the low power mode 92 | Uint16 QUALSTDBY:6; // 7:2 Qualification 93 | Uint16 rsvd1:8; // 15:8 reserved 94 | }; 95 | 96 | union LPMCR0_REG { 97 | Uint16 all; 98 | struct LPMCR0_BITS bit; 99 | }; 100 | 101 | // Low Power Mode 1 control register bit definitions: 102 | struct LPMCR1_BITS { // bits description 103 | Uint16 XINT1:1; // 0 Enable XINT1 to wake the device from standby 104 | Uint16 XNMI:1; // 1 Enable XMNI to wake the device from standby 105 | Uint16 WDINT:1; // 2 Enable watchdog interrupt to wake the device from standby 106 | Uint16 T1CTRIP:1; // 3 Enable T1CTRIP to wake the device from standby 107 | Uint16 T2CTRIP:1; // 4 Enable T2CTRIP to wake the device from standby 108 | Uint16 T3CTRIP:1; // 5 Enable T3CTRIP to wake the device from standby 109 | Uint16 T4CTRIP:1; // 6 Enable T4CTRIP to wake the device from standby 110 | Uint16 C1TRIP:1; // 7 Enable C1TRIP to wake the device from standby 111 | Uint16 C2TRIP:1; // 8 Enable C2TRIP to wake the device from standby 112 | Uint16 C3TRIP:1; // 9 Enable C3TRIP to wake the device from standby 113 | Uint16 C4TRIP:1; // 10 Enable C4TRIP to wake the device from standby 114 | Uint16 C5TRIP:1; // 11 Enable C5TRIP to wake the device from standby 115 | Uint16 C6TRIP:1; // 12 Enable C6TRIP to wake the device from standby 116 | Uint16 SCIRXA:1; // 13 Enable SCIRXA to wake the device from standby 117 | Uint16 SCIRXB:1; // 14 Enable SCIRXB to wake the device from standby 118 | Uint16 CANRX:1; // 15 Enable CANRX to wake the device from standby 119 | }; 120 | 121 | union LPMCR1_REG { 122 | Uint16 all; 123 | struct LPMCR1_BITS bit; 124 | }; 125 | 126 | //--------------------------------------------------------------------------- 127 | // System Control Register File: 128 | // 129 | struct SYS_CTRL_REGS { 130 | Uint16 rsvd1[10]; // 0-9 131 | union HISPCP_REG HISPCP; // 10: High-speed peripheral clock pre-scaler 132 | union LOSPCP_REG LOSPCP; // 11: Low-speed peripheral clock pre-scaler 133 | union PCLKCR_REG PCLKCR; // 12: Peripheral clock control register 134 | Uint16 rsvd2; // 13: reserved 135 | union LPMCR0_REG LPMCR0; // 14: Low-power mode control register 0 136 | union LPMCR1_REG LPMCR1; // 15: Low-power mode control register 1 137 | Uint16 rsvd3; // 16: reserved 138 | union PLLCR_REG PLLCR; // 17: PLL control register 139 | // No bit definitions are defined for SCSR because 140 | // a read-modify-write instruction can clear the WDOVERRIDE bit 141 | Uint16 SCSR; // 18: System control and status register 142 | Uint16 WDCNTR; // 19: WD counter register 143 | Uint16 rsvd4; // 20 144 | Uint16 WDKEY; // 21: WD reset key register 145 | Uint16 rsvd5[3]; // 22-24 146 | // No bit definitions are defined for WDCR because 147 | // the proper value must be written to the WDCHK field 148 | // whenever writing to this register. 149 | Uint16 WDCR; // 25: WD timer control register 150 | Uint16 rsvd6[6]; // 26-31 151 | }; 152 | 153 | 154 | /* --------------------------------------------------- */ 155 | /* CSM Registers */ 156 | /* */ 157 | /* ----------------------------------------------------*/ 158 | 159 | /* CSM Status & Control register bit definitions */ 160 | struct CSMSCR_BITS { // bit description 161 | Uint16 SECURE:1; // 0 Secure flag 162 | Uint16 rsvd1:14; // 14-1 reserved 163 | Uint16 FORCESEC:1; // 15 Force Secure control bit 164 | 165 | }; 166 | 167 | /* Allow access to the bit fields or entire register */ 168 | union CSMSCR_REG { 169 | Uint16 all; 170 | struct CSMSCR_BITS bit; 171 | }; 172 | 173 | /* CSM Register File */ 174 | struct CSM_REGS { 175 | Uint16 KEY0; // KEY reg bits 15-0 176 | Uint16 KEY1; // KEY reg bits 31-16 177 | Uint16 KEY2; // KEY reg bits 47-32 178 | Uint16 KEY3; // KEY reg bits 63-48 179 | Uint16 KEY4; // KEY reg bits 79-64 180 | Uint16 KEY5; // KEY reg bits 95-80 181 | Uint16 KEY6; // KEY reg bits 111-96 182 | Uint16 KEY7; // KEY reg bits 127-112 183 | Uint16 rsvd1; // reserved 184 | Uint16 rsvd2; // reserved 185 | Uint16 rsvd3; // reserved 186 | Uint16 rsvd4; // reserved 187 | Uint16 rsvd5; // reserved 188 | Uint16 rsvd6; // reserved 189 | Uint16 rsvd7; // reserved 190 | union CSMSCR_REG CSMSCR; // CSM Status & Control register 191 | }; 192 | 193 | /* Password locations */ 194 | struct CSM_PWL { 195 | Uint16 PSWD0; // PSWD bits 15-0 196 | Uint16 PSWD1; // PSWD bits 31-16 197 | Uint16 PSWD2; // PSWD bits 47-32 198 | Uint16 PSWD3; // PSWD bits 63-48 199 | Uint16 PSWD4; // PSWD bits 79-64 200 | Uint16 PSWD5; // PSWD bits 95-80 201 | Uint16 PSWD6; // PSWD bits 111-96 202 | Uint16 PSWD7; // PSWD bits 127-112 203 | }; 204 | 205 | 206 | 207 | /* Flash Registers */ 208 | 209 | #define FLASH_SLEEP 0x0000; 210 | #define FLASH_STANDBY 0x0001; 211 | #define FLASH_ACTIVE 0x0003; 212 | 213 | 214 | /* Flash Option Register bit definitions */ 215 | struct FOPT_BITS { // bit description 216 | Uint16 ENPIPE:1; // 0 Enable Pipeline Mode 217 | Uint16 rsvd:15; // 1-15 reserved 218 | }; 219 | 220 | /* Allow access to the bit fields or entire register */ 221 | union FOPT_REG { 222 | Uint16 all; 223 | struct FOPT_BITS bit; 224 | }; 225 | 226 | /* Flash Power Modes Register bit definitions */ 227 | struct FPWR_BITS { // bit description 228 | Uint16 PWR:2; // 0-1 Power Mode bits 229 | Uint16 rsvd:14; // 2-15 reserved 230 | }; 231 | 232 | /* Allow access to the bit fields or entire register */ 233 | union FPWR_REG { 234 | Uint16 all; 235 | struct FPWR_BITS bit; 236 | }; 237 | 238 | 239 | /* Flash Status Register bit definitions */ 240 | struct FSTATUS_BITS { // bit description 241 | Uint16 PWRS:2; // 0-1 Power Mode Status bits 242 | Uint16 STDBYWAITS:1; // 2 Bank/Pump Sleep to Standby Wait Counter Status bits 243 | Uint16 ACTIVEWAITS:1; // 3 Bank/Pump Standby to Active Wait Counter Status bits 244 | Uint16 rsvd1:4; // 4-7 reserved 245 | Uint16 V3STAT:1; // 8 VDD3V Status Latch bit 246 | Uint16 rsvd2:7; // 9-15 reserved 247 | }; 248 | 249 | /* Allow access to the bit fields or entire register */ 250 | union FSTATUS_REG { 251 | Uint16 all; 252 | struct FSTATUS_BITS bit; 253 | }; 254 | 255 | /* Flash Sleep to Standby Wait Counter Register bit definitions */ 256 | struct FSTDBYWAIT_BITS { // bit description 257 | Uint16 STDBYWAIT:8; // 0-7 Bank/Pump Sleep to Standby Wait Count bits 258 | Uint16 rsvd:8; // 8-15 reserved 259 | }; 260 | 261 | /* Allow access to the bit fields or entire register */ 262 | union FSTDBYWAIT_REG { 263 | Uint16 all; 264 | struct FSTDBYWAIT_BITS bit; 265 | }; 266 | 267 | /* Flash Standby to Active Wait Counter Register bit definitions */ 268 | struct FACTIVEWAIT_BITS { // bit description 269 | Uint16 ACTIVEWAIT:8; // 0-7 Bank/Pump Standby to Active Wait Count bits 270 | Uint16 rsvd:8; // 8-15 reserved 271 | }; 272 | 273 | /* Allow access to the bit fields or entire register */ 274 | union FACTIVEWAIT_REG { 275 | Uint16 all; 276 | struct FACTIVEWAIT_BITS bit; 277 | }; 278 | 279 | /* Bank Read Access Wait State Register bit definitions */ 280 | struct FBANKWAIT_BITS { // bit description 281 | Uint16 RANDWAIT:4; // 0-3 Flash Random Read Wait State bits 282 | Uint16 rsvd1:4; // 4-7 reserved 283 | Uint16 PAGEWAIT:4; // 8-11 Flash Paged Read Wait State bits 284 | Uint16 rsvd2:4; // 12-15 reserved 285 | }; 286 | 287 | /* Allow access to the bit fields or entire register */ 288 | union FBANKWAIT_REG { 289 | Uint16 all; 290 | struct FBANKWAIT_BITS bit; 291 | }; 292 | 293 | /* OTP Read Access Wait State Register bit definitions */ 294 | struct FOTPWAIT_BITS { // bit description 295 | Uint16 OTPWAIT:5; // 0-4 OTP Read Wait State bits 296 | Uint16 rsvd:11; // 5-15 reserved 297 | }; 298 | 299 | /* Allow access to the bit fields or entire register */ 300 | union FOTPWAIT_REG { 301 | Uint16 all; 302 | struct FOTPWAIT_BITS bit; 303 | }; 304 | 305 | 306 | struct FLASH_REGS { 307 | union FOPT_REG FOPT; // Option Register 308 | Uint16 rsvd1; // reserved 309 | union FPWR_REG FPWR; // Power Modes Register 310 | union FSTATUS_REG FSTATUS; // Status Register 311 | union FSTDBYWAIT_REG FSTDBYWAIT; // Pump/Bank Sleep to Standby Wait State Register 312 | union FACTIVEWAIT_REG FACTIVEWAIT; // Pump/Bank Standby to Active Wait State Register 313 | union FBANKWAIT_REG FBANKWAIT; // Bank Read Access Wait State Register 314 | union FOTPWAIT_REG FOTPWAIT; // OTP Read Access Wait State Register 315 | }; 316 | 317 | //--------------------------------------------------------------------------- 318 | // System Control External References & Function Declarations: 319 | // 320 | extern volatile struct SYS_CTRL_REGS SysCtrlRegs; 321 | extern volatile struct CSM_REGS CsmRegs; 322 | extern volatile struct CSM_PWL CsmPwl; 323 | extern volatile struct FLASH_REGS FlashRegs; 324 | 325 | 326 | #ifdef __cplusplus 327 | } 328 | #endif /* extern "C" */ 329 | 330 | #endif // end of DSP281x_SYS_CTRL_H definition 331 | 332 | //=========================================================================== 333 | // No more. 334 | //=========================================================================== 335 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_XIntrupt.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_XIntrupt.h 4 | // 5 | // TITLE: DSP281x Device External Interrupt Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #ifndef DSP281x_XINTRUPT_H 15 | #define DSP281x_XINTRUPT_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | //--------------------------------------------------------------------------- 23 | 24 | struct XINTCR_BITS { 25 | Uint16 ENABLE:1; // 0 enable/disable 26 | Uint16 rsvd1:1; // 1 reserved 27 | Uint16 POLARITY:1; // 2 pos/neg triggered 28 | Uint16 rsvd2:12; // 15:3 reserved 29 | }; 30 | 31 | union XINTCR_REG { 32 | Uint16 all; 33 | struct XINTCR_BITS bit; 34 | }; 35 | 36 | struct XNMICR_BITS { 37 | Uint16 ENABLE:1; // 0 enable/disable 38 | Uint16 SELECT:1; // 1 Timer 1 or XNMI connected to INT13 39 | Uint16 POLARITY:1; // 2 pos/neg triggered 40 | Uint16 rsvd2:12; // 15:3 reserved 41 | }; 42 | 43 | union XNMICR_REG { 44 | Uint16 all; 45 | struct XNMICR_BITS bit; 46 | }; 47 | 48 | 49 | 50 | 51 | //--------------------------------------------------------------------------- 52 | // External Interrupt Register File: 53 | // 54 | struct XINTRUPT_REGS { 55 | union XINTCR_REG XINT1CR; 56 | union XINTCR_REG XINT2CR; 57 | Uint16 rsvd1[5]; 58 | union XNMICR_REG XNMICR; 59 | Uint16 XINT1CTR; 60 | Uint16 XINT2CTR; 61 | Uint16 rsvd[5]; 62 | Uint16 XNMICTR; 63 | }; 64 | 65 | //--------------------------------------------------------------------------- 66 | // External Interrupt References & Function Declarations: 67 | // 68 | extern volatile struct XINTRUPT_REGS XIntruptRegs; 69 | 70 | #ifdef __cplusplus 71 | } 72 | #endif /* extern "C" */ 73 | 74 | #endif // end of DSP281x_XINTF_H definition 75 | 76 | //=========================================================================== 77 | // No more. 78 | //=========================================================================== 79 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/DSP281x_Xintf.h: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_Xintf.h 4 | // 5 | // TITLE: DSP281x Device External Interface Register Definitions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | No change since previous version (v.58 Alpha) 12 | //########################################################################### 13 | 14 | #ifndef DSP281x_XINTF_H 15 | #define DSP281x_XINTF_H 16 | 17 | 18 | #ifdef __cplusplus 19 | extern "C" { 20 | #endif 21 | 22 | 23 | // XINTF timing register bit definitions: 24 | struct XTIMING_BITS { // bits description 25 | Uint16 XWRTRAIL:2; // 1:0 Write access trail timing 26 | Uint16 XWRACTIVE:3; // 4:2 Write access active timing 27 | Uint16 XWRLEAD:2; // 6:5 Write access lead timing 28 | Uint16 XRDTRAIL:2; // 8:7 Read access trail timing 29 | Uint16 XRDACTIVE:3; // 11:9 Read access active timing 30 | Uint16 XRDLEAD:2; // 13:12 Read access lead timing 31 | Uint16 USEREADY:1; // 14 Extend access using HW waitstates 32 | Uint16 READYMODE:1; // 15 Ready mode 33 | Uint16 XSIZE:2; // 17:16 XINTF bus width - must be written as 11b 34 | Uint16 rsvd1:4; // 21:18 reserved 35 | Uint16 X2TIMING:1; // 22 Double lead/active/trail timing 36 | Uint16 rsvd3:9; // 31:23 reserved 37 | }; 38 | 39 | union XTIMING_REG { 40 | Uint32 all; 41 | struct XTIMING_BITS bit; 42 | }; 43 | 44 | // XINTF control register bit definitions: 45 | struct XINTCNF2_BITS { // bits description 46 | Uint16 WRBUFF:2; // 1:0 Write buffer depth 47 | Uint16 CLKMODE:1; // 2 Ratio for XCLKOUT with respect to XTIMCLK 48 | Uint16 CLKOFF:1; // 3 Disable XCLKOUT 49 | Uint16 rsvd1:2; // 5:4 reserved 50 | Uint16 WLEVEL:2; // 7:6 Current level of the write buffer 51 | Uint16 MPNMC:1; // 8 Micro-processor/micro-computer mode 52 | Uint16 HOLD:1; // 9 Hold enable/disable 53 | Uint16 HOLDS:1; // 10 Current state of HOLDn input 54 | Uint16 HOLDAS:1; // 11 Current state of HOLDAn output 55 | Uint16 rsvd2:4; // 15:12 reserved 56 | Uint16 XTIMCLK:3; // 18:16 Ratio for XTIMCLK 57 | Uint16 rsvd3:13; // 31:19 reserved 58 | }; 59 | 60 | union XINTCNF2_REG { 61 | Uint32 all; 62 | struct XINTCNF2_BITS bit; 63 | }; 64 | 65 | // XINTF bank switching register bit definitions: 66 | struct XBANK_BITS { // bits description 67 | Uint16 BANK:2; // 2:0 Zone for which banking is enabled 68 | Uint16 BCYC:3; // 5:3 XTIMCLK cycles to add 69 | Uint16 rsvd:10; // 15:6 reserved 70 | }; 71 | 72 | union XBANK_REG { 73 | Uint16 all; 74 | struct XBANK_BITS bit; 75 | }; 76 | 77 | 78 | //--------------------------------------------------------------------------- 79 | // XINTF Register File: 80 | // 81 | struct XINTF_REGS { 82 | union XTIMING_REG XTIMING0; 83 | union XTIMING_REG XTIMING1; 84 | union XTIMING_REG XTIMING2; 85 | Uint32 rsvd1[3]; 86 | union XTIMING_REG XTIMING6; 87 | union XTIMING_REG XTIMING7; 88 | Uint32 rsvd2[2]; 89 | union XINTCNF2_REG XINTCNF2; 90 | Uint32 rsvd3; 91 | union XBANK_REG XBANK; 92 | Uint16 rsvd4; 93 | Uint16 XREVISION; 94 | Uint16 rsvd5[5]; 95 | }; 96 | 97 | //--------------------------------------------------------------------------- 98 | // XINTF External References & Function Declarations: 99 | // 100 | extern volatile struct XINTF_REGS XintfRegs; 101 | 102 | 103 | #ifdef __cplusplus 104 | } 105 | #endif /* extern "C" */ 106 | 107 | #endif // end of DSP281x_XINTF_H definition 108 | 109 | //=========================================================================== 110 | // No more. 111 | //=========================================================================== 112 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/build.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: BUILD.H 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Incremental Build Level control file. 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | ================================================================================= */ 14 | 15 | #ifndef BUILDLEVEL 16 | 17 | /*------------------------------------------------------------------------------ 18 | Following is the list of the Build Level choices. 19 | ------------------------------------------------------------------------------*/ 20 | #define LEVEL1 1 // SVGEN_DQ and FC_PWM_DRV tests 21 | #define LEVEL2 2 // Currents measurement test 22 | #define LEVEL3 3 // Two current PI regulator tests 23 | #define LEVEL4 4 // QEP test and angle calibration 24 | #define LEVEL5 5 // Speed closed loop using measured speed based QEP 25 | 26 | /*------------------------------------------------------------------------------ 27 | This line sets the BUILDLEVEL to one of the available choices. 28 | ------------------------------------------------------------------------------*/ 29 | #define BUILDLEVEL LEVEL4 30 | 31 | 32 | #ifndef BUILDLEVEL 33 | #error Critical: BUILDLEVEL must be defined !! 34 | #endif // BUILDLEVEL 35 | 36 | #endif // BUILDLEVEL 37 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/clarke.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: CLARKE.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Header file containing constants, data type definitions, and 9 | function prototypes for the CLARKE. 10 | ===================================================================================== 11 | History: 12 | ------------------------------------------------------------------------------------- 13 | 04-15-2005 Version 3.20 14 | ------------------------------------------------------------------------------*/ 15 | #ifndef __CLARKE_H__ 16 | #define __CLARKE_H__ 17 | 18 | typedef struct { _iq As; // Input: phase-a stator variable 19 | _iq Bs; // Input: phase-b stator variable 20 | _iq Alpha; // Output: stationary d-axis stator variable 21 | _iq Beta; // Output: stationary q-axis stator variable 22 | void (*calc)(); // Pointer to calculation function 23 | } CLARKE; 24 | 25 | typedef CLARKE *CLARKE_handle; 26 | /*----------------------------------------------------------------------------- 27 | Default initalizer for the CLARKE object. 28 | -----------------------------------------------------------------------------*/ 29 | #define CLARKE_DEFAULTS { 0, \ 30 | 0, \ 31 | 0, \ 32 | 0, \ 33 | (void (*)(Uint32))clarke_calc } 34 | 35 | /*------------------------------------------------------------------------------ 36 | Prototypes for the functions in CLARKE.C 37 | ------------------------------------------------------------------------------*/ 38 | void clarke_calc(CLARKE_handle); 39 | 40 | #endif // __CLARKE_H__ 41 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/dlog4ch.h: -------------------------------------------------------------------------------- 1 | /* ============================================================================ 2 | File name: DLOG4CH.H 3 | 4 | Originator : Advanced Embeeded Control (AEC) 5 | Texas Instruments Inc. 6 | 7 | Description: 8 | Header file containing constants, data type definitions, and 9 | function prototypes for the DATALOG module. 10 | =============================================================================== 11 | History: 12 | ------------------------------------------------------------------------------- 13 | 18-5-2001 (DD/MM/YYYY) Release Rev 1.0 14 | ------------------------------------------------------------------------------*/ 15 | 16 | #ifndef __DLOG4CH_H__ 17 | #define __DLOG4CH_H__ 18 | 19 | #define NULL 0 20 | 21 | typedef struct { long task; // Variable: Task address pointer 22 | int *iptr1; // Input: First input pointer (Q15) 23 | int *iptr2; // Input: Second input pointer (Q15) 24 | int *iptr3; // Input: Third input pointer (Q15) 25 | int *iptr4; // Input: Fourth input pointer (Q15) 26 | int trig_value; // Input: Trigger point (Q15) 27 | int prescalar; // Parameter: Data log prescale 28 | int skip_cntr; // Variable: Data log skip counter 29 | int cntr; // Variable: Data log counter 30 | long write_ptr; // Variable: Graph address pointer 31 | int size; // Parameter: Maximum data buffer 32 | int (*init)(); // Pointer to init function 33 | int (*update)(); // Pointer to update function 34 | } DLOG_4CH; 35 | 36 | typedef DLOG_4CH *DLOG_4CH_handle; 37 | 38 | void DLOG_4CH_init(void *); 39 | void DLOG_4CH_update(void *); 40 | 41 | /*============================================================================= 42 | Default initalizer for the DLOG_4CH object. 43 | ==============================================================================*/ 44 | 45 | #define DLOG_4CH_DEFAULTS { 0UL, \ 46 | NULL, \ 47 | NULL, \ 48 | NULL, \ 49 | NULL, \ 50 | 0, \ 51 | 1, \ 52 | 0, \ 53 | 0, \ 54 | 0UL, \ 55 | 0x400, \ 56 | (int (*)(int))DLOG_4CH_init, \ 57 | (int (*)(int))DLOG_4CH_update } 58 | 59 | #endif 60 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/dmctype.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: DMCTYPE.H 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: DMC data type definition file. 8 | ===================================================================================== 9 | History: 10 | ------------------------------------------------------------------------------------- 11 | 04-15-2005 Version 3.20 12 | ------------------------------------------------------------------------------*/ 13 | 14 | #ifndef DMCTYPE 15 | #define DMCTYPE 16 | 17 | //--------------------------------------------------------------------------- 18 | // For Portability, User Is Recommended To Use Following Data Type Size 19 | // Definitions For 16-bit and 32-Bit Signed/Unsigned Integers: 20 | // 21 | 22 | typedef int int16; 23 | typedef long int32; 24 | typedef unsigned int Uint16; 25 | typedef unsigned long Uint32; 26 | typedef float float32; 27 | typedef long double float64; 28 | 29 | 30 | #endif // DMCTYPE 31 | 32 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/f281xbmsk.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/f281xbmsk.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/f281xileg_vdc.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/f281xileg_vdc.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/f281xpwm.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/f281xpwm.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/f281xpwmdac.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/f281xpwmdac.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/f281xqep.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/f281xqep.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/ipark.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: IPARK.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Header file containing constants, data type definitions, and 9 | function prototypes for the IPARK. 10 | 11 | ===================================================================================== 12 | History: 13 | ------------------------------------------------------------------------------------- 14 | 04-15-2005 Version 3.20 15 | ------------------------------------------------------------------------------*/ 16 | #ifndef __IPARK_H__ 17 | #define __IPARK_H__ 18 | 19 | typedef struct { _iq Alpha; // Output: stationary d-axis stator variable 20 | _iq Beta; // Output: stationary q-axis stator variable 21 | _iq Angle; // Input: rotating angle (pu) 22 | _iq Ds; // Input: rotating d-axis stator variable 23 | _iq Qs; // Input: rotating q-axis stator variable 24 | void (*calc)(); // Pointer to calculation function 25 | } IPARK; 26 | 27 | typedef IPARK *IPARK_handle; 28 | /*----------------------------------------------------------------------------- 29 | Default initalizer for the IPARK object. 30 | -----------------------------------------------------------------------------*/ 31 | #define IPARK_DEFAULTS { 0, \ 32 | 0, \ 33 | 0, \ 34 | 0, \ 35 | 0, \ 36 | (void (*)(Uint32))ipark_calc } 37 | 38 | /*------------------------------------------------------------------------------ 39 | Prototypes for the functions in IPARK.C 40 | ------------------------------------------------------------------------------*/ 41 | void ipark_calc(IPARK_handle); 42 | 43 | #endif // __IPARK_H__ 44 | 45 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/parameter.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/parameter.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/park.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: PARK.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Header file containing constants, data type definitions, and 9 | function prototypes for the PARK. 10 | 11 | ===================================================================================== 12 | History: 13 | ------------------------------------------------------------------------------------- 14 | 04-15-2005 Version 3.20 15 | ------------------------------------------------------------------------------*/ 16 | #ifndef __PARK_H__ 17 | #define __PARK_H__ 18 | 19 | typedef struct { _iq Alpha; // Input: stationary d-axis stator variable 20 | _iq Beta; // Input: stationary q-axis stator variable 21 | _iq Angle; // Input: rotating angle (pu) 22 | _iq Ds; // Output: rotating d-axis stator variable 23 | _iq Qs; // Output: rotating q-axis stator variable 24 | void (*calc)(); // Pointer to calculation function 25 | } PARK; 26 | 27 | typedef PARK *PARK_handle; 28 | /*----------------------------------------------------------------------------- 29 | Default initalizer for the PARK object. 30 | -----------------------------------------------------------------------------*/ 31 | #define PARK_DEFAULTS { 0, \ 32 | 0, \ 33 | 0, \ 34 | 0, \ 35 | 0, \ 36 | (void (*)(Uint32))park_calc } 37 | 38 | /*------------------------------------------------------------------------------ 39 | Prototypes for the functions in PARK.C 40 | ------------------------------------------------------------------------------*/ 41 | void park_calc(PARK_handle); 42 | 43 | #endif // __PARK_H__ 44 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/pid_reg3.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: PID_REG3.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Header file containing constants, data type definitions, and 9 | function prototypes for the PIDREG3. 10 | ===================================================================================== 11 | History: 12 | ------------------------------------------------------------------------------------- 13 | 04-15-2005 Version 3.20 14 | ------------------------------------------------------------------------------*/ 15 | #ifndef __PIDREG3_H__ 16 | #define __PIDREG3_H__ 17 | 18 | typedef struct { _iq Ref; // Input: Reference input 19 | _iq Fdb; // Input: Feedback input 20 | _iq Err; // Variable: Error 21 | _iq Kp; // Parameter: Proportional gain 22 | _iq Up; // Variable: Proportional output 23 | _iq Ui; // Variable: Integral output 24 | _iq Ud; // Variable: Derivative output 25 | _iq OutPreSat; // Variable: Pre-saturated output 26 | _iq OutMax; // Parameter: Maximum output 27 | _iq OutMin; // Parameter: Minimum output 28 | _iq Out; // Output: PID output 29 | _iq SatErr; // Variable: Saturated difference 30 | _iq Ki; // Parameter: Integral gain 31 | _iq Kc; // Parameter: Integral correction gain 32 | _iq Kd; // Parameter: Derivative gain 33 | _iq Up1; // History: Previous proportional output 34 | void (*calc)(); // Pointer to calculation function 35 | } PIDREG3; 36 | 37 | typedef PIDREG3 *PIDREG3_handle; 38 | /*----------------------------------------------------------------------------- 39 | Default initalizer for the PIDREG3 object. 40 | -----------------------------------------------------------------------------*/ 41 | #define PIDREG3_DEFAULTS { 0, \ 42 | 0, \ 43 | 0, \ 44 | _IQ(1.3), \ 45 | 0, \ 46 | 0, \ 47 | 0, \ 48 | 0, \ 49 | _IQ(1), \ 50 | _IQ(-1), \ 51 | 0, \ 52 | 0, \ 53 | _IQ(0.02), \ 54 | _IQ(0.5), \ 55 | _IQ(1.05), \ 56 | 0, \ 57 | (void (*)(Uint32))pid_reg3_calc } 58 | 59 | /*------------------------------------------------------------------------------ 60 | Prototypes for the functions in PIDREG3.C 61 | ------------------------------------------------------------------------------*/ 62 | void pid_reg3_calc(PIDREG3_handle); 63 | 64 | #endif // __PIDREG3_H__ 65 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/pmsm3_1.h: -------------------------------------------------------------------------------- 1 | /* ============================================================================== 2 | System Name: PMSM31 3 | 4 | File Name: PMSM3_1.H 5 | 6 | Description: Primary system header file for the Real Implementation of Sensored 7 | Field Orientation Control for a Three Phase Permanent-Magnet 8 | Synchronous Motor (PMSM) using QEP sensor 9 | 10 | Originator: Digital control systems Group - Texas Instruments 11 | 12 | Note: In this software, the default inverter is supposed to be DMC1500 board. 13 | ===================================================================================== 14 | History: 15 | ------------------------------------------------------------------------------------- 16 | 04-15-2005 Version 3.20: Support both F280x and F281x targets 17 | 04-25-2005 Version 3.21: Move EINT and ERTM down to ensure that all initialization 18 | is completed before interrupts are allowed. 19 | ================================================================================= */ 20 | 21 | #ifndef PMSM3_1_H 22 | #define PMSM3_1_H 23 | 24 | /*------------------------------------------------------------------------------- 25 | Next, Include project specific include files. 26 | -------------------------------------------------------------------------------*/ 27 | #include "park.h" // Include header for the PARK object 28 | #include "ipark.h" // Include header for the IPARK object 29 | #include "pid_reg3.h" // Include header for the PIDREG3 object 30 | #include "clarke.h" // Include header for the CLARKE object 31 | #include "svgen_dq.h" // Include header for the SVGENDQ object 32 | #include "speed_fr.h" // Include header for the SPEED_MEAS_QEP object 33 | #include "rampgen.h" // Include header for the RAMPGEN object 34 | #include "rmp_cntl.h" // Include header for the RMPCNTL object 35 | 36 | #include "f281xqep.h" // Include header for the QEP object 37 | #include "f281xileg_vdc.h" // Include header for the ILEG2DCBUSMEAS object 38 | #include "f281xpwm.h" // Include header for the PWMGEN object 39 | #include "f281xpwmdac.h" // Include header for the PWMDAC object 40 | 41 | #include "dlog4ch.h" // Include header for the DLOG_4CH object 42 | 43 | #endif // end of PMSM3_1.H definition 44 | 45 | //=========================================================================== 46 | // No more. 47 | //=========================================================================== 48 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/rampgen.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: RAMPGEN.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | This file contains type definitions, constants and initializers for 9 | the ramp generation functions contained in RAMPGEN.C 10 | ===================================================================================== 11 | History: 12 | ------------------------------------------------------------------------------------- 13 | 04-15-2005 Version 3.20 14 | ------------------------------------------------------------------------------*/ 15 | #ifndef __RAMPGEN_H__ 16 | #define __RAMPGEN_H__ 17 | 18 | typedef struct { _iq Freq; // Input: Ramp frequency (pu) 19 | _iq StepAngleMax; // Parameter: Maximum step angle (pu) 20 | _iq Angle; // Variable: Step angle (pu) 21 | _iq Gain; // Input: Ramp gain (pu) 22 | _iq Out; // Output: Ramp signal (pu) 23 | _iq Offset; // Input: Ramp offset (pu) 24 | void (*calc)(); // Pointer to calculation function 25 | } RAMPGEN; 26 | 27 | typedef RAMPGEN *RAMPGEN_handle; 28 | /*------------------------------------------------------------------------------ 29 | Object Initializers 30 | ------------------------------------------------------------------------------*/ 31 | #define RAMPGEN_DEFAULTS {0,0,0,_IQ(1),0,_IQ(1), \ 32 | (void (*)(Uint32))rampgen_calc } 33 | 34 | /*------------------------------------------------------------------------------ 35 | Funtion prototypes 36 | ------------------------------------------------------------------------------*/ 37 | void rampgen_calc(RAMPGEN_handle); 38 | 39 | #endif // __RAMPGEN_H__ 40 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/rmp_cntl.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/rmp_cntl.h -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/speed_fr.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: SPEED_FR.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Header file containing the data types, constants for the rotor angle based 9 | speed measurement function. Also contains the prototypes for the 10 | functions implemented in SPEED_FR.C 11 | ===================================================================================== 12 | History: 13 | ------------------------------------------------------------------------------------- 14 | 04-15-2005 Version 3.20 15 | ------------------------------------------------------------------------------*/ 16 | #ifndef __SPEED_FR_H__ 17 | #define __SPEED_FR_H__ 18 | 19 | typedef struct { 20 | _iq ElecTheta; // Input: Electrical angle (pu) 21 | Uint32 DirectionQep; // Variable: Direction of rotation (Q0) - independently with global Q 22 | _iq OldElecTheta; // History: Electrical angle at previous step (pu) 23 | _iq Speed; // Output: Speed in per-unit (pu) 24 | Uint32 BaseRpm; // Parameter: Base speed in rpm (Q0) - independently with global Q 25 | _iq21 K1; // Parameter: Constant for differentiator (Q21) - independently with global Q 26 | _iq K2; // Parameter: Constant for low-pass filter (pu) 27 | _iq K3; // Parameter: Constant for low-pass filter (pu) 28 | int32 SpeedRpm; // Output : Speed in rpm (Q0) - independently with global Q 29 | void (*calc)(); // Pointer to the calulation function 30 | } SPEED_MEAS_QEP; // Data type created 31 | 32 | typedef SPEED_MEAS_QEP *SPEED_MEAS_QEP_handle; 33 | /*----------------------------------------------------------------------------- 34 | Default initalizer for the SPEED_MEAS_QEP object. 35 | -----------------------------------------------------------------------------*/ 36 | #define SPEED_MEAS_QEP_DEFAULTS { 0, \ 37 | 1, \ 38 | 0, \ 39 | 0, \ 40 | 0, \ 41 | 0, \ 42 | 0, \ 43 | 0, \ 44 | 0, \ 45 | (void (*)(Uint32))speed_frq_calc } 46 | 47 | /*------------------------------------------------------------------------------ 48 | Prototypes for the functions in SPEED_FR.C 49 | ------------------------------------------------------------------------------*/ 50 | void speed_frq_calc(SPEED_MEAS_QEP_handle); 51 | 52 | #endif // __SPEED_FR_H__ 53 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/svgen_dq.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: SVGEN_DQ.H (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Header file containing constants, data type definitions, and 9 | function prototypes for the SVGEN_DQ. 10 | ===================================================================================== 11 | History: 12 | ------------------------------------------------------------------------------------- 13 | 04-15-2005 Version 3.20 14 | ------------------------------------------------------------------------------*/ 15 | #ifndef __SVGEN_DQ_H__ 16 | #define __SVGEN_DQ_H__ 17 | 18 | typedef struct { _iq Ualpha; // Input: reference alpha-axis phase voltage 19 | _iq Ubeta; // Input: reference beta-axis phase voltage 20 | _iq Ta; // Output: reference phase-a switching function 21 | _iq Tb; // Output: reference phase-b switching function 22 | _iq Tc; // Output: reference phase-c switching function 23 | void (*calc)(); // Pointer to calculation function 24 | } SVGENDQ; 25 | 26 | typedef SVGENDQ *SVGENDQ_handle; 27 | /*----------------------------------------------------------------------------- 28 | Default initalizer for the SVGENDQ object. 29 | -----------------------------------------------------------------------------*/ 30 | #define SVGENDQ_DEFAULTS { 0,0,0,0,0, \ 31 | (void (*)(Uint32))svgendq_calc } 32 | 33 | /*------------------------------------------------------------------------------ 34 | Prototypes for the functions in SVGEN_DQ.C 35 | ------------------------------------------------------------------------------*/ 36 | void svgendq_calc(SVGENDQ_handle); 37 | 38 | #endif // __SVGEN_DQ_H__ 39 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/target.h: -------------------------------------------------------------------------------- 1 | /* ================================================================================= 2 | File name: TARGET.H 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: 8 | Target device selection file. 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | ------------------------------------------------------------------------------*/ 14 | 15 | #ifndef DSP_TARGET 16 | 17 | /*------------------------------------------------------------------------------ 18 | Following is the selection list of the target choices. 19 | Note that the F2808 also represents the F2801 and F2806 devices, 20 | and F2812 also represents the F2810 and F2811 devices. 21 | ------------------------------------------------------------------------------*/ 22 | #define F2808 1 23 | #define F2812 2 24 | #define UNKNOWN 4 25 | 26 | /*------------------------------------------------------------------------------ 27 | This line sets the target to one of the available choices. 28 | ------------------------------------------------------------------------------*/ 29 | #ifdef TARGET_IS_F2808 30 | #define DSP_TARGET F2808 31 | #endif 32 | 33 | #ifdef TARGET_IS_F2812 34 | #define DSP_TARGET F2812 35 | #endif 36 | 37 | 38 | #ifndef DSP_TARGET 39 | #error Critical: A target must be defined Please define a target in the \ 40 | CCS Build Options/Compiler Tab/Preprocessor/ Symbol defines. 41 | #endif 42 | 43 | #endif // TARGET 44 | 45 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/include/vssver2.scc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/include/vssver2.scc -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/lib/IQmath.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/lib/IQmath.lib -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/lib/rts2800_ml.lib: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/lib/rts2800_ml.lib -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/DLOG4CHC.asm: -------------------------------------------------------------------------------- 1 | ;============================================================================== 2 | ; File name : DLOG4CHC.ASM 3 | ; 4 | ; Originator : Advanced Embeeded Control (AEC) 5 | ; Texas Instruments Inc. 6 | ; 7 | ; Description : 4-Channel Data logging module 8 | ; 9 | ; Date : 02/01/2002 (DD/MM/YYYY) 10 | ;============================================================================== 11 | ; Routine Name: data_log_update 12 | ; 13 | ; C prototype : void DLOG_4CH_update(DLOG_4CH_handle); 14 | ; void DLOG_4CH_init(DLOG_4CH_handle); 15 | ; 16 | ; The struct object is defined in the header file "dlog_4ch.h" as follows: 17 | ; 18 | ; typedef struct { 19 | ; long task; /* Variable: Task address pointer */ 20 | ; int *iptr1; /* Input: First input pointer (Q15) */ 21 | ; int *iptr2; /* Input: Second input pointer (Q15) */ 22 | ; int *iptr3; /* Input: Third input pointer (Q15) */ 23 | ; int *iptr4; /* Input: Fourth input pointer (Q15) */ 24 | ; int trig_value; /* Input: Trigger point (Q15) */ 25 | ; int prescalar; /* Parameter: Data log prescale */ 26 | ; int skip_cntr; /* Variable: Data log skip counter */ 27 | ; int cntr; /* Variable: Data log counter */ 28 | ; long write_ptr; /* Variable: Graph address pointer */ 29 | ; int size; /* Parameter: Maximum data DLOG_4CH_buffer */ 30 | ; int (*init)(); /* Pointer to init function */ 31 | ; int (*update)(); /* Pointer to update function */ 32 | ; } DLOG_4CH; 33 | 34 | ;============================================================================== 35 | 36 | ; External Reference 37 | .def _DLOG_4CH_update 38 | .def _DLOG_4CH_init 39 | 40 | ; Data log buffer definition 41 | BUFF_SIZE .set 400h 42 | 43 | DLOG_4CH_buff1 .usect "DLOG", BUFF_SIZE 44 | DLOG_4CH_buff2 .usect "DLOG", BUFF_SIZE 45 | DLOG_4CH_buff3 .usect "DLOG", BUFF_SIZE 46 | DLOG_4CH_buff4 .usect "DLOG", BUFF_SIZE 47 | 48 | 49 | ;============================================================================== 50 | ; Initialization Function 51 | ;============================================================================== 52 | 53 | _DLOG_4CH_init: 54 | MOVL XAR5,#POS_TRIG_S1 55 | MOVL *XAR4,XAR5 ; task=#POS_TRIG_S1 56 | ADDB XAR4,#10 ; XAR4->trig_value 57 | 58 | MOV *+XAR4[2],#0 59 | 60 | MOVL XAR5,#DLOG_4CH_buff1 61 | MOVL *+XAR4[4],XAR5 ; write_ptr=DLOG_4CH_buff1 62 | 63 | 64 | MOV AL,*+XAR4[6] ; ACC=size 65 | MOV *+XAR4[3],AL ; cntr=size 66 | LRETR 67 | 68 | ;============================================================================== 69 | ; Datalog Update Function 70 | ;============================================================================== 71 | 72 | _DLOG_4CH_update: 73 | SETC SXM 74 | MOVL XAR5,XAR4 ; XAR4->task 75 | MOVL XAR7,*XAR4++ ; XAR4->iptr1, XAR7=task 76 | ADDB XAR5,#10 ; XAR5->trig_value 77 | LB *XAR7 ; Branch to TASK 78 | 79 | POS_TRIG_S1: 80 | MOV ACC,*XAR5 ; ACC=trig_value 81 | MOVL XAR6,*XAR4 ; XAR6=iptr1 82 | SUB ACC,*XAR6 ; ACC=(trig_value - *iptr1) 83 | BF DL_EXIT,LEQ ; Exit if ACC <= 0 84 | 85 | MOVL XAR6,#POS_TRIG_S2 86 | MOVL *--XAR4,XAR6 ; task=POS_TRIG_S2 87 | LRETR 88 | 89 | POS_TRIG_S2: 90 | MOV ACC,*XAR5 ; ACC=trig_value 91 | MOVL XAR6,*XAR4 ; XAR6=iptr1 92 | SUB ACC,*XAR6 ; ACC=(trig_value - *iptr1) 93 | BF DL_EXIT,GEQ ; Exit if ACC >= 0 94 | 95 | MOVL XAR6,#DL_TRIGGERED 96 | MOVL *--XAR4,XAR6 ; task=POS_TRIG_S2 97 | LRETR 98 | 99 | DL_TRIGGERED: 100 | INC *+XAR5[2] ; skip_cntr=skip_cntr+1 101 | MOV ACC,*+XAR5[2] ; ACC=skip_cntr 102 | SUB ACC,*+XAR5[1] ; ACC=skip_cntr-prescalar 103 | SBF DL_EXIT,NEQ ; if (skip_cntr+1) < prescalar, then exit 104 | 105 | MOV *+XAR5[2],#0 ; skip_cntr=0 106 | MOV ACC,*+XAR5[3] ; ACC=cntr 107 | SBF DLOG_END,EQ 108 | 109 | DEC *+XAR5[3] ; cntr=cntr-1 110 | ADDB XAR5,#4 ; XAR5->write_ptr 111 | 112 | MOVL XAR6,*XAR5 ; XAR6=write_ptr 113 | ADDB XAR6,#1 ; XAR6=write_ptr+1 114 | MOVL *XAR5,XAR6 ; write_ptr=write_ptr + 1 115 | SUBB XAR6,#1 ; XAR6=write_ptr 116 | 117 | MOV AR0,#BUFF_SIZE ; AR0=BUFF_SIZE 118 | 119 | 120 | ; Log sample pointed by IPTR1 121 | MOVL XAR7,*XAR4++ ; XAR7=iptr1 122 | MOV AL,*XAR7 ; AL=*iptr1 123 | NOP *,ARP6 124 | MOV *0++,AL ; *write_ptr=*iptr1, XAR6=write_ptr+size 125 | 126 | ; Log sample pointed by IPTR2 127 | MOVL XAR7,*XAR4++ ; XAR7=iptr2 128 | MOV AL,*XAR7 ; AL=*iptr2 129 | NOP *,ARP6 130 | MOV *0++,AL ; *write_ptr=*iptr2, XAR6=write_ptr+size 131 | 132 | ; Log sample pointed by IPTR3 133 | MOVL XAR7,*XAR4++ ; XAR7=iptr3 134 | MOV AL,*XAR7 ; AL=*iptr3 135 | NOP *,ARP6 136 | MOV *0++,AL ; *write_ptr=*iptr3, XAR6=write_ptr+size 137 | 138 | ; Log sample pointed by IPTR4 139 | MOVL XAR7,*XAR4++ ; XAR7=iptr4 140 | MOV AL,*XAR7 ; AL=*iptr4 141 | NOP *,ARP6 142 | MOV *0++,AL ; *write_ptr=*iptr4, XAR6=write_ptr+size 143 | LRETR 144 | 145 | ; Reinitialise the module to log the data when the logging is triggered next 146 | 147 | DLOG_END: 148 | 149 | MOVL XAR6,#DLOG_4CH_buff1 150 | MOVL *+XAR5[4],XAR6 ; write_ptr=DLOG_4CH_buff1 151 | 152 | MOVL XAR6,#POS_TRIG_S1 153 | MOVL *--XAR4,XAR6 ; task=POS_TRIG_S2 154 | 155 | MOV AL,*+XAR5[6] ; ACC=size 156 | MOV *+XAR5[3],AL ; cntr=size 157 | 158 | DL_EXIT: 159 | LRETR 160 | 161 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/DSP281x_GlobalVariableDefs.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_GlobalVariableDefs.c 4 | // 5 | // TITLE: DSP281x Global Variables and Data Section Pragmas. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added support for C++ 13 | //########################################################################### 14 | 15 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 16 | 17 | //--------------------------------------------------------------------------- 18 | // Define Global Peripheral Variables: 19 | // 20 | 21 | #ifdef __cplusplus 22 | #pragma DATA_SECTION("AdcRegsFile") 23 | #else 24 | #pragma DATA_SECTION(AdcRegs,"AdcRegsFile"); 25 | #endif 26 | volatile struct ADC_REGS AdcRegs; 27 | 28 | 29 | #ifdef __cplusplus 30 | #pragma DATA_SECTION("CpuTimer0RegsFile") 31 | #else 32 | #pragma DATA_SECTION(CpuTimer0Regs,"CpuTimer0RegsFile"); 33 | #endif 34 | volatile struct CPUTIMER_REGS CpuTimer0Regs; 35 | 36 | 37 | // CPU Timer 1 and Timer2 are reserved for BIOS and thus not used 38 | //#pragma DATA_SECTION(CpuTimer1Regs,"CpuTimer1RegsFile"); 39 | //volatile struct CPUTIMER_REGS CpuTimer1Regs; 40 | //#pragma DATA_SECTION(CpuTimer2Regs,"CpuTimer2RegsFile"); 41 | //volatile struct CPUTIMER_REGS CpuTimer2Regs; 42 | 43 | //---------------------------------------- 44 | #ifdef __cplusplus 45 | #pragma DATA_SECTION("ECanaRegsFile") 46 | #else 47 | #pragma DATA_SECTION(ECanaRegs,"ECanaRegsFile"); 48 | #endif 49 | volatile struct ECAN_REGS ECanaRegs; 50 | 51 | //---------------------------------------- 52 | #ifdef __cplusplus 53 | #pragma DATA_SECTION("ECanaMboxesFile") 54 | #else 55 | #pragma DATA_SECTION(ECanaMboxes,"ECanaMboxesFile"); 56 | #endif 57 | volatile struct ECAN_MBOXES ECanaMboxes; 58 | 59 | //---------------------------------------- 60 | #ifdef __cplusplus 61 | #pragma DATA_SECTION("ECanaLAMRegsFile") 62 | #else 63 | #pragma DATA_SECTION(ECanaLAMRegs,"ECanaLAMRegsFile"); 64 | #endif 65 | volatile struct LAM_REGS ECanaLAMRegs; 66 | 67 | //---------------------------------------- 68 | #ifdef __cplusplus 69 | #pragma DATA_SECTION("ECanaMOTSRegsFile") 70 | #else 71 | #pragma DATA_SECTION(ECanaMOTSRegs,"ECanaMOTSRegsFile"); 72 | #endif 73 | volatile struct MOTS_REGS ECanaMOTSRegs; 74 | 75 | 76 | //---------------------------------------- 77 | #ifdef __cplusplus 78 | #pragma DATA_SECTION("ECanaMOTORegsFile") 79 | #else 80 | #pragma DATA_SECTION(ECanaMOTORegs,"ECanaMOTORegsFile"); 81 | #endif 82 | volatile struct MOTO_REGS ECanaMOTORegs; 83 | 84 | //---------------------------------------- 85 | #ifdef __cplusplus 86 | #pragma DATA_SECTION("EvaRegsFile") 87 | #else 88 | #pragma DATA_SECTION(EvaRegs,"EvaRegsFile"); 89 | #endif 90 | volatile struct EVA_REGS EvaRegs; 91 | 92 | //---------------------------------------- 93 | #ifdef __cplusplus 94 | #pragma DATA_SECTION("EvbRegsFile") 95 | #else 96 | #pragma DATA_SECTION(EvbRegs,"EvbRegsFile"); 97 | #endif 98 | volatile struct EVB_REGS EvbRegs; 99 | 100 | //---------------------------------------- 101 | #ifdef __cplusplus 102 | #pragma DATA_SECTION("GpioDataRegsFile") 103 | #else 104 | #pragma DATA_SECTION(GpioDataRegs,"GpioDataRegsFile"); 105 | #endif 106 | volatile struct GPIO_DATA_REGS GpioDataRegs; 107 | 108 | //---------------------------------------- 109 | #ifdef __cplusplus 110 | #pragma DATA_SECTION("GpioMuxRegsFile") 111 | #else 112 | #pragma DATA_SECTION(GpioMuxRegs,"GpioMuxRegsFile"); 113 | #endif 114 | volatile struct GPIO_MUX_REGS GpioMuxRegs; 115 | 116 | //---------------------------------------- 117 | #ifdef __cplusplus 118 | #pragma DATA_SECTION("McbspaRegsFile") 119 | #else 120 | #pragma DATA_SECTION(McbspaRegs,"McbspaRegsFile"); 121 | #endif 122 | volatile struct MCBSP_REGS McbspaRegs; 123 | 124 | //---------------------------------------- 125 | #ifdef __cplusplus 126 | #pragma DATA_SECTION("PieCtrlRegsFile") 127 | #else 128 | #pragma DATA_SECTION(PieCtrlRegs,"PieCtrlRegsFile"); 129 | #endif 130 | volatile struct PIE_CTRL_REGS PieCtrlRegs; 131 | 132 | //---------------------------------------- 133 | #ifdef __cplusplus 134 | #pragma DATA_SECTION("PieVectTableFile") 135 | #else 136 | #pragma DATA_SECTION(PieVectTable,"PieVectTableFile"); 137 | #endif 138 | struct PIE_VECT_TABLE PieVectTable; 139 | 140 | //---------------------------------------- 141 | #ifdef __cplusplus 142 | #pragma DATA_SECTION("SciaRegsFile") 143 | #else 144 | #pragma DATA_SECTION(SciaRegs,"SciaRegsFile"); 145 | #endif 146 | volatile struct SCI_REGS SciaRegs; 147 | 148 | //---------------------------------------- 149 | #ifdef __cplusplus 150 | #pragma DATA_SECTION("ScibRegsFile") 151 | #else 152 | #pragma DATA_SECTION(ScibRegs,"ScibRegsFile"); 153 | #endif 154 | volatile struct SCI_REGS ScibRegs; 155 | 156 | //---------------------------------------- 157 | #ifdef __cplusplus 158 | #pragma DATA_SECTION("SpiaRegsFile") 159 | #else 160 | #pragma DATA_SECTION(SpiaRegs,"SpiaRegsFile"); 161 | #endif 162 | volatile struct SPI_REGS SpiaRegs; 163 | 164 | //---------------------------------------- 165 | #ifdef __cplusplus 166 | #pragma DATA_SECTION("SysCtrlRegsFile") 167 | #else 168 | #pragma DATA_SECTION(SysCtrlRegs,"SysCtrlRegsFile"); 169 | #endif 170 | volatile struct SYS_CTRL_REGS SysCtrlRegs; 171 | 172 | //---------------------------------------- 173 | #ifdef __cplusplus 174 | #pragma DATA_SECTION("DevEmuRegsFile") 175 | #else 176 | #pragma DATA_SECTION(DevEmuRegs,"DevEmuRegsFile"); 177 | #endif 178 | volatile struct DEV_EMU_REGS DevEmuRegs; 179 | 180 | //---------------------------------------- 181 | #ifdef __cplusplus 182 | #pragma DATA_SECTION("CsmRegsFile") 183 | #else 184 | #pragma DATA_SECTION(CsmRegs,"CsmRegsFile"); 185 | #endif 186 | volatile struct CSM_REGS CsmRegs; 187 | 188 | //---------------------------------------- 189 | #ifdef __cplusplus 190 | #pragma DATA_SECTION("CsmPwlFile") 191 | #else 192 | #pragma DATA_SECTION(CsmPwl,"CsmPwlFile"); 193 | #endif 194 | volatile struct CSM_PWL CsmPwl; 195 | 196 | 197 | //---------------------------------------- 198 | #ifdef __cplusplus 199 | #pragma DATA_SECTION("FlashRegsFile") 200 | #else 201 | #pragma DATA_SECTION(FlashRegs,"FlashRegsFile"); 202 | #endif 203 | volatile struct FLASH_REGS FlashRegs; 204 | 205 | #if DSP28_F2812 206 | //---------------------------------------- 207 | #ifdef __cplusplus 208 | #pragma DATA_SECTION("XintfRegsFile") 209 | #else 210 | #pragma DATA_SECTION(XintfRegs,"XintfRegsFile"); 211 | #endif 212 | volatile struct XINTF_REGS XintfRegs; 213 | #endif 214 | 215 | //---------------------------------------- 216 | #ifdef __cplusplus 217 | #pragma DATA_SECTION("XIntruptRegsFile") 218 | #else 219 | #pragma DATA_SECTION(XIntruptRegs,"XIntruptRegsFile"); 220 | #endif 221 | volatile struct XINTRUPT_REGS XIntruptRegs; 222 | 223 | 224 | 225 | // The following are provided to support alternate notation 226 | // that was used in an early version of the header files 227 | 228 | #define ADCRegs AdcRegs 229 | #define CPUTimer0Regs CpuTimer0Regs 230 | #define ECANARegs ECanaRegs 231 | #define ECANAMboxes ECanaMboxes 232 | #define EVARegs EvaRegs 233 | #define GPIODataRegs GpioDataRegs 234 | #define GPIOMuxRegs GpioMuxRegs 235 | #define MCBSPARegs McbspaRegs 236 | #define PIECtrlRegs PieCtrlRegs 237 | #define PIEVectTable PieVectTable 238 | #define SCIARegs SciaRegs 239 | #define SCIBRegs ScibRegs 240 | #define SYSCtrlRegs SysCtrlRegs 241 | #define DEVEmuRegs DevEmuRegs 242 | #define CSMRegs CsmRegs 243 | #define CSMPwl CsmPwl 244 | #define FLASHRegs FlashRegs 245 | #define XINTFRegs XintfRegs 246 | #define XINTRUPTRegs XIntruptRegs 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/DSP281x_PieCtrl.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieCtrl.c 4 | // 5 | // TITLE: DSP281x Device PIE Control Register Initialization Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Added ENPIE = 0 to the IntPieCtrl function 13 | // | | | Removed ENPIE = 1 from the IntPieCtrl function 14 | // | | | Created EnableInterrupts function 15 | //########################################################################### 16 | 17 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 18 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 19 | 20 | //--------------------------------------------------------------------------- 21 | // InitPieCtrl: 22 | //--------------------------------------------------------------------------- 23 | // This function initializes the PIE control registers to a known state. 24 | // 25 | void InitPieCtrl(void) 26 | { 27 | // Disable Interrupts at the CPU level: 28 | DINT; 29 | 30 | // Disable the PIE 31 | PieCtrlRegs.PIECRTL.bit.ENPIE = 0; 32 | 33 | // Clear all PIEIER registers: 34 | PieCtrlRegs.PIEIER1.all = 0; 35 | PieCtrlRegs.PIEIER2.all = 0; 36 | PieCtrlRegs.PIEIER3.all = 0; 37 | PieCtrlRegs.PIEIER4.all = 0; 38 | PieCtrlRegs.PIEIER5.all = 0; 39 | PieCtrlRegs.PIEIER6.all = 0; 40 | PieCtrlRegs.PIEIER7.all = 0; 41 | PieCtrlRegs.PIEIER8.all = 0; 42 | PieCtrlRegs.PIEIER9.all = 0; 43 | PieCtrlRegs.PIEIER10.all = 0; 44 | PieCtrlRegs.PIEIER11.all = 0; 45 | PieCtrlRegs.PIEIER12.all = 0; 46 | 47 | // Clear all PIEIFR registers: 48 | PieCtrlRegs.PIEIFR1.all = 0; 49 | PieCtrlRegs.PIEIFR2.all = 0; 50 | PieCtrlRegs.PIEIFR3.all = 0; 51 | PieCtrlRegs.PIEIFR4.all = 0; 52 | PieCtrlRegs.PIEIFR5.all = 0; 53 | PieCtrlRegs.PIEIFR6.all = 0; 54 | PieCtrlRegs.PIEIFR7.all = 0; 55 | PieCtrlRegs.PIEIFR8.all = 0; 56 | PieCtrlRegs.PIEIFR9.all = 0; 57 | PieCtrlRegs.PIEIFR10.all = 0; 58 | PieCtrlRegs.PIEIFR11.all = 0; 59 | PieCtrlRegs.PIEIFR12.all = 0; 60 | 61 | 62 | } 63 | 64 | //--------------------------------------------------------------------------- 65 | // EnableInterrupts: 66 | //--------------------------------------------------------------------------- 67 | // This function enables the PIE module and CPU interrupts 68 | // 69 | void EnableInterrupts() 70 | { 71 | 72 | // Enable the PIE 73 | PieCtrlRegs.PIECRTL.bit.ENPIE = 1; 74 | 75 | // Enables PIE to drive a pulse into the CPU 76 | PieCtrlRegs.PIEACK.all = 0xFFFF; 77 | 78 | // Enable Interrupts at the CPU level 79 | EINT; 80 | 81 | } 82 | 83 | 84 | //=========================================================================== 85 | // No more. 86 | //=========================================================================== 87 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/DSP281x_PieVect.c: -------------------------------------------------------------------------------- 1 | //########################################################################### 2 | // 3 | // FILE: DSP281x_PieVect.c 4 | // 5 | // TITLE: DSP281x Devices PIE Vector Table Initialization Functions. 6 | // 7 | //########################################################################### 8 | // 9 | // Ver | dd mmm yyyy | Who | Description of changes 10 | // =====|=============|======|=============================================== 11 | // 1.00| 11 Sep 2003 | L.H. | Changes since previous version (v.58 Alpha) 12 | // | | | Changed USER0-USER11 to USER1-USER12 to match the CPU guide 13 | //########################################################################### 14 | 15 | #include "DSP281x_Device.h" // DSP281x Headerfile Include File 16 | #include "DSP281x_Examples.h" // DSP281x Examples Include File 17 | 18 | const struct PIE_VECT_TABLE PieVectTableInit = { 19 | 20 | PIE_RESERVED, // Reserved space 21 | PIE_RESERVED, 22 | PIE_RESERVED, 23 | PIE_RESERVED, 24 | PIE_RESERVED, 25 | PIE_RESERVED, 26 | PIE_RESERVED, 27 | PIE_RESERVED, 28 | PIE_RESERVED, 29 | PIE_RESERVED, 30 | PIE_RESERVED, 31 | PIE_RESERVED, 32 | PIE_RESERVED, 33 | 34 | 35 | // Non-Peripheral Interrupts 36 | INT13_ISR, // XINT13 or CPU-Timer 1 37 | INT14_ISR, // CPU-Timer2 38 | DATALOG_ISR, // Datalogging interrupt 39 | RTOSINT_ISR, // RTOS interrupt 40 | EMUINT_ISR, // Emulation interrupt 41 | NMI_ISR, // Non-maskable interrupt 42 | ILLEGAL_ISR, // Illegal operation TRAP 43 | USER1_ISR, // User Defined trap 1 44 | USER2_ISR, // User Defined trap 2 45 | USER3_ISR, // User Defined trap 3 46 | USER4_ISR, // User Defined trap 4 47 | USER5_ISR, // User Defined trap 5 48 | USER6_ISR, // User Defined trap 6 49 | USER7_ISR, // User Defined trap 7 50 | USER8_ISR, // User Defined trap 8 51 | USER9_ISR, // User Defined trap 9 52 | USER10_ISR, // User Defined trap 10 53 | USER11_ISR, // User Defined trap 11 54 | USER12_ISR, // User Defined trap 12 55 | 56 | // Group 1 PIE Vectors 57 | PDPINTA_ISR, // EV-A 58 | PDPINTB_ISR, // EV-B 59 | rsvd_ISR, 60 | XINT1_ISR, 61 | XINT2_ISR, 62 | ADCINT_ISR, // ADC 63 | TINT0_ISR, // Timer 0 64 | WAKEINT_ISR, // WD 65 | 66 | // Group 2 PIE Vectors 67 | CMP1INT_ISR, // EV-A 68 | CMP2INT_ISR, // EV-A 69 | CMP3INT_ISR, // EV-A 70 | T1PINT_ISR, // EV-A 71 | T1CINT_ISR, // EV-A 72 | T1UFINT_ISR, // EV-A 73 | T1OFINT_ISR, // EV-A 74 | rsvd_ISR, 75 | 76 | // Group 3 PIE Vectors 77 | T2PINT_ISR, // EV-A 78 | T2CINT_ISR, // EV-A 79 | T2UFINT_ISR, // EV-A 80 | T2OFINT_ISR, // EV-A 81 | CAPINT1_ISR, // EV-A 82 | CAPINT2_ISR, // EV-A 83 | CAPINT3_ISR, // EV-A 84 | rsvd_ISR, 85 | 86 | // Group 4 PIE Vectors 87 | CMP4INT_ISR, // EV-B 88 | CMP5INT_ISR, // EV-B 89 | CMP6INT_ISR, // EV-B 90 | T3PINT_ISR, // EV-B 91 | T3CINT_ISR, // EV-B 92 | T3UFINT_ISR, // EV-B 93 | T3OFINT_ISR, // EV-B 94 | rsvd_ISR, 95 | 96 | // Group 5 PIE Vectors 97 | T4PINT_ISR, // EV-B 98 | T4CINT_ISR, // EV-B 99 | T4UFINT_ISR, // EV-B 100 | T4OFINT_ISR, // EV-B 101 | CAPINT4_ISR, // EV-B 102 | CAPINT5_ISR, // EV-B 103 | CAPINT6_ISR, // EV-B 104 | rsvd_ISR, 105 | 106 | // Group 6 PIE Vectors 107 | SPIRXINTA_ISR, // SPI-A 108 | SPITXINTA_ISR, // SPI-A 109 | rsvd_ISR, 110 | rsvd_ISR, 111 | MRINTA_ISR, // McBSP-A 112 | MXINTA_ISR, // McBSP-A 113 | rsvd_ISR, 114 | rsvd_ISR, 115 | 116 | // Group 7 PIE Vectors 117 | rsvd_ISR, 118 | rsvd_ISR, 119 | rsvd_ISR, 120 | rsvd_ISR, 121 | rsvd_ISR, 122 | rsvd_ISR, 123 | rsvd_ISR, 124 | rsvd_ISR, 125 | 126 | // Group 8 PIE Vectors 127 | rsvd_ISR, 128 | rsvd_ISR, 129 | rsvd_ISR, 130 | rsvd_ISR, 131 | rsvd_ISR, 132 | rsvd_ISR, 133 | rsvd_ISR, 134 | rsvd_ISR, 135 | 136 | // Group 9 PIE Vectors 137 | SCIRXINTA_ISR, // SCI-A 138 | SCITXINTA_ISR, // SCI-A 139 | SCIRXINTB_ISR, // SCI-B 140 | SCITXINTB_ISR, // SCI-B 141 | ECAN0INTA_ISR, // eCAN 142 | ECAN1INTA_ISR, // eCAN 143 | rsvd_ISR, 144 | rsvd_ISR, 145 | 146 | // Group 10 PIE Vectors 147 | rsvd_ISR, 148 | rsvd_ISR, 149 | rsvd_ISR, 150 | rsvd_ISR, 151 | rsvd_ISR, 152 | rsvd_ISR, 153 | rsvd_ISR, 154 | rsvd_ISR, 155 | 156 | // Group 11 PIE Vectors 157 | rsvd_ISR, 158 | rsvd_ISR, 159 | rsvd_ISR, 160 | rsvd_ISR, 161 | rsvd_ISR, 162 | rsvd_ISR, 163 | rsvd_ISR, 164 | rsvd_ISR, 165 | 166 | // Group 12 PIE Vectors 167 | rsvd_ISR, 168 | rsvd_ISR, 169 | rsvd_ISR, 170 | rsvd_ISR, 171 | rsvd_ISR, 172 | rsvd_ISR, 173 | rsvd_ISR, 174 | rsvd_ISR, 175 | }; 176 | 177 | 178 | //--------------------------------------------------------------------------- 179 | // InitPieVectTable: 180 | //--------------------------------------------------------------------------- 181 | // This function initializes the PIE vector table to a known state. 182 | // This function must be executed after boot time. 183 | // 184 | 185 | void InitPieVectTable(void) 186 | { 187 | int16 i; 188 | Uint32 *Source = (void *) &PieVectTableInit; //******donnot understand!! 189 | Uint32 *Dest = (void *) &PieVectTable; //******donnot understand!! 190 | 191 | EALLOW; 192 | for(i=0; i < 128; i++) 193 | *Dest++ = *Source++; 194 | EDIS; 195 | 196 | // Enable the PIE Vector Table 197 | PieCtrlRegs.PIECRTL.bit.ENPIE = 1; 198 | 199 | } 200 | 201 | //=========================================================================== 202 | // No more. 203 | //=========================================================================== 204 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/DSP281x_SysCtrl.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/DSP281x_SysCtrl.c -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/DSP281x_usDelay.asm: -------------------------------------------------------------------------------- 1 | ;//########################################################################### 2 | ;// 3 | ;// FILE: DSP281x_usDelay.asm 4 | ;// 5 | ;// TITLE: Simple delay function 6 | ;// 7 | ;// DESCRIPTION: 8 | ;// 9 | ;// This is a simple delay function that can be used to insert a specified 10 | ;// delay into code. 11 | ;// 12 | ;// This function is only accurate if executed from internal zero-waitstate 13 | ;// SARAM. If it is executed from waitstate memory then the delay will be 14 | ;// longer then specified. 15 | ;// 16 | ;// To use this function: 17 | ;// 18 | ;// 1 - update the CPU clock speed in the DSP281x_Examples.h 19 | ;// file. For example: 20 | ;// #define CPU_CLOCK_SPEED 6.6667L // for a 150MHz CPU clock speed 21 | ;// 22 | ;// 2 - Call this function by using the DELAY_US(A) macro 23 | ;// that is defined in the DSP28_Device.h file. This macro 24 | ;// will convert the number of microseconds specified 25 | ;// into a loop count for use with this function. 26 | ;// This count will be based on the CPU frequency you specify. 27 | ;// 28 | ;// 3 - For the most accurate delay 29 | ;// - Execute this function in 0 waitstate RAM. 30 | ;// - Disable interrupts before calling the function 31 | ;// If you do not disable interrupts, then think of 32 | ;// this as an "at least" delay function as the actual 33 | ;// delay may be longer. 34 | ;// 35 | ;// The C assembly call from the DELAY_US(time) macro will 36 | ;// look as follows: 37 | ;// 38 | ;// extern void Delay(long LoopCount); 39 | ;// 40 | ;// MOV AL,#LowLoopCount 41 | ;// MOV AH,#HighLoopCount 42 | ;// LCR _Delay 43 | ;// 44 | ;// Or as follows (if count is less then 16-bits): 45 | ;// 46 | ;// MOV ACC,#LoopCount 47 | ;// LCR _Delay 48 | ;// 49 | ;// 50 | ;//########################################################################### 51 | ;// 52 | ;// Ver | dd mmm yyyy | Who | Description of changes 53 | ;// =====|=============|======|=============================================== 54 | ;// 1.00| 11 Sep 2003 | L.H. | No changes since v.58 55 | ;//########################################################################### 56 | 57 | .def _DSP28x_usDelay 58 | .sect "ramfuncs" 59 | 60 | .global __DSP28x_usDelay 61 | _DSP28x_usDelay: 62 | SUB ACC,#1 63 | BF _DSP28x_usDelay,GEQ ;; Loop if ACC >= 0 64 | LRETR 65 | 66 | ;There is a 9/10 cycle overhead and each loop 67 | ;takes five cycles. The LoopCount is given by 68 | ;the following formula: 69 | ; DELAY_CPU_CYCLES = 9 + 5*LoopCount 70 | ; LoopCount = (DELAY_CPU_CYCLES - 9) / 5 71 | ; The macro DELAY_US(A) performs this calculation for you 72 | ;================================================== 73 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/clarke.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: CLARKE.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: Clarke Transformation 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "clarke.h" 19 | 20 | void clarke_calc(CLARKE *v) 21 | { 22 | 23 | v->Alpha = v->As; 24 | 25 | v->Beta = _IQmpy((v->As + _IQmpy(_IQ(2),v->Bs)),_IQ(0.57735026918963)); // 1/sqrt(3) = 0.57735026918963 26 | 27 | } 28 | 29 | void clarke_calc(CLARKE *v) 30 | { 31 | 32 | v->Alpha = v->As; 33 | 34 | v->Beta = _IQmpy((v->As + _IQmpy(_IQ(2),v->Bs)),_IQ(0.57735026918963)); // 1/sqrt(3) = 0.57735026918963 35 | 36 | } 37 | 38 | 39 | 40 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/f281xileg_vdc.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/f281xileg_vdc.c -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/f281xpwm.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/f281xpwm.c -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/f281xpwmdac.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/f281xpwmdac.c -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/f281xqep.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/f281xqep.c -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/ipark.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: IPARK.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Dsscription: Inverse Park Transformation 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "ipark.h" 19 | 20 | void ipark_calc(IPARK *v) 21 | { 22 | _iq Cosine,Sine; 23 | 24 | // Using look-up IQ sine table 25 | Sine = _IQsinPU(v->Angle); 26 | Cosine = _IQcosPU(v->Angle); 27 | 28 | v->Alpha = _IQmpy(v->Ds,Cosine) - _IQmpy(v->Qs,Sine); 29 | v->Beta = _IQmpy(v->Qs,Cosine) + _IQmpy(v->Ds,Sine); 30 | } 31 | 32 | void ipark_calc(IPARK *v) 33 | { 34 | _iq Cosine,Sine; 35 | 36 | // Using look-up IQ sine table 37 | Sine = _IQsinPU(v->Angle); 38 | Cosine = _IQcosPU(v->Angle); 39 | 40 | v->Alpha = _IQmpy(v->Ds,Cosine) - _IQmpy(v->Qs,Sine); 41 | v->Beta = _IQmpy(v->Qs,Cosine) + _IQmpy(v->Ds,Sine); 42 | } 43 | 44 | 45 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/main.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/main.c -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/pid_reg3.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: PID_REG3.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: The PID controller with anti-windup 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "pid_reg3.h" 19 | 20 | void pid_reg3_calc(PIDREG3 *v) 21 | { 22 | // Compute the error 23 | v->Err = v->Ref - v->Fdb; 24 | 25 | // Compute the proportional output 26 | v->Up = _IQmpy(v->Kp,v->Err); 27 | 28 | // Compute the integral output 29 | v->Ui = v->Ui + _IQmpy(v->Ki,v->Up) + _IQmpy(v->Kc,v->SatErr); 30 | 31 | // Compute the derivative output 32 | v->Ud = _IQmpy(v->Kd,(v->Up - v->Up1)); 33 | 34 | // Compute the pre-saturated output 35 | v->OutPreSat = v->Up + v->Ui + v->Ud; 36 | 37 | // Saturate the output 38 | if (v->OutPreSat > v->OutMax) 39 | v->Out = v->OutMax; 40 | else if (v->OutPreSat < v->OutMin) 41 | v->Out = v->OutMin; 42 | else 43 | v->Out = v->OutPreSat; 44 | 45 | // Compute the saturate difference 46 | v->SatErr = v->Out - v->OutPreSat; 47 | 48 | // Update the previous proportional output 49 | v->Up1 = v->Up; 50 | 51 | } 52 | 53 | 54 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/rampgen.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: RAMPGEN.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: The Ramp Generation 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "rampgen.h" 19 | 20 | void rampgen_calc(RAMPGEN *v) 21 | { 22 | 23 | // Compute the angle rate 24 | v->Angle += _IQmpy(v->StepAngleMax,v->Freq); 25 | 26 | // Saturate the angle rate within (-1,1) 27 | if (v->Angle>_IQ(1.0)) 28 | v->Angle -= _IQ(1.0); 29 | else if (v->Angle<_IQ(-1.0)) 30 | v->Angle += _IQ(1.0); 31 | 32 | // Compute the ramp output 33 | v->Out = _IQmpy(v->Angle,v->Gain) + v->Offset; 34 | 35 | // Saturate the ramp output within (-1,1) 36 | if (v->Out>_IQ(1.0)) 37 | v->Out -= _IQ(1.0); 38 | else if (v->Out<_IQ(-1.0)) 39 | v->Out += _IQ(1.0); 40 | 41 | } 42 | 43 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/rmp_cntl.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: RMP_CNTL.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: The Ramp Control 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "rmp_cntl.h" 19 | 20 | 21 | void rmp_cntl_calc(RMPCNTL *v) 22 | { 23 | _iq tmp; 24 | 25 | tmp = v->TargetValue - v->SetpointValue; 26 | 27 | if (_IQabs(tmp) > _IQ(0.0000305)) 28 | { 29 | v->RampDelayCount += 1; 30 | if (v->RampDelayCount >= v->RampDelayMax) 31 | { 32 | if (v->TargetValue >= v->SetpointValue) 33 | { 34 | v->SetpointValue += _IQ(0.0000305); // 0.0000305 is resolution of Q15 35 | if (v->SetpointValue > v->RampHighLimit) 36 | v->SetpointValue = v->RampHighLimit; 37 | v->RampDelayCount = 0; 38 | } 39 | else 40 | { 41 | v->SetpointValue -= _IQ(0.0000305); // 0.0000305 is resolution of Q15 42 | if (v->SetpointValue < v->RampLowLimit) 43 | v->SetpointValue = v->RampLowLimit; 44 | v->RampDelayCount = 0; 45 | } 46 | } 47 | } 48 | else v->EqualFlag = 0x7FFFFFFF; 49 | } 50 | 51 | 52 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/speed_fr.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: SPEED_FR.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: Speed measurement computation based QEP encoder (rotor angle) 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "speed_fr.h" 19 | 20 | void speed_frq_calc(SPEED_MEAS_QEP *v) 21 | { 22 | 23 | _iq Tmp1; 24 | 25 | // Differentiator 26 | // Synchronous speed computation 27 | if ((v->ElecTheta < _IQ(0.9))&(v->ElecTheta > _IQ(0.1))) 28 | // Q21 = Q21*(GLOBAL_Q-GLOBAL_Q) 29 | Tmp1 = _IQmpy(v->K1,(v->ElecTheta - v->OldElecTheta)); 30 | else Tmp1 = _IQtoIQ21(v->Speed); 31 | 32 | 33 | // Low-pass filter 34 | // Q21 = GLOBAL_Q*Q21 + GLOBAL_Q*Q21 35 | Tmp1 = _IQmpy(v->K2,_IQtoIQ21(v->Speed))+_IQmpy(v->K3,Tmp1); 36 | 37 | if (Tmp1>_IQ21(1)) 38 | v->Speed = _IQ(1); 39 | else if (Tmp1<_IQ21(-1)) 40 | v->Speed = _IQ(-1); 41 | else 42 | v->Speed = _IQ21toIQ(Tmp1); 43 | 44 | // Update the electrical angle 45 | v->OldElecTheta = v->ElecTheta; 46 | 47 | // Change motor speed from pu value to rpm value (GLOBAL_Q -> Q0) 48 | // Q0 = Q0*GLOBAL_Q => _IQXmpy(), X = GLOBAL_Q 49 | v->SpeedRpm = _IQmpy(v->BaseRpm,v->Speed); 50 | 51 | } 52 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/svgen_dq.c: -------------------------------------------------------------------------------- 1 | /*===================================================================================== 2 | File name: SVGEN_DQ.C (IQ version) 3 | 4 | Originator: Digital Control Systems Group 5 | Texas Instruments 6 | 7 | Description: Space-vector PWM generation based on d-q components 8 | 9 | ===================================================================================== 10 | History: 11 | ------------------------------------------------------------------------------------- 12 | 04-15-2005 Version 3.20 13 | -------------------------------------------------------------------------------------*/ 14 | 15 | #include "IQmathLib.h" // Include header for IQmath library 16 | // Don't forget to set a proper GLOBAL_Q in "IQmathLib.h" file 17 | #include "dmctype.h" 18 | #include "svgen_dq.h" 19 | 20 | void svgendq_calc(SVGENDQ *v) 21 | { 22 | 23 | _iq Va,Vb,Vc,t1,t2; 24 | Uint32 Sector = 0; // Sector is treated as Q0 - independently with global Q 25 | 26 | // Inverse clarke transformation 27 | Va = v->Ubeta; 28 | Vb = _IQmpy(_IQ(-0.5),v->Ubeta) + _IQmpy(_IQ(0.8660254),v->Ualpha); // 0.8660254 = sqrt(3)/2 29 | Vc = _IQmpy(_IQ(-0.5),v->Ubeta) - _IQmpy(_IQ(0.8660254),v->Ualpha); // 0.8660254 = sqrt(3)/2 30 | 31 | // 60 degree Sector determination 32 | if (Va>_IQ(0)) 33 | Sector = 1; 34 | if (Vb>_IQ(0)) 35 | Sector = Sector + 2; 36 | if (Vc>_IQ(0)) 37 | Sector = Sector + 4; 38 | 39 | // X,Y,Z (Va,Vb,Vc) calculations 40 | Va = v->Ubeta; // X = Va 41 | Vb = _IQmpy(_IQ(0.5),v->Ubeta) + _IQmpy(_IQ(0.8660254),v->Ualpha); // Y = Vb 42 | Vc = _IQmpy(_IQ(0.5),v->Ubeta) - _IQmpy(_IQ(0.8660254),v->Ualpha); // Z = Vc 43 | 44 | if (Sector==0) // Sector 0: this is special case for (Ualpha,Ubeta) = (0,0) 45 | { 46 | v->Ta = _IQ(0.5); 47 | v->Tb = _IQ(0.5); 48 | v->Tc = _IQ(0.5); 49 | } 50 | if (Sector==1) // Sector 1: t1=Z and t2=Y (abc ---> Tb,Ta,Tc) 51 | { 52 | t1 = Vc; 53 | t2 = Vb; 54 | v->Tb = _IQmpy(_IQ(0.5),(_IQ(1)-t1-t2)); // tbon = (1-t1-t2)/2 55 | v->Ta = v->Tb+t1; // taon = tbon+t1 56 | v->Tc = v->Ta+t2; // tcon = taon+t2 57 | } 58 | else if (Sector==2) // Sector 2: t1=Y and t2=-X (abc ---> Ta,Tc,Tb) 59 | { 60 | t1 = Vb; 61 | t2 = -Va; 62 | v->Ta = _IQmpy(_IQ(0.5),(_IQ(1)-t1-t2)); // taon = (1-t1-t2)/2 63 | v->Tc = v->Ta+t1; // tcon = taon+t1 64 | v->Tb = v->Tc+t2; // tbon = tcon+t2 65 | } 66 | else if (Sector==3) // Sector 3: t1=-Z and t2=X (abc ---> Ta,Tb,Tc) 67 | { 68 | t1 = -Vc; 69 | t2 = Va; 70 | v->Ta = _IQmpy(_IQ(0.5),(_IQ(1)-t1-t2)); // taon = (1-t1-t2)/2 71 | v->Tb = v->Ta+t1; // tbon = taon+t1 72 | v->Tc = v->Tb+t2; // tcon = tbon+t2 73 | } 74 | else if (Sector==4) // Sector 4: t1=-X and t2=Z (abc ---> Tc,Tb,Ta) 75 | { 76 | t1 = -Va; 77 | t2 = Vc; 78 | v->Tc = _IQmpy(_IQ(0.5),(_IQ(1)-t1-t2)); // tcon = (1-t1-t2)/2 79 | v->Tb = v->Tc+t1; // tbon = tcon+t1 80 | v->Ta = v->Tb+t2; // taon = tbon+t2 81 | } 82 | else if (Sector==5) // Sector 5: t1=X and t2=-Y (abc ---> Tb,Tc,Ta) 83 | { 84 | t1 = Va; 85 | t2 = -Vb; 86 | v->Tb = _IQmpy(_IQ(0.5),(_IQ(1)-t1-t2)); // tbon = (1-t1-t2)/2 87 | v->Tc = v->Tb+t1; // tcon = tbon+t1 88 | v->Ta = v->Tc+t2; // taon = tcon+t2 89 | } 90 | else if (Sector==6) // Sector 6: t1=-Y and t2=-Z (abc ---> Tc,Ta,Tb) 91 | { 92 | t1 = -Vb; 93 | t2 = -Vc; 94 | v->Tc = _IQmpy(_IQ(0.5),(_IQ(1)-t1-t2)); // tcon = (1-t1-t2)/2 95 | v->Ta = v->Tc+t1; // taon = tcon+t1 96 | v->Tb = v->Ta+t2; // tbon = taon+t2 97 | } 98 | 99 | // Convert the unsigned GLOBAL_Q format (ranged (0,1)) -> signed GLOBAL_Q format (ranged (-1,1)) 100 | v->Ta = _IQmpy(_IQ(2.0),(v->Ta-_IQ(0.5))); 101 | v->Tb = _IQmpy(_IQ(2.0),(v->Tb-_IQ(0.5))); 102 | v->Tc = _IQmpy(_IQ(2.0),(v->Tc-_IQ(0.5))); 103 | 104 | } 105 | 106 | 107 | -------------------------------------------------------------------------------- /PMSMfoc_DSP2812/src/vssver2.scc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ruanpei1010/3demo_DSP2812_MC/5370ef7d99c45387b6c1ee4a2b9e975a37492899/PMSMfoc_DSP2812/src/vssver2.scc -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # DSP2812_MC 2 | PMSM_FOC 3 | 280x 4 | 28035 5 | motor——0415 6 | --------------------------------------------------------------------------------