├── App
├── Test.c
└── keil
│ ├── DebugConfig
│ ├── OSEKNM_STM32F407ZGTx.dbgconf
│ └── Target_1_STM32F407ZGTx.dbgconf
│ ├── JLinkLog.txt
│ ├── JLinkSettings.ini
│ ├── Listings
│ ├── OSEKNM.map
│ └── startup_stm32f40_41xxx.lst
│ ├── OSEKNM.uvguix.Administrator
│ ├── OSEKNM.uvoptx
│ └── OSEKNM.uvprojx
├── Driver
├── Driver_Common.c
├── Driver_Common.h
├── Win7
│ ├── Win7.c
│ └── Win7.h
└── stm32f407
│ ├── CAN
│ ├── CAN.c
│ └── CAN.h
│ ├── CORE
│ ├── arm_common_tables.h
│ ├── arm_math.h
│ ├── core_cm4.h
│ ├── core_cmFunc.h
│ ├── core_cmInstr.h
│ ├── core_cmSimd.h
│ └── startup_stm32f40_41xxx.s
│ ├── FWLIB
│ ├── inc
│ │ ├── misc.h
│ │ ├── stm32f4xx_adc.h
│ │ ├── stm32f4xx_can.h
│ │ ├── stm32f4xx_cec.h
│ │ ├── stm32f4xx_crc.h
│ │ ├── stm32f4xx_cryp.h
│ │ ├── stm32f4xx_dac.h
│ │ ├── stm32f4xx_dbgmcu.h
│ │ ├── stm32f4xx_dcmi.h
│ │ ├── stm32f4xx_dfsdm.h
│ │ ├── stm32f4xx_dma.h
│ │ ├── stm32f4xx_dma2d.h
│ │ ├── stm32f4xx_dsi.h
│ │ ├── stm32f4xx_exti.h
│ │ ├── stm32f4xx_flash.h
│ │ ├── stm32f4xx_flash_ramfunc.h
│ │ ├── stm32f4xx_fmc.h
│ │ ├── stm32f4xx_fmpi2c.h
│ │ ├── stm32f4xx_fsmc.h
│ │ ├── stm32f4xx_gpio.h
│ │ ├── stm32f4xx_hash.h
│ │ ├── stm32f4xx_i2c.h
│ │ ├── stm32f4xx_iwdg.h
│ │ ├── stm32f4xx_lptim.h
│ │ ├── stm32f4xx_ltdc.h
│ │ ├── stm32f4xx_pwr.h
│ │ ├── stm32f4xx_qspi.h
│ │ ├── stm32f4xx_rcc.h
│ │ ├── stm32f4xx_rng.h
│ │ ├── stm32f4xx_rtc.h
│ │ ├── stm32f4xx_sai.h
│ │ ├── stm32f4xx_sdio.h
│ │ ├── stm32f4xx_spdifrx.h
│ │ ├── stm32f4xx_spi.h
│ │ ├── stm32f4xx_syscfg.h
│ │ ├── stm32f4xx_tim.h
│ │ ├── stm32f4xx_usart.h
│ │ └── stm32f4xx_wwdg.h
│ └── src
│ │ ├── misc.c
│ │ ├── stm32f4xx_adc.c
│ │ ├── stm32f4xx_can.c
│ │ ├── stm32f4xx_cec.c
│ │ ├── stm32f4xx_crc.c
│ │ ├── stm32f4xx_cryp.c
│ │ ├── stm32f4xx_cryp_aes.c
│ │ ├── stm32f4xx_cryp_des.c
│ │ ├── stm32f4xx_cryp_tdes.c
│ │ ├── stm32f4xx_dac.c
│ │ ├── stm32f4xx_dbgmcu.c
│ │ ├── stm32f4xx_dcmi.c
│ │ ├── stm32f4xx_dfsdm.c
│ │ ├── stm32f4xx_dma.c
│ │ ├── stm32f4xx_dma2d.c
│ │ ├── stm32f4xx_dsi.c
│ │ ├── stm32f4xx_exti.c
│ │ ├── stm32f4xx_flash.c
│ │ ├── stm32f4xx_flash_ramfunc.c
│ │ ├── stm32f4xx_fmc.c
│ │ ├── stm32f4xx_fmpi2c.c
│ │ ├── stm32f4xx_fsmc.c
│ │ ├── stm32f4xx_gpio.c
│ │ ├── stm32f4xx_hash.c
│ │ ├── stm32f4xx_hash_md5.c
│ │ ├── stm32f4xx_hash_sha1.c
│ │ ├── stm32f4xx_i2c.c
│ │ ├── stm32f4xx_iwdg.c
│ │ ├── stm32f4xx_lptim.c
│ │ ├── stm32f4xx_ltdc.c
│ │ ├── stm32f4xx_pwr.c
│ │ ├── stm32f4xx_qspi.c
│ │ ├── stm32f4xx_rcc.c
│ │ ├── stm32f4xx_rng.c
│ │ ├── stm32f4xx_rtc.c
│ │ ├── stm32f4xx_sai.c
│ │ ├── stm32f4xx_sdio.c
│ │ ├── stm32f4xx_spdifrx.c
│ │ ├── stm32f4xx_spi.c
│ │ ├── stm32f4xx_syscfg.c
│ │ ├── stm32f4xx_tim.c
│ │ ├── stm32f4xx_usart.c
│ │ └── stm32f4xx_wwdg.c
│ ├── LED0
│ ├── led.c
│ └── led.h
│ ├── SYSTEM
│ ├── delay.c
│ ├── delay.h
│ ├── sys.c
│ ├── sys.h
│ ├── usart.c
│ └── usart.h
│ ├── Timer
│ ├── Timer.c
│ └── Timer.h
│ └── USER
│ ├── stm32f4xx.h
│ ├── stm32f4xx_conf.h
│ ├── stm32f4xx_it.c
│ ├── stm32f4xx_it.h
│ ├── system_stm32f4xx.c
│ └── system_stm32f4xx.h
├── OsekNM_core
├── OsekNM.c
├── OsekNM.h
├── OsekNMServer.c
└── OsekNMServer.h
├── README.md
└── ReadMe.txt
/App/Test.c:
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https://raw.githubusercontent.com/ruiyanganqing/OSEK_NM/b1990204982716e0ec25cc783f6bdcbfa7097f62/App/Test.c
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/App/keil/DebugConfig/OSEKNM_STM32F407ZGTx.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32F405_415_407_417_427_437_429_439.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
4 | // refer to STM32F40x STM32F41x datasheets
5 | // refer to STM32F42x STM32F43x datasheets
6 |
7 | // <<< Use Configuration Wizard in Context Menu >>>
8 |
9 | // Debug MCU configuration register (DBGMCU_CR)
10 | // DBG_STANDBY Debug Standby Mode
11 | // DBG_STOP Debug Stop Mode
12 | // DBG_SLEEP Debug Sleep Mode
13 | //
14 | DbgMCU_CR = 0x00000007;
15 |
16 | // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
17 | // Reserved bits must be kept at reset value
18 | // DBG_CAN2_STOP CAN2 stopped when core is halted
19 | // DBG_CAN1_STOP CAN2 stopped when core is halted
20 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted
21 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted
22 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted
23 | // DBG_IWDG_STOP Independent watchdog stopped when core is halted
24 | // DBG_WWDG_STOP Window watchdog stopped when core is halted
25 | // DBG_RTC_STOP RTC stopped when core is halted
26 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
27 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
28 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
29 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
30 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
31 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
32 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
33 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
34 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
35 | //
36 | DbgMCU_APB1_Fz = 0x00000000;
37 |
38 | // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
39 | // Reserved bits must be kept at reset value
40 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted
41 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted
42 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted
43 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
44 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
45 | //
46 | DbgMCU_APB2_Fz = 0x00000000;
47 |
48 | // <<< end of configuration section >>>
--------------------------------------------------------------------------------
/App/keil/DebugConfig/Target_1_STM32F407ZGTx.dbgconf:
--------------------------------------------------------------------------------
1 | // File: STM32F405_415_407_417_427_437_429_439.dbgconf
2 | // Version: 1.0.0
3 | // Note: refer to STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 reference manual (RM0090)
4 | // refer to STM32F40x STM32F41x datasheets
5 | // refer to STM32F42x STM32F43x datasheets
6 |
7 | // <<< Use Configuration Wizard in Context Menu >>>
8 |
9 | // Debug MCU configuration register (DBGMCU_CR)
10 | // DBG_STANDBY Debug Standby Mode
11 | // DBG_STOP Debug Stop Mode
12 | // DBG_SLEEP Debug Sleep Mode
13 | //
14 | DbgMCU_CR = 0x00000007;
15 |
16 | // Debug MCU APB1 freeze register (DBGMCU_APB1_FZ)
17 | // Reserved bits must be kept at reset value
18 | // DBG_CAN2_STOP CAN2 stopped when core is halted
19 | // DBG_CAN1_STOP CAN2 stopped when core is halted
20 | // DBG_I2C3_SMBUS_TIMEOUT I2C3 SMBUS timeout mode stopped when core is halted
21 | // DBG_I2C2_SMBUS_TIMEOUT I2C2 SMBUS timeout mode stopped when core is halted
22 | // DBG_I2C1_SMBUS_TIMEOUT I2C1 SMBUS timeout mode stopped when core is halted
23 | // DBG_IWDG_STOP Independent watchdog stopped when core is halted
24 | // DBG_WWDG_STOP Window watchdog stopped when core is halted
25 | // DBG_RTC_STOP RTC stopped when core is halted
26 | // DBG_TIM14_STOP TIM14 counter stopped when core is halted
27 | // DBG_TIM13_STOP TIM13 counter stopped when core is halted
28 | // DBG_TIM12_STOP TIM12 counter stopped when core is halted
29 | // DBG_TIM7_STOP TIM7 counter stopped when core is halted
30 | // DBG_TIM6_STOP TIM6 counter stopped when core is halted
31 | // DBG_TIM5_STOP TIM5 counter stopped when core is halted
32 | // DBG_TIM4_STOP TIM4 counter stopped when core is halted
33 | // DBG_TIM3_STOP TIM3 counter stopped when core is halted
34 | // DBG_TIM2_STOP TIM2 counter stopped when core is halted
35 | //
36 | DbgMCU_APB1_Fz = 0x00000000;
37 |
38 | // Debug MCU APB2 freeze register (DBGMCU_APB2_FZ)
39 | // Reserved bits must be kept at reset value
40 | // DBG_TIM11_STOP TIM11 counter stopped when core is halted
41 | // DBG_TIM10_STOP TIM10 counter stopped when core is halted
42 | // DBG_TIM9_STOP TIM9 counter stopped when core is halted
43 | // DBG_TIM8_STOP TIM8 counter stopped when core is halted
44 | // DBG_TIM1_STOP TIM1 counter stopped when core is halted
45 | //
46 | DbgMCU_APB2_Fz = 0x00000000;
47 |
48 | // <<< end of configuration section >>>
--------------------------------------------------------------------------------
/App/keil/JLinkSettings.ini:
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1 | [BREAKPOINTS]
2 | ForceImpTypeAny = 0
3 | ShowInfoWin = 1
4 | EnableFlashBP = 2
5 | BPDuringExecution = 0
6 | [CFI]
7 | CFISize = 0x00
8 | CFIAddr = 0x00
9 | [CPU]
10 | MonModeVTableAddr = 0xFFFFFFFF
11 | MonModeDebug = 0
12 | MaxNumAPs = 0
13 | LowPowerHandlingMode = 0
14 | OverrideMemMap = 0
15 | AllowSimulation = 1
16 | ScriptFile=""
17 | [FLASH]
18 | CacheExcludeSize = 0x00
19 | CacheExcludeAddr = 0x00
20 | MinNumBytesFlashDL = 0
21 | SkipProgOnCRCMatch = 1
22 | VerifyDownload = 1
23 | AllowCaching = 1
24 | EnableFlashDL = 2
25 | Override = 0
26 | Device="ARM7"
27 | [GENERAL]
28 | WorkRAMSize = 0x00
29 | WorkRAMAddr = 0x00
30 | RAMUsageLimit = 0x00
31 | [SWO]
32 | SWOLogFile=""
33 | [MEM]
34 | RdOverrideOrMask = 0x00
35 | RdOverrideAndMask = 0xFFFFFFFF
36 | RdOverrideAddr = 0xFFFFFFFF
37 | WrOverrideOrMask = 0x00
38 | WrOverrideAndMask = 0xFFFFFFFF
39 | WrOverrideAddr = 0xFFFFFFFF
40 |
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/Driver/Driver_Common.c:
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/Driver/Driver_Common.h:
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https://raw.githubusercontent.com/ruiyanganqing/OSEK_NM/b1990204982716e0ec25cc783f6bdcbfa7097f62/Driver/Driver_Common.h
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/Driver/Win7/Win7.c:
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https://raw.githubusercontent.com/ruiyanganqing/OSEK_NM/b1990204982716e0ec25cc783f6bdcbfa7097f62/Driver/Win7/Win7.c
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/Driver/Win7/Win7.h:
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https://raw.githubusercontent.com/ruiyanganqing/OSEK_NM/b1990204982716e0ec25cc783f6bdcbfa7097f62/Driver/Win7/Win7.h
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/Driver/stm32f407/CAN/CAN.c:
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https://raw.githubusercontent.com/ruiyanganqing/OSEK_NM/b1990204982716e0ec25cc783f6bdcbfa7097f62/Driver/stm32f407/CAN/CAN.c
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/Driver/stm32f407/CAN/CAN.h:
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1 | #ifndef CAN_H
2 | #define CAN_H
3 | #include "OSEKNM.h"
4 | #include "Driver_Common.h"
5 | int STM32_TX_CAN_Transmit(NMPDU_t* NMPDU);
6 | void STM32_CAN1_Init(void);
7 | #endif
8 |
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/Driver/stm32f407/CORE/arm_common_tables.h:
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1 | /* ----------------------------------------------------------------------
2 | * Copyright (C) 2010-2014 ARM Limited. All rights reserved.
3 | *
4 | * $Date: 19. March 2015
5 | * $Revision: V.1.4.5
6 | *
7 | * Project: CMSIS DSP Library
8 | * Title: arm_common_tables.h
9 | *
10 | * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
11 | *
12 | * Target Processor: Cortex-M4/Cortex-M3
13 | *
14 | * Redistribution and use in source and binary forms, with or without
15 | * modification, are permitted provided that the following conditions
16 | * are met:
17 | * - Redistributions of source code must retain the above copyright
18 | * notice, this list of conditions and the following disclaimer.
19 | * - Redistributions in binary form must reproduce the above copyright
20 | * notice, this list of conditions and the following disclaimer in
21 | * the documentation and/or other materials provided with the
22 | * distribution.
23 | * - Neither the name of ARM LIMITED nor the names of its contributors
24 | * may be used to endorse or promote products derived from this
25 | * software without specific prior written permission.
26 | *
27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 | * POSSIBILITY OF SUCH DAMAGE.
39 | * -------------------------------------------------------------------- */
40 |
41 | #ifndef _ARM_COMMON_TABLES_H
42 | #define _ARM_COMMON_TABLES_H
43 |
44 | #include "arm_math.h"
45 |
46 | extern const uint16_t armBitRevTable[1024];
47 | extern const q15_t armRecipTableQ15[64];
48 | extern const q31_t armRecipTableQ31[64];
49 | //extern const q31_t realCoefAQ31[1024];
50 | //extern const q31_t realCoefBQ31[1024];
51 | extern const float32_t twiddleCoef_16[32];
52 | extern const float32_t twiddleCoef_32[64];
53 | extern const float32_t twiddleCoef_64[128];
54 | extern const float32_t twiddleCoef_128[256];
55 | extern const float32_t twiddleCoef_256[512];
56 | extern const float32_t twiddleCoef_512[1024];
57 | extern const float32_t twiddleCoef_1024[2048];
58 | extern const float32_t twiddleCoef_2048[4096];
59 | extern const float32_t twiddleCoef_4096[8192];
60 | #define twiddleCoef twiddleCoef_4096
61 | extern const q31_t twiddleCoef_16_q31[24];
62 | extern const q31_t twiddleCoef_32_q31[48];
63 | extern const q31_t twiddleCoef_64_q31[96];
64 | extern const q31_t twiddleCoef_128_q31[192];
65 | extern const q31_t twiddleCoef_256_q31[384];
66 | extern const q31_t twiddleCoef_512_q31[768];
67 | extern const q31_t twiddleCoef_1024_q31[1536];
68 | extern const q31_t twiddleCoef_2048_q31[3072];
69 | extern const q31_t twiddleCoef_4096_q31[6144];
70 | extern const q15_t twiddleCoef_16_q15[24];
71 | extern const q15_t twiddleCoef_32_q15[48];
72 | extern const q15_t twiddleCoef_64_q15[96];
73 | extern const q15_t twiddleCoef_128_q15[192];
74 | extern const q15_t twiddleCoef_256_q15[384];
75 | extern const q15_t twiddleCoef_512_q15[768];
76 | extern const q15_t twiddleCoef_1024_q15[1536];
77 | extern const q15_t twiddleCoef_2048_q15[3072];
78 | extern const q15_t twiddleCoef_4096_q15[6144];
79 | extern const float32_t twiddleCoef_rfft_32[32];
80 | extern const float32_t twiddleCoef_rfft_64[64];
81 | extern const float32_t twiddleCoef_rfft_128[128];
82 | extern const float32_t twiddleCoef_rfft_256[256];
83 | extern const float32_t twiddleCoef_rfft_512[512];
84 | extern const float32_t twiddleCoef_rfft_1024[1024];
85 | extern const float32_t twiddleCoef_rfft_2048[2048];
86 | extern const float32_t twiddleCoef_rfft_4096[4096];
87 |
88 |
89 | /* floating-point bit reversal tables */
90 | #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
91 | #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
92 | #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
93 | #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
94 | #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
95 | #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
96 | #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
97 | #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
98 | #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
99 |
100 | extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
101 | extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
102 | extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
103 | extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
104 | extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
105 | extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
106 | extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
107 | extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
108 | extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
109 |
110 | /* fixed-point bit reversal tables */
111 | #define ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH ((uint16_t)12 )
112 | #define ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH ((uint16_t)24 )
113 | #define ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH ((uint16_t)56 )
114 | #define ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH ((uint16_t)112 )
115 | #define ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH ((uint16_t)240 )
116 | #define ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH ((uint16_t)480 )
117 | #define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992 )
118 | #define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
119 | #define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
120 |
121 | extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED___16_TABLE_LENGTH];
122 | extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED___32_TABLE_LENGTH];
123 | extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED___64_TABLE_LENGTH];
124 | extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED__128_TABLE_LENGTH];
125 | extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED__256_TABLE_LENGTH];
126 | extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED__512_TABLE_LENGTH];
127 | extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
128 | extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
129 | extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
130 |
131 | /* Tables for Fast Math Sine and Cosine */
132 | extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
133 | extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
134 | extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
135 |
136 | #endif /* ARM_COMMON_TABLES_H */
137 |
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/Driver/stm32f407/FWLIB/inc/misc.h:
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1 | /**
2 | ******************************************************************************
3 | * @file misc.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the miscellaneous
8 | * firmware library functions (add-on to CMSIS functions).
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __MISC_H
31 | #define __MISC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup MISC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief NVIC Init Structure definition
52 | */
53 |
54 | typedef struct
55 | {
56 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
57 | This parameter can be an enumerator of @ref IRQn_Type
58 | enumeration (For the complete STM32 Devices IRQ Channels
59 | list, please refer to stm32f4xx.h file) */
60 |
61 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
62 | specified in NVIC_IRQChannel. This parameter can be a value
63 | between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
64 | A lower priority value indicates a higher priority */
65 |
66 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
67 | in NVIC_IRQChannel. This parameter can be a value
68 | between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
69 | A lower priority value indicates a higher priority */
70 |
71 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
72 | will be enabled or disabled.
73 | This parameter can be set either to ENABLE or DISABLE */
74 | } NVIC_InitTypeDef;
75 |
76 | /* Exported constants --------------------------------------------------------*/
77 |
78 | /** @defgroup MISC_Exported_Constants
79 | * @{
80 | */
81 |
82 | /** @defgroup MISC_Vector_Table_Base
83 | * @{
84 | */
85 |
86 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000)
87 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
88 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
89 | ((VECTTAB) == NVIC_VectTab_FLASH))
90 | /**
91 | * @}
92 | */
93 |
94 | /** @defgroup MISC_System_Low_Power
95 | * @{
96 | */
97 |
98 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10)
99 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
100 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
101 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
102 | ((LP) == NVIC_LP_SLEEPDEEP) || \
103 | ((LP) == NVIC_LP_SLEEPONEXIT))
104 | /**
105 | * @}
106 | */
107 |
108 | /** @defgroup MISC_Preemption_Priority_Group
109 | * @{
110 | */
111 |
112 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
113 | 4 bits for subpriority */
114 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
115 | 3 bits for subpriority */
116 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
117 | 2 bits for subpriority */
118 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
119 | 1 bits for subpriority */
120 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
121 | 0 bits for subpriority */
122 |
123 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
124 | ((GROUP) == NVIC_PriorityGroup_1) || \
125 | ((GROUP) == NVIC_PriorityGroup_2) || \
126 | ((GROUP) == NVIC_PriorityGroup_3) || \
127 | ((GROUP) == NVIC_PriorityGroup_4))
128 |
129 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
130 |
131 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
132 |
133 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
134 |
135 | /**
136 | * @}
137 | */
138 |
139 | /** @defgroup MISC_SysTick_clock_source
140 | * @{
141 | */
142 |
143 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
144 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
145 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
146 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
147 | /**
148 | * @}
149 | */
150 |
151 | /**
152 | * @}
153 | */
154 |
155 | /* Exported macro ------------------------------------------------------------*/
156 | /* Exported functions --------------------------------------------------------*/
157 |
158 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
159 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
160 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
161 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
162 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
163 |
164 | #ifdef __cplusplus
165 | }
166 | #endif
167 |
168 | #endif /* __MISC_H */
169 |
170 | /**
171 | * @}
172 | */
173 |
174 | /**
175 | * @}
176 | */
177 |
178 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
179 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_crc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_crc.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the CRC firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_CRC_H
31 | #define __STM32F4xx_CRC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup CRC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup CRC_Exported_Constants
52 | * @{
53 | */
54 |
55 | /**
56 | * @}
57 | */
58 |
59 | /* Exported macro ------------------------------------------------------------*/
60 | /* Exported functions --------------------------------------------------------*/
61 |
62 | void CRC_ResetDR(void);
63 | uint32_t CRC_CalcCRC(uint32_t Data);
64 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
65 | uint32_t CRC_GetCRC(void);
66 | void CRC_SetIDRegister(uint8_t IDValue);
67 | uint8_t CRC_GetIDRegister(void);
68 |
69 | #ifdef __cplusplus
70 | }
71 | #endif
72 |
73 | #endif /* __STM32F4xx_CRC_H */
74 |
75 | /**
76 | * @}
77 | */
78 |
79 | /**
80 | * @}
81 | */
82 |
83 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
84 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_dbgmcu.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_dbgmcu.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F4xx_DBGMCU_H
30 | #define __STM32F4xx_DBGMCU_H
31 |
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 |
36 | /* Includes ------------------------------------------------------------------*/
37 | #include "stm32f4xx.h"
38 |
39 | /** @addtogroup STM32F4xx_StdPeriph_Driver
40 | * @{
41 | */
42 |
43 | /** @addtogroup DBGMCU
44 | * @{
45 | */
46 |
47 | /* Exported types ------------------------------------------------------------*/
48 | /* Exported constants --------------------------------------------------------*/
49 |
50 | /** @defgroup DBGMCU_Exported_Constants
51 | * @{
52 | */
53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001)
54 | #define DBGMCU_STOP ((uint32_t)0x00000002)
55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004)
56 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
57 |
58 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
59 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
60 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
61 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
62 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
63 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
64 | #define DBGMCU_TIM12_STOP ((uint32_t)0x00000040)
65 | #define DBGMCU_TIM13_STOP ((uint32_t)0x00000080)
66 | #define DBGMCU_TIM14_STOP ((uint32_t)0x00000100)
67 | #define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
68 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
69 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
70 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
71 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
72 | #define DBGMCU_I2C3_SMBUS_TIMEOUT ((uint32_t)0x00800000)
73 | #define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
74 | #define DBGMCU_CAN2_STOP ((uint32_t)0x04000000)
75 | #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
76 |
77 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
78 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
79 | #define DBGMCU_TIM9_STOP ((uint32_t)0x00010000)
80 | #define DBGMCU_TIM10_STOP ((uint32_t)0x00020000)
81 | #define DBGMCU_TIM11_STOP ((uint32_t)0x00040000)
82 | #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
83 | /**
84 | * @}
85 | */
86 |
87 | /* Exported macro ------------------------------------------------------------*/
88 | /* Exported functions --------------------------------------------------------*/
89 | uint32_t DBGMCU_GetREVID(void);
90 | uint32_t DBGMCU_GetDEVID(void);
91 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
92 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
93 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
94 |
95 | #ifdef __cplusplus
96 | }
97 | #endif
98 |
99 | #endif /* __STM32F4xx_DBGMCU_H */
100 |
101 | /**
102 | * @}
103 | */
104 |
105 | /**
106 | * @}
107 | */
108 |
109 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
110 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_exti.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_exti.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the EXTI firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_EXTI_H
31 | #define __STM32F4xx_EXTI_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup EXTI
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief EXTI mode enumeration
52 | */
53 |
54 | typedef enum
55 | {
56 | EXTI_Mode_Interrupt = 0x00,
57 | EXTI_Mode_Event = 0x04
58 | }EXTIMode_TypeDef;
59 |
60 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
61 |
62 | /**
63 | * @brief EXTI Trigger enumeration
64 | */
65 |
66 | typedef enum
67 | {
68 | EXTI_Trigger_Rising = 0x08,
69 | EXTI_Trigger_Falling = 0x0C,
70 | EXTI_Trigger_Rising_Falling = 0x10
71 | }EXTITrigger_TypeDef;
72 |
73 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
74 | ((TRIGGER) == EXTI_Trigger_Falling) || \
75 | ((TRIGGER) == EXTI_Trigger_Rising_Falling))
76 | /**
77 | * @brief EXTI Init Structure definition
78 | */
79 |
80 | typedef struct
81 | {
82 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
83 | This parameter can be any combination value of @ref EXTI_Lines */
84 |
85 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
86 | This parameter can be a value of @ref EXTIMode_TypeDef */
87 |
88 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
89 | This parameter can be a value of @ref EXTITrigger_TypeDef */
90 |
91 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
92 | This parameter can be set either to ENABLE or DISABLE */
93 | }EXTI_InitTypeDef;
94 |
95 | /* Exported constants --------------------------------------------------------*/
96 |
97 | /** @defgroup EXTI_Exported_Constants
98 | * @{
99 | */
100 |
101 | /** @defgroup EXTI_Lines
102 | * @{
103 | */
104 |
105 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */
106 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */
107 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */
108 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */
109 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */
110 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */
111 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */
112 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */
113 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */
114 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */
115 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */
116 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */
117 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */
118 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */
119 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */
120 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */
121 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */
122 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */
123 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */
124 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
125 | #define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event */
126 | #define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */
127 | #define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22 Connected to the RTC Wakeup event */
128 | #define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23 Connected to the LPTIM Wakeup event */
129 |
130 |
131 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
132 |
133 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
134 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
135 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
136 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
137 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
138 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
139 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
140 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
141 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
142 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
143 | ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
144 | ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
145 |
146 | /**
147 | * @}
148 | */
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /* Exported macro ------------------------------------------------------------*/
155 | /* Exported functions --------------------------------------------------------*/
156 |
157 | /* Function used to set the EXTI configuration to the default reset state *****/
158 | void EXTI_DeInit(void);
159 |
160 | /* Initialization and Configuration functions *********************************/
161 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
162 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
163 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
164 |
165 | /* Interrupts and flags management functions **********************************/
166 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
167 | void EXTI_ClearFlag(uint32_t EXTI_Line);
168 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
169 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
170 |
171 | #ifdef __cplusplus
172 | }
173 | #endif
174 |
175 | #endif /* __STM32F4xx_EXTI_H */
176 |
177 | /**
178 | * @}
179 | */
180 |
181 | /**
182 | * @}
183 | */
184 |
185 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
186 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_flash_ramfunc.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_flash_ramfunc.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief Header file of FLASH RAMFUNC driver.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_FLASH_RAMFUNC_H
31 | #define __STM32F4xx_FLASH_RAMFUNC_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup FLASH RAMFUNC
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Private define ------------------------------------------------------------*/
50 | /**
51 | * @brief __RAM_FUNC definition
52 | */
53 | #if defined ( __CC_ARM )
54 | /* ARM Compiler
55 | ------------
56 | RAM functions are defined using the toolchain options.
57 | Functions that are executed in RAM should reside in a separate source module.
58 | Using the 'Options for File' dialog you can simply change the 'Code / Const'
59 | area of a module to a memory space in physical RAM.
60 | Available memory areas are declared in the 'Target' tab of the 'Options for Target'
61 | dialog.
62 | */
63 | #define __RAM_FUNC void
64 |
65 | #elif defined ( __ICCARM__ )
66 | /* ICCARM Compiler
67 | ---------------
68 | RAM functions are defined using a specific toolchain keyword "__ramfunc".
69 | */
70 | #define __RAM_FUNC __ramfunc void
71 |
72 | #elif defined ( __GNUC__ )
73 | /* GNU Compiler
74 | ------------
75 | RAM functions are defined using a specific toolchain attribute
76 | "__attribute__((section(".RamFunc")))".
77 | */
78 | #define __RAM_FUNC void __attribute__((section(".RamFunc")))
79 |
80 | #endif
81 | /* Exported constants --------------------------------------------------------*/
82 | /* Exported macro ------------------------------------------------------------*/
83 | /* Exported functions --------------------------------------------------------*/
84 | __RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState);
85 | __RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState);
86 |
87 |
88 | #ifdef __cplusplus
89 | }
90 | #endif
91 |
92 | #endif /* __STM32F4xx_FLASH_RAMFUNC_H */
93 |
94 | /**
95 | * @}
96 | */
97 |
98 | /**
99 | * @}
100 | */
101 |
102 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
103 |
104 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_hash.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hash.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the HASH
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_HASH_H
31 | #define __STM32F4xx_HASH_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup HASH
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 |
50 | /**
51 | * @brief HASH Init structure definition
52 | */
53 | typedef struct
54 | {
55 | uint32_t HASH_AlgoSelection; /*!< SHA-1, SHA-224, SHA-256 or MD5. This parameter
56 | can be a value of @ref HASH_Algo_Selection */
57 | uint32_t HASH_AlgoMode; /*!< HASH or HMAC. This parameter can be a value
58 | of @ref HASH_processor_Algorithm_Mode */
59 | uint32_t HASH_DataType; /*!< 32-bit data, 16-bit data, 8-bit data or
60 | bit string. This parameter can be a value of
61 | @ref HASH_Data_Type */
62 | uint32_t HASH_HMACKeyType; /*!< HMAC Short key or HMAC Long Key. This parameter
63 | can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
64 | }HASH_InitTypeDef;
65 |
66 | /**
67 | * @brief HASH message digest result structure definition
68 | */
69 | typedef struct
70 | {
71 | uint32_t Data[8]; /*!< Message digest result : 8x 32bit wors for SHA-256,
72 | 7x 32bit wors for SHA-224,
73 | 5x 32bit words for SHA-1 or
74 | 4x 32bit words for MD5 */
75 | } HASH_MsgDigest;
76 |
77 | /**
78 | * @brief HASH context swapping structure definition
79 | */
80 | typedef struct
81 | {
82 | uint32_t HASH_IMR;
83 | uint32_t HASH_STR;
84 | uint32_t HASH_CR;
85 | uint32_t HASH_CSR[54];
86 | }HASH_Context;
87 |
88 | /* Exported constants --------------------------------------------------------*/
89 |
90 | /** @defgroup HASH_Exported_Constants
91 | * @{
92 | */
93 |
94 | /** @defgroup HASH_Algo_Selection
95 | * @{
96 | */
97 | #define HASH_AlgoSelection_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
98 | #define HASH_AlgoSelection_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
99 | #define HASH_AlgoSelection_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
100 | #define HASH_AlgoSelection_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
101 |
102 | #define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
103 | ((ALGOSELECTION) == HASH_AlgoSelection_SHA224) || \
104 | ((ALGOSELECTION) == HASH_AlgoSelection_SHA256) || \
105 | ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
106 | /**
107 | * @}
108 | */
109 |
110 | /** @defgroup HASH_processor_Algorithm_Mode
111 | * @{
112 | */
113 | #define HASH_AlgoMode_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
114 | #define HASH_AlgoMode_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
115 |
116 | #define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
117 | ((ALGOMODE) == HASH_AlgoMode_HMAC))
118 | /**
119 | * @}
120 | */
121 |
122 | /** @defgroup HASH_Data_Type
123 | * @{
124 | */
125 | #define HASH_DataType_32b ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
126 | #define HASH_DataType_16b HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
127 | #define HASH_DataType_8b HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
128 | #define HASH_DataType_1b HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
129 |
130 | #define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
131 | ((DATATYPE) == HASH_DataType_16b)|| \
132 | ((DATATYPE) == HASH_DataType_8b) || \
133 | ((DATATYPE) == HASH_DataType_1b))
134 | /**
135 | * @}
136 | */
137 |
138 | /** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode
139 | * @{
140 | */
141 | #define HASH_HMACKeyType_ShortKey ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
142 | #define HASH_HMACKeyType_LongKey HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
143 |
144 | #define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
145 | ((KEYTYPE) == HASH_HMACKeyType_LongKey))
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup Number_of_valid_bits_in_last_word_of_the_message
151 | * @{
152 | */
153 | #define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
154 |
155 | /**
156 | * @}
157 | */
158 |
159 | /** @defgroup HASH_interrupts_definition
160 | * @{
161 | */
162 | #define HASH_IT_DINI HASH_IMR_DINIM /*!< A new block can be entered into the input buffer (DIN) */
163 | #define HASH_IT_DCI HASH_IMR_DCIM /*!< Digest calculation complete */
164 |
165 | #define IS_HASH_IT(IT) ((((IT) & (uint32_t)0xFFFFFFFC) == 0x00000000) && ((IT) != 0x00000000))
166 | #define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
167 |
168 | /**
169 | * @}
170 | */
171 |
172 | /** @defgroup HASH_flags_definition
173 | * @{
174 | */
175 | #define HASH_FLAG_DINIS HASH_SR_DINIS /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer */
176 | #define HASH_FLAG_DCIS HASH_SR_DCIS /*!< Digest calculation complete */
177 | #define HASH_FLAG_DMAS HASH_SR_DMAS /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
178 | #define HASH_FLAG_BUSY HASH_SR_BUSY /*!< The hash core is Busy : processing a block of data */
179 | #define HASH_FLAG_DINNE HASH_CR_DINNE /*!< DIN not empty : The input buffer contains at least one word of data */
180 |
181 | #define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
182 | ((FLAG) == HASH_FLAG_DCIS) || \
183 | ((FLAG) == HASH_FLAG_DMAS) || \
184 | ((FLAG) == HASH_FLAG_BUSY) || \
185 | ((FLAG) == HASH_FLAG_DINNE))
186 |
187 | #define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
188 | ((FLAG) == HASH_FLAG_DCIS))
189 |
190 | /**
191 | * @}
192 | */
193 |
194 | /**
195 | * @}
196 | */
197 |
198 | /* Exported macro ------------------------------------------------------------*/
199 | /* Exported functions --------------------------------------------------------*/
200 |
201 | /* Function used to set the HASH configuration to the default reset state ****/
202 | void HASH_DeInit(void);
203 |
204 | /* HASH Configuration function ************************************************/
205 | void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
206 | void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
207 | void HASH_Reset(void);
208 |
209 | /* HASH Message Digest generation functions ***********************************/
210 | void HASH_DataIn(uint32_t Data);
211 | uint8_t HASH_GetInFIFOWordsNbr(void);
212 | void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
213 | void HASH_StartDigest(void);
214 | void HASH_AutoStartDigest(FunctionalState NewState);
215 | void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
216 |
217 | /* HASH Context swapping functions ********************************************/
218 | void HASH_SaveContext(HASH_Context* HASH_ContextSave);
219 | void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
220 |
221 | /* HASH DMA interface function ************************************************/
222 | void HASH_DMACmd(FunctionalState NewState);
223 |
224 | /* HASH Interrupts and flags management functions *****************************/
225 | void HASH_ITConfig(uint32_t HASH_IT, FunctionalState NewState);
226 | FlagStatus HASH_GetFlagStatus(uint32_t HASH_FLAG);
227 | void HASH_ClearFlag(uint32_t HASH_FLAG);
228 | ITStatus HASH_GetITStatus(uint32_t HASH_IT);
229 | void HASH_ClearITPendingBit(uint32_t HASH_IT);
230 |
231 | /* High Level SHA1 functions **************************************************/
232 | ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
233 | ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
234 | uint8_t *Input, uint32_t Ilen,
235 | uint8_t Output[20]);
236 |
237 | /* High Level MD5 functions ***************************************************/
238 | ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
239 | ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
240 | uint8_t *Input, uint32_t Ilen,
241 | uint8_t Output[16]);
242 |
243 | #ifdef __cplusplus
244 | }
245 | #endif
246 |
247 | #endif /*__STM32F4xx_HASH_H */
248 |
249 | /**
250 | * @}
251 | */
252 |
253 | /**
254 | * @}
255 | */
256 |
257 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
258 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_iwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_iwdg.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the IWDG
8 | * firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_IWDG_H
31 | #define __STM32F4xx_IWDG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup IWDG
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup IWDG_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup IWDG_WriteAccess
56 | * @{
57 | */
58 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
59 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
60 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
61 | ((ACCESS) == IWDG_WriteAccess_Disable))
62 | /**
63 | * @}
64 | */
65 |
66 | /** @defgroup IWDG_prescaler
67 | * @{
68 | */
69 | #define IWDG_Prescaler_4 ((uint8_t)0x00)
70 | #define IWDG_Prescaler_8 ((uint8_t)0x01)
71 | #define IWDG_Prescaler_16 ((uint8_t)0x02)
72 | #define IWDG_Prescaler_32 ((uint8_t)0x03)
73 | #define IWDG_Prescaler_64 ((uint8_t)0x04)
74 | #define IWDG_Prescaler_128 ((uint8_t)0x05)
75 | #define IWDG_Prescaler_256 ((uint8_t)0x06)
76 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
77 | ((PRESCALER) == IWDG_Prescaler_8) || \
78 | ((PRESCALER) == IWDG_Prescaler_16) || \
79 | ((PRESCALER) == IWDG_Prescaler_32) || \
80 | ((PRESCALER) == IWDG_Prescaler_64) || \
81 | ((PRESCALER) == IWDG_Prescaler_128)|| \
82 | ((PRESCALER) == IWDG_Prescaler_256))
83 | /**
84 | * @}
85 | */
86 |
87 | /** @defgroup IWDG_Flag
88 | * @{
89 | */
90 | #define IWDG_FLAG_PVU ((uint16_t)0x0001)
91 | #define IWDG_FLAG_RVU ((uint16_t)0x0002)
92 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
93 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
94 | /**
95 | * @}
96 | */
97 |
98 | /**
99 | * @}
100 | */
101 |
102 | /* Exported macro ------------------------------------------------------------*/
103 | /* Exported functions --------------------------------------------------------*/
104 |
105 | /* Prescaler and Counter configuration functions ******************************/
106 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
107 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
108 | void IWDG_SetReload(uint16_t Reload);
109 | void IWDG_ReloadCounter(void);
110 |
111 | /* IWDG activation function ***************************************************/
112 | void IWDG_Enable(void);
113 |
114 | /* Flag management function ***************************************************/
115 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
116 |
117 | #ifdef __cplusplus
118 | }
119 | #endif
120 |
121 | #endif /* __STM32F4xx_IWDG_H */
122 |
123 | /**
124 | * @}
125 | */
126 |
127 | /**
128 | * @}
129 | */
130 |
131 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
132 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_pwr.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_pwr.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the PWR firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_PWR_H
31 | #define __STM32F4xx_PWR_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup PWR
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup PWR_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup PWR_PVD_detection_level
56 | * @{
57 | */
58 | #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
59 | #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
60 | #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
61 | #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
62 | #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
63 | #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
64 | #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
65 | #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
66 |
67 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
68 | ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
69 | ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
70 | ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
71 | /**
72 | * @}
73 | */
74 |
75 |
76 | /** @defgroup PWR_Regulator_state_in_STOP_mode
77 | * @{
78 | */
79 | #define PWR_MainRegulator_ON ((uint32_t)0x00000000)
80 | #define PWR_LowPowerRegulator_ON PWR_CR_LPDS
81 |
82 | /* --- PWR_Legacy ---*/
83 | #define PWR_Regulator_ON PWR_MainRegulator_ON
84 | #define PWR_Regulator_LowPower PWR_LowPowerRegulator_ON
85 |
86 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MainRegulator_ON) || \
87 | ((REGULATOR) == PWR_LowPowerRegulator_ON))
88 |
89 | /**
90 | * @}
91 | */
92 |
93 | /** @defgroup PWR_Regulator_state_in_UnderDrive_mode
94 | * @{
95 | */
96 | #define PWR_MainRegulator_UnderDrive_ON PWR_CR_MRUDS
97 | #define PWR_LowPowerRegulator_UnderDrive_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
98 |
99 | #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MainRegulator_UnderDrive_ON) || \
100 | ((REGULATOR) == PWR_LowPowerRegulator_UnderDrive_ON))
101 |
102 | /**
103 | * @}
104 | */
105 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F446xx)
106 | /** @defgroup PWR_Wake_Up_Pin
107 | * @{
108 | */
109 | #define PWR_WakeUp_Pin1 ((uint32_t)0x00)
110 | #define PWR_WakeUp_Pin2 ((uint32_t)0x01)
111 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx)
112 | #define PWR_WakeUp_Pin3 ((uint32_t)0x02)
113 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx */
114 |
115 | #if defined(STM32F446xx)
116 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || \
117 | ((PIN) == PWR_WakeUp_Pin2))
118 | #else /* STM32F410xx || STM32F412xG */
119 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUp_Pin1) || ((PIN) == PWR_WakeUp_Pin2) || \
120 | ((PIN) == PWR_WakeUp_Pin3))
121 | #endif /* STM32F446xx */
122 | /**
123 | * @}
124 | */
125 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
126 |
127 | /** @defgroup PWR_STOP_mode_entry
128 | * @{
129 | */
130 | #define PWR_STOPEntry_WFI ((uint8_t)0x01)
131 | #define PWR_STOPEntry_WFE ((uint8_t)0x02)
132 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
133 | /**
134 | * @}
135 | */
136 |
137 | /** @defgroup PWR_Regulator_Voltage_Scale
138 | * @{
139 | */
140 | #define PWR_Regulator_Voltage_Scale1 ((uint32_t)0x0000C000)
141 | #define PWR_Regulator_Voltage_Scale2 ((uint32_t)0x00008000)
142 | #define PWR_Regulator_Voltage_Scale3 ((uint32_t)0x00004000)
143 | #define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_Regulator_Voltage_Scale1) || \
144 | ((VOLTAGE) == PWR_Regulator_Voltage_Scale2) || \
145 | ((VOLTAGE) == PWR_Regulator_Voltage_Scale3))
146 | /**
147 | * @}
148 | */
149 |
150 | /** @defgroup PWR_Flag
151 | * @{
152 | */
153 | #define PWR_FLAG_WU PWR_CSR_WUF
154 | #define PWR_FLAG_SB PWR_CSR_SBF
155 | #define PWR_FLAG_PVDO PWR_CSR_PVDO
156 | #define PWR_FLAG_BRR PWR_CSR_BRR
157 | #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
158 | #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
159 | #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
160 | #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
161 |
162 | /* --- FLAG Legacy ---*/
163 | #define PWR_FLAG_REGRDY PWR_FLAG_VOSRDY
164 |
165 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
166 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
167 | ((FLAG) == PWR_FLAG_VOSRDY) || ((FLAG) == PWR_FLAG_ODRDY) || \
168 | ((FLAG) == PWR_FLAG_ODSWRDY) || ((FLAG) == PWR_FLAG_UDRDY))
169 |
170 |
171 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
172 | ((FLAG) == PWR_FLAG_UDRDY))
173 |
174 | /**
175 | * @}
176 | */
177 |
178 | /**
179 | * @}
180 | */
181 |
182 | /* Exported macro ------------------------------------------------------------*/
183 | /* Exported functions --------------------------------------------------------*/
184 |
185 | /* Function used to set the PWR configuration to the default reset state ******/
186 | void PWR_DeInit(void);
187 |
188 | /* Backup Domain Access function **********************************************/
189 | void PWR_BackupAccessCmd(FunctionalState NewState);
190 |
191 | /* PVD configuration functions ************************************************/
192 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
193 | void PWR_PVDCmd(FunctionalState NewState);
194 |
195 | /* WakeUp pins configuration functions ****************************************/
196 | #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F411xE)
197 | void PWR_WakeUpPinCmd(FunctionalState NewState);
198 | #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F411xE */
199 | #if defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) ||defined(STM32F446xx)
200 | void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPinx, FunctionalState NewState);
201 | #endif /* STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F446xx */
202 | /* Main and Backup Regulators configuration functions *************************/
203 | void PWR_BackupRegulatorCmd(FunctionalState NewState);
204 | void PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage);
205 | void PWR_OverDriveCmd(FunctionalState NewState);
206 | void PWR_OverDriveSWCmd(FunctionalState NewState);
207 | void PWR_UnderDriveCmd(FunctionalState NewState);
208 |
209 | #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx)
210 | void PWR_MainRegulatorUnderDriveCmd(FunctionalState NewState);
211 | void PWR_LowRegulatorUnderDriveCmd(FunctionalState NewState);
212 | #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx */
213 |
214 | #if defined(STM32F401xx) || defined(STM32F410xx) || defined(STM32F411xE) || defined(STM32F412xG) || defined(STM32F413_423xx)
215 | void PWR_MainRegulatorLowVoltageCmd(FunctionalState NewState);
216 | void PWR_LowRegulatorLowVoltageCmd(FunctionalState NewState);
217 | #endif /* STM32F401xx || STM32F410xx || STM32F411xE || STM32F412xG || STM32F413_423xx */
218 |
219 | /* FLASH Power Down configuration functions ***********************************/
220 | void PWR_FlashPowerDownCmd(FunctionalState NewState);
221 |
222 | /* Low Power modes configuration functions ************************************/
223 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
224 | void PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
225 | void PWR_EnterSTANDBYMode(void);
226 |
227 | /* Flags management functions *************************************************/
228 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
229 | void PWR_ClearFlag(uint32_t PWR_FLAG);
230 |
231 | #ifdef __cplusplus
232 | }
233 | #endif
234 |
235 | #endif /* __STM32F4xx_PWR_H */
236 |
237 | /**
238 | * @}
239 | */
240 |
241 | /**
242 | * @}
243 | */
244 |
245 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
246 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_rng.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_rng.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the Random
8 | * Number Generator(RNG) firmware library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_RNG_H
31 | #define __STM32F4xx_RNG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup RNG
45 | * @{
46 | */
47 | #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F410xx) || defined(STM32F412xG) || defined(STM32F413_423xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup RNG_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup RNG_flags_definition
56 | * @{
57 | */
58 | #define RNG_FLAG_DRDY ((uint8_t)0x0001) /*!< Data ready */
59 | #define RNG_FLAG_CECS ((uint8_t)0x0002) /*!< Clock error current status */
60 | #define RNG_FLAG_SECS ((uint8_t)0x0004) /*!< Seed error current status */
61 |
62 | #define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
63 | ((RNG_FLAG) == RNG_FLAG_CECS) || \
64 | ((RNG_FLAG) == RNG_FLAG_SECS))
65 | #define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
66 | ((RNG_FLAG) == RNG_FLAG_SECS))
67 | /**
68 | * @}
69 | */
70 |
71 | /** @defgroup RNG_interrupts_definition
72 | * @{
73 | */
74 | #define RNG_IT_CEI ((uint8_t)0x20) /*!< Clock error interrupt */
75 | #define RNG_IT_SEI ((uint8_t)0x40) /*!< Seed error interrupt */
76 |
77 | #define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
78 | #define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
79 | /**
80 | * @}
81 | */
82 |
83 | /**
84 | * @}
85 | */
86 |
87 | /* Exported macro ------------------------------------------------------------*/
88 | /* Exported functions --------------------------------------------------------*/
89 |
90 | /* Function used to set the RNG configuration to the default reset state *****/
91 | void RNG_DeInit(void);
92 |
93 | /* Configuration function *****************************************************/
94 | void RNG_Cmd(FunctionalState NewState);
95 |
96 | /* Get 32 bit Random number function ******************************************/
97 | uint32_t RNG_GetRandomNumber(void);
98 |
99 | /* Interrupts and flags management functions **********************************/
100 | void RNG_ITConfig(FunctionalState NewState);
101 | FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
102 | void RNG_ClearFlag(uint8_t RNG_FLAG);
103 | ITStatus RNG_GetITStatus(uint8_t RNG_IT);
104 | void RNG_ClearITPendingBit(uint8_t RNG_IT);
105 | #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F410xx || STM32F412xG || STM32F413_423xx || STM32F429_439xx || STM32F469_479xx */
106 |
107 | #ifdef __cplusplus
108 | }
109 | #endif
110 |
111 | #endif /*__STM32F4xx_RNG_H */
112 |
113 | /**
114 | * @}
115 | */
116 |
117 | /**
118 | * @}
119 | */
120 |
121 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
122 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_spdifrx.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_spdifrx.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the SPDIFRX firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_SPDIFRX_H
31 | #define __STM32F4xx_SPDIFRX_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup SPDIFRX
45 | * @{
46 | */
47 | #if defined(STM32F446xx)
48 | /* Exported types ------------------------------------------------------------*/
49 | /**
50 | * @brief SPDIFRX Init structure definition
51 | */
52 | typedef struct
53 | {
54 | uint32_t SPDIFRX_InputSelection; /*!< Specifies the SPDIFRX input selection.
55 | This parameter can be a value of @ref SPDIFRX_Input_Selection */
56 |
57 | uint32_t SPDIFRX_Retries; /*!< Specifies the Maximum allowed re-tries during synchronization phase.
58 | This parameter can be a value of @ref SPDIFRX_Max_Retries */
59 |
60 | uint32_t SPDIFRX_WaitForActivity; /*!< Specifies the wait for activity on SPDIFRX selected input.
61 | This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */
62 |
63 | uint32_t SPDIFRX_ChannelSelection; /*!< Specifies whether the control flow will take the channel status from channel A or B.
64 | This parameter can be a value of @ref SPDIFRX_Channel_Selection */
65 |
66 | uint32_t SPDIFRX_DataFormat; /*!< Specifies the Data samples format (LSB, MSB, ...).
67 | This parameter can be a value of @ref SPDIFRX_Data_Format */
68 |
69 | uint32_t SPDIFRX_StereoMode; /*!< Specifies whether the peripheral is in stereo or mono mode.
70 | This parameter can be a value of @ref SPDIFRX_Stereo_Mode */
71 | }SPDIFRX_InitTypeDef;
72 |
73 |
74 | /* Exported constants --------------------------------------------------------*/
75 |
76 | /** @defgroup SPDIFRX_Exported_Constants
77 | * @{
78 | */
79 | #define IS_SPDIFRX_PERIPH(PERIPH) (((PERIPH) == SPDIFRX))
80 |
81 | /** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection
82 | * @{
83 | */
84 | #define SPDIFRX_Input_IN0 ((uint32_t)0x00000000)
85 | #define SPDIFRX_Input_IN1 ((uint32_t)0x00010000)
86 | #define SPDIFRX_Input_IN2 ((uint32_t)0x00020000)
87 | #define SPDIFRX_Input_IN3 ((uint32_t)0x00030000)
88 | #define IS_SPDIFRX_INPUT_SELECT(INPUT) (((INPUT) == SPDIFRX_Input_IN1) || \
89 | ((INPUT) == SPDIFRX_Input_IN2) || \
90 | ((INPUT) == SPDIFRX_Input_IN3) || \
91 | ((INPUT) == SPDIFRX_Input_IN0))
92 | /**
93 | * @}
94 | */
95 |
96 | /** @defgroup SPDIFRX_Max_Retries SPDIFRX Max Retries
97 | * @{
98 | */
99 | #define SPDIFRX_1MAX_RETRIES ((uint32_t)0x00000000)
100 | #define SPDIFRX_4MAX_RETRIES ((uint32_t)0x00001000)
101 | #define SPDIFRX_16MAX_RETRIES ((uint32_t)0x00002000)
102 | #define SPDIFRX_64MAX_RETRIES ((uint32_t)0x00003000)
103 | #define IS_SPDIFRX_MAX_RETRIES(RET) (((RET) == SPDIFRX_1MAX_RETRIES) || \
104 | ((RET) == SPDIFRX_4MAX_RETRIES) || \
105 | ((RET) == SPDIFRX_16MAX_RETRIES) || \
106 | ((RET) == SPDIFRX_64MAX_RETRIES))
107 | /**
108 | * @}
109 | */
110 |
111 | /** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity
112 | * @{
113 | */
114 | #define SPDIFRX_WaitForActivity_Off ((uint32_t)0x00000000)
115 | #define SPDIFRX_WaitForActivity_On ((uint32_t)SPDIFRX_CR_WFA)
116 | #define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL) (((VAL) == SPDIFRX_WaitForActivity_On) || \
117 | ((VAL) == SPDIFRX_WaitForActivity_Off))
118 | /**
119 | * @}
120 | */
121 |
122 | /** @defgroup SPDIFRX_ChannelSelection SPDIFRX Channel Selection
123 | * @{
124 | */
125 | #define SPDIFRX_Select_Channel_A ((uint32_t)0x00000000)
126 | #define SPDIFRX_Select_Channel_B ((uint32_t)SPDIFRX_CR_CHSEL)
127 | #define IS_SPDIFRX_CHANNEL(CHANNEL) (((CHANNEL) == SPDIFRX_Select_Channel_A) || \
128 | ((CHANNEL) == SPDIFRX_Select_Channel_B))
129 | /**
130 | * @}
131 | */
132 |
133 | /** @defgroup SPDIFRX_Block_Synchronization SPDIFRX Block Synchronization
134 | * @{
135 | */
136 | #define SPDIFRX_LSB_DataFormat ((uint32_t)0x00000000)
137 | #define SPDIFRX_MSB_DataFormat ((uint32_t)0x00000010)
138 | #define SPDIFRX_32BITS_DataFormat ((uint32_t)0x00000020)
139 | #define IS_SPDIFRX_DATA_FORMAT(FORMAT) (((FORMAT) == SPDIFRX_LSB_DataFormat) || \
140 | ((FORMAT) == SPDIFRX_MSB_DataFormat) || \
141 | ((FORMAT) == SPDIFRX_32BITS_DataFormat))
142 | /**
143 | * @}
144 | */
145 |
146 | /** @defgroup SPDIFRX_StereoMode SPDIFRX StereoMode
147 | * @{
148 | */
149 | #define SPDIFRX_StereoMode_Disabled ((uint32_t)0x00000000)
150 | #define SPDIFRX_StereoMode_Enabled ((uint32_t)SPDIFRX_CR_RXSTEO)
151 | #define IS_STEREO_MODE(MODE) (((MODE) == SPDIFRX_StereoMode_Disabled) || \
152 | ((MODE) == SPDIFRX_StereoMode_Enabled))
153 | /**
154 | * @}
155 | */
156 |
157 | /** @defgroup SPDIFRX_State SPDIFRX State
158 | * @{
159 | */
160 | #define SPDIFRX_STATE_IDLE ((uint32_t)0x00000000)
161 | #define SPDIFRX_STATE_SYNC ((uint32_t)0x00000001)
162 | #define SPDIFRX_STATE_RCV ((uint32_t)SPDIFRX_CR_SPDIFEN)
163 | #define IS_SPDIFRX_STATE(STATE) (((STATE) == SPDIFRX_STATE_IDLE) || \
164 | ((STATE) == SPDIFRX_STATE_SYNC) || \
165 | ((STATE) == SPDIFRX_STATE_RCV))
166 | /**
167 | * @}
168 | */
169 |
170 | /** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition
171 | * @{
172 | */
173 | #define SPDIFRX_IT_RXNE ((uint32_t)SPDIFRX_IMR_RXNEIE)
174 | #define SPDIFRX_IT_CSRNE ((uint32_t)SPDIFRX_IMR_CSRNEIE)
175 | #define SPDIFRX_IT_PERRIE ((uint32_t)SPDIFRX_IMR_PERRIE)
176 | #define SPDIFRX_IT_OVRIE ((uint32_t)SPDIFRX_IMR_OVRIE)
177 | #define SPDIFRX_IT_SBLKIE ((uint32_t)SPDIFRX_IMR_SBLKIE)
178 | #define SPDIFRX_IT_SYNCDIE ((uint32_t)SPDIFRX_IMR_SYNCDIE)
179 | #define SPDIFRX_IT_IFEIE ((uint32_t)SPDIFRX_IMR_IFEIE )
180 | #define IS_SPDIFRX_CONFIG_IT(IT) (((IT) == SPDIFRX_IT_RXNE) || \
181 | ((IT) == SPDIFRX_IT_CSRNE) || \
182 | ((IT) == SPDIFRX_IT_PERRIE) || \
183 | ((IT) == SPDIFRX_IT_OVRIE) || \
184 | ((IT) == SPDIFRX_IT_SBLKIE) || \
185 | ((IT) == SPDIFRX_IT_SYNCDIE) || \
186 | ((IT) == SPDIFRX_IT_IFEIE))
187 | /**
188 | * @}
189 | */
190 |
191 | /** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition
192 | * @{
193 | */
194 | #define SPDIFRX_FLAG_RXNE ((uint32_t)SPDIFRX_SR_RXNE)
195 | #define SPDIFRX_FLAG_CSRNE ((uint32_t)SPDIFRX_SR_CSRNE)
196 | #define SPDIFRX_FLAG_PERR ((uint32_t)SPDIFRX_SR_PERR)
197 | #define SPDIFRX_FLAG_OVR ((uint32_t)SPDIFRX_SR_OVR)
198 | #define SPDIFRX_FLAG_SBD ((uint32_t)SPDIFRX_SR_SBD)
199 | #define SPDIFRX_FLAG_SYNCD ((uint32_t)SPDIFRX_SR_SYNCD)
200 | #define SPDIFRX_FLAG_FERR ((uint32_t)SPDIFRX_SR_FERR)
201 | #define SPDIFRX_FLAG_SERR ((uint32_t)SPDIFRX_SR_SERR)
202 | #define SPDIFRX_FLAG_TERR ((uint32_t)SPDIFRX_SR_TERR)
203 | #define IS_SPDIFRX_FLAG(FLAG) (((FLAG) == SPDIFRX_FLAG_RXNE) || ((FLAG) == SPDIFRX_FLAG_CSRNE) || \
204 | ((FLAG) == SPDIFRX_FLAG_PERR) || ((FLAG) == SPDIFRX_FLAG_OVR) || \
205 | ((FLAG) == SPDIFRX_SR_SBD) || ((FLAG) == SPDIFRX_SR_SYNCD) || \
206 | ((FLAG) == SPDIFRX_SR_FERR) || ((FLAG) == SPDIFRX_SR_SERR) || \
207 | ((FLAG) == SPDIFRX_SR_TERR))
208 | #define IS_SPDIFRX_CLEAR_FLAG(FLAG) (((FLAG) == SPDIFRX_FLAG_PERR) || ((FLAG) == SPDIFRX_FLAG_OVR) || \
209 | ((FLAG) == SPDIFRX_SR_SBD) || ((FLAG) == SPDIFRX_SR_SYNCD))
210 | /**
211 | * @}
212 | */
213 |
214 | /**
215 | * @}
216 | */
217 |
218 | /* Exported macro ------------------------------------------------------------*/
219 | /* Exported functions --------------------------------------------------------*/
220 |
221 | /* Function used to set the SPDIFRX configuration to the default reset state *****/
222 | void SPDIFRX_DeInit(void);
223 |
224 | /* Initialization and Configuration functions *********************************/
225 | void SPDIFRX_Init(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct);
226 | void SPDIFRX_StructInit(SPDIFRX_InitTypeDef* SPDIFRX_InitStruct);
227 | void SPDIFRX_Cmd(uint32_t SPDIFRX_State);
228 | void SPDIFRX_SetPreambleTypeBit(FunctionalState NewState);
229 | void SPDIFRX_SetUserDataChannelStatusBits(FunctionalState NewState);
230 | void SPDIFRX_SetValidityBit(FunctionalState NewState);
231 | void SPDIFRX_SetParityBit(FunctionalState NewState);
232 |
233 | /* Data transfers functions ***************************************************/
234 | uint32_t SPDIFRX_ReceiveData(void);
235 |
236 | /* DMA transfers management functions *****************************************/
237 | void SPDIFRX_RxDMACmd(FunctionalState NewState);
238 | void SPDIFRX_CbDMACmd(FunctionalState NewState);
239 |
240 | /* Interrupts and flags management functions **********************************/
241 | void SPDIFRX_ITConfig(uint32_t SPDIFRX_IT, FunctionalState NewState);
242 | FlagStatus SPDIFRX_GetFlagStatus(uint32_t SPDIFRX_FLAG);
243 | void SPDIFRX_ClearFlag(uint32_t SPDIFRX_FLAG);
244 | ITStatus SPDIFRX_GetITStatus(uint32_t SPDIFRX_IT);
245 | void SPDIFRX_ClearITPendingBit(uint32_t SPDIFRX_IT);
246 |
247 | #endif /* STM32F446xx */
248 | /**
249 | * @}
250 | */
251 |
252 | /**
253 | * @}
254 | */
255 |
256 | #ifdef __cplusplus
257 | }
258 | #endif
259 |
260 | #endif /*__STM32F4xx_SPDIFRX_H */
261 |
262 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
263 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/inc/stm32f4xx_wwdg.h:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_wwdg.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains all the functions prototypes for the WWDG firmware
8 | * library.
9 | ******************************************************************************
10 | * @attention
11 | *
12 | * © COPYRIGHT 2016 STMicroelectronics
13 | *
14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
15 | * You may not use this file except in compliance with the License.
16 | * You may obtain a copy of the License at:
17 | *
18 | * http://www.st.com/software_license_agreement_liberty_v2
19 | *
20 | * Unless required by applicable law or agreed to in writing, software
21 | * distributed under the License is distributed on an "AS IS" BASIS,
22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
23 | * See the License for the specific language governing permissions and
24 | * limitations under the License.
25 | *
26 | ******************************************************************************
27 | */
28 |
29 | /* Define to prevent recursive inclusion -------------------------------------*/
30 | #ifndef __STM32F4xx_WWDG_H
31 | #define __STM32F4xx_WWDG_H
32 |
33 | #ifdef __cplusplus
34 | extern "C" {
35 | #endif
36 |
37 | /* Includes ------------------------------------------------------------------*/
38 | #include "stm32f4xx.h"
39 |
40 | /** @addtogroup STM32F4xx_StdPeriph_Driver
41 | * @{
42 | */
43 |
44 | /** @addtogroup WWDG
45 | * @{
46 | */
47 |
48 | /* Exported types ------------------------------------------------------------*/
49 | /* Exported constants --------------------------------------------------------*/
50 |
51 | /** @defgroup WWDG_Exported_Constants
52 | * @{
53 | */
54 |
55 | /** @defgroup WWDG_Prescaler
56 | * @{
57 | */
58 |
59 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000)
60 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080)
61 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100)
62 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180)
63 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
64 | ((PRESCALER) == WWDG_Prescaler_2) || \
65 | ((PRESCALER) == WWDG_Prescaler_4) || \
66 | ((PRESCALER) == WWDG_Prescaler_8))
67 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
68 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /**
75 | * @}
76 | */
77 |
78 | /* Exported macro ------------------------------------------------------------*/
79 | /* Exported functions --------------------------------------------------------*/
80 |
81 | /* Function used to set the WWDG configuration to the default reset state ****/
82 | void WWDG_DeInit(void);
83 |
84 | /* Prescaler, Refresh window and Counter configuration functions **************/
85 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
86 | void WWDG_SetWindowValue(uint8_t WindowValue);
87 | void WWDG_EnableIT(void);
88 | void WWDG_SetCounter(uint8_t Counter);
89 |
90 | /* WWDG activation function ***************************************************/
91 | void WWDG_Enable(uint8_t Counter);
92 |
93 | /* Interrupts and flags management functions **********************************/
94 | FlagStatus WWDG_GetFlagStatus(void);
95 | void WWDG_ClearFlag(void);
96 |
97 | #ifdef __cplusplus
98 | }
99 | #endif
100 |
101 | #endif /* __STM32F4xx_WWDG_H */
102 |
103 | /**
104 | * @}
105 | */
106 |
107 | /**
108 | * @}
109 | */
110 |
111 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
112 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/src/misc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file misc.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file provides all the miscellaneous firmware functions (add-on
8 | * to CMSIS functions).
9 | *
10 | * @verbatim
11 | *
12 | * ===================================================================
13 | * How to configure Interrupts using driver
14 | * ===================================================================
15 | *
16 | * This section provide functions allowing to configure the NVIC interrupts (IRQ).
17 | * The Cortex-M4 exceptions are managed by CMSIS functions.
18 | *
19 | * 1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
20 | * function according to the following table.
21 |
22 | * The table below gives the allowed values of the pre-emption priority and subpriority according
23 | * to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
24 | * ==========================================================================================================================
25 | * NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
26 | * ==========================================================================================================================
27 | * NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
28 | * | | | 4 bits for subpriority
29 | * --------------------------------------------------------------------------------------------------------------------------
30 | * NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
31 | * | | | 3 bits for subpriority
32 | * --------------------------------------------------------------------------------------------------------------------------
33 | * NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
34 | * | | | 2 bits for subpriority
35 | * --------------------------------------------------------------------------------------------------------------------------
36 | * NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
37 | * | | | 1 bits for subpriority
38 | * --------------------------------------------------------------------------------------------------------------------------
39 | * NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
40 | * | | | 0 bits for subpriority
41 | * ==========================================================================================================================
42 | *
43 | * 2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()
44 | *
45 | * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
46 | * The pending IRQ priority will be managed only by the subpriority.
47 | *
48 | * @note IRQ priority order (sorted by highest to lowest priority):
49 | * - Lowest pre-emption priority
50 | * - Lowest subpriority
51 | * - Lowest hardware priority (IRQ number)
52 | *
53 | * @endverbatim
54 | *
55 | ******************************************************************************
56 | * @attention
57 | *
58 | * © COPYRIGHT 2016 STMicroelectronics
59 | *
60 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
61 | * You may not use this file except in compliance with the License.
62 | * You may obtain a copy of the License at:
63 | *
64 | * http://www.st.com/software_license_agreement_liberty_v2
65 | *
66 | * Unless required by applicable law or agreed to in writing, software
67 | * distributed under the License is distributed on an "AS IS" BASIS,
68 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
69 | * See the License for the specific language governing permissions and
70 | * limitations under the License.
71 | *
72 | ******************************************************************************
73 | */
74 |
75 | /* Includes ------------------------------------------------------------------*/
76 | #include "misc.h"
77 |
78 | /** @addtogroup STM32F4xx_StdPeriph_Driver
79 | * @{
80 | */
81 |
82 | /** @defgroup MISC
83 | * @brief MISC driver modules
84 | * @{
85 | */
86 |
87 | /* Private typedef -----------------------------------------------------------*/
88 | /* Private define ------------------------------------------------------------*/
89 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
90 |
91 | /* Private macro -------------------------------------------------------------*/
92 | /* Private variables ---------------------------------------------------------*/
93 | /* Private function prototypes -----------------------------------------------*/
94 | /* Private functions ---------------------------------------------------------*/
95 |
96 | /** @defgroup MISC_Private_Functions
97 | * @{
98 | */
99 |
100 | /**
101 | * @brief Configures the priority grouping: pre-emption priority and subpriority.
102 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
103 | * This parameter can be one of the following values:
104 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
105 | * 4 bits for subpriority
106 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
107 | * 3 bits for subpriority
108 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
109 | * 2 bits for subpriority
110 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
111 | * 1 bits for subpriority
112 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
113 | * 0 bits for subpriority
114 | * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
115 | * The pending IRQ priority will be managed only by the subpriority.
116 | * @retval None
117 | */
118 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
119 | {
120 | /* Check the parameters */
121 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
122 |
123 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
124 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
125 | }
126 |
127 | /**
128 | * @brief Initializes the NVIC peripheral according to the specified
129 | * parameters in the NVIC_InitStruct.
130 | * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
131 | * function should be called before.
132 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
133 | * the configuration information for the specified NVIC peripheral.
134 | * @retval None
135 | */
136 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
137 | {
138 | uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
139 |
140 | /* Check the parameters */
141 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
142 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
143 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
144 |
145 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
146 | {
147 | /* Compute the Corresponding IRQ Priority --------------------------------*/
148 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
149 | tmppre = (0x4 - tmppriority);
150 | tmpsub = tmpsub >> tmppriority;
151 |
152 | tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
153 | tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
154 |
155 | tmppriority = tmppriority << 0x04;
156 |
157 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
158 |
159 | /* Enable the Selected IRQ Channels --------------------------------------*/
160 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
161 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
162 | }
163 | else
164 | {
165 | /* Disable the Selected IRQ Channels -------------------------------------*/
166 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
167 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
168 | }
169 | }
170 |
171 | /**
172 | * @brief Sets the vector table location and Offset.
173 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
174 | * This parameter can be one of the following values:
175 | * @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
176 | * @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
177 | * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
178 | * @retval None
179 | */
180 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
181 | {
182 | /* Check the parameters */
183 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
184 | assert_param(IS_NVIC_OFFSET(Offset));
185 |
186 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
187 | }
188 |
189 | /**
190 | * @brief Selects the condition for the system to enter low power mode.
191 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
192 | * This parameter can be one of the following values:
193 | * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
194 | * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
195 | * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
196 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
197 | * @retval None
198 | */
199 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
200 | {
201 | /* Check the parameters */
202 | assert_param(IS_NVIC_LP(LowPowerMode));
203 | assert_param(IS_FUNCTIONAL_STATE(NewState));
204 |
205 | if (NewState != DISABLE)
206 | {
207 | SCB->SCR |= LowPowerMode;
208 | }
209 | else
210 | {
211 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
212 | }
213 | }
214 |
215 | /**
216 | * @brief Configures the SysTick clock source.
217 | * @param SysTick_CLKSource: specifies the SysTick clock source.
218 | * This parameter can be one of the following values:
219 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
220 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
221 | * @retval None
222 | */
223 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
224 | {
225 | /* Check the parameters */
226 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
227 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
228 | {
229 | SysTick->CTRL |= SysTick_CLKSource_HCLK;
230 | }
231 | else
232 | {
233 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
234 | }
235 | }
236 |
237 | /**
238 | * @}
239 | */
240 |
241 | /**
242 | * @}
243 | */
244 |
245 | /**
246 | * @}
247 | */
248 |
249 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
250 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/src/stm32f4xx_crc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_crc.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file provides all the CRC firmware functions.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_crc.h"
30 |
31 | /** @addtogroup STM32F4xx_StdPeriph_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup CRC
36 | * @brief CRC driver modules
37 | * @{
38 | */
39 |
40 | /* Private typedef -----------------------------------------------------------*/
41 | /* Private define ------------------------------------------------------------*/
42 | /* Private macro -------------------------------------------------------------*/
43 | /* Private variables ---------------------------------------------------------*/
44 | /* Private function prototypes -----------------------------------------------*/
45 | /* Private functions ---------------------------------------------------------*/
46 |
47 | /** @defgroup CRC_Private_Functions
48 | * @{
49 | */
50 |
51 | /**
52 | * @brief Resets the CRC Data register (DR).
53 | * @param None
54 | * @retval None
55 | */
56 | void CRC_ResetDR(void)
57 | {
58 | /* Reset CRC generator */
59 | CRC->CR = CRC_CR_RESET;
60 | }
61 |
62 | /**
63 | * @brief Computes the 32-bit CRC of a given data word(32-bit).
64 | * @param Data: data word(32-bit) to compute its CRC
65 | * @retval 32-bit CRC
66 | */
67 | uint32_t CRC_CalcCRC(uint32_t Data)
68 | {
69 | CRC->DR = Data;
70 |
71 | return (CRC->DR);
72 | }
73 |
74 | /**
75 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
76 | * @param pBuffer: pointer to the buffer containing the data to be computed
77 | * @param BufferLength: length of the buffer to be computed
78 | * @retval 32-bit CRC
79 | */
80 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
81 | {
82 | uint32_t index = 0;
83 |
84 | for(index = 0; index < BufferLength; index++)
85 | {
86 | CRC->DR = pBuffer[index];
87 | }
88 | return (CRC->DR);
89 | }
90 |
91 | /**
92 | * @brief Returns the current CRC value.
93 | * @param None
94 | * @retval 32-bit CRC
95 | */
96 | uint32_t CRC_GetCRC(void)
97 | {
98 | return (CRC->DR);
99 | }
100 |
101 | /**
102 | * @brief Stores a 8-bit data in the Independent Data(ID) register.
103 | * @param IDValue: 8-bit value to be stored in the ID register
104 | * @retval None
105 | */
106 | void CRC_SetIDRegister(uint8_t IDValue)
107 | {
108 | CRC->IDR = IDValue;
109 | }
110 |
111 | /**
112 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register
113 | * @param None
114 | * @retval 8-bit value of the ID register
115 | */
116 | uint8_t CRC_GetIDRegister(void)
117 | {
118 | return (CRC->IDR);
119 | }
120 |
121 | /**
122 | * @}
123 | */
124 |
125 | /**
126 | * @}
127 | */
128 |
129 | /**
130 | * @}
131 | */
132 |
133 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
134 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/src/stm32f4xx_cryp_des.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_cryp_des.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file provides high level functions to encrypt and decrypt an
8 | * input message using DES in ECB/CBC modes.
9 | * It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
10 | * peripheral.
11 | *
12 | @verbatim
13 |
14 | ===================================================================
15 | ##### How to use this driver #####
16 | ===================================================================
17 | [..]
18 | (#) Enable The CRYP controller clock using
19 | RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
20 |
21 | (#) Encrypt and decrypt using DES in ECB Mode using CRYP_DES_ECB() function.
22 |
23 | (#) Encrypt and decrypt using DES in CBC Mode using CRYP_DES_CBC() function.
24 |
25 | @endverbatim
26 | *
27 | ******************************************************************************
28 | * @attention
29 | *
30 | * © COPYRIGHT 2016 STMicroelectronics
31 | *
32 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
33 | * You may not use this file except in compliance with the License.
34 | * You may obtain a copy of the License at:
35 | *
36 | * http://www.st.com/software_license_agreement_liberty_v2
37 | *
38 | * Unless required by applicable law or agreed to in writing, software
39 | * distributed under the License is distributed on an "AS IS" BASIS,
40 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41 | * See the License for the specific language governing permissions and
42 | * limitations under the License.
43 | *
44 | ******************************************************************************
45 | */
46 |
47 | /* Includes ------------------------------------------------------------------*/
48 | #include "stm32f4xx_cryp.h"
49 |
50 |
51 | /** @addtogroup STM32F4xx_StdPeriph_Driver
52 | * @{
53 | */
54 |
55 | /** @defgroup CRYP
56 | * @brief CRYP driver modules
57 | * @{
58 | */
59 |
60 | /* Private typedef -----------------------------------------------------------*/
61 | /* Private define ------------------------------------------------------------*/
62 | #define DESBUSY_TIMEOUT ((uint32_t) 0x00010000)
63 |
64 | /* Private macro -------------------------------------------------------------*/
65 | /* Private variables ---------------------------------------------------------*/
66 | /* Private function prototypes -----------------------------------------------*/
67 | /* Private functions ---------------------------------------------------------*/
68 |
69 |
70 | /** @defgroup CRYP_Private_Functions
71 | * @{
72 | */
73 |
74 | /** @defgroup CRYP_Group8 High Level DES functions
75 | * @brief High Level DES functions
76 | *
77 | @verbatim
78 | ===============================================================================
79 | ##### High Level DES functions #####
80 | ===============================================================================
81 | @endverbatim
82 | * @{
83 | */
84 |
85 | /**
86 | * @brief Encrypt and decrypt using DES in ECB Mode
87 | * @param Mode: encryption or decryption Mode.
88 | * This parameter can be one of the following values:
89 | * @arg MODE_ENCRYPT: Encryption
90 | * @arg MODE_DECRYPT: Decryption
91 | * @param Key: Key used for DES algorithm.
92 | * @param Ilength: length of the Input buffer, must be a multiple of 8.
93 | * @param Input: pointer to the Input buffer.
94 | * @param Output: pointer to the returned buffer.
95 | * @retval An ErrorStatus enumeration value:
96 | * - SUCCESS: Operation done
97 | * - ERROR: Operation failed
98 | */
99 | ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input,
100 | uint32_t Ilength, uint8_t *Output)
101 | {
102 | CRYP_InitTypeDef DES_CRYP_InitStructure;
103 | CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
104 | __IO uint32_t counter = 0;
105 | uint32_t busystatus = 0;
106 | ErrorStatus status = SUCCESS;
107 | uint32_t keyaddr = (uint32_t)Key;
108 | uint32_t inputaddr = (uint32_t)Input;
109 | uint32_t outputaddr = (uint32_t)Output;
110 | uint32_t i = 0;
111 |
112 | /* Crypto structures initialisation*/
113 | CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
114 |
115 | /* Crypto Init for Encryption process */
116 | if( Mode == MODE_ENCRYPT ) /* DES encryption */
117 | {
118 | DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
119 | }
120 | else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
121 | {
122 | DES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
123 | }
124 |
125 | DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
126 | DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
127 | CRYP_Init(&DES_CRYP_InitStructure);
128 |
129 | /* Key Initialisation */
130 | DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
131 | keyaddr+=4;
132 | DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
133 | CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
134 |
135 | /* Flush IN/OUT FIFO */
136 | CRYP_FIFOFlush();
137 |
138 | /* Enable Crypto processor */
139 | CRYP_Cmd(ENABLE);
140 |
141 | if(CRYP_GetCmdStatus() == DISABLE)
142 | {
143 | /* The CRYP peripheral clock is not enabled or the device doesn't embed
144 | the CRYP peripheral (please check the device sales type. */
145 | status = ERROR;
146 | }
147 | else
148 | {
149 | for(i=0; ((i© COPYRIGHT 2016 STMicroelectronics
31 | *
32 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
33 | * You may not use this file except in compliance with the License.
34 | * You may obtain a copy of the License at:
35 | *
36 | * http://www.st.com/software_license_agreement_liberty_v2
37 | *
38 | * Unless required by applicable law or agreed to in writing, software
39 | * distributed under the License is distributed on an "AS IS" BASIS,
40 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41 | * See the License for the specific language governing permissions and
42 | * limitations under the License.
43 | *
44 | ******************************************************************************
45 | */
46 |
47 | /* Includes ------------------------------------------------------------------*/
48 | #include "stm32f4xx_cryp.h"
49 |
50 |
51 | /** @addtogroup STM32F4xx_StdPeriph_Driver
52 | * @{
53 | */
54 |
55 | /** @defgroup CRYP
56 | * @brief CRYP driver modules
57 | * @{
58 | */
59 |
60 | /* Private typedef -----------------------------------------------------------*/
61 | /* Private define ------------------------------------------------------------*/
62 | #define TDESBUSY_TIMEOUT ((uint32_t) 0x00010000)
63 |
64 | /* Private macro -------------------------------------------------------------*/
65 | /* Private variables ---------------------------------------------------------*/
66 | /* Private function prototypes -----------------------------------------------*/
67 | /* Private functions ---------------------------------------------------------*/
68 |
69 |
70 | /** @defgroup CRYP_Private_Functions
71 | * @{
72 | */
73 |
74 | /** @defgroup CRYP_Group7 High Level TDES functions
75 | * @brief High Level TDES functions
76 | *
77 | @verbatim
78 | ===============================================================================
79 | ##### High Level TDES functions #####
80 | ===============================================================================
81 |
82 | @endverbatim
83 | * @{
84 | */
85 |
86 | /**
87 | * @brief Encrypt and decrypt using TDES in ECB Mode
88 | * @param Mode: encryption or decryption Mode.
89 | * This parameter can be one of the following values:
90 | * @arg MODE_ENCRYPT: Encryption
91 | * @arg MODE_DECRYPT: Decryption
92 | * @param Key: Key used for TDES algorithm.
93 | * @param Ilength: length of the Input buffer, must be a multiple of 8.
94 | * @param Input: pointer to the Input buffer.
95 | * @param Output: pointer to the returned buffer.
96 | * @retval An ErrorStatus enumeration value:
97 | * - SUCCESS: Operation done
98 | * - ERROR: Operation failed
99 | */
100 | ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input,
101 | uint32_t Ilength, uint8_t *Output)
102 | {
103 | CRYP_InitTypeDef TDES_CRYP_InitStructure;
104 | CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
105 | __IO uint32_t counter = 0;
106 | uint32_t busystatus = 0;
107 | ErrorStatus status = SUCCESS;
108 | uint32_t keyaddr = (uint32_t)Key;
109 | uint32_t inputaddr = (uint32_t)Input;
110 | uint32_t outputaddr = (uint32_t)Output;
111 | uint32_t i = 0;
112 |
113 | /* Crypto structures initialisation*/
114 | CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
115 |
116 | /* Crypto Init for Encryption process */
117 | if(Mode == MODE_ENCRYPT) /* TDES encryption */
118 | {
119 | TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
120 | }
121 | else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */
122 | {
123 | TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
124 | }
125 |
126 | TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
127 | TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
128 | CRYP_Init(&TDES_CRYP_InitStructure);
129 |
130 | /* Key Initialisation */
131 | TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
132 | keyaddr+=4;
133 | TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
134 | keyaddr+=4;
135 | TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
136 | keyaddr+=4;
137 | TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
138 | keyaddr+=4;
139 | TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
140 | keyaddr+=4;
141 | TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
142 | CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
143 |
144 | /* Flush IN/OUT FIFO */
145 | CRYP_FIFOFlush();
146 |
147 | /* Enable Crypto processor */
148 | CRYP_Cmd(ENABLE);
149 |
150 | if(CRYP_GetCmdStatus() == DISABLE)
151 | {
152 | /* The CRYP peripheral clock is not enabled or the device doesn't embed
153 | the CRYP peripheral (please check the device sales type. */
154 | status = ERROR;
155 | }
156 | else
157 | {
158 | for(i=0; ((i© COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Includes ------------------------------------------------------------------*/
29 | #include "stm32f4xx_dbgmcu.h"
30 |
31 | /** @addtogroup STM32F4xx_StdPeriph_Driver
32 | * @{
33 | */
34 |
35 | /** @defgroup DBGMCU
36 | * @brief DBGMCU driver modules
37 | * @{
38 | */
39 |
40 | /* Private typedef -----------------------------------------------------------*/
41 | /* Private define ------------------------------------------------------------*/
42 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
43 |
44 | /* Private macro -------------------------------------------------------------*/
45 | /* Private variables ---------------------------------------------------------*/
46 | /* Private function prototypes -----------------------------------------------*/
47 | /* Private functions ---------------------------------------------------------*/
48 |
49 | /** @defgroup DBGMCU_Private_Functions
50 | * @{
51 | */
52 |
53 | /**
54 | * @brief Returns the device revision identifier.
55 | * @param None
56 | * @retval Device revision identifier
57 | */
58 | uint32_t DBGMCU_GetREVID(void)
59 | {
60 | return(DBGMCU->IDCODE >> 16);
61 | }
62 |
63 | /**
64 | * @brief Returns the device identifier.
65 | * @param None
66 | * @retval Device identifier
67 | */
68 | uint32_t DBGMCU_GetDEVID(void)
69 | {
70 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
71 | }
72 |
73 | /**
74 | * @brief Configures low power mode behavior when the MCU is in Debug mode.
75 | * @param DBGMCU_Periph: specifies the low power mode.
76 | * This parameter can be any combination of the following values:
77 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
78 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
79 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
80 | * @param NewState: new state of the specified low power mode in Debug mode.
81 | * This parameter can be: ENABLE or DISABLE.
82 | * @retval None
83 | */
84 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
85 | {
86 | /* Check the parameters */
87 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
88 | assert_param(IS_FUNCTIONAL_STATE(NewState));
89 | if (NewState != DISABLE)
90 | {
91 | DBGMCU->CR |= DBGMCU_Periph;
92 | }
93 | else
94 | {
95 | DBGMCU->CR &= ~DBGMCU_Periph;
96 | }
97 | }
98 |
99 | /**
100 | * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
101 | * @param DBGMCU_Periph: specifies the APB1 peripheral.
102 | * This parameter can be any combination of the following values:
103 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
104 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
105 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
106 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
107 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
108 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
109 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
110 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
111 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
112 | * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.
113 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
114 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
115 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
116 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
117 | * @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
118 | * @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
119 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
120 | * This parameter can be: ENABLE or DISABLE.
121 | * @retval None
122 | */
123 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
124 | {
125 | /* Check the parameters */
126 | assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
127 | assert_param(IS_FUNCTIONAL_STATE(NewState));
128 |
129 | if (NewState != DISABLE)
130 | {
131 | DBGMCU->APB1FZ |= DBGMCU_Periph;
132 | }
133 | else
134 | {
135 | DBGMCU->APB1FZ &= ~DBGMCU_Periph;
136 | }
137 | }
138 |
139 | /**
140 | * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
141 | * @param DBGMCU_Periph: specifies the APB2 peripheral.
142 | * This parameter can be any combination of the following values:
143 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
144 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
145 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
146 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
147 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
148 | * @param NewState: new state of the specified peripheral in Debug mode.
149 | * This parameter can be: ENABLE or DISABLE.
150 | * @retval None
151 | */
152 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
153 | {
154 | /* Check the parameters */
155 | assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
156 | assert_param(IS_FUNCTIONAL_STATE(NewState));
157 |
158 | if (NewState != DISABLE)
159 | {
160 | DBGMCU->APB2FZ |= DBGMCU_Periph;
161 | }
162 | else
163 | {
164 | DBGMCU->APB2FZ &= ~DBGMCU_Periph;
165 | }
166 | }
167 |
168 | /**
169 | * @}
170 | */
171 |
172 | /**
173 | * @}
174 | */
175 |
176 | /**
177 | * @}
178 | */
179 |
180 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
181 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/src/stm32f4xx_exti.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_exti.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the EXTI peripheral:
9 | * + Initialization and Configuration
10 | * + Interrupts and flags management
11 | *
12 | @verbatim
13 |
14 | ===============================================================================
15 | ##### EXTI features #####
16 | ===============================================================================
17 |
18 | [..] External interrupt/event lines are mapped as following:
19 | (#) All available GPIO pins are connected to the 16 external
20 | interrupt/event lines from EXTI0 to EXTI15.
21 | (#) EXTI line 16 is connected to the PVD Output
22 | (#) EXTI line 17 is connected to the RTC Alarm event
23 | (#) EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event
24 | (#) EXTI line 19 is connected to the Ethernet Wakeup event
25 | (#) EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event
26 | (#) EXTI line 21 is connected to the RTC Tamper and Time Stamp events
27 | (#) EXTI line 22 is connected to the RTC Wakeup event
28 | (#) EXTI line 23 is connected to the LPTIM Wakeup event
29 |
30 | ##### How to use this driver #####
31 | ===============================================================================
32 |
33 | [..] In order to use an I/O pin as an external interrupt source, follow steps
34 | below:
35 | (#) Configure the I/O in input mode using GPIO_Init()
36 | (#) Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
37 | (#) Select the mode(interrupt, event) and configure the trigger
38 | selection (Rising, falling or both) using EXTI_Init()
39 | (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
40 |
41 | [..]
42 | (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
43 | registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
44 |
45 | @endverbatim
46 | *
47 | ******************************************************************************
48 | * @attention
49 | *
50 | * © COPYRIGHT 2016 STMicroelectronics
51 | *
52 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
53 | * You may not use this file except in compliance with the License.
54 | * You may obtain a copy of the License at:
55 | *
56 | * http://www.st.com/software_license_agreement_liberty_v2
57 | *
58 | * Unless required by applicable law or agreed to in writing, software
59 | * distributed under the License is distributed on an "AS IS" BASIS,
60 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
61 | * See the License for the specific language governing permissions and
62 | * limitations under the License.
63 | *
64 | ******************************************************************************
65 | */
66 |
67 | /* Includes ------------------------------------------------------------------*/
68 | #include "stm32f4xx_exti.h"
69 |
70 | /** @addtogroup STM32F4xx_StdPeriph_Driver
71 | * @{
72 | */
73 |
74 | /** @defgroup EXTI
75 | * @brief EXTI driver modules
76 | * @{
77 | */
78 |
79 | /* Private typedef -----------------------------------------------------------*/
80 | /* Private define ------------------------------------------------------------*/
81 |
82 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
83 |
84 | /* Private macro -------------------------------------------------------------*/
85 | /* Private variables ---------------------------------------------------------*/
86 | /* Private function prototypes -----------------------------------------------*/
87 | /* Private functions ---------------------------------------------------------*/
88 |
89 | /** @defgroup EXTI_Private_Functions
90 | * @{
91 | */
92 |
93 | /** @defgroup EXTI_Group1 Initialization and Configuration functions
94 | * @brief Initialization and Configuration functions
95 | *
96 | @verbatim
97 | ===============================================================================
98 | ##### Initialization and Configuration functions #####
99 | ===============================================================================
100 |
101 | @endverbatim
102 | * @{
103 | */
104 |
105 | /**
106 | * @brief Deinitializes the EXTI peripheral registers to their default reset values.
107 | * @param None
108 | * @retval None
109 | */
110 | void EXTI_DeInit(void)
111 | {
112 | EXTI->IMR = 0x00000000;
113 | EXTI->EMR = 0x00000000;
114 | EXTI->RTSR = 0x00000000;
115 | EXTI->FTSR = 0x00000000;
116 | EXTI->PR = 0x007FFFFF;
117 | }
118 |
119 | /**
120 | * @brief Initializes the EXTI peripheral according to the specified
121 | * parameters in the EXTI_InitStruct.
122 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
123 | * that contains the configuration information for the EXTI peripheral.
124 | * @retval None
125 | */
126 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
127 | {
128 | uint32_t tmp = 0;
129 |
130 | /* Check the parameters */
131 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
132 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
133 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
134 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
135 |
136 | tmp = (uint32_t)EXTI_BASE;
137 |
138 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
139 | {
140 | /* Clear EXTI line configuration */
141 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
142 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
143 |
144 | tmp += EXTI_InitStruct->EXTI_Mode;
145 |
146 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
147 |
148 | /* Clear Rising Falling edge configuration */
149 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
150 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
151 |
152 | /* Select the trigger for the selected external interrupts */
153 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
154 | {
155 | /* Rising Falling edge */
156 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
157 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
158 | }
159 | else
160 | {
161 | tmp = (uint32_t)EXTI_BASE;
162 | tmp += EXTI_InitStruct->EXTI_Trigger;
163 |
164 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
165 | }
166 | }
167 | else
168 | {
169 | tmp += EXTI_InitStruct->EXTI_Mode;
170 |
171 | /* Disable the selected external lines */
172 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
173 | }
174 | }
175 |
176 | /**
177 | * @brief Fills each EXTI_InitStruct member with its reset value.
178 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
179 | * be initialized.
180 | * @retval None
181 | */
182 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
183 | {
184 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
185 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
186 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
187 | EXTI_InitStruct->EXTI_LineCmd = DISABLE;
188 | }
189 |
190 | /**
191 | * @brief Generates a Software interrupt on selected EXTI line.
192 | * @param EXTI_Line: specifies the EXTI line on which the software interrupt
193 | * will be generated.
194 | * This parameter can be any combination of EXTI_Linex where x can be (0..22)
195 | * @retval None
196 | */
197 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
198 | {
199 | /* Check the parameters */
200 | assert_param(IS_EXTI_LINE(EXTI_Line));
201 |
202 | EXTI->SWIER |= EXTI_Line;
203 | }
204 |
205 | /**
206 | * @}
207 | */
208 |
209 | /** @defgroup EXTI_Group2 Interrupts and flags management functions
210 | * @brief Interrupts and flags management functions
211 | *
212 | @verbatim
213 | ===============================================================================
214 | ##### Interrupts and flags management functions #####
215 | ===============================================================================
216 |
217 | @endverbatim
218 | * @{
219 | */
220 |
221 | /**
222 | * @brief Checks whether the specified EXTI line flag is set or not.
223 | * @param EXTI_Line: specifies the EXTI line flag to check.
224 | * This parameter can be EXTI_Linex where x can be(0..22)
225 | * @retval The new state of EXTI_Line (SET or RESET).
226 | */
227 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
228 | {
229 | FlagStatus bitstatus = RESET;
230 | /* Check the parameters */
231 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
232 |
233 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
234 | {
235 | bitstatus = SET;
236 | }
237 | else
238 | {
239 | bitstatus = RESET;
240 | }
241 | return bitstatus;
242 | }
243 |
244 | /**
245 | * @brief Clears the EXTI's line pending flags.
246 | * @param EXTI_Line: specifies the EXTI lines flags to clear.
247 | * This parameter can be any combination of EXTI_Linex where x can be (0..22)
248 | * @retval None
249 | */
250 | void EXTI_ClearFlag(uint32_t EXTI_Line)
251 | {
252 | /* Check the parameters */
253 | assert_param(IS_EXTI_LINE(EXTI_Line));
254 |
255 | EXTI->PR = EXTI_Line;
256 | }
257 |
258 | /**
259 | * @brief Checks whether the specified EXTI line is asserted or not.
260 | * @param EXTI_Line: specifies the EXTI line to check.
261 | * This parameter can be EXTI_Linex where x can be(0..22)
262 | * @retval The new state of EXTI_Line (SET or RESET).
263 | */
264 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
265 | {
266 | FlagStatus bitstatus = RESET;
267 | /* Check the parameters */
268 | assert_param(IS_GET_EXTI_LINE(EXTI_Line));
269 |
270 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
271 | {
272 | bitstatus = SET;
273 | }
274 | else
275 | {
276 | bitstatus = RESET;
277 | }
278 | return bitstatus;
279 |
280 | }
281 |
282 | /**
283 | * @brief Clears the EXTI's line pending bits.
284 | * @param EXTI_Line: specifies the EXTI lines to clear.
285 | * This parameter can be any combination of EXTI_Linex where x can be (0..22)
286 | * @retval None
287 | */
288 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
289 | {
290 | /* Check the parameters */
291 | assert_param(IS_EXTI_LINE(EXTI_Line));
292 |
293 | EXTI->PR = EXTI_Line;
294 | }
295 |
296 | /**
297 | * @}
298 | */
299 |
300 | /**
301 | * @}
302 | */
303 |
304 | /**
305 | * @}
306 | */
307 |
308 | /**
309 | * @}
310 | */
311 |
312 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
313 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/src/stm32f4xx_flash_ramfunc.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_flash_ramfunc.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief FLASH RAMFUNC module driver.
8 | * This file provides a FLASH firmware functions which should be
9 | * executed from internal SRAM
10 | * + Stop/Start the flash interface while System Run
11 | * + Enable/Disable the flash sleep while System Run
12 | *
13 | @verbatim
14 | ==============================================================================
15 | ##### APIs executed from Internal RAM #####
16 | ==============================================================================
17 | [..]
18 | *** ARM Compiler ***
19 | --------------------
20 | [..] RAM functions are defined using the toolchain options.
21 | Functions that are be executed in RAM should reside in a separate
22 | source module. Using the 'Options for File' dialog you can simply change
23 | the 'Code / Const' area of a module to a memory space in physical RAM.
24 | Available memory areas are declared in the 'Target' tab of the
25 | Options for Target' dialog.
26 |
27 | *** ICCARM Compiler ***
28 | -----------------------
29 | [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
30 |
31 | *** GNU Compiler ***
32 | --------------------
33 | [..] RAM functions are defined using a specific toolchain attribute
34 | "__attribute__((section(".RamFunc")))".
35 |
36 | @endverbatim
37 | ******************************************************************************
38 | * @attention
39 | *
40 | * © COPYRIGHT 2016 STMicroelectronics
41 | *
42 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
43 | * You may not use this file except in compliance with the License.
44 | * You may obtain a copy of the License at:
45 | *
46 | * http://www.st.com/software_license_agreement_liberty_v2
47 | *
48 | * Unless required by applicable law or agreed to in writing, software
49 | * distributed under the License is distributed on an "AS IS" BASIS,
50 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
51 | * See the License for the specific language governing permissions and
52 | * limitations under the License.
53 | *
54 | ******************************************************************************
55 | */
56 |
57 | /* Includes ------------------------------------------------------------------*/
58 | #include "stm32f4xx_flash_ramfunc.h"
59 |
60 | /** @addtogroup STM32F4xx_StdPeriph_Driver
61 | * @{
62 | */
63 |
64 | /** @defgroup FLASH RAMFUNC
65 | * @brief FLASH RAMFUNC driver modules
66 | * @{
67 | */
68 |
69 | /* Private typedef -----------------------------------------------------------*/
70 | /* Private define ------------------------------------------------------------*/
71 | /* Private macro -------------------------------------------------------------*/
72 | /* Private variables ---------------------------------------------------------*/
73 | /* Private function prototypes -----------------------------------------------*/
74 | /* Private functions ---------------------------------------------------------*/
75 |
76 | /** @defgroup FLASH_RAMFUNC_Private_Functions
77 | * @{
78 | */
79 |
80 | /** @defgroup FLASH_RAMFUNC_Group1 Peripheral features functions executed from internal RAM
81 | * @brief Peripheral Extended features functions
82 | *
83 | @verbatim
84 |
85 | ===============================================================================
86 | ##### ramfunc functions #####
87 | ===============================================================================
88 | [..]
89 | This subsection provides a set of functions that should be executed from RAM
90 | transfers.
91 |
92 | @endverbatim
93 | * @{
94 | */
95 |
96 | /**
97 | * @brief Start/Stop the flash interface while System Run
98 | * @note This mode is only available for STM32F411xx devices.
99 | * @note This mode could n't be set while executing with the flash itself.
100 | * It should be done with specific routine executed from RAM.
101 | * @param NewState: new state of the Smart Card mode.
102 | * This parameter can be: ENABLE or DISABLE.
103 | * @retval None
104 | */
105 | __RAM_FUNC FLASH_FlashInterfaceCmd(FunctionalState NewState)
106 | {
107 | if (NewState != DISABLE)
108 | {
109 | /* Start the flash interface while System Run */
110 | CLEAR_BIT(PWR->CR, PWR_CR_FISSR);
111 | }
112 | else
113 | {
114 | /* Stop the flash interface while System Run */
115 | SET_BIT(PWR->CR, PWR_CR_FISSR);
116 | }
117 | }
118 |
119 | /**
120 | * @brief Enable/Disable the flash sleep while System Run
121 | * @note This mode is only available for STM32F411xx devices.
122 | * @note This mode could n't be set while executing with the flash itself.
123 | * It should be done with specific routine executed from RAM.
124 | * @param NewState: new state of the Smart Card mode.
125 | * This parameter can be: ENABLE or DISABLE.
126 | * @retval None
127 | */
128 | __RAM_FUNC FLASH_FlashSleepModeCmd(FunctionalState NewState)
129 | {
130 | if (NewState != DISABLE)
131 | {
132 | /* Enable the flash sleep while System Run */
133 | SET_BIT(PWR->CR, PWR_CR_FMSSR);
134 | }
135 | else
136 | {
137 | /* Disable the flash sleep while System Run */
138 | CLEAR_BIT(PWR->CR, PWR_CR_FMSSR);
139 | }
140 | }
141 |
142 | /**
143 | * @}
144 | */
145 |
146 | /**
147 | * @}
148 | */
149 |
150 | /**
151 | * @}
152 | */
153 |
154 | /**
155 | * @}
156 | */
157 |
158 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
159 |
--------------------------------------------------------------------------------
/Driver/stm32f407/FWLIB/src/stm32f4xx_hash_md5.c:
--------------------------------------------------------------------------------
1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_hash_md5.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file provides high level functions to compute the HASH MD5 and
8 | * HMAC MD5 Digest of an input message.
9 | * It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
10 | * peripheral.
11 | *
12 | @verbatim
13 | ===================================================================
14 | ##### How to use this driver #####
15 | ===================================================================
16 | [..]
17 | (#) Enable The HASH controller clock using
18 | RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
19 |
20 | (#) Calculate the HASH MD5 Digest using HASH_MD5() function.
21 |
22 | (#) Calculate the HMAC MD5 Digest using HMAC_MD5() function.
23 |
24 | @endverbatim
25 | *
26 | ******************************************************************************
27 | * @attention
28 | *
29 | * © COPYRIGHT 2016 STMicroelectronics
30 | *
31 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
32 | * You may not use this file except in compliance with the License.
33 | * You may obtain a copy of the License at:
34 | *
35 | * http://www.st.com/software_license_agreement_liberty_v2
36 | *
37 | * Unless required by applicable law or agreed to in writing, software
38 | * distributed under the License is distributed on an "AS IS" BASIS,
39 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
40 | * See the License for the specific language governing permissions and
41 | * limitations under the License.
42 | *
43 | ******************************************************************************
44 | */
45 |
46 | /* Includes ------------------------------------------------------------------*/
47 | #include "stm32f4xx_hash.h"
48 |
49 | /** @addtogroup STM32F4xx_StdPeriph_Driver
50 | * @{
51 | */
52 |
53 | /** @defgroup HASH
54 | * @brief HASH driver modules
55 | * @{
56 | */
57 |
58 | /* Private typedef -----------------------------------------------------------*/
59 | /* Private define ------------------------------------------------------------*/
60 | #define MD5BUSY_TIMEOUT ((uint32_t) 0x00010000)
61 |
62 | /* Private macro -------------------------------------------------------------*/
63 | /* Private variables ---------------------------------------------------------*/
64 | /* Private function prototypes -----------------------------------------------*/
65 | /* Private functions ---------------------------------------------------------*/
66 |
67 | /** @defgroup HASH_Private_Functions
68 | * @{
69 | */
70 |
71 | /** @defgroup HASH_Group7 High Level MD5 functions
72 | * @brief High Level MD5 Hash and HMAC functions
73 | *
74 | @verbatim
75 | ===============================================================================
76 | ##### High Level MD5 Hash and HMAC functions #####
77 | ===============================================================================
78 |
79 |
80 | @endverbatim
81 | * @{
82 | */
83 |
84 | /**
85 | * @brief Compute the HASH MD5 digest.
86 | * @param Input: pointer to the Input buffer to be treated.
87 | * @param Ilen: length of the Input buffer.
88 | * @param Output: the returned digest
89 | * @retval An ErrorStatus enumeration value:
90 | * - SUCCESS: digest computation done
91 | * - ERROR: digest computation failed
92 | */
93 | ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
94 | {
95 | HASH_InitTypeDef MD5_HASH_InitStructure;
96 | HASH_MsgDigest MD5_MessageDigest;
97 | __IO uint16_t nbvalidbitsdata = 0;
98 | uint32_t i = 0;
99 | __IO uint32_t counter = 0;
100 | uint32_t busystatus = 0;
101 | ErrorStatus status = SUCCESS;
102 | uint32_t inputaddr = (uint32_t)Input;
103 | uint32_t outputaddr = (uint32_t)Output;
104 |
105 |
106 | /* Number of valid bits in last word of the Input data */
107 | nbvalidbitsdata = 8 * (Ilen % 4);
108 |
109 | /* HASH peripheral initialization */
110 | HASH_DeInit();
111 |
112 | /* HASH Configuration */
113 | MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
114 | MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
115 | MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
116 | HASH_Init(&MD5_HASH_InitStructure);
117 |
118 | /* Configure the number of valid bits in last word of the data */
119 | HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
120 |
121 | /* Write the Input block in the IN FIFO */
122 | for(i=0; i 64)
197 | {
198 | /* HMAC long Key */
199 | MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
200 | }
201 | else
202 | {
203 | /* HMAC short Key */
204 | MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
205 | }
206 | HASH_Init(&MD5_HASH_InitStructure);
207 |
208 | /* Configure the number of valid bits in last word of the Key */
209 | HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
210 |
211 | /* Write the Key */
212 | for(i=0; i© COPYRIGHT 2016 STMicroelectronics
30 | *
31 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
32 | * You may not use this file except in compliance with the License.
33 | * You may obtain a copy of the License at:
34 | *
35 | * http://www.st.com/software_license_agreement_liberty_v2
36 | *
37 | * Unless required by applicable law or agreed to in writing, software
38 | * distributed under the License is distributed on an "AS IS" BASIS,
39 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
40 | * See the License for the specific language governing permissions and
41 | * limitations under the License.
42 | *
43 | ******************************************************************************
44 | */
45 |
46 | /* Includes ------------------------------------------------------------------*/
47 | #include "stm32f4xx_hash.h"
48 |
49 | /** @addtogroup STM32F4xx_StdPeriph_Driver
50 | * @{
51 | */
52 |
53 | /** @defgroup HASH
54 | * @brief HASH driver modules
55 | * @{
56 | */
57 |
58 | /* Private typedef -----------------------------------------------------------*/
59 | /* Private define ------------------------------------------------------------*/
60 | #define SHA1BUSY_TIMEOUT ((uint32_t) 0x00010000)
61 |
62 | /* Private macro -------------------------------------------------------------*/
63 | /* Private variables ---------------------------------------------------------*/
64 | /* Private function prototypes -----------------------------------------------*/
65 | /* Private functions ---------------------------------------------------------*/
66 |
67 | /** @defgroup HASH_Private_Functions
68 | * @{
69 | */
70 |
71 | /** @defgroup HASH_Group6 High Level SHA1 functions
72 | * @brief High Level SHA1 Hash and HMAC functions
73 | *
74 | @verbatim
75 | ===============================================================================
76 | ##### High Level SHA1 Hash and HMAC functions #####
77 | ===============================================================================
78 |
79 |
80 | @endverbatim
81 | * @{
82 | */
83 |
84 | /**
85 | * @brief Compute the HASH SHA1 digest.
86 | * @param Input: pointer to the Input buffer to be treated.
87 | * @param Ilen: length of the Input buffer.
88 | * @param Output: the returned digest
89 | * @retval An ErrorStatus enumeration value:
90 | * - SUCCESS: digest computation done
91 | * - ERROR: digest computation failed
92 | */
93 | ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
94 | {
95 | HASH_InitTypeDef SHA1_HASH_InitStructure;
96 | HASH_MsgDigest SHA1_MessageDigest;
97 | __IO uint16_t nbvalidbitsdata = 0;
98 | uint32_t i = 0;
99 | __IO uint32_t counter = 0;
100 | uint32_t busystatus = 0;
101 | ErrorStatus status = SUCCESS;
102 | uint32_t inputaddr = (uint32_t)Input;
103 | uint32_t outputaddr = (uint32_t)Output;
104 |
105 | /* Number of valid bits in last word of the Input data */
106 | nbvalidbitsdata = 8 * (Ilen % 4);
107 |
108 | /* HASH peripheral initialization */
109 | HASH_DeInit();
110 |
111 | /* HASH Configuration */
112 | SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
113 | SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
114 | SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
115 | HASH_Init(&SHA1_HASH_InitStructure);
116 |
117 | /* Configure the number of valid bits in last word of the data */
118 | HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
119 |
120 | /* Write the Input block in the IN FIFO */
121 | for(i=0; i 64)
198 | {
199 | /* HMAC long Key */
200 | SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
201 | }
202 | else
203 | {
204 | /* HMAC short Key */
205 | SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
206 | }
207 | HASH_Init(&SHA1_HASH_InitStructure);
208 |
209 | /* Configure the number of valid bits in last word of the Key */
210 | HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
211 |
212 | /* Write the Key */
213 | for(i=0; i© COPYRIGHT 2016 STMicroelectronics
68 | *
69 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
70 | * You may not use this file except in compliance with the License.
71 | * You may obtain a copy of the License at:
72 | *
73 | * http://www.st.com/software_license_agreement_liberty_v2
74 | *
75 | * Unless required by applicable law or agreed to in writing, software
76 | * distributed under the License is distributed on an "AS IS" BASIS,
77 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
78 | * See the License for the specific language governing permissions and
79 | * limitations under the License.
80 | *
81 | ******************************************************************************
82 | */
83 |
84 | /* Includes ------------------------------------------------------------------*/
85 | #include "stm32f4xx_iwdg.h"
86 |
87 | /** @addtogroup STM32F4xx_StdPeriph_Driver
88 | * @{
89 | */
90 |
91 | /** @defgroup IWDG
92 | * @brief IWDG driver modules
93 | * @{
94 | */
95 |
96 | /* Private typedef -----------------------------------------------------------*/
97 | /* Private define ------------------------------------------------------------*/
98 |
99 | /* KR register bit mask */
100 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA)
101 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC)
102 |
103 | /* Private macro -------------------------------------------------------------*/
104 | /* Private variables ---------------------------------------------------------*/
105 | /* Private function prototypes -----------------------------------------------*/
106 | /* Private functions ---------------------------------------------------------*/
107 |
108 | /** @defgroup IWDG_Private_Functions
109 | * @{
110 | */
111 |
112 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
113 | * @brief Prescaler and Counter configuration functions
114 | *
115 | @verbatim
116 | ===============================================================================
117 | ##### Prescaler and Counter configuration functions #####
118 | ===============================================================================
119 |
120 | @endverbatim
121 | * @{
122 | */
123 |
124 | /**
125 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
126 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
127 | * This parameter can be one of the following values:
128 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
129 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
130 | * @retval None
131 | */
132 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
133 | {
134 | /* Check the parameters */
135 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
136 | IWDG->KR = IWDG_WriteAccess;
137 | }
138 |
139 | /**
140 | * @brief Sets IWDG Prescaler value.
141 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
142 | * This parameter can be one of the following values:
143 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
144 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
145 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
146 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
147 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
148 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
149 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
150 | * @retval None
151 | */
152 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
153 | {
154 | /* Check the parameters */
155 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
156 | IWDG->PR = IWDG_Prescaler;
157 | }
158 |
159 | /**
160 | * @brief Sets IWDG Reload value.
161 | * @param Reload: specifies the IWDG Reload value.
162 | * This parameter must be a number between 0 and 0x0FFF.
163 | * @retval None
164 | */
165 | void IWDG_SetReload(uint16_t Reload)
166 | {
167 | /* Check the parameters */
168 | assert_param(IS_IWDG_RELOAD(Reload));
169 | IWDG->RLR = Reload;
170 | }
171 |
172 | /**
173 | * @brief Reloads IWDG counter with value defined in the reload register
174 | * (write access to IWDG_PR and IWDG_RLR registers disabled).
175 | * @param None
176 | * @retval None
177 | */
178 | void IWDG_ReloadCounter(void)
179 | {
180 | IWDG->KR = KR_KEY_RELOAD;
181 | }
182 |
183 | /**
184 | * @}
185 | */
186 |
187 | /** @defgroup IWDG_Group2 IWDG activation function
188 | * @brief IWDG activation function
189 | *
190 | @verbatim
191 | ===============================================================================
192 | ##### IWDG activation function #####
193 | ===============================================================================
194 |
195 | @endverbatim
196 | * @{
197 | */
198 |
199 | /**
200 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
201 | * @param None
202 | * @retval None
203 | */
204 | void IWDG_Enable(void)
205 | {
206 | IWDG->KR = KR_KEY_ENABLE;
207 | }
208 |
209 | /**
210 | * @}
211 | */
212 |
213 | /** @defgroup IWDG_Group3 Flag management function
214 | * @brief Flag management function
215 | *
216 | @verbatim
217 | ===============================================================================
218 | ##### Flag management function #####
219 | ===============================================================================
220 |
221 | @endverbatim
222 | * @{
223 | */
224 |
225 | /**
226 | * @brief Checks whether the specified IWDG flag is set or not.
227 | * @param IWDG_FLAG: specifies the flag to check.
228 | * This parameter can be one of the following values:
229 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
230 | * @arg IWDG_FLAG_RVU: Reload Value Update on going
231 | * @retval The new state of IWDG_FLAG (SET or RESET).
232 | */
233 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
234 | {
235 | FlagStatus bitstatus = RESET;
236 | /* Check the parameters */
237 | assert_param(IS_IWDG_FLAG(IWDG_FLAG));
238 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
239 | {
240 | bitstatus = SET;
241 | }
242 | else
243 | {
244 | bitstatus = RESET;
245 | }
246 | /* Return the flag status */
247 | return bitstatus;
248 | }
249 |
250 | /**
251 | * @}
252 | */
253 |
254 | /**
255 | * @}
256 | */
257 |
258 | /**
259 | * @}
260 | */
261 |
262 | /**
263 | * @}
264 | */
265 |
266 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
267 |
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/Driver/stm32f407/FWLIB/src/stm32f4xx_wwdg.c:
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1 | /**
2 | ******************************************************************************
3 | * @file stm32f4xx_wwdg.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file provides firmware functions to manage the following
8 | * functionalities of the Window watchdog (WWDG) peripheral:
9 | * + Prescaler, Refresh window and Counter configuration
10 | * + WWDG activation
11 | * + Interrupts and flags management
12 | *
13 | @verbatim
14 | ===============================================================================
15 | ##### WWDG features #####
16 | ===============================================================================
17 | [..]
18 | Once enabled the WWDG generates a system reset on expiry of a programmed
19 | time period, unless the program refreshes the counter (downcounter)
20 | before to reach 0x3F value (i.e. a reset is generated when the counter
21 | value rolls over from 0x40 to 0x3F).
22 | An MCU reset is also generated if the counter value is refreshed
23 | before the counter has reached the refresh window value. This
24 | implies that the counter must be refreshed in a limited window.
25 |
26 | Once enabled the WWDG cannot be disabled except by a system reset.
27 |
28 | WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
29 | reset occurs.
30 |
31 | The WWDG counter input clock is derived from the APB clock divided
32 | by a programmable prescaler.
33 |
34 | WWDG counter clock = PCLK1 / Prescaler
35 | WWDG timeout = (WWDG counter clock) * (counter value)
36 |
37 | Min-max timeout value @42 MHz(PCLK1): ~97.5 us / ~49.9 ms
38 |
39 | ##### How to use this driver #####
40 | ===============================================================================
41 | [..]
42 | (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
43 |
44 | (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function
45 |
46 | (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function
47 |
48 | (#) Set the WWDG counter value and start it using WWDG_Enable() function.
49 | When the WWDG is enabled the counter value should be configured to
50 | a value greater than 0x40 to prevent generating an immediate reset.
51 |
52 | (#) Optionally you can enable the Early wakeup interrupt which is
53 | generated when the counter reach 0x40.
54 | Once enabled this interrupt cannot be disabled except by a system reset.
55 |
56 | (#) Then the application program must refresh the WWDG counter at regular
57 | intervals during normal operation to prevent an MCU reset, using
58 | WWDG_SetCounter() function. This operation must occur only when
59 | the counter value is lower than the refresh window value,
60 | programmed using WWDG_SetWindowValue().
61 |
62 | @endverbatim
63 | ******************************************************************************
64 | * @attention
65 | *
66 | * © COPYRIGHT 2016 STMicroelectronics
67 | *
68 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
69 | * You may not use this file except in compliance with the License.
70 | * You may obtain a copy of the License at:
71 | *
72 | * http://www.st.com/software_license_agreement_liberty_v2
73 | *
74 | * Unless required by applicable law or agreed to in writing, software
75 | * distributed under the License is distributed on an "AS IS" BASIS,
76 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
77 | * See the License for the specific language governing permissions and
78 | * limitations under the License.
79 | *
80 | ******************************************************************************
81 | */
82 |
83 | /* Includes ------------------------------------------------------------------*/
84 | #include "stm32f4xx_wwdg.h"
85 | #include "stm32f4xx_rcc.h"
86 |
87 | /** @addtogroup STM32F4xx_StdPeriph_Driver
88 | * @{
89 | */
90 |
91 | /** @defgroup WWDG
92 | * @brief WWDG driver modules
93 | * @{
94 | */
95 |
96 | /* Private typedef -----------------------------------------------------------*/
97 | /* Private define ------------------------------------------------------------*/
98 |
99 | /* ----------- WWDG registers bit address in the alias region ----------- */
100 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
101 | /* Alias word address of EWI bit */
102 | #define CFR_OFFSET (WWDG_OFFSET + 0x04)
103 | #define EWI_BitNumber 0x09
104 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
105 |
106 | /* --------------------- WWDG registers bit mask ------------------------ */
107 | /* CFR register bit mask */
108 | #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
109 | #define CFR_W_MASK ((uint32_t)0xFFFFFF80)
110 | #define BIT_MASK ((uint8_t)0x7F)
111 |
112 | /* Private macro -------------------------------------------------------------*/
113 | /* Private variables ---------------------------------------------------------*/
114 | /* Private function prototypes -----------------------------------------------*/
115 | /* Private functions ---------------------------------------------------------*/
116 |
117 | /** @defgroup WWDG_Private_Functions
118 | * @{
119 | */
120 |
121 | /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
122 | * @brief Prescaler, Refresh window and Counter configuration functions
123 | *
124 | @verbatim
125 | ===============================================================================
126 | ##### Prescaler, Refresh window and Counter configuration functions #####
127 | ===============================================================================
128 |
129 | @endverbatim
130 | * @{
131 | */
132 |
133 | /**
134 | * @brief Deinitializes the WWDG peripheral registers to their default reset values.
135 | * @param None
136 | * @retval None
137 | */
138 | void WWDG_DeInit(void)
139 | {
140 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
141 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
142 | }
143 |
144 | /**
145 | * @brief Sets the WWDG Prescaler.
146 | * @param WWDG_Prescaler: specifies the WWDG Prescaler.
147 | * This parameter can be one of the following values:
148 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
149 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
150 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
151 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
152 | * @retval None
153 | */
154 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
155 | {
156 | uint32_t tmpreg = 0;
157 | /* Check the parameters */
158 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
159 | /* Clear WDGTB[1:0] bits */
160 | tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
161 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
162 | tmpreg |= WWDG_Prescaler;
163 | /* Store the new value */
164 | WWDG->CFR = tmpreg;
165 | }
166 |
167 | /**
168 | * @brief Sets the WWDG window value.
169 | * @param WindowValue: specifies the window value to be compared to the downcounter.
170 | * This parameter value must be lower than 0x80.
171 | * @retval None
172 | */
173 | void WWDG_SetWindowValue(uint8_t WindowValue)
174 | {
175 | __IO uint32_t tmpreg = 0;
176 |
177 | /* Check the parameters */
178 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
179 | /* Clear W[6:0] bits */
180 |
181 | tmpreg = WWDG->CFR & CFR_W_MASK;
182 |
183 | /* Set W[6:0] bits according to WindowValue value */
184 | tmpreg |= WindowValue & (uint32_t) BIT_MASK;
185 |
186 | /* Store the new value */
187 | WWDG->CFR = tmpreg;
188 | }
189 |
190 | /**
191 | * @brief Enables the WWDG Early Wakeup interrupt(EWI).
192 | * @note Once enabled this interrupt cannot be disabled except by a system reset.
193 | * @param None
194 | * @retval None
195 | */
196 | void WWDG_EnableIT(void)
197 | {
198 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
199 | }
200 |
201 | /**
202 | * @brief Sets the WWDG counter value.
203 | * @param Counter: specifies the watchdog counter value.
204 | * This parameter must be a number between 0x40 and 0x7F (to prevent generating
205 | * an immediate reset)
206 | * @retval None
207 | */
208 | void WWDG_SetCounter(uint8_t Counter)
209 | {
210 | /* Check the parameters */
211 | assert_param(IS_WWDG_COUNTER(Counter));
212 | /* Write to T[6:0] bits to configure the counter value, no need to do
213 | a read-modify-write; writing a 0 to WDGA bit does nothing */
214 | WWDG->CR = Counter & BIT_MASK;
215 | }
216 | /**
217 | * @}
218 | */
219 |
220 | /** @defgroup WWDG_Group2 WWDG activation functions
221 | * @brief WWDG activation functions
222 | *
223 | @verbatim
224 | ===============================================================================
225 | ##### WWDG activation function #####
226 | ===============================================================================
227 |
228 | @endverbatim
229 | * @{
230 | */
231 |
232 | /**
233 | * @brief Enables WWDG and load the counter value.
234 | * @param Counter: specifies the watchdog counter value.
235 | * This parameter must be a number between 0x40 and 0x7F (to prevent generating
236 | * an immediate reset)
237 | * @retval None
238 | */
239 | void WWDG_Enable(uint8_t Counter)
240 | {
241 | /* Check the parameters */
242 | assert_param(IS_WWDG_COUNTER(Counter));
243 | WWDG->CR = WWDG_CR_WDGA | Counter;
244 | }
245 | /**
246 | * @}
247 | */
248 |
249 | /** @defgroup WWDG_Group3 Interrupts and flags management functions
250 | * @brief Interrupts and flags management functions
251 | *
252 | @verbatim
253 | ===============================================================================
254 | ##### Interrupts and flags management functions #####
255 | ===============================================================================
256 |
257 | @endverbatim
258 | * @{
259 | */
260 |
261 | /**
262 | * @brief Checks whether the Early Wakeup interrupt flag is set or not.
263 | * @param None
264 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
265 | */
266 | FlagStatus WWDG_GetFlagStatus(void)
267 | {
268 | FlagStatus bitstatus = RESET;
269 |
270 | if ((WWDG->SR) != (uint32_t)RESET)
271 | {
272 | bitstatus = SET;
273 | }
274 | else
275 | {
276 | bitstatus = RESET;
277 | }
278 | return bitstatus;
279 | }
280 |
281 | /**
282 | * @brief Clears Early Wakeup interrupt flag.
283 | * @param None
284 | * @retval None
285 | */
286 | void WWDG_ClearFlag(void)
287 | {
288 | WWDG->SR = (uint32_t)RESET;
289 | }
290 |
291 | /**
292 | * @}
293 | */
294 |
295 | /**
296 | * @}
297 | */
298 |
299 | /**
300 | * @}
301 | */
302 |
303 | /**
304 | * @}
305 | */
306 |
307 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
308 |
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/Driver/stm32f407/LED0/led.h:
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1 | #ifndef LED_H
2 | #define LED_H
3 | #include "stm32f4xx.h"
4 | void InitLed0(void);
5 | #endif
6 |
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/Driver/stm32f407/Timer/Timer.h:
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1 | #ifndef TIMER_H
2 | #define TIMER_H
3 | #include "stm32f4xx.h"
4 |
5 | void Stm32Timer3Init(void);
6 | void Stm32Timer3ShutDown(void);
7 | #endif
8 |
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1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_conf.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief Library configuration file.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F4xx_CONF_H
30 | #define __STM32F4xx_CONF_H
31 |
32 | /* Includes ------------------------------------------------------------------*/
33 | /* Uncomment the line below to enable peripheral header file inclusion */
34 | #include "stm32f4xx_adc.h"
35 | #include "stm32f4xx_crc.h"
36 | #include "stm32f4xx_dbgmcu.h"
37 | #include "stm32f4xx_dma.h"
38 | #include "stm32f4xx_exti.h"
39 | #include "stm32f4xx_flash.h"
40 | #include "stm32f4xx_gpio.h"
41 | #include "stm32f4xx_i2c.h"
42 | #include "stm32f4xx_iwdg.h"
43 | #include "stm32f4xx_pwr.h"
44 | #include "stm32f4xx_rcc.h"
45 | #include "stm32f4xx_rtc.h"
46 | #include "stm32f4xx_sdio.h"
47 | #include "stm32f4xx_spi.h"
48 | #include "stm32f4xx_syscfg.h"
49 | #include "stm32f4xx_tim.h"
50 | #include "stm32f4xx_usart.h"
51 | #include "stm32f4xx_wwdg.h"
52 | #include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
53 |
54 | #if defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
55 | #include "stm32f4xx_cryp.h"
56 | #include "stm32f4xx_hash.h"
57 | #include "stm32f4xx_rng.h"
58 | #include "stm32f4xx_can.h"
59 | #include "stm32f4xx_dac.h"
60 | #include "stm32f4xx_dcmi.h"
61 | #include "stm32f4xx_dma2d.h"
62 | #include "stm32f4xx_fmc.h"
63 | #include "stm32f4xx_ltdc.h"
64 | #include "stm32f4xx_sai.h"
65 | #endif /* STM32F429_439xx || STM32F446xx || STM32F469_479xx */
66 |
67 | #if defined(STM32F427_437xx)
68 | #include "stm32f4xx_cryp.h"
69 | #include "stm32f4xx_hash.h"
70 | #include "stm32f4xx_rng.h"
71 | #include "stm32f4xx_can.h"
72 | #include "stm32f4xx_dac.h"
73 | #include "stm32f4xx_dcmi.h"
74 | #include "stm32f4xx_dma2d.h"
75 | #include "stm32f4xx_fmc.h"
76 | #include "stm32f4xx_sai.h"
77 | #endif /* STM32F427_437xx */
78 |
79 | #if defined(STM32F40_41xxx)
80 | #include "stm32f4xx_cryp.h"
81 | #include "stm32f4xx_hash.h"
82 | #include "stm32f4xx_rng.h"
83 | #include "stm32f4xx_can.h"
84 | #include "stm32f4xx_dac.h"
85 | #include "stm32f4xx_dcmi.h"
86 | #include "stm32f4xx_fsmc.h"
87 | #endif /* STM32F40_41xxx */
88 |
89 | #if defined(STM32F410xx)
90 | #include "stm32f4xx_rng.h"
91 | #include "stm32f4xx_dac.h"
92 | #endif /* STM32F410xx */
93 |
94 | #if defined(STM32F411xE)
95 | #include "stm32f4xx_flash_ramfunc.h"
96 | #endif /* STM32F411xE */
97 |
98 | #if defined(STM32F446xx) || defined(STM32F469_479xx)
99 | #include "stm32f4xx_qspi.h"
100 | #endif /* STM32F446xx || STM32F469_479xx */
101 |
102 | #if defined(STM32F410xx) || defined(STM32F446xx)
103 | #include "stm32f4xx_fmpi2c.h"
104 | #endif /* STM32F410xx || STM32F446xx */
105 |
106 | #if defined(STM32F446xx)
107 | #include "stm32f4xx_spdifrx.h"
108 | #include "stm32f4xx_cec.h"
109 | #endif /* STM32F446xx */
110 |
111 | #if defined(STM32F469_479xx)
112 | #include "stm32f4xx_dsi.h"
113 | #endif /* STM32F469_479xx */
114 |
115 | #if defined(STM32F410xx)
116 | #include "stm32f4xx_lptim.h"
117 | #endif /* STM32F410xx */
118 |
119 | #if defined(STM32F412xG)
120 | #include "stm32f4xx_rng.h"
121 | #include "stm32f4xx_can.h"
122 | #include "stm32f4xx_qspi.h"
123 | #include "stm32f4xx_rng.h"
124 | #include "stm32f4xx_fsmc.h"
125 | #include "stm32f4xx_dfsdm.h"
126 | #endif /* STM32F412xG */
127 |
128 | #if defined(STM32F413_423xx)
129 | #include "stm32f4xx_cryp.h"
130 | #include "stm32f4xx_fmpi2c.h"
131 | #include "stm32f4xx_rng.h"
132 | #include "stm32f4xx_can.h"
133 | #include "stm32f4xx_qspi.h"
134 | #include "stm32f4xx_rng.h"
135 | #include "stm32f4xx_fsmc.h"
136 | #include "stm32f4xx_dfsdm.h"
137 | #endif /* STM32F413_423xx */
138 |
139 | /* Exported types ------------------------------------------------------------*/
140 | /* Exported constants --------------------------------------------------------*/
141 |
142 | /* If an external clock source is used, then the value of the following define
143 | should be set to the value of the external clock source, else, if no external
144 | clock is used, keep this define commented */
145 | /*#define I2S_EXTERNAL_CLOCK_VAL 12288000 */ /* Value of the external clock in Hz */
146 |
147 |
148 | /* Uncomment the line below to expanse the "assert_param" macro in the
149 | Standard Peripheral Library drivers code */
150 | /* #define USE_FULL_ASSERT 1 */
151 |
152 | /* Exported macro ------------------------------------------------------------*/
153 | #ifdef USE_FULL_ASSERT
154 |
155 | /**
156 | * @brief The assert_param macro is used for function's parameters check.
157 | * @param expr: If expr is false, it calls assert_failed function
158 | * which reports the name of the source file and the source
159 | * line number of the call that failed.
160 | * If expr is true, it returns no value.
161 | * @retval None
162 | */
163 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
164 | /* Exported functions ------------------------------------------------------- */
165 | void assert_failed(uint8_t* file, uint32_t line);
166 | #else
167 | #define assert_param(expr) ((void)0)
168 | #endif /* USE_FULL_ASSERT */
169 |
170 | #endif /* __STM32F4xx_CONF_H */
171 |
172 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
173 |
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/Driver/stm32f407/USER/stm32f4xx_it.c:
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1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.c
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief Main Interrupt Service Routines.
8 | * This file provides template for all exceptions handler and
9 | * peripherals interrupt service routine.
10 | ******************************************************************************
11 | * @attention
12 | *
13 | * © COPYRIGHT 2016 STMicroelectronics
14 | *
15 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
16 | * You may not use this file except in compliance with the License.
17 | * You may obtain a copy of the License at:
18 | *
19 | * http://www.st.com/software_license_agreement_liberty_v2
20 | *
21 | * Unless required by applicable law or agreed to in writing, software
22 | * distributed under the License is distributed on an "AS IS" BASIS,
23 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
24 | * See the License for the specific language governing permissions and
25 | * limitations under the License.
26 | *
27 | ******************************************************************************
28 | */
29 |
30 | /* Includes ------------------------------------------------------------------*/
31 | #include "stm32f4xx_it.h"
32 |
33 |
34 | /** @addtogroup Template_Project
35 | * @{
36 | */
37 |
38 | /* Private typedef -----------------------------------------------------------*/
39 | /* Private define ------------------------------------------------------------*/
40 | /* Private macro -------------------------------------------------------------*/
41 | /* Private variables ---------------------------------------------------------*/
42 | /* Private function prototypes -----------------------------------------------*/
43 | /* Private functions ---------------------------------------------------------*/
44 |
45 | /******************************************************************************/
46 | /* Cortex-M4 Processor Exceptions Handlers */
47 | /******************************************************************************/
48 |
49 | /**
50 | * @brief This function handles NMI exception.
51 | * @param None
52 | * @retval None
53 | */
54 | void NMI_Handler(void)
55 | {
56 | }
57 |
58 | /**
59 | * @brief This function handles Hard Fault exception.
60 | * @param None
61 | * @retval None
62 | */
63 | void HardFault_Handler(void)
64 | {
65 | /* Go to infinite loop when Hard Fault exception occurs */
66 | while (1)
67 | {
68 | }
69 | }
70 |
71 | /**
72 | * @brief This function handles Memory Manage exception.
73 | * @param None
74 | * @retval None
75 | */
76 | void MemManage_Handler(void)
77 | {
78 | /* Go to infinite loop when Memory Manage exception occurs */
79 | while (1)
80 | {
81 | }
82 | }
83 |
84 | /**
85 | * @brief This function handles Bus Fault exception.
86 | * @param None
87 | * @retval None
88 | */
89 | void BusFault_Handler(void)
90 | {
91 | /* Go to infinite loop when Bus Fault exception occurs */
92 | while (1)
93 | {
94 | }
95 | }
96 |
97 | /**
98 | * @brief This function handles Usage Fault exception.
99 | * @param None
100 | * @retval None
101 | */
102 | void UsageFault_Handler(void)
103 | {
104 | /* Go to infinite loop when Usage Fault exception occurs */
105 | while (1)
106 | {
107 | }
108 | }
109 |
110 | /**
111 | * @brief This function handles SVCall exception.
112 | * @param None
113 | * @retval None
114 | */
115 | void SVC_Handler(void)
116 | {
117 | }
118 |
119 | /**
120 | * @brief This function handles Debug Monitor exception.
121 | * @param None
122 | * @retval None
123 | */
124 | void DebugMon_Handler(void)
125 | {
126 | }
127 |
128 | /**
129 | * @brief This function handles PendSVC exception.
130 | * @param None
131 | * @retval None
132 | */
133 | void PendSV_Handler(void)
134 | {
135 | }
136 |
137 | /**
138 | * @brief This function handles SysTick Handler.
139 | * @param None
140 | * @retval None
141 | */
142 | void SysTick_Handler(void)
143 | {
144 |
145 | }
146 |
147 | /******************************************************************************/
148 | /* STM32F4xx Peripherals Interrupt Handlers */
149 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
150 | /* available peripheral interrupt handler's name please refer to the startup */
151 | /* file (startup_stm32f4xx.s). */
152 | /******************************************************************************/
153 |
154 | /**
155 | * @brief This function handles PPP interrupt request.
156 | * @param None
157 | * @retval None
158 | */
159 | /*void PPP_IRQHandler(void)
160 | {
161 | }*/
162 |
163 | /**
164 | * @}
165 | */
166 |
167 |
168 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
169 |
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/Driver/stm32f407/USER/stm32f4xx_it.h:
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1 | /**
2 | ******************************************************************************
3 | * @file Project/STM32F4xx_StdPeriph_Templates/stm32f4xx_it.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 04-November-2016
7 | * @brief This file contains the headers of the interrupt handlers.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /* Define to prevent recursive inclusion -------------------------------------*/
29 | #ifndef __STM32F4xx_IT_H
30 | #define __STM32F4xx_IT_H
31 |
32 | #ifdef __cplusplus
33 | extern "C" {
34 | #endif
35 |
36 | /* Includes ------------------------------------------------------------------*/
37 | #include "stm32f4xx.h"
38 |
39 | /* Exported types ------------------------------------------------------------*/
40 | /* Exported constants --------------------------------------------------------*/
41 | /* Exported macro ------------------------------------------------------------*/
42 | /* Exported functions ------------------------------------------------------- */
43 |
44 | void NMI_Handler(void);
45 | void HardFault_Handler(void);
46 | void MemManage_Handler(void);
47 | void BusFault_Handler(void);
48 | void UsageFault_Handler(void);
49 | void SVC_Handler(void);
50 | void DebugMon_Handler(void);
51 | void PendSV_Handler(void);
52 | void SysTick_Handler(void);
53 |
54 | #ifdef __cplusplus
55 | }
56 | #endif
57 |
58 | #endif /* __STM32F4xx_IT_H */
59 |
60 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
61 |
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1 | /**
2 | ******************************************************************************
3 | * @file system_stm32f4xx.h
4 | * @author MCD Application Team
5 | * @version V1.8.0
6 | * @date 09-November-2016
7 | * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices.
8 | ******************************************************************************
9 | * @attention
10 | *
11 | * © COPYRIGHT 2016 STMicroelectronics
12 | *
13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
14 | * You may not use this file except in compliance with the License.
15 | * You may obtain a copy of the License at:
16 | *
17 | * http://www.st.com/software_license_agreement_liberty_v2
18 | *
19 | * Unless required by applicable law or agreed to in writing, software
20 | * distributed under the License is distributed on an "AS IS" BASIS,
21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22 | * See the License for the specific language governing permissions and
23 | * limitations under the License.
24 | *
25 | ******************************************************************************
26 | */
27 |
28 | /** @addtogroup CMSIS
29 | * @{
30 | */
31 |
32 | /** @addtogroup stm32f4xx_system
33 | * @{
34 | */
35 |
36 | /**
37 | * @brief Define to prevent recursive inclusion
38 | */
39 | #ifndef __SYSTEM_STM32F4XX_H
40 | #define __SYSTEM_STM32F4XX_H
41 |
42 | #ifdef __cplusplus
43 | extern "C" {
44 | #endif
45 |
46 | /** @addtogroup STM32F4xx_System_Includes
47 | * @{
48 | */
49 |
50 | /**
51 | * @}
52 | */
53 |
54 |
55 | /** @addtogroup STM32F4xx_System_Exported_types
56 | * @{
57 | */
58 |
59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
60 |
61 |
62 | /**
63 | * @}
64 | */
65 |
66 | /** @addtogroup STM32F4xx_System_Exported_Constants
67 | * @{
68 | */
69 |
70 | /**
71 | * @}
72 | */
73 |
74 | /** @addtogroup STM32F4xx_System_Exported_Macros
75 | * @{
76 | */
77 |
78 | /**
79 | * @}
80 | */
81 |
82 | /** @addtogroup STM32F4xx_System_Exported_Functions
83 | * @{
84 | */
85 |
86 | extern void SystemInit(void);
87 | extern void SystemCoreClockUpdate(void);
88 | /**
89 | * @}
90 | */
91 |
92 | #ifdef __cplusplus
93 | }
94 | #endif
95 |
96 | #endif /*__SYSTEM_STM32F4XX_H */
97 |
98 | /**
99 | * @}
100 | */
101 |
102 | /**
103 | * @}
104 | */
105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
106 |
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/OsekNM_core/OsekNM.c:
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/README.md:
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1 | # OSEK_NM
2 | 基于OsekNM 2.5.3协议实现的OsekNM，跨平台的结构，目前只实现了STM32F407ZGT6平台的驱动。
3 |
4 | # 1. 目录结构
5 | 1.1 App目录是一个keil5工程，App/keil/Objects/OsekNM.hex是一个可以直接在STM32F407ZGT6平台运行的hex文件。
6 | 1.2 Driver目录包含了stm32f407子目录和Win7子目录，stm32f407目录下就是实现的STM32F407ZGT6平台的底层驱动，包括定时器和CAN模块的驱动，以及Stm32标准库的 东西；Win7子目录是在windows7平台下执行的一些文件；Driver_Common.c是一些公用的驱动，由OsekNM_core统一调用。
7 | 1.3 OsekNM_core实现了OsekNM 2.5.3协议的核心逻辑，OsekNM.c实现了对各个节点各状态的处理，OsekNMServer.c实现了OsekNM 2.5.3协议提供给应用程序的API。
8 |
9 | # 2. 移植
10 | 2.1 在Driver目录新建文件夹，保存新平台的驱动程序，新的平台下需要实现CAN模块和定时器及中断的驱动程序。
11 | 2.2 修改Driver_Common.c文件，修改TX_CAN_Transmit()函数，调用新平台发送CAN报文的CAN模块驱动程序，修改InitPlatform()函数，调用新平台初始化CAN模块和 定时器的函数；Recv_EveryMessage()被CAN接受报文中断服务函数调用。
12 | 2.3 修改Driver_Common.h文件，#define 新的平台，并包含驱动相关的头文件，#define NMID 新的网络管理报文ID，#define ADDR_SELF 新的节点源地址。
13 | 2.4 可以参考stm32f407的例子来实现自己平台的移植。
14 |
15 | # 3. 附注
16 | 整个代码移植到我的开发板，并且验证通过。
17 | 专门在Vspy平台实现了虚拟的网络管理节点。
18 | 如果在移植过程遇到问题，可以联系我。
19 | 微信：ys18908109394
20 | qq: 1175818152
21 |
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/ReadMe.txt:
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1 | 基于OsekNM 2.5.3协议实现的OsekNM，跨平台的结构，目前只实现了STM32F407ZGT6平台的驱动。
2 | 1. 目录结构
3 | 1.1 App目录是一个keil5工程，App/keil/Objects/OsekNM.hex是一个可以直接在STM32F407ZGT6平台运 行的hex文件。
4 | 1.2 Driver目录包含了stm32f407子目录和Win7子目录，stm32f407目录下就是实现的STM32F407ZGT6平台的底层驱动，包括定时器和CAN模块的驱动，以及Stm32标准库的东西；Win7子目录是在windows7平台下执行的一些文件；Driver_Common.c是一些公用的驱动，由OsekNM_core统一调用。
5 |
6 | 1.3 OsekNM_core实现了OsekNM 2.5.3协议的核心逻辑，OsekNM.c实现了对各个节点各状态的处理，OsekNMServer.c实现了OsekNM 2.5.3协议提供给应用程序的API。
7 |
8 | 2. 移植
9 | 2.1 在Driver目录新建文件夹，保存新平台的驱动程序，新的平台下需要实现CAN模块和定时器及中断的驱动程序。
10 | 2.2 修改Driver_Common.c文件，修改TX_CAN_Transmit()函数，调用新平台发送CAN报文的CAN模块驱动程序，修改InitPlatform()函数，调用新平台初始化CAN模块和定时器的函数；Recv_EveryMessage()被CAN接受报文中断服务函数调用。
11 | 2.3 修改Driver_Common.h文件，#define 新的平台，并包含驱动相关的头文件，#define NMID 新的网络管理报文ID，#define ADDR_SELF 新的节点源地址。
12 | 2.4 可以参考stm32f407的例子来实现自己平台的移植。
13 |
14 | 3. 附注
15 | 整个代码移植到我的开发板，并且在CANoe平台验证过。
16 | 专门在Vspy平台实现了虚拟的网络管理节点，需要的朋友可以联系。
17 | 如果在移植过程遇到问题，可以联系我。
18 | 微信：ys18908109394
19 | qq: 1175818152
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