├── .gitignore ├── COPYING ├── Makefile ├── Makefile.xilinx ├── README ├── bch.vh ├── bch_blank_ecc.v ├── bch_chien.v ├── bch_decoder.v ├── bch_defs.vh ├── bch_encode.v ├── bch_encode.vh ├── bch_error_dec.v ├── bch_error_one.v ├── bch_error_tmec.v ├── bch_math.v ├── bch_params.vh ├── bch_sigma_bma_noinv.v ├── bch_sigma_bma_parallel.v ├── bch_sigma_bma_serial.v ├── bch_syndrome.v ├── bch_syndrome.vh ├── bch_syndrome_method1.v ├── bch_syndrome_method2.v ├── benchmark ├── xilinx_decoder.sh ├── xilinx_decoder.v ├── xilinx_encode.sh ├── xilinx_encode.v ├── xilinx_error_dec.sh ├── xilinx_error_dec.v ├── xilinx_error_one.sh ├── xilinx_error_one.v ├── xilinx_error_tmec.sh ├── xilinx_error_tmec.v ├── xilinx_inverter.sh ├── xilinx_inverter.v ├── xilinx_mdecoder.sh ├── xilinx_mdecoder.v ├── xilinx_noinv.sh ├── xilinx_noinv.v ├── xilinx_parallel.sh ├── xilinx_parallel.v ├── xilinx_serial.sh ├── xilinx_serial.v ├── xilinx_syndrome.sh └── xilinx_syndrome.v ├── compare_cla.v ├── config.vh ├── log2.vh ├── matrix.v ├── matrix.vh ├── scripts ├── benchmark.sh └── makedeps.sh ├── sim.v ├── tb_basis.v ├── tb_inverter.v ├── tb_mult.v ├── tb_sim.v ├── util.v └── xilinx.ucf /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | tb_sim 3 | *.vcd 4 | -------------------------------------------------------------------------------- /COPYING: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/russdill/bch_verilog/HEAD/COPYING -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/russdill/bch_verilog/HEAD/Makefile -------------------------------------------------------------------------------- /Makefile.xilinx: -------------------------------------------------------------------------------- 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