├── CNAME ├── .gitignore ├── _config.yml ├── README.md └── blogs ├── cn ├── gitlab-runner-supports-riscv-20251021.md └── 20250907-PTS-Project-Announced.md └── en ├── gitlab-runner-supports-riscv-20251021.md └── 20250907-PTS-Project-Announced.md /CNAME: -------------------------------------------------------------------------------- 1 | rv2036.org -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.lock 2 | -------------------------------------------------------------------------------- /_config.yml: -------------------------------------------------------------------------------- 1 | title: Jiachen Project (甲辰计划) 2 | description: RISC-V Prosperity 2036 3 | remote_theme: pages-themes/architect@v0.2.0 4 | plugins: 5 | - jekyll-remote-theme 6 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Jiachen Project - RISC-V Prosperity 2036 2 | 3 | ## Background 4 | 5 | Today, the RISC-V ecosystem has entered a phase of exponential growth. In the past 18 months, RISC-V has seen breakthrough in high performance server chips, desktop operating systems, mobile and wearable devices, AIoT, automotive systems, information security, and many other fields. In 2025, we expect to see the number of developers growing past a million and RISC-V super computers will enter the TOP500 list (with TOP10 projected for 2030). 6 | 7 | With the development of computer architecture and foundational software platforms entering a “golden age” of rapid growth, open instruction set architectures such as RISC-V brought forth new scientific problems and engineering challenges. As leading contributors to the RISC-V ecosystem, we invite friends and experts around the globe to join us in this long-term collective effort to realize the goals of RISC-V Prosperity 2036. 8 | 9 | ## Vision & Mission 10 | 11 | 2024 is the year of the dragon, with 2036 coming up as the next. 12 | 13 | RISC-V Prosperity 2036 aims to realize a mature RISC-V’s hardware and software ecosystem akin to that of the other mainstream architectures by the next year of the dragon, 2036. This means mainstream-level maturity in applications such as datacenters, desktop computing, wearable technologies, and Internet of things - all implemented with systems of open standards and open source system software stacks. 14 | 15 | ## Goals 16 | 17 | 1. Bringing a joint effort of over 100 chip and solutions manufacturers and over 500 software development firms, in order to port, optimize, and deploy over 1,000 key commercial software packages across 18 essential industries. 18 | 2. Developing solutions suitable for commercial applications around high-performance RISC-V chips and IPs such as SG2380 and XiangShan, helping our target industries. These industries include AI acceleration, edge computing, storage, robotics, computer-assisted industrial simulation, computer-assisted medical solutions, and many more. 19 | 3. Building a human resource development effort for RISC-V to network over 10,000 potential experts in RISC-V chip design, software development, community management, as well as education and training. This will allow us to enable a industry-wide human resource network. 20 | 21 | ## Project Home 22 | 23 | - Website: [https://rv2036.org](https://rv2036.org) 24 | - GitHub: [gh/rv2036/](https://github.com/rv2036/) 25 | 26 | ## Members 27 | 28 | Meet our members :[gh/rv2036/jiachen-community](https://github.com/rv2036/jiachen-community/blob/main/members.md) 29 | -------------------------------------------------------------------------------- /blogs/cn/gitlab-runner-supports-riscv-20251021.md: -------------------------------------------------------------------------------- 1 | A Big Step: After 11 months of review, GitLab officially merged RISC-V Runner support! 2 | 3 | TL;DR: GitLab Runners now have official RISC-V binary versions! This means that hundreds of thousands of open source software projects hosted by GitLab will be able to more easily incorporate RISC-V into their CI/CD processes. The RISC-V software ecosystem will usher in another major growth. 4 | 5 | GitLab, a popular open source end-to-end software development platform, hosts well-known projects such as Wireshark, KiCAD, QEMU, and wget. Its community open source version supports well-known open source projects such as GNOME, KDE, Debian, Arch, and Kali Linux. Today, RISC-V runner support was added to its official repository. The native RISC-V runner means faster running speed and more realistic test environment, which is a breakthrough in common code hosting platforms[1]. 6 | 7 | For projects hosted by GitLab, there will be no need to compile the RISC-V runner yourself in the future. CI/CD can directly use the official RISC-V runner binary for building without special configuration, which further facilitates project management and reduces the mental burden of developers in developing/configuring pipelines (workflows). 8 | 9 | The corresponding commit address [2], this Merge Request was provided by Meng Zhuo, an engineer at the Institute of Software, Chinese Academy of Sciences, and was finally merged after 11 months of careful review by GitLab upstream developers. 10 | 11 | GitLab is expected to provide an official RISC-V runtime environment in the future, narrowing the gap with the mainstream x86 and Arm architectures. 12 | 13 | Currently, the largest code hosting platform, such as GitHub, is limited by the fact that dotnet does not support RISC-V and the Azure platform does not have a corresponding RISC-V virtual machine. RISC-V runner is still not officially supported. There are only actions provided by enthusiasts, such as setup-riscv-gnu-toolchain [3] based on QEMU, run-on-architecture-riscv64-alpine [4], and RISC-V builders based on real development boards [5]. 14 | 15 | Contributor profile: Meng Zhuo is a PLCT Lab [7] development engineer, Go language RISC-V architecture maintainer [8], focusing on the development of RISC-V cloud native related applications. Welcome to follow his Github [6]. 16 | 17 | References: 18 | 19 | - [1] https://en.wikipedia.org/wiki/Comparison_of_source-code-hosting_facilities) 20 | - [2] https://gitlab.com/gitlab-org/gitlab-runner/-/merge_requests/5131 21 | - [3] https://github.com/marketplace/actions/setup-riscv-gnu-toolchain 22 | - [4] https://github.com/marketplace/actions/run-on-architecture-riscv64-alpine 23 | - [5] https://riscv.builders/ 24 | - [6] https://github.com/mengzhuo 25 | - [7] PLCT Lab is affiliated with the Intelligent Software Research Center (ISRC) of the Institute of Software, Chinese Academy of Sciences (ISCAS). 26 | - [8] [zh_cn] [Meng Zhuo: the way Go to RISC-V](https://mp.weixin.qq.com/s/cJ8AJjPEh-DqQBCKqPNsfg) 27 | -------------------------------------------------------------------------------- /blogs/en/gitlab-runner-supports-riscv-20251021.md: -------------------------------------------------------------------------------- 1 | A Big Step: After 11 months of review, GitLab officially merged RISC-V Runner support! 2 | 3 | TL;DR: GitLab Runners now have official RISC-V binary versions! This means that hundreds of thousands of open source software projects hosted by GitLab will be able to more easily incorporate RISC-V into their CI/CD processes. The RISC-V software ecosystem will usher in another major growth. 4 | 5 | GitLab, a popular open source end-to-end software development platform, hosts well-known projects such as Wireshark, KiCAD, QEMU, and wget. Its community open source version supports well-known open source projects such as GNOME, KDE, Debian, Arch, and Kali Linux. Today, RISC-V runner support was added to its official repository. The native RISC-V runner means faster running speed and more realistic test environment, which is a breakthrough in common code hosting platforms[1]. 6 | 7 | For projects hosted by GitLab, there will be no need to compile the RISC-V runner yourself in the future. CI/CD can directly use the official RISC-V runner binary for building without special configuration, which further facilitates project management and reduces the mental burden of developers in developing/configuring pipelines (workflows). 8 | 9 | The corresponding commit address [2], this Merge Request was provided by Meng Zhuo, an engineer at the Institute of Software, Chinese Academy of Sciences, and was finally merged after 11 months of careful review by GitLab upstream developers. 10 | 11 | GitLab is expected to provide an official RISC-V runtime environment in the future, narrowing the gap with the mainstream x86 and Arm architectures. 12 | 13 | Currently, the largest code hosting platform, such as GitHub, is limited by the fact that dotnet does not support RISC-V and the Azure platform does not have a corresponding RISC-V virtual machine. RISC-V runner is still not officially supported. There are only actions provided by enthusiasts, such as setup-riscv-gnu-toolchain [3] based on QEMU, run-on-architecture-riscv64-alpine [4], and RISC-V builders based on real development boards [5]. 14 | 15 | Contributor profile: Meng Zhuo is a PLCT Lab [7] development engineer, Go language RISC-V architecture maintainer [8], focusing on the development of RISC-V cloud native related applications. Welcome to follow his Github [6]. 16 | 17 | References: 18 | 19 | - [1] https://en.wikipedia.org/wiki/Comparison_of_source-code-hosting_facilities) 20 | - [2] https://gitlab.com/gitlab-org/gitlab-runner/-/merge_requests/5131 21 | - [3] https://github.com/marketplace/actions/setup-riscv-gnu-toolchain 22 | - [4] https://github.com/marketplace/actions/run-on-architecture-riscv64-alpine 23 | - [5] https://riscv.builders/ 24 | - [6] https://github.com/mengzhuo 25 | - [7] PLCT Lab is affiliated with the Intelligent Software Research Center (ISRC) of the Institute of Software, Chinese Academy of Sciences (ISCAS). 26 | - [8] [zh_cn] [Meng Zhuo: the way Go to RISC-V](https://mp.weixin.qq.com/s/cJ8AJjPEh-DqQBCKqPNsfg) 27 | -------------------------------------------------------------------------------- /blogs/cn/20250907-PTS-Project-Announced.md: -------------------------------------------------------------------------------- 1 | 是时候了：甲辰计划启动RISC-V开源软件性能跟踪平台（PTS）建设，关注全球重要开源软件RISC-V性能演化趋势并发布路线图；诚邀RISC-V厂商捐赠机器参与共建 2 | 3 | ## PTS的背景、使命、历史重要性 4 | RISC-V开源软件性能跟踪平台（Performance Tracking System, PTS）的想法最早诞生于2020年[1]，当时甲辰计划主理人吴伟先生作为RISC-V国际基金会的 Code Speed SIG 的联席主席，希望能够建设一个类似 Mozilla 的 `AreWeFastYet.com` 平台一样的可视化的愿系统，来跟踪包括 JavaScript Engines 在内的各种重要的开源软件在 RISC-V 芯片和系统上的性能。当时 RISC-V IP 和芯片的发展还聚焦在嵌入式领域，能够运行 Linux 桌面环境的开发板只有 SiFive Unmatched 等少量型号。 5 | 6 | 在当时PTS项目还是比较超前的，最大的顾虑也包括了如果过早的公开RISC-V芯片和Arm/X86的性能差距，有可能会对RISC-V的全球生态发展势头起到计划外的负面作用。 7 | 8 | Code Speed SIG 在成立一年之后因为各种原因解散并重组，PTS项目也就一直雪藏到了现在。期间PLCT实验室曾在2021、2023年数次尝试启动PTS的建设，但是由于各种资源限制和裁员分流等原因未能冲线。 9 | 10 | 2024年除夕，甲辰计划启动了，带来了转机。经过一年多的发展，已经有超过50家企业加入甲辰计划，**逐步形成了「RISC-V开发板随缘漂流计划」、「开源实习生联合招聘培养项目」等相互支撑的项目，使得PTS的建设可能性重新被提出。**甲辰计划目前已经积累了足够的场地赞助和运营支持（苦芽科技、英麒智能、PLCT实验室、合肥工业大学、大连理工大学等），并积累了最够多的RISC-V开发板设备（其中阿里巴巴达摩院玄铁团队捐赠了200套TH1520开发板LicheePi 4A），建设PTS所需要的启动阶段的硬件和资金支持已经就绪。 11 | PTS的建设和运营对于RISC-V全球生态系统的发展至关重要。目前RISC-V已经完成了在嵌入式等领域的覆盖，并正在朝着高性能计算和数据中心场景进行冲刺。全球开源软件生态对于RISC-V已经有了相当不错的功能性支持，往后的重点会是寻找各种提升速度的优化机会。有一个自动化性能测评系统以及由其产生的方便查询和对比的性能数据库，对于开发人员定位性能回退、寻找优化机会都会事半功倍。 12 | 13 | PTS将会作为一个开源项目托管在甲辰计划GitHub组织账号下。如果一切顺利，2025年10月1日起可以通过 `pts.rv2036.org` 进行访问。PTS收集到的所有的性能数据也将开源，并托管于 `https://github.com/rv2036` 组织账号下。 14 | 15 | ## 跟踪的开源软件和benchmark范围 16 | 17 | 以下是初始阶段规划纳入观测范围的软件。后续会逐步添加RISC-V社区关注的软件。性能测评套件常见的包括 SPEC CPU 20xx 系列、CoreMark 系列等。不同的语言和执行环境有不同的测试集合，PTS默认将会搜集尽可能多的开源免费测试集纳入跟踪范围。 18 | 19 | **编译工具链** 20 | - GNU Toolchain：包含C/C++、Fortran等语言的编译器的性能。 21 | - Clang/LLVM：包含Clang、Flang等语言的编译器的性能。 22 | - Rust Toolchain 23 | 24 | **虚拟机** 25 | - V8 26 | - Spidermonkey 27 | - OpenJDK 28 | - Jeandle 29 | - Go Runtime 30 | - LuaJIT 31 | - .NET 32 | 33 | **模拟器** 34 | - QEMU 35 | - Box64 36 | - Wine-CE 37 | 38 | **系统库和计算库、计算栈** 39 | - glibc 40 | - musl-c 41 | - llvm libc 42 | - OpenBLAS 43 | - llama.cpp 44 | - Eigen 45 | - Highway 46 | - 等等 47 | 48 | ## 跟踪的RISC-V芯片/系统范围 49 | 50 | **主力测试机型（设备充足）** 51 | - TH1520: SipeedLicheePi 4A 52 | - SG2042: Milk-V PioneerBox 53 | 54 | **标准测试机型（有至少1台设备可以长期稳定使用）** 55 | - EIC7700: Milk-V Megrez 56 | - K1: Sipeed LicheePi 3A 57 | 58 | **期待测试机型（还没有稳定机器，但是 call for donation）** 59 | - Sophgo SG2044 60 | - A210 61 | - SpacemiT K3 62 | - DP1000: Milk-V Titan 63 | 64 | ### 基准操作系统 65 | - RevyOS：玄铁IP系列默认使用的Debian发行版 66 | - KarsierOS：苦芽科技基于openEuler社区版开发维护的商业维护版本 67 | - Ubuntu：Canonical 对部分 RISC-V 开发板原生支持 68 | - deepin：甲辰计划成员社区，在图形化界面方面很有本土化优势 69 | - openKylin：甲辰计划成员社区，在图形化界面方面很有本土化优势 70 | 71 | ## 对比基线的选择 72 | PTS将会陆续引入以下硬件系统作为非RISC-V架构的参考对比： 73 | - RaspberryPi 4B - 2025Q3 74 | - RaspberryPi 5 - 2025Q4 - call for donation 75 | - Mac mini w/ M1 - 2025Q4 - call for donation 76 | - AMD9950x - 2026Q1 - call for donation 77 | - Mac mini w/ M4 - 2026Q2 - call for donation 78 | 79 | 80 | ## 路线图及成果发布 81 | 82 | 自2025Q4开始，PTS将会在每个季度结束之后15日内发布「RISC-V性能提升报告」。 83 | 84 | **2025Q3** 85 | - PTS开始筹建。 86 | - 首批RISC-V设备上线（TH1520、SG2042、香山南湖单核）。 87 | - V8进入PTS观测范围。 88 | - 基线RaspberryPi 4B 上线 89 | 90 | **2025Q4** 91 | - 「RISC-V性能提升报告」创刊号发布。 92 | - Spidermonkey进入观测范围。 93 | - GNU Toolchain进入观测范围。 94 | - Clang/LLVM进入观测范围。 95 | - SPEC CPU 2006/2017 进入观测范围。 96 | - 香山南湖四核上线 97 | - 超睿DP100（Milk-V Titan）上线 98 | - ESWIN EIC7700 SBC 上线 99 | - Mac mini M1 上线 100 | - RaspberryPi 5 上线 101 | 102 | **2026Q1*8 103 | - A210设备上线 104 | - 香山昆明湖系列芯片上线 105 | - 蓝芯CPU上线（TBD） 106 | 107 | **2026Q2** 108 | - 测试测评设备增加至100台、超过20种。 109 | - 常用开源数据库进入测评范围。 110 | - 增加稳定性测试。 111 | 112 | **2026Q3** 113 | - 测试设备增加至200台、完成对所有流行 114 | - 所有HPC相关的常见开源测试集纳入测评范围。 115 | 116 | **2026Q4** 117 | - 所有数据中心关注的测评指标进入观测范围。 118 | 119 | **2027Q1** 120 | - 进入稳定维护状态。 121 | - 测评硬件设备超过500台（套），跟踪软件项目超过100个，性能指标超过1000个。 122 | - 添加至少2款128核RISC-V处理器。 123 | 124 | ## 与开源社区和开源团队的联动 125 | 即使筹备了5年，这依然是一个非常宏大的工程，有太多的工作需要完成和探索。甲辰计划主理人欢迎所有对该项目感兴趣的开发人和RISC-V相关团队加入进来。 126 | ## RISC-V开发板征集 127 | 欢迎RISC-V芯片和开发板厂商进行设备捐赠或借用。参与甲辰计划PTS的厂商将能够更快的观测到开源软件社区对自家芯片和硬件系统的支持情况，及时对性能回退进行修复，保持竞争优势地位。 128 | 129 | ## 总结和展望 130 | RISC-V是一个充满活力的世界，欢迎加入！让我们用一纪的时间，在所有基础关键行业领域完成面向RISC-V的适配与优化，并形成超过万人的顶尖人才网络。 131 | 132 | ## 参考文献： 133 | - [1] https://lists.riscv.org/g/sig-code-speed/topic/slides_proposal_of_code/79032157 134 | - [2] https://arewefastyet.com/win11/benchmarks/overview?numDays=90 135 | - [3] https://github.com/rv2036 136 | -------------------------------------------------------------------------------- /blogs/en/20250907-PTS-Project-Announced.md: -------------------------------------------------------------------------------- 1 | # It’s time: The Jiachen Project has launched the construction of the RISC-V open source software Performance Tracking System (PTS) 2 | 3 | (Automatically generated by Google Translate.) 4 | 5 | The PTS is focusing on the performance evolution trend of the important global open source software RISC-V and publishing a roadmap; RISC-V manufacturers are sincerely invited to donate machines to participate in the construction 6 | 7 | ## Background, mission, and historical importance of PTS 8 | The idea of the RISC-V open source software performance tracking system (PTS) was first born in 2020 [1]. At that time, Mr. Wu Wei, the leader of the Jiachen Project, as the co-chair of the Code Speed SIG of the RISC-V International Foundation, hoped to build a visual system similar to Mozilla's `AreWeFastYet.com` system to track the performance of various important open source software including JavaScript Engines on RISC-V chips and systems. At that time, the development of RISC-V IP and chips was still focused on the embedded field, and there were only a few models of development boards that could run the Linux desktop environment, such as SiFive Unmatched. 9 | 10 | At the time, the PTS project was still quite advanced. The biggest concern was that prematurely disclosing the performance gap between RISC-V chips and Arm/X86 chips could have unintended negative consequences for the global RISC-V ecosystem. 11 | 12 | A year after its establishment, the Code Speed SIG disbanded and reorganized for various reasons, and the PTS project has remained dormant until now. During this time, the PLCT Lab attempted to launch PTS several times in 2021 and 2023, but failed due to various resource constraints and layoffs. 13 | 14 | On New Year's Eve 2024, the Jiachen Project launched, marking a turning point. After more than a year of development, over 50 companies have joined the Jiachen Project, gradually forming mutually supportive projects such as the "RISC-V Development Board Casual Drifting Project" and the "Open Source Internship Joint Recruitment and Training Program," rekindling the possibility of building a PTS. **The Jiachen Project has already secured sufficient venue sponsorship and operational support** (from Kuya Technology, Yingqi Intelligent, PLCT Laboratory, Hefei University of Technology, Dalian University of Technology, etc.), as well as a sufficient number of RISC-V development boards (including 200 LicheePi 4A TH1520 development boards donated by the Alibaba DAMO Academy's Xuantie team). The hardware and funding necessary for the initial phase of building the PTS are now in place. 15 | 16 | The construction and operation of the PTS are crucial to the development of the global RISC-V ecosystem. RISC-V has already achieved widespread adoption in embedded systems and is expanding into high-performance computing and data center scenarios. The global open source software ecosystem already has considerable functional support for RISC-V. Going forward, the focus will be on identifying various optimization opportunities to increase speed. An automated performance evaluation system and the resulting performance database, which is easily queried and compared, will greatly facilitate developers in identifying performance regressions and identifying optimization opportunities. 17 | 18 | The PTS will be hosted as an open source project under the Jiachen Project GitHub organization account. If all goes well, the data will be accessible via `pts.rv2036.org` starting October 1, 2025. All performance data collected by PTS will also be open source and hosted under the organization account `https://github.com/rv2036`. 19 | 20 | ## Tracked Open Source Software and Benchmark Scope 21 | 22 | The following software is initially planned for monitoring. Software of interest to the RISC-V community will be added over time. Common performance benchmark suites include the SPEC CPU 20xx series and the CoreMark series. Different languages and execution environments have different test sets. By default, PTS will collect as many open source and free test sets as possible for tracking. 23 | 24 | **Compilation Toolchain** 25 | - GNU Toolchain: Includes performance of compilers for languages such as C/C++ and Fortran. 26 | - Clang/LLVM: Includes performance of compilers for languages such as Clang and Flang. 27 | - Rust Toolchain 28 | 29 | **Virtual Machine** 30 | - V8 31 | - Spidermonkey 32 | - OpenJDK 33 | - Jeandle 34 | - Go Runtime 35 | - LuaJIT 36 | - .NET 37 | 38 | **Emulator** 39 | - QEMU 40 | - Box64 41 | - Wine-CE 42 | 43 | **System Libraries and Computing Libraries, Computing Stack** 44 | - glibc 45 | - musl-c 46 | - llvm libc 47 | - OpenBLAS 48 | - llama.cpp 49 | - Eigen 50 | - Highway 51 | - etc. 52 | 53 | ## Tracked RISC-V Chip/System Range 54 | 55 | **Main Test Machine (Sufficient Equipment)** 56 | - TH1520: Sipeed LicheePi 4A 57 | - SG2042: Milk-V PioneerBox 58 | 59 | **Standard Test Machine (At least one device with long-term stable use)** 60 | - EIC7700: Milk-V Megrez 61 | - K1: Sipeed LicheePi 3A 62 | 63 | **Expected Test Machine (No stable machine yet, but call (for donation)** 64 | - Sophgo SG2044 65 | - A210 66 | - SpacemiT K3 67 | - DP1000: Milk-V Titan 68 | 69 | ### Baseline Operating Systems 70 | - RevyOS: The default Debian distribution for the Xuantie IP series 71 | - KarsierOS: A commercially maintained distribution developed and maintained by Kuya Technology based on the openEuler community version 72 | - Ubuntu: Canonical natively supports some RISC-V development boards 73 | - deepin: A member of the Jiachen Project community, with strong localization advantages in graphical user interfaces 74 | - openKylin: A member of the Jiachen Project community, with strong localization advantages in graphical user interfaces 75 | 76 | ## Comparison Baseline Selection 77 | PTS will gradually introduce the following hardware systems as reference comparisons for non-RISC-V architectures: 78 | - RaspberryPi 4B - 2025Q3 79 | - RaspberryPi 5 - 2025Q4 - call for donation 80 | - Mac mini with M1 - 2025Q4 - call for donation 81 | - AMD9950x - 2026Q1 - Call for donations 82 | - Mac mini with M4 processor - 2026Q2 - Call for donations 83 | 84 | ## Roadmap and Results Release 85 | 86 | Starting in 2025Q4, PTS will release the "RISC-V Performance Improvement Report" within 15 days of the end of each quarter. 87 | 88 | **2025Q3** 89 | - PTS construction begins. 90 | - The first batch of RISC-V devices go online (TH1520, SG2042, Xiangshan Nanhu single-core). 91 | - V8 enters PTS observation range. 92 | - Baseline Raspberry Pi 4B goes online. 93 | 94 | **2025Q4** 95 | 96 | - The first issue of the "RISC-V Performance Improvement Report" is released. 97 | - Spidermonkey enters observation range. 98 | - GNU Toolchain enters observation range. 99 | - Clang/LLVM enters observation range. 100 | - SPEC CPU 2006/2017 enters observation range. 101 | - Xiangshan Nanhu quad-core launched 102 | - Super Rui DP100 (Milk-V Titan) launched 103 | - ESWIN EIC7700 SBC launched 104 | - Mac mini M1 launched 105 | - Raspberry Pi 5 launched 106 | 107 | **2026Q1** 108 | 109 | - A210 device launched 110 | - Xiangshan Kunming Lake series chip launched 111 | - Blue Core CPU launched (TBD) 112 | 113 | **2026Q2** 114 | - Test and evaluation equipment increased to 100 devices, covering over 20 types. 115 | - Common open source databases added to the test scope. 116 | - Stability testing added. 117 | 118 | **2026Q3** 119 | - Test equipment increased to 200 devices, completing testing of all popular databases. 120 | - All common HPC-related open source test suites added to the test scope. 121 | 122 | **2026Q4** 123 | - All data center-focused evaluation metrics now under observation. 124 | 125 | **2027Q1** 126 | - Entered stable maintenance status. 127 | - Evaluate over 500 hardware devices, track over 100 software projects, and measure over 1,000 performance metrics. 128 | - Add at least two 128-core RISC-V processors. 129 | 130 | ## Collaboration with Open Source Communities and Teams 131 | Even after five years of preparation, this remains a massive undertaking, with much work to accomplish and explore. The Jiachen Project organizers welcome all developers and RISC-V-related teams interested in the project to join. 132 | ## Call for RISC-V Development Boards 133 | RISC-V chip and development board vendors are welcome to donate or loan equipment. Vendors participating in the Jiachen Project PTS will be able to more quickly observe the open source software community's support for their chips and hardware systems, promptly address performance regressions, and maintain their competitive advantage. 134 | 135 | ## Summary and Outlook 136 | RISC-V is a vibrant world, and we welcome you to join us! Let's complete RISC-V adaptation and optimization across all key industry sectors within a century, and build a network of over 10,000 top talents. 137 | 138 | ## References: 139 | - [1] https://lists.riscv.org/g/sig-code-speed/topic/slides_proposal_of_code/79032157 140 | - [2] https://arewefastyet.com/win11/benchmarks/overview?numDays=90 141 | - [3] https://github.com/rv2036 --------------------------------------------------------------------------------