├── Disassembler ├── LLVMBuild.txt ├── Makefile └── SampleDisassembler.cpp ├── InstPrinter ├── CMakeLists.txt ├── LLVMBuild.txt ├── Makefile ├── SampleInstPrinter.cpp └── SampleInstPrinter.h ├── LLVMBuild.txt ├── MCTargetDesc ├── LLVMBuild.txt ├── Makefile ├── SampleAsmBackend.cpp ├── SampleBaseInfo.h ├── SampleELFObjectWriter.cpp ├── SampleFixupKinds.h ├── SampleMCAsmInfo.cpp ├── SampleMCAsmInfo.h ├── SampleMCCodeEmitter.cpp ├── SampleMCTargetDesc.cpp └── SampleMCTargetDesc.h ├── Makefile ├── README ├── Sample.h ├── Sample.td ├── SampleAsmPrinter.cpp ├── SampleFrameLowering.cpp ├── SampleFrameLowering.h ├── SampleISelDAGtoDAG.cpp ├── SampleISelLowering.cpp ├── SampleISelLowering.h ├── SampleInstrInfo.cpp ├── SampleInstrInfo.h ├── SampleMCInstLower.cpp ├── SampleMCInstLower.h ├── SampleMachineFunction.cpp ├── SampleMachineFunction.h ├── SampleRegisterInfo.cpp ├── SampleRegisterInfo.h ├── SampleSelectionDAGInfo.cpp ├── SampleSelectionDAGInfo.h ├── SampleSubtarget.cpp ├── SampleSubtarget.h ├── SampleTargetMachine.cpp ├── SampleTargetMachine.h ├── TargetInfo ├── LLVMBuild.txt ├── Makefile └── SampleTargetInfo.cpp └── config.patch /Disassembler/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Sample/Disassembler/LLVMBuild.txt --------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = SampleDisassembler 21 | parent = Sample 22 | required_libraries = MC Support SampleInfo 23 | add_to_library_groups = Sample 24 | -------------------------------------------------------------------------------- /Disassembler/Makefile: -------------------------------------------------------------------------------- 1 | ##===- lib/Target/Sample/Disassembler/Makefile ----------------*- Makefile -*-===## 2 | # 3 | # The LLVM Compiler Infrastructure 4 | # 5 | # This file is distributed under the University of Illinois Open Source 6 | # License. See LICENSE.TXT for details. 7 | # 8 | ##===----------------------------------------------------------------------===## 9 | 10 | LEVEL = ../../../.. 11 | LIBRARYNAME = LLVMSampleDisassembler 12 | 13 | # Hack: we need to include 'main' Sample target directory to grab private headers 14 | CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. 15 | 16 | include $(LEVEL)/Makefile.common 17 | -------------------------------------------------------------------------------- /Disassembler/SampleDisassembler.cpp: -------------------------------------------------------------------------------- 1 | //===- SampleDisassembler.cpp - Disassembler for Sample -------------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file is part of the Sample Disassembler. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "Sample.h" 15 | #include "SampleSubtarget.h" 16 | #include "llvm/MC/EDInstInfo.h" 17 | #include "llvm/MC/MCDisassembler.h" 18 | #include "llvm/MC/MCFixedLenDisassembler.h" 19 | #include "llvm/Support/MemoryObject.h" 20 | #include "llvm/Support/TargetRegistry.h" 21 | #include "llvm/MC/MCSubtargetInfo.h" 22 | #include "llvm/MC/MCInst.h" 23 | #include "llvm/MC/MCRegisterInfo.h" 24 | #include "llvm/Support/MathExtras.h" 25 | 26 | #include "SampleGenEDInfo.inc" 27 | 28 | using namespace llvm; 29 | 30 | typedef MCDisassembler::DecodeStatus DecodeStatus; 31 | 32 | /// SampleDisassembler - a disasembler class for Sample32. 33 | class SampleDisassembler : public MCDisassembler { 34 | public: 35 | /// Constructor - Initializes the disassembler. 36 | /// 37 | SampleDisassembler(const MCSubtargetInfo &STI) 38 | : MCDisassembler(STI) {} 39 | 40 | ~SampleDisassembler() {} 41 | 42 | /// getInstruction - See MCDisassembler. 43 | DecodeStatus getInstruction(MCInst &instr, 44 | uint64_t &size, 45 | const MemoryObject ®ion, 46 | uint64_t address, 47 | raw_ostream &vStream, 48 | raw_ostream &cStream) const; 49 | 50 | const EDInstInfo *getEDInfo() const; 51 | 52 | private: 53 | DecodeStatus readInstruction32(const MemoryObject ®ion, 54 | uint64_t address, 55 | uint64_t &size, 56 | uint32_t &insn) const; 57 | }; 58 | 59 | const EDInstInfo *SampleDisassembler::getEDInfo() const { 60 | return instInfoSample; 61 | } 62 | 63 | // Decoder tables for Sample register 64 | static const unsigned CPURegsTable[] = { 65 | Sample::ZERO, Sample::V0, 66 | Sample::A0, Sample::A1, Sample::A2, Sample::A3, 67 | Sample::T0, Sample::T1, Sample::T2, Sample::T3, 68 | Sample::S0, Sample::S1, Sample::S2, Sample::S3, 69 | Sample::SP, Sample::RA 70 | }; 71 | 72 | // Forward declare these because the autogenerated code will reference them. 73 | // Definitions are further down. 74 | // DecodeXXX関数はtablegenでDecoderMethodを指定した場合に 75 | // decodeSampleInstruction32()から参照される。 76 | 77 | // tablegenで作成したCPURegs(RegisterClass)を表示する 78 | static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, 79 | unsigned RegNo, 80 | uint64_t Address, 81 | const void *Decoder); 82 | static DecodeStatus DecodeMem(MCInst &Inst, 83 | unsigned RegNo, 84 | uint64_t Address, 85 | const void *Decoder); 86 | 87 | static DecodeStatus DecodeMoveTarget(MCInst &Inst, 88 | unsigned Insn, 89 | uint64_t Address, 90 | const void *Decoder); 91 | 92 | static DecodeStatus DecodeCallTarget(MCInst &Inst, 93 | unsigned Insn, 94 | uint64_t Address, 95 | const void *Decoder); 96 | 97 | static MCDisassembler *createSampleDisassembler( 98 | const Target &T, 99 | const MCSubtargetInfo &STI) { 100 | return new SampleDisassembler(STI); 101 | } 102 | 103 | extern "C" void LLVMInitializeSampleDisassembler() { 104 | // Register the disassembler. 105 | TargetRegistry::RegisterMCDisassembler(TheSampleTarget, 106 | createSampleDisassembler); 107 | } 108 | 109 | #include "SampleGenDisassemblerTables.inc" 110 | 111 | /// readInstruction - read four bytes from the MemoryObject 112 | /// and return 32 bit word sorted according to the given endianess 113 | DecodeStatus SampleDisassembler:: 114 | readInstruction32(const MemoryObject ®ion, 115 | uint64_t address, 116 | uint64_t &size, 117 | uint32_t &insn) const { 118 | uint8_t Bytes[4]; 119 | 120 | // We want to read exactly 4 Bytes of data. 121 | if (region.readBytes(address, 4, (uint8_t*)Bytes, NULL) == -1) { 122 | size = 0; 123 | return MCDisassembler::Fail; 124 | } 125 | 126 | // Encoded as a small-endian 32-bit word in the stream. 127 | insn = (Bytes[3] << 0) | 128 | (Bytes[2] << 8) | 129 | (Bytes[1] << 16) | 130 | (Bytes[0] << 24); 131 | 132 | return MCDisassembler::Success; 133 | } 134 | 135 | DecodeStatus SampleDisassembler:: 136 | getInstruction(MCInst &instr, 137 | uint64_t &Size, 138 | const MemoryObject &Region, 139 | uint64_t Address, 140 | raw_ostream &vStream, 141 | raw_ostream &cStream) const { 142 | uint32_t Insn; 143 | 144 | DecodeStatus Result = readInstruction32(Region, Address, Size, 145 | Insn); 146 | if (Result == MCDisassembler::Fail) 147 | return MCDisassembler::Fail; 148 | 149 | // Calling the auto-generated decoder function. 150 | Result = decodeInstruction(DecoderTableSample32, 151 | instr, Insn, Address, this, STI); 152 | if (Result != MCDisassembler::Fail) { 153 | Size = 4; 154 | return Result; 155 | } 156 | 157 | return MCDisassembler::Fail; 158 | } 159 | 160 | static DecodeStatus DecodeCPURegsRegisterClass(MCInst &Inst, 161 | unsigned RegNo, 162 | uint64_t Address, 163 | const void *Decoder) { 164 | if (RegNo > 31) 165 | return MCDisassembler::Fail; 166 | 167 | Inst.addOperand(MCOperand::CreateReg(CPURegsTable[RegNo])); 168 | return MCDisassembler::Success; 169 | } 170 | 171 | static DecodeStatus DecodeMem(MCInst &Inst, 172 | unsigned Insn, 173 | uint64_t Address, 174 | const void *Decoder) { 175 | int Offset = SignExtend32<16>(Insn & 0xffff); 176 | int Reg = (int)fieldFromInstruction(Insn, 16, 4); 177 | int Base = (int)fieldFromInstruction(Insn, 20, 4); 178 | 179 | Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg])); 180 | Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Base])); 181 | Inst.addOperand(MCOperand::CreateImm(Offset)); 182 | 183 | return MCDisassembler::Success; 184 | } 185 | 186 | static DecodeStatus DecodeMoveTarget(MCInst &Inst, 187 | unsigned Insn, 188 | uint64_t Address, 189 | const void *Decoder) { 190 | int Offset = SignExtend32<20>(Insn & 0xfffff); 191 | int Reg = (int)fieldFromInstruction(Insn, 20, 4); 192 | 193 | Inst.addOperand(MCOperand::CreateReg(CPURegsTable[Reg])); 194 | Inst.addOperand(MCOperand::CreateImm(Offset)); 195 | 196 | return MCDisassembler::Success; 197 | } 198 | 199 | static DecodeStatus DecodeCallTarget(MCInst &Inst, 200 | unsigned Insn, 201 | uint64_t Address, 202 | const void *Decoder) { 203 | 204 | unsigned CallOffset = fieldFromInstruction(Insn, 0, 24) << 2; 205 | Inst.addOperand(MCOperand::CreateImm(CallOffset)); 206 | return MCDisassembler::Success; 207 | } 208 | -------------------------------------------------------------------------------- /InstPrinter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. ) 2 | 3 | add_llvm_library(LLVMMipsAsmPrinter 4 | MipsInstPrinter.cpp 5 | ) 6 | 7 | add_dependencies(LLVMMipsAsmPrinter MipsCommonTableGen) 8 | -------------------------------------------------------------------------------- /InstPrinter/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Mips/InstPrinter/LLVMBuild.txt --------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = SampleAsmPrinter 21 | parent = Sample 22 | required_libraries = MC Support 23 | add_to_library_groups = Sample 24 | -------------------------------------------------------------------------------- /InstPrinter/Makefile: -------------------------------------------------------------------------------- 1 | ##===- lib/Target/Mips/AsmPrinter/Makefile -----------------*- Makefile -*-===## 2 | # 3 | # The LLVM Compiler Infrastructure 4 | # 5 | # This file is distributed under the University of Illinois Open Source 6 | # License. See LICENSE.TXT for details. 7 | # 8 | ##===----------------------------------------------------------------------===## 9 | LEVEL = ../../../.. 10 | LIBRARYNAME = LLVMSampleAsmPrinter 11 | 12 | # Hack: we need to include 'main' mips target directory to grab private headers 13 | CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. 14 | 15 | include $(LEVEL)/Makefile.common 16 | -------------------------------------------------------------------------------- /InstPrinter/SampleInstPrinter.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleInstPrinter.cpp - Convert Sample MCInst to assembly syntax ------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints an Sample MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #define DEBUG_TYPE "asm-printer" 15 | #include "SampleInstPrinter.h" 16 | #include "llvm/ADT/StringExtras.h" 17 | #include "llvm/MC/MCExpr.h" 18 | #include "llvm/MC/MCInst.h" 19 | #include "llvm/MC/MCInstrInfo.h" 20 | #include "llvm/MC/MCSymbol.h" 21 | #include "llvm/Support/ErrorHandling.h" 22 | #include "llvm/Support/raw_ostream.h" 23 | using namespace llvm; 24 | 25 | #include "SampleGenAsmWriter.inc" 26 | 27 | void SampleInstPrinter:: 28 | printRegName(raw_ostream &OS, unsigned RegNo) const { 29 | OS << '$' << StringRef(getRegisterName(RegNo)).lower(); 30 | } 31 | 32 | void SampleInstPrinter:: 33 | printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) { 34 | DEBUG(dbgs() << ">>> printInst:"; MI->dump()); 35 | printInstruction(MI, O); 36 | printAnnotation(O, Annot); 37 | } 38 | 39 | void SampleInstPrinter:: 40 | printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) { 41 | DEBUG(dbgs() << ">>> printOperand:" << *MI << " OpNo:" << OpNo << "\n"); 42 | const MCOperand &Op = MI->getOperand(OpNo); 43 | if (Op.isReg()) { 44 | printRegName(O, Op.getReg()); 45 | } else if (Op.isImm()) { 46 | O << Op.getImm(); 47 | } else { 48 | assert(Op.isExpr() && "unknown operand kind in printOperand"); 49 | O << *Op.getExpr(); 50 | } 51 | } 52 | 53 | void SampleInstPrinter:: 54 | printMemOperand(const MCInst *MI, int opNum, raw_ostream &O) { 55 | DEBUG(dbgs() << ">>> printMemOperand:"; MI->dump()); 56 | printOperand(MI, opNum+1, O); 57 | O << "("; 58 | printOperand(MI, opNum, O); 59 | O << ")"; 60 | } 61 | -------------------------------------------------------------------------------- /InstPrinter/SampleInstPrinter.h: -------------------------------------------------------------------------------- 1 | //=== SampleInstPrinter.h - Convert Sample MCInst to assembly syntax -*- C++ -*-==// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This class prints a Sample MCInst to a .s file. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLE_INSTPRINTER_H 15 | #define SAMPLE_INSTPRINTER_H 16 | #include "llvm/MC/MCInstPrinter.h" 17 | #include "llvm/Support/Debug.h" 18 | 19 | namespace llvm { 20 | // These enumeration declarations were orignally in SampleInstrInfo.h but 21 | // had to be moved here to avoid circular dependencies between 22 | // LLVMSampleCodeGen and LLVMSampleAsmPrinter. 23 | class TargetMachine; 24 | 25 | class SampleInstPrinter : public MCInstPrinter { 26 | public: 27 | SampleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII, 28 | const MCRegisterInfo &MRI) 29 | : MCInstPrinter(MAI, MII, MRI) {} 30 | 31 | // must implement 32 | virtual void printRegName(raw_ostream &OS, unsigned RegNo) const /*override*/; 33 | virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) /*override*/; 34 | 35 | private: 36 | // Autogenerated by tblgen. 37 | void printInstruction(const MCInst *MI, raw_ostream &O); 38 | static const char *getRegisterName(unsigned RegNo); 39 | 40 | // used in printInstruction 41 | void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O); 42 | void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); 43 | }; 44 | } // end namespace llvm 45 | 46 | #endif 47 | -------------------------------------------------------------------------------- /LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Sample/LLVMBuild.txt --------------------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [common] 19 | ;subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo 20 | subdirectories = Disassembler InstPrinter MCTargetDesc TargetInfo 21 | 22 | [component_0] 23 | type = TargetGroup 24 | name = Sample 25 | parent = Target 26 | ;has_asmparser = 1 27 | has_asmprinter = 1 28 | has_disassembler = 1 29 | ;has_jit = 1 30 | 31 | [component_1] 32 | type = Library 33 | name = SampleCodeGen 34 | parent = Sample 35 | required_libraries = AsmPrinter CodeGen Core MC SampleAsmPrinter SampleDesc SampleInfo SelectionDAG Support Target 36 | add_to_library_groups = Sample 37 | -------------------------------------------------------------------------------- /MCTargetDesc/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Mips/MCTargetDesc/LLVMBuild.txt -------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = SampleDesc 21 | parent = Sample 22 | required_libraries = MC SampleAsmPrinter SampleInfo Support Target 23 | add_to_library_groups = Sample 24 | -------------------------------------------------------------------------------- /MCTargetDesc/Makefile: -------------------------------------------------------------------------------- 1 | ##===- lib/Target/Sample/TargetDesc/Makefile -----------------*- Makefile -*-===## 2 | # 3 | # The LLVM Compiler Infrastructure 4 | # 5 | # This file is distributed under the University of Illinois Open Source 6 | # License. See LICENSE.TXT for details. 7 | # 8 | ##===----------------------------------------------------------------------===## 9 | 10 | LEVEL = ../../../.. 11 | LIBRARYNAME = LLVMSampleDesc 12 | 13 | # Hack: we need to include 'main' target directory to grab private headers 14 | CPP.Flags += -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. 15 | 16 | include $(LEVEL)/Makefile.common 17 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleAsmBackend.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleASMBackend.cpp - Sample Asm Backend ----------------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements the SampleAsmBackend and SampleELFObjectWriter classes. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | // 14 | 15 | #include "SampleFixupKinds.h" 16 | #include "MCTargetDesc/SampleMCTargetDesc.h" 17 | #include "llvm/MC/MCAsmBackend.h" 18 | #include "llvm/MC/MCAssembler.h" 19 | #include "llvm/MC/MCDirectives.h" 20 | #include "llvm/MC/MCELFObjectWriter.h" 21 | #include "llvm/MC/MCFixupKindInfo.h" 22 | #include "llvm/MC/MCObjectWriter.h" 23 | #include "llvm/MC/MCSubtargetInfo.h" 24 | #include "llvm/Support/ErrorHandling.h" 25 | #include "llvm/Support/Debug.h" 26 | #include "llvm/Support/raw_ostream.h" 27 | #include "llvm/Support/Format.h" 28 | 29 | using namespace llvm; 30 | 31 | // Prepare value for the target space for it 32 | static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 33 | DEBUG(dbgs() << ">> adjustFixupValue: kind:" << Kind << " Value:" << Value << "\n"); 34 | 35 | switch (Kind) { 36 | default: 37 | return 0; 38 | case Sample::fixup_Sample_24: 39 | Value >>= 2; 40 | break; 41 | } 42 | 43 | return Value; 44 | } 45 | 46 | namespace { 47 | class SampleAsmBackend : public MCAsmBackend { 48 | Triple::OSType OSType; 49 | 50 | public: 51 | SampleAsmBackend(const Target &T, Triple::OSType _OSType) 52 | :MCAsmBackend(), OSType(_OSType) {} 53 | 54 | MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 55 | return createSampleELFObjectWriter(OS, OSType); 56 | } 57 | 58 | /// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided 59 | /// data fragment, at the offset specified by the fixup and following the 60 | /// fixup kind as appropriate. 61 | void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 62 | uint64_t Value) const; 63 | 64 | unsigned getNumFixupKinds() const { return Sample::NumTargetFixupKinds; } 65 | 66 | const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const; 67 | 68 | /// @name Target Relaxation Interfaces 69 | /// @{ 70 | 71 | /// MayNeedRelaxation - Check whether the given instruction may need 72 | /// relaxation. 73 | /// 74 | /// \param Inst - The instruction to test. 75 | bool mayNeedRelaxation(const MCInst &Inst) const { 76 | return false; 77 | } 78 | 79 | /// fixupNeedsRelaxation - Target specific predicate for whether a given 80 | /// fixup requires the associated instruction to be relaxed. 81 | bool fixupNeedsRelaxation(const MCFixup &Fixup, 82 | uint64_t Value, 83 | const MCInstFragment *DF, 84 | const MCAsmLayout &Layout) const { 85 | // FIXME. 86 | assert(0 && "RelaxInstruction() unimplemented"); 87 | return false; 88 | } 89 | 90 | /// RelaxInstruction - Relax the instruction in the given fragment 91 | /// to the next wider instruction. 92 | /// 93 | /// \param Inst - The instruction to relax, which may be the same 94 | /// as the output. 95 | /// \parm Res [output] - On return, the relaxed instruction. 96 | void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 97 | } 98 | 99 | /// @} 100 | 101 | /// WriteNopData - Write an (optimal) nop sequence of Count bytes 102 | /// to the given output. If the target cannot generate such a sequence, 103 | /// it should return an error. 104 | /// 105 | /// \return - True on success. 106 | bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 107 | return true; 108 | } 109 | }; // class SampleAsmBackend 110 | 111 | void SampleAsmBackend:: 112 | applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 113 | uint64_t Value) const { 114 | MCFixupKind Kind = Fixup.getKind(); 115 | Value = adjustFixupValue((unsigned)Kind, Value); 116 | 117 | if (!Value) 118 | return; // Doesn't change encoding. 119 | 120 | // Where do we start in the object 121 | unsigned Offset = Fixup.getOffset(); 122 | // Number of bytes we need to fixup 123 | unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8; 124 | 125 | DEBUG(dbgs() << " Offset: " << Offset << "\n"); 126 | DEBUG(dbgs() << " NumBytes: " << NumBytes << "\n"); 127 | DEBUG(dbgs() << " TargetSize: " << getFixupKindInfo(Kind).TargetSize << "\n"); 128 | DEBUG(dbgs() << format(" Data: 0x%08x\n", (uint32_t)Data[Offset])); 129 | 130 | // Grab current value, if any, from bits. 131 | uint64_t CurVal = 0; 132 | 133 | for (unsigned i = 0; i != NumBytes; ++i) { 134 | unsigned Idx = i; 135 | CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8); 136 | } 137 | DEBUG(dbgs() << format(" CurVal: 0x%08x\n", CurVal)); 138 | 139 | uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize)); 140 | CurVal |= Value & Mask; 141 | DEBUG(dbgs() << format(" CurVal: 0x%08x\n", CurVal)); 142 | 143 | // Write out the fixed up bytes back to the code/data bits. 144 | for (unsigned i = 0; i != NumBytes; ++i) { 145 | unsigned Idx = i; 146 | Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff); 147 | } 148 | 149 | DEBUG(dbgs() << format(" Data: 0x%08x\n", (uint32_t)Data[Offset])); 150 | } 151 | 152 | const MCFixupKindInfo &SampleAsmBackend:: 153 | getFixupKindInfo(MCFixupKind Kind) const { 154 | const static MCFixupKindInfo Infos[Sample::NumTargetFixupKinds] = { 155 | // This table *must* be in same the order of fixup_* kinds in 156 | // SampleFixupKinds.h. 157 | // 158 | // name offset bits flags 159 | {"fixup_Sample_24", 0, 24, 0} 160 | }; 161 | 162 | if (Kind < FirstTargetFixupKind) 163 | return MCAsmBackend::getFixupKindInfo(Kind); 164 | 165 | assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 166 | "Invalid kind!"); 167 | return Infos[Kind - FirstTargetFixupKind]; 168 | } 169 | 170 | } // namespace 171 | 172 | // MCAsmBackend 173 | MCAsmBackend *llvm::createSampleAsmBackend(const Target &T, StringRef TT, 174 | StringRef CPU) { 175 | return new SampleAsmBackend(T, Triple(TT).getOS()); 176 | } 177 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleBaseInfo.h: -------------------------------------------------------------------------------- 1 | //===-- SampleBaseInfo.h - Top level definitions for MIPS MC ------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains small standalone helper functions and enum definitions for 11 | // the Sample target useful for the compiler back-end and the MC libraries. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | #ifndef SAMPLEBASEINFO_H 15 | #define SAMPLEASEINFO_H 16 | 17 | //#include "SampleFixupKinds.h" 18 | #include "SampleMCTargetDesc.h" 19 | #include "llvm/MC/MCExpr.h" 20 | #include "llvm/Support/DataTypes.h" 21 | #include "llvm/Support/ErrorHandling.h" 22 | 23 | namespace llvm { 24 | 25 | /// getSampleRegisterNumbering - Given the enum value for some register, 26 | /// return the number that it corresponds to. 27 | inline static unsigned getSampleRegisterNumbering(unsigned RegEnum) 28 | { 29 | switch (RegEnum) { 30 | case Sample::ZERO: 31 | return 0; 32 | case Sample::V0: 33 | return 1; 34 | case Sample::A0: 35 | return 2; 36 | case Sample::A1: 37 | return 3; 38 | case Sample::A2: 39 | return 4; 40 | case Sample::A3: 41 | return 5; 42 | case Sample::T0: 43 | return 6; 44 | case Sample::T1: 45 | return 7; 46 | case Sample::T2: 47 | return 8; 48 | case Sample::T3: 49 | return 9; 50 | case Sample::S0: 51 | return 10; 52 | case Sample::S1: 53 | return 11; 54 | case Sample::S2: 55 | return 12; 56 | case Sample::S3: 57 | return 13; 58 | case Sample::SP: 59 | return 14; 60 | case Sample::RA: 61 | return 15; 62 | default: llvm_unreachable("Unknown register number!"); 63 | } 64 | } 65 | } 66 | 67 | #endif 68 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleELFObjectWriter.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleELFObjectWriter.cpp - Sample ELF Writer -------------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #include "MCTargetDesc/SampleBaseInfo.h" 11 | #include "MCTargetDesc/SampleFixupKinds.h" 12 | #include "MCTargetDesc/SampleMCTargetDesc.h" 13 | #include "llvm/MC/MCAssembler.h" 14 | #include "llvm/MC/MCELFObjectWriter.h" 15 | #include "llvm/MC/MCExpr.h" 16 | #include "llvm/MC/MCSection.h" 17 | #include "llvm/MC/MCValue.h" 18 | #include "llvm/Support/ErrorHandling.h" 19 | #include 20 | 21 | using namespace llvm; 22 | 23 | namespace { 24 | struct RelEntry { 25 | RelEntry(const ELFRelocationEntry &R, const MCSymbol *S, int64_t O) : 26 | Reloc(R), Sym(S), Offset(O) {} 27 | ELFRelocationEntry Reloc; 28 | const MCSymbol *Sym; 29 | int64_t Offset; 30 | }; 31 | 32 | typedef std::list RelLs; 33 | typedef RelLs::iterator RelLsIter; 34 | 35 | class SampleELFObjectWriter : public MCELFObjectTargetWriter { 36 | public: 37 | SampleELFObjectWriter(uint8_t OSABI); 38 | virtual ~SampleELFObjectWriter(); 39 | 40 | // オブジェクトを生成するときやリンク時にアドレス解決するために 41 | // ELFObjectWriterなどから参照される 42 | virtual unsigned GetRelocType(const MCValue &Target, const MCFixup &Fixup, 43 | bool IsPCRel, bool IsRelocWithSymbol, 44 | int64_t Addend) const; 45 | }; 46 | } 47 | 48 | SampleELFObjectWriter:: 49 | SampleELFObjectWriter(uint8_t OSABI) 50 | : MCELFObjectTargetWriter(/*_is64Bit*/ false, OSABI, ELF::EM_NONE, 51 | /*HasRelocationAddend*/ false) {} 52 | 53 | SampleELFObjectWriter::~SampleELFObjectWriter() {} 54 | 55 | unsigned SampleELFObjectWriter:: 56 | GetRelocType(const MCValue &Target, 57 | const MCFixup &Fixup, 58 | bool IsPCRel, 59 | bool IsRelocWithSymbol, 60 | int64_t Addend) const { 61 | // determine the type of the relocation 62 | unsigned Type = (unsigned)ELF::R_MIPS_NONE; 63 | unsigned Kind = (unsigned)Fixup.getKind(); 64 | 65 | switch (Kind) { 66 | default: 67 | llvm_unreachable("invalid fixup kind!"); 68 | case Sample::fixup_Sample_24: 69 | Type = ELF::R_MIPS_26; 70 | break; 71 | } 72 | 73 | return Type; 74 | } 75 | 76 | MCObjectWriter *llvm::createSampleELFObjectWriter(raw_ostream &OS, 77 | uint8_t OSABI) { 78 | MCELFObjectTargetWriter *MOTW = new SampleELFObjectWriter(OSABI); 79 | return createELFObjectWriter(MOTW, OS, /*isLittleEndian*/ true); 80 | } 81 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleFixupKinds.h: -------------------------------------------------------------------------------- 1 | //===-- SampleFixupKinds.h - Sample Specific Fixup Entries ----------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #ifndef LLVM_SAMPLE_FIXUPKINDS_H 11 | #define LLVM_SAMPLE_FIXUPKINDS_H 12 | 13 | #include "llvm/MC/MCFixup.h" 14 | 15 | namespace llvm { 16 | namespace Sample { 17 | // Although most of the current fixup types reflect a unique relocation 18 | // one can have multiple fixup types for a given relocation and thus need 19 | // to be uniquely named. 20 | // 21 | // This table *must* be in the save order of 22 | // MCFixupKindInfo Infos[Sample::NumTargetFixupKinds] 23 | // in SampleAsmBackend.cpp. 24 | // 25 | enum Fixups { 26 | fixup_Sample_24 = FirstTargetFixupKind, 27 | LastTargetFixupKind, 28 | NumTargetFixupKinds = LastTargetFixupKind - FirstTargetFixupKind 29 | }; 30 | } // namespace Sample 31 | } // namespace llvm 32 | 33 | 34 | #endif // LLVM_SAMPLE_SAMPLEFIXUPKINDS_H 35 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleMCAsmInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleMCAsmInfo.cpp - Sample asm properties -----------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the declarations of the SampleMCAsmInfo properties. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "SampleMCAsmInfo.h" 15 | #include "llvm/ADT/StringRef.h" 16 | using namespace llvm; 17 | 18 | SampleMCAsmInfo::SampleMCAsmInfo(const Target &T, StringRef TT) { 19 | PointerSize = 4; 20 | 21 | PrivateGlobalPrefix = ".L"; 22 | //WeakRefDirective ="\t.weak\t"; 23 | PCSymbol="."; 24 | CommentString = ";"; 25 | 26 | AlignmentIsInBytes = false; 27 | AllowNameToStartWithDigit = true; 28 | UsesELFSectionDirectiveForBSS = true; 29 | } 30 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleMCAsmInfo.h: -------------------------------------------------------------------------------- 1 | //===-- SampleMCAsmInfo.h - Sample asm properties --------------*- C++ -*--===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the declaration of the SampleMCAsmInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLE_TARGETASMINFO_H 15 | #define SAMPLE_TARGETASMINFO_H 16 | 17 | #include "llvm/MC/MCAsmInfo.h" 18 | 19 | namespace llvm { 20 | class StringRef; 21 | class Target; 22 | 23 | class SampleMCAsmInfo : public MCAsmInfo { 24 | virtual void anchor() {}; 25 | public: 26 | explicit SampleMCAsmInfo(const Target &T, StringRef TT); 27 | }; 28 | 29 | } // namespace llvm 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleMCCodeEmitter.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleMCCodeEmitter.cpp - Convert Sample Code to Machine Code ---------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements the SampleMCCodeEmitter class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | // 14 | #define DEBUG_TYPE "mccodeemitter" 15 | #include "MCTargetDesc/SampleBaseInfo.h" 16 | #include "MCTargetDesc/SampleFixupKinds.h" 17 | #include "MCTargetDesc/SampleMCTargetDesc.h" 18 | #include "llvm/ADT/APFloat.h" 19 | #include "llvm/ADT/Statistic.h" 20 | #include "llvm/MC/MCCodeEmitter.h" 21 | #include "llvm/MC/MCExpr.h" 22 | #include "llvm/MC/MCInst.h" 23 | #include "llvm/MC/MCInstrInfo.h" 24 | #include "llvm/MC/MCRegisterInfo.h" 25 | #include "llvm/MC/MCSubtargetInfo.h" 26 | #include "llvm/Support/raw_ostream.h" 27 | 28 | using namespace llvm; 29 | 30 | namespace { 31 | class SampleMCCodeEmitter : public MCCodeEmitter { 32 | SampleMCCodeEmitter(const SampleMCCodeEmitter &); // DO NOT IMPLEMENT 33 | void operator=(const SampleMCCodeEmitter &); // DO NOT IMPLEMENT 34 | const MCInstrInfo &MCII; 35 | const MCSubtargetInfo &STI; 36 | MCContext &Ctx; 37 | 38 | public: 39 | SampleMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti, 40 | MCContext &ctx) : 41 | MCII(mcii), STI(sti) , Ctx(ctx) {} 42 | 43 | ~SampleMCCodeEmitter() {} 44 | 45 | // EncodeInstruction - AsmStreamerから実行される 46 | // 命令をバイナリにして出力する 47 | void EncodeInstruction(const MCInst &MI, raw_ostream &OS, 48 | SmallVectorImpl &Fixups) const; 49 | 50 | private: 51 | // getBinaryCodeForInstr - TableGenが自動生成 52 | // 命令のバイナリエンコーディングを取得 53 | uint64_t getBinaryCodeForInstr(const MCInst &MI, 54 | SmallVectorImpl &Fixups) const; 55 | 56 | // getMachineOpValue - TableGenの中から必ず参照される 57 | // オペランドのバイナリエンコーディングを取得 58 | unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 59 | SmallVectorImpl &Fixups) const; 60 | 61 | // getMemEncoding - TableGenのDecoderMethodで指定 62 | // load/storeのオペランドのバイナリエンコーディングを取得 63 | unsigned getMemEncoding(const MCInst &MI, unsigned OpNo, 64 | SmallVectorImpl &Fixups) const; 65 | 66 | // getMoveTargetOpValue - TableGenのDecoderMethodで指定 67 | // moveのオペランドのバイナリエンコーディングを取得 68 | unsigned getMoveTargetOpValue(const MCInst &MI, unsigned OpNo, 69 | SmallVectorImpl &Fixups) const; 70 | 71 | // call命令のオペランドのバイナリエンコーディングを取得 72 | unsigned getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 73 | SmallVectorImpl &Fixups) const; 74 | 75 | 76 | }; // class SampleMCCodeEmitter 77 | } // namespace 78 | 79 | MCCodeEmitter *llvm::createSampleMCCodeEmitter(const MCInstrInfo &MCII, 80 | const MCRegisterInfo &MRI, 81 | const MCSubtargetInfo &STI, 82 | MCContext &Ctx) 83 | { 84 | return new SampleMCCodeEmitter(MCII, STI, Ctx); 85 | } 86 | 87 | /// EncodeInstruction - Emit the instruction. 88 | void SampleMCCodeEmitter:: 89 | EncodeInstruction(const MCInst &MI, raw_ostream &OS, 90 | SmallVectorImpl &Fixups) const 91 | { 92 | uint32_t Binary = getBinaryCodeForInstr(MI, Fixups); 93 | 94 | // For now all instructions are 4 bytes 95 | int Size = 4; // FIXME: Have Desc.getSize() return the correct value! 96 | 97 | for (int i = Size - 1; i >= 0; --i) { 98 | unsigned Shift = i * 8; 99 | OS << char((Binary >> Shift) & 0xff); 100 | } 101 | } 102 | 103 | /// getMachineOpValue - Return binary encoding of operand. If the machine 104 | /// operand requires relocation, record the relocation and return zero. 105 | unsigned SampleMCCodeEmitter:: 106 | getMachineOpValue(const MCInst &MI, const MCOperand &MO, 107 | SmallVectorImpl &Fixups) const { 108 | if (MO.isReg()) { 109 | unsigned Reg = MO.getReg(); 110 | unsigned RegNo = getSampleRegisterNumbering(Reg); 111 | return RegNo; 112 | } else if (MO.isImm()) { 113 | return static_cast(MO.getImm()); 114 | } else if (MO.isFPImm()) { 115 | return static_cast(APFloat(MO.getFPImm()) 116 | .bitcastToAPInt().getHiBits(32).getLimitedValue()); 117 | } 118 | 119 | // MO must be an Expr. 120 | assert(MO.isExpr()); 121 | 122 | llvm_unreachable("not implemented"); 123 | return 0; 124 | } 125 | 126 | /// getMemEncoding - Return binary encoding of memory related operand. 127 | /// If the offset operand requires relocation, record the relocation. 128 | unsigned SampleMCCodeEmitter:: 129 | getMemEncoding(const MCInst &MI, unsigned OpNo, 130 | SmallVectorImpl &Fixups) const { 131 | //llvm_unreachable("not implemented"); 132 | // Base register is encoded in bits 19-16, offset is encoded in bits 15-0. 133 | assert(MI.getOperand(OpNo).isReg()); 134 | unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups) << 16; 135 | unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups); 136 | 137 | return (OffBits & 0xFFFF) | RegBits; 138 | } 139 | 140 | /// getMoveTargetOpValue - Return binary encoding of the move 141 | /// target operand. 142 | unsigned SampleMCCodeEmitter:: 143 | getMoveTargetOpValue(const MCInst &MI, unsigned OpNo, 144 | SmallVectorImpl &Fixups) const { 145 | assert(MI.getOperand(OpNo).isImm()); 146 | unsigned value = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups); 147 | return value & 0xFFFFF; 148 | } 149 | 150 | /// getJumpTargetOpValue - Return binary encoding of the jump 151 | /// target operand. If the machine operand requires relocation, 152 | /// record the relocation and return zero. 153 | unsigned SampleMCCodeEmitter:: 154 | getCallTargetOpValue(const MCInst &MI, unsigned OpNo, 155 | SmallVectorImpl &Fixups) const { 156 | 157 | const MCOperand &MO = MI.getOperand(OpNo); 158 | assert(MO.isExpr() && "getCallTargetOpValue expects only expressions"); 159 | 160 | const MCExpr *Expr = MO.getExpr(); 161 | Fixups.push_back(MCFixup::Create(0, Expr, 162 | MCFixupKind(Sample::fixup_Sample_24))); 163 | return 0; 164 | } 165 | 166 | #include "SampleGenMCCodeEmitter.inc" 167 | 168 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleMCTargetDesc.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleMCTargetDesc.cpp - Sample Target Descriptions -------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file provides Sample specific target descriptions. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "SampleMCAsmInfo.h" 15 | #include "SampleMCTargetDesc.h" 16 | #include "InstPrinter/SampleInstPrinter.h" 17 | #include "llvm/MC/MachineLocation.h" 18 | #include "llvm/MC/MCCodeGenInfo.h" 19 | #include "llvm/MC/MCInstrInfo.h" 20 | #include "llvm/MC/MCRegisterInfo.h" 21 | #include "llvm/MC/MCStreamer.h" 22 | #include "llvm/MC/MCSubtargetInfo.h" 23 | #include "llvm/Support/ErrorHandling.h" 24 | #include "llvm/Support/TargetRegistry.h" 25 | 26 | #define GET_INSTRINFO_MC_DESC 27 | #include "SampleGenInstrInfo.inc" 28 | 29 | #define GET_SUBTARGETINFO_MC_DESC 30 | #include "SampleGenSubtargetInfo.inc" 31 | 32 | #define GET_REGINFO_MC_DESC 33 | #include "SampleGenRegisterInfo.inc" 34 | 35 | using namespace llvm; 36 | 37 | static MCInstrInfo *createSampleMCInstrInfo() { 38 | MCInstrInfo *X = new MCInstrInfo(); 39 | InitSampleMCInstrInfo(X); 40 | return X; 41 | } 42 | 43 | static MCRegisterInfo *createSampleMCRegisterInfo(StringRef TT) { 44 | MCRegisterInfo *X = new MCRegisterInfo(); 45 | InitSampleMCRegisterInfo(X, Sample::RA); 46 | return X; 47 | } 48 | 49 | static MCSubtargetInfo *createSampleMCSubtargetInfo(StringRef TT, StringRef CPU, 50 | StringRef FS) { 51 | MCSubtargetInfo *X = new MCSubtargetInfo(); 52 | InitSampleMCSubtargetInfo(X, TT, CPU, FS); 53 | return X; 54 | } 55 | 56 | static MCAsmInfo *createSampleMCAsmInfo(const Target &T, StringRef TT) { 57 | MCAsmInfo *MAI = new SampleMCAsmInfo(T, TT); 58 | 59 | MachineLocation Dst(MachineLocation::VirtualFP); 60 | MachineLocation Src(Sample::SP, 0); 61 | MAI->addInitialFrameState(0, Dst, Src); 62 | 63 | return MAI; 64 | } 65 | 66 | static MCCodeGenInfo *createSampleMCCodeGenInfo(StringRef TT, Reloc::Model RM, 67 | CodeModel::Model CM, 68 | CodeGenOpt::Level OL) { 69 | MCCodeGenInfo *X = new MCCodeGenInfo(); 70 | X->InitMCCodeGenInfo(RM, CM, OL); 71 | return X; 72 | } 73 | 74 | static MCInstPrinter *createSampleMCInstPrinter(const Target &T, 75 | unsigned SyntaxVariant, 76 | const MCAsmInfo &MAI, 77 | const MCInstrInfo &MII, 78 | const MCRegisterInfo &MRI, 79 | const MCSubtargetInfo &STI) { 80 | return new SampleInstPrinter(MAI, MII, MRI); 81 | } 82 | 83 | static MCStreamer *createMCStreamer(const Target &T, StringRef TT, 84 | MCContext &Ctx, MCAsmBackend &MAB, 85 | raw_ostream &_OS, 86 | MCCodeEmitter *_Emitter, 87 | bool RelaxAll, 88 | bool NoExecStack) { 89 | Triple TheTriple(TT); 90 | 91 | return createELFStreamer(Ctx, MAB, _OS, _Emitter, RelaxAll, NoExecStack); 92 | } 93 | 94 | extern "C" void LLVMInitializeSampleTargetMC() { 95 | // Register the MC asm info. 96 | RegisterMCAsmInfoFn X(TheSampleTarget, createSampleMCAsmInfo); 97 | // Register the MC codegen info. 98 | TargetRegistry::RegisterMCCodeGenInfo(TheSampleTarget, 99 | createSampleMCCodeGenInfo); 100 | // Register the MC instruction info. 101 | TargetRegistry::RegisterMCInstrInfo(TheSampleTarget, createSampleMCInstrInfo); 102 | // Register the MC register info. 103 | TargetRegistry::RegisterMCRegInfo(TheSampleTarget, createSampleMCRegisterInfo); 104 | // Register the MC Code Emitter 105 | TargetRegistry::RegisterMCCodeEmitter(TheSampleTarget, 106 | createSampleMCCodeEmitter); 107 | // Register the object streamer. 108 | TargetRegistry::RegisterMCObjectStreamer(TheSampleTarget, createMCStreamer); 109 | // Register the asm backend. 110 | TargetRegistry::RegisterMCAsmBackend(TheSampleTarget, 111 | createSampleAsmBackend); 112 | // Register the MC subtarget info. 113 | TargetRegistry::RegisterMCSubtargetInfo(TheSampleTarget, 114 | createSampleMCSubtargetInfo); 115 | // Register the MCInstPrinter. 116 | TargetRegistry::RegisterMCInstPrinter(TheSampleTarget, 117 | createSampleMCInstPrinter); 118 | } 119 | 120 | -------------------------------------------------------------------------------- /MCTargetDesc/SampleMCTargetDesc.h: -------------------------------------------------------------------------------- 1 | //===-- SampleMCTargetDesc.h - Sample Target Descriptions -----------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file provides Sample specific target descriptions. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLEMCTARGETDESC_H 15 | #define SAMPLEMCTARGETDESC_H 16 | 17 | #include "llvm/Support/DataTypes.h" 18 | #include "llvm/Support/Debug.h" 19 | 20 | namespace llvm { 21 | class MCAsmBackend; 22 | class MCCodeEmitter; 23 | class MCContext; 24 | class MCInstrInfo; 25 | class MCObjectWriter; 26 | class MCRegisterInfo; 27 | class MCSubtargetInfo; 28 | class StringRef; 29 | class Target; 30 | class raw_ostream; 31 | 32 | extern Target TheSampleTarget; 33 | 34 | MCCodeEmitter *createSampleMCCodeEmitter(const MCInstrInfo &MCII, 35 | const MCRegisterInfo &MRI, 36 | const MCSubtargetInfo &STI, 37 | MCContext &Ctx); 38 | 39 | MCAsmBackend *createSampleAsmBackend(const Target &T, StringRef TT, StringRef CPU); 40 | 41 | MCObjectWriter *createSampleELFObjectWriter(raw_ostream &OS, 42 | uint8_t OSABI); 43 | } // End llvm namespace 44 | 45 | // Defines symbolic names for Sample registers. This defines a mapping from 46 | // register name to register number. 47 | #define GET_REGINFO_ENUM 48 | #include "SampleGenRegisterInfo.inc" 49 | 50 | // Defines symbolic names for the Sample instructions. 51 | #define GET_INSTRINFO_ENUM 52 | #include "SampleGenInstrInfo.inc" 53 | 54 | #define GET_SUBTARGETINFO_ENUM 55 | #include "SampleGenSubtargetInfo.inc" 56 | 57 | #endif 58 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | ##===- lib/Target/Sample/Makefile ----------------------------*- Makefile -*-===## 2 | # 3 | # The LLVM Compiler Infrastructure 4 | # 5 | # This file is distributed under the University of Illinois Open Source 6 | # License. See LICENSE.TXT for details. 7 | # 8 | ##===----------------------------------------------------------------------===## 9 | 10 | LEVEL = ../../.. 11 | LIBRARYNAME = LLVMSampleCodeGen 12 | TARGET = Sample 13 | 14 | # Make sure that tblgen is run, first thing. 15 | BUILT_SOURCES = SampleGenRegisterInfo.inc SampleGenInstrInfo.inc \ 16 | SampleGenAsmWriter.inc SampleGenCodeEmitter.inc \ 17 | SampleGenDAGISel.inc SampleGenCallingConv.inc \ 18 | SampleGenSubtargetInfo.inc SampleGenMCCodeEmitter.inc \ 19 | SampleGenEDInfo.inc SampleGenDisassemblerTables.inc 20 | 21 | DIRS = InstPrinter Disassembler TargetInfo MCTargetDesc 22 | 23 | include $(LEVEL)/Makefile.common 24 | 25 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | ## setup sample target 2 | $ wget http://llvm.org/releases/3.2/llvm-3.2.src.tar.gz 3 | $ tar zxf llvm-3.2.src.tar.gz 4 | $ cd llvm-3.2.src/lib/Target 5 | $ git clone git://github.com/sabottenda/llvm-sample-target.git Sample 6 | $ cd - && cd llvm-3.2.src 7 | $ patch -p1 < ./lib/Target/Sample/config.patch 8 | 9 | ## compile and install 10 | $ cd - 11 | $ mkdir build 12 | $ cd build 13 | $ ../llvm-3.2.src/configure --prefix=/opt/llvm --enable-debug-runtime --enable-assertions --enable-debug-symbols --disable-optimized --enable-debug-runtime 14 | $ make -j4 15 | $ sudo make install 16 | -------------------------------------------------------------------------------- /Sample.h: -------------------------------------------------------------------------------- 1 | //===-- Sample.h - Top-level interface for Sample representation ----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the entry points for global functions defined in 11 | // the LLVM Sample back-end. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #ifndef TARGET_SAMPLE_H 16 | #define TARGET_SAMPLE_H 17 | 18 | #include "MCTargetDesc/SampleMCTargetDesc.h" 19 | #include "llvm/Target/TargetMachine.h" 20 | #include "llvm/Support/Debug.h" 21 | #include "llvm/Support/raw_ostream.h" 22 | #include "llvm/Support/Format.h" 23 | 24 | namespace llvm { 25 | class SampleTargetMachine; 26 | class FunctionPass; 27 | 28 | FunctionPass *createSampleISelDag(SampleTargetMachine &TM); 29 | } // end namespace llvm; 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /Sample.td: -------------------------------------------------------------------------------- 1 | //===-- Sample.td - Describe the Sample Target Machine ---------*- tablegen -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // This is the top level entry point for the Sample target. 10 | //===----------------------------------------------------------------------===// 11 | 12 | //===----------------------------------------------------------------------===// 13 | // Target-independent interfaces 14 | //===----------------------------------------------------------------------===// 15 | 16 | include "llvm/Target/Target.td" 17 | 18 | //===----------------------------------------------------------------------===// 19 | // Registers 20 | //===----------------------------------------------------------------------===// 21 | 22 | class SampleReg num, string n> : Register { 23 | field bits<4> num; 24 | let Namespace = "Sample"; 25 | } 26 | 27 | // General Purpose Registers 28 | def ZERO : SampleReg< 0, "ZERO">, DwarfRegNum<[0]>; 29 | def V0 : SampleReg< 1, "V0">, DwarfRegNum<[1]>; 30 | def A0 : SampleReg< 2, "A0">, DwarfRegNum<[2]>; 31 | def A1 : SampleReg< 3, "A1">, DwarfRegNum<[3]>; 32 | def A2 : SampleReg< 4, "A2">, DwarfRegNum<[4]>; 33 | def A3 : SampleReg< 5, "A3">, DwarfRegNum<[5]>; 34 | def T0 : SampleReg< 6, "T0">, DwarfRegNum<[6]>; 35 | def T1 : SampleReg< 7, "T1">, DwarfRegNum<[7]>; 36 | def T2 : SampleReg< 8, "T2">, DwarfRegNum<[8]>; 37 | def T3 : SampleReg< 9, "T3">, DwarfRegNum<[9]>; 38 | def S0 : SampleReg< 10, "S0">, DwarfRegNum<[10]>; 39 | def S1 : SampleReg< 11, "S1">, DwarfRegNum<[11]>; 40 | def S2 : SampleReg< 12, "S2">, DwarfRegNum<[12]>; 41 | def S3 : SampleReg< 13, "S3">, DwarfRegNum<[13]>; 42 | def SP : SampleReg< 14, "SP">, DwarfRegNum<[14]>; 43 | def RA : SampleReg< 15, "RA">, DwarfRegNum<[15]>; 44 | 45 | 46 | //===----------------------------------------------------------------------===// 47 | // Register Classes 48 | //===----------------------------------------------------------------------===// 49 | 50 | def CPURegs : RegisterClass<"Sample", [i32], 32, (add 51 | // 戻り値と引数用レジスタ (Return values and Arguments registers) 52 | V0, A0, A1, A2, A3, 53 | // 呼び出し元待避レジスタ (Caller saved registers) 54 | T0, T1, T2, T3, 55 | // 呼び出し先待避レジスタ (Callee saved registers) 56 | S0, S1, S2, S3, 57 | // 予約レジスタ (Reserved registers) 58 | ZERO, SP, RA)>; 59 | 60 | //===----------------------------------------------------------------------===// 61 | // Functional units 62 | //===----------------------------------------------------------------------===// 63 | 64 | def ALU : FuncUnit; 65 | 66 | //===----------------------------------------------------------------------===// 67 | // Instruction Itinerary classes 68 | //===----------------------------------------------------------------------===// 69 | def IICAlu : InstrItinClass; 70 | def IICLoad : InstrItinClass; 71 | def IICStore : InstrItinClass; 72 | def IICBranch : InstrItinClass; 73 | def IICPseudo : InstrItinClass; 74 | 75 | //===----------------------------------------------------------------------===// 76 | // Sample Generic instruction itineraries. 77 | //===----------------------------------------------------------------------===// 78 | 79 | def SampleGenericItineraries : ProcessorItineraries<[ALU], [], [ 80 | InstrItinData]>, 81 | InstrItinData]>, 82 | InstrItinData]>, 83 | InstrItinData]>, 84 | InstrItinData]> 85 | ]>; 86 | 87 | //===----------------------------------------------------------------------===// 88 | // Sample Operand Definitions. 89 | //===----------------------------------------------------------------------===// 90 | 91 | // load/storeで利用するオペランド.20bit 92 | // 19-16: CPURegs Operand(base) 93 | // 15-0 : 符号付き16bit整数(offset) 94 | // printMethod: base(offset) 形式で出力 95 | // EncoderMethod: bit列から2つの値を取得 96 | def mem : Operand { 97 | let PrintMethod = "printMemOperand"; 98 | let MIOperandInfo = (ops CPURegs, i16imm); 99 | let EncoderMethod = "getMemEncoding"; 100 | } 101 | 102 | // 即値ロード用のオペランド. 20bit 103 | // 19-0: 符号付き20bit整数 104 | // EncoderMethod: bit列から符号付き20bit整数を取得 105 | def movetarget : Operand { 106 | let EncoderMethod = "getMoveTargetOpValue"; 107 | } 108 | 109 | def calltarget : Operand { 110 | let EncoderMethod = "getCallTargetOpValue"; 111 | } 112 | 113 | // 符号付き20bit整数 114 | // 定数(ISD::Constant)で20bitで表現可能なもの 115 | def immSExt20 : PatLeaf<(imm), [{ return isInt<20>(N->getSExtValue()); }]>; 116 | 117 | //===----------------------------------------------------------------------===// 118 | // Sample Complex Pattern Definitions. 119 | //===----------------------------------------------------------------------===// 120 | 121 | def addr : ComplexPattern; 122 | 123 | //===----------------------------------------------------------------------===// 124 | // Sample Format Definitions. 125 | //===----------------------------------------------------------------------===// 126 | 127 | class Format val> { 128 | bits<3> Value = val; 129 | } 130 | 131 | def Pseudo : Format<0>; 132 | def FormReg0 : Format<1>; 133 | def FormReg1 : Format<2>; 134 | def FormReg2 : Format<3>; 135 | def FormReg3 : Format<4>; 136 | 137 | // Generic Sample Format 138 | class SampleInst pattern, InstrItinClass itin, Format f> 139 | : Instruction 140 | { 141 | field bits<32> Inst; 142 | Format Form = f; 143 | 144 | bits<8> Opcode = 0; 145 | 146 | let Namespace = "Sample"; 147 | let Size = 4; 148 | let Inst{31-24} = Opcode; 149 | let OutOperandList = outs; 150 | let InOperandList = ins; 151 | let AsmString = asmstr; 152 | let Pattern = pattern; 153 | let Itinerary = itin; 154 | 155 | bits<3> FormBits = Form.Value; 156 | 157 | let DecoderNamespace = "Sample"; 158 | 159 | field bits<32> SoftFail = 0; 160 | } 161 | 162 | class SamplePseudo pattern>: 163 | SampleInst { 164 | let isCodeGenOnly = 1; 165 | let isPseudo = 1; 166 | } 167 | 168 | // FormReg0 169 | class SampleInstFormReg0 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin> 170 | : SampleInst 171 | { 172 | bits<24> other; 173 | 174 | let Opcode = op; 175 | 176 | let Inst{23-0} = other; 177 | } 178 | 179 | // FormReg1 180 | class SampleInstFormReg1 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin> 181 | : SampleInst 182 | { 183 | bits<4> rc; 184 | bits<20> other; 185 | 186 | let Opcode = op; 187 | 188 | let Inst{23-20} = rc; 189 | let Inst{19-0} = other; 190 | } 191 | 192 | // FormReg3 193 | class SampleInstFormReg3 op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin> 194 | : SampleInst 195 | { 196 | bits<4> rc; 197 | bits<4> ra; 198 | bits<4> rb; 199 | bits<12> other; 200 | 201 | let Opcode = op; 202 | 203 | let Inst{23-20} = rc; 204 | let Inst{19-16} = ra; 205 | let Inst{15-12} = rb; 206 | let Inst{11-0} = other; 207 | } 208 | 209 | //===----------------------------------------------------------------------===// 210 | // Sample profiles and nodes 211 | //===----------------------------------------------------------------------===// 212 | 213 | // SDTypeProfileはSDNodeの必要条件を定義する。 214 | // 第一引数: 結果Node数 215 | // 第二引数: オペランドNode数 216 | // 第三引数: 制約条件(SDTypeConstraint) 217 | 218 | // SDTCisInt: N番目のオペランドはInt型 219 | // SDTCisVT: N番目のオペランドはVT型 220 | 221 | // SDNodeは新しいSDNodeを定義する。 222 | // 第一引数: opcode 223 | // 第二引数: 制約条件(SDTypeProfile) 224 | // 第三引数: SDNodeProperty 225 | 226 | // SDNodeProperty 227 | // SDNPCommutative : // 可換 228 | // SDNPAssociative : // 結合法則 229 | // SDNPHasChain : // R/W chain operand and result 230 | // SDNPOutGlue : // Write a flag result 231 | // SDNPInGlue : // Read a flag operand 232 | // SDNPOptInGlue : // Optionally read a flag operand 233 | // SDNPMayStore : // May write to memory, sets 'mayStore'. 234 | // SDNPMayLoad : // May read memory, sets 'mayLoad'. 235 | // SDNPSideEffect : // Sets 'HasUnmodelledSideEffects'. 236 | // SDNPMemOperand : // Touches memory, has assoc MemOperand 237 | // SDNPVariadic : // 可変引数を持つ 238 | // SDNPWantRoot : // ComplexPattern gets the root of match 239 | // SDNPWantParent : // ComplexPattern gets the parent 240 | 241 | def SDT_SampleRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 242 | def SampleRet : SDNode<"SampleISD::Ret", SDT_SampleRet, 243 | [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 244 | 245 | def SDT_SampleCall : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 246 | 247 | def SampleCall : SDNode<"SampleISD::Call",SDT_SampleCall, 248 | [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 249 | SDNPVariadic]>; 250 | 251 | def SDT_SampleCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>; 252 | def SDT_SampleCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 253 | 254 | def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SampleCallSeqStart, 255 | [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; 256 | def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SampleCallSeqEnd, 257 | [SDNPHasChain, SDNPSideEffect, 258 | SDNPOptInGlue, SDNPOutGlue]>; 259 | 260 | //===----------------------------------------------------------------------===// 261 | // Instructions specific format 262 | //===----------------------------------------------------------------------===// 263 | 264 | // Arithmetic and logical instructions with 3 register operands. 265 | class ArithLogicInst op, string asmstr, SDNode OpNode, InstrItinClass itin, RegisterClass RC> 266 | : SampleInstFormReg3 { 269 | } 270 | 271 | // Load/Store common form 272 | // DecoderMethod: objdumpなどでバイナリから値をデコードする 273 | class FMem op, dag outs, dag ins, string asmstr, list pattern, InstrItinClass itin> 274 | : SampleInstFormReg1 { 275 | bits<20> addr; 276 | let Inst{19-0} = addr; 277 | let DecoderMethod = "DecodeMem"; 278 | } 279 | 280 | // Load 281 | let canFoldAsLoad = 1 in 282 | class LoadM op, string asmstr, RegisterClass RC>: 283 | FMem; 286 | 287 | // Store 288 | class StoreM op, string asmstr, RegisterClass RC>: 289 | FMem; 292 | 293 | // Return 294 | class RetInst op, string asmstr>: 295 | SampleInstFormReg1 { 297 | let isBranch=1; 298 | let isTerminator=1; 299 | let isBarrier=1; 300 | let isReturn=1; 301 | } 302 | 303 | // Load Immediate 304 | // DecoderMethod: 即値ロード用のデコード 305 | class LoadI op, string asmstr>: 306 | SampleInstFormReg1 { 308 | let DecoderMethod = "DecodeMoveTarget"; 309 | } 310 | 311 | class Call op, string asmstr>: 312 | SampleInstFormReg0 { 315 | let isCall=1; 316 | let DecoderMethod = "DecodeCallTarget"; 317 | } 318 | 319 | //===----------------------------------------------------------------------===// 320 | // Sample Instruction definition 321 | //===----------------------------------------------------------------------===// 322 | 323 | def LOAD : LoadM<0x00, "load", CPURegs>; 324 | def STORE : StoreM<0x01, "store", CPURegs>; 325 | def MOVE : LoadI<0x02, "move">; 326 | def CALL : Call<0x03, "call">; 327 | def RET : RetInst<0x04, "ret">; 328 | def ADD : ArithLogicInst<0x05, "add", add, IICAlu, CPURegs>; 329 | def SUB : ArithLogicInst<0x06, "sub", sub, IICAlu, CPURegs>; 330 | 331 | //===----------------------------------------------------------------------===// 332 | // Pseudo instructions 333 | //===----------------------------------------------------------------------===// 334 | 335 | let Defs = [SP], Uses = [SP] in { 336 | def ADJCALLSTACKDOWN : SamplePseudo<(outs), (ins i32imm:$amt), 337 | "!ADJCALLSTACKDOWN $amt", 338 | [(callseq_start timm:$amt)]>; 339 | def ADJCALLSTACKUP : SamplePseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), 340 | "!ADJCALLSTACKUP $amt1", 341 | [(callseq_end timm:$amt1, timm:$amt2)]>; 342 | } 343 | 344 | //===----------------------------------------------------------------------===// 345 | // Arbitrary patterns that map to one or more instructions 346 | //===----------------------------------------------------------------------===// 347 | 348 | def : Pat<(SampleCall (i32 tglobaladdr:$dst)), 349 | (CALL tglobaladdr:$dst)>; 350 | def : Pat<(SampleCall (i32 texternalsym:$dst)), 351 | (CALL texternalsym:$dst)>; 352 | 353 | //===----------------------------------------------------------------------===// 354 | // Sample Calling Convention 355 | //===----------------------------------------------------------------------===// 356 | 357 | def CC_Sample : CallingConv<[ 358 | // i8/i16型の引数はi32型に昇格する 359 | CCIfType<[i8, i16], CCPromoteToType>, 360 | 361 | // 整数型はレジスタに渡す 362 | CCIfType<[i32], CCAssignToReg<[A0, A1, A2, A3]>> 363 | ]>; 364 | 365 | def RetCC_Sample : CallingConv<[ 366 | // i32型はV0レジスタに渡す 367 | CCIfType<[i32], CCAssignToReg<[V0]>> 368 | ]>; 369 | 370 | //===----------------------------------------------------------------------===// 371 | // Callee-saved register lists. 372 | //===----------------------------------------------------------------------===// 373 | 374 | // 呼び出し先待避レジスタ(Callee-saved register) 375 | def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "S%u", 3, 0), RA)>; 376 | 377 | //===----------------------------------------------------------------------===// 378 | // Sample processors supported. 379 | //===----------------------------------------------------------------------===// 380 | 381 | def SampleInstrInfo : InstrInfo; 382 | 383 | def : Processor<"sample32", SampleGenericItineraries, []>; 384 | 385 | def SampleAsmWriter : AsmWriter { 386 | string AsmWriterClassName = "InstPrinter"; 387 | bit isMCAsmWriter = 1; 388 | } 389 | 390 | def Sample : Target { 391 | let InstructionSet = SampleInstrInfo; 392 | let AssemblyWriters = [SampleAsmWriter]; 393 | } 394 | -------------------------------------------------------------------------------- /SampleAsmPrinter.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleAsmPrinter.cpp - Sample LLVM assembly writer ----------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains a printer that converts from our internal representation 11 | // of machine-dependent LLVM code to the Sample assembly language. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #define DEBUG_TYPE "asm-printer" 16 | #include "Sample.h" 17 | #include "SampleInstrInfo.h" 18 | #include "SampleMCInstLower.h" 19 | #include "SampleTargetMachine.h" 20 | #include "InstPrinter/SampleInstPrinter.h" 21 | #include "llvm/Constants.h" 22 | #include "llvm/DerivedTypes.h" 23 | #include "llvm/Module.h" 24 | #include "llvm/Assembly/Writer.h" 25 | #include "llvm/CodeGen/AsmPrinter.h" 26 | #include "llvm/CodeGen/MachineModuleInfo.h" 27 | #include "llvm/CodeGen/MachineFunctionPass.h" 28 | #include "llvm/CodeGen/MachineConstantPool.h" 29 | #include "llvm/CodeGen/MachineInstr.h" 30 | #include "llvm/MC/MCAsmInfo.h" 31 | #include "llvm/MC/MCInst.h" 32 | #include "llvm/MC/MCStreamer.h" 33 | #include "llvm/MC/MCSymbol.h" 34 | #include "llvm/Target/Mangler.h" 35 | #include "llvm/Support/TargetRegistry.h" 36 | using namespace llvm; 37 | 38 | namespace { 39 | class SampleAsmPrinter : public AsmPrinter { 40 | public: 41 | SampleAsmPrinter(TargetMachine &TM, MCStreamer &Streamer) 42 | : AsmPrinter(TM, Streamer) {} 43 | 44 | virtual const char *getPassName() const { 45 | return "Sample Assembly Printer"; 46 | } 47 | 48 | // should overwrite functions 49 | void EmitInstruction(const MachineInstr *MI) /*override*/; 50 | }; 51 | } // end of anonymous namespace 52 | 53 | void SampleAsmPrinter:: 54 | EmitInstruction(const MachineInstr *MI) { 55 | DEBUG(dbgs() << ">> SampleAsmPinter::EmitInstruction <<\n"); 56 | DEBUG(MI->dump()); 57 | SampleMCInstLower MCInstLowering(OutContext, *Mang, *this); 58 | MCInst TmpInst; 59 | MCInstLowering.Lower(MI, TmpInst); 60 | OutStreamer.EmitInstruction(TmpInst); 61 | } 62 | 63 | // Force static initialization. 64 | extern "C" void LLVMInitializeSampleAsmPrinter() { 65 | RegisterAsmPrinter X(TheSampleTarget); 66 | } 67 | -------------------------------------------------------------------------------- /SampleFrameLowering.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleFrameLowering.cpp - Sample Frame Information --------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the Sample implementation of TargetFrameLowering class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "SampleFrameLowering.h" 15 | #include "SampleInstrInfo.h" 16 | #include "SampleMachineFunction.h" 17 | #include "MCTargetDesc/SampleMCTargetDesc.h" 18 | #include "llvm/Function.h" 19 | #include "llvm/CodeGen/MachineFrameInfo.h" 20 | #include "llvm/CodeGen/MachineFunction.h" 21 | #include "llvm/CodeGen/MachineInstrBuilder.h" 22 | #include "llvm/CodeGen/MachineModuleInfo.h" 23 | #include "llvm/CodeGen/MachineRegisterInfo.h" 24 | #include "llvm/DataLayout.h" 25 | #include "llvm/Target/TargetOptions.h" 26 | #include "llvm/Support/CommandLine.h" 27 | 28 | using namespace llvm; 29 | 30 | bool SampleFrameLowering:: 31 | hasFP(const MachineFunction &MF) const { 32 | return false; 33 | } 34 | 35 | void SampleFrameLowering:: 36 | emitPrologue(MachineFunction &MF) const { 37 | DEBUG(dbgs() << ">> SampleFrameLowering::emitPrologue <<\n"); 38 | 39 | MachineBasicBlock &MBB = MF.front(); 40 | MachineFrameInfo *MFI = MF.getFrameInfo(); 41 | 42 | const SampleInstrInfo &TII = 43 | *static_cast(MF.getTarget().getInstrInfo()); 44 | 45 | MachineBasicBlock::iterator MBBI = MBB.begin(); 46 | DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); 47 | 48 | // allocate fixed size for simplicity 49 | uint64_t StackSize = 4 * 16; 50 | 51 | // Update stack size 52 | MFI->setStackSize(StackSize); 53 | 54 | BuildMI(MBB, MBBI, dl, TII.get(Sample::MOVE), Sample::T0) 55 | .addImm(-StackSize); 56 | BuildMI(MBB, MBBI, dl, TII.get(Sample::ADD), Sample::SP) 57 | .addReg(Sample::SP) 58 | .addReg(Sample::T0); 59 | } 60 | 61 | void SampleFrameLowering:: 62 | emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { 63 | DEBUG(dbgs() << ">> SampleFrameLowering::emitEpilogue <<\n"); 64 | 65 | MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 66 | MachineFrameInfo *MFI = MF.getFrameInfo(); 67 | const SampleInstrInfo &TII = 68 | *static_cast(MF.getTarget().getInstrInfo()); 69 | DebugLoc dl = MBBI->getDebugLoc(); 70 | 71 | // Get the number of bytes from FrameInfo 72 | uint64_t StackSize = MFI->getStackSize(); 73 | 74 | // Adjust stack. 75 | BuildMI(MBB, MBBI, dl, TII.get(Sample::MOVE), Sample::T0) 76 | .addImm(StackSize); 77 | BuildMI(MBB, MBBI, dl, TII.get(Sample::ADD), Sample::SP) 78 | .addReg(Sample::SP) 79 | .addReg(Sample::T0); 80 | } 81 | -------------------------------------------------------------------------------- /SampleFrameLowering.h: -------------------------------------------------------------------------------- 1 | //===-- SampleFrameLowering.h - Define frame lowering for Sample ----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLE_FRAMELOWERING_H 15 | #define SAMPLE_FRAMELOWERING_H 16 | 17 | #include "Sample.h" 18 | #include "SampleSubtarget.h" 19 | #include "llvm/Target/TargetFrameLowering.h" 20 | 21 | namespace llvm { 22 | class SampleSubtarget; 23 | 24 | class SampleFrameLowering : public TargetFrameLowering { 25 | protected: 26 | const SampleSubtarget &STI; 27 | 28 | public: 29 | explicit SampleFrameLowering(const SampleSubtarget &sti) 30 | : TargetFrameLowering(StackGrowsDown, 8, 0), STI(sti) { 31 | } 32 | 33 | /// emitProlog/emitEpilog - These methods insert prolog and epilog code into 34 | /// the function. 35 | void emitPrologue(MachineFunction &MF) const /*override*/; 36 | void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const /*override*/; 37 | bool hasFP(const MachineFunction &MF) const /*override*/; 38 | }; 39 | } // End llvm namespace 40 | 41 | #endif 42 | -------------------------------------------------------------------------------- /SampleISelDAGtoDAG.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Sample --------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file defines an instruction selector for the Sample target. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #define DEBUG_TYPE "sample-isel" 15 | #include "Sample.h" 16 | #include "SampleRegisterInfo.h" 17 | #include "SampleSubtarget.h" 18 | #include "SampleTargetMachine.h" 19 | #include "MCTargetDesc/SampleMCTargetDesc.h" 20 | #include "llvm/GlobalValue.h" 21 | #include "llvm/Instructions.h" 22 | #include "llvm/Intrinsics.h" 23 | #include "llvm/Support/CFG.h" 24 | #include "llvm/Type.h" 25 | #include "llvm/CodeGen/MachineConstantPool.h" 26 | #include "llvm/CodeGen/MachineFunction.h" 27 | #include "llvm/CodeGen/MachineFrameInfo.h" 28 | #include "llvm/CodeGen/MachineInstrBuilder.h" 29 | #include "llvm/CodeGen/MachineRegisterInfo.h" 30 | #include "llvm/CodeGen/SelectionDAGISel.h" 31 | #include "llvm/CodeGen/SelectionDAGNodes.h" 32 | #include "llvm/Target/TargetMachine.h" 33 | #include "llvm/Support/Debug.h" 34 | #include "llvm/Support/ErrorHandling.h" 35 | #include "llvm/Support/raw_ostream.h" 36 | 37 | using namespace llvm; 38 | 39 | //===----------------------------------------------------------------------===// 40 | // Instruction Selector Implementation 41 | //===----------------------------------------------------------------------===// 42 | 43 | //===----------------------------------------------------------------------===// 44 | // SampleDAGToDAGISel - Sample specific code to select Sample machine 45 | // instructions for SelectionDAG operations. 46 | //===----------------------------------------------------------------------===// 47 | namespace { 48 | 49 | class SampleDAGToDAGISel : public SelectionDAGISel { 50 | 51 | /// TM - Keep a reference to SampleTargetMachine. 52 | const SampleTargetMachine &TM; 53 | 54 | /// Subtarget - Keep a pointer to the SampleSubtarget around so that we can 55 | /// make the right decision when generating code for different targets. 56 | const SampleSubtarget &Subtarget; 57 | 58 | public: 59 | explicit SampleDAGToDAGISel(SampleTargetMachine &tm) : 60 | SelectionDAGISel(tm), 61 | TM(tm), 62 | Subtarget(tm.getSubtarget()) {} 63 | 64 | // Pass Name 65 | virtual const char *getPassName() const { 66 | return "Sample DAG->DAG Pattern Instruction Selection"; 67 | } 68 | 69 | private: 70 | // Include the pieces autogenerated from the target description. 71 | #include "SampleGenDAGISel.inc" 72 | 73 | /// getTargetMachine - Return a reference to the TargetMachine, casted 74 | /// to the target-specific type. 75 | const SampleTargetMachine &getTargetMachine() { 76 | return static_cast(TM); 77 | } 78 | 79 | /// getInstrInfo - Return a reference to the TargetInstrInfo, casted 80 | /// to the target-specific type. 81 | const SampleInstrInfo *getInstrInfo() { 82 | return getTargetMachine().getInstrInfo(); 83 | } 84 | 85 | SDNode *Select(SDNode *N) /*override*/; 86 | 87 | // Complex Pattern. 88 | bool SelectAddr(SDValue N, SDValue &Base, SDValue &Offset); 89 | }; 90 | } 91 | 92 | /// ComplexPattern used on SampleInstrInfo 93 | /// Used on Sample Load/Store instructions 94 | bool SampleDAGToDAGISel:: 95 | SelectAddr(SDValue N, SDValue &Base, SDValue &Offset) { 96 | EVT ValTy = N.getValueType(); 97 | 98 | if (FrameIndexSDNode *FIN = dyn_cast(N)) { 99 | Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); 100 | Offset = CurDAG->getTargetConstant(0, ValTy); 101 | return true; 102 | } 103 | 104 | llvm_unreachable("Unknown pattern"); 105 | return true; 106 | } 107 | 108 | /// Select instructions not customized! Used for 109 | /// expanded, promoted and normal instructions 110 | SDNode* SampleDAGToDAGISel:: 111 | Select(SDNode *Node) { 112 | // Select the default instruction 113 | SDNode *ResNode = SelectCode(Node); 114 | 115 | DEBUG(errs() << "=> "); 116 | if (ResNode == NULL || ResNode == Node) 117 | DEBUG(Node->dumpr(CurDAG)); 118 | else 119 | DEBUG(ResNode->dumpr(CurDAG)); 120 | DEBUG(errs() << "\n"); 121 | return ResNode; 122 | } 123 | 124 | /// createSampleISelDag - This pass converts a legalized DAG into a 125 | /// Sample-specific DAG, ready for instruction scheduling. 126 | FunctionPass *llvm::createSampleISelDag(SampleTargetMachine &TM) { 127 | return new SampleDAGToDAGISel(TM); 128 | } 129 | -------------------------------------------------------------------------------- /SampleISelLowering.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleISelLowering.cpp - Sample DAG Lowering Implementation -----------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file defines the interfaces that Sample uses to lower LLVM code into a 11 | // selection DAG. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #define DEBUG_TYPE "sample-lower" 16 | #include "SampleISelLowering.h" 17 | #include "SampleMachineFunction.h" 18 | #include "SampleTargetMachine.h" 19 | #include "SampleSubtarget.h" 20 | #include "InstPrinter/SampleInstPrinter.h" 21 | #include "MCTargetDesc/SampleMCTargetDesc.h" 22 | #include "llvm/DerivedTypes.h" 23 | #include "llvm/Function.h" 24 | #include "llvm/GlobalVariable.h" 25 | #include "llvm/Intrinsics.h" 26 | #include "llvm/CallingConv.h" 27 | #include "llvm/CodeGen/CallingConvLower.h" 28 | #include "llvm/CodeGen/MachineFrameInfo.h" 29 | #include "llvm/CodeGen/MachineFunction.h" 30 | #include "llvm/CodeGen/MachineInstrBuilder.h" 31 | #include "llvm/CodeGen/MachineRegisterInfo.h" 32 | #include "llvm/CodeGen/SelectionDAGISel.h" 33 | #include "llvm/CodeGen/ValueTypes.h" 34 | #include "llvm/Support/Debug.h" 35 | #include "llvm/Support/ErrorHandling.h" 36 | #include "llvm/Support/raw_ostream.h" 37 | 38 | #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" 39 | using namespace llvm; 40 | 41 | std::string getFlagsString(const ISD::ArgFlagsTy &Flags) { 42 | if (Flags.isZExt()) { 43 | return "ZExt"; 44 | } else if (Flags.isSExt()) { 45 | return "SExt"; 46 | } else if (Flags.isInReg()) { 47 | return "Reg"; 48 | } else if (Flags.isSRet()) { 49 | return "SRet"; 50 | } else if (Flags.isByVal()) { 51 | return "ByVal"; 52 | } else if (Flags.isNest()) { 53 | return "Nest"; 54 | } else { 55 | return "No Flags"; 56 | } 57 | } 58 | 59 | SampleTargetLowering:: 60 | SampleTargetLowering(SampleTargetMachine &TM) 61 | : TargetLowering(TM, new TargetLoweringObjectFileELF()), 62 | Subtarget(*TM.getSubtargetImpl()) { 63 | DEBUG(dbgs() << ">> SampleTargetLowering::constructor <<\n"); 64 | 65 | // booleanをどう表すかを定義 66 | setBooleanContents(ZeroOrOneBooleanContent); 67 | setBooleanVectorContents(ZeroOrOneBooleanContent); 68 | 69 | // ターゲットで利用できるレジスタを登録 70 | addRegisterClass(MVT::i32, &Sample::CPURegsRegClass); 71 | 72 | // (符号)拡張ロード命令が対応していない型の操作方法を登録 73 | setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 74 | setLoadExtAction(ISD::EXTLOAD, MVT::i8, Promote); 75 | setLoadExtAction(ISD::EXTLOAD, MVT::i16, Promote); 76 | setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 77 | setLoadExtAction(ISD::ZEXTLOAD, MVT::i8, Promote); 78 | setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Promote); 79 | setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 80 | setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Promote); 81 | setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Promote); 82 | 83 | // 関数のアラインメント 84 | setMinFunctionAlignment(2); 85 | 86 | // スタックポインタのレジスタを指定 87 | setStackPointerRegisterToSaveRestore(Sample::SP); 88 | 89 | // レジスタの操作方法を計算 90 | computeRegisterProperties(); 91 | } 92 | 93 | SDValue SampleTargetLowering:: 94 | LowerOperation(SDValue Op, SelectionDAG &DAG) const { 95 | llvm_unreachable("not supported operation"); 96 | return SDValue(); 97 | } 98 | 99 | //===----------------------------------------------------------------------===// 100 | // Calling Convention Implementation 101 | //===----------------------------------------------------------------------===// 102 | 103 | #include "SampleGenCallingConv.inc" 104 | 105 | SDValue SampleTargetLowering:: 106 | LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 107 | bool isVarArg, 108 | const SmallVectorImpl &Ins, 109 | DebugLoc dl, SelectionDAG &DAG, 110 | SmallVectorImpl &InVals) const { 111 | DEBUG(dbgs() << ">> SampleTargetLowering::LowerFormalArguments <<\n"); 112 | DEBUG(dbgs() << " Chain: "; Chain->dumpr();); 113 | 114 | MachineFunction &MF = DAG.getMachineFunction(); 115 | MachineFrameInfo *MFI = MF.getFrameInfo(); 116 | MachineRegisterInfo &RegInfo = MF.getRegInfo(); 117 | 118 | // Assign locations to all of the incoming arguments. 119 | SmallVector ArgLocs; 120 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 121 | getTargetMachine(), ArgLocs, *DAG.getContext()); 122 | CCInfo.AnalyzeFormalArguments(Ins, CC_Sample); 123 | 124 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 125 | CCValAssign &VA = ArgLocs[i]; 126 | if (VA.isRegLoc()) { 127 | // 引数がレジスタで渡された場合 128 | EVT RegVT = VA.getLocVT(); 129 | const TargetRegisterClass *RC = &Sample::CPURegsRegClass; 130 | 131 | DEBUG(dbgs() << " Reg N" << i 132 | << " LowerFormalArguments Unhandled argument type: " 133 | << RegVT.getSimpleVT().SimpleTy << "\n";); 134 | if (VA.getLocInfo() != CCValAssign::Full) { 135 | llvm_unreachable("not supported yet"); 136 | } 137 | 138 | unsigned VReg = RegInfo.createVirtualRegister(RC); 139 | RegInfo.addLiveIn(VA.getLocReg(), VReg); 140 | SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT); 141 | InVals.push_back(ArgValue); 142 | } else { // VA.isRegLoc() 143 | // 引数がメモリで渡された場合 144 | 145 | // Sanity check 146 | assert(VA.isMemLoc()); 147 | // Load the argument to a virtual register 148 | unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; 149 | DEBUG(dbgs() << " Mem N" << i 150 | << " LowerFormalArguments Unhandled argument type: " 151 | << EVT(VA.getLocVT()).getEVTString() 152 | << "\n";); 153 | 154 | // フレームインデックスを作成する 155 | int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset(), true); 156 | 157 | // スタックから引数を取得するためにloadノードを作成する 158 | SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); 159 | InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, 160 | MachinePointerInfo::getFixedStack(FI), 161 | false, false, false, 0)); 162 | } 163 | } 164 | 165 | DEBUG( 166 | for (SmallVectorImpl::const_iterator i = InVals.begin(); 167 | i != InVals.end(); ++i) { 168 | dbgs() << " InVals: "; i->getNode()->dump(); 169 | }); 170 | 171 | DEBUG(dbgs() << ">> done LowerFormalArguments <<\n";); 172 | return Chain; 173 | } 174 | 175 | //===----------------------------------------------------------------------===// 176 | // Call Calling Convention Implementation 177 | //===----------------------------------------------------------------------===// 178 | 179 | /// LowerCall - functions arguments are copied from virtual regs to 180 | /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 181 | /// TODO: isTailCall. 182 | SDValue SampleTargetLowering:: 183 | LowerCall(CallLoweringInfo &CLI, 184 | SmallVectorImpl &InVals) const { 185 | SelectionDAG &DAG = CLI.DAG; 186 | DebugLoc &dl = CLI.DL; 187 | SmallVector &Outs = CLI.Outs; 188 | SmallVector &OutVals = CLI.OutVals; 189 | SmallVector &Ins = CLI.Ins; 190 | SDValue InChain = CLI.Chain; 191 | SDValue Callee = CLI.Callee; 192 | bool &isTailCall = CLI.IsTailCall; 193 | CallingConv::ID CallConv = CLI.CallConv; 194 | bool isVarArg = CLI.IsVarArg; 195 | 196 | DEBUG(dbgs() << ">> SampleTargetLowering::LowerCall <<\n"); 197 | DEBUG(dbgs() << " InChain: "; InChain->dumpr();); 198 | DEBUG(dbgs() << " Callee: "; Callee->dumpr();); 199 | 200 | // 末尾呼び出しは未対応 201 | isTailCall = false; 202 | 203 | // 関数のオペランドを解析してオペランドをレジスタに割り当てる 204 | SmallVector ArgLocs; 205 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 206 | getTargetMachine(), ArgLocs, *DAG.getContext()); 207 | 208 | CCInfo.AnalyzeCallOperands(Outs, CC_Sample); 209 | 210 | // スタックを何Byte使っているか取得 211 | unsigned NumBytes = CCInfo.getNextStackOffset(); 212 | DEBUG(dbgs() << " stack offset: " << NumBytes << "\n"); 213 | 214 | // 関数呼び出し開始のNode 215 | InChain = DAG.getCALLSEQ_START(InChain , 216 | DAG.getConstant(NumBytes, getPointerTy(), true)); 217 | 218 | SmallVector, 4> RegsToPass; 219 | SDValue StackPtr; 220 | 221 | // 引数をRegsToPassに追加していく 222 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 223 | SDValue Arg = OutVals[i]; 224 | CCValAssign &VA = ArgLocs[i]; 225 | ISD::ArgFlagsTy Flags = Outs[i].Flags; 226 | DEBUG(dbgs() << " Arg: "; Arg->dumpr()); 227 | 228 | // 引数が数値 229 | if (Flags.isByVal()) { 230 | assert(Flags.getByValSize() && 231 | "ByVal args of size 0 should have been ignored by front-end."); 232 | llvm_unreachable("ByVal arguments are not supported"); 233 | continue; 234 | } 235 | 236 | // 必要に応じてPromoteする 237 | switch (VA.getLocInfo()) { 238 | default: llvm_unreachable("Unknown loc info!"); 239 | case CCValAssign::Full: break; 240 | case CCValAssign::SExt: 241 | Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 242 | break; 243 | case CCValAssign::ZExt: 244 | Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 245 | break; 246 | case CCValAssign::AExt: 247 | Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 248 | break; 249 | } 250 | 251 | // レジスタ経由の引数はRegsToPassに追加 252 | if (VA.isRegLoc()) { 253 | DEBUG(dbgs() << " Reg: " << VA.getLocReg() << "\n"); 254 | RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 255 | } else { 256 | assert(VA.isMemLoc()); 257 | llvm_unreachable("MemLoc arguments are not supported"); 258 | } 259 | } 260 | 261 | // レジスタをコピーするノードを作成 262 | SDValue InFlag; 263 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 264 | InChain = DAG.getCopyToReg(InChain, dl, RegsToPass[i].first, 265 | RegsToPass[i].second, InFlag); 266 | InFlag = InChain.getValue(1); 267 | } 268 | 269 | if (GlobalAddressSDNode *G = dyn_cast(Callee)) { 270 | Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32); 271 | DEBUG(dbgs() << " Global: " << Callee.getNode() << "\n"); 272 | } else if (ExternalSymbolSDNode *E = dyn_cast(Callee)) { 273 | Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32); 274 | DEBUG(dbgs() << " External: " << Callee.getNode() << "\n"); 275 | } 276 | 277 | SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 278 | SmallVector Ops; 279 | Ops.push_back(InChain); 280 | Ops.push_back(Callee); 281 | 282 | // 引数のレジスタをリストに追加 283 | for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 284 | Ops.push_back(DAG.getRegister(RegsToPass[i].first, 285 | RegsToPass[i].second.getValueType())); 286 | } 287 | 288 | if (InFlag.getNode()) 289 | Ops.push_back(InFlag); 290 | 291 | InChain = DAG.getNode(SampleISD::Call, dl, NodeTys, &Ops[0], Ops.size()); 292 | InFlag = InChain.getValue(1); 293 | 294 | // 関数呼び出し終了のNode 295 | InChain = DAG.getCALLSEQ_END(InChain, 296 | DAG.getConstant(NumBytes, getPointerTy(), true), 297 | DAG.getConstant(0, getPointerTy(), true), 298 | InFlag); 299 | InFlag = InChain.getValue(1); 300 | 301 | // 戻り値の処理 302 | return LowerCallResult(InChain, InFlag, CallConv, isVarArg, 303 | Ins, dl, DAG, InVals); 304 | } 305 | 306 | /// LowerCallResult - Lower the result values of a call into the 307 | /// appropriate copies out of appropriate physical registers. 308 | SDValue SampleTargetLowering:: 309 | LowerCallResult(SDValue Chain, SDValue InFlag, 310 | CallingConv::ID CallConv, bool isVarArg, 311 | const SmallVectorImpl &Ins, 312 | DebugLoc dl, SelectionDAG &DAG, 313 | SmallVectorImpl &InVals) const { 314 | // Assign locations to each value returned by this call. 315 | SmallVector RVLocs; 316 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 317 | getTargetMachine(), RVLocs, *DAG.getContext()); 318 | 319 | CCInfo.AnalyzeCallResult(Ins, RetCC_Sample); 320 | 321 | // 結果レジスタをコピー 322 | for (unsigned i = 0; i != RVLocs.size(); ++i) { 323 | Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 324 | RVLocs[i].getValVT(), InFlag).getValue(1); 325 | InFlag = Chain.getValue(2); 326 | InVals.push_back(Chain.getValue(0)); 327 | } 328 | 329 | return Chain; 330 | } 331 | 332 | //===----------------------------------------------------------------------===// 333 | // Return Value Calling Convention Implementation 334 | //===----------------------------------------------------------------------===// 335 | 336 | SDValue SampleTargetLowering:: 337 | LowerReturn(SDValue Chain, 338 | CallingConv::ID CallConv, bool isVarArg, 339 | const SmallVectorImpl &Outs, 340 | const SmallVectorImpl &OutVals, 341 | DebugLoc dl, SelectionDAG &DAG) const { 342 | DEBUG(dbgs() << ">> SampleTargetLowering::LowerReturn <<\n"); 343 | DEBUG(dbgs() << " Chain: "; Chain->dumpr();); 344 | 345 | SmallVector RVLocs; 346 | CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 347 | getTargetMachine(), RVLocs, *DAG.getContext()); 348 | 349 | // 戻り値を解析する 350 | CCInfo.AnalyzeReturn(Outs, RetCC_Sample); 351 | 352 | // この関数で最初の戻り値の場合はレジスタをliveoutに追加 353 | if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 354 | for (unsigned i = 0; i != RVLocs.size(); ++i) 355 | if (RVLocs[i].isRegLoc()) 356 | DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 357 | } 358 | 359 | SDValue Flag; 360 | 361 | // 戻り値をレジスタにコピーするノードを作成 362 | for (unsigned i = 0; i != RVLocs.size(); ++i) { 363 | CCValAssign &VA = RVLocs[i]; 364 | assert(VA.isRegLoc() && "Can only return in registers!"); 365 | 366 | Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 367 | OutVals[i], Flag); 368 | 369 | // Guarantee that all emitted copies are stuck together, 370 | // avoiding something bad. 371 | Flag = Chain.getValue(1); 372 | } 373 | 374 | DEBUG( 375 | for (SmallVectorImpl::const_iterator i = OutVals.begin(); 376 | i != OutVals.end(); ++i) { 377 | dbgs() << " OutVals: "; i->getNode()->dump(); 378 | }); 379 | 380 | // 常に "ret $ra" を生成 381 | if (Flag.getNode()) 382 | return DAG.getNode(SampleISD::Ret, dl, MVT::Other, 383 | Chain, DAG.getRegister(Sample::RA, MVT::i32), Flag); 384 | else // Return Void 385 | return DAG.getNode(SampleISD::Ret, dl, MVT::Other, 386 | Chain, DAG.getRegister(Sample::RA, MVT::i32)); 387 | } 388 | -------------------------------------------------------------------------------- /SampleISelLowering.h: -------------------------------------------------------------------------------- 1 | //===-- SampleISelLowering.h - Sample DAG Lowering Interface --------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file defines the interfaces that Sample uses to lower LLVM code into a 11 | // selection DAG. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #ifndef SAMPLE_ISELLOWERING_H 16 | #define SAMPLE_ISELLOWERING_H 17 | 18 | #include "Sample.h" 19 | #include "SampleSubtarget.h" 20 | #include "llvm/CodeGen/SelectionDAG.h" 21 | #include "llvm/Target/TargetLowering.h" 22 | 23 | namespace llvm { 24 | namespace SampleISD { 25 | enum { 26 | FIRST_NUMBER = ISD::BUILTIN_OP_END, 27 | 28 | // Jump and link (call) 29 | Call, 30 | 31 | // Return 32 | Ret 33 | }; 34 | } 35 | 36 | class SampleSubtarget; 37 | //===--------------------------------------------------------------------===// 38 | // TargetLowering Implementation 39 | //===--------------------------------------------------------------------===// 40 | 41 | class SampleTargetLowering : public TargetLowering { 42 | const SampleSubtarget &Subtarget; 43 | 44 | public: 45 | explicit SampleTargetLowering(SampleTargetMachine &TM); 46 | 47 | /// LowerOperation - Provide custom lowering hooks for some operations. 48 | virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; 49 | virtual SDValue 50 | LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, 51 | bool isVarArg, 52 | const SmallVectorImpl &Ins, 53 | DebugLoc dl, SelectionDAG &DAG, 54 | SmallVectorImpl &InVals) const; 55 | 56 | virtual SDValue 57 | LowerCall(CallLoweringInfo &CLI, 58 | SmallVectorImpl &InVals) const; 59 | 60 | virtual SDValue 61 | LowerCallResult(SDValue Chain, SDValue InFlag, 62 | CallingConv::ID CallConv, bool isVarArg, 63 | const SmallVectorImpl &Ins, 64 | DebugLoc dl, SelectionDAG &DAG, 65 | SmallVectorImpl &InVals) const; 66 | 67 | virtual SDValue 68 | LowerReturn(SDValue Chain, 69 | CallingConv::ID CallConv, bool isVarArg, 70 | const SmallVectorImpl &Outs, 71 | const SmallVectorImpl &OutVals, 72 | DebugLoc dl, SelectionDAG &DAG) const; 73 | 74 | private: 75 | }; 76 | } // end of namespace llvm 77 | 78 | #endif // SAMPLE_ISELLOWERING_H 79 | -------------------------------------------------------------------------------- /SampleInstrInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleInstrInfo.cpp - Sample Instruction Information ------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the Sample implementation of the TargetInstrInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "SampleInstrInfo.h" 15 | #include "SampleTargetMachine.h" 16 | #include "SampleMachineFunction.h" 17 | #include "MCTargetDesc/SampleMCTargetDesc.h" 18 | #include "InstPrinter/SampleInstPrinter.h" 19 | #include "llvm/CodeGen/MachineInstrBuilder.h" 20 | #include "llvm/CodeGen/MachineRegisterInfo.h" 21 | #include "llvm/Support/ErrorHandling.h" 22 | #include "llvm/Support/TargetRegistry.h" 23 | #include "llvm/ADT/STLExtras.h" 24 | 25 | #define GET_INSTRINFO_CTOR 26 | #include "SampleGenInstrInfo.inc" 27 | 28 | using namespace llvm; 29 | 30 | SampleInstrInfo::SampleInstrInfo(SampleTargetMachine &tm) 31 | : SampleGenInstrInfo(Sample::ADJCALLSTACKDOWN, Sample::ADJCALLSTACKUP), 32 | TM(tm), 33 | RI(*this){} 34 | 35 | const SampleRegisterInfo &SampleInstrInfo::getRegisterInfo() const { 36 | return RI; 37 | } 38 | 39 | /// isLoadFromStackSlot - If the specified machine instruction is a direct 40 | /// load from a stack slot, return the virtual or physical register number of 41 | /// the destination along with the FrameIndex of the loaded stack slot. If 42 | /// not, return 0. This predicate must return 0 if the instruction has 43 | /// any side effects other than loading from the stack slot. 44 | unsigned SampleInstrInfo:: 45 | isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const { 46 | unsigned Opc = MI->getOpcode(); 47 | 48 | if (Opc == Sample::LOAD && // Load命令 49 | MI->getOperand(1).isFI() && // スタックスロット 50 | MI->getOperand(2).isImm() && // 即値が0 51 | MI->getOperand(2).getImm() == 0) { 52 | FrameIndex = MI->getOperand(1).getIndex(); 53 | return MI->getOperand(0).getReg(); 54 | } 55 | return 0; 56 | } 57 | 58 | /// isStoreToStackSlot - If the specified machine instruction is a direct 59 | /// store to a stack slot, return the virtual or physical register number of 60 | /// the source reg along with the FrameIndex of the loaded stack slot. If 61 | /// not, return 0. This predicate must return 0 if the instruction has 62 | /// any side effects other than storing to the stack slot. 63 | unsigned SampleInstrInfo:: 64 | isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const { 65 | unsigned Opc = MI->getOpcode(); 66 | 67 | if (Opc == Sample::STORE && // Store命令 68 | MI->getOperand(1).isFI() && // スタックスロット 69 | MI->getOperand(2).isImm() && // 即値が0 70 | MI->getOperand(2).getImm() == 0) { 71 | FrameIndex = MI->getOperand(1).getIndex(); 72 | return MI->getOperand(0).getReg(); 73 | } 74 | return 0; 75 | } 76 | 77 | void SampleInstrInfo:: 78 | copyPhysReg(MachineBasicBlock &MBB, 79 | MachineBasicBlock::iterator I, DebugLoc DL, 80 | unsigned DestReg, unsigned SrcReg, 81 | bool KillSrc) const { 82 | unsigned Opc = 0, ZeroReg = 0; 83 | Opc = Sample::ADD, ZeroReg = Sample::ZERO; 84 | 85 | MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 86 | 87 | if (DestReg) 88 | MIB.addReg(DestReg, RegState::Define); 89 | 90 | if (ZeroReg) 91 | MIB.addReg(ZeroReg); 92 | 93 | if (SrcReg) 94 | MIB.addReg(SrcReg, getKillRegState(KillSrc)); 95 | } 96 | 97 | void SampleInstrInfo:: 98 | storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 99 | unsigned SrcReg, bool isKill, int FI, 100 | const TargetRegisterClass *RC, 101 | const TargetRegisterInfo *TRI) const { 102 | DEBUG(dbgs() << ">> SampleInstrInfo::storeRegToStackSlot <<\n"); 103 | 104 | DebugLoc DL; 105 | if (I != MBB.end()) DL = I->getDebugLoc(); 106 | MachineFunction &MF = *MBB.getParent(); 107 | MachineFrameInfo &MFI = *MF.getFrameInfo(); 108 | 109 | MachineMemOperand *MMO = 110 | MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 111 | MachineMemOperand::MOStore, 112 | MFI.getObjectSize(FI), 113 | MFI.getObjectAlignment(FI)); 114 | 115 | BuildMI(MBB, I, DL, get(Sample::STORE)) 116 | .addReg(SrcReg, getKillRegState(isKill)) 117 | .addFrameIndex(FI).addImm(0).addMemOperand(MMO); 118 | } 119 | 120 | void SampleInstrInfo:: 121 | loadRegFromStackSlot(MachineBasicBlock &MBB, 122 | MachineBasicBlock::iterator MI, 123 | unsigned DestReg, int FI, 124 | const TargetRegisterClass *RC, 125 | const TargetRegisterInfo *TRI) const 126 | { 127 | DEBUG(dbgs() << ">> SampleInstrInfo::loadRegFromStackSlot <<\n"); 128 | 129 | DebugLoc DL; 130 | if (MI != MBB.end()) DL = MI->getDebugLoc(); 131 | MachineFunction &MF = *MBB.getParent(); 132 | MachineFrameInfo &MFI = *MF.getFrameInfo(); 133 | 134 | MachineMemOperand *MMO = 135 | MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI), 136 | MachineMemOperand::MOLoad, 137 | MFI.getObjectSize(FI), 138 | MFI.getObjectAlignment(FI)); 139 | 140 | BuildMI(MBB, MI, DL, get(Sample::LOAD)) 141 | .addReg(DestReg).addFrameIndex(FI).addImm(0).addMemOperand(MMO); 142 | } 143 | 144 | //===----------------------------------------------------------------------===// 145 | // Branch Analysis 146 | //===----------------------------------------------------------------------===// 147 | 148 | bool SampleInstrInfo:: 149 | AnalyzeBranch(MachineBasicBlock &MBB, 150 | MachineBasicBlock *&TBB, 151 | MachineBasicBlock *&FBB, 152 | SmallVectorImpl &Cond, 153 | bool AllowModify) const 154 | { 155 | // 未実装の場合はtrueを返す 156 | return true; 157 | } 158 | 159 | unsigned SampleInstrInfo:: 160 | InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 161 | MachineBasicBlock *FBB, 162 | const SmallVectorImpl &Cond, 163 | DebugLoc DL) const { 164 | llvm_unreachable("Target doesn't implement SampleInstrInfo::InsertBranch!"); 165 | } 166 | 167 | unsigned SampleInstrInfo:: 168 | RemoveBranch(MachineBasicBlock &MBB) const 169 | { 170 | llvm_unreachable("Target doesn't implement SampleInstrInfo::RemoveBranch"); 171 | } 172 | -------------------------------------------------------------------------------- /SampleInstrInfo.h: -------------------------------------------------------------------------------- 1 | //===-- SampleInstrInfo.h - Sample Instruction Information ----------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the Sample implementation of the TargetInstrInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLE_INSTRUCTIONINFO_H 15 | #define SAMPLE_INSTRUCTIONINFO_H 16 | 17 | #include "Sample.h" 18 | #include "SampleRegisterInfo.h" 19 | #include "llvm/Support/ErrorHandling.h" 20 | #include "llvm/Target/TargetInstrInfo.h" 21 | 22 | #define GET_INSTRINFO_HEADER 23 | #include "SampleGenInstrInfo.inc" 24 | 25 | namespace llvm { 26 | 27 | namespace Sample { 28 | /// GetOppositeBranchOpc - Return the inverse of the specified 29 | /// opcode, e.g. turning BEQ to BNE. 30 | unsigned GetOppositeBranchOpc(unsigned Opc); 31 | } 32 | 33 | class SampleInstrInfo : public SampleGenInstrInfo { 34 | SampleTargetMachine &TM; 35 | const SampleRegisterInfo RI; 36 | public: 37 | explicit SampleInstrInfo(SampleTargetMachine &TM); 38 | 39 | /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As 40 | /// such, whenever a client has an instance of instruction info, it should 41 | /// always be able to get register info as well (through this method). 42 | /// 43 | virtual const SampleRegisterInfo &getRegisterInfo() const; 44 | 45 | /// isLoadFromStackSlot - If the specified machine instruction is a direct 46 | /// load from a stack slot, return the virtual or physical register number of 47 | /// the destination along with the FrameIndex of the loaded stack slot. If 48 | /// not, return 0. This predicate must return 0 if the instruction has 49 | /// any side effects other than loading from the stack slot. 50 | virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 51 | int &FrameIndex) const; 52 | 53 | /// isStoreToStackSlot - If the specified machine instruction is a direct 54 | /// store to a stack slot, return the virtual or physical register number of 55 | /// the source reg along with the FrameIndex of the loaded stack slot. If 56 | /// not, return 0. This predicate must return 0 if the instruction has 57 | /// any side effects other than storing to the stack slot. 58 | virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 59 | int &FrameIndex) const; 60 | 61 | virtual void copyPhysReg(MachineBasicBlock &MBB, 62 | MachineBasicBlock::iterator MI, DebugLoc DL, 63 | unsigned DestReg, unsigned SrcReg, 64 | bool KillSrc) const; 65 | virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 66 | MachineBasicBlock::iterator MBBI, 67 | unsigned SrcReg, bool isKill, int FrameIndex, 68 | const TargetRegisterClass *RC, 69 | const TargetRegisterInfo *TRI) const; 70 | 71 | virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 72 | MachineBasicBlock::iterator MBBI, 73 | unsigned DestReg, int FrameIndex, 74 | const TargetRegisterClass *RC, 75 | const TargetRegisterInfo *TRI) const; 76 | 77 | /// Branch Analysis 78 | virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 79 | MachineBasicBlock *&FBB, 80 | SmallVectorImpl &Cond, 81 | bool AllowModify) const; 82 | 83 | virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 84 | 85 | virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 86 | MachineBasicBlock *FBB, 87 | const SmallVectorImpl &Cond, 88 | DebugLoc DL) const; 89 | }; 90 | 91 | } 92 | 93 | #endif 94 | -------------------------------------------------------------------------------- /SampleMCInstLower.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleMCInstLower.cpp - Convert Sample MachineInstr to an MCInst --===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains code to lower Sample MachineInstrs to their corresponding 11 | // MCInst records. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | 15 | #include "SampleMCInstLower.h" 16 | #include "llvm/CodeGen/AsmPrinter.h" 17 | #include "llvm/CodeGen/MachineBasicBlock.h" 18 | #include "llvm/CodeGen/MachineInstr.h" 19 | #include "llvm/CodeGen/MachineOperand.h" 20 | #include "llvm/MC/MCAsmInfo.h" 21 | #include "llvm/MC/MCContext.h" 22 | #include "llvm/MC/MCExpr.h" 23 | #include "llvm/MC/MCInst.h" 24 | #include "llvm/Target/Mangler.h" 25 | #include "llvm/Support/raw_ostream.h" 26 | #include "llvm/Support/ErrorHandling.h" 27 | #include "llvm/ADT/SmallString.h" 28 | #include "llvm/MC/MCSymbol.h" 29 | #include "llvm/Support/Debug.h" 30 | 31 | using namespace llvm; 32 | 33 | MCOperand SampleMCInstLower:: 34 | LowerSymbolOperand(const MachineOperand &MO, 35 | MachineOperandType MOTy) const { 36 | DEBUG(dbgs() << ">>> LowerSymbolOperand <<<\n"); 37 | 38 | switch(MO.getTargetFlags()) { 39 | default: llvm_unreachable("Invalid target flag!"); 40 | case 0: break; 41 | } 42 | 43 | const MCSymbol *Symbol; 44 | unsigned Offset = 0; 45 | switch (MOTy) { 46 | case MachineOperand::MO_MachineBasicBlock: 47 | Symbol = MO.getMBB()->getSymbol(); 48 | break; 49 | case MachineOperand::MO_GlobalAddress: 50 | Symbol = Mang.getSymbol(MO.getGlobal()); 51 | Offset = MO.getOffset(); 52 | break; 53 | case MachineOperand::MO_BlockAddress: 54 | Symbol = Printer.GetBlockAddressSymbol(MO.getBlockAddress()); 55 | break; 56 | case MachineOperand::MO_ExternalSymbol: 57 | Symbol = Printer.GetExternalSymbolSymbol(MO.getSymbolName()); 58 | break; 59 | case MachineOperand::MO_JumpTableIndex: 60 | Symbol = Printer.GetJTISymbol(MO.getIndex()); 61 | break; 62 | case MachineOperand::MO_ConstantPoolIndex: 63 | Symbol = Printer.GetCPISymbol(MO.getIndex()); 64 | Offset = MO.getOffset(); 65 | break; 66 | default: 67 | llvm_unreachable(""); 68 | } 69 | 70 | const MCExpr *Expr = MCSymbolRefExpr::Create(Symbol, Ctx); 71 | 72 | if (Offset) { 73 | const MCConstantExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx); 74 | Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx); 75 | } 76 | 77 | return MCOperand::CreateExpr(Expr); 78 | } 79 | 80 | MCOperand SampleMCInstLower:: 81 | LowerOperand(const MachineOperand& MO) const { 82 | DEBUG(dbgs() 83 | << ">>> LowerOperand:" << MO 84 | << " type:" << MO.getType() << "\n"); 85 | 86 | MachineOperandType MOTy = MO.getType(); 87 | switch (MOTy) { 88 | case MachineOperand::MO_Register: 89 | // Ignore all implicit register operands. 90 | if (MO.isImplicit()) break; 91 | return MCOperand::CreateReg(MO.getReg()); 92 | case MachineOperand::MO_Immediate: 93 | return MCOperand::CreateImm(MO.getImm()); 94 | case MachineOperand::MO_MachineBasicBlock: 95 | case MachineOperand::MO_GlobalAddress: 96 | case MachineOperand::MO_ExternalSymbol: 97 | case MachineOperand::MO_JumpTableIndex: 98 | case MachineOperand::MO_ConstantPoolIndex: 99 | case MachineOperand::MO_BlockAddress: 100 | return LowerSymbolOperand(MO, MOTy); 101 | case MachineOperand::MO_RegisterMask: 102 | break; 103 | default: 104 | llvm_unreachable("unknown operand type"); 105 | } 106 | 107 | return MCOperand(); 108 | } 109 | 110 | void SampleMCInstLower:: 111 | Lower(const MachineInstr *MI, MCInst &OutMI) const { 112 | DEBUG(dbgs() << ">> SampleMCInstLower::Lower <<\n"); 113 | OutMI.setOpcode(MI->getOpcode()); 114 | 115 | for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 116 | const MachineOperand &MO = MI->getOperand(i); 117 | MCOperand MCOp = LowerOperand(MO); 118 | 119 | if (MCOp.isValid()) 120 | OutMI.addOperand(MCOp); 121 | } 122 | } 123 | -------------------------------------------------------------------------------- /SampleMCInstLower.h: -------------------------------------------------------------------------------- 1 | //===-- SampleMCInstLower.h - Lower MachineInstr to MCInst ------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #ifndef SAMPLE_MCINSTLOWER_H 11 | #define SAMPLE_MCINSTLOWER_H 12 | 13 | #include "llvm/Support/Compiler.h" 14 | #include "llvm/CodeGen/MachineOperand.h" 15 | 16 | namespace llvm { 17 | class AsmPrinter; 18 | class MCContext; 19 | class MCInst; 20 | class MCOperand; 21 | class MCSymbol; 22 | class MachineInstr; 23 | class MachineModuleInfoMachO; 24 | class MachineOperand; 25 | class Mangler; 26 | 27 | /// SampleMCInstLower - This class is used to lower an MachineInstr 28 | /// into an MCInst. 29 | class LLVM_LIBRARY_VISIBILITY SampleMCInstLower { 30 | typedef MachineOperand::MachineOperandType MachineOperandType; 31 | MCContext &Ctx; 32 | Mangler &Mang; 33 | const AsmPrinter &Printer; 34 | 35 | public: 36 | SampleMCInstLower(MCContext &ctx, Mangler &mang, AsmPrinter &printer) 37 | : Ctx(ctx), Mang(mang), Printer(printer) {} 38 | void Lower(const MachineInstr *MI, MCInst &OutMI) const; 39 | 40 | private: 41 | MCOperand LowerOperand(const MachineOperand& MO) const; 42 | MCOperand LowerSymbolOperand(const MachineOperand &MO, 43 | MachineOperandType MOTy) const; 44 | }; 45 | } // end of namespace llvm 46 | 47 | #endif 48 | -------------------------------------------------------------------------------- /SampleMachineFunction.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleMachineFunctionInfo.cpp - Private data used for Sample ----------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #include "SampleMachineFunction.h" 11 | #include "SampleInstrInfo.h" 12 | #include "MCTargetDesc/SampleMCTargetDesc.h" 13 | #include "llvm/Function.h" 14 | #include "llvm/CodeGen/MachineInstrBuilder.h" 15 | #include "llvm/CodeGen/MachineRegisterInfo.h" 16 | #include "llvm/Support/CommandLine.h" 17 | 18 | using namespace llvm; 19 | 20 | void SampleMachineFunctionInfo::anchor() { } 21 | -------------------------------------------------------------------------------- /SampleMachineFunction.h: -------------------------------------------------------------------------------- 1 | //===-- SampleMachineFunctionInfo.h - Private data used for Sample ----*- C++ -*-=// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file declares the Sample specific subclass of MachineFunctionInfo. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLE_MACHINE_FUNCTION_INFO_H 15 | #define SAMPLE_MACHINE_FUNCTION_INFO_H 16 | 17 | #include "llvm/CodeGen/MachineFunction.h" 18 | #include "llvm/CodeGen/MachineFrameInfo.h" 19 | #include 20 | 21 | namespace llvm { 22 | 23 | /// SampleFunctionInfo - This class is derived from MachineFunction private 24 | /// Sample target-specific information for each MachineFunction. 25 | class SampleMachineFunctionInfo : public MachineFunctionInfo { 26 | virtual void anchor(); 27 | 28 | public: 29 | SampleMachineFunctionInfo(MachineFunction& MF) {} 30 | }; 31 | } // end of namespace llvm 32 | 33 | #endif // SAMPLE_MACHINE_FUNCTION_INFO_H 34 | -------------------------------------------------------------------------------- /SampleRegisterInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleRegisterInfo.cpp - Sample Register Information -== --------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the Sample implementation of the TargetRegisterInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #define DEBUG_TYPE "sample-reg-info" 15 | 16 | #include "SampleRegisterInfo.h" 17 | #include "Sample.h" 18 | #include "llvm/Constants.h" 19 | #include "llvm/Type.h" 20 | #include "llvm/Function.h" 21 | #include "llvm/CodeGen/ValueTypes.h" 22 | #include "llvm/CodeGen/MachineInstrBuilder.h" 23 | #include "llvm/CodeGen/MachineFunction.h" 24 | #include "llvm/CodeGen/MachineFrameInfo.h" 25 | #include "llvm/Target/TargetFrameLowering.h" 26 | #include "llvm/Target/TargetMachine.h" 27 | #include "llvm/Target/TargetOptions.h" 28 | #include "llvm/Target/TargetInstrInfo.h" 29 | #include "llvm/Support/CommandLine.h" 30 | #include "llvm/Support/Debug.h" 31 | #include "llvm/Support/ErrorHandling.h" 32 | #include "llvm/Support/raw_ostream.h" 33 | #include "llvm/ADT/BitVector.h" 34 | #include "llvm/ADT/STLExtras.h" 35 | #include "llvm/DebugInfo.h" 36 | 37 | #include "MCTargetDesc/SampleMCTargetDesc.h" 38 | 39 | #define GET_REGINFO_TARGET_DESC 40 | #include "SampleGenRegisterInfo.inc" 41 | 42 | using namespace llvm; 43 | 44 | SampleRegisterInfo:: 45 | SampleRegisterInfo(const TargetInstrInfo &tii) 46 | : SampleGenRegisterInfo(Sample::RA), TII(tii) { } 47 | 48 | //===----------------------------------------------------------------------===// 49 | // Callee Saved Registers methods 50 | //===----------------------------------------------------------------------===// 51 | 52 | // 呼び出し先待避レジスタ 53 | const uint16_t* SampleRegisterInfo:: 54 | getCalleeSavedRegs(const MachineFunction *MF) const { 55 | return CSR_SingleFloatOnly_SaveList; 56 | } 57 | 58 | // 呼び出し元待避レジスタ 59 | const uint32_t* SampleRegisterInfo:: 60 | getCallPreservedMask(CallingConv::ID) const { 61 | return CSR_SingleFloatOnly_RegMask; 62 | } 63 | 64 | BitVector SampleRegisterInfo:: 65 | getReservedRegs(const MachineFunction &MF) const { 66 | static const uint16_t ReservedCPURegs[] = { 67 | Sample::ZERO, Sample::SP, Sample::RA, Sample::V0, 68 | }; 69 | 70 | BitVector Reserved(getNumRegs()); 71 | typedef TargetRegisterClass::iterator RegIter; 72 | 73 | for (unsigned I = 0; I < array_lengthof(ReservedCPURegs); ++I) 74 | Reserved.set(ReservedCPURegs[I]); 75 | 76 | return Reserved; 77 | } 78 | 79 | // ADJCALLSTACKDOWNとADJCALLSTACKUPを単純に削除する 80 | void SampleRegisterInfo:: 81 | eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 82 | MachineBasicBlock::iterator I) const { 83 | DEBUG(dbgs() << ">> SampleRegisterInfo::eliminateCallFramePseudoInstr <<\n";); 84 | MBB.erase(I); 85 | } 86 | 87 | // FrameIndexをスタックポインタに置き換える 88 | void SampleRegisterInfo:: 89 | eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, 90 | RegScavenger *RS) const { 91 | DEBUG(dbgs() << ">> SampleRegisterInfo::eliminateFrameIndex <<\n";); 92 | 93 | MachineInstr &MI = *II; 94 | const MachineFunction &MF = *MI.getParent()->getParent(); 95 | 96 | unsigned opIndex; 97 | for (opIndex = 0; opIndex < MI.getNumOperands(); opIndex++) { 98 | if (MI.getOperand(opIndex).isFI()) break; 99 | } 100 | assert(opIndex < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); 101 | 102 | int FrameIndex = MI.getOperand(opIndex).getIndex(); 103 | uint64_t stackSize = MF.getFrameInfo()->getStackSize(); 104 | int64_t spOffset = MF.getFrameInfo()->getObjectOffset(FrameIndex); 105 | int64_t Offset = spOffset + stackSize + MI.getOperand(opIndex+1).getImm(); 106 | unsigned FrameReg = Sample::SP; 107 | 108 | DEBUG(errs() 109 | << "\nFunction : " << MF.getFunction()->getName() << "\n" 110 | << "<--------->\n" << MI 111 | << "FrameIndex : " << FrameIndex << "\n" 112 | << "spOffset : " << spOffset << "\n" 113 | << "stackSize : " << stackSize << "\n" 114 | << "Offset : " << Offset << "\n" << "<--------->\n"); 115 | 116 | DEBUG(errs() << "Before:" << MI); 117 | MI.getOperand(opIndex).ChangeToRegister(FrameReg, false); 118 | MI.getOperand(opIndex+1).ChangeToImmediate(Offset); 119 | DEBUG(errs() << "After:" << MI); 120 | } 121 | 122 | unsigned SampleRegisterInfo:: 123 | getFrameRegister(const MachineFunction &MF) const { 124 | return Sample::SP; 125 | } 126 | -------------------------------------------------------------------------------- /SampleRegisterInfo.h: -------------------------------------------------------------------------------- 1 | //===-- SampleRegisterInfo.h - Sample Register Information Impl -----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the Sample implementation of the TargetRegisterInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLEREGISTERINFO_H 15 | #define SAMPLEREGISTERINFO_H 16 | 17 | #include "Sample.h" 18 | #include "llvm/Target/TargetRegisterInfo.h" 19 | 20 | #define GET_REGINFO_HEADER 21 | #include "SampleGenRegisterInfo.inc" 22 | 23 | namespace llvm { 24 | class SampleSubtarget; 25 | class TargetInstrInfo; 26 | class Type; 27 | 28 | struct SampleRegisterInfo : public SampleGenRegisterInfo { 29 | const TargetInstrInfo &TII; 30 | 31 | SampleRegisterInfo(const TargetInstrInfo &tii); 32 | 33 | /// Code Generation virtual methods... 34 | const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const /*override*/; 35 | const uint32_t *getCallPreservedMask(CallingConv::ID) const /*override*/; 36 | 37 | BitVector getReservedRegs(const MachineFunction &MF) const /*override*/; 38 | 39 | void eliminateCallFramePseudoInstr(MachineFunction &MF, 40 | MachineBasicBlock &MBB, 41 | MachineBasicBlock::iterator I) const /*override*/; 42 | 43 | /// Stack Frame Processing Methods 44 | void eliminateFrameIndex(MachineBasicBlock::iterator II, 45 | int SPAdj, RegScavenger *RS = NULL) const; 46 | 47 | /// Debug information queries. 48 | unsigned getFrameRegister(const MachineFunction &MF) const /*override*/; 49 | }; 50 | 51 | } // end namespace llvm 52 | 53 | 54 | #endif 55 | 56 | -------------------------------------------------------------------------------- /SampleSelectionDAGInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleSelectionDAGInfo.cpp - Sample SelectionDAG Info -----------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements the SampleSelectionDAGInfo class. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #define DEBUG_TYPE "sample-selectiondag-info" 15 | #include "SampleTargetMachine.h" 16 | using namespace llvm; 17 | 18 | SampleSelectionDAGInfo::SampleSelectionDAGInfo(const SampleTargetMachine &TM) 19 | : TargetSelectionDAGInfo(TM) {} 20 | 21 | SampleSelectionDAGInfo::~SampleSelectionDAGInfo() {} 22 | -------------------------------------------------------------------------------- /SampleSelectionDAGInfo.h: -------------------------------------------------------------------------------- 1 | //===-- SampleSelectionDAGInfo.h - Sample SelectionDAG Info ---------*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file defines the Sample subclass for TargetSelectionDAGInfo. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef SAMPLE_SELECTIONDAGINFO_H 15 | #define SAMPLE_SELECTIONDAGINFO_H 16 | 17 | #include "llvm/Target/TargetSelectionDAGInfo.h" 18 | 19 | namespace llvm { 20 | 21 | class SampleTargetMachine; 22 | 23 | class SampleSelectionDAGInfo : public TargetSelectionDAGInfo { 24 | public: 25 | explicit SampleSelectionDAGInfo(const SampleTargetMachine &TM); 26 | ~SampleSelectionDAGInfo(); 27 | }; 28 | } // end of namespace llvm 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /SampleSubtarget.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleSubtarget.cpp - Sample Subtarget Information ----------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file implements the Sample specific subclass of TargetSubtargetInfo. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "SampleSubtarget.h" 15 | #include "Sample.h" 16 | #include "llvm/Support/TargetRegistry.h" 17 | 18 | #define GET_SUBTARGETINFO_TARGET_DESC 19 | #define GET_SUBTARGETINFO_CTOR 20 | #include "SampleGenSubtargetInfo.inc" 21 | 22 | using namespace llvm; 23 | 24 | SampleSubtarget::SampleSubtarget(const std::string &TT, 25 | const std::string &CPU, 26 | const std::string &FS) 27 | : SampleGenSubtargetInfo(TT, CPU, FS) { 28 | std::string CPUName = "generic"; 29 | 30 | // Parse features string. 31 | ParseSubtargetFeatures(CPUName, FS); 32 | } 33 | -------------------------------------------------------------------------------- /SampleSubtarget.h: -------------------------------------------------------------------------------- 1 | //===-- SampleSubtarget.h - Define Subtarget for the Sample ----*- C++ -*--===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file declares the Sample specific subclass of TargetSubtargetInfo. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #ifndef LLVM_TARGET_SAMPLE_SUBTARGET_H 15 | #define LLVM_TARGET_SAMPLE_SUBTARGET_H 16 | 17 | #include "llvm/Target/TargetSubtargetInfo.h" 18 | #include 19 | 20 | #define GET_SUBTARGETINFO_HEADER 21 | #include "SampleGenSubtargetInfo.inc" 22 | 23 | namespace llvm { 24 | class StringRef; 25 | 26 | class SampleSubtarget : public SampleGenSubtargetInfo { 27 | virtual void anchor() {}; 28 | bool ExtendedInsts; 29 | public: 30 | /// This constructor initializes the data members to match that 31 | /// of the specified triple. 32 | SampleSubtarget(const std::string &TT, const std::string &CPU, 33 | const std::string &FS); 34 | 35 | // Autogenerated by tblgen. 36 | /// ParseSubtargetFeatures - Parses features string setting specified 37 | /// subtarget options. Definition of function is auto generated by tblgen. 38 | void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 39 | }; 40 | } // End llvm namespace 41 | 42 | #endif // LLVM_TARGET_SAMPLE_SUBTARGET_H 43 | -------------------------------------------------------------------------------- /SampleTargetMachine.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleTargetMachine.cpp - Define TargetMachine for Sample -------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // Implements the info about Sample target spec. 11 | // 12 | //===----------------------------------------------------------------------===// 13 | 14 | #include "SampleTargetMachine.h" 15 | #include "Sample.h" 16 | #include "llvm/PassManager.h" 17 | #include "llvm/CodeGen/Passes.h" 18 | #include "llvm/MC/MCAsmInfo.h" 19 | #include "llvm/Support/TargetRegistry.h" 20 | using namespace llvm; 21 | 22 | extern "C" void LLVMInitializeSampleTarget() { 23 | // Register the target. 24 | RegisterTargetMachine X(TheSampleTarget); 25 | } 26 | 27 | SampleTargetMachine:: 28 | SampleTargetMachine(const Target &T, StringRef Triple, 29 | StringRef CPU, StringRef FS, const TargetOptions &Options, 30 | Reloc::Model RM, CodeModel::Model CM, 31 | CodeGenOpt::Level OL) 32 | : LLVMTargetMachine(T, Triple, CPU, FS, Options, RM, CM, OL), 33 | DL("e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32"), 34 | Subtarget(Triple, CPU, FS), 35 | InstrInfo(*this), 36 | FrameLowering(Subtarget), 37 | TLInfo(*this), TSInfo(*this) {} 38 | 39 | namespace { 40 | /// Sample Code Generator Pass Configuration Options. 41 | class SamplePassConfig : public TargetPassConfig { 42 | public: 43 | SamplePassConfig(SampleTargetMachine *TM, PassManagerBase &PM) 44 | : TargetPassConfig(TM, PM) {} 45 | 46 | SampleTargetMachine &getSampleTargetMachine() const { 47 | return getTM(); 48 | } 49 | 50 | virtual bool addInstSelector(); 51 | }; 52 | } // namespace 53 | 54 | TargetPassConfig *SampleTargetMachine::createPassConfig(PassManagerBase &PM) { 55 | return new SamplePassConfig(this, PM); 56 | } 57 | 58 | bool SamplePassConfig::addInstSelector() { 59 | // Install an instruction selector. 60 | addPass(createSampleISelDag(getSampleTargetMachine())); 61 | return false; 62 | } 63 | -------------------------------------------------------------------------------- /SampleTargetMachine.h: -------------------------------------------------------------------------------- 1 | //===-- Sample.h - Top-level interface for Sample representation ----*- C++ -*-===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | // 10 | // This file contains the entry points for global functions defined in 11 | // the LLVM Sample back-end. 12 | // 13 | //===----------------------------------------------------------------------===// 14 | #ifndef SAMPLE_TARGETMACHINE_H 15 | #define SAMPLE_TARGETMACHINE_H 16 | 17 | #include "SampleFrameLowering.h" 18 | #include "SampleInstrInfo.h" 19 | #include "SampleISelLowering.h" 20 | #include "SampleSelectionDAGInfo.h" 21 | #include "SampleRegisterInfo.h" 22 | #include "SampleSubtarget.h" 23 | #include "llvm/DataLayout.h" 24 | #include "llvm/Target/TargetMachine.h" 25 | #include "llvm/Target/TargetFrameLowering.h" 26 | #include "llvm/Support/Debug.h" 27 | 28 | namespace llvm { 29 | 30 | class Module; 31 | 32 | class SampleTargetMachine : public LLVMTargetMachine { 33 | const DataLayout DL; 34 | SampleSubtarget Subtarget; 35 | SampleInstrInfo InstrInfo; 36 | SampleFrameLowering FrameLowering; 37 | SampleTargetLowering TLInfo; 38 | SampleSelectionDAGInfo TSInfo; 39 | 40 | public: 41 | SampleTargetMachine(const Target &T, StringRef TT, 42 | StringRef CPU, StringRef FS, const TargetOptions &Options, 43 | Reloc::Model RM, CodeModel::Model CM, 44 | CodeGenOpt::Level OL); 45 | 46 | virtual const SampleInstrInfo *getInstrInfo() const { 47 | return &InstrInfo; 48 | } 49 | virtual const SampleSubtarget *getSubtargetImpl() const { 50 | return &Subtarget; 51 | } 52 | virtual const SampleRegisterInfo *getRegisterInfo() const { 53 | return &InstrInfo.getRegisterInfo(); 54 | } 55 | virtual const DataLayout *getDataLayout() const { 56 | return &DL; 57 | } 58 | virtual const SampleTargetLowering *getTargetLowering() const { 59 | return &TLInfo; 60 | } 61 | virtual const SampleFrameLowering *getFrameLowering() const{ 62 | return &FrameLowering; 63 | } 64 | virtual const SampleSelectionDAGInfo* getSelectionDAGInfo() const { 65 | return &TSInfo; 66 | } 67 | 68 | // Pass Pipeline Configuration 69 | virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); 70 | }; 71 | } // end namespace llvm 72 | 73 | #endif 74 | -------------------------------------------------------------------------------- /TargetInfo/LLVMBuild.txt: -------------------------------------------------------------------------------- 1 | ;===- ./lib/Target/Sample/TargetInfo/LLVMBuild.txt -------------*- Conf -*--===; 2 | ; 3 | ; The LLVM Compiler Infrastructure 4 | ; 5 | ; This file is distributed under the University of Illinois Open Source 6 | ; License. See LICENSE.TXT for details. 7 | ; 8 | ;===------------------------------------------------------------------------===; 9 | ; 10 | ; This is an LLVMBuild description file for the components in this subdirectory. 11 | ; 12 | ; For more information on the LLVMBuild system, please see: 13 | ; 14 | ; http://llvm.org/docs/LLVMBuild.html 15 | ; 16 | ;===------------------------------------------------------------------------===; 17 | 18 | [component_0] 19 | type = Library 20 | name = SampleInfo 21 | parent = Sample 22 | required_libraries = MC Support Target 23 | add_to_library_groups = Sample 24 | -------------------------------------------------------------------------------- /TargetInfo/Makefile: -------------------------------------------------------------------------------- 1 | ##===- lib/Target/Sample/TargetInfo/Makefile ---------------*- Makefile -*-===## 2 | # 3 | # The LLVM Compiler Infrastructure 4 | # 5 | # This file is distributed under the University of Illinois Open Source 6 | # License. See LICENSE.TXT for details. 7 | # 8 | ##===----------------------------------------------------------------------===## 9 | LEVEL = ../../../.. 10 | LIBRARYNAME = LLVMSampleInfo 11 | 12 | # Hack: we need to include 'main' target directory to grab private headers 13 | CPPFLAGS = -I$(PROJ_OBJ_DIR)/.. -I$(PROJ_SRC_DIR)/.. 14 | 15 | include $(LEVEL)/Makefile.common 16 | -------------------------------------------------------------------------------- /TargetInfo/SampleTargetInfo.cpp: -------------------------------------------------------------------------------- 1 | //===-- SampleTargetInfo.cpp - Sample Target Implementation -------------------===// 2 | // 3 | // The LLVM Compiler Infrastructure 4 | // 5 | // This file is distributed under the University of Illinois Open Source 6 | // License. See LICENSE.TXT for details. 7 | // 8 | //===----------------------------------------------------------------------===// 9 | 10 | #include "Sample.h" 11 | #include "llvm/Module.h" 12 | #include "llvm/Support/TargetRegistry.h" 13 | using namespace llvm; 14 | 15 | Target llvm::TheSampleTarget; 16 | 17 | extern "C" void LLVMInitializeSampleTargetInfo() { 18 | DEBUG(dbgs() << ">> InitSampleTargetInfo <<\n"); 19 | RegisterTarget 20 | X(TheSampleTarget, "sample", "Sample"); 21 | } 22 | -------------------------------------------------------------------------------- /config.patch: -------------------------------------------------------------------------------- 1 | diff -Nur llvm-3.2.src/autoconf/configure.ac llvm-3.2/autoconf/configure.ac 2 | --- llvm-3.2.src/autoconf/configure.ac 2012-11-22 01:13:35.000000000 +0900 3 | +++ llvm-3.2/autoconf/configure.ac 2013-03-20 21:18:46.402839000 +0900 4 | @@ -370,6 +370,7 @@ 5 | hexagon-*) llvm_cv_target_arch="Hexagon" ;; 6 | mblaze-*) llvm_cv_target_arch="MBlaze" ;; 7 | nvptx-*) llvm_cv_target_arch="NVPTX" ;; 8 | + sample-*) llvm_cv_target_arch="Sample" ;; 9 | *) llvm_cv_target_arch="Unknown" ;; 10 | esac]) 11 | 12 | @@ -723,6 +724,7 @@ 13 | hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;; 14 | mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; 15 | nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;; 16 | + sample) TARGETS_TO_BUILD="Sample $TARGETS_TO_BUILD" ;; 17 | host) case "$llvm_cv_target_arch" in 18 | x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 19 | x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 20 | diff -Nur llvm-3.2.src/configure llvm-3.2/configure 21 | --- llvm-3.2.src/configure 2012-11-22 01:13:35.000000000 +0900 22 | +++ llvm-3.2/configure 2013-03-20 21:18:46.402839000 +0900 23 | @@ -5419,7 +5419,7 @@ 24 | enableval=host 25 | fi 26 | case "$enableval" in 27 | - all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon" ;; 28 | + all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 CppBackend MBlaze NVPTX Hexagon Sample" ;; 29 | *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do 30 | case "$a_target" in 31 | x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 32 | @@ -5438,6 +5438,7 @@ 33 | hexagon) TARGETS_TO_BUILD="Hexagon $TARGETS_TO_BUILD" ;; 34 | mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; 35 | nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;; 36 | + sample) TARGETS_TO_BUILD="Sample $TARGETS_TO_BUILD" ;; 37 | host) case "$llvm_cv_target_arch" in 38 | x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 39 | x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 40 | diff -Nur llvm-3.2.src/include/llvm/ADT/Triple.h llvm-3.2/include/llvm/ADT/Triple.h 41 | --- llvm-3.2.src/include/llvm/ADT/Triple.h 2012-11-16 06:24:48.000000000 +0900 42 | +++ llvm-3.2/include/llvm/ADT/Triple.h 2013-03-20 21:18:46.402839000 +0900 43 | @@ -67,7 +67,8 @@ 44 | le32, // le32: generic little-endian 32-bit CPU (PNaCl / Emscripten) 45 | amdil, // amdil: amd IL 46 | spir, // SPIR: standard portable IR for OpenCL 32-bit version 47 | - spir64 // SPIR: standard portable IR for OpenCL 64-bit version 48 | + spir64, // SPIR: standard portable IR for OpenCL 64-bit version 49 | + sample // Sample: sample 50 | }; 51 | enum VendorType { 52 | UnknownVendor, 53 | diff -Nur llvm-3.2.src/lib/Support/Triple.cpp llvm-3.2/lib/Support/Triple.cpp 54 | --- llvm-3.2.src/lib/Support/Triple.cpp 2012-11-16 06:24:48.000000000 +0900 55 | +++ llvm-3.2/lib/Support/Triple.cpp 2013-03-20 21:18:46.402839000 +0900 56 | @@ -44,6 +44,7 @@ 57 | case amdil: return "amdil"; 58 | case spir: return "spir"; 59 | case spir64: return "spir64"; 60 | + case sample: return "sample"; 61 | } 62 | 63 | llvm_unreachable("Invalid ArchType!"); 64 | @@ -180,6 +181,7 @@ 65 | .Case("amdil", amdil) 66 | .Case("spir", spir) 67 | .Case("spir64", spir64) 68 | + .Case("sample", sample) 69 | .Default(UnknownArch); 70 | } 71 | 72 | @@ -242,6 +244,7 @@ 73 | .Case("amdil", Triple::amdil) 74 | .Case("spir", Triple::spir) 75 | .Case("spir64", Triple::spir64) 76 | + .Case("sample", Triple::sample) 77 | .Default(Triple::UnknownArch); 78 | } 79 | 80 | @@ -678,6 +681,7 @@ 81 | case llvm::Triple::x86: 82 | case llvm::Triple::xcore: 83 | case llvm::Triple::spir: 84 | + case llvm::Triple::sample: 85 | return 32; 86 | 87 | case llvm::Triple::mips64: 88 | @@ -729,6 +733,7 @@ 89 | case Triple::thumb: 90 | case Triple::x86: 91 | case Triple::xcore: 92 | + case Triple::sample: 93 | // Already 32-bit. 94 | break; 95 | 96 | @@ -758,6 +763,7 @@ 97 | case Triple::tce: 98 | case Triple::thumb: 99 | case Triple::xcore: 100 | + case Triple::sample: 101 | T.setArch(UnknownArch); 102 | break; 103 | 104 | diff -Nur llvm-3.2.src/lib/Target/LLVMBuild.txt llvm-3.2/lib/Target/LLVMBuild.txt 105 | --- llvm-3.2.src/lib/Target/LLVMBuild.txt 2012-07-17 03:19:46.000000000 +0900 106 | +++ llvm-3.2/lib/Target/LLVMBuild.txt 2013-03-20 21:18:46.402839000 +0900 107 | @@ -16,7 +16,7 @@ 108 | ;===------------------------------------------------------------------------===; 109 | 110 | [common] 111 | -subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC Sparc X86 XCore 112 | +subdirectories = ARM CellSPU CppBackend Hexagon MBlaze MSP430 NVPTX Mips PowerPC Sparc X86 XCore Sample 113 | 114 | ; This is a special group whose required libraries are extended (by llvm-build) 115 | ; with the best execution engine (the native JIT, if available, or the 116 | diff -Nur llvm-3.2.src/projects/sample/configure llvm-3.2/projects/sample/configure 117 | --- llvm-3.2.src/projects/sample/configure 2012-10-30 04:49:45.000000000 +0900 118 | +++ llvm-3.2/projects/sample/configure 2013-03-20 21:18:46.402839000 +0900 119 | @@ -5255,7 +5255,7 @@ 120 | enableval=host 121 | fi 122 | case "$enableval" in 123 | - all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 Hexagon CppBackend MBlaze NVPTX" ;; 124 | + all) TARGETS_TO_BUILD="X86 Sparc PowerPC ARM Mips CellSPU XCore MSP430 Hexagon CppBackend MBlaze NVPTX Sample" ;; 125 | *)for a_target in `echo $enableval|sed -e 's/,/ /g' ` ; do 126 | case "$a_target" in 127 | x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 128 | @@ -5271,6 +5271,7 @@ 129 | cpp) TARGETS_TO_BUILD="CppBackend $TARGETS_TO_BUILD" ;; 130 | mblaze) TARGETS_TO_BUILD="MBlaze $TARGETS_TO_BUILD" ;; 131 | nvptx) TARGETS_TO_BUILD="NVPTX $TARGETS_TO_BUILD" ;; 132 | + sample) TARGETS_TO_BUILD="Sample $TARGETS_TO_BUILD" ;; 133 | host) case "$llvm_cv_target_arch" in 134 | x86) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 135 | x86_64) TARGETS_TO_BUILD="X86 $TARGETS_TO_BUILD" ;; 136 | --------------------------------------------------------------------------------