├── .clang-format ├── Inc └── usblib.h ├── LICENSE ├── README.md ├── RTE └── Device │ └── STM32F103C8 │ ├── RTE_Device.h │ ├── startup_stm32f10x_md.s │ └── system_stm32f10x.c ├── RemoteSwitchHUB.inf ├── STM32F103-USB-CDC-CMSIS.uvoptx ├── STM32F103-USB-CDC-CMSIS.uvprojx └── Src ├── main.c └── usblib.c /.clang-format: -------------------------------------------------------------------------------- 1 | UseTab: Never 2 | IndentWidth: 4 3 | BreakBeforeBraces: Linux 4 | AllowShortIfStatementsOnASingleLine: false 5 | IndentCaseLabels: false 6 | ColumnLimit: 0 7 | AlignConsecutiveAssignments: true 8 | AlignConsecutiveDeclarations: true 9 | AllowShortLoopsOnASingleLine: true -------------------------------------------------------------------------------- /Inc/usblib.h: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the SaeWave RemoteSwitch (USB-CDC-CMSIS) 3 | * distribution (https://github.com/saewave/STM32F103-USB-CDC-CMSIS). 4 | * Copyright (c) 2017 Samoilov Alexey. 5 | * 6 | * This program is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation, version 3. 9 | * 10 | * This program is distributed in the hope that it will be useful, but 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #ifndef USBLIB_H 20 | #define USBLIB_H 21 | 22 | #include "stdint.h" 23 | 24 | #define EPCOUNT 4 25 | #define USB_BASE ((uint32_t)0x40005C00) 26 | #define USB_PBUFFER ((uint32_t)0x40006000) 27 | #define STRX 12 28 | #define STTX 4 29 | #define CTR_RX 0x8000 30 | #define CTR_TX 0x80 31 | #define CDC_CMD_PACKET_SIZE 8 /* Control Endpoint Packet size */ 32 | #define CDC_DATA_FS_CMD_PACKET_SIZE 16 /* Endpoint IN & OUT Packet size */ 33 | #define CDC_DATA_FS_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */ 34 | #define LANG_US (uint16_t)0x0409 35 | 36 | #define DEVICE_VENDOR_ID 0x25AE 37 | #define DEVICE_PRODUCT_ID 0x24AB 38 | #define STRING_DT 3 39 | 40 | /* EPxREG: EndPoint Registers Bit Definitions */ 41 | #define EP_CTR_RX 0x8000 /* Correct RX Transfer */ 42 | #define EP_DTOG_RX 0x4000 /* RX Data Toggle */ 43 | #define EP_STAT_RX 0x3000 /* RX Status */ 44 | #define EP_SETUP 0x0800 /* EndPoint Setup */ 45 | #define EP_TYPE 0x0600 /* EndPoint Type */ 46 | #define EP_KIND 0x0100 /* EndPoint Kind */ 47 | #define EP_CTR_TX 0x0080 /* Correct TX Transfer */ 48 | #define EP_DTOG_TX 0x0040 /* TX Data Toggle */ 49 | #define EP_STAT_TX 0x0030 /* TX Status */ 50 | #define EP_EA 0x000F /* EndPoint Address */ 51 | #define EP_MASK (EP_CTR_RX | EP_SETUP | EP_TYPE | EP_KIND | EP_CTR_TX | EP_EA) 52 | 53 | /* EP_STAT_TX: TX Status */ 54 | #define TX_DISABLE 0x0000 /* Disabled */ 55 | #define TX_STALL 0x0010 /* Stalled */ 56 | #define TX_NAK 0x0020 /* NAKed */ 57 | #define TX_VALID 0x0030 /* Valid */ 58 | 59 | /* EP_STAT_RX: RX Status */ 60 | #define RX_DISABLE 0x0000 /* Disabled */ 61 | #define RX_STALL 0x1000 /* Stalled */ 62 | #define RX_NAK 0x2000 /* NAKed */ 63 | #define RX_VALID 0x3000 /* Valid */ 64 | 65 | /* EP_TYPE: EndPoint Types */ 66 | #define EP_BULK 0x0000 /* BULK EndPoint */ 67 | #define EP_CONTROL 0x0200 /* CONTROL EndPoint */ 68 | #define EP_ISOCHRONOUS 0x0400 /* ISOCHRONOUS EndPoint */ 69 | #define EP_INTERRUPT 0x0600 /* INTERRUPT EndPoint */ 70 | 71 | /* bmRequestType.Type */ 72 | #define REQUEST_STANDARD 0 73 | #define REQUEST_CLASS 1 74 | #define REQUEST_VENDOR 2 75 | #define REQUEST_RESERVED 3 76 | 77 | /* USB Standard Request Codes */ 78 | #define USB_REQUEST_GET_STATUS 0 79 | #define USB_REQUEST_CLEAR_FEATURE 1 80 | #define USB_REQUEST_SET_FEATURE 3 81 | #define USB_REQUEST_SET_ADDRESS 5 82 | #define USB_REQUEST_GET_DESCRIPTOR 6 83 | #define USB_REQUEST_SET_DESCRIPTOR 7 84 | #define USB_REQUEST_GET_CONFIGURATION 8 85 | #define USB_REQUEST_SET_CONFIGURATION 9 86 | #define USB_REQUEST_GET_INTERFACE 10 87 | #define USB_REQUEST_SET_INTERFACE 11 88 | #define USB_REQUEST_SYNC_FRAME 12 89 | 90 | /* USB Descriptor Types */ 91 | #define USB_DEVICE_DESC_TYPE 1 92 | #define USB_CFG_DESC_TYPE 2 93 | #define USB_STR_DESC_TYPE 3 94 | #define USB_IFACE_DESC_TYPE 4 95 | #define USB_EP_DESC_TYPE 5 96 | #define USB_DEVICE_QR_DESC_TYPE 6 97 | #define USB_OSPEED_CFG_DESC_TYPE 7 98 | #define USB_IFACE_PWR_DESC_TYPE 8 99 | /* USB Device Classes */ 100 | #define USB_RESERVED 0x00 101 | #define USB_AUDIO 0x01 102 | #define USB_COMM 0x02 103 | #define USB_HID 0x03 104 | #define USB_MONITOR 0x04 105 | #define USB_PHYSIC 0x05 106 | #define USB_POWER 0x06 107 | #define USB_PRINTER 0x07 108 | #define USB_STORAGE 0x08 109 | #define USB_HUB 0x09 110 | #define USB_VENDOR_SPEC 0xFF 111 | /* Interface Class SubClass Codes */ 112 | #define USB_ACM_COMM 0x02 113 | 114 | #define CDC_DATA_IFACE 0x0A 115 | #define CS_INTERFACE 0x24 116 | #define CS_ENDPOINT 0x25 117 | 118 | /* CDC */ 119 | #define USB_CDC_CONFIG_DESC_SIZ 67 120 | #define CDC_CMD_EP 0x81 /* EP2 for CDC commands */ 121 | #define CDC_IN_EP 0x82 /* EP1 for data IN */ 122 | #define CDC_OUT_EP 0x02 /* EP1 for data OUT */ 123 | 124 | #define USB_DEVICE_CDC_REQUEST_SEND_ENCAPSULATED_COMMAND \ 125 | (0x00) /*!< The CDC class request code for SEND_ENCAPSULATED_COMMAND. */ 126 | #define USB_DEVICE_CDC_REQUEST_GET_ENCAPSULATED_RESPONSE \ 127 | (0x01) /*!< The CDC class request code for GET_ENCAPSULATED_RESPONSE. */ 128 | #define USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE (0x02) /*!< The CDC class request code for SET_COMM_FEATURE. */ 129 | #define USB_DEVICE_CDC_REQUEST_GET_COMM_FEATURE (0x03) /*!< The CDC class request code for GET_COMM_FEATURE. */ 130 | #define USB_DEVICE_CDC_REQUEST_CLEAR_COMM_FEATURE (0x04) /*!< The CDC class request code for CLEAR_COMM_FEATURE. */ 131 | #define USB_DEVICE_CDC_REQUEST_SET_AUX_LINE_STATE (0x10) /*!< The CDC class request code for SET_AUX_LINE_STATE. */ 132 | #define USB_DEVICE_CDC_REQUEST_SET_HOOK_STATE (0x11) /*!< The CDC class request code for SET_HOOK_STATE. */ 133 | #define USB_DEVICE_CDC_REQUEST_PULSE_SETUP (0x12) /*!< The CDC class request code for PULSE_SETUP. */ 134 | #define USB_DEVICE_CDC_REQUEST_SEND_PULSE (0x13) /*!< The CDC class request code for SEND_PULSE. */ 135 | #define USB_DEVICE_CDC_REQUEST_SET_PULSE_TIME (0x14) /*!< The CDC class request code for SET_PULSE_TIME. */ 136 | #define USB_DEVICE_CDC_REQUEST_RING_AUX_JACK (0x15) /*!< The CDC class request code for RING_AUX_JACK. */ 137 | #define USB_DEVICE_CDC_REQUEST_SET_LINE_CODING (0x20) /*!< The CDC class request code for SET_LINE_CODING. */ 138 | #define USB_DEVICE_CDC_REQUEST_GET_LINE_CODING (0x21) /*!< The CDC class request code for GET_LINE_CODING. */ 139 | #define USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE \ 140 | (0x22) /*!< The CDC class request code for SET_CONTROL_LINE_STATE. */ 141 | #define USB_DEVICE_CDC_REQUEST_SEND_BREAK (0x23) /*!< The CDC class request code for SEND_BREAK. */ 142 | #define USB_DEVICE_CDC_REQUEST_SET_RINGER_PARAMS (0x30) /*!< The CDC class request code for SET_RINGER_PARAMS. */ 143 | #define USB_DEVICE_CDC_REQUEST_GET_RINGER_PARAMS (0x31) /*!< The CDC class request code for GET_RINGER_PARAMS. */ 144 | #define USB_DEVICE_CDC_REQUEST_SET_OPERATION_PARAM (0x32) /*!< The CDC class request code for SET_OPERATION_PARAM. */ 145 | #define USB_DEVICE_CDC_REQUEST_GET_OPERATION_PARAM (0x33) /*!< The CDC class request code for GET_OPERATION_PARAM. */ 146 | #define USB_DEVICE_CDC_REQUEST_SET_LINE_PARAMS (0x34) /*!< The CDC class request code for SET_LINE_PARAMS. */ 147 | #define USB_DEVICE_CDC_REQUEST_GET_LINE_PARAMS (0x35) /*!< The CDC class request code for GET_LINE_PARAMS. */ 148 | #define USB_DEVICE_CDC_REQUEST_DIAL_DIGITS (0x36) /*!< The CDC class request code for DIAL_DIGITS. */ 149 | #define USB_DEVICE_CDC_REQUEST_SET_UNIT_PARAMETER (0x37) /*!< The CDC class request code for SET_UNIT_PARAMETER. */ 150 | #define USB_DEVICE_CDC_REQUEST_GET_UNIT_PARAMETER (0x38) /*!< The CDC class request code for GET_UNIT_PARAMETER. */ 151 | #define USB_DEVICE_CDC_REQUEST_CLEAR_UNIT_PARAMETER \ 152 | (0x39) /*!< The CDC class request code for CLEAR_UNIT_PARAMETER. */ 153 | #define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS \ 154 | (0x40) /*!< The CDC class request code for SET_ETHERNET_MULTICAST_FILTERS. */ 155 | #define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_POW_PATTER_FILTER \ 156 | (0x41) /*!< The CDC class request code for SET_ETHERNET_POW_PATTER_FILTER. */ 157 | #define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_POW_PATTER_FILTER \ 158 | (0x42) /*!< The CDC class request code for GET_ETHERNET_POW_PATTER_FILTER. */ 159 | #define USB_DEVICE_CDC_REQUEST_SET_ETHERNET_PACKET_FILTER \ 160 | (0x43) /*!< The CDC class request code for SET_ETHERNET_PACKET_FILTER. */ 161 | #define USB_DEVICE_CDC_REQUEST_GET_ETHERNET_STATISTIC \ 162 | (0x44) /*!< The CDC class request code for GET_ETHERNET_STATISTIC. */ 163 | #define USB_DEVICE_CDC_REQUEST_SET_ATM_DATA_FORMAT (0x50) /*!< The CDC class request code for SET_ATM_DATA_FORMAT. */ 164 | #define USB_DEVICE_CDC_REQUEST_GET_ATM_DEVICE_STATISTICS \ 165 | (0x51) /*!< The CDC class request code for GET_ATM_DEVICE_STATISTICS. */ 166 | #define USB_DEVICE_CDC_REQUEST_SET_ATM_DEFAULT_VC (0x52) /*!< The CDC class request code for SET_ATM_DEFAULT_VC. */ 167 | #define USB_DEVICE_CDC_REQUEST_GET_ATM_VC_STATISTICS \ 168 | (0x53) /*!< The CDC class request code for GET_ATM_VC_STATISTICS. */ 169 | #define USB_DEVICE_CDC_REQUEST_MDLM_SPECIFIC_REQUESTS_MASK \ 170 | (0x7F) /*!< The CDC class request code for MDLM_SPECIFIC_REQUESTS_MASK. */ 171 | 172 | #define RXCNT(bsize, nblock) (uint16_t)(((bsize & 1) << 15) | ((nblock / 2 & 0x1F) << 10)) 173 | #define LOBYTE(x) ((uint8_t)(x & 0x00FF)) 174 | #define HIBYTE(x) ((uint8_t)((x & 0xFF00) >> 8)) 175 | 176 | #define LOG_LENGTH 50 177 | #define LOG_DATA_LENGTH 10 178 | #define LOG_OP_RESET 1 179 | #define LOG_OP_GET_DESC_RX 2 180 | #define LOG_OP_GET_DESC_TX 3 181 | #define LOG_OP_GET_STATUS_TX 4 182 | #define LOG_OP_SET_ADDRESS_RX 5 183 | #define LOG_OP_GET_CLASS_DATA 6 184 | 185 | #define _USB_STRING_(name, ws) \ 186 | \ 187 | const struct name \ 188 | { \ 189 | uint8_t bLength; \ 190 | uint8_t bDescriptorType; \ 191 | uint16_t bString[(sizeof(ws) - 2) / 2]; \ 192 | \ 193 | } \ 194 | name __attribute__((used, section("usb_string"))) = {sizeof(name), 0x03, ws}; 195 | 196 | #define _USB_LANG_ID_(lng_id) \ 197 | \ 198 | const struct wLANGID \ 199 | { \ 200 | uint8_t bLength; \ 201 | uint8_t bDescriptorType; \ 202 | uint16_t bString[1]; \ 203 | \ 204 | } \ 205 | wLANGID __attribute__((used, section("usb_string"))) = {0x04, 0x03, lng_id}; 206 | 207 | #pragma pack(push, 1) 208 | 209 | typedef struct _USB_STRING_DESCRIPTOR_ { 210 | uint8_t bLength; 211 | uint8_t bDescriptorType; 212 | } USB_STR_DESCRIPTOR; 213 | 214 | typedef struct _USB_DEVICE_DESCRIPTOR_ { 215 | uint8_t bLength; 216 | uint8_t bDescriptorType; 217 | uint16_t bcdUSB; 218 | uint8_t bDeviceClass; 219 | uint8_t bDeviceSubClass; 220 | uint8_t bDeviceProtocol; 221 | uint8_t bMaxPacketSize0; 222 | uint16_t idVendor; 223 | uint16_t idProduct; 224 | uint16_t bcdDevice; 225 | uint8_t iManufacturer; 226 | uint8_t iProduct; 227 | uint8_t iSerialNumber; 228 | uint8_t bNumConfigurations; 229 | } USB_DEVICE_DESCRIPTOR; 230 | 231 | typedef struct { 232 | uint32_t EPR[8]; 233 | uint32_t RESERVED[8]; 234 | uint32_t CNTR; 235 | uint32_t ISTR; 236 | uint32_t FNR; 237 | uint32_t DADDR; 238 | uint32_t BTABLE; 239 | } USB_TypeDef; 240 | 241 | typedef struct { 242 | uint16_t Value; 243 | uint16_t _res; 244 | } USBLIB_PBElement; 245 | 246 | typedef struct { 247 | USBLIB_PBElement TX_Address; 248 | USBLIB_PBElement TX_Count; 249 | USBLIB_PBElement RX_Address; 250 | USBLIB_PBElement RX_Count; 251 | } USBLIB_EPBuf; 252 | 253 | typedef struct { 254 | uint16_t Number; // EP number 255 | uint16_t Type; // EP Type 256 | uint8_t TX_Max; // Max TX EP Buffer 257 | uint8_t RX_Max; // Max RT EP Buffer 258 | uint16_t *pTX_BUFF; // TX Buffer pointer 259 | uint32_t lTX; // TX Data length 260 | uint16_t *pRX_BUFF; // RX Buffer pointer 261 | uint32_t lRX; // RX Data length 262 | uint8_t TX_BUFF_SIZE; // Max length of pTX_BUFF buf, NOT a EP Buf!!! 263 | uint32_t lRX_PMA; // ? 264 | 265 | } USBLIB_EPData; 266 | 267 | typedef struct 268 | { 269 | uint8_t Recipient : 5; 270 | uint8_t Type : 2; 271 | uint8_t Dir : 1; 272 | } USBLIB_RequestType; 273 | 274 | typedef struct 275 | { 276 | uint8_t L : 8; 277 | uint8_t H : 8; 278 | } USBLIB_WByte; 279 | 280 | typedef struct 281 | { 282 | USBLIB_RequestType bmRequestType; 283 | uint8_t bRequest; 284 | USBLIB_WByte wValue; 285 | USBLIB_WByte wIndex; 286 | uint8_t wLength; 287 | } USBLIB_SetupPacket; 288 | 289 | typedef struct 290 | { 291 | uint8_t EPn; 292 | uint8_t Operation; 293 | uint8_t Data[LOG_DATA_LENGTH]; 294 | uint8_t Length; 295 | } USBLIB_Log; 296 | 297 | typedef struct { 298 | uint8_t Size; 299 | uint8_t DescriptorType; 300 | uint16_t *String; 301 | } USBLIB_StringDesc; 302 | 303 | typedef struct { 304 | uint32_t baudRate; 305 | uint8_t charFormat; 306 | uint8_t parityType; 307 | uint8_t dataBits; 308 | } USBLIB_LineCoding; 309 | 310 | #pragma pack(pop) 311 | 312 | void USBLIB_Init(void); 313 | void USBLIB_EP_Init(void); 314 | //void USBLIB_HandleStatus(void); 315 | void USBLIB_ResetUSB(void); 316 | void USBLIB_Reset(void); 317 | void USBLIB_SetEPTable(uint8_t EP, uint32_t TXAddress, uint32_t TXCount, uint32_t RXAddress, uint32_t RXCount); 318 | void USBLIB_LogCheckForTransmit(void); 319 | void USBLIB_Transmit(uint16_t *Data, uint16_t Length); 320 | void uUSBLIB_LineStateHandler(USBLIB_WByte LineState); 321 | 322 | __weak void uUSBLIB_DataReceivedHandler(uint16_t *Data, uint16_t Length); 323 | __weak void uUSBLIB_DataTransmitedHandler(uint8_t EPn, USBLIB_EPData EpData); 324 | 325 | #endif 326 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | GNU GENERAL PUBLIC LICENSE 2 | Version 3, 29 June 2007 3 | 4 | Copyright (C) 2007 Free Software Foundation, Inc. 5 | Everyone is permitted to copy and distribute verbatim copies 6 | of this license document, but changing it is not allowed. 7 | 8 | Preamble 9 | 10 | The GNU General Public License is a free, copyleft license for 11 | software and other kinds of works. 12 | 13 | The licenses for most software and other practical works are designed 14 | to take away your freedom to share and change the works. By contrast, 15 | the GNU General Public License is intended to guarantee your freedom to 16 | share and change all versions of a program--to make sure it remains free 17 | software for all its users. We, the Free Software Foundation, use the 18 | GNU General Public License for most of our software; it applies also to 19 | any other work released this way by its authors. You can apply it to 20 | your programs, too. 21 | 22 | When we speak of free software, we are referring to freedom, not 23 | price. Our General Public Licenses are designed to make sure that you 24 | have the freedom to distribute copies of free software (and charge for 25 | them if you wish), that you receive source code or can get it if you 26 | want it, that you can change the software or use pieces of it in new 27 | free programs, and that you know you can do these things. 28 | 29 | To protect your rights, we need to prevent others from denying you 30 | these rights or asking you to surrender the rights. Therefore, you have 31 | certain responsibilities if you distribute copies of the software, or if 32 | you modify it: responsibilities to respect the freedom of others. 33 | 34 | For example, if you distribute copies of such a program, whether 35 | gratis or for a fee, you must pass on to the recipients the same 36 | freedoms that you received. You must make sure that they, too, receive 37 | or can get the source code. And you must show them these terms so they 38 | know their rights. 39 | 40 | Developers that use the GNU GPL protect your rights with two steps: 41 | (1) assert copyright on the software, and (2) offer you this License 42 | giving you legal permission to copy, distribute and/or modify it. 43 | 44 | For the developers' and authors' protection, the GPL clearly explains 45 | that there is no warranty for this free software. For both users' and 46 | authors' sake, the GPL requires that modified versions be marked as 47 | changed, so that their problems will not be attributed erroneously to 48 | authors of previous versions. 49 | 50 | Some devices are designed to deny users access to install or run 51 | modified versions of the software inside them, although the manufacturer 52 | can do so. This is fundamentally incompatible with the aim of 53 | protecting users' freedom to change the software. The systematic 54 | pattern of such abuse occurs in the area of products for individuals to 55 | use, which is precisely where it is most unacceptable. Therefore, we 56 | have designed this version of the GPL to prohibit the practice for those 57 | products. If such problems arise substantially in other domains, we 58 | stand ready to extend this provision to those domains in future versions 59 | of the GPL, as needed to protect the freedom of users. 60 | 61 | Finally, every program is threatened constantly by software patents. 62 | States should not allow patents to restrict development and use of 63 | software on general-purpose computers, but in those that do, we wish to 64 | avoid the special danger that patents applied to a free program could 65 | make it effectively proprietary. To prevent this, the GPL assures that 66 | patents cannot be used to render the program non-free. 67 | 68 | The precise terms and conditions for copying, distribution and 69 | modification follow. 70 | 71 | TERMS AND CONDITIONS 72 | 73 | 0. Definitions. 74 | 75 | "This License" refers to version 3 of the GNU General Public License. 76 | 77 | "Copyright" also means copyright-like laws that apply to other kinds of 78 | works, such as semiconductor masks. 79 | 80 | "The Program" refers to any copyrightable work licensed under this 81 | License. Each licensee is addressed as "you". "Licensees" and 82 | "recipients" may be individuals or organizations. 83 | 84 | To "modify" a work means to copy from or adapt all or part of the work 85 | in a fashion requiring copyright permission, other than the making of an 86 | exact copy. The resulting work is called a "modified version" of the 87 | earlier work or a work "based on" the earlier work. 88 | 89 | A "covered work" means either the unmodified Program or a work based 90 | on the Program. 91 | 92 | To "propagate" a work means to do anything with it that, without 93 | permission, would make you directly or secondarily liable for 94 | infringement under applicable copyright law, except executing it on a 95 | computer or modifying a private copy. Propagation includes copying, 96 | distribution (with or without modification), making available to the 97 | public, and in some countries other activities as well. 98 | 99 | To "convey" a work means any kind of propagation that enables other 100 | parties to make or receive copies. Mere interaction with a user through 101 | a computer network, with no transfer of a copy, is not conveying. 102 | 103 | An interactive user interface displays "Appropriate Legal Notices" 104 | to the extent that it includes a convenient and prominently visible 105 | feature that (1) displays an appropriate copyright notice, and (2) 106 | tells the user that there is no warranty for the work (except to the 107 | extent that warranties are provided), that licensees may convey the 108 | work under this License, and how to view a copy of this License. If 109 | the interface presents a list of user commands or options, such as a 110 | menu, a prominent item in the list meets this criterion. 111 | 112 | 1. Source Code. 113 | 114 | The "source code" for a work means the preferred form of the work 115 | for making modifications to it. "Object code" means any non-source 116 | form of a work. 117 | 118 | A "Standard Interface" means an interface that either is an official 119 | standard defined by a recognized standards body, or, in the case of 120 | interfaces specified for a particular programming language, one that 121 | is widely used among developers working in that language. 122 | 123 | The "System Libraries" of an executable work include anything, other 124 | than the work as a whole, that (a) is included in the normal form of 125 | packaging a Major Component, but which is not part of that Major 126 | Component, and (b) serves only to enable use of the work with that 127 | Major Component, or to implement a Standard Interface for which an 128 | implementation is available to the public in source code form. A 129 | "Major Component", in this context, means a major essential component 130 | (kernel, window system, and so on) of the specific operating system 131 | (if any) on which the executable work runs, or a compiler used to 132 | produce the work, or an object code interpreter used to run it. 133 | 134 | The "Corresponding Source" for a work in object code form means all 135 | the source code needed to generate, install, and (for an executable 136 | work) run the object code and to modify the work, including scripts to 137 | control those activities. However, it does not include the work's 138 | System Libraries, or general-purpose tools or generally available free 139 | programs which are used unmodified in performing those activities but 140 | which are not part of the work. For example, Corresponding Source 141 | includes interface definition files associated with source files for 142 | the work, and the source code for shared libraries and dynamically 143 | linked subprograms that the work is specifically designed to require, 144 | such as by intimate data communication or control flow between those 145 | subprograms and other parts of the work. 146 | 147 | The Corresponding Source need not include anything that users 148 | can regenerate automatically from other parts of the Corresponding 149 | Source. 150 | 151 | The Corresponding Source for a work in source code form is that 152 | same work. 153 | 154 | 2. Basic Permissions. 155 | 156 | All rights granted under this License are granted for the term of 157 | copyright on the Program, and are irrevocable provided the stated 158 | conditions are met. This License explicitly affirms your unlimited 159 | permission to run the unmodified Program. The output from running a 160 | covered work is covered by this License only if the output, given its 161 | content, constitutes a covered work. This License acknowledges your 162 | rights of fair use or other equivalent, as provided by copyright law. 163 | 164 | You may make, run and propagate covered works that you do not 165 | convey, without conditions so long as your license otherwise remains 166 | in force. You may convey covered works to others for the sole purpose 167 | of having them make modifications exclusively for you, or provide you 168 | with facilities for running those works, provided that you comply with 169 | the terms of this License in conveying all material for which you do 170 | not control copyright. Those thus making or running the covered works 171 | for you must do so exclusively on your behalf, under your direction 172 | and control, on terms that prohibit them from making any copies of 173 | your copyrighted material outside their relationship with you. 174 | 175 | Conveying under any other circumstances is permitted solely under 176 | the conditions stated below. Sublicensing is not allowed; section 10 177 | makes it unnecessary. 178 | 179 | 3. Protecting Users' Legal Rights From Anti-Circumvention Law. 180 | 181 | No covered work shall be deemed part of an effective technological 182 | measure under any applicable law fulfilling obligations under article 183 | 11 of the WIPO copyright treaty adopted on 20 December 1996, or 184 | similar laws prohibiting or restricting circumvention of such 185 | measures. 186 | 187 | When you convey a covered work, you waive any legal power to forbid 188 | circumvention of technological measures to the extent such circumvention 189 | is effected by exercising rights under this License with respect to 190 | the covered work, and you disclaim any intention to limit operation or 191 | modification of the work as a means of enforcing, against the work's 192 | users, your or third parties' legal rights to forbid circumvention of 193 | technological measures. 194 | 195 | 4. Conveying Verbatim Copies. 196 | 197 | You may convey verbatim copies of the Program's source code as you 198 | receive it, in any medium, provided that you conspicuously and 199 | appropriately publish on each copy an appropriate copyright notice; 200 | keep intact all notices stating that this License and any 201 | non-permissive terms added in accord with section 7 apply to the code; 202 | keep intact all notices of the absence of any warranty; and give all 203 | recipients a copy of this License along with the Program. 204 | 205 | You may charge any price or no price for each copy that you convey, 206 | and you may offer support or warranty protection for a fee. 207 | 208 | 5. Conveying Modified Source Versions. 209 | 210 | You may convey a work based on the Program, or the modifications to 211 | produce it from the Program, in the form of source code under the 212 | terms of section 4, provided that you also meet all of these conditions: 213 | 214 | a) The work must carry prominent notices stating that you modified 215 | it, and giving a relevant date. 216 | 217 | b) The work must carry prominent notices stating that it is 218 | released under this License and any conditions added under section 219 | 7. This requirement modifies the requirement in section 4 to 220 | "keep intact all notices". 221 | 222 | c) You must license the entire work, as a whole, under this 223 | License to anyone who comes into possession of a copy. This 224 | License will therefore apply, along with any applicable section 7 225 | additional terms, to the whole of the work, and all its parts, 226 | regardless of how they are packaged. This License gives no 227 | permission to license the work in any other way, but it does not 228 | invalidate such permission if you have separately received it. 229 | 230 | d) If the work has interactive user interfaces, each must display 231 | Appropriate Legal Notices; however, if the Program has interactive 232 | interfaces that do not display Appropriate Legal Notices, your 233 | work need not make them do so. 234 | 235 | A compilation of a covered work with other separate and independent 236 | works, which are not by their nature extensions of the covered work, 237 | and which are not combined with it such as to form a larger program, 238 | in or on a volume of a storage or distribution medium, is called an 239 | "aggregate" if the compilation and its resulting copyright are not 240 | used to limit the access or legal rights of the compilation's users 241 | beyond what the individual works permit. Inclusion of a covered work 242 | in an aggregate does not cause this License to apply to the other 243 | parts of the aggregate. 244 | 245 | 6. Conveying Non-Source Forms. 246 | 247 | You may convey a covered work in object code form under the terms 248 | of sections 4 and 5, provided that you also convey the 249 | machine-readable Corresponding Source under the terms of this License, 250 | in one of these ways: 251 | 252 | a) Convey the object code in, or embodied in, a physical product 253 | (including a physical distribution medium), accompanied by the 254 | Corresponding Source fixed on a durable physical medium 255 | customarily used for software interchange. 256 | 257 | b) Convey the object code in, or embodied in, a physical product 258 | (including a physical distribution medium), accompanied by a 259 | written offer, valid for at least three years and valid for as 260 | long as you offer spare parts or customer support for that product 261 | model, to give anyone who possesses the object code either (1) a 262 | copy of the Corresponding Source for all the software in the 263 | product that is covered by this License, on a durable physical 264 | medium customarily used for software interchange, for a price no 265 | more than your reasonable cost of physically performing this 266 | conveying of source, or (2) access to copy the 267 | Corresponding Source from a network server at no charge. 268 | 269 | c) Convey individual copies of the object code with a copy of the 270 | written offer to provide the Corresponding Source. This 271 | alternative is allowed only occasionally and noncommercially, and 272 | only if you received the object code with such an offer, in accord 273 | with subsection 6b. 274 | 275 | d) Convey the object code by offering access from a designated 276 | place (gratis or for a charge), and offer equivalent access to the 277 | Corresponding Source in the same way through the same place at no 278 | further charge. You need not require recipients to copy the 279 | Corresponding Source along with the object code. If the place to 280 | copy the object code is a network server, the Corresponding Source 281 | may be on a different server (operated by you or a third party) 282 | that supports equivalent copying facilities, provided you maintain 283 | clear directions next to the object code saying where to find the 284 | Corresponding Source. Regardless of what server hosts the 285 | Corresponding Source, you remain obligated to ensure that it is 286 | available for as long as needed to satisfy these requirements. 287 | 288 | e) Convey the object code using peer-to-peer transmission, provided 289 | you inform other peers where the object code and Corresponding 290 | Source of the work are being offered to the general public at no 291 | charge under subsection 6d. 292 | 293 | A separable portion of the object code, whose source code is excluded 294 | from the Corresponding Source as a System Library, need not be 295 | included in conveying the object code work. 296 | 297 | A "User Product" is either (1) a "consumer product", which means any 298 | tangible personal property which is normally used for personal, family, 299 | or household purposes, or (2) anything designed or sold for incorporation 300 | into a dwelling. In determining whether a product is a consumer product, 301 | doubtful cases shall be resolved in favor of coverage. For a particular 302 | product received by a particular user, "normally used" refers to a 303 | typical or common use of that class of product, regardless of the status 304 | of the particular user or of the way in which the particular user 305 | actually uses, or expects or is expected to use, the product. A product 306 | is a consumer product regardless of whether the product has substantial 307 | commercial, industrial or non-consumer uses, unless such uses represent 308 | the only significant mode of use of the product. 309 | 310 | "Installation Information" for a User Product means any methods, 311 | procedures, authorization keys, or other information required to install 312 | and execute modified versions of a covered work in that User Product from 313 | a modified version of its Corresponding Source. The information must 314 | suffice to ensure that the continued functioning of the modified object 315 | code is in no case prevented or interfered with solely because 316 | modification has been made. 317 | 318 | If you convey an object code work under this section in, or with, or 319 | specifically for use in, a User Product, and the conveying occurs as 320 | part of a transaction in which the right of possession and use of the 321 | User Product is transferred to the recipient in perpetuity or for a 322 | fixed term (regardless of how the transaction is characterized), the 323 | Corresponding Source conveyed under this section must be accompanied 324 | by the Installation Information. But this requirement does not apply 325 | if neither you nor any third party retains the ability to install 326 | modified object code on the User Product (for example, the work has 327 | been installed in ROM). 328 | 329 | The requirement to provide Installation Information does not include a 330 | requirement to continue to provide support service, warranty, or updates 331 | for a work that has been modified or installed by the recipient, or for 332 | the User Product in which it has been modified or installed. Access to a 333 | network may be denied when the modification itself materially and 334 | adversely affects the operation of the network or violates the rules and 335 | protocols for communication across the network. 336 | 337 | Corresponding Source conveyed, and Installation Information provided, 338 | in accord with this section must be in a format that is publicly 339 | documented (and with an implementation available to the public in 340 | source code form), and must require no special password or key for 341 | unpacking, reading or copying. 342 | 343 | 7. Additional Terms. 344 | 345 | "Additional permissions" are terms that supplement the terms of this 346 | License by making exceptions from one or more of its conditions. 347 | Additional permissions that are applicable to the entire Program shall 348 | be treated as though they were included in this License, to the extent 349 | that they are valid under applicable law. If additional permissions 350 | apply only to part of the Program, that part may be used separately 351 | under those permissions, but the entire Program remains governed by 352 | this License without regard to the additional permissions. 353 | 354 | When you convey a copy of a covered work, you may at your option 355 | remove any additional permissions from that copy, or from any part of 356 | it. (Additional permissions may be written to require their own 357 | removal in certain cases when you modify the work.) You may place 358 | additional permissions on material, added by you to a covered work, 359 | for which you have or can give appropriate copyright permission. 360 | 361 | Notwithstanding any other provision of this License, for material you 362 | add to a covered work, you may (if authorized by the copyright holders of 363 | that material) supplement the terms of this License with terms: 364 | 365 | a) Disclaiming warranty or limiting liability differently from the 366 | terms of sections 15 and 16 of this License; or 367 | 368 | b) Requiring preservation of specified reasonable legal notices or 369 | author attributions in that material or in the Appropriate Legal 370 | Notices displayed by works containing it; or 371 | 372 | c) Prohibiting misrepresentation of the origin of that material, or 373 | requiring that modified versions of such material be marked in 374 | reasonable ways as different from the original version; or 375 | 376 | d) Limiting the use for publicity purposes of names of licensors or 377 | authors of the material; or 378 | 379 | e) Declining to grant rights under trademark law for use of some 380 | trade names, trademarks, or service marks; or 381 | 382 | f) Requiring indemnification of licensors and authors of that 383 | material by anyone who conveys the material (or modified versions of 384 | it) with contractual assumptions of liability to the recipient, for 385 | any liability that these contractual assumptions directly impose on 386 | those licensors and authors. 387 | 388 | All other non-permissive additional terms are considered "further 389 | restrictions" within the meaning of section 10. If the Program as you 390 | received it, or any part of it, contains a notice stating that it is 391 | governed by this License along with a term that is a further 392 | restriction, you may remove that term. If a license document contains 393 | a further restriction but permits relicensing or conveying under this 394 | License, you may add to a covered work material governed by the terms 395 | of that license document, provided that the further restriction does 396 | not survive such relicensing or conveying. 397 | 398 | If you add terms to a covered work in accord with this section, you 399 | must place, in the relevant source files, a statement of the 400 | additional terms that apply to those files, or a notice indicating 401 | where to find the applicable terms. 402 | 403 | Additional terms, permissive or non-permissive, may be stated in the 404 | form of a separately written license, or stated as exceptions; 405 | the above requirements apply either way. 406 | 407 | 8. Termination. 408 | 409 | You may not propagate or modify a covered work except as expressly 410 | provided under this License. Any attempt otherwise to propagate or 411 | modify it is void, and will automatically terminate your rights under 412 | this License (including any patent licenses granted under the third 413 | paragraph of section 11). 414 | 415 | However, if you cease all violation of this License, then your 416 | license from a particular copyright holder is reinstated (a) 417 | provisionally, unless and until the copyright holder explicitly and 418 | finally terminates your license, and (b) permanently, if the copyright 419 | holder fails to notify you of the violation by some reasonable means 420 | prior to 60 days after the cessation. 421 | 422 | Moreover, your license from a particular copyright holder is 423 | reinstated permanently if the copyright holder notifies you of the 424 | violation by some reasonable means, this is the first time you have 425 | received notice of violation of this License (for any work) from that 426 | copyright holder, and you cure the violation prior to 30 days after 427 | your receipt of the notice. 428 | 429 | Termination of your rights under this section does not terminate the 430 | licenses of parties who have received copies or rights from you under 431 | this License. If your rights have been terminated and not permanently 432 | reinstated, you do not qualify to receive new licenses for the same 433 | material under section 10. 434 | 435 | 9. Acceptance Not Required for Having Copies. 436 | 437 | You are not required to accept this License in order to receive or 438 | run a copy of the Program. Ancillary propagation of a covered work 439 | occurring solely as a consequence of using peer-to-peer transmission 440 | to receive a copy likewise does not require acceptance. However, 441 | nothing other than this License grants you permission to propagate or 442 | modify any covered work. These actions infringe copyright if you do 443 | not accept this License. Therefore, by modifying or propagating a 444 | covered work, you indicate your acceptance of this License to do so. 445 | 446 | 10. Automatic Licensing of Downstream Recipients. 447 | 448 | Each time you convey a covered work, the recipient automatically 449 | receives a license from the original licensors, to run, modify and 450 | propagate that work, subject to this License. You are not responsible 451 | for enforcing compliance by third parties with this License. 452 | 453 | An "entity transaction" is a transaction transferring control of an 454 | organization, or substantially all assets of one, or subdividing an 455 | organization, or merging organizations. If propagation of a covered 456 | work results from an entity transaction, each party to that 457 | transaction who receives a copy of the work also receives whatever 458 | licenses to the work the party's predecessor in interest had or could 459 | give under the previous paragraph, plus a right to possession of the 460 | Corresponding Source of the work from the predecessor in interest, if 461 | the predecessor has it or can get it with reasonable efforts. 462 | 463 | You may not impose any further restrictions on the exercise of the 464 | rights granted or affirmed under this License. For example, you may 465 | not impose a license fee, royalty, or other charge for exercise of 466 | rights granted under this License, and you may not initiate litigation 467 | (including a cross-claim or counterclaim in a lawsuit) alleging that 468 | any patent claim is infringed by making, using, selling, offering for 469 | sale, or importing the Program or any portion of it. 470 | 471 | 11. Patents. 472 | 473 | A "contributor" is a copyright holder who authorizes use under this 474 | License of the Program or a work on which the Program is based. The 475 | work thus licensed is called the contributor's "contributor version". 476 | 477 | A contributor's "essential patent claims" are all patent claims 478 | owned or controlled by the contributor, whether already acquired or 479 | hereafter acquired, that would be infringed by some manner, permitted 480 | by this License, of making, using, or selling its contributor version, 481 | but do not include claims that would be infringed only as a 482 | consequence of further modification of the contributor version. For 483 | purposes of this definition, "control" includes the right to grant 484 | patent sublicenses in a manner consistent with the requirements of 485 | this License. 486 | 487 | Each contributor grants you a non-exclusive, worldwide, royalty-free 488 | patent license under the contributor's essential patent claims, to 489 | make, use, sell, offer for sale, import and otherwise run, modify and 490 | propagate the contents of its contributor version. 491 | 492 | In the following three paragraphs, a "patent license" is any express 493 | agreement or commitment, however denominated, not to enforce a patent 494 | (such as an express permission to practice a patent or covenant not to 495 | sue for patent infringement). To "grant" such a patent license to a 496 | party means to make such an agreement or commitment not to enforce a 497 | patent against the party. 498 | 499 | If you convey a covered work, knowingly relying on a patent license, 500 | and the Corresponding Source of the work is not available for anyone 501 | to copy, free of charge and under the terms of this License, through a 502 | publicly available network server or other readily accessible means, 503 | then you must either (1) cause the Corresponding Source to be so 504 | available, or (2) arrange to deprive yourself of the benefit of the 505 | patent license for this particular work, or (3) arrange, in a manner 506 | consistent with the requirements of this License, to extend the patent 507 | license to downstream recipients. "Knowingly relying" means you have 508 | actual knowledge that, but for the patent license, your conveying the 509 | covered work in a country, or your recipient's use of the covered work 510 | in a country, would infringe one or more identifiable patents in that 511 | country that you have reason to believe are valid. 512 | 513 | If, pursuant to or in connection with a single transaction or 514 | arrangement, you convey, or propagate by procuring conveyance of, a 515 | covered work, and grant a patent license to some of the parties 516 | receiving the covered work authorizing them to use, propagate, modify 517 | or convey a specific copy of the covered work, then the patent license 518 | you grant is automatically extended to all recipients of the covered 519 | work and works based on it. 520 | 521 | A patent license is "discriminatory" if it does not include within 522 | the scope of its coverage, prohibits the exercise of, or is 523 | conditioned on the non-exercise of one or more of the rights that are 524 | specifically granted under this License. You may not convey a covered 525 | work if you are a party to an arrangement with a third party that is 526 | in the business of distributing software, under which you make payment 527 | to the third party based on the extent of your activity of conveying 528 | the work, and under which the third party grants, to any of the 529 | parties who would receive the covered work from you, a discriminatory 530 | patent license (a) in connection with copies of the covered work 531 | conveyed by you (or copies made from those copies), or (b) primarily 532 | for and in connection with specific products or compilations that 533 | contain the covered work, unless you entered into that arrangement, 534 | or that patent license was granted, prior to 28 March 2007. 535 | 536 | Nothing in this License shall be construed as excluding or limiting 537 | any implied license or other defenses to infringement that may 538 | otherwise be available to you under applicable patent law. 539 | 540 | 12. No Surrender of Others' Freedom. 541 | 542 | If conditions are imposed on you (whether by court order, agreement or 543 | otherwise) that contradict the conditions of this License, they do not 544 | excuse you from the conditions of this License. If you cannot convey a 545 | covered work so as to satisfy simultaneously your obligations under this 546 | License and any other pertinent obligations, then as a consequence you may 547 | not convey it at all. For example, if you agree to terms that obligate you 548 | to collect a royalty for further conveying from those to whom you convey 549 | the Program, the only way you could satisfy both those terms and this 550 | License would be to refrain entirely from conveying the Program. 551 | 552 | 13. Use with the GNU Affero General Public License. 553 | 554 | Notwithstanding any other provision of this License, you have 555 | permission to link or combine any covered work with a work licensed 556 | under version 3 of the GNU Affero General Public License into a single 557 | combined work, and to convey the resulting work. The terms of this 558 | License will continue to apply to the part which is the covered work, 559 | but the special requirements of the GNU Affero General Public License, 560 | section 13, concerning interaction through a network will apply to the 561 | combination as such. 562 | 563 | 14. Revised Versions of this License. 564 | 565 | The Free Software Foundation may publish revised and/or new versions of 566 | the GNU General Public License from time to time. Such new versions will 567 | be similar in spirit to the present version, but may differ in detail to 568 | address new problems or concerns. 569 | 570 | Each version is given a distinguishing version number. If the 571 | Program specifies that a certain numbered version of the GNU General 572 | Public License "or any later version" applies to it, you have the 573 | option of following the terms and conditions either of that numbered 574 | version or of any later version published by the Free Software 575 | Foundation. If the Program does not specify a version number of the 576 | GNU General Public License, you may choose any version ever published 577 | by the Free Software Foundation. 578 | 579 | If the Program specifies that a proxy can decide which future 580 | versions of the GNU General Public License can be used, that proxy's 581 | public statement of acceptance of a version permanently authorizes you 582 | to choose that version for the Program. 583 | 584 | Later license versions may give you additional or different 585 | permissions. However, no additional obligations are imposed on any 586 | author or copyright holder as a result of your choosing to follow a 587 | later version. 588 | 589 | 15. Disclaimer of Warranty. 590 | 591 | THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY 592 | APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT 593 | HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY 594 | OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, 595 | THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 596 | PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM 597 | IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF 598 | ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 599 | 600 | 16. Limitation of Liability. 601 | 602 | IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING 603 | WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS 604 | THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY 605 | GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE 606 | USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF 607 | DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD 608 | PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), 609 | EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF 610 | SUCH DAMAGES. 611 | 612 | 17. Interpretation of Sections 15 and 16. 613 | 614 | If the disclaimer of warranty and limitation of liability provided 615 | above cannot be given local legal effect according to their terms, 616 | reviewing courts shall apply local law that most closely approximates 617 | an absolute waiver of all civil liability in connection with the 618 | Program, unless a warranty or assumption of liability accompanies a 619 | copy of the Program in return for a fee. 620 | 621 | END OF TERMS AND CONDITIONS 622 | 623 | How to Apply These Terms to Your New Programs 624 | 625 | If you develop a new program, and you want it to be of the greatest 626 | possible use to the public, the best way to achieve this is to make it 627 | free software which everyone can redistribute and change under these terms. 628 | 629 | To do so, attach the following notices to the program. It is safest 630 | to attach them to the start of each source file to most effectively 631 | state the exclusion of warranty; and each file should have at least 632 | the "copyright" line and a pointer to where the full notice is found. 633 | 634 | 635 | Copyright (C) 636 | 637 | This program is free software: you can redistribute it and/or modify 638 | it under the terms of the GNU General Public License as published by 639 | the Free Software Foundation, either version 3 of the License, or 640 | (at your option) any later version. 641 | 642 | This program is distributed in the hope that it will be useful, 643 | but WITHOUT ANY WARRANTY; without even the implied warranty of 644 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 645 | GNU General Public License for more details. 646 | 647 | You should have received a copy of the GNU General Public License 648 | along with this program. If not, see . 649 | 650 | Also add information on how to contact you by electronic and paper mail. 651 | 652 | If the program does terminal interaction, make it output a short 653 | notice like this when it starts in an interactive mode: 654 | 655 | Copyright (C) 656 | This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. 657 | This is free software, and you are welcome to redistribute it 658 | under certain conditions; type `show c' for details. 659 | 660 | The hypothetical commands `show w' and `show c' should show the appropriate 661 | parts of the General Public License. Of course, your program's commands 662 | might be different; for a GUI interface, you would use an "about box". 663 | 664 | You should also get your employer (if you work as a programmer) or school, 665 | if any, to sign a "copyright disclaimer" for the program, if necessary. 666 | For more information on this, and how to apply and follow the GNU GPL, see 667 | . 668 | 669 | The GNU General Public License does not permit incorporating your program 670 | into proprietary programs. If your program is a subroutine library, you 671 | may consider it more useful to permit linking proprietary applications with 672 | the library. If this is what you want to do, use the GNU Lesser General 673 | Public License instead of this License. But first, please read 674 | . 675 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # STM32F103-USB-CDC-CMSIS 2 | STM32F103 USB CDC CMSIS provires a simple low weight firmware for STM32F1 serie to implement Virtual Com Port. 3 | Current implementation create Virtual Com Port with next settings: 115200, 0, none, 8, but you can change these settings as you want. 4 | ## How to use 5 | * Add `usblib.c` and `usblib.h` to your project. 6 | * Make sure you have configured USB to 48 MHz clock and RCC to 48 MHz or more (72 MHz is recomended). 7 | * It's strongly recomended to use 1,5K GPIO driven pull-up rezistor to have full controll of USB line initiate sequence. 8 | * Call `USBLIB_Init();` to enable USB and make initial configuration of USB registers. Please note - `USBLIB_Init();` will trigget USB RESET sequence. 9 | * Enable 1.5K pull-up resistor to allow host detect device connection. 10 | * If your device connected to Windows host use `RemoteSwitchHUB.inf` to install a default Windows driver. After installation you will see new COM port named `RemoteSwitch HUB` (If you want to change this name you need to edit it in `usblib.c` and `inf` files). 11 | * If your device connected to Unix systems then you will see a new device in /dev/ dir. 12 | * Implement ```void uUSBLIB_LineStateHandler(USBLIB_WByte LineState)``` in your code to handle line state. See `main.c` for example. 13 | NOTE: you can't send any data to host when port is closed! To controll when port is opened use this condition: 14 | ```c 15 | if (LineState.L) { //App connected to the virtual port 16 | USBLIB_Transmit((uint16_t *)"Welcome to the club!\r\n", 22); 17 | } 18 | ``` 19 | * Inplement `void uUSBLIB_DataReceivedHandler(uint16_t *Data, uint16_t Length)` in your code to accept data from host. See `main.c` f.e. 20 | 21 | Code well tested on Windows7, MacOS 10.13 (High Sierra) and Raspbian OS. 22 | -------------------------------------------------------------------------------- /RTE/Device/STM32F103C8/RTE_Device.h: -------------------------------------------------------------------------------- 1 | /* ----------------------------------------------------------------------------- 2 | * Copyright (C) 2015 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 8. October 2015 5 | * $Revision: V1.1.0 6 | * 7 | * Project: RTE Device Configuration for STMicroelectronics STM32F1xx 8 | * -------------------------------------------------------------------------- */ 9 | 10 | //-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- 11 | 12 | #ifndef __RTE_DEVICE_H 13 | #define __RTE_DEVICE_H 14 | 15 | 16 | #define GPIO_PORT(num) \ 17 | ((num == 0) ? GPIOA : \ 18 | (num == 1) ? GPIOB : \ 19 | (num == 2) ? GPIOC : \ 20 | (num == 3) ? GPIOD : \ 21 | (num == 4) ? GPIOE : \ 22 | (num == 5) ? GPIOF : \ 23 | (num == 6) ? GPIOG : \ 24 | NULL) 25 | 26 | 27 | // Clock Configuration 28 | // High-speed Internal Clock <1-999999999> 29 | #define RTE_HSI 8000000 30 | // High-speed External Clock <1-999999999> 31 | #define RTE_HSE 25000000 32 | // System Clock <1-999999999> 33 | #define RTE_SYSCLK 72000000 34 | // HCLK Clock <1-999999999> 35 | #define RTE_HCLK 72000000 36 | // APB1 Clock <1-999999999> 37 | #define RTE_PCLK1 36000000 38 | // APB2 Clock <1-999999999> 39 | #define RTE_PCLK2 72000000 40 | // ADC Clock <1-999999999> 41 | #define RTE_ADCCLK 36000000 42 | // USB Clock 43 | #define RTE_USBCLK 48000000 44 | // 45 | 46 | 47 | // USART1 (Universal synchronous asynchronous receiver transmitter) 48 | // Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART 49 | #define RTE_USART1 0 50 | 51 | // USART1_TX Pin <0=>PA9 52 | #define RTE_USART1_TX_PORT_ID_DEF 0 53 | #if (RTE_USART1_TX_PORT_ID_DEF == 0) 54 | #define RTE_USART1_TX_PORT_DEF GPIOA 55 | #define RTE_USART1_TX_BIT_DEF 9 56 | #else 57 | #error "Invalid USART1_TX Pin Configuration!" 58 | #endif 59 | 60 | // USART1_RX Pin <0=>PA10 61 | #define RTE_USART1_RX_PORT_ID_DEF 0 62 | #if (RTE_USART1_RX_PORT_ID_DEF == 0) 63 | #define RTE_USART1_RX_PORT_DEF GPIOA 64 | #define RTE_USART1_RX_BIT_DEF 10 65 | #else 66 | #error "Invalid USART1_RX Pin Configuration!" 67 | #endif 68 | 69 | // USART1_CK Pin <0=>Not Used <1=>PA8 70 | #define RTE_USART1_CK_PORT_ID_DEF 0 71 | #if (RTE_USART1_CK_PORT_ID_DEF == 0) 72 | #define RTE_USART1_CK 0 73 | #elif (RTE_USART1_CK_PORT_ID_DEF == 1) 74 | #define RTE_USART1_CK 1 75 | #define RTE_USART1_CK_PORT_DEF GPIOA 76 | #define RTE_USART1_CK_BIT_DEF 8 77 | #else 78 | #error "Invalid USART1_CK Pin Configuration!" 79 | #endif 80 | 81 | // USART1_CTS Pin <0=>Not Used <1=>PA11 82 | #define RTE_USART1_CTS_PORT_ID_DEF 0 83 | #if (RTE_USART1_CTS_PORT_ID_DEF == 0) 84 | #define RTE_USART1_CTS 0 85 | #elif (RTE_USART1_CTS_PORT_ID_DEF == 1) 86 | #define RTE_USART1_CTS 1 87 | #define RTE_USART1_CTS_PORT_DEF GPIOA 88 | #define RTE_USART1_CTS_BIT_DEF 11 89 | #else 90 | #error "Invalid USART1_CTS Pin Configuration!" 91 | #endif 92 | 93 | // USART1_RTS Pin <0=>Not Used <1=>PA12 94 | #define RTE_USART1_RTS_PORT_ID_DEF 0 95 | #if (RTE_USART1_RTS_PORT_ID_DEF == 0) 96 | #define RTE_USART1_RTS 0 97 | #elif (RTE_USART1_RTS_PORT_ID_DEF == 1) 98 | #define RTE_USART1_RTS 1 99 | #define RTE_USART1_RTS_PORT_DEF GPIOA 100 | #define RTE_USART1_RTS_BIT_DEF 12 101 | #else 102 | #error "Invalid USART1_RTS Pin Configuration!" 103 | #endif 104 | 105 | // USART1 Pin Remap 106 | // Enable USART1 Pin Remapping 107 | #define RTE_USART1_REMAP_FULL 0 108 | 109 | // USART1_TX Pin <0=>PB6 110 | #define RTE_USART1_TX_PORT_ID_FULL 0 111 | #if (RTE_USART1_TX_PORT_ID_FULL == 0) 112 | #define RTE_USART1_TX_PORT_FULL GPIOB 113 | #define RTE_USART1_TX_BIT_FULL 6 114 | #else 115 | #error "Invalid USART1_TX Pin Configuration!" 116 | #endif 117 | 118 | // USART1_RX Pin <0=>PB7 119 | #define RTE_USART1_RX_PORT_ID_FULL 0 120 | #if (RTE_USART1_RX_PORT_ID_FULL == 0) 121 | #define RTE_USART1_RX_PORT_FULL GPIOB 122 | #define RTE_USART1_RX_BIT_FULL 7 123 | #else 124 | #error "Invalid USART1_RX Pin Configuration!" 125 | #endif 126 | // 127 | 128 | #if (RTE_USART1_REMAP_FULL) 129 | #define RTE_USART1_AF_REMAP AFIO_USART1_REMAP 130 | #define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_FULL 131 | #define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_FULL 132 | #define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_FULL 133 | #define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_FULL 134 | #define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF 135 | #define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF 136 | #define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF 137 | #define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF 138 | #define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF 139 | #define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF 140 | #else 141 | #define RTE_USART1_AF_REMAP AFIO_USART1_NO_REMAP 142 | #define RTE_USART1_TX_PORT RTE_USART1_TX_PORT_DEF 143 | #define RTE_USART1_TX_BIT RTE_USART1_TX_BIT_DEF 144 | #define RTE_USART1_RX_PORT RTE_USART1_RX_PORT_DEF 145 | #define RTE_USART1_RX_BIT RTE_USART1_RX_BIT_DEF 146 | #define RTE_USART1_CK_PORT RTE_USART1_CK_PORT_DEF 147 | #define RTE_USART1_CK_BIT RTE_USART1_CK_BIT_DEF 148 | #define RTE_USART1_CTS_PORT RTE_USART1_CTS_PORT_DEF 149 | #define RTE_USART1_CTS_BIT RTE_USART1_CTS_BIT_DEF 150 | #define RTE_USART1_RTS_PORT RTE_USART1_RTS_PORT_DEF 151 | #define RTE_USART1_RTS_BIT RTE_USART1_RTS_BIT_DEF 152 | #endif 153 | 154 | // DMA Rx 155 | // Number <1=>1 156 | // Selects DMA Number (only DMA1 can be used) 157 | // Channel <5=>5 158 | // Selects DMA Channel (only Channel 5 can be used) 159 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 160 | // Set DMA Channel priority 161 | // 162 | #define RTE_USART1_RX_DMA 0 163 | #define RTE_USART1_RX_DMA_NUMBER 1 164 | #define RTE_USART1_RX_DMA_CHANNEL 5 165 | #define RTE_USART1_RX_DMA_PRIORITY 0 166 | // DMA Tx 167 | // Number <1=>1 168 | // Selects DMA Number (only DMA1 can be used) 169 | // Channel <4=>4 170 | // Selects DMA Channel (only Channel 4 can be used) 171 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 172 | // Set DMA Channel priority 173 | // 174 | #define RTE_USART1_TX_DMA 0 175 | #define RTE_USART1_TX_DMA_NUMBER 1 176 | #define RTE_USART1_TX_DMA_CHANNEL 4 177 | #define RTE_USART1_TX_DMA_PRIORITY 0 178 | // 179 | 180 | 181 | // USART2 (Universal synchronous asynchronous receiver transmitter) 182 | // Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART 183 | #define RTE_USART2 0 184 | 185 | // USART2_TX Pin <0=>PA2 186 | #define RTE_USART2_TX_PORT_ID_DEF 0 187 | #if (RTE_USART2_TX_PORT_ID_DEF == 0) 188 | #define RTE_USART2_TX_PORT_DEF GPIOA 189 | #define RTE_USART2_TX_BIT_DEF 2 190 | #else 191 | #error "Invalid USART2_TX Pin Configuration!" 192 | #endif 193 | 194 | // USART2_RX Pin <0=>PA3 195 | #define RTE_USART2_RX_PORT_ID_DEF 0 196 | #if (RTE_USART2_RX_PORT_ID_DEF == 0) 197 | #define RTE_USART2_RX_PORT_DEF GPIOA 198 | #define RTE_USART2_RX_BIT_DEF 3 199 | #else 200 | #error "Invalid USART2_RX Pin Configuration!" 201 | #endif 202 | 203 | // USART2_CK Pin <0=>Not Used <1=>PA4 204 | #define RTE_USART2_CK_PORT_ID_DEF 0 205 | #if (RTE_USART2_CK_PORT_ID_DEF == 0) 206 | #define RTE_USART2_CK 0 207 | #elif (RTE_USART2_CK_PORT_ID_DEF == 1) 208 | #define RTE_USART2_CK 1 209 | #define RTE_USART2_CK_PORT_DEF GPIOA 210 | #define RTE_USART2_CK_BIT_DEF 4 211 | #else 212 | #error "Invalid USART2_CK Pin Configuration!" 213 | #endif 214 | 215 | // USART2_CTS Pin <0=>Not Used<1=>PA0 216 | #define RTE_USART2_CTS_PORT_ID_DEF 0 217 | #if (RTE_USART2_CTS_PORT_ID_DEF == 0) 218 | #define RTE_USART2_CTS 0 219 | #elif (RTE_USART2_CTS_PORT_ID_DEF == 1) 220 | #define RTE_USART2_CTS 1 221 | #define RTE_USART2_CTS_PORT_DEF GPIOA 222 | #define RTE_USART2_CTS_BIT_DEF 0 223 | #else 224 | #error "Invalid USART2_CTS Pin Configuration!" 225 | #endif 226 | 227 | // USART2_RTS Pin <0=>Not Used <1=>PA1 228 | #define RTE_USART2_RTS_PORT_ID_DEF 0 229 | #if (RTE_USART2_RTS_PORT_ID_DEF == 0) 230 | #define RTE_USART2_RTS 0 231 | #elif (RTE_USART2_RTS_PORT_ID_DEF == 1) 232 | #define RTE_USART2_RTS 1 233 | #define RTE_USART2_RTS_PORT_DEF GPIOA 234 | #define RTE_USART2_RTS_BIT_DEF 1 235 | #else 236 | #error "Invalid USART2_RTS Pin Configuration!" 237 | #endif 238 | 239 | // USART2 Pin Remap 240 | // Enable USART2 Pin Remapping 241 | #define RTE_USART2_REMAP_FULL 0 242 | 243 | // USART2_TX Pin <0=>PD5 244 | #define RTE_USART2_TX_PORT_ID_FULL 0 245 | #if (RTE_USART2_TX_PORT_ID_FULL == 0) 246 | #define RTE_USART2_TX_PORT_FULL GPIOD 247 | #define RTE_USART2_TX_BIT_FULL 5 248 | #else 249 | #error "Invalid USART2_TX Pin Configuration!" 250 | #endif 251 | 252 | // USART2_RX Pin <0=>PD6 253 | #define RTE_USART2_RX_PORT_ID_FULL 0 254 | #if (RTE_USART2_RX_PORT_ID_FULL == 0) 255 | #define RTE_USART2_RX_PORT_FULL GPIOD 256 | #define RTE_USART2_RX_BIT_FULL 6 257 | #else 258 | #error "Invalid USART2_RX Pin Configuration!" 259 | #endif 260 | 261 | // USART3_CK Pin <0=>Not Used <1=>PD7 262 | #define RTE_USART2_CK_PORT_ID_FULL 0 263 | #if (RTE_USART2_CK_PORT_ID_FULL == 0) 264 | #define RTE_USART2_CK 0 265 | #elif (RTE_USART2_CK_PORT_ID_FULL == 1) 266 | #define RTE_USART2_CK 1 267 | #define RTE_USART2_CK_PORT_FULL GPIOD 268 | #define RTE_USART2_CK_BIT_FULL 7 269 | #else 270 | #error "Invalid USART2_CK Pin Configuration!" 271 | #endif 272 | 273 | // USART2_CTS Pin <0=>Not Used <1=>PD3 274 | #define RTE_USART2_CTS_PORT_ID_FULL 0 275 | #if (RTE_USART2_CTS_PORT_ID_FULL == 0) 276 | #define RTE_USART2_CTS 0 277 | #elif (RTE_USART2_CTS_PORT_ID_FULL == 1) 278 | #define RTE_USART2_CTS 1 279 | #define RTE_USART2_CTS_PORT_FULL GPIOD 280 | #define RTE_USART2_CTS_BIT_FULL 3 281 | #else 282 | #error "Invalid USART2_CTS Pin Configuration!" 283 | #endif 284 | 285 | // USART2_RTS Pin <0=>Not Used <1=>PD4 286 | #define RTE_USART2_RTS_PORT_ID_FULL 0 287 | #if (RTE_USART2_RTS_PORT_ID_FULL == 0) 288 | #define RTE_USART2_RTS 0 289 | #elif (RTE_USART2_RTS_PORT_ID_FULL == 1) 290 | #define RTE_USART2_RTS 1 291 | #define RTE_USART2_RTS_PORT_FULL GPIOD 292 | #define RTE_USART2_RTS_BIT_FULL 4 293 | #else 294 | #error "Invalid USART2_RTS Pin Configuration!" 295 | #endif 296 | // 297 | 298 | #if (RTE_USART2_REMAP_FULL) 299 | #define RTE_USART2_AF_REMAP AFIO_USART2_REMAP 300 | #define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_FULL 301 | #define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_FULL 302 | #define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_FULL 303 | #define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_FULL 304 | #define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_FULL 305 | #define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_FULL 306 | #define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_FULL 307 | #define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_FULL 308 | #define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_FULL 309 | #define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_FULL 310 | #else 311 | #define RTE_USART2_AF_REMAP AFIO_USART2_NO_REMAP 312 | #define RTE_USART2_TX_PORT RTE_USART2_TX_PORT_DEF 313 | #define RTE_USART2_TX_BIT RTE_USART2_TX_BIT_DEF 314 | #define RTE_USART2_RX_PORT RTE_USART2_RX_PORT_DEF 315 | #define RTE_USART2_RX_BIT RTE_USART2_RX_BIT_DEF 316 | #define RTE_USART2_CK_PORT RTE_USART2_CK_PORT_DEF 317 | #define RTE_USART2_CK_BIT RTE_USART2_CK_BIT_DEF 318 | #define RTE_USART2_CTS_PORT RTE_USART2_CTS_PORT_DEF 319 | #define RTE_USART2_CTS_BIT RTE_USART2_CTS_BIT_DEF 320 | #define RTE_USART2_RTS_PORT RTE_USART2_RTS_PORT_DEF 321 | #define RTE_USART2_RTS_BIT RTE_USART2_RTS_BIT_DEF 322 | #endif 323 | 324 | // DMA Rx 325 | // Number <1=>1 326 | // Selects DMA Number (only DMA1 can be used) 327 | // Channel <6=>6 328 | // Selects DMA Channel (only Channel 6 can be used) 329 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 330 | // Set DMA Channel priority 331 | // 332 | #define RTE_USART2_RX_DMA 0 333 | #define RTE_USART2_RX_DMA_NUMBER 1 334 | #define RTE_USART2_RX_DMA_CHANNEL 6 335 | #define RTE_USART2_RX_DMA_PRIORITY 0 336 | 337 | // DMA Tx 338 | // Number <1=>1 339 | // Selects DMA Number (only DMA1 can be used) 340 | // Channel <7=>7 341 | // Selects DMA Channel (only Channel 7 can be used) 342 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 343 | // Set DMA Channel priority 344 | // 345 | #define RTE_USART2_TX_DMA 0 346 | #define RTE_USART2_TX_DMA_NUMBER 1 347 | #define RTE_USART2_TX_DMA_CHANNEL 7 348 | #define RTE_USART2_TX_DMA_PRIORITY 0 349 | 350 | // 351 | 352 | 353 | // USART3 (Universal synchronous asynchronous receiver transmitter) 354 | // Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART 355 | #define RTE_USART3 0 356 | 357 | // USART3_TX Pin <0=>PB10 358 | #define RTE_USART3_TX_PORT_ID_DEF 0 359 | #if (RTE_USART3_TX_PORT_ID_DEF == 0) 360 | #define RTE_USART3_TX_PORT_DEF GPIOB 361 | #define RTE_USART3_TX_BIT_DEF 10 362 | #else 363 | #error "Invalid USART3_TX Pin Configuration!" 364 | #endif 365 | 366 | // USART3_RX Pin <0=>PB11 367 | #define RTE_USART3_RX_PORT_ID_DEF 0 368 | #if (RTE_USART3_RX_PORT_ID_DEF == 0) 369 | #define RTE_USART3_RX_PORT_DEF GPIOB 370 | #define RTE_USART3_RX_BIT_DEF 11 371 | #else 372 | #error "Invalid USART3_RX Pin Configuration!" 373 | #endif 374 | 375 | // USART3_CK Pin <0=>Not Used <1=>PB12 376 | #define RTE_USART3_CK_PORT_ID_DEF 0 377 | #if (RTE_USART3_CK_PORT_ID_DEF == 0) 378 | #define RTE_USART3_CK 0 379 | #elif (RTE_USART3_CK_PORT_ID_DEF == 1) 380 | #define RTE_USART3_CK 1 381 | #define RTE_USART3_CK_PORT_DEF GPIOB 382 | #define RTE_USART3_CK_BIT_DEF 12 383 | #else 384 | #error "Invalid USART3_CK Pin Configuration!" 385 | #endif 386 | 387 | // USART3_CTS Pin <0=>Not Used <1=>PB13 388 | #define RTE_USART3_CTS_PORT_ID_DEF 0 389 | #if (RTE_USART3_CTS_PORT_ID_DEF == 0) 390 | #define RTE_USART3_CTS 0 391 | #elif (RTE_USART3_CTS_PORT_ID_DEF == 1) 392 | #define RTE_USART3_CTS 1 393 | #define RTE_USART3_CTS_PORT_DEF GPIOB 394 | #define RTE_USART3_CTS_BIT_DEF 13 395 | #else 396 | #error "Invalid USART3_CTS Pin Configuration!" 397 | #endif 398 | 399 | // USART3_RTS Pin <0=>Not Used <1=>PB14 400 | #define RTE_USART3_RTS_PORT_ID_DEF 0 401 | #if (RTE_USART3_RTS_PORT_ID_DEF == 0) 402 | #define RTE_USART3_RTS 0 403 | #elif (RTE_USART3_RTS_PORT_ID_DEF == 1) 404 | #define RTE_USART3_RTS 1 405 | #define RTE_USART3_RTS_PORT_DEF GPIOB 406 | #define RTE_USART3_RTS_BIT_DEF 14 407 | #else 408 | #error "Invalid USART3_RTS Pin Configuration!" 409 | #endif 410 | 411 | // USART3 Partial Pin Remap 412 | // Enable USART3 Partial Pin Remapping 413 | #define RTE_USART3_REMAP_PARTIAL 0 414 | 415 | // USART3_TX Pin <0=>PC10 416 | #define RTE_USART3_TX_PORT_ID_PARTIAL 0 417 | #if (RTE_USART3_TX_PORT_ID_PARTIAL == 0) 418 | #define RTE_USART3_TX_PORT_PARTIAL GPIOC 419 | #define RTE_USART3_TX_BIT_PARTIAL 10 420 | #else 421 | #error "Invalid USART3_TX Pin Configuration!" 422 | #endif 423 | 424 | // USART3_RX Pin <0=>PC11 425 | #define RTE_USART3_RX_PORT_ID_PARTIAL 0 426 | #if (RTE_USART3_RX_PORT_ID_PARTIAL == 0) 427 | #define RTE_USART3_RX_PORT_PARTIAL GPIOC 428 | #define RTE_USART3_RX_BIT_PARTIAL 11 429 | #else 430 | #error "Invalid USART3_RX Pin Configuration!" 431 | #endif 432 | 433 | // USART3_CK Pin <0=>Not Used <1=>PC12 434 | #define RTE_USART3_CK_PORT_ID_PARTIAL 0 435 | #if (RTE_USART3_CK_PORT_ID_PARTIAL == 0) 436 | #define RTE_USART3_CK 0 437 | #elif (RTE_USART3_CK_PORT_ID_PARTIAL == 1) 438 | #define RTE_USART3_CK 1 439 | #define RTE_USART3_CK_PORT_PARTIAL GPIOC 440 | #define RTE_USART3_CK_BIT_PARTIAL 12 441 | #else 442 | #error "Invalid USART3_CK Pin Configuration!" 443 | #endif 444 | // 445 | 446 | // USART3 Full Pin Remap 447 | // Enable USART3 Full Pin Remapping 448 | #define RTE_USART3_REMAP_FULL 0 449 | 450 | // USART3_TX Pin <0=>PD8 451 | #define RTE_USART3_TX_PORT_ID_FULL 0 452 | #if (RTE_USART3_TX_PORT_ID_FULL == 0) 453 | #define RTE_USART3_TX_PORT_FULL GPIOD 454 | #define RTE_USART3_TX_BIT_FULL 8 455 | #else 456 | #error "Invalid USART3_TX Pin Configuration!" 457 | #endif 458 | 459 | // USART3_RX Pin <0=>PD9 460 | #define RTE_USART3_RX_PORT_ID_FULL 0 461 | #if (RTE_USART3_RX_PORT_ID_FULL == 0) 462 | #define RTE_USART3_RX_PORT_FULL GPIOD 463 | #define RTE_USART3_RX_BIT_FULL 9 464 | #else 465 | #error "Invalid USART3_RX Pin Configuration!" 466 | #endif 467 | 468 | // USART3_CK Pin <0=>Not Used <1=>PD10 469 | #define RTE_USART3_CK_PORT_ID_FULL 0 470 | #if (RTE_USART3_CK_PORT_ID_FULL == 0) 471 | #define RTE_USART3_CK 0 472 | #elif (RTE_USART3_CK_PORT_ID_FULL == 1) 473 | #define RTE_USART3_CK 1 474 | #define RTE_USART3_CK_PORT_FULL GPIOD 475 | #define RTE_USART3_CK_BIT_FULL 10 476 | #else 477 | #error "Invalid USART3_CK Pin Configuration!" 478 | #endif 479 | 480 | // USART3_CTS Pin <0=>Not Used <1=>PD11 481 | #define RTE_USART3_CTS_PORT_ID_FULL 0 482 | #if (RTE_USART3_CTS_PORT_ID_FULL == 0) 483 | #define RTE_USART3_CTS 0 484 | #elif (RTE_USART3_CTS_PORT_ID_FULL == 1) 485 | #define RTE_USART3_CTS 1 486 | #define RTE_USART3_CTS_PORT_FULL GPIOD 487 | #define RTE_USART3_CTS_BIT_FULL 11 488 | #else 489 | #error "Invalid USART3_CTS Pin Configuration!" 490 | #endif 491 | 492 | // USART3_RTS Pin <0=>Not Used <1=>PD12 493 | #define RTE_USART3_RTS_PORT_ID_FULL 0 494 | #if (RTE_USART3_RTS_PORT_ID_FULL == 0) 495 | #define RTE_USART3_RTS 0 496 | #elif (RTE_USART3_RTS_PORT_ID_FULL == 1) 497 | #define RTE_USART3_RTS 1 498 | #define RTE_USART3_RTS_PORT_FULL GPIOD 499 | #define RTE_USART3_RTS_BIT_FULL 12 500 | #else 501 | #error "Invalid USART3_RTS Pin Configuration!" 502 | #endif 503 | // 504 | 505 | #if ((RTE_USART3_REMAP_PARTIAL == 1) && (RTE_USART3_REMAP_FULL == 1)) 506 | #error "Invalid USART3 Pin Remap Configuration!" 507 | #endif 508 | 509 | #if (RTE_USART3_REMAP_FULL) 510 | #define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_FULL 511 | #define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_FULL 512 | #define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_FULL 513 | #define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_FULL 514 | #define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_FULL 515 | #define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_FULL 516 | #define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_FULL 517 | #define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_FULL 518 | #define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_FULL 519 | #define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_FULL 520 | #define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_FULL 521 | #elif (RTE_USART3_REMAP_PARTIAL) 522 | #define RTE_USART3_AF_REMAP AFIO_USART3_REMAP_PARTIAL 523 | #define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_PARTIAL 524 | #define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_PARTIAL 525 | #define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_PARTIAL 526 | #define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_PARTIAL 527 | #define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_PARTIAL 528 | #define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_PARTIAL 529 | #define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF 530 | #define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF 531 | #define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF 532 | #define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF 533 | #else 534 | #define RTE_USART3_AF_REMAP AFIO_USART3_NO_REMAP 535 | #define RTE_USART3_TX_PORT RTE_USART3_TX_PORT_DEF 536 | #define RTE_USART3_TX_BIT RTE_USART3_TX_BIT_DEF 537 | #define RTE_USART3_RX_PORT RTE_USART3_RX_PORT_DEF 538 | #define RTE_USART3_RX_BIT RTE_USART3_RX_BIT_DEF 539 | #define RTE_USART3_CK_PORT RTE_USART3_CK_PORT_DEF 540 | #define RTE_USART3_CK_BIT RTE_USART3_CK_BIT_DEF 541 | #define RTE_USART3_CTS_PORT RTE_USART3_CTS_PORT_DEF 542 | #define RTE_USART3_CTS_BIT RTE_USART3_CTS_BIT_DEF 543 | #define RTE_USART3_RTS_PORT RTE_USART3_RTS_PORT_DEF 544 | #define RTE_USART3_RTS_BIT RTE_USART3_RTS_BIT_DEF 545 | #endif 546 | 547 | // DMA Rx 548 | // Number <1=>1 549 | // Selects DMA Number (only DMA1 can be used) 550 | // Channel <3=>3 551 | // Selects DMA Channel (only Channel 3 can be used) 552 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 553 | // Sets DMA Channel priority 554 | // 555 | #define RTE_USART3_RX_DMA 0 556 | #define RTE_USART3_RX_DMA_NUMBER 1 557 | #define RTE_USART3_RX_DMA_CHANNEL 3 558 | #define RTE_USART3_RX_DMA_PRIORITY 0 559 | 560 | // DMA Tx 561 | // Number <1=>1 562 | // Selects DMA Number (only DMA1 can be used) 563 | // Channel <2=>2 564 | // Selects DMA Channel (only Channel 2 can be used) 565 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 566 | // Sets DMA Channel priority 567 | // 568 | #define RTE_USART3_TX_DMA 0 569 | #define RTE_USART3_TX_DMA_NUMBER 1 570 | #define RTE_USART3_TX_DMA_CHANNEL 2 571 | #define RTE_USART3_TX_DMA_PRIORITY 0 572 | 573 | // 574 | 575 | 576 | // UART4 (Universal asynchronous receiver transmitter) 577 | // Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART 578 | #define RTE_UART4 0 579 | #define RTE_UART4_AF_REMAP AFIO_UNAVAILABLE_REMAP 580 | 581 | // UART4_TX Pin <0=>PC10 582 | #define RTE_UART4_TX_ID 0 583 | #if (RTE_UART4_TX_ID == 0) 584 | #define RTE_UART4_TX_PORT GPIOC 585 | #define RTE_UART4_TX_BIT 10 586 | #else 587 | #error "Invalid UART4_TX Pin Configuration!" 588 | #endif 589 | 590 | // UART4_RX Pin <0=>PC11 591 | #define RTE_UART4_RX_ID 0 592 | #if (RTE_UART4_RX_ID == 0) 593 | #define RTE_UART4_RX_PORT GPIOC 594 | #define RTE_UART4_RX_BIT 11 595 | #else 596 | #error "Invalid UART4_RX Pin Configuration!" 597 | #endif 598 | 599 | 600 | // DMA Rx 601 | // Number <2=>2 602 | // Selects DMA Number (only DMA2 can be used) 603 | // Channel <3=>3 604 | // Selects DMA Channel (only Channel 3 can be used) 605 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 606 | // Sets DMA Channel priority 607 | // 608 | #define RTE_UART4_RX_DMA 0 609 | #define RTE_UART4_RX_DMA_NUMBER 2 610 | #define RTE_UART4_RX_DMA_CHANNEL 3 611 | #define RTE_UART4_RX_DMA_PRIORITY 0 612 | 613 | // DMA Tx 614 | // Number <2=>2 615 | // Selects DMA Number (only DMA2 can be used) 616 | // Channel <5=>5 617 | // Selects DMA Channel (only Channel 5 can be used) 618 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very high 619 | // Sets DMA Channel priority 620 | // 621 | #define RTE_UART4_TX_DMA 0 622 | #define RTE_UART4_TX_DMA_NUMBER 2 623 | #define RTE_UART4_TX_DMA_CHANNEL 5 624 | #define RTE_UART4_TX_DMA_PRIORITY 0 625 | 626 | // 627 | 628 | 629 | // UART5 (Universal asynchronous receiver transmitter) 630 | // Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART 631 | #define RTE_UART5 0 632 | #define RTE_UART5_AF_REMAP AFIO_UNAVAILABLE_REMAP 633 | 634 | // UART5_TX Pin <0=>PC12 635 | #define RTE_UART5_TX_ID 0 636 | #if (RTE_UART5_TX_ID == 0) 637 | #define RTE_UART5_TX_PORT GPIOC 638 | #define RTE_UART5_TX_BIT 12 639 | #else 640 | #error "Invalid UART5_TX Pin Configuration!" 641 | #endif 642 | 643 | // UART5_RX Pin <0=>PD2 644 | #define RTE_UART5_RX_ID 0 645 | #if (RTE_UART5_RX_ID == 0) 646 | #define RTE_UART5_RX_PORT GPIOD 647 | #define RTE_UART5_RX_BIT 2 648 | #else 649 | #error "Invalid UART5_RX Pin Configuration!" 650 | #endif 651 | // 652 | 653 | 654 | // I2C1 (Inter-integrated Circuit Interface 1) 655 | // Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C 656 | #define RTE_I2C1 0 657 | 658 | // I2C1_SCL Pin <0=>PB6 659 | #define RTE_I2C1_SCL_PORT_ID_DEF 0 660 | #if (RTE_I2C1_SCL_PORT_ID_DEF == 0) 661 | #define RTE_I2C1_SCL_PORT_DEF GPIOB 662 | #define RTE_I2C1_SCL_BIT_DEF 6 663 | #else 664 | #error "Invalid I2C1_SCL Pin Configuration!" 665 | #endif 666 | 667 | // I2C1_SDA Pin <0=>PB7 668 | #define RTE_I2C1_SDA_PORT_ID_DEF 0 669 | #if (RTE_I2C1_SDA_PORT_ID_DEF == 0) 670 | #define RTE_I2C1_SDA_PORT_DEF GPIOB 671 | #define RTE_I2C1_SDA_BIT_DEF 7 672 | #else 673 | #error "Invalid I2C1_SCL Pin Configuration!" 674 | #endif 675 | 676 | // I2C1 Pin Remap 677 | // Enable I2C1 Pin Remapping 678 | #define RTE_I2C1_REMAP_FULL 0 679 | 680 | // I2C1_SCL Pin <0=>PB8 681 | #define RTE_I2C1_SCL_PORT_ID_FULL 0 682 | #if (RTE_I2C1_SCL_PORT_ID_FULL == 0) 683 | #define RTE_I2C1_SCL_PORT_FULL GPIOB 684 | #define RTE_I2C1_SCL_BIT_FULL 8 685 | #else 686 | #error "Invalid I2C1_SCL Pin Configuration!" 687 | #endif 688 | 689 | // I2C1_SDA Pin <0=>PB9 690 | #define RTE_I2C1_SDA_PORT_ID_FULL 0 691 | #if (RTE_I2C1_SDA_PORT_ID_FULL == 0) 692 | #define RTE_I2C1_SDA_PORT_FULL GPIOB 693 | #define RTE_I2C1_SDA_BIT_FULL 9 694 | #else 695 | #error "Invalid I2C1_SCL Pin Configuration!" 696 | #endif 697 | 698 | // 699 | 700 | #if (RTE_I2C1_REMAP_FULL) 701 | #define RTE_I2C1_AF_REMAP AFIO_I2C1_REMAP 702 | #define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_FULL 703 | #define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_FULL 704 | #define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_FULL 705 | #define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_FULL 706 | #else 707 | #define RTE_I2C1_AF_REMAP AFIO_I2C1_NO_REMAP 708 | #define RTE_I2C1_SCL_PORT RTE_I2C1_SCL_PORT_DEF 709 | #define RTE_I2C1_SCL_BIT RTE_I2C1_SCL_BIT_DEF 710 | #define RTE_I2C1_SDA_PORT RTE_I2C1_SDA_PORT_DEF 711 | #define RTE_I2C1_SDA_BIT RTE_I2C1_SDA_BIT_DEF 712 | #endif 713 | 714 | 715 | // DMA Rx 716 | // Number <1=>1 717 | // Selects DMA Number (only DMA1 can be used) 718 | // Channel <7=>7 719 | // Selects DMA Channel (only Channel 7 can be used) 720 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 721 | // Selects DMA Priority 722 | // 723 | #define RTE_I2C1_RX_DMA 0 724 | #define RTE_I2C1_RX_DMA_NUMBER 1 725 | #define RTE_I2C1_RX_DMA_CHANNEL 7 726 | #define RTE_I2C1_RX_DMA_PRIORITY 0 727 | 728 | // DMA Tx 729 | // Number <1=>1 730 | // Selects DMA Number (only DMA1 can be used) 731 | // Channel <6=>6 732 | // Selects DMA Channel (only Channel 6 can be used) 733 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 734 | // Selects DMA Priority 735 | // 736 | #define RTE_I2C1_TX_DMA 0 737 | #define RTE_I2C1_TX_DMA_NUMBER 1 738 | #define RTE_I2C1_TX_DMA_CHANNEL 6 739 | #define RTE_I2C1_TX_DMA_PRIORITY 0 740 | 741 | // 742 | 743 | 744 | // I2C2 (Inter-integrated Circuit Interface 2) 745 | // Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C 746 | #define RTE_I2C2 0 747 | #define RTE_I2C2_AF_REMAP AFIO_UNAVAILABLE_REMAP 748 | 749 | // I2C2_SCL Pin <0=>PB10 750 | #define RTE_I2C2_SCL_PORT_ID 0 751 | #if (RTE_I2C2_SCL_PORT_ID == 0) 752 | #define RTE_I2C2_SCL_PORT GPIOB 753 | #define RTE_I2C2_SCL_BIT 10 754 | #else 755 | #error "Invalid I2C2_SCL Pin Configuration!" 756 | #endif 757 | 758 | // I2C2_SDA Pin <0=>PB11 759 | #define RTE_I2C2_SDA_PORT_ID 0 760 | #if (RTE_I2C2_SDA_PORT_ID == 0) 761 | #define RTE_I2C2_SDA_PORT GPIOB 762 | #define RTE_I2C2_SDA_BIT 11 763 | #else 764 | #error "Invalid I2C2_SCL Pin Configuration!" 765 | #endif 766 | 767 | // DMA Rx 768 | // Number <1=>1 769 | // Selects DMA Number (only DMA1 can be used) 770 | // Channel <5=>5 771 | // Selects DMA Channel (only Channel 5 can be used) 772 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 773 | // Selects DMA Priority 774 | // 775 | #define RTE_I2C2_RX_DMA 1 776 | #define RTE_I2C2_RX_DMA_NUMBER 1 777 | #define RTE_I2C2_RX_DMA_CHANNEL 5 778 | #define RTE_I2C2_RX_DMA_PRIORITY 0 779 | 780 | // DMA Tx 781 | // Number <1=>1 782 | // Selects DMA Number (only DMA1 can be used) 783 | // Channel <4=>4 784 | // Selects DMA Channel (only Channel 4 can be used) 785 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 786 | // Selects DMA Priority 787 | // 788 | #define RTE_I2C2_TX_DMA 1 789 | #define RTE_I2C2_TX_DMA_NUMBER 1 790 | #define RTE_I2C2_TX_DMA_CHANNEL 4 791 | #define RTE_I2C2_TX_DMA_PRIORITY 0 792 | 793 | // 794 | 795 | 796 | // SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] 797 | // Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI 798 | #define RTE_SPI1 0 799 | 800 | // SPI1_NSS Pin 801 | // Configure Pin if exists 802 | // GPIO Pxy (x = A..G, y = 0..15) 803 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 804 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 805 | // Selects Port Name 806 | // Bit <0-15> 807 | // Selects Port Bit 808 | // 809 | #define RTE_SPI1_NSS_PIN 1 810 | #define RTE_SPI1_NSS_PORT GPIO_PORT(0) 811 | #define RTE_SPI1_NSS_BIT 4 812 | 813 | // SPI1_SCK Pin <0=>PA5 814 | #define RTE_SPI1_SCK_PORT_ID_DEF 0 815 | #if (RTE_SPI1_SCK_PORT_ID_DEF == 0) 816 | #define RTE_SPI1_SCK_PORT_DEF GPIOA 817 | #define RTE_SPI1_SCK_BIT_DEF 5 818 | #else 819 | #error "Invalid SPI1_SCK Pin Configuration!" 820 | #endif 821 | 822 | // SPI1_MISO Pin <0=>PA6 823 | #define RTE_SPI1_MISO_PORT_ID_DEF 0 824 | #if (RTE_SPI1_MISO_PORT_ID_DEF == 0) 825 | #define RTE_SPI1_MISO_PORT_DEF GPIOA 826 | #define RTE_SPI1_MISO_BIT_DEF 6 827 | #else 828 | #error "Invalid SPI1_MISO Pin Configuration!" 829 | #endif 830 | 831 | // SPI1_MOSI Pin <0=>PA7 832 | #define RTE_SPI1_MOSI_PORT_ID_DEF 0 833 | #if (RTE_SPI1_MOSI_PORT_ID_DEF == 0) 834 | #define RTE_SPI1_MOSI_PORT_DEF GPIOA 835 | #define RTE_SPI1_MOSI_BIT_DEF 7 836 | #else 837 | #error "Invalid SPI1_MISO Pin Configuration!" 838 | #endif 839 | 840 | // SPI1 Pin Remap 841 | // Enable SPI1 Pin Remapping. 842 | #define RTE_SPI1_REMAP 0 843 | 844 | // SPI1_SCK Pin <0=>PB3 845 | #define RTE_SPI1_SCK_PORT_ID_FULL 0 846 | #if (RTE_SPI1_SCK_PORT_ID_FULL == 0) 847 | #define RTE_SPI1_SCK_PORT_FULL GPIOB 848 | #define RTE_SPI1_SCK_BIT_FULL 3 849 | #else 850 | #error "Invalid SPI1_SCK Pin Configuration!" 851 | #endif 852 | 853 | // SPI1_MISO Pin <0=>PB4 854 | #define RTE_SPI1_MISO_PORT_ID_FULL 0 855 | #if (RTE_SPI1_MISO_PORT_ID_FULL == 0) 856 | #define RTE_SPI1_MISO_PORT_FULL GPIOB 857 | #define RTE_SPI1_MISO_BIT_FULL 4 858 | #else 859 | #error "Invalid SPI1_MISO Pin Configuration!" 860 | #endif 861 | // SPI1_MOSI Pin <0=>PB5 862 | #define RTE_SPI1_MOSI_PORT_ID_FULL 0 863 | #if (RTE_SPI1_MOSI_PORT_ID_FULL == 0) 864 | #define RTE_SPI1_MOSI_PORT_FULL GPIOB 865 | #define RTE_SPI1_MOSI_BIT_FULL 5 866 | #else 867 | #error "Invalid SPI1_MOSI Pin Configuration!" 868 | #endif 869 | 870 | // 871 | 872 | #if (RTE_SPI1_REMAP) 873 | #define RTE_SPI1_AF_REMAP AFIO_SPI1_REMAP 874 | #define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_FULL 875 | #define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_FULL 876 | #define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_FULL 877 | #define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_FULL 878 | #define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_FULL 879 | #define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_FULL 880 | #else 881 | #define RTE_SPI1_AF_REMAP AFIO_SPI1_NO_REMAP 882 | #define RTE_SPI1_SCK_PORT RTE_SPI1_SCK_PORT_DEF 883 | #define RTE_SPI1_SCK_BIT RTE_SPI1_SCK_BIT_DEF 884 | #define RTE_SPI1_MISO_PORT RTE_SPI1_MISO_PORT_DEF 885 | #define RTE_SPI1_MISO_BIT RTE_SPI1_MISO_BIT_DEF 886 | #define RTE_SPI1_MOSI_PORT RTE_SPI1_MOSI_PORT_DEF 887 | #define RTE_SPI1_MOSI_BIT RTE_SPI1_MOSI_BIT_DEF 888 | #endif 889 | 890 | // DMA Rx 891 | // Number <1=>1 892 | // Selects DMA Number (only DMA1 can be used) 893 | // Channel <2=>2 894 | // Selects DMA Channel (only Channel 2 can be used) 895 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 896 | // Selects DMA Priority 897 | // 898 | #define RTE_SPI1_RX_DMA 0 899 | #define RTE_SPI1_RX_DMA_NUMBER 1 900 | #define RTE_SPI1_RX_DMA_CHANNEL 2 901 | #define RTE_SPI1_RX_DMA_PRIORITY 0 902 | 903 | // DMA Tx 904 | // Number <1=>1 905 | // Selects DMA Number (only DMA1 can be used) 906 | // Channel <3=>3 907 | // Selects DMA Channel (only Channel 3 can be used) 908 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 909 | // Selects DMA Priority 910 | // 911 | #define RTE_SPI1_TX_DMA 0 912 | #define RTE_SPI1_TX_DMA_NUMBER 1 913 | #define RTE_SPI1_TX_DMA_CHANNEL 3 914 | #define RTE_SPI1_TX_DMA_PRIORITY 0 915 | 916 | // 917 | 918 | 919 | // SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] 920 | // Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI 921 | #define RTE_SPI2 0 922 | 923 | // SPI2_NSS Pin 924 | // Configure Pin if exists 925 | // GPIO Pxy (x = A..G, y = 0..15) 926 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 927 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 928 | // Selects Port Name 929 | // Bit <0-15> 930 | // Selects Port Bit 931 | // 932 | #define RTE_SPI2_NSS_PIN 1 933 | #define RTE_SPI2_NSS_PORT GPIO_PORT(1) 934 | #define RTE_SPI2_NSS_BIT 12 935 | 936 | // SPI2_SCK Pin <0=>PB13 937 | #define RTE_SPI2_SCK_PORT_ID 0 938 | #if (RTE_SPI2_SCK_PORT_ID == 0) 939 | #define RTE_SPI2_SCK_PORT GPIOB 940 | #define RTE_SPI2_SCK_BIT 13 941 | #define RTE_SPI2_SCK_REMAP 0 942 | #else 943 | #error "Invalid SPI2_SCK Pin Configuration!" 944 | #endif 945 | 946 | // SPI2_MISO Pin <0=>PB14 947 | #define RTE_SPI2_MISO_PORT_ID 0 948 | #if (RTE_SPI2_MISO_PORT_ID == 0) 949 | #define RTE_SPI2_MISO_PORT GPIOB 950 | #define RTE_SPI2_MISO_BIT 14 951 | #define RTE_SPI2_MISO_REMAP 0 952 | #else 953 | #error "Invalid SPI2_MISO Pin Configuration!" 954 | #endif 955 | 956 | // SPI2_MOSI Pin <0=>PB15 957 | #define RTE_SPI2_MOSI_PORT_ID 0 958 | #if (RTE_SPI2_MOSI_PORT_ID == 0) 959 | #define RTE_SPI2_MOSI_PORT GPIOB 960 | #define RTE_SPI2_MOSI_BIT 15 961 | #define RTE_SPI2_MOSI_REMAP 0 962 | #else 963 | #error "Invalid SPI2_MISO Pin Configuration!" 964 | #endif 965 | 966 | // DMA Rx 967 | // Number <1=>1 968 | // Selects DMA Number (only DMA1 can be used) 969 | // Channel <4=>4 970 | // Selects DMA Channel (only Channel 4 can be used) 971 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 972 | // Selects DMA Priority 973 | // 974 | #define RTE_SPI2_RX_DMA 0 975 | #define RTE_SPI2_RX_DMA_NUMBER 1 976 | #define RTE_SPI2_RX_DMA_CHANNEL 4 977 | #define RTE_SPI2_RX_DMA_PRIORITY 0 978 | 979 | // DMA Tx 980 | // Number <1=>1 981 | // Selects DMA Number (only DMA1 can be used) 982 | // Channel <5=>5 983 | // Selects DMA Channel (only Channel 5 can be used) 984 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 985 | // Selects DMA Priority 986 | // 987 | #define RTE_SPI2_TX_DMA 0 988 | #define RTE_SPI2_TX_DMA_NUMBER 1 989 | #define RTE_SPI2_TX_DMA_CHANNEL 5 990 | #define RTE_SPI2_TX_DMA_PRIORITY 0 991 | 992 | // 993 | 994 | 995 | // SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] 996 | // Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI 997 | #define RTE_SPI3 0 998 | 999 | // SPI3_NSS Pin 1000 | // Configure Pin if exists 1001 | // GPIO Pxy (x = A..G, y = 0..15) 1002 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 1003 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 1004 | // Selects Port Name 1005 | // Bit <0-15> 1006 | // Selects Port Bit 1007 | // 1008 | #define RTE_SPI3_NSS_PIN 1 1009 | #define RTE_SPI3_NSS_PORT GPIO_PORT(0) 1010 | #define RTE_SPI3_NSS_BIT 15 1011 | 1012 | // SPI3_SCK Pin <0=>PB3 1013 | #define RTE_SPI3_SCK_PORT_ID_DEF 0 1014 | #if (RTE_SPI3_SCK_PORT_ID_DEF == 0) 1015 | #define RTE_SPI3_SCK_PORT_DEF GPIOB 1016 | #define RTE_SPI3_SCK_BIT_DEF 3 1017 | #else 1018 | #error "Invalid SPI3_SCK Pin Configuration!" 1019 | #endif 1020 | 1021 | // SPI3_MISO Pin <0=>PB4 1022 | #define RTE_SPI3_MISO_PORT_ID_DEF 0 1023 | #if (RTE_SPI3_MISO_PORT_ID_DEF == 0) 1024 | #define RTE_SPI3_MISO_PORT_DEF GPIOB 1025 | #define RTE_SPI3_MISO_BIT_DEF 4 1026 | #else 1027 | #error "Invalid SPI3_MISO Pin Configuration!" 1028 | #endif 1029 | 1030 | // SPI3_MOSI Pin <0=>PB5 1031 | #define RTE_SPI3_MOSI_PORT_ID_DEF 0 1032 | #if (RTE_SPI3_MOSI_PORT_ID_DEF == 0) 1033 | #define RTE_SPI3_MOSI_PORT_DEF GPIOB 1034 | #define RTE_SPI3_MOSI_BIT_DEF 5 1035 | #else 1036 | #error "Invalid SPI3_MOSI Pin Configuration!" 1037 | #endif 1038 | 1039 | // SPI3 Pin Remap 1040 | // Enable SPI3 Pin Remapping. 1041 | // SPI 3 Pin Remapping is available only in connectivity line devices! 1042 | #define RTE_SPI3_REMAP 0 1043 | 1044 | // SPI3_SCK Pin <0=>PC10 1045 | #define RTE_SPI3_SCK_PORT_ID_FULL 0 1046 | #if (RTE_SPI3_SCK_PORT_ID_FULL == 0) 1047 | #define RTE_SPI3_SCK_PORT_FULL GPIOC 1048 | #define RTE_SPI3_SCK_BIT_FULL 10 1049 | #else 1050 | #error "Invalid SPI3_SCK Pin Configuration!" 1051 | #endif 1052 | 1053 | // SPI3_MISO Pin <0=>PC11 1054 | #define RTE_SPI3_MISO_PORT_ID_FULL 0 1055 | #if (RTE_SPI3_MISO_PORT_ID_FULL == 0) 1056 | #define RTE_SPI3_MISO_PORT_FULL GPIOC 1057 | #define RTE_SPI3_MISO_BIT_FULL 11 1058 | #else 1059 | #error "Invalid SPI3_MISO Pin Configuration!" 1060 | #endif 1061 | // SPI3_MOSI Pin <0=>PC12 1062 | #define RTE_SPI3_MOSI_PORT_ID_FULL 0 1063 | #if (RTE_SPI3_MOSI_PORT_ID_FULL == 0) 1064 | #define RTE_SPI3_MOSI_PORT_FULL GPIOC 1065 | #define RTE_SPI3_MOSI_BIT_FULL 12 1066 | #else 1067 | #error "Invalid SPI3_MOSI Pin Configuration!" 1068 | #endif 1069 | 1070 | // 1071 | 1072 | #if (RTE_SPI3_REMAP) 1073 | #define RTE_SPI3_AF_REMAP AFIO_SPI3_REMAP 1074 | #define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_FULL 1075 | #define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_FULL 1076 | #define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_FULL 1077 | #define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_FULL 1078 | #define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_FULL 1079 | #define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_FULL 1080 | #else 1081 | #define RTE_SPI3_AF_REMAP AFIO_SPI3_NO_REMAP 1082 | #define RTE_SPI3_SCK_PORT RTE_SPI3_SCK_PORT_DEF 1083 | #define RTE_SPI3_SCK_BIT RTE_SPI3_SCK_BIT_DEF 1084 | #define RTE_SPI3_MISO_PORT RTE_SPI3_MISO_PORT_DEF 1085 | #define RTE_SPI3_MISO_BIT RTE_SPI3_MISO_BIT_DEF 1086 | #define RTE_SPI3_MOSI_PORT RTE_SPI3_MOSI_PORT_DEF 1087 | #define RTE_SPI3_MOSI_BIT RTE_SPI3_MOSI_BIT_DEF 1088 | #endif 1089 | 1090 | // DMA Rx 1091 | // Number <2=>2 1092 | // Selects DMA Number (only DMA2 can be used) 1093 | // Channel <1=>1 1094 | // Selects DMA Channel (only Channel 1 can be used) 1095 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 1096 | // Selects DMA Priority 1097 | // 1098 | #define RTE_SPI3_RX_DMA 0 1099 | #define RTE_SPI3_RX_DMA_NUMBER 2 1100 | #define RTE_SPI3_RX_DMA_CHANNEL 1 1101 | #define RTE_SPI3_RX_DMA_PRIORITY 0 1102 | 1103 | // DMA Tx 1104 | // Number <2=>2 1105 | // Selects DMA Number (only DMA2 can be used) 1106 | // Channel <2=>2 1107 | // Selects DMA Channel (only Channel 2 can be used) 1108 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 1109 | // Selects DMA Priority 1110 | // 1111 | #define RTE_SPI3_TX_DMA 0 1112 | #define RTE_SPI3_TX_DMA_NUMBER 2 1113 | #define RTE_SPI3_TX_DMA_CHANNEL 2 1114 | #define RTE_SPI3_TX_DMA_PRIORITY 0 1115 | 1116 | // 1117 | 1118 | 1119 | // SDIO (Secure Digital Input/Output) [Driver_MCI0] 1120 | // Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI 1121 | #define RTE_SDIO 0 1122 | 1123 | // SDIO Peripheral Bus 1124 | // SDIO_CK Pin <0=>PC12 1125 | #define RTE_SDIO_CK_PORT_ID 0 1126 | #if (RTE_SDIO_CK_PORT_ID == 0) 1127 | #define RTE_SDIO_CK_PORT GPIOC 1128 | #define RTE_SDIO_CK_PIN 12 1129 | #else 1130 | #error "Invalid SDIO_CLK Pin Configuration!" 1131 | #endif 1132 | // SDIO_CMD Pin <0=>PD2 1133 | #define RTE_SDIO_CMD_PORT_ID 0 1134 | #if (RTE_SDIO_CMD_PORT_ID == 0) 1135 | #define RTE_SDIO_CMD_PORT GPIOD 1136 | #define RTE_SDIO_CMD_PIN 2 1137 | #else 1138 | #error "Invalid SDIO_CMD Pin Configuration!" 1139 | #endif 1140 | // SDIO_D0 Pin <0=>PC8 1141 | #define RTE_SDIO_D0_PORT_ID 0 1142 | #if (RTE_SDIO_D0_PORT_ID == 0) 1143 | #define RTE_SDIO_D0_PORT GPIOC 1144 | #define RTE_SDIO_D0_PIN 8 1145 | #else 1146 | #error "Invalid SDIO_DAT0 Pin Configuration!" 1147 | #endif 1148 | // SDIO_D[1 .. 3] 1149 | #define RTE_SDIO_BUS_WIDTH_4 1 1150 | // SDIO_D1 Pin <0=>PC9 1151 | #define RTE_SDIO_D1_PORT_ID 0 1152 | #if (RTE_SDIO_D1_PORT_ID == 0) 1153 | #define RTE_SDIO_D1_PORT GPIOC 1154 | #define RTE_SDIO_D1_PIN 9 1155 | #else 1156 | #error "Invalid SDIO_D1 Pin Configuration!" 1157 | #endif 1158 | // SDIO_D2 Pin <0=>PC10 1159 | #define RTE_SDIO_D2_PORT_ID 0 1160 | #if (RTE_SDIO_D2_PORT_ID == 0) 1161 | #define RTE_SDIO_D2_PORT GPIOC 1162 | #define RTE_SDIO_D2_PIN 10 1163 | #else 1164 | #error "Invalid SDIO_D2 Pin Configuration!" 1165 | #endif 1166 | // SDIO_D3 Pin <0=>PC11 1167 | #define RTE_SDIO_D3_PORT_ID 0 1168 | #if (RTE_SDIO_D3_PORT_ID == 0) 1169 | #define RTE_SDIO_D3_PORT GPIOC 1170 | #define RTE_SDIO_D3_PIN 11 1171 | #else 1172 | #error "Invalid SDIO_D3 Pin Configuration!" 1173 | #endif 1174 | // SDIO_D[1 .. 3] 1175 | // SDIO_D[4 .. 7] 1176 | #define RTE_SDIO_BUS_WIDTH_8 0 1177 | // SDIO_D4 Pin <0=>PB8 1178 | #define RTE_SDIO_D4_PORT_ID 0 1179 | #if (RTE_SDIO_D4_PORT_ID == 0) 1180 | #define RTE_SDIO_D4_PORT GPIOB 1181 | #define RTE_SDIO_D4_PIN 8 1182 | #else 1183 | #error "Invalid SDIO_D4 Pin Configuration!" 1184 | #endif 1185 | // SDIO_D5 Pin <0=>PB9 1186 | #define RTE_SDIO_D5_PORT_ID 0 1187 | #if (RTE_SDIO_D5_PORT_ID == 0) 1188 | #define RTE_SDIO_D5_PORT GPIOB 1189 | #define RTE_SDIO_D5_PIN 9 1190 | #else 1191 | #error "Invalid SDIO_D5 Pin Configuration!" 1192 | #endif 1193 | // SDIO_D6 Pin <0=>PC6 1194 | #define RTE_SDIO_D6_PORT_ID 0 1195 | #if (RTE_SDIO_D6_PORT_ID == 0) 1196 | #define RTE_SDIO_D6_PORT GPIOC 1197 | #define RTE_SDIO_D6_PIN 6 1198 | #else 1199 | #error "Invalid SDIO_D6 Pin Configuration!" 1200 | #endif 1201 | // SDIO_D7 Pin <0=>PC7 1202 | #define RTE_SDIO_D7_PORT_ID 0 1203 | #if (RTE_SDIO_D7_PORT_ID == 0) 1204 | #define RTE_SDIO_D7_PORT GPIOC 1205 | #define RTE_SDIO_D7_PIN 7 1206 | #else 1207 | #error "Invalid SDIO_D7 Pin Configuration!" 1208 | #endif 1209 | // SDIO_D[4 .. 7] 1210 | // SDIO Peripheral Bus 1211 | 1212 | // Card Detect Pin 1213 | // Configure Pin if exists 1214 | // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) 1215 | // Active State <0=>Low <1=>High 1216 | // Selects Active State Logical Level 1217 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 1218 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 1219 | // Selects Port Name 1220 | // Bit <0-15> 1221 | // Selects Port Bit 1222 | // 1223 | #define RTE_SDIO_CD_EN 1 1224 | #define RTE_SDIO_CD_ACTIVE 0 1225 | #define RTE_SDIO_CD_PORT GPIO_PORT(5) 1226 | #define RTE_SDIO_CD_PIN 11 1227 | 1228 | // Write Protect Pin 1229 | // Configure Pin if exists 1230 | // GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) 1231 | // Active State <0=>Low <1=>High 1232 | // Selects Active State Logical Level 1233 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 1234 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 1235 | // Selects Port Name 1236 | // Bit <0-15> 1237 | // Selects Port Bit 1238 | // 1239 | #define RTE_SDIO_WP_EN 0 1240 | #define RTE_SDIO_WP_ACTIVE 1 1241 | #define RTE_SDIO_WP_PORT GPIO_PORT(0) 1242 | #define RTE_SDIO_WP_PIN 10 1243 | 1244 | // DMA 1245 | // Number <2=>2 1246 | // Selects DMA Number (only DMA2 can be used) 1247 | // Channel <4=>4 1248 | // Selects DMA Channel (only Channel 4 can be used) 1249 | // Priority <0=>Low <1=>Medium <2=>High <3=>Very High 1250 | // Selects DMA Priority 1251 | // 1252 | #define RTE_SDIO_DMA_NUMBER 2 1253 | #define RTE_SDIO_DMA_CHANNEL 4 1254 | #define RTE_SDIO_DMA_PRIORITY 0 1255 | 1256 | // 1257 | 1258 | 1259 | // CAN1 (Controller Area Network 1) [Driver_CAN1] 1260 | // Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN 1261 | #define RTE_CAN1 0 1262 | 1263 | // CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 1264 | #define RTE_CAN1_RX_PORT_ID 0 1265 | #if (RTE_CAN1_RX_PORT_ID == 0) 1266 | #define RTE_CAN1_RX_PORT GPIOA 1267 | #define RTE_CAN1_RX_BIT 11 1268 | #elif (RTE_CAN1_RX_PORT_ID == 1) 1269 | #define RTE_CAN1_RX_PORT GPIOB 1270 | #define RTE_CAN1_RX_BIT 8 1271 | #elif (RTE_CAN1_RX_PORT_ID == 2) 1272 | #define RTE_CAN1_RX_PORT GPIOD 1273 | #define RTE_CAN1_RX_BIT 0 1274 | #else 1275 | #error "Invalid CAN1_RX Pin Configuration!" 1276 | #endif 1277 | 1278 | // CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 1279 | #define RTE_CAN1_TX_PORT_ID 0 1280 | #if (RTE_CAN1_TX_PORT_ID == 0) 1281 | #define RTE_CAN1_TX_PORT GPIOA 1282 | #define RTE_CAN1_TX_BIT 12 1283 | #elif (RTE_CAN1_TX_PORT_ID == 1) 1284 | #define RTE_CAN1_TX_PORT GPIOB 1285 | #define RTE_CAN1_TX_BIT 9 1286 | #elif (RTE_CAN1_TX_PORT_ID == 2) 1287 | #define RTE_CAN1_TX_PORT GPIOD 1288 | #define RTE_CAN1_TX_BIT 1 1289 | #else 1290 | #error "Invalid CAN1_TX Pin Configuration!" 1291 | #endif 1292 | 1293 | // 1294 | 1295 | 1296 | // CAN2 (Controller Area Network 2) [Driver_CAN2] 1297 | // Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN 1298 | #define RTE_CAN2 0 1299 | 1300 | // CAN2_RX Pin <0=>PB5 <1=>PB12 1301 | #define RTE_CAN2_RX_PORT_ID 0 1302 | #if (RTE_CAN2_RX_PORT_ID == 0) 1303 | #define RTE_CAN2_RX_PORT GPIOB 1304 | #define RTE_CAN2_RX_BIT 5 1305 | #elif (RTE_CAN2_RX_PORT_ID == 1) 1306 | #define RTE_CAN2_RX_PORT GPIOB 1307 | #define RTE_CAN2_RX_BIT 12 1308 | #else 1309 | #error "Invalid CAN2_RX Pin Configuration!" 1310 | #endif 1311 | 1312 | // CAN2_TX Pin <0=>PB6 <1=>PB13 1313 | #define RTE_CAN2_TX_PORT_ID 0 1314 | #if (RTE_CAN2_TX_PORT_ID == 0) 1315 | #define RTE_CAN2_TX_PORT GPIOB 1316 | #define RTE_CAN2_TX_BIT 6 1317 | #elif (RTE_CAN2_TX_PORT_ID == 1) 1318 | #define RTE_CAN2_TX_PORT GPIOB 1319 | #define RTE_CAN2_TX_BIT 13 1320 | #else 1321 | #error "Invalid CAN2_TX Pin Configuration!" 1322 | #endif 1323 | 1324 | // 1325 | 1326 | 1327 | // ETH (Ethernet Interface) [Driver_ETH_MAC0] 1328 | // Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC 1329 | #define RTE_ETH 0 1330 | 1331 | // MII (Media Independent Interface) 1332 | // Enable Media Independent Interface pin configuration 1333 | #define RTE_ETH_MII 0 1334 | 1335 | // ETH_MII_TX_CLK Pin <0=>PC3 1336 | #define RTE_ETH_MII_TX_CLK_PORT_ID 0 1337 | #if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) 1338 | #define RTE_ETH_MII_TX_CLK_PORT GPIOC 1339 | #define RTE_ETH_MII_TX_CLK_PIN 3 1340 | #else 1341 | #error "Invalid ETH_MII_TX_CLK Pin Configuration!" 1342 | #endif 1343 | // ETH_MII_TXD0 Pin <0=>PB12 1344 | #define RTE_ETH_MII_TXD0_PORT_ID 0 1345 | #if (RTE_ETH_MII_TXD0_PORT_ID == 0) 1346 | #define RTE_ETH_MII_TXD0_PORT GPIOB 1347 | #define RTE_ETH_MII_TXD0_PIN 12 1348 | #else 1349 | #error "Invalid ETH_MII_TXD0 Pin Configuration!" 1350 | #endif 1351 | // ETH_MII_TXD1 Pin <0=>PB13 1352 | #define RTE_ETH_MII_TXD1_PORT_ID 0 1353 | #if (RTE_ETH_MII_TXD1_PORT_ID == 0) 1354 | #define RTE_ETH_MII_TXD1_PORT GPIOB 1355 | #define RTE_ETH_MII_TXD1_PIN 13 1356 | #else 1357 | #error "Invalid ETH_MII_TXD1 Pin Configuration!" 1358 | #endif 1359 | // ETH_MII_TXD2 Pin <0=>PC2 1360 | #define RTE_ETH_MII_TXD2_PORT_ID 0 1361 | #if (RTE_ETH_MII_TXD2_PORT_ID == 0) 1362 | #define RTE_ETH_MII_TXD2_PORT GPIOC 1363 | #define RTE_ETH_MII_TXD2_PIN 2 1364 | #else 1365 | #error "Invalid ETH_MII_TXD2 Pin Configuration!" 1366 | #endif 1367 | // ETH_MII_TXD3 Pin <0=>PB8 1368 | #define RTE_ETH_MII_TXD3_PORT_ID 0 1369 | #if (RTE_ETH_MII_TXD3_PORT_ID == 0) 1370 | #define RTE_ETH_MII_TXD3_PORT GPIOB 1371 | #define RTE_ETH_MII_TXD3_PIN 8 1372 | #else 1373 | #error "Invalid ETH_MII_TXD3 Pin Configuration!" 1374 | #endif 1375 | // ETH_MII_TX_EN Pin <0=>PB11 1376 | #define RTE_ETH_MII_TX_EN_PORT_ID 0 1377 | #if (RTE_ETH_MII_TX_EN_PORT_ID == 0) 1378 | #define RTE_ETH_MII_TX_EN_PORT GPIOB 1379 | #define RTE_ETH_MII_TX_EN_PIN 11 1380 | #else 1381 | #error "Invalid ETH_MII_TX_EN Pin Configuration!" 1382 | #endif 1383 | // ETH_MII_RX_CLK Pin <0=>PA1 1384 | #define RTE_ETH_MII_RX_CLK_PORT_ID 0 1385 | #if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) 1386 | #define RTE_ETH_MII_RX_CLK_PORT GPIOA 1387 | #define RTE_ETH_MII_RX_CLK_PIN 1 1388 | #else 1389 | #error "Invalid ETH_MII_RX_CLK Pin Configuration!" 1390 | #endif 1391 | // ETH_MII_RXD0 Pin <0=>PC4 1392 | #define RTE_ETH_MII_RXD0_DEF 0 1393 | 1394 | // ETH_MII_RXD1 Pin <0=>PC5 1395 | #define RTE_ETH_MII_RXD1_DEF 0 1396 | 1397 | // ETH_MII_RXD2 Pin <0=>PB0 1398 | #define RTE_ETH_MII_RXD2_DEF 0 1399 | 1400 | // ETH_MII_RXD3 Pin <0=>PB1 <1=>PD12 1401 | #define RTE_ETH_MII_RXD3_DEF 0 1402 | 1403 | // ETH_MII_RX_DV Pin <0=>PA7 1404 | #define RTE_ETH_MII_RX_DV_DEF 0 1405 | 1406 | // ETH_MII_RX_ER Pin <0=>PB10 1407 | #define RTE_ETH_MII_RX_ER_PORT_ID 0 1408 | #if (RTE_ETH_MII_RX_ER_PORT_ID == 0) 1409 | #define RTE_ETH_MII_RX_ER_PORT GPIOB 1410 | #define RTE_ETH_MII_RX_ER_PIN 10 1411 | #else 1412 | #error "Invalid ETH_MII_RX_ER Pin Configuration!" 1413 | #endif 1414 | // ETH_MII_CRS Pin <0=>PA0 1415 | #define RTE_ETH_MII_CRS_PORT_ID 0 1416 | #if (RTE_ETH_MII_CRS_PORT_ID == 0) 1417 | #define RTE_ETH_MII_CRS_PORT GPIOA 1418 | #define RTE_ETH_MII_CRS_PIN 0 1419 | #else 1420 | #error "Invalid ETH_MII_CRS Pin Configuration!" 1421 | #endif 1422 | // ETH_MII_COL Pin <0=>PA3 1423 | #define RTE_ETH_MII_COL_PORT_ID 0 1424 | #if (RTE_ETH_MII_COL_PORT_ID == 0) 1425 | #define RTE_ETH_MII_COL_PORT GPIOA 1426 | #define RTE_ETH_MII_COL_PIN 3 1427 | #else 1428 | #error "Invalid ETH_MII_COL Pin Configuration!" 1429 | #endif 1430 | 1431 | // Ethernet MAC I/O remapping 1432 | // Remap Ethernet pins 1433 | #define RTE_ETH_MII_REMAP 0 1434 | 1435 | // ETH_MII_RXD0 Pin <1=>PD9 1436 | #define RTE_ETH_MII_RXD0_REMAP 1 1437 | 1438 | // ETH_MII_RXD1 Pin <1=>PD10 1439 | #define RTE_ETH_MII_RXD1_REMAP 1 1440 | 1441 | // ETH_MII_RXD2 Pin <1=>PD11 1442 | #define RTE_ETH_MII_RXD2_REMAP 1 1443 | 1444 | // ETH_MII_RXD3 Pin <1=>PD12 1445 | #define RTE_ETH_MII_RXD3_REMAP 1 1446 | 1447 | // ETH_MII_RX_DV Pin <1=>PD8 1448 | #define RTE_ETH_MII_RX_DV_REMAP 1 1449 | // 1450 | 1451 | // 1452 | 1453 | #if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD0_DEF == 0)) 1454 | #define RTE_ETH_MII_RXD0_PORT GPIOC 1455 | #define RTE_ETH_MII_RXD0_PIN 4 1456 | #elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD0_REMAP == 1)) 1457 | #define RTE_ETH_MII_RXD0_PORT GPIOD 1458 | #define RTE_ETH_MII_RXD0_PIN 9 1459 | #else 1460 | #error "Invalid ETH_MII_RXD0 Pin Configuration!" 1461 | #endif 1462 | 1463 | #if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD1_DEF == 0)) 1464 | #define RTE_ETH_MII_RXD1_PORT GPIOC 1465 | #define RTE_ETH_MII_RXD1_PIN 5 1466 | #elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD1_REMAP == 1)) 1467 | #define RTE_ETH_MII_RXD1_PORT GPIOD 1468 | #define RTE_ETH_MII_RXD1_PIN 10 1469 | #else 1470 | #error "Invalid ETH_MII_RXD1 Pin Configuration!" 1471 | #endif 1472 | 1473 | #if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD2_DEF == 0)) 1474 | #define RTE_ETH_MII_RXD2_PORT GPIOB 1475 | #define RTE_ETH_MII_RXD2_PIN 0 1476 | #elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD2_REMAP == 1)) 1477 | #define RTE_ETH_MII_RXD2_PORT GPIOD 1478 | #define RTE_ETH_MII_RXD2_PIN 11 1479 | #else 1480 | #error "Invalid ETH_MII_RXD2 Pin Configuration!" 1481 | #endif 1482 | 1483 | #if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RXD3_DEF == 0)) 1484 | #define RTE_ETH_MII_RXD3_PORT GPIOB 1485 | #define RTE_ETH_MII_RXD3_PIN 1 1486 | #elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RXD3_REMAP == 1)) 1487 | #define RTE_ETH_MII_RXD3_PORT GPIOD 1488 | #define RTE_ETH_MII_RXD3_PIN 12 1489 | #else 1490 | #error "Invalid ETH_MII_RXD3 Pin Configuration!" 1491 | #endif 1492 | 1493 | #if ((RTE_ETH_MII_REMAP == 0) && (RTE_ETH_MII_RX_DV_DEF == 0)) 1494 | #define RTE_ETH_MII_RX_DV_PORT GPIOA 1495 | #define RTE_ETH_MII_RX_DV_PIN 7 1496 | #elif ((RTE_ETH_MII_REMAP == 1) && (RTE_ETH_MII_RX_DV_REMAP == 1)) 1497 | #define RTE_ETH_MII_RX_DV_PORT GPIOD 1498 | #define RTE_ETH_MII_RX_DV_PIN 8 1499 | #else 1500 | #error "Invalid ETH_MII_RX_DV Pin Configuration!" 1501 | #endif 1502 | 1503 | // RMII (Reduced Media Independent Interface) 1504 | #define RTE_ETH_RMII 0 1505 | 1506 | // ETH_RMII_TXD0 Pin <0=>PB12 1507 | #define RTE_ETH_RMII_TXD0_PORT_ID 0 1508 | #if (RTE_ETH_RMII_TXD0_PORT_ID == 0) 1509 | #define RTE_ETH_RMII_TXD0_PORT GPIOB 1510 | #define RTE_ETH_RMII_TXD0_PIN 12 1511 | #else 1512 | #error "Invalid ETH_RMII_TXD0 Pin Configuration!" 1513 | #endif 1514 | // ETH_RMII_TXD1 Pin <0=>PB13 1515 | #define RTE_ETH_RMII_TXD1_PORT_ID 0 1516 | #if (RTE_ETH_RMII_TXD1_PORT_ID == 0) 1517 | #define RTE_ETH_RMII_TXD1_PORT GPIOB 1518 | #define RTE_ETH_RMII_TXD1_PIN 13 1519 | #else 1520 | #error "Invalid ETH_RMII_TXD1 Pin Configuration!" 1521 | #endif 1522 | // ETH_RMII_TX_EN Pin <0=>PB11 1523 | #define RTE_ETH_RMII_TX_EN_PORT_ID 0 1524 | #if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) 1525 | #define RTE_ETH_RMII_TX_EN_PORT GPIOB 1526 | #define RTE_ETH_RMII_TX_EN_PIN 11 1527 | #else 1528 | #error "Invalid ETH_RMII_TX_EN Pin Configuration!" 1529 | #endif 1530 | // ETH_RMII_RXD0 Pin <0=>PC4 1531 | #define RTE_ETH_RMII_RXD0_DEF 0 1532 | 1533 | // ETH_RMII_RXD1 Pin <0=>PC5 1534 | #define RTE_ETH_RMII_RXD1_DEF 0 1535 | 1536 | // ETH_RMII_REF_CLK Pin <0=>PA1 1537 | #define RTE_ETH_RMII_REF_CLK_PORT_ID 0 1538 | #if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) 1539 | #define RTE_ETH_RMII_REF_CLK_PORT GPIOA 1540 | #define RTE_ETH_RMII_REF_CLK_PIN 1 1541 | #else 1542 | #error "Invalid ETH_RMII_REF_CLK Pin Configuration!" 1543 | #endif 1544 | // ETH_RMII_CRS_DV Pin <0=>PA7 1545 | #define RTE_ETH_RMII_CRS_DV_DEF 0 1546 | 1547 | // Ethernet MAC I/O remapping 1548 | // Remap Ethernet pins 1549 | #define RTE_ETH_RMII_REMAP 0 1550 | // ETH_RMII_RXD0 Pin <1=>PD9 1551 | #define RTE_ETH_RMII_RXD0_REMAP 1 1552 | 1553 | // ETH_RMII_RXD1 Pin <1=>PD10 1554 | #define RTE_ETH_RMII_RXD1_REMAP 1 1555 | 1556 | // ETH_RMII_CRS_DV Pin <1=>PD8 1557 | #define RTE_ETH_RMII_CRS_DV_REMAP 1 1558 | // 1559 | 1560 | #if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD0_DEF == 0)) 1561 | #define RTE_ETH_RMII_RXD0_PORT GPIOC 1562 | #define RTE_ETH_RMII_RXD0_PIN 4 1563 | #elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD0_REMAP == 1)) 1564 | #define RTE_ETH_RMII_RXD0_PORT GPIOD 1565 | #define RTE_ETH_RMII_RXD0_PIN 9 1566 | #else 1567 | #error "Invalid ETH_RMII_RXD0 Pin Configuration!" 1568 | #endif 1569 | 1570 | #if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_RXD1_DEF == 0)) 1571 | #define RTE_ETH_RMII_RXD1_PORT GPIOC 1572 | #define RTE_ETH_RMII_RXD1_PIN 5 1573 | #elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_RXD1_REMAP == 1)) 1574 | #define RTE_ETH_RMII_RXD1_PORT GPIOD 1575 | #define RTE_ETH_RMII_RXD1_PIN 10 1576 | #else 1577 | #error "Invalid ETH_RMII_RXD1 Pin Configuration!" 1578 | #endif 1579 | 1580 | #if ((RTE_ETH_RMII_REMAP == 0) && (RTE_ETH_RMII_CRS_DV_DEF == 0)) 1581 | #define RTE_ETH_RMII_CRS_DV_PORT GPIOA 1582 | #define RTE_ETH_RMII_CRS_DV_PIN 7 1583 | #elif ((RTE_ETH_RMII_REMAP == 1) && (RTE_ETH_RMII_CRS_DV_REMAP == 1)) 1584 | #define RTE_ETH_RMII_CRS_DV_PORT GPIOD 1585 | #define RTE_ETH_RMII_CRS_DV_PIN 8 1586 | #else 1587 | #error "Invalid ETH_RMII_CRS_DV Pin Configuration!" 1588 | #endif 1589 | 1590 | // 1591 | 1592 | // Management Data Interface 1593 | // ETH_MDC Pin <0=>PC1 1594 | #define RTE_ETH_MDI_MDC_PORT_ID 0 1595 | #if (RTE_ETH_MDI_MDC_PORT_ID == 0) 1596 | #define RTE_ETH_MDI_MDC_PORT GPIOC 1597 | #define RTE_ETH_MDI_MDC_PIN 1 1598 | #else 1599 | #error "Invalid ETH_MDC Pin Configuration!" 1600 | #endif 1601 | // ETH_MDIO Pin <0=>PA2 1602 | #define RTE_ETH_MDI_MDIO_PORT_ID 0 1603 | #if (RTE_ETH_MDI_MDIO_PORT_ID == 0) 1604 | #define RTE_ETH_MDI_MDIO_PORT GPIOA 1605 | #define RTE_ETH_MDI_MDIO_PIN 2 1606 | #else 1607 | #error "Invalid ETH_MDIO Pin Configuration!" 1608 | #endif 1609 | // 1610 | 1611 | // Reference 25MHz Clock generation on MCO pin <0=>Disabled <1=>Enabled 1612 | #define RTE_ETH_REF_CLOCK_ID 0 1613 | #if (RTE_ETH_REF_CLOCK_ID == 0) 1614 | #define RTE_ETH_REF_CLOCK 0 1615 | #elif (RTE_ETH_REF_CLOCK_ID == 1) 1616 | #define RTE_ETH_REF_CLOCK 1 1617 | #else 1618 | #error "Invalid MCO Ethernet Reference Clock Configuration!" 1619 | #endif 1620 | // 1621 | 1622 | 1623 | // USB Device Full-speed 1624 | // Configuration settings for Driver_USBD0 in component ::Drivers:USB Device 1625 | #define RTE_USB_DEVICE 0 1626 | 1627 | // CON On/Off Pin 1628 | // Configure Pin for driving D+ pull-up 1629 | // GPIO Pxy (x = A..G, y = 0..15) 1630 | // Active State <0=>Low <1=>High 1631 | // Selects Active State Logical Level 1632 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 1633 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 1634 | // Selects Port Name 1635 | // Bit <0-15> 1636 | // Selects Port Bit 1637 | // 1638 | #define RTE_USB_DEVICE_CON_PIN 1 1639 | #define RTE_USB_DEVICE_CON_ACTIVE 0 1640 | #define RTE_USB_DEVICE_CON_PORT GPIO_PORT(1) 1641 | #define RTE_USB_DEVICE_CON_BIT 14 1642 | 1643 | // 1644 | 1645 | 1646 | // USB OTG Full-speed 1647 | #define RTE_USB_OTG_FS 0 1648 | 1649 | // Host [Driver_USBH0] 1650 | // Configuration settings for Driver_USBH0 in component ::Drivers:USB Host 1651 | 1652 | #define RTE_USB_OTG_FS_HOST 0 1653 | 1654 | // VBUS Power On/Off Pin 1655 | // Configure Pin for driving VBUS 1656 | // GPIO Pxy (x = A..G, y = 0..15) 1657 | // Active State <0=>Low <1=>High 1658 | // Selects Active State Logical Level 1659 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 1660 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 1661 | // Selects Port Name 1662 | // Bit <0-15> 1663 | // Selects Port Bit 1664 | // 1665 | #define RTE_OTG_FS_VBUS_PIN 1 1666 | #define RTE_OTG_FS_VBUS_ACTIVE 0 1667 | #define RTE_OTG_FS_VBUS_PORT GPIO_PORT(2) 1668 | #define RTE_OTG_FS_VBUS_BIT 9 1669 | 1670 | // Overcurrent Detection Pin 1671 | // Configure Pin for overcurrent detection 1672 | // GPIO Pxy (x = A..G, y = 0..15) 1673 | // Active State <0=>Low <1=>High 1674 | // Selects Active State Logical Level 1675 | // Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD 1676 | // <4=>GPIOE <5=>GPIOF <6=>GPIOG 1677 | // Selects Port Name 1678 | // Bit <0-15> 1679 | // Selects Port Bit 1680 | // 1681 | #define RTE_OTG_FS_OC_PIN 1 1682 | #define RTE_OTG_FS_OC_ACTIVE 0 1683 | #define RTE_OTG_FS_OC_PORT GPIO_PORT(4) 1684 | #define RTE_OTG_FS_OC_BIT 1 1685 | // 1686 | 1687 | // 1688 | 1689 | 1690 | #endif /* __RTE_DEVICE_H */ 1691 | -------------------------------------------------------------------------------- /RTE/Device/STM32F103C8/startup_stm32f10x_md.s: -------------------------------------------------------------------------------- 1 | ;******************** (C) COPYRIGHT 2011 STMicroelectronics ******************** 2 | ;* File Name : startup_stm32f10x_md.s 3 | ;* Author : MCD Application Team 4 | ;* Version : V3.5.0 5 | ;* Date : 11-March-2011 6 | ;* Description : STM32F10x Medium Density Devices vector table for MDK-ARM 7 | ;* toolchain. 8 | ;* This module performs: 9 | ;* - Set the initial SP 10 | ;* - Set the initial PC == Reset_Handler 11 | ;* - Set the vector table entries with the exceptions ISR address 12 | ;* - Configure the clock system 13 | ;* - Branches to __main in the C library (which eventually 14 | ;* calls main()). 15 | ;* After Reset the CortexM3 processor is in Thread mode, 16 | ;* priority is Privileged, and the Stack is set to Main. 17 | ;* <<< Use Configuration Wizard in Context Menu >>> 18 | ;******************************************************************************* 19 | ; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 20 | ; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. 21 | ; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, 22 | ; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE 23 | ; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING 24 | ; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 25 | ;******************************************************************************* 26 | 27 | ; Amount of memory (in bytes) allocated for Stack 28 | ; Tailor this value to your application needs 29 | ; Stack Configuration 30 | ; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> 31 | ; 32 | 33 | Stack_Size EQU 0x00000400 34 | 35 | AREA STACK, NOINIT, READWRITE, ALIGN=3 36 | Stack_Mem SPACE Stack_Size 37 | __initial_sp 38 | 39 | 40 | ; Heap Configuration 41 | ; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> 42 | ; 43 | 44 | Heap_Size EQU 0x00000200 45 | 46 | AREA HEAP, NOINIT, READWRITE, ALIGN=3 47 | __heap_base 48 | Heap_Mem SPACE Heap_Size 49 | __heap_limit 50 | 51 | PRESERVE8 52 | THUMB 53 | 54 | 55 | ; Vector Table Mapped to Address 0 at Reset 56 | AREA RESET, DATA, READONLY 57 | EXPORT __Vectors 58 | EXPORT __Vectors_End 59 | EXPORT __Vectors_Size 60 | 61 | __Vectors DCD __initial_sp ; Top of Stack 62 | DCD Reset_Handler ; Reset Handler 63 | DCD NMI_Handler ; NMI Handler 64 | DCD HardFault_Handler ; Hard Fault Handler 65 | DCD MemManage_Handler ; MPU Fault Handler 66 | DCD BusFault_Handler ; Bus Fault Handler 67 | DCD UsageFault_Handler ; Usage Fault Handler 68 | DCD 0 ; Reserved 69 | DCD 0 ; Reserved 70 | DCD 0 ; Reserved 71 | DCD 0 ; Reserved 72 | DCD SVC_Handler ; SVCall Handler 73 | DCD DebugMon_Handler ; Debug Monitor Handler 74 | DCD 0 ; Reserved 75 | DCD PendSV_Handler ; PendSV Handler 76 | DCD SysTick_Handler ; SysTick Handler 77 | 78 | ; External Interrupts 79 | DCD WWDG_IRQHandler ; Window Watchdog 80 | DCD PVD_IRQHandler ; PVD through EXTI Line detect 81 | DCD TAMPER_IRQHandler ; Tamper 82 | DCD RTC_IRQHandler ; RTC 83 | DCD FLASH_IRQHandler ; Flash 84 | DCD RCC_IRQHandler ; RCC 85 | DCD EXTI0_IRQHandler ; EXTI Line 0 86 | DCD EXTI1_IRQHandler ; EXTI Line 1 87 | DCD EXTI2_IRQHandler ; EXTI Line 2 88 | DCD EXTI3_IRQHandler ; EXTI Line 3 89 | DCD EXTI4_IRQHandler ; EXTI Line 4 90 | DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 91 | DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 92 | DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 93 | DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 94 | DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 95 | DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 96 | DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 97 | DCD ADC1_2_IRQHandler ; ADC1_2 98 | DCD USB_HP_CAN1_TX_IRQHandler ; USB High Priority or CAN1 TX 99 | DCD USB_LP_CAN1_RX0_IRQHandler ; USB Low Priority or CAN1 RX0 100 | DCD CAN1_RX1_IRQHandler ; CAN1 RX1 101 | DCD CAN1_SCE_IRQHandler ; CAN1 SCE 102 | DCD EXTI9_5_IRQHandler ; EXTI Line 9..5 103 | DCD TIM1_BRK_IRQHandler ; TIM1 Break 104 | DCD TIM1_UP_IRQHandler ; TIM1 Update 105 | DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation 106 | DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare 107 | DCD TIM2_IRQHandler ; TIM2 108 | DCD TIM3_IRQHandler ; TIM3 109 | DCD TIM4_IRQHandler ; TIM4 110 | DCD I2C1_EV_IRQHandler ; I2C1 Event 111 | DCD I2C1_ER_IRQHandler ; I2C1 Error 112 | DCD I2C2_EV_IRQHandler ; I2C2 Event 113 | DCD I2C2_ER_IRQHandler ; I2C2 Error 114 | DCD SPI1_IRQHandler ; SPI1 115 | DCD SPI2_IRQHandler ; SPI2 116 | DCD USART1_IRQHandler ; USART1 117 | DCD USART2_IRQHandler ; USART2 118 | DCD USART3_IRQHandler ; USART3 119 | DCD EXTI15_10_IRQHandler ; EXTI Line 15..10 120 | DCD RTCAlarm_IRQHandler ; RTC Alarm through EXTI Line 121 | DCD USBWakeUp_IRQHandler ; USB Wakeup from suspend 122 | __Vectors_End 123 | 124 | __Vectors_Size EQU __Vectors_End - __Vectors 125 | 126 | AREA |.text|, CODE, READONLY 127 | 128 | ; Reset handler 129 | Reset_Handler PROC 130 | EXPORT Reset_Handler [WEAK] 131 | IMPORT __main 132 | IMPORT SystemInit 133 | LDR R0, =SystemInit 134 | BLX R0 135 | LDR R0, =__main 136 | BX R0 137 | ENDP 138 | 139 | ; Dummy Exception Handlers (infinite loops which can be modified) 140 | 141 | NMI_Handler PROC 142 | EXPORT NMI_Handler [WEAK] 143 | B . 144 | ENDP 145 | HardFault_Handler\ 146 | PROC 147 | EXPORT HardFault_Handler [WEAK] 148 | B . 149 | ENDP 150 | MemManage_Handler\ 151 | PROC 152 | EXPORT MemManage_Handler [WEAK] 153 | B . 154 | ENDP 155 | BusFault_Handler\ 156 | PROC 157 | EXPORT BusFault_Handler [WEAK] 158 | B . 159 | ENDP 160 | UsageFault_Handler\ 161 | PROC 162 | EXPORT UsageFault_Handler [WEAK] 163 | B . 164 | ENDP 165 | SVC_Handler PROC 166 | EXPORT SVC_Handler [WEAK] 167 | B . 168 | ENDP 169 | DebugMon_Handler\ 170 | PROC 171 | EXPORT DebugMon_Handler [WEAK] 172 | B . 173 | ENDP 174 | PendSV_Handler PROC 175 | EXPORT PendSV_Handler [WEAK] 176 | B . 177 | ENDP 178 | SysTick_Handler PROC 179 | EXPORT SysTick_Handler [WEAK] 180 | B . 181 | ENDP 182 | 183 | Default_Handler PROC 184 | 185 | EXPORT WWDG_IRQHandler [WEAK] 186 | EXPORT PVD_IRQHandler [WEAK] 187 | EXPORT TAMPER_IRQHandler [WEAK] 188 | EXPORT RTC_IRQHandler [WEAK] 189 | EXPORT FLASH_IRQHandler [WEAK] 190 | EXPORT RCC_IRQHandler [WEAK] 191 | EXPORT EXTI0_IRQHandler [WEAK] 192 | EXPORT EXTI1_IRQHandler [WEAK] 193 | EXPORT EXTI2_IRQHandler [WEAK] 194 | EXPORT EXTI3_IRQHandler [WEAK] 195 | EXPORT EXTI4_IRQHandler [WEAK] 196 | EXPORT DMA1_Channel1_IRQHandler [WEAK] 197 | EXPORT DMA1_Channel2_IRQHandler [WEAK] 198 | EXPORT DMA1_Channel3_IRQHandler [WEAK] 199 | EXPORT DMA1_Channel4_IRQHandler [WEAK] 200 | EXPORT DMA1_Channel5_IRQHandler [WEAK] 201 | EXPORT DMA1_Channel6_IRQHandler [WEAK] 202 | EXPORT DMA1_Channel7_IRQHandler [WEAK] 203 | EXPORT ADC1_2_IRQHandler [WEAK] 204 | EXPORT USB_HP_CAN1_TX_IRQHandler [WEAK] 205 | EXPORT USB_LP_CAN1_RX0_IRQHandler [WEAK] 206 | EXPORT CAN1_RX1_IRQHandler [WEAK] 207 | EXPORT CAN1_SCE_IRQHandler [WEAK] 208 | EXPORT EXTI9_5_IRQHandler [WEAK] 209 | EXPORT TIM1_BRK_IRQHandler [WEAK] 210 | EXPORT TIM1_UP_IRQHandler [WEAK] 211 | EXPORT TIM1_TRG_COM_IRQHandler [WEAK] 212 | EXPORT TIM1_CC_IRQHandler [WEAK] 213 | EXPORT TIM2_IRQHandler [WEAK] 214 | EXPORT TIM3_IRQHandler [WEAK] 215 | EXPORT TIM4_IRQHandler [WEAK] 216 | EXPORT I2C1_EV_IRQHandler [WEAK] 217 | EXPORT I2C1_ER_IRQHandler [WEAK] 218 | EXPORT I2C2_EV_IRQHandler [WEAK] 219 | EXPORT I2C2_ER_IRQHandler [WEAK] 220 | EXPORT SPI1_IRQHandler [WEAK] 221 | EXPORT SPI2_IRQHandler [WEAK] 222 | EXPORT USART1_IRQHandler [WEAK] 223 | EXPORT USART2_IRQHandler [WEAK] 224 | EXPORT USART3_IRQHandler [WEAK] 225 | EXPORT EXTI15_10_IRQHandler [WEAK] 226 | EXPORT RTCAlarm_IRQHandler [WEAK] 227 | EXPORT USBWakeUp_IRQHandler [WEAK] 228 | 229 | WWDG_IRQHandler 230 | PVD_IRQHandler 231 | TAMPER_IRQHandler 232 | RTC_IRQHandler 233 | FLASH_IRQHandler 234 | RCC_IRQHandler 235 | EXTI0_IRQHandler 236 | EXTI1_IRQHandler 237 | EXTI2_IRQHandler 238 | EXTI3_IRQHandler 239 | EXTI4_IRQHandler 240 | DMA1_Channel1_IRQHandler 241 | DMA1_Channel2_IRQHandler 242 | DMA1_Channel3_IRQHandler 243 | DMA1_Channel4_IRQHandler 244 | DMA1_Channel5_IRQHandler 245 | DMA1_Channel6_IRQHandler 246 | DMA1_Channel7_IRQHandler 247 | ADC1_2_IRQHandler 248 | USB_HP_CAN1_TX_IRQHandler 249 | USB_LP_CAN1_RX0_IRQHandler 250 | CAN1_RX1_IRQHandler 251 | CAN1_SCE_IRQHandler 252 | EXTI9_5_IRQHandler 253 | TIM1_BRK_IRQHandler 254 | TIM1_UP_IRQHandler 255 | TIM1_TRG_COM_IRQHandler 256 | TIM1_CC_IRQHandler 257 | TIM2_IRQHandler 258 | TIM3_IRQHandler 259 | TIM4_IRQHandler 260 | I2C1_EV_IRQHandler 261 | I2C1_ER_IRQHandler 262 | I2C2_EV_IRQHandler 263 | I2C2_ER_IRQHandler 264 | SPI1_IRQHandler 265 | SPI2_IRQHandler 266 | USART1_IRQHandler 267 | USART2_IRQHandler 268 | USART3_IRQHandler 269 | EXTI15_10_IRQHandler 270 | RTCAlarm_IRQHandler 271 | USBWakeUp_IRQHandler 272 | 273 | B . 274 | 275 | ENDP 276 | 277 | ALIGN 278 | 279 | ;******************************************************************************* 280 | ; User Stack and Heap initialization 281 | ;******************************************************************************* 282 | IF :DEF:__MICROLIB 283 | 284 | EXPORT __initial_sp 285 | EXPORT __heap_base 286 | EXPORT __heap_limit 287 | 288 | ELSE 289 | 290 | IMPORT __use_two_region_memory 291 | EXPORT __user_initial_stackheap 292 | 293 | __user_initial_stackheap 294 | 295 | LDR R0, = Heap_Mem 296 | LDR R1, =(Stack_Mem + Stack_Size) 297 | LDR R2, = (Heap_Mem + Heap_Size) 298 | LDR R3, = Stack_Mem 299 | BX LR 300 | 301 | ALIGN 302 | 303 | ENDIF 304 | 305 | END 306 | 307 | ;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE***** 308 | -------------------------------------------------------------------------------- /RTE/Device/STM32F103C8/system_stm32f10x.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. 8 | * 9 | * 1. This file provides two functions and one global variable to be called from 10 | * user application: 11 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 12 | * factors, AHB/APBx prescalers and Flash settings). 13 | * This function is called at startup just after reset and 14 | * before branch to main program. This call is made inside 15 | * the "startup_stm32f10x_xx.s" file. 16 | * 17 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 18 | * by the user application to setup the SysTick 19 | * timer or configure other parameters. 20 | * 21 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 22 | * be called whenever the core clock is changed 23 | * during program execution. 24 | * 25 | * 2. After each device reset the HSI (8 MHz) is used as system clock source. 26 | * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to 27 | * configure the system clock before to branch to main program. 28 | * 29 | * 3. If the system clock source selected by user fails to startup, the SystemInit() 30 | * function will do nothing and HSI still used as system clock source. User can 31 | * add some code to deal with this issue inside the SetSysClock() function. 32 | * 33 | * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on 34 | * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. 35 | * When HSE is used as system clock source, directly or through PLL, and you 36 | * are using different crystal you have to adapt the HSE value to your own 37 | * configuration. 38 | * 39 | ****************************************************************************** 40 | * @attention 41 | * 42 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 43 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 44 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 45 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 46 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 47 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 48 | * 49 | *

© COPYRIGHT 2011 STMicroelectronics

50 | ****************************************************************************** 51 | */ 52 | 53 | /** @addtogroup CMSIS 54 | * @{ 55 | */ 56 | 57 | /** @addtogroup stm32f10x_system 58 | * @{ 59 | */ 60 | 61 | /** @addtogroup STM32F10x_System_Private_Includes 62 | * @{ 63 | */ 64 | 65 | #include "stm32f10x.h" 66 | 67 | /** 68 | * @} 69 | */ 70 | 71 | /** @addtogroup STM32F10x_System_Private_TypesDefinitions 72 | * @{ 73 | */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @addtogroup STM32F10x_System_Private_Defines 80 | * @{ 81 | */ 82 | 83 | /*!< Uncomment the line corresponding to the desired System clock (SYSCLK) 84 | frequency (after reset the HSI is used as SYSCLK source) 85 | 86 | IMPORTANT NOTE: 87 | ============== 88 | 1. After each device reset the HSI is used as System clock source. 89 | 90 | 2. Please make sure that the selected System clock doesn't exceed your device's 91 | maximum frequency. 92 | 93 | 3. If none of the define below is enabled, the HSI is used as System clock 94 | source. 95 | 96 | 4. The System clock configuration functions provided within this file assume that: 97 | - For Low, Medium and High density Value line devices an external 8MHz 98 | crystal is used to drive the System clock. 99 | - For Low, Medium and High density devices an external 8MHz crystal is 100 | used to drive the System clock. 101 | - For Connectivity line devices an external 25MHz crystal is used to drive 102 | the System clock. 103 | If you are using different crystal you have to adapt those functions accordingly. 104 | */ 105 | 106 | #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) 107 | /* #define SYSCLK_FREQ_HSE HSE_VALUE */ 108 | #define SYSCLK_FREQ_24MHz 24000000 109 | #else 110 | /* #define SYSCLK_FREQ_HSE HSE_VALUE */ 111 | /* #define SYSCLK_FREQ_24MHz 24000000 */ 112 | /* #define SYSCLK_FREQ_36MHz 36000000 */ 113 | /* #define SYSCLK_FREQ_48MHz 48000000 */ 114 | /* #define SYSCLK_FREQ_56MHz 56000000 */ 115 | #define SYSCLK_FREQ_72MHz 72000000 116 | #endif 117 | 118 | /*!< Uncomment the following line if you need to use external SRAM mounted 119 | on STM3210E-EVAL board (STM32 High density and XL-density devices) or on 120 | STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ 121 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) 122 | /* #define DATA_IN_ExtSRAM */ 123 | #endif 124 | 125 | /*!< Uncomment the following line if you need to relocate your vector Table in 126 | Internal SRAM. */ 127 | /* #define VECT_TAB_SRAM */ 128 | #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. 129 | This value must be a multiple of 0x200. */ 130 | 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** @addtogroup STM32F10x_System_Private_Macros 137 | * @{ 138 | */ 139 | 140 | /** 141 | * @} 142 | */ 143 | 144 | /** @addtogroup STM32F10x_System_Private_Variables 145 | * @{ 146 | */ 147 | 148 | /******************************************************************************* 149 | * Clock Definitions 150 | *******************************************************************************/ 151 | #ifdef SYSCLK_FREQ_HSE 152 | uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ 153 | #elif defined SYSCLK_FREQ_24MHz 154 | uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ 155 | #elif defined SYSCLK_FREQ_36MHz 156 | uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ 157 | #elif defined SYSCLK_FREQ_48MHz 158 | uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ 159 | #elif defined SYSCLK_FREQ_56MHz 160 | uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ 161 | #elif defined SYSCLK_FREQ_72MHz 162 | uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ 163 | #else /*!< HSI Selected as System Clock source */ 164 | uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ 165 | #endif 166 | 167 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 168 | /** 169 | * @} 170 | */ 171 | 172 | /** @addtogroup STM32F10x_System_Private_FunctionPrototypes 173 | * @{ 174 | */ 175 | 176 | static void SetSysClock(void); 177 | 178 | #ifdef SYSCLK_FREQ_HSE 179 | static void SetSysClockToHSE(void); 180 | #elif defined SYSCLK_FREQ_24MHz 181 | static void SetSysClockTo24(void); 182 | #elif defined SYSCLK_FREQ_36MHz 183 | static void SetSysClockTo36(void); 184 | #elif defined SYSCLK_FREQ_48MHz 185 | static void SetSysClockTo48(void); 186 | #elif defined SYSCLK_FREQ_56MHz 187 | static void SetSysClockTo56(void); 188 | #elif defined SYSCLK_FREQ_72MHz 189 | static void SetSysClockTo72(void); 190 | #endif 191 | 192 | #ifdef DATA_IN_ExtSRAM 193 | static void SystemInit_ExtMemCtl(void); 194 | #endif /* DATA_IN_ExtSRAM */ 195 | 196 | /** 197 | * @} 198 | */ 199 | 200 | /** @addtogroup STM32F10x_System_Private_Functions 201 | * @{ 202 | */ 203 | 204 | /** 205 | * @brief Setup the microcontroller system 206 | * Initialize the Embedded Flash Interface, the PLL and update the 207 | * SystemCoreClock variable. 208 | * @note This function should be used only after reset. 209 | * @param None 210 | * @retval None 211 | */ 212 | void SystemInit (void) 213 | { 214 | /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ 215 | /* Set HSION bit */ 216 | RCC->CR |= (uint32_t)0x00000001; 217 | 218 | /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ 219 | #ifndef STM32F10X_CL 220 | RCC->CFGR &= (uint32_t)0xF8FF0000; 221 | #else 222 | RCC->CFGR &= (uint32_t)0xF0FF0000; 223 | #endif /* STM32F10X_CL */ 224 | 225 | /* Reset HSEON, CSSON and PLLON bits */ 226 | RCC->CR &= (uint32_t)0xFEF6FFFF; 227 | 228 | /* Reset HSEBYP bit */ 229 | RCC->CR &= (uint32_t)0xFFFBFFFF; 230 | 231 | /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ 232 | RCC->CFGR &= (uint32_t)0xFF80FFFF; 233 | 234 | #ifdef STM32F10X_CL 235 | /* Reset PLL2ON and PLL3ON bits */ 236 | RCC->CR &= (uint32_t)0xEBFFFFFF; 237 | 238 | /* Disable all interrupts and clear pending bits */ 239 | RCC->CIR = 0x00FF0000; 240 | 241 | /* Reset CFGR2 register */ 242 | RCC->CFGR2 = 0x00000000; 243 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) 244 | /* Disable all interrupts and clear pending bits */ 245 | RCC->CIR = 0x009F0000; 246 | 247 | /* Reset CFGR2 register */ 248 | RCC->CFGR2 = 0x00000000; 249 | #else 250 | /* Disable all interrupts and clear pending bits */ 251 | RCC->CIR = 0x009F0000; 252 | #endif /* STM32F10X_CL */ 253 | 254 | #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) 255 | #ifdef DATA_IN_ExtSRAM 256 | SystemInit_ExtMemCtl(); 257 | #endif /* DATA_IN_ExtSRAM */ 258 | #endif 259 | 260 | /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ 261 | /* Configure the Flash Latency cycles and enable prefetch buffer */ 262 | SetSysClock(); 263 | 264 | #ifdef VECT_TAB_SRAM 265 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ 266 | #else 267 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ 268 | #endif 269 | } 270 | 271 | /** 272 | * @brief Update SystemCoreClock variable according to Clock Register Values. 273 | * The SystemCoreClock variable contains the core clock (HCLK), it can 274 | * be used by the user application to setup the SysTick timer or configure 275 | * other parameters. 276 | * 277 | * @note Each time the core clock (HCLK) changes, this function must be called 278 | * to update SystemCoreClock variable value. Otherwise, any configuration 279 | * based on this variable will be incorrect. 280 | * 281 | * @note - The system frequency computed by this function is not the real 282 | * frequency in the chip. It is calculated based on the predefined 283 | * constant and the selected clock source: 284 | * 285 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 286 | * 287 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 288 | * 289 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 290 | * or HSI_VALUE(*) multiplied by the PLL factors. 291 | * 292 | * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value 293 | * 8 MHz) but the real value may vary depending on the variations 294 | * in voltage and temperature. 295 | * 296 | * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value 297 | * 8 MHz or 25 MHz, depedning on the product used), user has to ensure 298 | * that HSE_VALUE is same as the real frequency of the crystal used. 299 | * Otherwise, this function may have wrong result. 300 | * 301 | * - The result of this function could be not correct when using fractional 302 | * value for HSE crystal. 303 | * @param None 304 | * @retval None 305 | */ 306 | void SystemCoreClockUpdate (void) 307 | { 308 | uint32_t tmp = 0, pllmull = 0, pllsource = 0; 309 | 310 | #ifdef STM32F10X_CL 311 | uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; 312 | #endif /* STM32F10X_CL */ 313 | 314 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) 315 | uint32_t prediv1factor = 0; 316 | #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ 317 | 318 | /* Get SYSCLK source -------------------------------------------------------*/ 319 | tmp = RCC->CFGR & RCC_CFGR_SWS; 320 | 321 | switch (tmp) 322 | { 323 | case 0x00: /* HSI used as system clock */ 324 | SystemCoreClock = HSI_VALUE; 325 | break; 326 | case 0x04: /* HSE used as system clock */ 327 | SystemCoreClock = HSE_VALUE; 328 | break; 329 | case 0x08: /* PLL used as system clock */ 330 | 331 | /* Get PLL clock source and multiplication factor ----------------------*/ 332 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 333 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 334 | 335 | #ifndef STM32F10X_CL 336 | pllmull = ( pllmull >> 18) + 2; 337 | 338 | if (pllsource == 0x00) 339 | { 340 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 341 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 342 | } 343 | else 344 | { 345 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) 346 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 347 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 348 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 349 | #else 350 | /* HSE selected as PLL clock entry */ 351 | if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) 352 | {/* HSE oscillator clock divided by 2 */ 353 | SystemCoreClock = (HSE_VALUE >> 1) * pllmull; 354 | } 355 | else 356 | { 357 | SystemCoreClock = HSE_VALUE * pllmull; 358 | } 359 | #endif 360 | } 361 | #else 362 | pllmull = pllmull >> 18; 363 | 364 | if (pllmull != 0x0D) 365 | { 366 | pllmull += 2; 367 | } 368 | else 369 | { /* PLL multiplication factor = PLL input clock * 6.5 */ 370 | pllmull = 13 / 2; 371 | } 372 | 373 | if (pllsource == 0x00) 374 | { 375 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 376 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 377 | } 378 | else 379 | {/* PREDIV1 selected as PLL clock entry */ 380 | 381 | /* Get PREDIV1 clock source and division factor */ 382 | prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; 383 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 384 | 385 | if (prediv1source == 0) 386 | { 387 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 388 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 389 | } 390 | else 391 | {/* PLL2 clock selected as PREDIV1 clock entry */ 392 | 393 | /* Get PREDIV2 division factor and PLL2 multiplication factor */ 394 | prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; 395 | pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; 396 | SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; 397 | } 398 | } 399 | #endif /* STM32F10X_CL */ 400 | break; 401 | 402 | default: 403 | SystemCoreClock = HSI_VALUE; 404 | break; 405 | } 406 | 407 | /* Compute HCLK clock frequency ----------------*/ 408 | /* Get HCLK prescaler */ 409 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 410 | /* HCLK clock frequency */ 411 | SystemCoreClock >>= tmp; 412 | } 413 | 414 | /** 415 | * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. 416 | * @param None 417 | * @retval None 418 | */ 419 | static void SetSysClock(void) 420 | { 421 | #ifdef SYSCLK_FREQ_HSE 422 | SetSysClockToHSE(); 423 | #elif defined SYSCLK_FREQ_24MHz 424 | SetSysClockTo24(); 425 | #elif defined SYSCLK_FREQ_36MHz 426 | SetSysClockTo36(); 427 | #elif defined SYSCLK_FREQ_48MHz 428 | SetSysClockTo48(); 429 | #elif defined SYSCLK_FREQ_56MHz 430 | SetSysClockTo56(); 431 | #elif defined SYSCLK_FREQ_72MHz 432 | SetSysClockTo72(); 433 | #endif 434 | 435 | /* If none of the define above is enabled, the HSI is used as System clock 436 | source (default after reset) */ 437 | } 438 | 439 | /** 440 | * @brief Setup the external memory controller. Called in startup_stm32f10x.s 441 | * before jump to __main 442 | * @param None 443 | * @retval None 444 | */ 445 | #ifdef DATA_IN_ExtSRAM 446 | /** 447 | * @brief Setup the external memory controller. 448 | * Called in startup_stm32f10x_xx.s/.c before jump to main. 449 | * This function configures the external SRAM mounted on STM3210E-EVAL 450 | * board (STM32 High density devices). This SRAM will be used as program 451 | * data memory (including heap and stack). 452 | * @param None 453 | * @retval None 454 | */ 455 | void SystemInit_ExtMemCtl(void) 456 | { 457 | /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is 458 | required, then adjust the Register Addresses */ 459 | 460 | /* Enable FSMC clock */ 461 | RCC->AHBENR = 0x00000114; 462 | 463 | /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ 464 | RCC->APB2ENR = 0x000001E0; 465 | 466 | /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ 467 | /*---------------- SRAM Address lines configuration -------------------------*/ 468 | /*---------------- NOE and NWE configuration --------------------------------*/ 469 | /*---------------- NE3 configuration ----------------------------------------*/ 470 | /*---------------- NBL0, NBL1 configuration ---------------------------------*/ 471 | 472 | GPIOD->CRL = 0x44BB44BB; 473 | GPIOD->CRH = 0xBBBBBBBB; 474 | 475 | GPIOE->CRL = 0xB44444BB; 476 | GPIOE->CRH = 0xBBBBBBBB; 477 | 478 | GPIOF->CRL = 0x44BBBBBB; 479 | GPIOF->CRH = 0xBBBB4444; 480 | 481 | GPIOG->CRL = 0x44BBBBBB; 482 | GPIOG->CRH = 0x44444B44; 483 | 484 | /*---------------- FSMC Configuration ---------------------------------------*/ 485 | /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ 486 | 487 | FSMC_Bank1->BTCR[4] = 0x00001011; 488 | FSMC_Bank1->BTCR[5] = 0x00000200; 489 | } 490 | #endif /* DATA_IN_ExtSRAM */ 491 | 492 | #ifdef SYSCLK_FREQ_HSE 493 | /** 494 | * @brief Selects HSE as System clock source and configure HCLK, PCLK2 495 | * and PCLK1 prescalers. 496 | * @note This function should be used only after reset. 497 | * @param None 498 | * @retval None 499 | */ 500 | static void SetSysClockToHSE(void) 501 | { 502 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 503 | 504 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ 505 | /* Enable HSE */ 506 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 507 | 508 | /* Wait till HSE is ready and if Time out is reached exit */ 509 | do 510 | { 511 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 512 | StartUpCounter++; 513 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 514 | 515 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 516 | { 517 | HSEStatus = (uint32_t)0x01; 518 | } 519 | else 520 | { 521 | HSEStatus = (uint32_t)0x00; 522 | } 523 | 524 | if (HSEStatus == (uint32_t)0x01) 525 | { 526 | 527 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 528 | /* Enable Prefetch Buffer */ 529 | FLASH->ACR |= FLASH_ACR_PRFTBE; 530 | 531 | /* Flash 0 wait state */ 532 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 533 | 534 | #ifndef STM32F10X_CL 535 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; 536 | #else 537 | if (HSE_VALUE <= 24000000) 538 | { 539 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; 540 | } 541 | else 542 | { 543 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; 544 | } 545 | #endif /* STM32F10X_CL */ 546 | #endif 547 | 548 | /* HCLK = SYSCLK */ 549 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 550 | 551 | /* PCLK2 = HCLK */ 552 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 553 | 554 | /* PCLK1 = HCLK */ 555 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; 556 | 557 | /* Select HSE as system clock source */ 558 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 559 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; 560 | 561 | /* Wait till HSE is used as system clock source */ 562 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) 563 | { 564 | } 565 | } 566 | else 567 | { /* If HSE fails to start-up, the application will have wrong clock 568 | configuration. User can add here some code to deal with this error */ 569 | } 570 | } 571 | #elif defined SYSCLK_FREQ_24MHz 572 | /** 573 | * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 574 | * and PCLK1 prescalers. 575 | * @note This function should be used only after reset. 576 | * @param None 577 | * @retval None 578 | */ 579 | static void SetSysClockTo24(void) 580 | { 581 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 582 | 583 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ 584 | /* Enable HSE */ 585 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 586 | 587 | /* Wait till HSE is ready and if Time out is reached exit */ 588 | do 589 | { 590 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 591 | StartUpCounter++; 592 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 593 | 594 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 595 | { 596 | HSEStatus = (uint32_t)0x01; 597 | } 598 | else 599 | { 600 | HSEStatus = (uint32_t)0x00; 601 | } 602 | 603 | if (HSEStatus == (uint32_t)0x01) 604 | { 605 | #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL 606 | /* Enable Prefetch Buffer */ 607 | FLASH->ACR |= FLASH_ACR_PRFTBE; 608 | 609 | /* Flash 0 wait state */ 610 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 611 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0; 612 | #endif 613 | 614 | /* HCLK = SYSCLK */ 615 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 616 | 617 | /* PCLK2 = HCLK */ 618 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 619 | 620 | /* PCLK1 = HCLK */ 621 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; 622 | 623 | #ifdef STM32F10X_CL 624 | /* Configure PLLs ------------------------------------------------------*/ 625 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ 626 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); 627 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 628 | RCC_CFGR_PLLMULL6); 629 | 630 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ 631 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ 632 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | 633 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); 634 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | 635 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); 636 | 637 | /* Enable PLL2 */ 638 | RCC->CR |= RCC_CR_PLL2ON; 639 | /* Wait till PLL2 is ready */ 640 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) 641 | { 642 | } 643 | #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 644 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ 645 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 646 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6); 647 | #else 648 | /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ 649 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 650 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6); 651 | #endif /* STM32F10X_CL */ 652 | 653 | /* Enable PLL */ 654 | RCC->CR |= RCC_CR_PLLON; 655 | 656 | /* Wait till PLL is ready */ 657 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 658 | { 659 | } 660 | 661 | /* Select PLL as system clock source */ 662 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 663 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 664 | 665 | /* Wait till PLL is used as system clock source */ 666 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 667 | { 668 | } 669 | } 670 | else 671 | { /* If HSE fails to start-up, the application will have wrong clock 672 | configuration. User can add here some code to deal with this error */ 673 | } 674 | } 675 | #elif defined SYSCLK_FREQ_36MHz 676 | /** 677 | * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 678 | * and PCLK1 prescalers. 679 | * @note This function should be used only after reset. 680 | * @param None 681 | * @retval None 682 | */ 683 | static void SetSysClockTo36(void) 684 | { 685 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 686 | 687 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ 688 | /* Enable HSE */ 689 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 690 | 691 | /* Wait till HSE is ready and if Time out is reached exit */ 692 | do 693 | { 694 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 695 | StartUpCounter++; 696 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 697 | 698 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 699 | { 700 | HSEStatus = (uint32_t)0x01; 701 | } 702 | else 703 | { 704 | HSEStatus = (uint32_t)0x00; 705 | } 706 | 707 | if (HSEStatus == (uint32_t)0x01) 708 | { 709 | /* Enable Prefetch Buffer */ 710 | FLASH->ACR |= FLASH_ACR_PRFTBE; 711 | 712 | /* Flash 1 wait state */ 713 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 714 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; 715 | 716 | /* HCLK = SYSCLK */ 717 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 718 | 719 | /* PCLK2 = HCLK */ 720 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 721 | 722 | /* PCLK1 = HCLK */ 723 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; 724 | 725 | #ifdef STM32F10X_CL 726 | /* Configure PLLs ------------------------------------------------------*/ 727 | 728 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ 729 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); 730 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 731 | RCC_CFGR_PLLMULL9); 732 | 733 | /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ 734 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ 735 | 736 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | 737 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); 738 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | 739 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); 740 | 741 | /* Enable PLL2 */ 742 | RCC->CR |= RCC_CR_PLL2ON; 743 | /* Wait till PLL2 is ready */ 744 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) 745 | { 746 | } 747 | 748 | #else 749 | /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ 750 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 751 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9); 752 | #endif /* STM32F10X_CL */ 753 | 754 | /* Enable PLL */ 755 | RCC->CR |= RCC_CR_PLLON; 756 | 757 | /* Wait till PLL is ready */ 758 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 759 | { 760 | } 761 | 762 | /* Select PLL as system clock source */ 763 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 764 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 765 | 766 | /* Wait till PLL is used as system clock source */ 767 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 768 | { 769 | } 770 | } 771 | else 772 | { /* If HSE fails to start-up, the application will have wrong clock 773 | configuration. User can add here some code to deal with this error */ 774 | } 775 | } 776 | #elif defined SYSCLK_FREQ_48MHz 777 | /** 778 | * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 779 | * and PCLK1 prescalers. 780 | * @note This function should be used only after reset. 781 | * @param None 782 | * @retval None 783 | */ 784 | static void SetSysClockTo48(void) 785 | { 786 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 787 | 788 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ 789 | /* Enable HSE */ 790 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 791 | 792 | /* Wait till HSE is ready and if Time out is reached exit */ 793 | do 794 | { 795 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 796 | StartUpCounter++; 797 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 798 | 799 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 800 | { 801 | HSEStatus = (uint32_t)0x01; 802 | } 803 | else 804 | { 805 | HSEStatus = (uint32_t)0x00; 806 | } 807 | 808 | if (HSEStatus == (uint32_t)0x01) 809 | { 810 | /* Enable Prefetch Buffer */ 811 | FLASH->ACR |= FLASH_ACR_PRFTBE; 812 | 813 | /* Flash 1 wait state */ 814 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 815 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1; 816 | 817 | /* HCLK = SYSCLK */ 818 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 819 | 820 | /* PCLK2 = HCLK */ 821 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 822 | 823 | /* PCLK1 = HCLK */ 824 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 825 | 826 | #ifdef STM32F10X_CL 827 | /* Configure PLLs ------------------------------------------------------*/ 828 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ 829 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ 830 | 831 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | 832 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); 833 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | 834 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); 835 | 836 | /* Enable PLL2 */ 837 | RCC->CR |= RCC_CR_PLL2ON; 838 | /* Wait till PLL2 is ready */ 839 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) 840 | { 841 | } 842 | 843 | 844 | /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ 845 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); 846 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 847 | RCC_CFGR_PLLMULL6); 848 | #else 849 | /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ 850 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 851 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6); 852 | #endif /* STM32F10X_CL */ 853 | 854 | /* Enable PLL */ 855 | RCC->CR |= RCC_CR_PLLON; 856 | 857 | /* Wait till PLL is ready */ 858 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 859 | { 860 | } 861 | 862 | /* Select PLL as system clock source */ 863 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 864 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 865 | 866 | /* Wait till PLL is used as system clock source */ 867 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 868 | { 869 | } 870 | } 871 | else 872 | { /* If HSE fails to start-up, the application will have wrong clock 873 | configuration. User can add here some code to deal with this error */ 874 | } 875 | } 876 | 877 | #elif defined SYSCLK_FREQ_56MHz 878 | /** 879 | * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 880 | * and PCLK1 prescalers. 881 | * @note This function should be used only after reset. 882 | * @param None 883 | * @retval None 884 | */ 885 | static void SetSysClockTo56(void) 886 | { 887 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 888 | 889 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ 890 | /* Enable HSE */ 891 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 892 | 893 | /* Wait till HSE is ready and if Time out is reached exit */ 894 | do 895 | { 896 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 897 | StartUpCounter++; 898 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 899 | 900 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 901 | { 902 | HSEStatus = (uint32_t)0x01; 903 | } 904 | else 905 | { 906 | HSEStatus = (uint32_t)0x00; 907 | } 908 | 909 | if (HSEStatus == (uint32_t)0x01) 910 | { 911 | /* Enable Prefetch Buffer */ 912 | FLASH->ACR |= FLASH_ACR_PRFTBE; 913 | 914 | /* Flash 2 wait state */ 915 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 916 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 917 | 918 | /* HCLK = SYSCLK */ 919 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 920 | 921 | /* PCLK2 = HCLK */ 922 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 923 | 924 | /* PCLK1 = HCLK */ 925 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 926 | 927 | #ifdef STM32F10X_CL 928 | /* Configure PLLs ------------------------------------------------------*/ 929 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ 930 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ 931 | 932 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | 933 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); 934 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | 935 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); 936 | 937 | /* Enable PLL2 */ 938 | RCC->CR |= RCC_CR_PLL2ON; 939 | /* Wait till PLL2 is ready */ 940 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) 941 | { 942 | } 943 | 944 | 945 | /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ 946 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); 947 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 948 | RCC_CFGR_PLLMULL7); 949 | #else 950 | /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ 951 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 952 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7); 953 | 954 | #endif /* STM32F10X_CL */ 955 | 956 | /* Enable PLL */ 957 | RCC->CR |= RCC_CR_PLLON; 958 | 959 | /* Wait till PLL is ready */ 960 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 961 | { 962 | } 963 | 964 | /* Select PLL as system clock source */ 965 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 966 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 967 | 968 | /* Wait till PLL is used as system clock source */ 969 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 970 | { 971 | } 972 | } 973 | else 974 | { /* If HSE fails to start-up, the application will have wrong clock 975 | configuration. User can add here some code to deal with this error */ 976 | } 977 | } 978 | 979 | #elif defined SYSCLK_FREQ_72MHz 980 | /** 981 | * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 982 | * and PCLK1 prescalers. 983 | * @note This function should be used only after reset. 984 | * @param None 985 | * @retval None 986 | */ 987 | static void SetSysClockTo72(void) 988 | { 989 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 990 | 991 | /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ 992 | /* Enable HSE */ 993 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 994 | 995 | /* Wait till HSE is ready and if Time out is reached exit */ 996 | do 997 | { 998 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 999 | StartUpCounter++; 1000 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 1001 | 1002 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 1003 | { 1004 | HSEStatus = (uint32_t)0x01; 1005 | } 1006 | else 1007 | { 1008 | HSEStatus = (uint32_t)0x00; 1009 | } 1010 | 1011 | if (HSEStatus == (uint32_t)0x01) 1012 | { 1013 | /* Enable Prefetch Buffer */ 1014 | FLASH->ACR |= FLASH_ACR_PRFTBE; 1015 | 1016 | /* Flash 2 wait state */ 1017 | FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); 1018 | FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2; 1019 | 1020 | 1021 | /* HCLK = SYSCLK */ 1022 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 1023 | 1024 | /* PCLK2 = HCLK */ 1025 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; 1026 | 1027 | /* PCLK1 = HCLK */ 1028 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; 1029 | 1030 | #ifdef STM32F10X_CL 1031 | /* Configure PLLs ------------------------------------------------------*/ 1032 | /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ 1033 | /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ 1034 | 1035 | RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | 1036 | RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); 1037 | RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | 1038 | RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); 1039 | 1040 | /* Enable PLL2 */ 1041 | RCC->CR |= RCC_CR_PLL2ON; 1042 | /* Wait till PLL2 is ready */ 1043 | while((RCC->CR & RCC_CR_PLL2RDY) == 0) 1044 | { 1045 | } 1046 | 1047 | 1048 | /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 1049 | RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); 1050 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 | 1051 | RCC_CFGR_PLLMULL9); 1052 | #else 1053 | /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ 1054 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | 1055 | RCC_CFGR_PLLMULL)); 1056 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9); 1057 | #endif /* STM32F10X_CL */ 1058 | 1059 | /* Enable PLL */ 1060 | RCC->CR |= RCC_CR_PLLON; 1061 | 1062 | /* Wait till PLL is ready */ 1063 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 1064 | { 1065 | } 1066 | 1067 | /* Select PLL as system clock source */ 1068 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 1069 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 1070 | 1071 | /* Wait till PLL is used as system clock source */ 1072 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) 1073 | { 1074 | } 1075 | } 1076 | else 1077 | { /* If HSE fails to start-up, the application will have wrong clock 1078 | configuration. User can add here some code to deal with this error */ 1079 | } 1080 | } 1081 | #endif 1082 | 1083 | /** 1084 | * @} 1085 | */ 1086 | 1087 | /** 1088 | * @} 1089 | */ 1090 | 1091 | /** 1092 | * @} 1093 | */ 1094 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 1095 | -------------------------------------------------------------------------------- /RemoteSwitchHUB.inf: -------------------------------------------------------------------------------- 1 | ; Windows USB CDC ACM Setup File 2 | ; Copyright (c) 2000 Microsoft Corporation 3 | ; Copyright (C) 2007 Microchip Technology Inc. 4 | 5 | [Version] 6 | Signature="$Windows NT$" 7 | Class=Ports 8 | ClassGuid={4D36E978-E325-11CE-BFC1-08002BE10318} 9 | Provider=%MFGNAME% 10 | LayoutFile=layout.inf 11 | ;CatalogFile=%MFGFILENAME%.cat 12 | ;DriverVer=02/16/2011,1.0 13 | DriverVer=12/03/2009,5.1.2600.3 14 | 15 | [Manufacturer] 16 | %MFGNAME%=DeviceList, NTamd64 17 | 18 | [DestinationDirs] 19 | DefaultDestDir=12 20 | ;------------------------------------------------------------------------------ 21 | ; Windows 2000/XP/Vista-32bit Sections 22 | ;------------------------------------------------------------------------------ 23 | 24 | [DriverInstall.NT] 25 | include=mdmcpq.inf 26 | CopyFiles=DriverCopyFiles.NT 27 | AddReg=DriverInstall.NT.AddReg 28 | 29 | [DriverInstall.NT.HW] 30 | AddReg=DriverInstall.NT.HW.AddReg 31 | 32 | [DriverCopyFiles.NT] 33 | %DRIVERFILENAME%.sys,,,0x20 34 | 35 | [DriverInstall.NT.AddReg] 36 | HKR,,DevLoader,,*ntkern 37 | HKR,,NTMPDriver,,%DRIVERFILENAME%.sys 38 | HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" 39 | 40 | [DriverInstall.NT.HW.AddReg] 41 | HKR,,"UpperFilters",0x00010000,%FILTERDRIVERFILENAME% 42 | ;HKR,,"ConfigData",1,01,04,00,00,10,27,88,13,C4,09,E2,04,71,02,38,41,9c,80,4E,C0,34,00,1A,00,0D,00,06,40,03,80,00,00,d0,80 43 | ;HKR,,"ConfigData",1,11,04,00,00,10,27,00,00,88,13,00,00,C4,09,00,00,E2,04,00,00,71,02,00,00,38,41,00,00,9C,80,00,00,4E,C0,00,00,34,00,00,00,1A,00,00,00,0D,00,00,00,06,40,00,00,03,80,00,00,00,00,00,00,D0,80,00,00 44 | ;HKR,,"MinReadTimeout",0x00010001,0 45 | ;HKR,,"MinWriteTimeout",0x00010001,0 46 | ;HKR,,"LatencyTimer",0x00010001,2 47 | 48 | [DriverInstall.NT.Services] 49 | AddService =%DRIVERFILENAME%, 0x00000002, DriverService.NT 50 | AddService =%FILTERDRIVERFILENAME%,,SerenumService 51 | 52 | [DriverService.NT] 53 | DisplayName=%SERVICE% 54 | ServiceType=1 55 | StartType=3 56 | ErrorControl=1 57 | ServiceBinary=%12%\%DRIVERFILENAME%.sys 58 | ;------------------------------------------------------------------------------ 59 | ; Vista-64bit Sections 60 | ;------------------------------------------------------------------------------ 61 | [DriverInstall.NTamd64] 62 | include=mdmcpq.inf 63 | CopyFiles=DriverCopyFiles.NTamd64 64 | AddReg=DriverInstall.NTamd64.AddReg 65 | 66 | [DriverInstall.NTamd64.HW] 67 | AddReg=DriverInstall.NTamd64.HW.AddReg 68 | 69 | [DriverCopyFiles.NTamd64] 70 | %DRIVERFILENAME%.sys,,,0x20 71 | 72 | [DriverInstall.NTamd64.AddReg] 73 | HKR,,DevLoader,,*ntkern 74 | HKR,,NTMPDriver,,%DRIVERFILENAME%.sys 75 | HKR,,EnumPropPages32,,"MsPorts.dll,SerialPortPropPageProvider" 76 | 77 | [DriverInstall.NTamd64.HW.AddReg] 78 | HKR,,"UpperFilters",0x00010000,%FILTERDRIVERFILENAME% 79 | 80 | [DriverInstall.NTamd64.Services] 81 | AddService=%DRIVERFILENAME%, 0x00000002, DriverService.NTamd64 82 | AddService =%FILTERDRIVERFILENAME%,,SerenumService 83 | 84 | [DriverService.NTamd64] 85 | DisplayName=%SERVICE% 86 | ServiceType=1 87 | StartType=3 88 | ErrorControl=1 89 | ServiceBinary=%12%\%DRIVERFILENAME%.sys 90 | 91 | [SerenumService] 92 | DisplayName = %SERENUMDESC% 93 | ServiceType = 1 ; SERVICE_KERNEL_DRIVER 94 | StartType = 3 ; SERVICE_DEMAND_START 95 | ErrorControl = 1 ; SERVICE_ERROR_NORMAL 96 | ServiceBinary = %12%\%FILTERDRIVERFILENAME%.sys 97 | LoadOrderGroup = PNP Filter 98 | 99 | [SourceDisksFiles] 100 | [SourceDisksNames] 101 | ;------------------------------------------------------------------------------ 102 | ; Vendor and Product ID Definitions 103 | ;------------------------------------------------------------------------------ 104 | [DeviceList] 105 | %DESCRIPTION%=DriverInstall, USB\VID_25AE&PID_24AB 106 | 107 | [DeviceList.NTamd64] 108 | %DESCRIPTION%=DriverInstall, USB\VID_25AE&PID_24AB 109 | ;------------------------------------------------------------------------------ 110 | ; String Definitions 111 | ;------------------------------------------------------------------------------ 112 | [Strings] 113 | MFGFILENAME="RemoteSwitchHUB" 114 | DRIVERFILENAME ="usbser" 115 | MFGNAME="SaeWave.com" 116 | DESCRIPTION="RemoteSwitch HUB" 117 | SERVICE="RemoteSwitch HUB driver" 118 | FILTERDRIVERFILENAME ="serenum" 119 | SERENUMDESC = "Serenum Filter Driver" 120 | ;DEVINTERFACE_COMPORT="{86E0D1E0-8089-11D0-9CE4-08003E301F73}" 121 | -------------------------------------------------------------------------------- /STM32F103-USB-CDC-CMSIS.uvoptx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 1.0 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | *.c 10 | *.s*; *.src; *.a* 11 | *.obj 12 | *.lib 13 | *.txt; *.h; *.inc 14 | *.plm 15 | *.cpp 16 | 0 17 | 18 | 19 | 20 | 0 21 | 0 22 | 23 | 24 | 25 | STM32F103-USB-CDC-CMSIS 26 | 0x4 27 | ARM-ADS 28 | 29 | 12000000 30 | 31 | 1 32 | 1 33 | 0 34 | 1 35 | 0 36 | 37 | 38 | 1 39 | 65535 40 | 0 41 | 0 42 | 0 43 | 44 | 45 | 79 46 | 66 47 | 8 48 | .\Listings\ 49 | 50 | 51 | 1 52 | 1 53 | 1 54 | 0 55 | 1 56 | 1 57 | 0 58 | 1 59 | 0 60 | 0 61 | 0 62 | 0 63 | 64 | 65 | 1 66 | 1 67 | 1 68 | 1 69 | 1 70 | 1 71 | 1 72 | 0 73 | 0 74 | 75 | 76 | 1 77 | 0 78 | 1 79 | 80 | 18 81 | 82 | 0 83 | 1 84 | 1 85 | 1 86 | 1 87 | 1 88 | 1 89 | 1 90 | 1 91 | 1 92 | 1 93 | 1 94 | 1 95 | 1 96 | 0 97 | 1 98 | 1 99 | 1 100 | 1 101 | 0 102 | 0 103 | 1 104 | 11 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | STLink\ST-LINKIII-KEIL_SWO.dll 116 | 117 | 118 | 119 | 0 120 | ARMRTXEVENTFLAGS 121 | -L50 -Z18 -C0 -M0 -T0 122 | 123 | 124 | 0 125 | DLGTARM 126 | (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)(1009=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(1011=-1,-1,-1,-1,0)(180=-1,-1,-1,-1,0)(120=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(123=-1,-1,-1,-1,0)(140=-1,-1,-1,-1,0)(240=-1,-1,-1,-1,0)(190=-1,-1,-1,-1,0)(200=-1,-1,-1,-1,0)(170=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(133=-1,-1,-1,-1,0)(160=-1,-1,-1,-1,0)(161=-1,-1,-1,-1,0)(162=-1,-1,-1,-1,0)(210=-1,-1,-1,-1,0)(211=-1,-1,-1,-1,0)(220=-1,-1,-1,-1,0)(221=-1,-1,-1,-1,0)(230=-1,-1,-1,-1,0)(231=-1,-1,-1,-1,0)(232=-1,-1,-1,-1,0)(233=-1,-1,-1,-1,0)(150=-1,-1,-1,-1,0)(151=-1,-1,-1,-1,0) 127 | 128 | 129 | 0 130 | ARMDBGFLAGS 131 | 132 | 133 | 134 | 0 135 | DLGUARM 136 | (105=-1,-1,-1,-1,0) 137 | 138 | 139 | 0 140 | ST-LINKIII-KEIL_SWO 141 | -U066CFF525056805087065634 -O2254 -SF4000 -C0 -A0 -I0 -HNlocalhost -HP7184 -P2 -N00("ARM CoreSight SW-DP") -D00(1BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8004 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128.FLM -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM) 142 | 143 | 144 | 0 145 | UL2CM3 146 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash\STM32F10x_128.FLM)) 147 | 148 | 149 | 150 | 151 | 152 | 0 153 | 1 154 | USBLIB_EPBufTable 155 | 156 | 157 | 158 | 159 | 0 160 | 2 161 | SetupPacket 162 | 163 | 164 | 1 165 | 2 166 | EpData 167 | 168 | 169 | 2 170 | 2 171 | EPBufTable 172 | 173 | 174 | 3 175 | 2 176 | LogPassIdx 177 | 178 | 179 | 4 180 | 2 181 | Log 182 | 183 | 184 | 5 185 | 2 186 | lineCoding 187 | 188 | 189 | 190 | 191 | 1 192 | 0 193 | 0x20000110 194 | 0 195 | 196 | 197 | 198 | 199 | 2 200 | 0 201 | 0x40006080 202 | 0 203 | 204 | 205 | 206 | 0 207 | 208 | 209 | 0 210 | 1 211 | 0 212 | 0 213 | 0 214 | 0 215 | 0 216 | 1 217 | 0 218 | 0 219 | 0 220 | 0 221 | 0 222 | 0 223 | 0 224 | 0 225 | 0 226 | 0 227 | 0 228 | 0 229 | 0 230 | 0 231 | 0 232 | 0 233 | 234 | 235 | 236 | 0 237 | 0 238 | 0 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | System Viewer\TIM1 250 | 35904 251 | 252 | 253 | System Viewer\USB 254 | 35905 255 | 256 | 257 | 258 | 1 259 | 0 260 | 2 261 | 10000000 262 | 263 | 264 | 265 | 266 | 267 | Main 268 | 1 269 | 0 270 | 0 271 | 0 272 | 273 | 1 274 | 1 275 | 1 276 | 0 277 | 0 278 | 0 279 | .\Src\main.c 280 | main.c 281 | 0 282 | 0 283 | 284 | 285 | 1 286 | 2 287 | 1 288 | 0 289 | 0 290 | 0 291 | .\Src\usblib.c 292 | usblib.c 293 | 0 294 | 0 295 | 296 | 297 | 298 | 299 | ::CMSIS 300 | 0 301 | 0 302 | 0 303 | 1 304 | 305 | 306 | 307 | ::Device 308 | 1 309 | 0 310 | 0 311 | 1 312 | 313 | 314 | 315 | -------------------------------------------------------------------------------- /STM32F103-USB-CDC-CMSIS.uvprojx: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 2.1 5 | 6 |
### uVision Project, (C) Keil Software
7 | 8 | 9 | 10 | STM32F103-USB-CDC-CMSIS 11 | 0x4 12 | ARM-ADS 13 | 5060528::V5.06 update 5 (build 528)::ARMCC 14 | 0 15 | 16 | 17 | STM32F103C8 18 | STMicroelectronics 19 | Keil.STM32F1xx_DFP.2.2.0 20 | http://www.keil.com/pack/ 21 | IROM(0x08000000,0x10000) IRAM(0x20000000,0x5000) CPUTYPE("Cortex-M3") CLOCK(12000000) ELITTLE 22 | 23 | 24 | UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F10x_128 -FS08000000 -FL020000 -FP0($$Device:STM32F103C8$Flash/STM32F10x_128.FLM)) 25 | 4235 26 | $$Device:STM32F103C8$Device/Include/stm32f10x.h 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | $$Device:STM32F103C8$SVD\STM32F103xx.svd 37 | 0 38 | 0 39 | 40 | 41 | 42 | 43 | 44 | 45 | 0 46 | 0 47 | 0 48 | 0 49 | 1 50 | 51 | .\Objects\ 52 | STM32F103-USB-CDC-CMSIS 53 | 1 54 | 0 55 | 0 56 | 1 57 | 1 58 | .\Listings\ 59 | 1 60 | 0 61 | 0 62 | 63 | 0 64 | 0 65 | 66 | 67 | 0 68 | 0 69 | 0 70 | 0 71 | 72 | 73 | 0 74 | 0 75 | 76 | 77 | 0 78 | 0 79 | 0 80 | 0 81 | 82 | 83 | 0 84 | 0 85 | 86 | 87 | 0 88 | 0 89 | 0 90 | 0 91 | 92 | 0 93 | 94 | 95 | 96 | 0 97 | 0 98 | 0 99 | 0 100 | 0 101 | 1 102 | 0 103 | 0 104 | 0 105 | 0 106 | 3 107 | 108 | 109 | 1 110 | 111 | 112 | SARMCM3.DLL 113 | 114 | DARMSTM.DLL 115 | -pSTM32F103C8 116 | SARMCM3.DLL 117 | 118 | TARMSTM.DLL 119 | -pSTM32F103C8 120 | 121 | 122 | 123 | 1 124 | 0 125 | 0 126 | 0 127 | 16 128 | 129 | 130 | 131 | 132 | 1 133 | 0 134 | 0 135 | 1 136 | 1 137 | 4096 138 | 139 | 1 140 | BIN\UL2CM3.DLL 141 | "" () 142 | 143 | 144 | 145 | 146 | 0 147 | 148 | 149 | 150 | 0 151 | 1 152 | 1 153 | 1 154 | 1 155 | 1 156 | 1 157 | 1 158 | 0 159 | 1 160 | 1 161 | 0 162 | 1 163 | 1 164 | 0 165 | 0 166 | 1 167 | 1 168 | 1 169 | 1 170 | 1 171 | 1 172 | 1 173 | 1 174 | 1 175 | 0 176 | 0 177 | "Cortex-M3" 178 | 179 | 0 180 | 0 181 | 0 182 | 1 183 | 1 184 | 0 185 | 0 186 | 0 187 | 0 188 | 0 189 | 8 190 | 0 191 | 0 192 | 0 193 | 0 194 | 3 195 | 3 196 | 0 197 | 0 198 | 0 199 | 0 200 | 0 201 | 0 202 | 0 203 | 0 204 | 0 205 | 0 206 | 1 207 | 0 208 | 0 209 | 0 210 | 0 211 | 1 212 | 0 213 | 214 | 215 | 0 216 | 0x0 217 | 0x0 218 | 219 | 220 | 0 221 | 0x0 222 | 0x0 223 | 224 | 225 | 0 226 | 0x0 227 | 0x0 228 | 229 | 230 | 0 231 | 0x0 232 | 0x0 233 | 234 | 235 | 0 236 | 0x0 237 | 0x0 238 | 239 | 240 | 0 241 | 0x0 242 | 0x0 243 | 244 | 245 | 0 246 | 0x20000000 247 | 0x5000 248 | 249 | 250 | 1 251 | 0x8000000 252 | 0x10000 253 | 254 | 255 | 0 256 | 0x0 257 | 0x0 258 | 259 | 260 | 1 261 | 0x0 262 | 0x0 263 | 264 | 265 | 1 266 | 0x0 267 | 0x0 268 | 269 | 270 | 1 271 | 0x0 272 | 0x0 273 | 274 | 275 | 1 276 | 0x8000000 277 | 0x10000 278 | 279 | 280 | 1 281 | 0x0 282 | 0x0 283 | 284 | 285 | 0 286 | 0x0 287 | 0x0 288 | 289 | 290 | 0 291 | 0x0 292 | 0x0 293 | 294 | 295 | 0 296 | 0x0 297 | 0x0 298 | 299 | 300 | 0 301 | 0x20000000 302 | 0x5000 303 | 304 | 305 | 0 306 | 0x0 307 | 0x0 308 | 309 | 310 | 311 | 312 | 313 | 1 314 | 4 315 | 0 316 | 0 317 | 0 318 | 0 319 | 0 320 | 0 321 | 0 322 | 0 323 | 2 324 | 0 325 | 0 326 | 1 327 | 0 328 | 1 329 | 1 330 | 1 331 | 1 332 | 0 333 | 0 334 | 0 335 | 336 | 337 | 338 | 339 | .\Inc 340 | 341 | 342 | 343 | 1 344 | 0 345 | 0 346 | 0 347 | 0 348 | 0 349 | 0 350 | 0 351 | 0 352 | 0 353 | 354 | 355 | 356 | 357 | 358 | 359 | 360 | 361 | 1 362 | 0 363 | 0 364 | 0 365 | 1 366 | 0 367 | 0x08000000 368 | 0x20000000 369 | 370 | .\Objects\STM32F103-USB-CDC-CMSIS.sct 371 | 372 | 373 | 374 | 375 | 376 | 377 | 378 | 379 | 380 | 381 | Main 382 | 383 | 384 | main.c 385 | 1 386 | .\Src\main.c 387 | 388 | 389 | usblib.c 390 | 1 391 | .\Src\usblib.c 392 | 393 | 394 | 395 | 396 | ::CMSIS 397 | 398 | 399 | ::Device 400 | 401 | 402 | 403 | 404 | 405 | 406 | 407 | 408 | 409 | 410 | 411 | 412 | 413 | 414 | 415 | 416 | 417 | 418 | 419 | 420 | 421 | 422 | 423 | RTE\Device\STM32F103C8\RTE_Device.h 424 | 425 | 426 | 427 | 428 | 429 | 430 | 431 | RTE\Device\STM32F103C8\startup_stm32f10x_md.s 432 | 433 | 434 | 435 | 436 | 437 | 438 | 439 | RTE\Device\STM32F103C8\system_stm32f10x.c 440 | 441 | 442 | 443 | 444 | 445 | 446 | 447 | 448 | 449 | 450 | -------------------------------------------------------------------------------- /Src/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the SaeWave RemoteSwitch (USB-CDC-CMSIS) 3 | * distribution (https://github.com/saewave/STM32F103-USB-CDC-CMSIS). 4 | * Copyright (c) 2017 Samoilov Alexey. 5 | * 6 | * This program is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation, version 3. 9 | * 10 | * This program is distributed in the hope that it will be useful, but 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #include "stm32f10x.h" 20 | #include "usblib.h" 21 | 22 | USBLIB_WByte _LineState; 23 | 24 | int main(void) 25 | { 26 | 27 | /* ============ 48 MHz ============= */ 28 | RCC->CFGR &= ~RCC_CFGR_SW; // Change System Clock to HSI 29 | while ((RCC->CFGR & RCC_CFGR_SWS) != 0x00) { 30 | __NOP(); 31 | }; 32 | RCC->CR &= ~RCC_CR_PLLON; // Disable Pll 33 | while ((RCC->CR & RCC_CR_PLLON)) { 34 | __NOP(); 35 | }; 36 | RCC->CFGR &= ~0x3C0000; 37 | RCC->CFGR |= RCC_CFGR_PLLMULL4; // Set Pll Mul to 4 38 | RCC->CFGR |= RCC_CFGR_USBPRE; 39 | RCC->CFGR |= RCC_CFGR_PLLSRC; 40 | RCC->CR |= RCC_CR_PLLON; 41 | while (!(RCC->CR & RCC_CR_PLLON)) { 42 | __NOP(); 43 | }; 44 | RCC->CFGR |= RCC_CFGR_SW_1; // Change System Clock to PLL 45 | while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1) { 46 | __NOP(); 47 | }; 48 | 49 | RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_AFIOEN; 50 | /* ========= PB13 USB CONNECT ========= */ 51 | /* PB12 - LED. Output PP */ 52 | GPIOB->CRH |= GPIO_CRH_MODE12_0; 53 | GPIOB->CRH &= ~GPIO_CRH_CNF12; 54 | 55 | /* PB13 - USB EN. Output PP */ 56 | GPIOB->CRH |= GPIO_CRH_MODE13_0; 57 | GPIOB->CRH &= ~GPIO_CRH_CNF13; 58 | 59 | /* =========== TIM1 ========== */ 60 | RCC->APB2ENR |= RCC_APB2ENR_TIM1EN; 61 | TIM1->PSC = 1000 - 1; 62 | TIM1->ARR = 48000 - 1; 63 | TIM1->DIER |= TIM_DIER_UIE; 64 | //TIM1->CR1 = TIM_CR1_CEN | TIM_CR1_ARPE; 65 | NVIC_SetPriority(TIM1_UP_IRQn, 15); 66 | NVIC_EnableIRQ(TIM1_UP_IRQn); 67 | 68 | GPIOB->ODR &= ~GPIO_ODR_ODR13; //LOW 69 | for (int i = 0; i < 1000000; i++) { 70 | __NOP(); 71 | }; 72 | 73 | USBLIB_Init(); 74 | GPIOB->ODR |= GPIO_ODR_ODR13; //UP 75 | 76 | while (1) {}; 77 | } 78 | 79 | void TIM1_UP_IRQHandler() { 80 | TIM1->SR &= ~TIM_SR_UIF; 81 | GPIOB->ODR ^= GPIO_ODR_ODR12; 82 | 83 | if (_LineState.L) { //App connected to the virtual port 84 | USBLIB_Transmit((uint16_t *)"Welcome to the club!\r\n", 22); 85 | } else { 86 | USBLIB_Transmit((uint16_t *)"Bye bye!\r\n", 10); 87 | } 88 | } 89 | 90 | void uUSBLIB_DataReceivedHandler(uint16_t *Data, uint16_t Length) 91 | { 92 | USBLIB_Transmit(Data, Length); 93 | } 94 | 95 | void uUSBLIB_LineStateHandler(USBLIB_WByte LineState) 96 | { 97 | if (LineState.L) { //App connected to the virtual port 98 | _LineState = LineState; 99 | TIM1->CR1 = TIM_CR1_CEN | TIM_CR1_ARPE; 100 | } 101 | } 102 | -------------------------------------------------------------------------------- /Src/usblib.c: -------------------------------------------------------------------------------- 1 | /* 2 | * This file is part of the SaeWave RemoteSwitch (USB-CDC-CMSIS) 3 | * distribution (https://github.com/saewave/STM32F103-USB-CDC-CMSIS). 4 | * Copyright (c) 2017 Samoilov Alexey. 5 | * 6 | * This program is free software: you can redistribute it and/or modify 7 | * it under the terms of the GNU General Public License as published by 8 | * the Free Software Foundation, version 3. 9 | * 10 | * This program is distributed in the hope that it will be useful, but 11 | * WITHOUT ANY WARRANTY; without even the implied warranty of 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | * General Public License for more details. 14 | * 15 | * You should have received a copy of the GNU General Public License 16 | * along with this program. If not, see . 17 | */ 18 | 19 | #include "usblib.h" 20 | #include "stm32f10x.h" 21 | #include 22 | #include 23 | 24 | volatile USB_TypeDef *USB = (USB_TypeDef *)USB_BASE; 25 | volatile USBLIB_EPBuf EPBufTable[EPCOUNT] __attribute__((at(USB_PBUFFER))); 26 | volatile uint32_t USBEP[EPCOUNT] __attribute__((at(USB_BASE))); 27 | USBLIB_SetupPacket *SetupPacket; 28 | volatile uint8_t DeviceAddress = 0; 29 | volatile USBLIB_WByte LineState; 30 | 31 | USBLIB_EPData EpData[EPCOUNT] = 32 | { 33 | {0, EP_CONTROL, 8, 8, 0, 0, 0, 0, 64, 0}, 34 | {1, EP_INTERRUPT, 16, 16, 0, 0, 0, 0, 64, 0}, 35 | {2, EP_BULK, 64, 64, 0, 0, 0, 0, 64, 0}, //IN (Device -> Host) 36 | {3, EP_BULK, 64, 64, 0, 0, 0, 0, 64, 0}}; //OUT (Host -> Device) 37 | 38 | void USBLIB_Init(void) 39 | { 40 | NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn); 41 | RCC->APB1ENR |= RCC_APB1ENR_USBEN; 42 | 43 | USB->CNTR = USB_CNTR_FRES; /* Force USB Reset */ 44 | USB->BTABLE = 0; 45 | USB->DADDR = 0; 46 | USB->ISTR = 0; 47 | USB->CNTR = USB_CNTR_RESETM; 48 | NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); 49 | } 50 | 51 | USBLIB_LineCoding lineCoding = {115200, 0, 0, 8}; 52 | 53 | const uint8_t USB_DEVICE_DESC[] = 54 | { 55 | (uint8_t)18, // bLength 56 | (uint8_t)USB_DEVICE_DESC_TYPE, // bDescriptorType 57 | (uint8_t)0x00, // bcdUSB 58 | (uint8_t)0x02, // bcdUSB 59 | (uint8_t)USB_COMM, // bDeviceClass 60 | (uint8_t)0, // bDeviceSubClass 61 | (uint8_t)0, // bDeviceProtocol 62 | (uint8_t)8, // bMaxPacketSize0 63 | (uint8_t)LOBYTE(DEVICE_VENDOR_ID), // idVendor 64 | (uint8_t)HIBYTE(DEVICE_VENDOR_ID), // idVendor 65 | (uint8_t)LOBYTE(DEVICE_PRODUCT_ID), // idProduct 66 | (uint8_t)HIBYTE(DEVICE_PRODUCT_ID), // idProduct 67 | (uint8_t)0x00, // bcdDevice 68 | (uint8_t)0x01, // bcdDevice 69 | (uint8_t)1, // iManufacturer 70 | (uint8_t)2, // iProduct 71 | (uint8_t)3, // iSerialNumbert 72 | (uint8_t)1 // bNumConfigurations 73 | }; 74 | const uint8_t USBD_CDC_CFG_DESCRIPTOR[] = 75 | { 76 | /*Configuration Descriptor*/ 77 | 0x09, /* bLength: Configuration Descriptor size */ 78 | 0x02, /* bDescriptorType: Configuration */ 79 | 67, /* wTotalLength:no of returned bytes */ 80 | 0x00, 81 | 0x02, /* bNumInterfaces: 2 interface */ 82 | 0x01, /* bConfigurationValue: Configuration value */ 83 | 0x00, /* iConfiguration: Index of string descriptor describing the configuration */ 84 | 0x80, /* bmAttributes - Bus powered */ 85 | 0x32, /* MaxPower 100 mA */ 86 | 87 | /*---------------------------------------------------------------------------*/ 88 | 89 | /*Interface Descriptor */ 90 | 0x09, /* bLength: Interface Descriptor size */ 91 | 0x04, /* bDescriptorType: Interface */ 92 | 0x00, /* bInterfaceNumber: Number of Interface */ 93 | 0x00, /* bAlternateSetting: Alternate setting */ 94 | 0x01, /* bNumEndpoints: One endpoints used */ 95 | 0x02, /* bInterfaceClass: Communication Interface Class */ 96 | 0x02, /* bInterfaceSubClass: Abstract Control Model */ 97 | 0x01, /* bInterfaceProtocol: Common AT commands */ 98 | 0x00, /* iInterface: */ 99 | 100 | /*Header Functional Descriptor*/ 101 | 0x05, /* bLength: Endpoint Descriptor size */ 102 | 0x24, /* bDescriptorType: CS_INTERFACE */ 103 | 0x00, /* bDescriptorSubtype: Header Func Desc */ 104 | 0x10, /* bcdCDC: spec release number */ 105 | 0x01, 106 | 107 | /*Call Management Functional Descriptor*/ 108 | 0x05, /* bFunctionLength */ 109 | 0x24, /* bDescriptorType: CS_INTERFACE */ 110 | 0x01, /* bDescriptorSubtype: Call Management Func Desc */ 111 | 0x00, /* bmCapabilities: D0+D1 */ 112 | 0x01, /* bDataInterface: 1 */ 113 | 114 | /*ACM Functional Descriptor*/ 115 | 0x04, /* bFunctionLength */ 116 | 0x24, /* bDescriptorType: CS_INTERFACE */ 117 | 0x02, /* bDescriptorSubtype: Abstract Control Management desc */ 118 | 0x02, /* bmCapabilities */ 119 | 120 | /*Union Functional Descriptor*/ 121 | 0x05, /* bFunctionLength */ 122 | 0x24, /* bDescriptorType: CS_INTERFACE */ 123 | 0x06, /* bDescriptorSubtype: Union func desc */ 124 | 0x00, /* bMasterInterface: Communication class interface */ 125 | 0x01, /* bSlaveInterface0: Data Class Interface */ 126 | 127 | /*Endpoint 2 Descriptor*/ 128 | 0x07, /* bLength: Endpoint Descriptor size */ 129 | 0x05, /* bDescriptorType: Endpoint */ 130 | 0x81, /* bEndpointAddress IN1 */ 131 | 0x03, /* bmAttributes: Interrupt */ 132 | 0x08, /* wMaxPacketSize LO: */ 133 | 0x00, /* wMaxPacketSize HI: */ 134 | 0x10, /* bInterval: */ 135 | /*---------------------------------------------------------------------------*/ 136 | 137 | /*Data class interface descriptor*/ 138 | 0x09, /* bLength: Endpoint Descriptor size */ 139 | 0x04, /* bDescriptorType: */ 140 | 0x01, /* bInterfaceNumber: Number of Interface */ 141 | 0x00, /* bAlternateSetting: Alternate setting */ 142 | 0x02, /* bNumEndpoints: Two endpoints used */ 143 | 0x0A, /* bInterfaceClass: CDC */ 144 | 0x02, /* bInterfaceSubClass: */ 145 | 0x00, /* bInterfaceProtocol: */ 146 | 0x00, /* iInterface: */ 147 | 148 | /*Endpoint IN2 Descriptor*/ 149 | 0x07, /* bLength: Endpoint Descriptor size */ 150 | 0x05, /* bDescriptorType: Endpoint */ 151 | 0x82, /* bEndpointAddress IN2 */ 152 | 0x02, /* bmAttributes: Bulk */ 153 | 64, /* wMaxPacketSize: */ 154 | 0x00, 155 | 0x00, /* bInterval: ignore for Bulk transfer */ 156 | 157 | /*Endpoint OUT3 Descriptor*/ 158 | 0x07, /* bLength: Endpoint Descriptor size */ 159 | 0x05, /* bDescriptorType: Endpoint */ 160 | 0x03, /* bEndpointAddress */ 161 | 0x02, /* bmAttributes: Bulk */ 162 | 64, /* wMaxPacketSize: */ 163 | 0, 164 | 0x00 /* bInterval: ignore for Bulk transfer */ 165 | }; 166 | 167 | /* USB String Descriptors */ 168 | _USB_LANG_ID_(LANG_US); 169 | _USB_STRING_(wsVendor, L"SaeWave.com") 170 | _USB_STRING_(wsProd, L"RemoteSwitch HUB") 171 | _USB_STRING_(wsSN, L"0123-4567-89") 172 | _USB_STRING_(wsCDC, L"CDC Device") 173 | _USB_STRING_(wsCDCData, L"CDC Data") 174 | 175 | void USBLIB_Reset(void) 176 | { 177 | /* *********** WARNING ********** */ 178 | /* We DO NOT CHANGE BTABLE!! So we asume that buffer table start from address 0!!! */ 179 | 180 | uint16_t Addr = sizeof(EPBufTable); 181 | for (uint8_t i = 0; i < EPCOUNT; i++) { 182 | EPBufTable[i].TX_Address.Value = Addr; 183 | EPBufTable[i].TX_Count.Value = 0; 184 | Addr += EpData[i].TX_Max; 185 | EPBufTable[i].RX_Address.Value = Addr; 186 | if (EpData[i].RX_Max >= 64) 187 | EPBufTable[i].RX_Count.Value = 0x8000 | ((EpData[i].RX_Max / 64) << 10); 188 | else 189 | EPBufTable[i].RX_Count.Value = ((EpData[i].RX_Max / 2) << 10); 190 | 191 | Addr += EpData[i].RX_Max; 192 | 193 | if (!EpData[i].pRX_BUFF) 194 | EpData[i].pRX_BUFF = (uint16_t *)malloc(EpData[i].RX_Max); 195 | 196 | USB->EPR[i] = (EpData[i].Number | EpData[i].Type | RX_VALID | TX_NAK); 197 | } 198 | 199 | for (uint8_t i = EPCOUNT; i < 8; i++) { 200 | USB->EPR[i] = i | RX_NAK | TX_NAK; 201 | } 202 | USB->CNTR = USB_CNTR_CTRM | USB_CNTR_RESETM | USB_CNTR_SUSPM; 203 | USB->ISTR = 0x00; 204 | USB->BTABLE = 0x00; 205 | USB->DADDR = USB_DADDR_EF; 206 | } 207 | 208 | void USBLIB_setStatTx(uint8_t EPn, uint16_t Stat) 209 | { 210 | register uint16_t val = USB->EPR[EPn]; 211 | USB->EPR[EPn] = (val ^ (Stat & EP_STAT_TX)) & (EP_MASK | EP_STAT_TX); 212 | } 213 | 214 | void USBLIB_setStatRx(uint8_t EPn, uint16_t Stat) 215 | { 216 | register uint16_t val = USB->EPR[EPn]; 217 | USB->EPR[EPn] = (val ^ (Stat & EP_STAT_RX)) & (EP_MASK | EP_STAT_RX); 218 | } 219 | 220 | void USBLIB_Pma2EPBuf2(uint8_t EPn) 221 | { 222 | uint8_t Count = EpData[EPn].lRX = (EPBufTable[EPn].RX_Count.Value & 0x3FF); 223 | uint32_t *Address = (uint32_t *)(USB_PBUFFER + EPBufTable[EPn].RX_Address.Value * 2); 224 | uint16_t *Distination = (uint16_t *)EpData[EPn].pRX_BUFF; 225 | for (uint8_t i = 0; i < Count; i++) { 226 | *(uint16_t *)Distination = *(uint16_t *)Address; 227 | Distination++; 228 | Address++; 229 | } 230 | } 231 | 232 | void USBLIB_EPBuf2Pma(uint8_t EPn) 233 | { 234 | uint32_t *Distination; 235 | uint8_t Count; 236 | 237 | Count = EpData[EPn].lTX <= EpData[EPn].TX_Max ? EpData[EPn].lTX : EpData[EPn].TX_Max; 238 | EPBufTable[EPn].TX_Count.Value = Count; 239 | 240 | Distination = (uint32_t *)(USB_PBUFFER + EPBufTable[EPn].TX_Address.Value * 2); 241 | for (uint8_t i = 0; i < (Count + 1) / 2; i++) { 242 | *(uint32_t *)Distination = *(uint16_t *)EpData[EPn].pTX_BUFF; 243 | Distination++; 244 | EpData[EPn].pTX_BUFF++; 245 | } 246 | EpData[EPn].lTX -= Count; 247 | } 248 | 249 | void USBLIB_SendData(uint8_t EPn, uint16_t *Data, uint16_t Length) 250 | { 251 | 252 | EpData[EPn].lTX = Length; 253 | EpData[EPn].pTX_BUFF = Data; 254 | if (Length > 0) { 255 | USBLIB_EPBuf2Pma(EPn); 256 | } else { 257 | EPBufTable[EPn].TX_Count.Value = 0; 258 | } 259 | USBLIB_setStatTx(EPn, TX_VALID); 260 | } 261 | 262 | void USBLIB_GetDescriptor(USBLIB_SetupPacket *SPacket) 263 | { 264 | uint8_t c; 265 | USB_STR_DESCRIPTOR *pSTR; 266 | switch (SPacket->wValue.H) { 267 | case USB_DEVICE_DESC_TYPE: 268 | USBLIB_SendData(0, (uint16_t *)&USB_DEVICE_DESC, sizeof(USB_DEVICE_DESC)); 269 | break; 270 | 271 | case USB_CFG_DESC_TYPE: 272 | USBLIB_SendData(0, (uint16_t *)&USBD_CDC_CFG_DESCRIPTOR, sizeof(USBD_CDC_CFG_DESCRIPTOR)); 273 | break; 274 | 275 | case USB_STR_DESC_TYPE: 276 | pSTR = (USB_STR_DESCRIPTOR *)&wLANGID; 277 | 278 | for (c = 0; c < SetupPacket->wValue.L; c++) { 279 | pSTR = (USB_STR_DESCRIPTOR *)((uint8_t *)pSTR + pSTR->bLength); 280 | } 281 | USBLIB_SendData(0, (uint16_t *)pSTR, pSTR->bLength); 282 | break; 283 | default: 284 | USBLIB_SendData(0, 0, 0); 285 | break; 286 | } 287 | } 288 | 289 | void USBLIB_EPHandler(uint16_t Status) 290 | { 291 | uint16_t DeviceConfigured = 0, DeviceStatus = 0; 292 | uint8_t EPn = Status & USB_ISTR_EP_ID; 293 | uint32_t EP = USBEP[EPn]; 294 | if (EP & EP_CTR_RX) { //something received 295 | USBLIB_Pma2EPBuf2(EPn); 296 | if (EPn == 0) { //If control endpoint 297 | if (EP & USB_EP0R_SETUP) { 298 | SetupPacket = (USBLIB_SetupPacket *)EpData[EPn].pRX_BUFF; 299 | switch (SetupPacket->bRequest) { 300 | case USB_REQUEST_SET_ADDRESS: 301 | USBLIB_SendData(0, 0, 0); 302 | DeviceAddress = SetupPacket->wValue.L; 303 | break; 304 | 305 | case USB_REQUEST_GET_DESCRIPTOR: 306 | USBLIB_GetDescriptor(SetupPacket); 307 | break; 308 | 309 | case USB_REQUEST_GET_STATUS: 310 | USBLIB_SendData(0, &DeviceStatus, 2); 311 | break; 312 | 313 | case USB_REQUEST_GET_CONFIGURATION: 314 | USBLIB_SendData(0, &DeviceConfigured, 1); 315 | break; 316 | 317 | case USB_REQUEST_SET_CONFIGURATION: 318 | DeviceConfigured = 1; 319 | USBLIB_SendData(0, 0, 0); 320 | break; 321 | 322 | case USB_DEVICE_CDC_REQUEST_SET_COMM_FEATURE: 323 | //TODO 324 | break; 325 | 326 | case USB_DEVICE_CDC_REQUEST_SET_LINE_CODING: //0x20 327 | USBLIB_SendData(0, 0, 0); 328 | break; 329 | 330 | case USB_DEVICE_CDC_REQUEST_GET_LINE_CODING: //0x21 331 | USBLIB_SendData(EPn, (uint16_t *)&lineCoding, sizeof(lineCoding)); 332 | break; 333 | 334 | case USB_DEVICE_CDC_REQUEST_SET_CONTROL_LINE_STATE: //0x22 335 | LineState = SetupPacket->wValue; 336 | USBLIB_SendData(0, 0, 0); 337 | uUSBLIB_LineStateHandler(SetupPacket->wValue); 338 | break; 339 | } 340 | } 341 | } else { // Got data from another EP 342 | // Call user function 343 | uUSBLIB_DataReceivedHandler(EpData[EPn].pRX_BUFF, EpData[EPn].lRX); 344 | } 345 | USBEP[EPn] &= 0x78f; 346 | USBLIB_setStatRx(EPn, RX_VALID); 347 | } 348 | if (EP & EP_CTR_TX) { //something transmitted 349 | if (DeviceAddress) { 350 | USB->DADDR = DeviceAddress | 0x80; 351 | DeviceAddress = 0; 352 | } 353 | 354 | if (EpData[EPn].lTX) { //Have to transmit something? 355 | USBLIB_EPBuf2Pma(EPn); 356 | USBLIB_setStatTx(EPn, TX_VALID); 357 | } else { 358 | uUSBLIB_DataTransmitedHandler(EPn, EpData[EPn]); 359 | } 360 | 361 | USBEP[EPn] &= 0x870f; 362 | } 363 | } 364 | 365 | void USB_LP_CAN1_RX0_IRQHandler() 366 | { 367 | if (USB->ISTR & USB_ISTR_RESET) { // Reset 368 | USB->ISTR &= ~USB_ISTR_RESET; 369 | USBLIB_Reset(); 370 | return; 371 | } 372 | if (USB->ISTR & USB_ISTR_CTR) { //Handle data on EP 373 | USBLIB_EPHandler((uint16_t)USB->ISTR); 374 | USB->ISTR &= ~USB_ISTR_CTR; 375 | return; 376 | } 377 | if (USB->ISTR & USB_ISTR_PMAOVR) { 378 | USB->ISTR &= ~USB_ISTR_PMAOVR; 379 | // Handle PMAOVR status 380 | return; 381 | } 382 | if (USB->ISTR & USB_ISTR_SUSP) { 383 | USB->ISTR &= ~USB_ISTR_SUSP; 384 | if (USB->DADDR & 0x7f) { 385 | USB->DADDR = 0; 386 | USB->CNTR &= ~ 0x800; 387 | } 388 | return; 389 | } 390 | if (USB->ISTR & USB_ISTR_ERR) { 391 | USB->ISTR &= ~USB_ISTR_ERR; 392 | // Handle Error 393 | return; 394 | } 395 | if (USB->ISTR & USB_ISTR_WKUP) { 396 | USB->ISTR &= ~USB_ISTR_WKUP; 397 | // Handle Wakeup 398 | return; 399 | } 400 | if (USB->ISTR & USB_ISTR_SOF) { 401 | USB->ISTR &= ~USB_ISTR_SOF; 402 | // Handle SOF 403 | return; 404 | } 405 | if (USB->ISTR & USB_ISTR_ESOF) { 406 | USB->ISTR &= ~USB_ISTR_ESOF; 407 | // Handle ESOF 408 | return; 409 | } 410 | USB->ISTR = 0; 411 | } 412 | 413 | void USBLIB_Transmit(uint16_t *Data, uint16_t Length) 414 | { 415 | // if (LineState.L) { 416 | USBLIB_SendData(2, Data, Length); 417 | // } 418 | } 419 | 420 | __weak void uUSBLIB_DataReceivedHandler(uint16_t *Data, uint16_t Length) 421 | { 422 | /* NOTE: This function Should not be modified, when the callback is needed, 423 | the uUSBLIB_DataReceivedHandler could be implemented in the user file 424 | */ 425 | } 426 | 427 | __weak void uUSBLIB_DataTransmitedHandler(uint8_t EPn, USBLIB_EPData EpData) 428 | { 429 | /* NOTE: This function Should not be modified, when the callback is needed, 430 | the uUSBLIB_EPStateHandler could be implemented in the user file 431 | */ 432 | } 433 | 434 | __weak void uUSBLIB_LineStateHandler(USBLIB_WByte LineState) 435 | { 436 | /* NOTE: This function Should not be modified, when the callback is needed, 437 | the uUSBLIB_LineStateHandler could be implemented in the user file 438 | */ 439 | } 440 | --------------------------------------------------------------------------------