├── .gitignore ├── README.md └── Software ├── .gitignore ├── Core ├── Inc │ ├── bldc.h │ ├── gpio.h │ ├── interface.h │ ├── main.h │ ├── pwm.h │ ├── stm32f0xx_hal_conf.h │ ├── stm32f0xx_it.h │ └── tim.h ├── Src │ ├── bldc.c │ ├── gpio.c │ ├── interface.c │ ├── main.c │ ├── pwm.c │ ├── stm32f0xx_hal_msp.c │ ├── stm32f0xx_it.c │ ├── syscalls.c │ ├── sysmem.c │ ├── system_stm32f0xx.c │ └── tim.c └── Startup │ └── startup_stm32f042k6tx.s ├── Drivers ├── CMSIS │ ├── Device │ │ └── ST │ │ │ └── STM32F0xx │ │ │ └── Include │ │ │ ├── stm32f042x6.h │ │ │ ├── stm32f0xx.h │ │ │ └── system_stm32f0xx.h │ └── Include │ │ ├── cmsis_armcc.h │ │ ├── cmsis_armclang.h │ │ ├── cmsis_compiler.h │ │ ├── cmsis_gcc.h │ │ ├── cmsis_iccarm.h │ │ ├── cmsis_version.h │ │ ├── core_armv8mbl.h │ │ ├── core_armv8mml.h │ │ ├── core_cm0.h │ │ ├── core_cm0plus.h │ │ ├── core_cm1.h │ │ ├── core_cm23.h │ │ ├── core_cm3.h │ │ ├── core_cm33.h │ │ ├── core_cm4.h │ │ ├── core_cm7.h │ │ ├── core_sc000.h │ │ ├── core_sc300.h │ │ ├── mpu_armv7.h │ │ ├── mpu_armv8.h │ │ └── tz_context.h └── STM32F0xx_HAL_Driver │ ├── Inc │ ├── Legacy │ │ └── stm32_hal_legacy.h │ ├── stm32f0xx_hal.h │ ├── stm32f0xx_hal_cortex.h │ ├── stm32f0xx_hal_def.h │ ├── stm32f0xx_hal_dma.h │ ├── stm32f0xx_hal_dma_ex.h │ ├── stm32f0xx_hal_exti.h │ ├── stm32f0xx_hal_flash.h │ ├── stm32f0xx_hal_flash_ex.h │ ├── stm32f0xx_hal_gpio.h │ ├── stm32f0xx_hal_gpio_ex.h │ ├── stm32f0xx_hal_i2c.h │ ├── stm32f0xx_hal_i2c_ex.h │ ├── stm32f0xx_hal_pwr.h │ ├── stm32f0xx_hal_pwr_ex.h │ ├── stm32f0xx_hal_rcc.h │ ├── stm32f0xx_hal_rcc_ex.h │ ├── stm32f0xx_hal_tim.h │ └── stm32f0xx_hal_tim_ex.h │ └── Src │ ├── stm32f0xx_hal.c │ ├── stm32f0xx_hal_cortex.c │ ├── stm32f0xx_hal_dma.c │ ├── stm32f0xx_hal_exti.c │ ├── stm32f0xx_hal_flash.c │ ├── stm32f0xx_hal_flash_ex.c │ ├── stm32f0xx_hal_gpio.c │ ├── stm32f0xx_hal_i2c.c │ ├── stm32f0xx_hal_i2c_ex.c │ ├── stm32f0xx_hal_pwr.c │ ├── stm32f0xx_hal_pwr_ex.c │ ├── stm32f0xx_hal_rcc.c │ ├── stm32f0xx_hal_rcc_ex.c │ ├── stm32f0xx_hal_tim.c │ └── stm32f0xx_hal_tim_ex.c ├── STM32F042K6TX_FLASH.ld ├── SensorlessESC.ioc └── scripts ├── format.sh └── test_format.sh /.gitignore: -------------------------------------------------------------------------------- 1 | # Prerequisites 2 | *.d 3 | 4 | # Object files 5 | *.o 6 | *.ko 7 | *.obj 8 | *.elf 9 | 10 | # Linker output 11 | *.ilk 12 | *.map 13 | *.exp 14 | 15 | # Precompiled Headers 16 | *.gch 17 | *.pch 18 | 19 | # Libraries 20 | *.lib 21 | *.a 22 | *.la 23 | *.lo 24 | 25 | # Shared objects (inc. Windows DLLs) 26 | *.dll 27 | *.so 28 | *.so.* 29 | *.dylib 30 | 31 | # Executables 32 | *.exe 33 | *.out 34 | *.app 35 | *.i*86 36 | *.x86_64 37 | *.hex 38 | 39 | # Debug files 40 | *.dSYM/ 41 | *.su 42 | *.idb 43 | *.pdb 44 | 45 | # Kernel Module Compile Results 46 | *.mod* 47 | *.cmd 48 | .tmp_versions/ 49 | modules.order 50 | Module.symvers 51 | Mkfile.old 52 | dkms.conf 53 | *.json 54 | 55 | Release/ 56 | Debug/ 57 | *.launch 58 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SensorlessESCSoftware 2 | 3 | I like making motors spin! I decided to make a custom sensorless BLDC motor controller. 4 | 5 | ## Commentary 6 | - A standard RC servo PWM control interface is employed (1000-2000us Duty Cycle, 50Hz) to control the BLDC motor to make it usable in RC drones and cars 7 | - I opted to make the BackEMF Zero-Sensing with an external comparator to simplify the code. Additionally, it would make the software easier for a sensored ESC 8 | - Due to chip shortage, the pins were broken out and a nucleo was used instead. 9 | 10 | ## Schematic 11 | ![image](https://user-images.githubusercontent.com/32375512/142559879-6bcc972d-e7d7-4192-b4b5-bf94f3be7d23.png) 12 | ![image](https://user-images.githubusercontent.com/32375512/142559903-1e754333-308f-49bd-9c56-6b7a22ce56b6.png) 13 | 14 | ## Photo: 15 | -------------------------------------------------------------------------------- /Software/.gitignore: -------------------------------------------------------------------------------- 1 | Debug/ 2 | .settings/ 3 | .mxproject 4 | .project 5 | .cproject -------------------------------------------------------------------------------- /Software/Core/Inc/bldc.h: -------------------------------------------------------------------------------- 1 | #ifndef BLDC_H 2 | #define BLDC_H 3 | 4 | #include "tim.h" 5 | #include 6 | 7 | /** 8 | * @brief initalizes the BLDC motor controller 9 | */ 10 | void bldc_init(); 11 | 12 | /** 13 | * @brief loops through the BLDC motor control algo. Called by while(1) 14 | */ 15 | void bldc_loop(); 16 | 17 | /** 18 | * @brief BackEMF GPIO interrupt callback 19 | */ 20 | void BackEMF_Callback(uint16_t GPIO_Pin); 21 | 22 | /** 23 | * @brief BLDC update control parameters 24 | */ 25 | void update_control(uint8_t new_speed, bool is_reversed); 26 | 27 | #endif 28 | -------------------------------------------------------------------------------- /Software/Core/Inc/gpio.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file gpio.h 4 | * @brief This file contains all the function prototypes for 5 | * the gpio.c file 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __GPIO_H__ 21 | #define __GPIO_H__ 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "main.h" 29 | 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* USER CODE BEGIN Private defines */ 35 | 36 | /* USER CODE END Private defines */ 37 | 38 | void MX_GPIO_Init(void); 39 | 40 | /* USER CODE BEGIN Prototypes */ 41 | 42 | /* USER CODE END Prototypes */ 43 | 44 | #ifdef __cplusplus 45 | } 46 | #endif 47 | #endif /*__ GPIO_H__ */ 48 | 49 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 50 | -------------------------------------------------------------------------------- /Software/Core/Inc/interface.h: -------------------------------------------------------------------------------- 1 | #ifndef INTERFACE_H_ 2 | #define INTERFACE_H_ 3 | 4 | /** 5 | * @brief initalizes the input capture timer stuff 6 | */ 7 | void interface_init(void); 8 | 9 | #endif /* INTERFACE_H_ */ 10 | -------------------------------------------------------------------------------- /Software/Core/Inc/main.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.h 5 | * @brief : Header for main.c file. 6 | * This file contains the common defines of the application. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MAIN_H 24 | #define __MAIN_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f0xx_hal.h" 32 | 33 | /* Private includes ----------------------------------------------------------*/ 34 | /* USER CODE BEGIN Includes */ 35 | 36 | /* USER CODE END Includes */ 37 | 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* USER CODE BEGIN ET */ 40 | 41 | /* USER CODE END ET */ 42 | 43 | /* Exported constants --------------------------------------------------------*/ 44 | /* USER CODE BEGIN EC */ 45 | 46 | /* USER CODE END EC */ 47 | 48 | /* Exported macro ------------------------------------------------------------*/ 49 | /* USER CODE BEGIN EM */ 50 | 51 | /* USER CODE END EM */ 52 | 53 | /* Exported functions prototypes ---------------------------------------------*/ 54 | void Error_Handler(void); 55 | 56 | /* USER CODE BEGIN EFP */ 57 | 58 | /* USER CODE END EFP */ 59 | 60 | /* Private defines -----------------------------------------------------------*/ 61 | #define PWM_A_Pin GPIO_PIN_0 62 | #define PWM_A_GPIO_Port GPIOA 63 | #define PWM_B_Pin GPIO_PIN_1 64 | #define PWM_B_GPIO_Port GPIOA 65 | #define PWM_C_Pin GPIO_PIN_2 66 | #define PWM_C_GPIO_Port GPIOA 67 | #define OD_A_Pin GPIO_PIN_3 68 | #define OD_A_GPIO_Port GPIOA 69 | #define OD_B_Pin GPIO_PIN_4 70 | #define OD_B_GPIO_Port GPIOA 71 | #define OD_C_Pin GPIO_PIN_5 72 | #define OD_C_GPIO_Port GPIOA 73 | #define LED_Pin GPIO_PIN_3 74 | #define LED_GPIO_Port GPIOB 75 | #define BEMF_A_Pin GPIO_PIN_5 76 | #define BEMF_A_GPIO_Port GPIOB 77 | #define BEMF_A_EXTI_IRQn EXTI4_15_IRQn 78 | #define BEMF_B_Pin GPIO_PIN_6 79 | #define BEMF_B_GPIO_Port GPIOB 80 | #define BEMF_B_EXTI_IRQn EXTI4_15_IRQn 81 | #define BEMF_C_Pin GPIO_PIN_7 82 | #define BEMF_C_GPIO_Port GPIOB 83 | #define BEMF_C_EXTI_IRQn EXTI4_15_IRQn 84 | /* USER CODE BEGIN Private defines */ 85 | 86 | #define TIM_ARR (100UL) 87 | 88 | /* USER CODE END Private defines */ 89 | 90 | #ifdef __cplusplus 91 | } 92 | #endif 93 | 94 | #endif /* __MAIN_H */ 95 | 96 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 97 | -------------------------------------------------------------------------------- /Software/Core/Inc/pwm.h: -------------------------------------------------------------------------------- 1 | #ifndef PWM_H 2 | #define PWM_H 3 | 4 | #include 5 | #include 6 | 7 | extern uint8_t PHASE_A_INDEX; 8 | extern uint8_t PHASE_B_INDEX; 9 | extern uint8_t PHASE_C_INDEX; 10 | 11 | /** 12 | * Initalizes the PWM timer interfaces 13 | */ 14 | void pwm_init(); 15 | 16 | /** 17 | * Inverts the phases of the BLDC motor. 18 | */ 19 | void invert_phases(bool inverted); 20 | 21 | /** 22 | * Sets the duty cycle of the PWM signal for Phase A 23 | * @param dutyValue the duty cycle value 24 | * @param enableOutput true to enable the output, false to disable the half 25 | * bridge 26 | */ 27 | void setPhaseADuty(uint32_t dutyValue, bool enableOutput); 28 | 29 | /** 30 | * Sets the duty cycle of the PWM signal for Phase A 31 | * @param dutyValue the duty cycle value 32 | * @param enableOutput true to enable the output, false to disable the half 33 | * bridge 34 | */ 35 | void setPhaseBDuty(uint32_t dutyValue, bool enableOutput); 36 | 37 | /** 38 | * Sets the duty cycle of the PWM signal for Phase A 39 | * @param dutyValue the duty cycle value 40 | * @param enableOutput true to enable the output, false to disable the half 41 | * bridge 42 | */ 43 | void setPhaseCDuty(uint32_t dutyValue, bool enableOutput); 44 | 45 | #endif 46 | -------------------------------------------------------------------------------- /Software/Core/Inc/stm32f0xx_hal_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_conf.h 4 | * @brief HAL configuration file. 5 | ****************************************************************************** 6 | * @attention 7 | * 8 | *

© Copyright (c) 2016 STMicroelectronics. 9 | * All rights reserved.

10 | * 11 | * This software component is licensed by ST under BSD 3-Clause license, 12 | * the "License"; You may not use this file except in compliance with the 13 | * License. You may obtain a copy of the License at: 14 | * opensource.org/licenses/BSD-3-Clause 15 | * 16 | ****************************************************************************** 17 | */ 18 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __STM32F0xx_HAL_CONF_H 21 | #define __STM32F0xx_HAL_CONF_H 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Exported types ------------------------------------------------------------*/ 28 | /* Exported constants --------------------------------------------------------*/ 29 | 30 | /* ########################## Module Selection ############################## */ 31 | /** 32 | * @brief This is the list of modules to be used in the HAL driver 33 | */ 34 | #define HAL_MODULE_ENABLED 35 | /*#define HAL_ADC_MODULE_ENABLED */ 36 | /*#define HAL_CRYP_MODULE_ENABLED */ 37 | /*#define HAL_CAN_MODULE_ENABLED */ 38 | /*#define HAL_CEC_MODULE_ENABLED */ 39 | /*#define HAL_COMP_MODULE_ENABLED */ 40 | /*#define HAL_CRC_MODULE_ENABLED */ 41 | /*#define HAL_CRYP_MODULE_ENABLED */ 42 | /*#define HAL_TSC_MODULE_ENABLED */ 43 | /*#define HAL_DAC_MODULE_ENABLED */ 44 | /*#define HAL_I2S_MODULE_ENABLED */ 45 | /*#define HAL_IWDG_MODULE_ENABLED */ 46 | /*#define HAL_LCD_MODULE_ENABLED */ 47 | /*#define HAL_LPTIM_MODULE_ENABLED */ 48 | /*#define HAL_RNG_MODULE_ENABLED */ 49 | /*#define HAL_RTC_MODULE_ENABLED */ 50 | /*#define HAL_SPI_MODULE_ENABLED */ 51 | #define HAL_TIM_MODULE_ENABLED 52 | /*#define HAL_UART_MODULE_ENABLED */ 53 | /*#define HAL_USART_MODULE_ENABLED */ 54 | /*#define HAL_IRDA_MODULE_ENABLED */ 55 | /*#define HAL_SMARTCARD_MODULE_ENABLED */ 56 | /*#define HAL_SMBUS_MODULE_ENABLED */ 57 | /*#define HAL_WWDG_MODULE_ENABLED */ 58 | /*#define HAL_PCD_MODULE_ENABLED */ 59 | #define HAL_CORTEX_MODULE_ENABLED 60 | #define HAL_DMA_MODULE_ENABLED 61 | #define HAL_FLASH_MODULE_ENABLED 62 | #define HAL_GPIO_MODULE_ENABLED 63 | #define HAL_EXTI_MODULE_ENABLED 64 | #define HAL_PWR_MODULE_ENABLED 65 | #define HAL_RCC_MODULE_ENABLED 66 | #define HAL_I2C_MODULE_ENABLED 67 | 68 | /* ########################## HSE/HSI Values adaptation ##################### */ 69 | /** 70 | * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. 71 | * This value is used by the RCC HAL module to compute the system frequency 72 | * (when HSE is used as system clock source, directly or through the PLL). 73 | */ 74 | #if !defined (HSE_VALUE) 75 | #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ 76 | #endif /* HSE_VALUE */ 77 | 78 | /** 79 | * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 80 | * Timeout value 81 | */ 82 | #if !defined (HSE_STARTUP_TIMEOUT) 83 | #define HSE_STARTUP_TIMEOUT ((uint32_t)100) /*!< Time out for HSE start up, in ms */ 84 | #endif /* HSE_STARTUP_TIMEOUT */ 85 | 86 | /** 87 | * @brief Internal High Speed oscillator (HSI) value. 88 | * This value is used by the RCC HAL module to compute the system frequency 89 | * (when HSI is used as system clock source, directly or through the PLL). 90 | */ 91 | #if !defined (HSI_VALUE) 92 | #define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ 93 | #endif /* HSI_VALUE */ 94 | 95 | /** 96 | * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup 97 | * Timeout value 98 | */ 99 | #if !defined (HSI_STARTUP_TIMEOUT) 100 | #define HSI_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for HSI start up */ 101 | #endif /* HSI_STARTUP_TIMEOUT */ 102 | 103 | /** 104 | * @brief Internal High Speed oscillator for ADC (HSI14) value. 105 | */ 106 | #if !defined (HSI14_VALUE) 107 | #define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz. 108 | The real value may vary depending on the variations 109 | in voltage and temperature. */ 110 | #endif /* HSI14_VALUE */ 111 | 112 | /** 113 | * @brief Internal High Speed oscillator for USB (HSI48) value. 114 | */ 115 | #if !defined (HSI48_VALUE) 116 | #define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz. 117 | The real value may vary depending on the variations 118 | in voltage and temperature. */ 119 | #endif /* HSI48_VALUE */ 120 | 121 | /** 122 | * @brief Internal Low Speed oscillator (LSI) value. 123 | */ 124 | #if !defined (LSI_VALUE) 125 | #define LSI_VALUE ((uint32_t)40000) 126 | #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz 127 | The real value may vary depending on the variations 128 | in voltage and temperature. */ 129 | /** 130 | * @brief External Low Speed oscillator (LSI) value. 131 | */ 132 | #if !defined (LSE_VALUE) 133 | #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ 134 | #endif /* LSE_VALUE */ 135 | 136 | /** 137 | * @brief Time out for LSE start up value in ms. 138 | */ 139 | #if !defined (LSE_STARTUP_TIMEOUT) 140 | #define LSE_STARTUP_TIMEOUT ((uint32_t)5000) /*!< Time out for LSE start up, in ms */ 141 | #endif /* LSE_STARTUP_TIMEOUT */ 142 | 143 | /* Tip: To avoid modifying this file each time you need to use different HSE, 144 | === you can define the HSE value in your toolchain compiler preprocessor. */ 145 | 146 | /* ########################### System Configuration ######################### */ 147 | /** 148 | * @brief This is the HAL system configuration section 149 | */ 150 | #define VDD_VALUE ((uint32_t)3300) /*!< Value of VDD in mv */ 151 | #define TICK_INT_PRIORITY ((uint32_t)3) /*!< tick interrupt priority (lowest by default) */ 152 | /* Warning: Must be set to higher priority for HAL_Delay() */ 153 | /* and HAL_GetTick() usage under interrupt context */ 154 | #define USE_RTOS 0 155 | #define PREFETCH_ENABLE 1 156 | #define INSTRUCTION_CACHE_ENABLE 0 157 | #define DATA_CACHE_ENABLE 0 158 | #define USE_SPI_CRC 0U 159 | 160 | #define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ 161 | #define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ 162 | #define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ 163 | #define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ 164 | #define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ 165 | #define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ 166 | #define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ 167 | #define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ 168 | #define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ 169 | #define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ 170 | #define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ 171 | #define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ 172 | #define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ 173 | #define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ 174 | #define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ 175 | #define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ 176 | #define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ 177 | #define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ 178 | 179 | /* ########################## Assert Selection ############################## */ 180 | /** 181 | * @brief Uncomment the line below to expanse the "assert_param" macro in the 182 | * HAL drivers code 183 | */ 184 | /* #define USE_FULL_ASSERT 1U */ 185 | 186 | /* Includes ------------------------------------------------------------------*/ 187 | /** 188 | * @brief Include module's header file 189 | */ 190 | 191 | #ifdef HAL_RCC_MODULE_ENABLED 192 | #include "stm32f0xx_hal_rcc.h" 193 | #endif /* HAL_RCC_MODULE_ENABLED */ 194 | 195 | #ifdef HAL_GPIO_MODULE_ENABLED 196 | #include "stm32f0xx_hal_gpio.h" 197 | #endif /* HAL_GPIO_MODULE_ENABLED */ 198 | 199 | #ifdef HAL_EXTI_MODULE_ENABLED 200 | #include "stm32f0xx_hal_exti.h" 201 | #endif /* HAL_EXTI_MODULE_ENABLED */ 202 | 203 | #ifdef HAL_DMA_MODULE_ENABLED 204 | #include "stm32f0xx_hal_dma.h" 205 | #endif /* HAL_DMA_MODULE_ENABLED */ 206 | 207 | #ifdef HAL_CORTEX_MODULE_ENABLED 208 | #include "stm32f0xx_hal_cortex.h" 209 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 210 | 211 | #ifdef HAL_ADC_MODULE_ENABLED 212 | #include "stm32f0xx_hal_adc.h" 213 | #endif /* HAL_ADC_MODULE_ENABLED */ 214 | 215 | #ifdef HAL_CAN_MODULE_ENABLED 216 | #include "stm32f0xx_hal_can.h" 217 | #endif /* HAL_CAN_MODULE_ENABLED */ 218 | 219 | #ifdef HAL_CEC_MODULE_ENABLED 220 | #include "stm32f0xx_hal_cec.h" 221 | #endif /* HAL_CEC_MODULE_ENABLED */ 222 | 223 | #ifdef HAL_COMP_MODULE_ENABLED 224 | #include "stm32f0xx_hal_comp.h" 225 | #endif /* HAL_COMP_MODULE_ENABLED */ 226 | 227 | #ifdef HAL_CRC_MODULE_ENABLED 228 | #include "stm32f0xx_hal_crc.h" 229 | #endif /* HAL_CRC_MODULE_ENABLED */ 230 | 231 | #ifdef HAL_DAC_MODULE_ENABLED 232 | #include "stm32f0xx_hal_dac.h" 233 | #endif /* HAL_DAC_MODULE_ENABLED */ 234 | 235 | #ifdef HAL_FLASH_MODULE_ENABLED 236 | #include "stm32f0xx_hal_flash.h" 237 | #endif /* HAL_FLASH_MODULE_ENABLED */ 238 | 239 | #ifdef HAL_I2C_MODULE_ENABLED 240 | #include "stm32f0xx_hal_i2c.h" 241 | #endif /* HAL_I2C_MODULE_ENABLED */ 242 | 243 | #ifdef HAL_I2S_MODULE_ENABLED 244 | #include "stm32f0xx_hal_i2s.h" 245 | #endif /* HAL_I2S_MODULE_ENABLED */ 246 | 247 | #ifdef HAL_IRDA_MODULE_ENABLED 248 | #include "stm32f0xx_hal_irda.h" 249 | #endif /* HAL_IRDA_MODULE_ENABLED */ 250 | 251 | #ifdef HAL_IWDG_MODULE_ENABLED 252 | #include "stm32f0xx_hal_iwdg.h" 253 | #endif /* HAL_IWDG_MODULE_ENABLED */ 254 | 255 | #ifdef HAL_PCD_MODULE_ENABLED 256 | #include "stm32f0xx_hal_pcd.h" 257 | #endif /* HAL_PCD_MODULE_ENABLED */ 258 | 259 | #ifdef HAL_PWR_MODULE_ENABLED 260 | #include "stm32f0xx_hal_pwr.h" 261 | #endif /* HAL_PWR_MODULE_ENABLED */ 262 | 263 | #ifdef HAL_RTC_MODULE_ENABLED 264 | #include "stm32f0xx_hal_rtc.h" 265 | #endif /* HAL_RTC_MODULE_ENABLED */ 266 | 267 | #ifdef HAL_SMARTCARD_MODULE_ENABLED 268 | #include "stm32f0xx_hal_smartcard.h" 269 | #endif /* HAL_SMARTCARD_MODULE_ENABLED */ 270 | 271 | #ifdef HAL_SMBUS_MODULE_ENABLED 272 | #include "stm32f0xx_hal_smbus.h" 273 | #endif /* HAL_SMBUS_MODULE_ENABLED */ 274 | 275 | #ifdef HAL_SPI_MODULE_ENABLED 276 | #include "stm32f0xx_hal_spi.h" 277 | #endif /* HAL_SPI_MODULE_ENABLED */ 278 | 279 | #ifdef HAL_TIM_MODULE_ENABLED 280 | #include "stm32f0xx_hal_tim.h" 281 | #endif /* HAL_TIM_MODULE_ENABLED */ 282 | 283 | #ifdef HAL_TSC_MODULE_ENABLED 284 | #include "stm32f0xx_hal_tsc.h" 285 | #endif /* HAL_TSC_MODULE_ENABLED */ 286 | 287 | #ifdef HAL_UART_MODULE_ENABLED 288 | #include "stm32f0xx_hal_uart.h" 289 | #endif /* HAL_UART_MODULE_ENABLED */ 290 | 291 | #ifdef HAL_USART_MODULE_ENABLED 292 | #include "stm32f0xx_hal_usart.h" 293 | #endif /* HAL_USART_MODULE_ENABLED */ 294 | 295 | #ifdef HAL_WWDG_MODULE_ENABLED 296 | #include "stm32f0xx_hal_wwdg.h" 297 | #endif /* HAL_WWDG_MODULE_ENABLED */ 298 | 299 | /* Exported macro ------------------------------------------------------------*/ 300 | #ifdef USE_FULL_ASSERT 301 | /** 302 | * @brief The assert_param macro is used for function's parameters check. 303 | * @param expr If expr is false, it calls assert_failed function 304 | * which reports the name of the source file and the source 305 | * line number of the call that failed. 306 | * If expr is true, it returns no value. 307 | * @retval None 308 | */ 309 | #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) 310 | /* Exported functions ------------------------------------------------------- */ 311 | void assert_failed(uint8_t* file, uint32_t line); 312 | #else 313 | #define assert_param(expr) ((void)0U) 314 | #endif /* USE_FULL_ASSERT */ 315 | 316 | #ifdef __cplusplus 317 | } 318 | #endif 319 | 320 | #endif /* __STM32F0xx_HAL_CONF_H */ 321 | 322 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 323 | -------------------------------------------------------------------------------- /Software/Core/Inc/stm32f0xx_it.h: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f0xx_it.h 5 | * @brief This file contains the headers of the interrupt handlers. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F0xx_IT_H 23 | #define __STM32F0xx_IT_H 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Private includes ----------------------------------------------------------*/ 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN ET */ 36 | 37 | /* USER CODE END ET */ 38 | 39 | /* Exported constants --------------------------------------------------------*/ 40 | /* USER CODE BEGIN EC */ 41 | 42 | /* USER CODE END EC */ 43 | 44 | /* Exported macro ------------------------------------------------------------*/ 45 | /* USER CODE BEGIN EM */ 46 | 47 | /* USER CODE END EM */ 48 | 49 | /* Exported functions prototypes ---------------------------------------------*/ 50 | void NMI_Handler(void); 51 | void HardFault_Handler(void); 52 | void SVC_Handler(void); 53 | void PendSV_Handler(void); 54 | void SysTick_Handler(void); 55 | void EXTI4_15_IRQHandler(void); 56 | void TIM2_IRQHandler(void); 57 | void TIM3_IRQHandler(void); 58 | /* USER CODE BEGIN EFP */ 59 | 60 | /* USER CODE END EFP */ 61 | 62 | #ifdef __cplusplus 63 | } 64 | #endif 65 | 66 | #endif /* __STM32F0xx_IT_H */ 67 | 68 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 69 | -------------------------------------------------------------------------------- /Software/Core/Inc/tim.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file tim.h 4 | * @brief This file contains all the function prototypes for 5 | * the tim.c file 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* Define to prevent recursive inclusion -------------------------------------*/ 20 | #ifndef __TIM_H__ 21 | #define __TIM_H__ 22 | 23 | #ifdef __cplusplus 24 | extern "C" { 25 | #endif 26 | 27 | /* Includes ------------------------------------------------------------------*/ 28 | #include "main.h" 29 | 30 | /* USER CODE BEGIN Includes */ 31 | 32 | /* USER CODE END Includes */ 33 | 34 | extern TIM_HandleTypeDef htim2; 35 | extern TIM_HandleTypeDef htim3; 36 | 37 | /* USER CODE BEGIN Private defines */ 38 | 39 | /* USER CODE END Private defines */ 40 | 41 | void MX_TIM2_Init(void); 42 | void MX_TIM3_Init(void); 43 | 44 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); 45 | 46 | /* USER CODE BEGIN Prototypes */ 47 | 48 | /* USER CODE END Prototypes */ 49 | 50 | #ifdef __cplusplus 51 | } 52 | #endif 53 | 54 | #endif /* __TIM_H__ */ 55 | 56 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 57 | -------------------------------------------------------------------------------- /Software/Core/Src/bldc.c: -------------------------------------------------------------------------------- 1 | #include "bldc.h" 2 | #include "gpio.h" 3 | #include "main.h" 4 | #include "pwm.h" 5 | #include 6 | #include 7 | //#define ENABLE_BACKEMF_SENSEING_DEBUG 8 | 9 | typedef struct backemf_gpio_map { 10 | GPIO_TypeDef *GPIOx; 11 | uint16_t GPIO_Pin; 12 | } backemf_gpio_map_t; 13 | 14 | #ifdef ENABLE_BACKEMF_SENSEING_DEBUG 15 | static backemf_gpio_map_t backemf_gpio_mapping[] = { 16 | {BEMF_A_GPIO_Port, BEMF_A_Pin}, 17 | {BEMF_B_GPIO_Port, BEMF_B_Pin}, 18 | {BEMF_C_GPIO_Port, BEMF_C_Pin}, 19 | }; 20 | #endif 21 | 22 | static volatile uint8_t speed = 30; 23 | static volatile uint8_t bldc_state = 0; 24 | static volatile bool reversed = false; 25 | static volatile bool flag_set_state_switch = false; 26 | 27 | // Timer Wraparound checks 28 | static volatile uint64_t pwm_tim_cnt = 0; 29 | static volatile uint64_t pwm_tim_ccr = 30; 30 | 31 | static void control_loop(); 32 | 33 | static void commutate_motor_trapazoidal(uint8_t state); 34 | 35 | // 10KHz Timer Callback 36 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) { 37 | // Assert that the correct timer callback has occured 38 | if (htim != &htim2) { 39 | return; 40 | } 41 | pwm_tim_cnt += 1; 42 | if (pwm_tim_cnt == pwm_tim_ccr) { 43 | bldc_state++; 44 | bldc_state %= 6; 45 | commutate_motor_trapazoidal(bldc_state); 46 | pwm_tim_cnt = 0; 47 | } 48 | 49 | // Run the 10kHz control loop 50 | control_loop(); 51 | } 52 | 53 | void bldc_init() { 54 | pwm_init(); 55 | HAL_TIM_Base_Start_IT(&htim2); // Start interrupt time base 56 | } 57 | 58 | void bldc_loop() { 59 | HAL_GPIO_TogglePin(LED_GPIO_Port, LED_Pin); 60 | HAL_Delay(500); 61 | } 62 | 63 | // Control Loop, 10kHz 64 | static void control_loop() { invert_phases(reversed); } 65 | 66 | void update_control(uint8_t new_speed, bool is_reversed) { 67 | speed = new_speed; 68 | reversed = is_reversed; 69 | } 70 | 71 | static void commutate_motor_trapazoidal(uint8_t state) { 72 | switch (state) { 73 | case 0: 74 | // Step 0, A high, B low, C off 75 | // BEMF C rising 76 | setPhaseADuty(speed, true); 77 | setPhaseBDuty(0, true); 78 | setPhaseCDuty(0, false); 79 | break; 80 | case 1: 81 | // Step 1, A high, B off, C low 82 | // BEMF B falling 83 | setPhaseADuty(speed, true); 84 | setPhaseBDuty(0, false); 85 | setPhaseCDuty(0, true); 86 | break; 87 | case 2: 88 | // Step 2, A off, B high, C low 89 | // BEMF A rising 90 | setPhaseADuty(0, false); 91 | setPhaseBDuty(speed, true); 92 | setPhaseCDuty(0, true); 93 | break; 94 | case 3: 95 | // Step 3, A low, B high, C off 96 | // BEMF C falling 97 | setPhaseADuty(0, true); 98 | setPhaseBDuty(speed, true); 99 | setPhaseCDuty(0, false); 100 | break; 101 | case 4: 102 | // Step 4, A low, B off, C high 103 | // BEMF B rising 104 | setPhaseADuty(0, true); 105 | setPhaseBDuty(0, false); 106 | setPhaseCDuty(speed, true); 107 | break; 108 | case 5: 109 | // Step 5, A off, B low, C high 110 | // BEMF A falling 111 | setPhaseADuty(0, false); 112 | setPhaseBDuty(0, true); 113 | setPhaseCDuty(speed, true); 114 | break; 115 | } 116 | } 117 | 118 | void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin) { 119 | #ifdef ENABLE_BACKEMF_SENSEING_DEBUG 120 | backemf_gpio_map_t phaseA_backemf_map = backemf_gpio_mapping[PHASE_A_INDEX]; 121 | backemf_gpio_map_t phaseB_backemf_map = backemf_gpio_mapping[PHASE_B_INDEX]; 122 | backemf_gpio_map_t phaseC_backemf_map = backemf_gpio_mapping[PHASE_C_INDEX]; 123 | 124 | backemf_gpio_map_t *appropriate_backemf_map; 125 | 126 | // MUXING LOGIC 127 | if (bldc_state == 2 || bldc_state == 5) { 128 | appropriate_backemf_map = &backemf_gpio_mapping[PHASE_A_INDEX]; 129 | } else if (bldc_state == 1 || bldc_state == 4) { 130 | appropriate_backemf_map = &backemf_gpio_mapping[PHASE_B_INDEX]; 131 | } else { 132 | appropriate_backemf_map = &backemf_gpio_mapping[PHASE_C_INDEX]; 133 | } 134 | 135 | if (GPIO_Pin == appropriate_backemf_map->GPIO_Pin) { 136 | // Correct BackEMF signal 137 | for (int8_t counter = 0; counter < 100; counter++) { 138 | bool bemf_state = HAL_GPIO_ReadPin(appropriate_backemf_map->GPIOx, 139 | appropriate_backemf_map->GPIO_Pin); 140 | // Debounce logic 141 | if (bldc_state & 1) // falling edge BEMF 142 | { 143 | if (bemf_state) { 144 | counter--; 145 | } 146 | } else // Falling Edge BEMF 147 | { 148 | if (!bemf_state) { 149 | counter--; 150 | } 151 | } 152 | } 153 | // Update the timer stuff 154 | pwm_tim_ccr = pwm_tim_cnt * 2; 155 | } 156 | #endif 157 | } 158 | -------------------------------------------------------------------------------- /Software/Core/Src/gpio.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file gpio.c 4 | * @brief This file provides code for the configuration 5 | * of all used GPIO pins. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "gpio.h" 22 | 23 | /* USER CODE BEGIN 0 */ 24 | 25 | /* USER CODE END 0 */ 26 | 27 | /*----------------------------------------------------------------------------*/ 28 | /* Configure GPIO */ 29 | /*----------------------------------------------------------------------------*/ 30 | /* USER CODE BEGIN 1 */ 31 | 32 | /* USER CODE END 1 */ 33 | 34 | /** Configure pins 35 | */ 36 | void MX_GPIO_Init(void) 37 | { 38 | 39 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 40 | 41 | /* GPIO Ports Clock Enable */ 42 | __HAL_RCC_GPIOA_CLK_ENABLE(); 43 | __HAL_RCC_GPIOB_CLK_ENABLE(); 44 | 45 | /*Configure GPIO pin Output Level */ 46 | HAL_GPIO_WritePin(GPIOA, OD_A_Pin|OD_B_Pin|OD_C_Pin, GPIO_PIN_RESET); 47 | 48 | /*Configure GPIO pin Output Level */ 49 | HAL_GPIO_WritePin(LED_GPIO_Port, LED_Pin, GPIO_PIN_RESET); 50 | 51 | /*Configure GPIO pins : PAPin PAPin PAPin */ 52 | GPIO_InitStruct.Pin = OD_A_Pin|OD_B_Pin|OD_C_Pin; 53 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 54 | GPIO_InitStruct.Pull = GPIO_NOPULL; 55 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 56 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 57 | 58 | /*Configure GPIO pin : PtPin */ 59 | GPIO_InitStruct.Pin = LED_Pin; 60 | GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 61 | GPIO_InitStruct.Pull = GPIO_NOPULL; 62 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 63 | HAL_GPIO_Init(LED_GPIO_Port, &GPIO_InitStruct); 64 | 65 | /*Configure GPIO pin : PtPin */ 66 | GPIO_InitStruct.Pin = BEMF_A_Pin; 67 | GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 68 | GPIO_InitStruct.Pull = GPIO_NOPULL; 69 | HAL_GPIO_Init(BEMF_A_GPIO_Port, &GPIO_InitStruct); 70 | 71 | /*Configure GPIO pins : PBPin PBPin */ 72 | GPIO_InitStruct.Pin = BEMF_B_Pin|BEMF_C_Pin; 73 | GPIO_InitStruct.Mode = GPIO_MODE_IT_RISING_FALLING; 74 | GPIO_InitStruct.Pull = GPIO_NOPULL; 75 | HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 76 | 77 | /* EXTI interrupt init*/ 78 | HAL_NVIC_SetPriority(EXTI4_15_IRQn, 2, 0); 79 | HAL_NVIC_EnableIRQ(EXTI4_15_IRQn); 80 | 81 | } 82 | 83 | /* USER CODE BEGIN 2 */ 84 | 85 | /* USER CODE END 2 */ 86 | 87 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 88 | -------------------------------------------------------------------------------- /Software/Core/Src/interface.c: -------------------------------------------------------------------------------- 1 | /* 2 | * interface.c 3 | * 4 | * Created on: Nov 5, 2021 5 | * Author: Sahil 6 | */ 7 | 8 | #include "interface.h" 9 | #include "bldc.h" 10 | #include "tim.h" 11 | 12 | void interface_init(void) 13 | { 14 | HAL_TIM_IC_Start_IT(&htim3, TIM_CHANNEL_1); //Main Channel 15 | HAL_TIM_IC_Start(&htim3, TIM_CHANNEL_2); //Alternate Channel 16 | } 17 | 18 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) 19 | { 20 | if(htim != &htim3) 21 | { 22 | return; 23 | } 24 | if(htim->Channel == HAL_TIM_ACTIVE_CHANNEL_1) //Triggered by rising edge 25 | { 26 | 27 | } 28 | } 29 | 30 | -------------------------------------------------------------------------------- /Software/Core/Src/main.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file : main.c 5 | * @brief : Main program body 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "main.h" 22 | #include "tim.h" 23 | #include "gpio.h" 24 | 25 | /* Private includes ----------------------------------------------------------*/ 26 | /* USER CODE BEGIN Includes */ 27 | #include "bldc.h" 28 | 29 | /* USER CODE END Includes */ 30 | 31 | /* Private typedef -----------------------------------------------------------*/ 32 | /* USER CODE BEGIN PTD */ 33 | 34 | /* USER CODE END PTD */ 35 | 36 | /* Private define ------------------------------------------------------------*/ 37 | /* USER CODE BEGIN PD */ 38 | /* USER CODE END PD */ 39 | 40 | /* Private macro -------------------------------------------------------------*/ 41 | /* USER CODE BEGIN PM */ 42 | 43 | /* USER CODE END PM */ 44 | 45 | /* Private variables ---------------------------------------------------------*/ 46 | 47 | /* USER CODE BEGIN PV */ 48 | 49 | /* USER CODE END PV */ 50 | 51 | /* Private function prototypes -----------------------------------------------*/ 52 | void SystemClock_Config(void); 53 | /* USER CODE BEGIN PFP */ 54 | 55 | /* USER CODE END PFP */ 56 | 57 | /* Private user code ---------------------------------------------------------*/ 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | 62 | /** 63 | * @brief The application entry point. 64 | * @retval int 65 | */ 66 | int main(void) 67 | { 68 | /* USER CODE BEGIN 1 */ 69 | 70 | /* USER CODE END 1 */ 71 | 72 | /* MCU Configuration--------------------------------------------------------*/ 73 | 74 | /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ 75 | HAL_Init(); 76 | 77 | /* USER CODE BEGIN Init */ 78 | 79 | /* USER CODE END Init */ 80 | 81 | /* Configure the system clock */ 82 | SystemClock_Config(); 83 | 84 | /* USER CODE BEGIN SysInit */ 85 | 86 | /* USER CODE END SysInit */ 87 | 88 | /* Initialize all configured peripherals */ 89 | MX_GPIO_Init(); 90 | MX_TIM2_Init(); 91 | MX_TIM3_Init(); 92 | /* USER CODE BEGIN 2 */ 93 | bldc_init(); 94 | 95 | /* USER CODE END 2 */ 96 | 97 | /* Infinite loop */ 98 | /* USER CODE BEGIN WHILE */ 99 | while (1) 100 | { 101 | bldc_loop(); 102 | /* USER CODE END WHILE */ 103 | 104 | /* USER CODE BEGIN 3 */ 105 | } 106 | /* USER CODE END 3 */ 107 | } 108 | 109 | /** 110 | * @brief System Clock Configuration 111 | * @retval None 112 | */ 113 | void SystemClock_Config(void) 114 | { 115 | RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 116 | RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 117 | 118 | /** Initializes the RCC Oscillators according to the specified parameters 119 | * in the RCC_OscInitTypeDef structure. 120 | */ 121 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 122 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; 123 | RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 124 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 125 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 126 | { 127 | Error_Handler(); 128 | } 129 | /** Initializes the CPU, AHB and APB buses clocks 130 | */ 131 | RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 132 | |RCC_CLOCKTYPE_PCLK1; 133 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 134 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 135 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 136 | 137 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 138 | { 139 | Error_Handler(); 140 | } 141 | } 142 | 143 | /* USER CODE BEGIN 4 */ 144 | 145 | /* USER CODE END 4 */ 146 | 147 | /** 148 | * @brief This function is executed in case of error occurrence. 149 | * @retval None 150 | */ 151 | void Error_Handler(void) 152 | { 153 | /* USER CODE BEGIN Error_Handler_Debug */ 154 | /* User can add his own implementation to report the HAL error return state */ 155 | __disable_irq(); 156 | while (1) 157 | { 158 | } 159 | /* USER CODE END Error_Handler_Debug */ 160 | } 161 | 162 | #ifdef USE_FULL_ASSERT 163 | /** 164 | * @brief Reports the name of the source file and the source line number 165 | * where the assert_param error has occurred. 166 | * @param file: pointer to the source file name 167 | * @param line: assert_param error line source number 168 | * @retval None 169 | */ 170 | void assert_failed(uint8_t *file, uint32_t line) 171 | { 172 | /* USER CODE BEGIN 6 */ 173 | /* User can add his own implementation to report the file name and line number, 174 | ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ 175 | /* USER CODE END 6 */ 176 | } 177 | #endif /* USE_FULL_ASSERT */ 178 | 179 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 180 | -------------------------------------------------------------------------------- /Software/Core/Src/pwm.c: -------------------------------------------------------------------------------- 1 | #include "pwm.h" 2 | 3 | #include "gpio.h" 4 | #include "main.h" 5 | #include "tim.h" 6 | #include 7 | #include 8 | 9 | #define NUM_PHASES (3UL) 10 | 11 | uint8_t PHASE_A_INDEX = 0; 12 | uint8_t PHASE_B_INDEX = 1; 13 | uint8_t PHASE_C_INDEX = 2; 14 | 15 | #define MAX_VAL_32_BIT (0xFFFFFFFF) 16 | #define MAX_VAL_16_BIT (0xFFFF) 17 | 18 | typedef struct PhasePinConfig { 19 | uint16_t OutputEnableGPIONum; 20 | GPIO_TypeDef *OutputEnableGPIOPort; 21 | TIM_HandleTypeDef *timer; 22 | uint16_t timer_channel; 23 | } PhasePinConfig_t; 24 | 25 | static PhasePinConfig_t PhasePinConfig[NUM_PHASES] = { 26 | {.OutputEnableGPIONum = OD_A_Pin, 27 | .OutputEnableGPIOPort = OD_A_GPIO_Port, 28 | .timer = &htim2, 29 | .timer_channel = TIM_CHANNEL_1}, 30 | {.OutputEnableGPIONum = OD_B_Pin, 31 | .OutputEnableGPIOPort = OD_B_GPIO_Port, 32 | .timer = &htim2, 33 | .timer_channel = TIM_CHANNEL_2}, 34 | {.OutputEnableGPIONum = OD_C_Pin, 35 | .OutputEnableGPIOPort = OD_C_GPIO_Port, 36 | .timer = &htim2, 37 | .timer_channel = TIM_CHANNEL_3}, 38 | 39 | }; 40 | 41 | static void timer_init(); 42 | static void set_duty_cycle(PhasePinConfig_t *config, uint32_t dutyValue, 43 | bool enableOutput); 44 | 45 | static void timer_init() { 46 | for (size_t i = 0; i < NUM_PHASES; i++) { 47 | PhasePinConfig_t *config = &PhasePinConfig[i]; 48 | HAL_TIM_PWM_Start(config->timer, config->timer_channel); 49 | __HAL_TIM_SET_COMPARE(config->timer, config->timer_channel, 0); 50 | HAL_GPIO_WritePin(config->OutputEnableGPIOPort, config->OutputEnableGPIONum, 51 | false); 52 | } 53 | } 54 | 55 | void pwm_init() { timer_init(); } 56 | 57 | void invert_phases(bool inverted) { 58 | if (inverted) { 59 | PHASE_B_INDEX = 2; 60 | PHASE_C_INDEX = 1; 61 | } else { 62 | PHASE_B_INDEX = 1; 63 | PHASE_C_INDEX = 2; 64 | } 65 | } 66 | 67 | void setPhaseADuty(uint32_t dutyValue, bool enableOutput) { 68 | PhasePinConfig_t *config = &PhasePinConfig[PHASE_A_INDEX]; 69 | set_duty_cycle(config, dutyValue, enableOutput); 70 | } 71 | 72 | void setPhaseBDuty(uint32_t dutyValue, bool enableOutput) { 73 | PhasePinConfig_t *config = &PhasePinConfig[PHASE_B_INDEX]; 74 | set_duty_cycle(config, dutyValue, enableOutput); 75 | } 76 | 77 | void setPhaseCDuty(uint32_t dutyValue, bool enableOutput) { 78 | PhasePinConfig_t *config = &PhasePinConfig[PHASE_C_INDEX]; 79 | set_duty_cycle(config, dutyValue, enableOutput); 80 | } 81 | 82 | static void set_duty_cycle(PhasePinConfig_t *config, uint32_t dutyValue, 83 | bool enableOutput) { 84 | if (dutyValue > TIM_ARR) { 85 | dutyValue = TIM_ARR; 86 | } 87 | // HAL_TIM_PWM_Stop(config->timer, config->timer_channel); 88 | __HAL_TIM_SET_COMPARE(config->timer, config->timer_channel, dutyValue); 89 | HAL_GPIO_WritePin(config->OutputEnableGPIOPort, config->OutputEnableGPIONum, 90 | enableOutput); 91 | // HAL_TIM_PWM_Start(config->timer, config->timer_channel); 92 | } 93 | -------------------------------------------------------------------------------- /Software/Core/Src/stm32f0xx_hal_msp.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f0xx_hal_msp.c 5 | * @brief This file provides code for the MSP Initialization 6 | * and de-Initialization codes. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2021 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | /* USER CODE END Header */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "main.h" 24 | /* USER CODE BEGIN Includes */ 25 | 26 | /* USER CODE END Includes */ 27 | 28 | /* Private typedef -----------------------------------------------------------*/ 29 | /* USER CODE BEGIN TD */ 30 | 31 | /* USER CODE END TD */ 32 | 33 | /* Private define ------------------------------------------------------------*/ 34 | /* USER CODE BEGIN Define */ 35 | 36 | /* USER CODE END Define */ 37 | 38 | /* Private macro -------------------------------------------------------------*/ 39 | /* USER CODE BEGIN Macro */ 40 | 41 | /* USER CODE END Macro */ 42 | 43 | /* Private variables ---------------------------------------------------------*/ 44 | /* USER CODE BEGIN PV */ 45 | 46 | /* USER CODE END PV */ 47 | 48 | /* Private function prototypes -----------------------------------------------*/ 49 | /* USER CODE BEGIN PFP */ 50 | 51 | /* USER CODE END PFP */ 52 | 53 | /* External functions --------------------------------------------------------*/ 54 | /* USER CODE BEGIN ExternalFunctions */ 55 | 56 | /* USER CODE END ExternalFunctions */ 57 | 58 | /* USER CODE BEGIN 0 */ 59 | 60 | /* USER CODE END 0 */ 61 | /** 62 | * Initializes the Global MSP. 63 | */ 64 | void HAL_MspInit(void) 65 | { 66 | /* USER CODE BEGIN MspInit 0 */ 67 | 68 | /* USER CODE END MspInit 0 */ 69 | 70 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 71 | __HAL_RCC_PWR_CLK_ENABLE(); 72 | 73 | /* System interrupt init*/ 74 | 75 | /* USER CODE BEGIN MspInit 1 */ 76 | 77 | /* USER CODE END MspInit 1 */ 78 | } 79 | 80 | /* USER CODE BEGIN 1 */ 81 | 82 | /* USER CODE END 1 */ 83 | 84 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 85 | -------------------------------------------------------------------------------- /Software/Core/Src/stm32f0xx_it.c: -------------------------------------------------------------------------------- 1 | /* USER CODE BEGIN Header */ 2 | /** 3 | ****************************************************************************** 4 | * @file stm32f0xx_it.c 5 | * @brief Interrupt Service Routines. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | /* USER CODE END Header */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "main.h" 23 | #include "stm32f0xx_it.h" 24 | /* Private includes ----------------------------------------------------------*/ 25 | /* USER CODE BEGIN Includes */ 26 | #include "bldc.h" 27 | /* USER CODE END Includes */ 28 | 29 | /* Private typedef -----------------------------------------------------------*/ 30 | /* USER CODE BEGIN TD */ 31 | 32 | /* USER CODE END TD */ 33 | 34 | /* Private define ------------------------------------------------------------*/ 35 | /* USER CODE BEGIN PD */ 36 | 37 | /* USER CODE END PD */ 38 | 39 | /* Private macro -------------------------------------------------------------*/ 40 | /* USER CODE BEGIN PM */ 41 | 42 | /* USER CODE END PM */ 43 | 44 | /* Private variables ---------------------------------------------------------*/ 45 | /* USER CODE BEGIN PV */ 46 | 47 | /* USER CODE END PV */ 48 | 49 | /* Private function prototypes -----------------------------------------------*/ 50 | /* USER CODE BEGIN PFP */ 51 | 52 | /* USER CODE END PFP */ 53 | 54 | /* Private user code ---------------------------------------------------------*/ 55 | /* USER CODE BEGIN 0 */ 56 | 57 | /* USER CODE END 0 */ 58 | 59 | /* External variables --------------------------------------------------------*/ 60 | extern TIM_HandleTypeDef htim2; 61 | extern TIM_HandleTypeDef htim3; 62 | /* USER CODE BEGIN EV */ 63 | 64 | /* USER CODE END EV */ 65 | 66 | /******************************************************************************/ 67 | /* Cortex-M0 Processor Interruption and Exception Handlers */ 68 | /******************************************************************************/ 69 | /** 70 | * @brief This function handles Non maskable interrupt. 71 | */ 72 | void NMI_Handler(void) 73 | { 74 | /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ 75 | 76 | /* USER CODE END NonMaskableInt_IRQn 0 */ 77 | /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ 78 | while (1) 79 | { 80 | } 81 | /* USER CODE END NonMaskableInt_IRQn 1 */ 82 | } 83 | 84 | /** 85 | * @brief This function handles Hard fault interrupt. 86 | */ 87 | void HardFault_Handler(void) 88 | { 89 | /* USER CODE BEGIN HardFault_IRQn 0 */ 90 | 91 | /* USER CODE END HardFault_IRQn 0 */ 92 | while (1) 93 | { 94 | /* USER CODE BEGIN W1_HardFault_IRQn 0 */ 95 | /* USER CODE END W1_HardFault_IRQn 0 */ 96 | } 97 | } 98 | 99 | /** 100 | * @brief This function handles System service call via SWI instruction. 101 | */ 102 | void SVC_Handler(void) 103 | { 104 | /* USER CODE BEGIN SVC_IRQn 0 */ 105 | 106 | /* USER CODE END SVC_IRQn 0 */ 107 | /* USER CODE BEGIN SVC_IRQn 1 */ 108 | 109 | /* USER CODE END SVC_IRQn 1 */ 110 | } 111 | 112 | /** 113 | * @brief This function handles Pendable request for system service. 114 | */ 115 | void PendSV_Handler(void) 116 | { 117 | /* USER CODE BEGIN PendSV_IRQn 0 */ 118 | 119 | /* USER CODE END PendSV_IRQn 0 */ 120 | /* USER CODE BEGIN PendSV_IRQn 1 */ 121 | 122 | /* USER CODE END PendSV_IRQn 1 */ 123 | } 124 | 125 | /** 126 | * @brief This function handles System tick timer. 127 | */ 128 | void SysTick_Handler(void) 129 | { 130 | /* USER CODE BEGIN SysTick_IRQn 0 */ 131 | 132 | /* USER CODE END SysTick_IRQn 0 */ 133 | HAL_IncTick(); 134 | /* USER CODE BEGIN SysTick_IRQn 1 */ 135 | 136 | /* USER CODE END SysTick_IRQn 1 */ 137 | } 138 | 139 | /******************************************************************************/ 140 | /* STM32F0xx Peripheral Interrupt Handlers */ 141 | /* Add here the Interrupt Handlers for the used peripherals. */ 142 | /* For the available peripheral interrupt handler names, */ 143 | /* please refer to the startup file (startup_stm32f0xx.s). */ 144 | /******************************************************************************/ 145 | 146 | /** 147 | * @brief This function handles EXTI line 4 to 15 interrupts. 148 | */ 149 | void EXTI4_15_IRQHandler(void) 150 | { 151 | /* USER CODE BEGIN EXTI4_15_IRQn 0 */ 152 | 153 | /* USER CODE END EXTI4_15_IRQn 0 */ 154 | HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_5); 155 | HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_6); 156 | HAL_GPIO_EXTI_IRQHandler(GPIO_PIN_7); 157 | /* USER CODE BEGIN EXTI4_15_IRQn 1 */ 158 | 159 | /* USER CODE END EXTI4_15_IRQn 1 */ 160 | } 161 | 162 | /** 163 | * @brief This function handles TIM2 global interrupt. 164 | */ 165 | void TIM2_IRQHandler(void) 166 | { 167 | /* USER CODE BEGIN TIM2_IRQn 0 */ 168 | 169 | /* USER CODE END TIM2_IRQn 0 */ 170 | HAL_TIM_IRQHandler(&htim2); 171 | /* USER CODE BEGIN TIM2_IRQn 1 */ 172 | 173 | /* USER CODE END TIM2_IRQn 1 */ 174 | } 175 | 176 | /** 177 | * @brief This function handles TIM3 global interrupt. 178 | */ 179 | void TIM3_IRQHandler(void) 180 | { 181 | /* USER CODE BEGIN TIM3_IRQn 0 */ 182 | 183 | /* USER CODE END TIM3_IRQn 0 */ 184 | HAL_TIM_IRQHandler(&htim3); 185 | /* USER CODE BEGIN TIM3_IRQn 1 */ 186 | 187 | /* USER CODE END TIM3_IRQn 1 */ 188 | } 189 | 190 | /* USER CODE BEGIN 1 */ 191 | 192 | /* USER CODE END 1 */ 193 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 194 | -------------------------------------------------------------------------------- /Software/Core/Src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file syscalls.c 4 | * @author Auto-generated by STM32CubeIDE 5 | * @brief STM32CubeIDE Minimal System calls file 6 | * 7 | * For more information about which c-functions 8 | * need which of these lowlevel functions 9 | * please consult the Newlib libc-manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | #include 28 | #include 29 | #include 30 | #include 31 | #include 32 | #include 33 | 34 | 35 | /* Variables */ 36 | extern int __io_putchar(int ch) __attribute__((weak)); 37 | extern int __io_getchar(void) __attribute__((weak)); 38 | 39 | 40 | char *__env[1] = { 0 }; 41 | char **environ = __env; 42 | 43 | 44 | /* Functions */ 45 | void initialise_monitor_handles() 46 | { 47 | } 48 | 49 | int _getpid(void) 50 | { 51 | return 1; 52 | } 53 | 54 | int _kill(int pid, int sig) 55 | { 56 | errno = EINVAL; 57 | return -1; 58 | } 59 | 60 | void _exit (int status) 61 | { 62 | _kill(status, -1); 63 | while (1) {} /* Make sure we hang here */ 64 | } 65 | 66 | __attribute__((weak)) int _read(int file, char *ptr, int len) 67 | { 68 | int DataIdx; 69 | 70 | for (DataIdx = 0; DataIdx < len; DataIdx++) 71 | { 72 | *ptr++ = __io_getchar(); 73 | } 74 | 75 | return len; 76 | } 77 | 78 | __attribute__((weak)) int _write(int file, char *ptr, int len) 79 | { 80 | int DataIdx; 81 | 82 | for (DataIdx = 0; DataIdx < len; DataIdx++) 83 | { 84 | __io_putchar(*ptr++); 85 | } 86 | return len; 87 | } 88 | 89 | int _close(int file) 90 | { 91 | return -1; 92 | } 93 | 94 | 95 | int _fstat(int file, struct stat *st) 96 | { 97 | st->st_mode = S_IFCHR; 98 | return 0; 99 | } 100 | 101 | int _isatty(int file) 102 | { 103 | return 1; 104 | } 105 | 106 | int _lseek(int file, int ptr, int dir) 107 | { 108 | return 0; 109 | } 110 | 111 | int _open(char *path, int flags, ...) 112 | { 113 | /* Pretend like we always fail */ 114 | return -1; 115 | } 116 | 117 | int _wait(int *status) 118 | { 119 | errno = ECHILD; 120 | return -1; 121 | } 122 | 123 | int _unlink(char *name) 124 | { 125 | errno = ENOENT; 126 | return -1; 127 | } 128 | 129 | int _times(struct tms *buf) 130 | { 131 | return -1; 132 | } 133 | 134 | int _stat(char *file, struct stat *st) 135 | { 136 | st->st_mode = S_IFCHR; 137 | return 0; 138 | } 139 | 140 | int _link(char *old, char *new) 141 | { 142 | errno = EMLINK; 143 | return -1; 144 | } 145 | 146 | int _fork(void) 147 | { 148 | errno = EAGAIN; 149 | return -1; 150 | } 151 | 152 | int _execve(char *name, char **argv, char **env) 153 | { 154 | errno = ENOMEM; 155 | return -1; 156 | } 157 | -------------------------------------------------------------------------------- /Software/Core/Src/sysmem.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file sysmem.c 4 | * @author Generated by STM32CubeIDE 5 | * @brief STM32CubeIDE System Memory calls file 6 | * 7 | * For more information about which C functions 8 | * need which of these lowlevel functions 9 | * please consult the newlib libc manual 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | *

© Copyright (c) 2020 STMicroelectronics. 14 | * All rights reserved.

15 | * 16 | * This software component is licensed by ST under BSD 3-Clause license, 17 | * the "License"; You may not use this file except in compliance with the 18 | * License. You may obtain a copy of the License at: 19 | * opensource.org/licenses/BSD-3-Clause 20 | * 21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes */ 25 | #include 26 | #include 27 | 28 | /** 29 | * Pointer to the current high watermark of the heap usage 30 | */ 31 | static uint8_t *__sbrk_heap_end = NULL; 32 | 33 | /** 34 | * @brief _sbrk() allocates memory to the newlib heap and is used by malloc 35 | * and others from the C library 36 | * 37 | * @verbatim 38 | * ############################################################################ 39 | * # .data # .bss # newlib heap # MSP stack # 40 | * # # # # Reserved by _Min_Stack_Size # 41 | * ############################################################################ 42 | * ^-- RAM start ^-- _end _estack, RAM end --^ 43 | * @endverbatim 44 | * 45 | * This implementation starts allocating at the '_end' linker symbol 46 | * The '_Min_Stack_Size' linker symbol reserves a memory for the MSP stack 47 | * The implementation considers '_estack' linker symbol to be RAM end 48 | * NOTE: If the MSP stack, at any point during execution, grows larger than the 49 | * reserved size, please increase the '_Min_Stack_Size'. 50 | * 51 | * @param incr Memory size 52 | * @return Pointer to allocated memory 53 | */ 54 | void *_sbrk(ptrdiff_t incr) 55 | { 56 | extern uint8_t _end; /* Symbol defined in the linker script */ 57 | extern uint8_t _estack; /* Symbol defined in the linker script */ 58 | extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ 59 | const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; 60 | const uint8_t *max_heap = (uint8_t *)stack_limit; 61 | uint8_t *prev_heap_end; 62 | 63 | /* Initialize heap end at first call */ 64 | if (NULL == __sbrk_heap_end) 65 | { 66 | __sbrk_heap_end = &_end; 67 | } 68 | 69 | /* Protect heap from growing into the reserved MSP stack */ 70 | if (__sbrk_heap_end + incr > max_heap) 71 | { 72 | errno = ENOMEM; 73 | return (void *)-1; 74 | } 75 | 76 | prev_heap_end = __sbrk_heap_end; 77 | __sbrk_heap_end += incr; 78 | 79 | return (void *)prev_heap_end; 80 | } 81 | -------------------------------------------------------------------------------- /Software/Core/Src/system_stm32f0xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.c 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. 6 | * 7 | * 1. This file provides two functions and one global variable to be called from 8 | * user application: 9 | * - SystemInit(): This function is called at startup just after reset and 10 | * before branch to main program. This call is made inside 11 | * the "startup_stm32f0xx.s" file. 12 | * 13 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 14 | * by the user application to setup the SysTick 15 | * timer or configure other parameters. 16 | * 17 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 18 | * be called whenever the core clock is changed 19 | * during program execution. 20 | * 21 | * 22 | ****************************************************************************** 23 | * @attention 24 | * 25 | *

© Copyright (c) 2016 STMicroelectronics. 26 | * All rights reserved.

27 | * 28 | * This software component is licensed by ST under BSD 3-Clause license, 29 | * the "License"; You may not use this file except in compliance with the 30 | * License. You may obtain a copy of the License at: 31 | * opensource.org/licenses/BSD-3-Clause 32 | * 33 | ****************************************************************************** 34 | */ 35 | 36 | /** @addtogroup CMSIS 37 | * @{ 38 | */ 39 | 40 | /** @addtogroup stm32f0xx_system 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup STM32F0xx_System_Private_Includes 45 | * @{ 46 | */ 47 | 48 | #include "stm32f0xx.h" 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions 55 | * @{ 56 | */ 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /** @addtogroup STM32F0xx_System_Private_Defines 63 | * @{ 64 | */ 65 | #if !defined (HSE_VALUE) 66 | #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. 67 | This value can be provided and adapted by the user application. */ 68 | #endif /* HSE_VALUE */ 69 | 70 | #if !defined (HSI_VALUE) 71 | #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. 72 | This value can be provided and adapted by the user application. */ 73 | #endif /* HSI_VALUE */ 74 | 75 | #if !defined (HSI48_VALUE) 76 | #define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. 77 | This value can be provided and adapted by the user application. */ 78 | #endif /* HSI48_VALUE */ 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @addtogroup STM32F0xx_System_Private_Macros 84 | * @{ 85 | */ 86 | 87 | /** 88 | * @} 89 | */ 90 | 91 | /** @addtogroup STM32F0xx_System_Private_Variables 92 | * @{ 93 | */ 94 | /* This variable is updated in three ways: 95 | 1) by calling CMSIS function SystemCoreClockUpdate() 96 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() 97 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 98 | Note: If you use this function to configure the system clock; then there 99 | is no need to call the 2 first functions listed above, since SystemCoreClock 100 | variable is updated automatically. 101 | */ 102 | uint32_t SystemCoreClock = 8000000; 103 | 104 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 105 | const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes 112 | * @{ 113 | */ 114 | 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @addtogroup STM32F0xx_System_Private_Functions 120 | * @{ 121 | */ 122 | 123 | /** 124 | * @brief Setup the microcontroller system 125 | * @param None 126 | * @retval None 127 | */ 128 | void SystemInit(void) 129 | { 130 | /* NOTE :SystemInit(): This function is called at startup just after reset and 131 | before branch to main program. This call is made inside 132 | the "startup_stm32f0xx.s" file. 133 | User can setups the default system clock (System clock source, PLL Multiplier 134 | and Divider factors, AHB/APBx prescalers and Flash settings). 135 | */ 136 | } 137 | 138 | /** 139 | * @brief Update SystemCoreClock variable according to Clock Register Values. 140 | * The SystemCoreClock variable contains the core clock (HCLK), it can 141 | * be used by the user application to setup the SysTick timer or configure 142 | * other parameters. 143 | * 144 | * @note Each time the core clock (HCLK) changes, this function must be called 145 | * to update SystemCoreClock variable value. Otherwise, any configuration 146 | * based on this variable will be incorrect. 147 | * 148 | * @note - The system frequency computed by this function is not the real 149 | * frequency in the chip. It is calculated based on the predefined 150 | * constant and the selected clock source: 151 | * 152 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 153 | * 154 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 155 | * 156 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 157 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 158 | * 159 | * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value 160 | * 8 MHz) but the real value may vary depending on the variations 161 | * in voltage and temperature. 162 | * 163 | * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value 164 | * depends on the application requirements), user has to ensure that HSE_VALUE 165 | * is same as the real frequency of the crystal used. Otherwise, this function 166 | * may have wrong result. 167 | * 168 | * - The result of this function could be not correct when using fractional 169 | * value for HSE crystal. 170 | * 171 | * @param None 172 | * @retval None 173 | */ 174 | void SystemCoreClockUpdate (void) 175 | { 176 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; 177 | 178 | /* Get SYSCLK source -------------------------------------------------------*/ 179 | tmp = RCC->CFGR & RCC_CFGR_SWS; 180 | 181 | switch (tmp) 182 | { 183 | case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ 184 | SystemCoreClock = HSI_VALUE; 185 | break; 186 | case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ 187 | SystemCoreClock = HSE_VALUE; 188 | break; 189 | case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ 190 | /* Get PLL clock source and multiplication factor ----------------------*/ 191 | pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; 192 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 193 | pllmull = ( pllmull >> 18) + 2; 194 | predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; 195 | 196 | if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) 197 | { 198 | /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ 199 | SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; 200 | } 201 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) 202 | else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) 203 | { 204 | /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ 205 | SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; 206 | } 207 | #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ 208 | else 209 | { 210 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ 211 | || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ 212 | || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) 213 | /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ 214 | SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; 215 | #else 216 | /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ 217 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 218 | #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || 219 | STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || 220 | STM32F091xC || STM32F098xx || STM32F030xC */ 221 | } 222 | break; 223 | default: /* HSI used as system clock */ 224 | SystemCoreClock = HSI_VALUE; 225 | break; 226 | } 227 | /* Compute HCLK clock frequency ----------------*/ 228 | /* Get HCLK prescaler */ 229 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 230 | /* HCLK clock frequency */ 231 | SystemCoreClock >>= tmp; 232 | } 233 | 234 | /** 235 | * @} 236 | */ 237 | 238 | /** 239 | * @} 240 | */ 241 | 242 | /** 243 | * @} 244 | */ 245 | 246 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 247 | 248 | -------------------------------------------------------------------------------- /Software/Core/Src/tim.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file tim.c 4 | * @brief This file provides code for the configuration 5 | * of the TIM instances. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2021 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Includes ------------------------------------------------------------------*/ 21 | #include "tim.h" 22 | 23 | /* USER CODE BEGIN 0 */ 24 | 25 | /* USER CODE END 0 */ 26 | 27 | TIM_HandleTypeDef htim2; 28 | TIM_HandleTypeDef htim3; 29 | 30 | /* TIM2 init function */ 31 | void MX_TIM2_Init(void) 32 | { 33 | 34 | /* USER CODE BEGIN TIM2_Init 0 */ 35 | 36 | /* USER CODE END TIM2_Init 0 */ 37 | 38 | TIM_MasterConfigTypeDef sMasterConfig = {0}; 39 | TIM_OC_InitTypeDef sConfigOC = {0}; 40 | 41 | /* USER CODE BEGIN TIM2_Init 1 */ 42 | 43 | /* USER CODE END TIM2_Init 1 */ 44 | htim2.Instance = TIM2; 45 | htim2.Init.Prescaler = 8-1; 46 | htim2.Init.CounterMode = TIM_COUNTERMODE_UP; 47 | htim2.Init.Period = 100; 48 | htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 49 | htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 50 | if (HAL_TIM_PWM_Init(&htim2) != HAL_OK) 51 | { 52 | Error_Handler(); 53 | } 54 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 55 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 56 | if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK) 57 | { 58 | Error_Handler(); 59 | } 60 | sConfigOC.OCMode = TIM_OCMODE_PWM1; 61 | sConfigOC.Pulse = 0; 62 | sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 63 | sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 64 | if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 65 | { 66 | Error_Handler(); 67 | } 68 | if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 69 | { 70 | Error_Handler(); 71 | } 72 | if (HAL_TIM_PWM_ConfigChannel(&htim2, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 73 | { 74 | Error_Handler(); 75 | } 76 | /* USER CODE BEGIN TIM2_Init 2 */ 77 | 78 | /* USER CODE END TIM2_Init 2 */ 79 | HAL_TIM_MspPostInit(&htim2); 80 | 81 | } 82 | /* TIM3 init function */ 83 | void MX_TIM3_Init(void) 84 | { 85 | 86 | /* USER CODE BEGIN TIM3_Init 0 */ 87 | 88 | /* USER CODE END TIM3_Init 0 */ 89 | 90 | TIM_SlaveConfigTypeDef sSlaveConfig = {0}; 91 | TIM_IC_InitTypeDef sConfigIC = {0}; 92 | TIM_MasterConfigTypeDef sMasterConfig = {0}; 93 | 94 | /* USER CODE BEGIN TIM3_Init 1 */ 95 | 96 | /* USER CODE END TIM3_Init 1 */ 97 | htim3.Instance = TIM3; 98 | htim3.Init.Prescaler = 0; 99 | htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 100 | htim3.Init.Period = 65535; 101 | htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 102 | htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 103 | if (HAL_TIM_IC_Init(&htim3) != HAL_OK) 104 | { 105 | Error_Handler(); 106 | } 107 | sSlaveConfig.SlaveMode = TIM_SLAVEMODE_RESET; 108 | sSlaveConfig.InputTrigger = TIM_TS_TI1FP1; 109 | sSlaveConfig.TriggerPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 110 | sSlaveConfig.TriggerPrescaler = TIM_ICPSC_DIV1; 111 | sSlaveConfig.TriggerFilter = 0; 112 | if (HAL_TIM_SlaveConfigSynchro(&htim3, &sSlaveConfig) != HAL_OK) 113 | { 114 | Error_Handler(); 115 | } 116 | sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING; 117 | sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI; 118 | sConfigIC.ICPrescaler = TIM_ICPSC_DIV1; 119 | sConfigIC.ICFilter = 0; 120 | if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_1) != HAL_OK) 121 | { 122 | Error_Handler(); 123 | } 124 | sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_FALLING; 125 | sConfigIC.ICSelection = TIM_ICSELECTION_INDIRECTTI; 126 | if (HAL_TIM_IC_ConfigChannel(&htim3, &sConfigIC, TIM_CHANNEL_2) != HAL_OK) 127 | { 128 | Error_Handler(); 129 | } 130 | sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 131 | sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 132 | if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 133 | { 134 | Error_Handler(); 135 | } 136 | /* USER CODE BEGIN TIM3_Init 2 */ 137 | 138 | /* USER CODE END TIM3_Init 2 */ 139 | 140 | } 141 | 142 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* tim_pwmHandle) 143 | { 144 | 145 | if(tim_pwmHandle->Instance==TIM2) 146 | { 147 | /* USER CODE BEGIN TIM2_MspInit 0 */ 148 | 149 | /* USER CODE END TIM2_MspInit 0 */ 150 | /* TIM2 clock enable */ 151 | __HAL_RCC_TIM2_CLK_ENABLE(); 152 | 153 | /* TIM2 interrupt Init */ 154 | HAL_NVIC_SetPriority(TIM2_IRQn, 1, 0); 155 | HAL_NVIC_EnableIRQ(TIM2_IRQn); 156 | /* USER CODE BEGIN TIM2_MspInit 1 */ 157 | 158 | /* USER CODE END TIM2_MspInit 1 */ 159 | } 160 | } 161 | 162 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef* tim_icHandle) 163 | { 164 | 165 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 166 | if(tim_icHandle->Instance==TIM3) 167 | { 168 | /* USER CODE BEGIN TIM3_MspInit 0 */ 169 | 170 | /* USER CODE END TIM3_MspInit 0 */ 171 | /* TIM3 clock enable */ 172 | __HAL_RCC_TIM3_CLK_ENABLE(); 173 | 174 | __HAL_RCC_GPIOA_CLK_ENABLE(); 175 | /**TIM3 GPIO Configuration 176 | PA6 ------> TIM3_CH1 177 | */ 178 | GPIO_InitStruct.Pin = GPIO_PIN_6; 179 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 180 | GPIO_InitStruct.Pull = GPIO_NOPULL; 181 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 182 | GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; 183 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 184 | 185 | /* TIM3 interrupt Init */ 186 | HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0); 187 | HAL_NVIC_EnableIRQ(TIM3_IRQn); 188 | /* USER CODE BEGIN TIM3_MspInit 1 */ 189 | 190 | /* USER CODE END TIM3_MspInit 1 */ 191 | } 192 | } 193 | void HAL_TIM_MspPostInit(TIM_HandleTypeDef* timHandle) 194 | { 195 | 196 | GPIO_InitTypeDef GPIO_InitStruct = {0}; 197 | if(timHandle->Instance==TIM2) 198 | { 199 | /* USER CODE BEGIN TIM2_MspPostInit 0 */ 200 | 201 | /* USER CODE END TIM2_MspPostInit 0 */ 202 | 203 | __HAL_RCC_GPIOA_CLK_ENABLE(); 204 | /**TIM2 GPIO Configuration 205 | PA0 ------> TIM2_CH1 206 | PA1 ------> TIM2_CH2 207 | PA2 ------> TIM2_CH3 208 | */ 209 | GPIO_InitStruct.Pin = PWM_A_Pin|PWM_B_Pin|PWM_C_Pin; 210 | GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 211 | GPIO_InitStruct.Pull = GPIO_NOPULL; 212 | GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 213 | GPIO_InitStruct.Alternate = GPIO_AF2_TIM2; 214 | HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 215 | 216 | /* USER CODE BEGIN TIM2_MspPostInit 1 */ 217 | 218 | /* USER CODE END TIM2_MspPostInit 1 */ 219 | } 220 | 221 | } 222 | 223 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* tim_pwmHandle) 224 | { 225 | 226 | if(tim_pwmHandle->Instance==TIM2) 227 | { 228 | /* USER CODE BEGIN TIM2_MspDeInit 0 */ 229 | 230 | /* USER CODE END TIM2_MspDeInit 0 */ 231 | /* Peripheral clock disable */ 232 | __HAL_RCC_TIM2_CLK_DISABLE(); 233 | 234 | /* TIM2 interrupt Deinit */ 235 | HAL_NVIC_DisableIRQ(TIM2_IRQn); 236 | /* USER CODE BEGIN TIM2_MspDeInit 1 */ 237 | 238 | /* USER CODE END TIM2_MspDeInit 1 */ 239 | } 240 | } 241 | 242 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef* tim_icHandle) 243 | { 244 | 245 | if(tim_icHandle->Instance==TIM3) 246 | { 247 | /* USER CODE BEGIN TIM3_MspDeInit 0 */ 248 | 249 | /* USER CODE END TIM3_MspDeInit 0 */ 250 | /* Peripheral clock disable */ 251 | __HAL_RCC_TIM3_CLK_DISABLE(); 252 | 253 | /**TIM3 GPIO Configuration 254 | PA6 ------> TIM3_CH1 255 | */ 256 | HAL_GPIO_DeInit(GPIOA, GPIO_PIN_6); 257 | 258 | /* TIM3 interrupt Deinit */ 259 | HAL_NVIC_DisableIRQ(TIM3_IRQn); 260 | /* USER CODE BEGIN TIM3_MspDeInit 1 */ 261 | 262 | /* USER CODE END TIM3_MspDeInit 1 */ 263 | } 264 | } 265 | 266 | /* USER CODE BEGIN 1 */ 267 | 268 | /* USER CODE END 1 */ 269 | 270 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 271 | -------------------------------------------------------------------------------- /Software/Core/Startup/startup_stm32f042k6tx.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32f042x6.s 4 | * @author MCD Application Team 5 | * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain. 6 | * This module performs: 7 | * - Set the initial SP 8 | * - Set the initial PC == Reset_Handler, 9 | * - Set the vector table entries with the exceptions ISR address 10 | * - Branches to main in the C library (which eventually 11 | * calls main()). 12 | * After Reset the Cortex-M0 processor is in Thread mode, 13 | * priority is Privileged, and the Stack is set to Main. 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | *

© Copyright (c) 2016 STMicroelectronics. 18 | * All rights reserved.

19 | * 20 | * This software component is licensed by ST under BSD 3-Clause license, 21 | * the "License"; You may not use this file except in compliance with the 22 | * License. You may obtain a copy of the License at: 23 | * opensource.org/licenses/BSD-3-Clause 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | .syntax unified 29 | .cpu cortex-m0 30 | .fpu softvfp 31 | .thumb 32 | 33 | .global g_pfnVectors 34 | .global Default_Handler 35 | 36 | /* start address for the initialization values of the .data section. 37 | defined in linker script */ 38 | .word _sidata 39 | /* start address for the .data section. defined in linker script */ 40 | .word _sdata 41 | /* end address for the .data section. defined in linker script */ 42 | .word _edata 43 | /* start address for the .bss section. defined in linker script */ 44 | .word _sbss 45 | /* end address for the .bss section. defined in linker script */ 46 | .word _ebss 47 | 48 | /** 49 | * @brief This is the code that gets called when the processor first 50 | * starts execution following a reset event. Only the absolutely 51 | * necessary set is performed, after which the application 52 | * supplied main() routine is called. 53 | * @param None 54 | * @retval : None 55 | */ 56 | 57 | .section .text.Reset_Handler 58 | .weak Reset_Handler 59 | .type Reset_Handler, %function 60 | Reset_Handler: 61 | ldr r0, =_estack 62 | mov sp, r0 /* set stack pointer */ 63 | 64 | /*Check if boot space corresponds to test memory*/ 65 | 66 | LDR R0,=0x00000004 67 | LDR R1, [R0] 68 | LSRS R1, R1, #24 69 | LDR R2,=0x1F 70 | CMP R1, R2 71 | BNE ApplicationStart 72 | 73 | /*SYSCFG clock enable*/ 74 | 75 | LDR R0,=0x40021018 76 | LDR R1,=0x00000001 77 | STR R1, [R0] 78 | 79 | /*Set CFGR1 register with flash memory remap at address 0*/ 80 | LDR R0,=0x40010000 81 | LDR R1,=0x00000000 82 | STR R1, [R0] 83 | 84 | ApplicationStart: 85 | /* Copy the data segment initializers from flash to SRAM */ 86 | ldr r0, =_sdata 87 | ldr r1, =_edata 88 | ldr r2, =_sidata 89 | movs r3, #0 90 | b LoopCopyDataInit 91 | 92 | CopyDataInit: 93 | ldr r4, [r2, r3] 94 | str r4, [r0, r3] 95 | adds r3, r3, #4 96 | 97 | LoopCopyDataInit: 98 | adds r4, r0, r3 99 | cmp r4, r1 100 | bcc CopyDataInit 101 | 102 | /* Zero fill the bss segment. */ 103 | ldr r2, =_sbss 104 | ldr r4, =_ebss 105 | movs r3, #0 106 | b LoopFillZerobss 107 | 108 | FillZerobss: 109 | str r3, [r2] 110 | adds r2, r2, #4 111 | 112 | LoopFillZerobss: 113 | cmp r2, r4 114 | bcc FillZerobss 115 | 116 | /* Call the clock system intitialization function.*/ 117 | bl SystemInit 118 | /* Call static constructors */ 119 | bl __libc_init_array 120 | /* Call the application's entry point.*/ 121 | bl main 122 | 123 | LoopForever: 124 | b LoopForever 125 | 126 | 127 | .size Reset_Handler, .-Reset_Handler 128 | 129 | /** 130 | * @brief This is the code that gets called when the processor receives an 131 | * unexpected interrupt. This simply enters an infinite loop, preserving 132 | * the system state for examination by a debugger. 133 | * 134 | * @param None 135 | * @retval : None 136 | */ 137 | .section .text.Default_Handler,"ax",%progbits 138 | Default_Handler: 139 | Infinite_Loop: 140 | b Infinite_Loop 141 | .size Default_Handler, .-Default_Handler 142 | /****************************************************************************** 143 | * 144 | * The minimal vector table for a Cortex M0. Note that the proper constructs 145 | * must be placed on this to ensure that it ends up at physical address 146 | * 0x0000.0000. 147 | * 148 | ******************************************************************************/ 149 | .section .isr_vector,"a",%progbits 150 | .type g_pfnVectors, %object 151 | .size g_pfnVectors, .-g_pfnVectors 152 | 153 | 154 | g_pfnVectors: 155 | .word _estack 156 | .word Reset_Handler 157 | .word NMI_Handler 158 | .word HardFault_Handler 159 | .word 0 160 | .word 0 161 | .word 0 162 | .word 0 163 | .word 0 164 | .word 0 165 | .word 0 166 | .word SVC_Handler 167 | .word 0 168 | .word 0 169 | .word PendSV_Handler 170 | .word SysTick_Handler 171 | .word WWDG_IRQHandler /* Window WatchDog */ 172 | .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ 173 | .word RTC_IRQHandler /* RTC through the EXTI line */ 174 | .word FLASH_IRQHandler /* FLASH */ 175 | .word RCC_CRS_IRQHandler /* RCC and CRS */ 176 | .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ 177 | .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ 178 | .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ 179 | .word TSC_IRQHandler /* TSC */ 180 | .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ 181 | .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ 182 | .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ 183 | .word ADC1_IRQHandler /* ADC1 */ 184 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ 185 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ 186 | .word TIM2_IRQHandler /* TIM2 */ 187 | .word TIM3_IRQHandler /* TIM3 */ 188 | .word 0 /* Reserved */ 189 | .word 0 /* Reserved */ 190 | .word TIM14_IRQHandler /* TIM14 */ 191 | .word 0 /* Reserved */ 192 | .word TIM16_IRQHandler /* TIM16 */ 193 | .word TIM17_IRQHandler /* TIM17 */ 194 | .word I2C1_IRQHandler /* I2C1 */ 195 | .word 0 /* Reserved */ 196 | .word SPI1_IRQHandler /* SPI1 */ 197 | .word SPI2_IRQHandler /* SPI2 */ 198 | .word USART1_IRQHandler /* USART1 */ 199 | .word USART2_IRQHandler /* USART2 */ 200 | .word 0 /* Reserved */ 201 | .word CEC_CAN_IRQHandler /* CEC and CAN */ 202 | .word USB_IRQHandler /* USB */ 203 | 204 | /******************************************************************************* 205 | * 206 | * Provide weak aliases for each Exception handler to the Default_Handler. 207 | * As they are weak aliases, any function with the same name will override 208 | * this definition. 209 | * 210 | *******************************************************************************/ 211 | 212 | .weak NMI_Handler 213 | .thumb_set NMI_Handler,Default_Handler 214 | 215 | .weak HardFault_Handler 216 | .thumb_set HardFault_Handler,Default_Handler 217 | 218 | .weak SVC_Handler 219 | .thumb_set SVC_Handler,Default_Handler 220 | 221 | .weak PendSV_Handler 222 | .thumb_set PendSV_Handler,Default_Handler 223 | 224 | .weak SysTick_Handler 225 | .thumb_set SysTick_Handler,Default_Handler 226 | 227 | .weak WWDG_IRQHandler 228 | .thumb_set WWDG_IRQHandler,Default_Handler 229 | 230 | .weak PVD_VDDIO2_IRQHandler 231 | .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler 232 | 233 | .weak RTC_IRQHandler 234 | .thumb_set RTC_IRQHandler,Default_Handler 235 | 236 | .weak FLASH_IRQHandler 237 | .thumb_set FLASH_IRQHandler,Default_Handler 238 | 239 | .weak RCC_CRS_IRQHandler 240 | .thumb_set RCC_CRS_IRQHandler,Default_Handler 241 | 242 | .weak EXTI0_1_IRQHandler 243 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 244 | 245 | .weak EXTI2_3_IRQHandler 246 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 247 | 248 | .weak EXTI4_15_IRQHandler 249 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 250 | 251 | .weak TSC_IRQHandler 252 | .thumb_set TSC_IRQHandler,Default_Handler 253 | 254 | .weak DMA1_Channel1_IRQHandler 255 | .thumb_set DMA1_Channel1_IRQHandler,Default_Handler 256 | 257 | .weak DMA1_Channel2_3_IRQHandler 258 | .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler 259 | 260 | .weak DMA1_Channel4_5_IRQHandler 261 | .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler 262 | 263 | .weak ADC1_IRQHandler 264 | .thumb_set ADC1_IRQHandler,Default_Handler 265 | 266 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 267 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 268 | 269 | .weak TIM1_CC_IRQHandler 270 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 271 | 272 | .weak TIM2_IRQHandler 273 | .thumb_set TIM2_IRQHandler,Default_Handler 274 | 275 | .weak TIM3_IRQHandler 276 | .thumb_set TIM3_IRQHandler,Default_Handler 277 | 278 | .weak TIM14_IRQHandler 279 | .thumb_set TIM14_IRQHandler,Default_Handler 280 | 281 | .weak TIM16_IRQHandler 282 | .thumb_set TIM16_IRQHandler,Default_Handler 283 | 284 | .weak TIM17_IRQHandler 285 | .thumb_set TIM17_IRQHandler,Default_Handler 286 | 287 | .weak I2C1_IRQHandler 288 | .thumb_set I2C1_IRQHandler,Default_Handler 289 | 290 | .weak SPI1_IRQHandler 291 | .thumb_set SPI1_IRQHandler,Default_Handler 292 | 293 | .weak SPI2_IRQHandler 294 | .thumb_set SPI2_IRQHandler,Default_Handler 295 | 296 | .weak USART1_IRQHandler 297 | .thumb_set USART1_IRQHandler,Default_Handler 298 | 299 | .weak USART2_IRQHandler 300 | .thumb_set USART2_IRQHandler,Default_Handler 301 | 302 | .weak CEC_CAN_IRQHandler 303 | .thumb_set CEC_CAN_IRQHandler,Default_Handler 304 | 305 | .weak USB_IRQHandler 306 | .thumb_set USB_IRQHandler,Default_Handler 307 | 308 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 309 | 310 | -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sahil-kale/SensorlessESCSoftware/7f379359967c7beaa12021386578f4df11a52acb/Software/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sahil-kale/SensorlessESCSoftware/7f379359967c7beaa12021386578f4df11a52acb/Software/Drivers/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.h 4 | * @author MCD Application Team 5 | * @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /** @addtogroup CMSIS 21 | * @{ 22 | */ 23 | 24 | /** @addtogroup stm32f0xx_system 25 | * @{ 26 | */ 27 | 28 | /** 29 | * @brief Define to prevent recursive inclusion 30 | */ 31 | #ifndef __SYSTEM_STM32F0XX_H 32 | #define __SYSTEM_STM32F0XX_H 33 | 34 | #ifdef __cplusplus 35 | extern "C" { 36 | #endif 37 | 38 | /** @addtogroup STM32F0xx_System_Includes 39 | * @{ 40 | */ 41 | 42 | /** 43 | * @} 44 | */ 45 | 46 | 47 | /** @addtogroup STM32F0xx_System_Exported_types 48 | * @{ 49 | */ 50 | /* This variable is updated in three ways: 51 | 1) by calling CMSIS function SystemCoreClockUpdate() 52 | 3) by calling HAL API function HAL_RCC_GetHCLKFreq() 53 | 3) by calling HAL API function HAL_RCC_ClockConfig() 54 | Note: If you use this function to configure the system clock; then there 55 | is no need to call the 2 first functions listed above, since SystemCoreClock 56 | variable is updated automatically. 57 | */ 58 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 59 | extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ 60 | extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @addtogroup STM32F0xx_System_Exported_Constants 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @addtogroup STM32F0xx_System_Exported_Macros 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @} 80 | */ 81 | 82 | /** @addtogroup STM32F0xx_System_Exported_Functions 83 | * @{ 84 | */ 85 | 86 | extern void SystemInit(void); 87 | extern void SystemCoreClockUpdate(void); 88 | /** 89 | * @} 90 | */ 91 | 92 | #ifdef __cplusplus 93 | } 94 | #endif 95 | 96 | #endif /*__SYSTEM_STM32F0XX_H */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 106 | -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Include/cmsis_compiler.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_compiler.h 3 | * @brief CMSIS compiler generic header file 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #ifndef __CMSIS_COMPILER_H 26 | #define __CMSIS_COMPILER_H 27 | 28 | #include 29 | 30 | /* 31 | * Arm Compiler 4/5 32 | */ 33 | #if defined ( __CC_ARM ) 34 | #include "cmsis_armcc.h" 35 | 36 | 37 | /* 38 | * Arm Compiler 6 (armclang) 39 | */ 40 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) 41 | #include "cmsis_armclang.h" 42 | 43 | 44 | /* 45 | * GNU Compiler 46 | */ 47 | #elif defined ( __GNUC__ ) 48 | #include "cmsis_gcc.h" 49 | 50 | 51 | /* 52 | * IAR Compiler 53 | */ 54 | #elif defined ( __ICCARM__ ) 55 | #include 56 | 57 | 58 | /* 59 | * TI Arm Compiler 60 | */ 61 | #elif defined ( __TI_ARM__ ) 62 | #include 63 | 64 | #ifndef __ASM 65 | #define __ASM __asm 66 | #endif 67 | #ifndef __INLINE 68 | #define __INLINE inline 69 | #endif 70 | #ifndef __STATIC_INLINE 71 | #define __STATIC_INLINE static inline 72 | #endif 73 | #ifndef __STATIC_FORCEINLINE 74 | #define __STATIC_FORCEINLINE __STATIC_INLINE 75 | #endif 76 | #ifndef __NO_RETURN 77 | #define __NO_RETURN __attribute__((noreturn)) 78 | #endif 79 | #ifndef __USED 80 | #define __USED __attribute__((used)) 81 | #endif 82 | #ifndef __WEAK 83 | #define __WEAK __attribute__((weak)) 84 | #endif 85 | #ifndef __PACKED 86 | #define __PACKED __attribute__((packed)) 87 | #endif 88 | #ifndef __PACKED_STRUCT 89 | #define __PACKED_STRUCT struct __attribute__((packed)) 90 | #endif 91 | #ifndef __PACKED_UNION 92 | #define __PACKED_UNION union __attribute__((packed)) 93 | #endif 94 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 95 | struct __attribute__((packed)) T_UINT32 { uint32_t v; }; 96 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 97 | #endif 98 | #ifndef __UNALIGNED_UINT16_WRITE 99 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 100 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) 101 | #endif 102 | #ifndef __UNALIGNED_UINT16_READ 103 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 104 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 105 | #endif 106 | #ifndef __UNALIGNED_UINT32_WRITE 107 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 108 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 109 | #endif 110 | #ifndef __UNALIGNED_UINT32_READ 111 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 112 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 113 | #endif 114 | #ifndef __ALIGNED 115 | #define __ALIGNED(x) __attribute__((aligned(x))) 116 | #endif 117 | #ifndef __RESTRICT 118 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 119 | #define __RESTRICT 120 | #endif 121 | 122 | 123 | /* 124 | * TASKING Compiler 125 | */ 126 | #elif defined ( __TASKING__ ) 127 | /* 128 | * The CMSIS functions have been implemented as intrinsics in the compiler. 129 | * Please use "carm -?i" to get an up to date list of all intrinsics, 130 | * Including the CMSIS ones. 131 | */ 132 | 133 | #ifndef __ASM 134 | #define __ASM __asm 135 | #endif 136 | #ifndef __INLINE 137 | #define __INLINE inline 138 | #endif 139 | #ifndef __STATIC_INLINE 140 | #define __STATIC_INLINE static inline 141 | #endif 142 | #ifndef __STATIC_FORCEINLINE 143 | #define __STATIC_FORCEINLINE __STATIC_INLINE 144 | #endif 145 | #ifndef __NO_RETURN 146 | #define __NO_RETURN __attribute__((noreturn)) 147 | #endif 148 | #ifndef __USED 149 | #define __USED __attribute__((used)) 150 | #endif 151 | #ifndef __WEAK 152 | #define __WEAK __attribute__((weak)) 153 | #endif 154 | #ifndef __PACKED 155 | #define __PACKED __packed__ 156 | #endif 157 | #ifndef __PACKED_STRUCT 158 | #define __PACKED_STRUCT struct __packed__ 159 | #endif 160 | #ifndef __PACKED_UNION 161 | #define __PACKED_UNION union __packed__ 162 | #endif 163 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 164 | struct __packed__ T_UINT32 { uint32_t v; }; 165 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 166 | #endif 167 | #ifndef __UNALIGNED_UINT16_WRITE 168 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 169 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 170 | #endif 171 | #ifndef __UNALIGNED_UINT16_READ 172 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 173 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 174 | #endif 175 | #ifndef __UNALIGNED_UINT32_WRITE 176 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 177 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 178 | #endif 179 | #ifndef __UNALIGNED_UINT32_READ 180 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 181 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 182 | #endif 183 | #ifndef __ALIGNED 184 | #define __ALIGNED(x) __align(x) 185 | #endif 186 | #ifndef __RESTRICT 187 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 188 | #define __RESTRICT 189 | #endif 190 | 191 | 192 | /* 193 | * COSMIC Compiler 194 | */ 195 | #elif defined ( __CSMC__ ) 196 | #include 197 | 198 | #ifndef __ASM 199 | #define __ASM _asm 200 | #endif 201 | #ifndef __INLINE 202 | #define __INLINE inline 203 | #endif 204 | #ifndef __STATIC_INLINE 205 | #define __STATIC_INLINE static inline 206 | #endif 207 | #ifndef __STATIC_FORCEINLINE 208 | #define __STATIC_FORCEINLINE __STATIC_INLINE 209 | #endif 210 | #ifndef __NO_RETURN 211 | // NO RETURN is automatically detected hence no warning here 212 | #define __NO_RETURN 213 | #endif 214 | #ifndef __USED 215 | #warning No compiler specific solution for __USED. __USED is ignored. 216 | #define __USED 217 | #endif 218 | #ifndef __WEAK 219 | #define __WEAK __weak 220 | #endif 221 | #ifndef __PACKED 222 | #define __PACKED @packed 223 | #endif 224 | #ifndef __PACKED_STRUCT 225 | #define __PACKED_STRUCT @packed struct 226 | #endif 227 | #ifndef __PACKED_UNION 228 | #define __PACKED_UNION @packed union 229 | #endif 230 | #ifndef __UNALIGNED_UINT32 /* deprecated */ 231 | @packed struct T_UINT32 { uint32_t v; }; 232 | #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) 233 | #endif 234 | #ifndef __UNALIGNED_UINT16_WRITE 235 | __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; 236 | #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) 237 | #endif 238 | #ifndef __UNALIGNED_UINT16_READ 239 | __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; 240 | #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) 241 | #endif 242 | #ifndef __UNALIGNED_UINT32_WRITE 243 | __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; 244 | #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) 245 | #endif 246 | #ifndef __UNALIGNED_UINT32_READ 247 | __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; 248 | #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) 249 | #endif 250 | #ifndef __ALIGNED 251 | #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. 252 | #define __ALIGNED(x) 253 | #endif 254 | #ifndef __RESTRICT 255 | #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. 256 | #define __RESTRICT 257 | #endif 258 | 259 | 260 | #else 261 | #error Unknown compiler. 262 | #endif 263 | 264 | 265 | #endif /* __CMSIS_COMPILER_H */ 266 | 267 | -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Include/cmsis_version.h: -------------------------------------------------------------------------------- 1 | /**************************************************************************//** 2 | * @file cmsis_version.h 3 | * @brief CMSIS Core(M) Version definitions 4 | * @version V5.0.2 5 | * @date 19. April 2017 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef __CMSIS_VERSION_H 32 | #define __CMSIS_VERSION_H 33 | 34 | /* CMSIS Version definitions */ 35 | #define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ 36 | #define __CM_CMSIS_VERSION_SUB ( 1U) /*!< [15:0] CMSIS Core(M) sub version */ 37 | #define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ 38 | __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ 39 | #endif 40 | -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Include/mpu_armv7.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv7.h 3 | * @brief CMSIS MPU API for Armv7-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV7_H 32 | #define ARM_MPU_ARMV7_H 33 | 34 | #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes 35 | #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes 36 | #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes 37 | #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes 38 | #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes 39 | #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte 40 | #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes 41 | #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes 42 | #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes 43 | #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes 44 | #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes 45 | #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes 46 | #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes 47 | #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes 48 | #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes 49 | #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte 50 | #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes 51 | #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes 52 | #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes 53 | #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes 54 | #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes 55 | #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes 56 | #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes 57 | #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes 58 | #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes 59 | #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte 60 | #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes 61 | #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes 62 | 63 | #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access 64 | #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only 65 | #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only 66 | #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access 67 | #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only 68 | #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access 69 | 70 | /** MPU Region Base Address Register Value 71 | * 72 | * \param Region The region to be configured, number 0 to 15. 73 | * \param BaseAddress The base address for the region. 74 | */ 75 | #define ARM_MPU_RBAR(Region, BaseAddress) \ 76 | (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ 77 | ((Region) & MPU_RBAR_REGION_Msk) | \ 78 | (MPU_RBAR_VALID_Msk)) 79 | 80 | /** 81 | * MPU Memory Access Attributes 82 | * 83 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 84 | * \param IsShareable Region is shareable between multiple bus masters. 85 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 86 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 87 | */ 88 | #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ 89 | ((((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ 90 | (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ 91 | (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ 92 | (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) 93 | 94 | /** 95 | * MPU Region Attribute and Size Register Value 96 | * 97 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 98 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 99 | * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. 100 | * \param SubRegionDisable Sub-region disable field. 101 | * \param Size Region size of the region to be configured, for example 4K, 8K. 102 | */ 103 | #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ 104 | ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ 105 | (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ 106 | (((AccessAttributes) ) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) 107 | 108 | /** 109 | * MPU Region Attribute and Size Register Value 110 | * 111 | * \param DisableExec Instruction access disable bit, 1= disable instruction fetches. 112 | * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. 113 | * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. 114 | * \param IsShareable Region is shareable between multiple bus masters. 115 | * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. 116 | * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. 117 | * \param SubRegionDisable Sub-region disable field. 118 | * \param Size Region size of the region to be configured, for example 4K, 8K. 119 | */ 120 | #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ 121 | ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) 122 | 123 | /** 124 | * MPU Memory Access Attribute for strongly ordered memory. 125 | * - TEX: 000b 126 | * - Shareable 127 | * - Non-cacheable 128 | * - Non-bufferable 129 | */ 130 | #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) 131 | 132 | /** 133 | * MPU Memory Access Attribute for device memory. 134 | * - TEX: 000b (if non-shareable) or 010b (if shareable) 135 | * - Shareable or non-shareable 136 | * - Non-cacheable 137 | * - Bufferable (if shareable) or non-bufferable (if non-shareable) 138 | * 139 | * \param IsShareable Configures the device memory as shareable or non-shareable. 140 | */ 141 | #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) 142 | 143 | /** 144 | * MPU Memory Access Attribute for normal memory. 145 | * - TEX: 1BBb (reflecting outer cacheability rules) 146 | * - Shareable or non-shareable 147 | * - Cacheable or non-cacheable (reflecting inner cacheability rules) 148 | * - Bufferable or non-bufferable (reflecting inner cacheability rules) 149 | * 150 | * \param OuterCp Configures the outer cache policy. 151 | * \param InnerCp Configures the inner cache policy. 152 | * \param IsShareable Configures the memory as shareable or non-shareable. 153 | */ 154 | #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) 155 | 156 | /** 157 | * MPU Memory Access Attribute non-cacheable policy. 158 | */ 159 | #define ARM_MPU_CACHEP_NOCACHE 0U 160 | 161 | /** 162 | * MPU Memory Access Attribute write-back, write and read allocate policy. 163 | */ 164 | #define ARM_MPU_CACHEP_WB_WRA 1U 165 | 166 | /** 167 | * MPU Memory Access Attribute write-through, no write allocate policy. 168 | */ 169 | #define ARM_MPU_CACHEP_WT_NWA 2U 170 | 171 | /** 172 | * MPU Memory Access Attribute write-back, no write allocate policy. 173 | */ 174 | #define ARM_MPU_CACHEP_WB_NWA 3U 175 | 176 | 177 | /** 178 | * Struct for a single MPU Region 179 | */ 180 | typedef struct { 181 | uint32_t RBAR; //!< The region base address register value (RBAR) 182 | uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR 183 | } ARM_MPU_Region_t; 184 | 185 | /** Enable the MPU. 186 | * \param MPU_Control Default access permissions for unconfigured regions. 187 | */ 188 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 189 | { 190 | __DSB(); 191 | __ISB(); 192 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 193 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 194 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 195 | #endif 196 | } 197 | 198 | /** Disable the MPU. 199 | */ 200 | __STATIC_INLINE void ARM_MPU_Disable(void) 201 | { 202 | __DSB(); 203 | __ISB(); 204 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 205 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 206 | #endif 207 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 208 | } 209 | 210 | /** Clear and disable the given MPU region. 211 | * \param rnr Region number to be cleared. 212 | */ 213 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 214 | { 215 | MPU->RNR = rnr; 216 | MPU->RASR = 0U; 217 | } 218 | 219 | /** Configure an MPU region. 220 | * \param rbar Value for RBAR register. 221 | * \param rsar Value for RSAR register. 222 | */ 223 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) 224 | { 225 | MPU->RBAR = rbar; 226 | MPU->RASR = rasr; 227 | } 228 | 229 | /** Configure the given MPU region. 230 | * \param rnr Region number to be configured. 231 | * \param rbar Value for RBAR register. 232 | * \param rsar Value for RSAR register. 233 | */ 234 | __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) 235 | { 236 | MPU->RNR = rnr; 237 | MPU->RBAR = rbar; 238 | MPU->RASR = rasr; 239 | } 240 | 241 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 242 | * \param dst Destination data is copied to. 243 | * \param src Source data is copied from. 244 | * \param len Amount of data words to be copied. 245 | */ 246 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 247 | { 248 | uint32_t i; 249 | for (i = 0U; i < len; ++i) 250 | { 251 | dst[i] = src[i]; 252 | } 253 | } 254 | 255 | /** Load the given number of MPU regions from a table. 256 | * \param table Pointer to the MPU configuration table. 257 | * \param cnt Amount of regions to be configured. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 260 | { 261 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 262 | while (cnt > MPU_TYPE_RALIASES) { 263 | orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); 264 | table += MPU_TYPE_RALIASES; 265 | cnt -= MPU_TYPE_RALIASES; 266 | } 267 | orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); 268 | } 269 | 270 | #endif 271 | -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Include/mpu_armv8.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file mpu_armv8.h 3 | * @brief CMSIS MPU API for Armv8-M MPU 4 | * @version V5.0.4 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef ARM_MPU_ARMV8_H 32 | #define ARM_MPU_ARMV8_H 33 | 34 | /** \brief Attribute for device memory (outer only) */ 35 | #define ARM_MPU_ATTR_DEVICE ( 0U ) 36 | 37 | /** \brief Attribute for non-cacheable, normal memory */ 38 | #define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) 39 | 40 | /** \brief Attribute for normal memory (outer and inner) 41 | * \param NT Non-Transient: Set to 1 for non-transient data. 42 | * \param WB Write-Back: Set to 1 to use write-back update policy. 43 | * \param RA Read Allocation: Set to 1 to use cache allocation on read miss. 44 | * \param WA Write Allocation: Set to 1 to use cache allocation on write miss. 45 | */ 46 | #define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ 47 | (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) 48 | 49 | /** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ 50 | #define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) 51 | 52 | /** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ 53 | #define ARM_MPU_ATTR_DEVICE_nGnRE (1U) 54 | 55 | /** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ 56 | #define ARM_MPU_ATTR_DEVICE_nGRE (2U) 57 | 58 | /** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ 59 | #define ARM_MPU_ATTR_DEVICE_GRE (3U) 60 | 61 | /** \brief Memory Attribute 62 | * \param O Outer memory attributes 63 | * \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes 64 | */ 65 | #define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) 66 | 67 | /** \brief Normal memory non-shareable */ 68 | #define ARM_MPU_SH_NON (0U) 69 | 70 | /** \brief Normal memory outer shareable */ 71 | #define ARM_MPU_SH_OUTER (2U) 72 | 73 | /** \brief Normal memory inner shareable */ 74 | #define ARM_MPU_SH_INNER (3U) 75 | 76 | /** \brief Memory access permissions 77 | * \param RO Read-Only: Set to 1 for read-only memory. 78 | * \param NP Non-Privileged: Set to 1 for non-privileged memory. 79 | */ 80 | #define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) 81 | 82 | /** \brief Region Base Address Register value 83 | * \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. 84 | * \param SH Defines the Shareability domain for this memory region. 85 | * \param RO Read-Only: Set to 1 for a read-only memory region. 86 | * \param NP Non-Privileged: Set to 1 for a non-privileged memory region. 87 | * \oaram XN eXecute Never: Set to 1 for a non-executable memory region. 88 | */ 89 | #define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ 90 | ((BASE & MPU_RBAR_BASE_Msk) | \ 91 | ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ 92 | ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ 93 | ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) 94 | 95 | /** \brief Region Limit Address Register value 96 | * \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. 97 | * \param IDX The attribute index to be associated with this memory region. 98 | */ 99 | #define ARM_MPU_RLAR(LIMIT, IDX) \ 100 | ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ 101 | ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ 102 | (MPU_RLAR_EN_Msk)) 103 | 104 | /** 105 | * Struct for a single MPU Region 106 | */ 107 | typedef struct { 108 | uint32_t RBAR; /*!< Region Base Address Register value */ 109 | uint32_t RLAR; /*!< Region Limit Address Register value */ 110 | } ARM_MPU_Region_t; 111 | 112 | /** Enable the MPU. 113 | * \param MPU_Control Default access permissions for unconfigured regions. 114 | */ 115 | __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) 116 | { 117 | __DSB(); 118 | __ISB(); 119 | MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 120 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 121 | SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 122 | #endif 123 | } 124 | 125 | /** Disable the MPU. 126 | */ 127 | __STATIC_INLINE void ARM_MPU_Disable(void) 128 | { 129 | __DSB(); 130 | __ISB(); 131 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 132 | SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 133 | #endif 134 | MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; 135 | } 136 | 137 | #ifdef MPU_NS 138 | /** Enable the Non-secure MPU. 139 | * \param MPU_Control Default access permissions for unconfigured regions. 140 | */ 141 | __STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) 142 | { 143 | __DSB(); 144 | __ISB(); 145 | MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 146 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 147 | SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 148 | #endif 149 | } 150 | 151 | /** Disable the Non-secure MPU. 152 | */ 153 | __STATIC_INLINE void ARM_MPU_Disable_NS(void) 154 | { 155 | __DSB(); 156 | __ISB(); 157 | #ifdef SCB_SHCSR_MEMFAULTENA_Msk 158 | SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 159 | #endif 160 | MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; 161 | } 162 | #endif 163 | 164 | /** Set the memory attribute encoding to the given MPU. 165 | * \param mpu Pointer to the MPU to be configured. 166 | * \param idx The attribute index to be set [0-7] 167 | * \param attr The attribute value to be set. 168 | */ 169 | __STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) 170 | { 171 | const uint8_t reg = idx / 4U; 172 | const uint32_t pos = ((idx % 4U) * 8U); 173 | const uint32_t mask = 0xFFU << pos; 174 | 175 | if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { 176 | return; // invalid index 177 | } 178 | 179 | mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); 180 | } 181 | 182 | /** Set the memory attribute encoding. 183 | * \param idx The attribute index to be set [0-7] 184 | * \param attr The attribute value to be set. 185 | */ 186 | __STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) 187 | { 188 | ARM_MPU_SetMemAttrEx(MPU, idx, attr); 189 | } 190 | 191 | #ifdef MPU_NS 192 | /** Set the memory attribute encoding to the Non-secure MPU. 193 | * \param idx The attribute index to be set [0-7] 194 | * \param attr The attribute value to be set. 195 | */ 196 | __STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) 197 | { 198 | ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); 199 | } 200 | #endif 201 | 202 | /** Clear and disable the given MPU region of the given MPU. 203 | * \param mpu Pointer to MPU to be used. 204 | * \param rnr Region number to be cleared. 205 | */ 206 | __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) 207 | { 208 | mpu->RNR = rnr; 209 | mpu->RLAR = 0U; 210 | } 211 | 212 | /** Clear and disable the given MPU region. 213 | * \param rnr Region number to be cleared. 214 | */ 215 | __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) 216 | { 217 | ARM_MPU_ClrRegionEx(MPU, rnr); 218 | } 219 | 220 | #ifdef MPU_NS 221 | /** Clear and disable the given Non-secure MPU region. 222 | * \param rnr Region number to be cleared. 223 | */ 224 | __STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) 225 | { 226 | ARM_MPU_ClrRegionEx(MPU_NS, rnr); 227 | } 228 | #endif 229 | 230 | /** Configure the given MPU region of the given MPU. 231 | * \param mpu Pointer to MPU to be used. 232 | * \param rnr Region number to be configured. 233 | * \param rbar Value for RBAR register. 234 | * \param rlar Value for RLAR register. 235 | */ 236 | __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) 237 | { 238 | mpu->RNR = rnr; 239 | mpu->RBAR = rbar; 240 | mpu->RLAR = rlar; 241 | } 242 | 243 | /** Configure the given MPU region. 244 | * \param rnr Region number to be configured. 245 | * \param rbar Value for RBAR register. 246 | * \param rlar Value for RLAR register. 247 | */ 248 | __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) 249 | { 250 | ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); 251 | } 252 | 253 | #ifdef MPU_NS 254 | /** Configure the given Non-secure MPU region. 255 | * \param rnr Region number to be configured. 256 | * \param rbar Value for RBAR register. 257 | * \param rlar Value for RLAR register. 258 | */ 259 | __STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) 260 | { 261 | ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); 262 | } 263 | #endif 264 | 265 | /** Memcopy with strictly ordered memory access, e.g. for register targets. 266 | * \param dst Destination data is copied to. 267 | * \param src Source data is copied from. 268 | * \param len Amount of data words to be copied. 269 | */ 270 | __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) 271 | { 272 | uint32_t i; 273 | for (i = 0U; i < len; ++i) 274 | { 275 | dst[i] = src[i]; 276 | } 277 | } 278 | 279 | /** Load the given number of MPU regions from a table to the given MPU. 280 | * \param mpu Pointer to the MPU registers to be used. 281 | * \param rnr First region number to be configured. 282 | * \param table Pointer to the MPU configuration table. 283 | * \param cnt Amount of regions to be configured. 284 | */ 285 | __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 286 | { 287 | const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; 288 | if (cnt == 1U) { 289 | mpu->RNR = rnr; 290 | orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); 291 | } else { 292 | uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); 293 | uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; 294 | 295 | mpu->RNR = rnrBase; 296 | while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { 297 | uint32_t c = MPU_TYPE_RALIASES - rnrOffset; 298 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); 299 | table += c; 300 | cnt -= c; 301 | rnrOffset = 0U; 302 | rnrBase += MPU_TYPE_RALIASES; 303 | mpu->RNR = rnrBase; 304 | } 305 | 306 | orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); 307 | } 308 | } 309 | 310 | /** Load the given number of MPU regions from a table. 311 | * \param rnr First region number to be configured. 312 | * \param table Pointer to the MPU configuration table. 313 | * \param cnt Amount of regions to be configured. 314 | */ 315 | __STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 316 | { 317 | ARM_MPU_LoadEx(MPU, rnr, table, cnt); 318 | } 319 | 320 | #ifdef MPU_NS 321 | /** Load the given number of MPU regions from a table to the Non-secure MPU. 322 | * \param rnr First region number to be configured. 323 | * \param table Pointer to the MPU configuration table. 324 | * \param cnt Amount of regions to be configured. 325 | */ 326 | __STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 327 | { 328 | ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); 329 | } 330 | #endif 331 | 332 | #endif 333 | 334 | -------------------------------------------------------------------------------- /Software/Drivers/CMSIS/Include/tz_context.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | * @file tz_context.h 3 | * @brief Context Management for Armv8-M TrustZone 4 | * @version V1.0.1 5 | * @date 10. January 2018 6 | ******************************************************************************/ 7 | /* 8 | * Copyright (c) 2017-2018 Arm Limited. All rights reserved. 9 | * 10 | * SPDX-License-Identifier: Apache-2.0 11 | * 12 | * Licensed under the Apache License, Version 2.0 (the License); you may 13 | * not use this file except in compliance with the License. 14 | * You may obtain a copy of the License at 15 | * 16 | * www.apache.org/licenses/LICENSE-2.0 17 | * 18 | * Unless required by applicable law or agreed to in writing, software 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 | * See the License for the specific language governing permissions and 22 | * limitations under the License. 23 | */ 24 | 25 | #if defined ( __ICCARM__ ) 26 | #pragma system_include /* treat file as system include file for MISRA check */ 27 | #elif defined (__clang__) 28 | #pragma clang system_header /* treat file as system include file */ 29 | #endif 30 | 31 | #ifndef TZ_CONTEXT_H 32 | #define TZ_CONTEXT_H 33 | 34 | #include 35 | 36 | #ifndef TZ_MODULEID_T 37 | #define TZ_MODULEID_T 38 | /// \details Data type that identifies secure software modules called by a process. 39 | typedef uint32_t TZ_ModuleId_t; 40 | #endif 41 | 42 | /// \details TZ Memory ID identifies an allocated memory slot. 43 | typedef uint32_t TZ_MemoryId_t; 44 | 45 | /// Initialize secure context memory system 46 | /// \return execution status (1: success, 0: error) 47 | uint32_t TZ_InitContextSystem_S (void); 48 | 49 | /// Allocate context memory for calling secure software modules in TrustZone 50 | /// \param[in] module identifies software modules called from non-secure mode 51 | /// \return value != 0 id TrustZone memory slot identifier 52 | /// \return value 0 no memory available or internal error 53 | TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); 54 | 55 | /// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S 56 | /// \param[in] id TrustZone memory slot identifier 57 | /// \return execution status (1: success, 0: error) 58 | uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); 59 | 60 | /// Load secure context (called on RTOS thread context switch) 61 | /// \param[in] id TrustZone memory slot identifier 62 | /// \return execution status (1: success, 0: error) 63 | uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); 64 | 65 | /// Store secure context (called on RTOS thread context switch) 66 | /// \param[in] id TrustZone memory slot identifier 67 | /// \return execution status (1: success, 0: error) 68 | uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); 69 | 70 | #endif // TZ_CONTEXT_H 71 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_cortex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_cortex.h 4 | * @author MCD Application Team 5 | * @brief Header file of CORTEX HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F0xx_HAL_CORTEX_H 22 | #define __STM32F0xx_HAL_CORTEX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f0xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F0xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup CORTEX CORTEX 36 | * @{ 37 | */ 38 | /* Exported types ------------------------------------------------------------*/ 39 | /* Exported constants --------------------------------------------------------*/ 40 | 41 | /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 42 | * @{ 43 | */ 44 | 45 | /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 46 | * @{ 47 | */ 48 | #define SYSTICK_CLKSOURCE_HCLK_DIV8 (0x00000000U) 49 | #define SYSTICK_CLKSOURCE_HCLK (0x00000004U) 50 | 51 | /** 52 | * @} 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /* Exported Macros -----------------------------------------------------------*/ 60 | 61 | /* Exported functions --------------------------------------------------------*/ 62 | /** @addtogroup CORTEX_Exported_Functions CORTEX Exported Functions 63 | * @{ 64 | */ 65 | /** @addtogroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 66 | * @brief Initialization and Configuration functions 67 | * @{ 68 | */ 69 | /* Initialization and de-initialization functions *******************************/ 70 | void HAL_NVIC_SetPriority(IRQn_Type IRQn,uint32_t PreemptPriority, uint32_t SubPriority); 71 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 72 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 73 | void HAL_NVIC_SystemReset(void); 74 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @addtogroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 80 | * @brief Cortex control functions 81 | * @{ 82 | */ 83 | 84 | /* Peripheral Control functions *************************************************/ 85 | uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn); 86 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 87 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 88 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 89 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 90 | void HAL_SYSTICK_IRQHandler(void); 91 | void HAL_SYSTICK_Callback(void); 92 | /** 93 | * @} 94 | */ 95 | 96 | /** 97 | * @} 98 | */ 99 | 100 | /* Private types -------------------------------------------------------------*/ 101 | /* Private variables ---------------------------------------------------------*/ 102 | /* Private constants ---------------------------------------------------------*/ 103 | /* Private macros ------------------------------------------------------------*/ 104 | /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 105 | * @{ 106 | */ 107 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x4) 108 | 109 | #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 110 | 111 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 112 | ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 113 | /** 114 | * @} 115 | */ 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** 122 | * @} 123 | */ 124 | 125 | #ifdef __cplusplus 126 | } 127 | #endif 128 | 129 | #endif /* __STM32F0xx_HAL_CORTEX_H */ 130 | 131 | 132 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 133 | 134 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_def.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_def.h 4 | * @author MCD Application Team 5 | * @brief This file contains HAL common defines, enumeration, macros and 6 | * structures definitions. 7 | ****************************************************************************** 8 | * @attention 9 | * 10 | *

© Copyright (c) 2016 STMicroelectronics. 11 | * All rights reserved.

12 | * 13 | * This software component is licensed by ST under BSD 3-Clause license, 14 | * the "License"; You may not use this file except in compliance with the 15 | * License. You may obtain a copy of the License at: 16 | * opensource.org/licenses/BSD-3-Clause 17 | * 18 | ****************************************************************************** 19 | */ 20 | 21 | /* Define to prevent recursive inclusion -------------------------------------*/ 22 | #ifndef __STM32F0xx_HAL_DEF 23 | #define __STM32F0xx_HAL_DEF 24 | 25 | #ifdef __cplusplus 26 | extern "C" { 27 | #endif 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f0xx.h" 31 | #include "Legacy/stm32_hal_legacy.h" 32 | #include 33 | 34 | /* Exported types ------------------------------------------------------------*/ 35 | 36 | /** 37 | * @brief HAL Status structures definition 38 | */ 39 | typedef enum 40 | { 41 | HAL_OK = 0x00U, 42 | HAL_ERROR = 0x01U, 43 | HAL_BUSY = 0x02U, 44 | HAL_TIMEOUT = 0x03U 45 | } HAL_StatusTypeDef; 46 | 47 | /** 48 | * @brief HAL Lock structures definition 49 | */ 50 | typedef enum 51 | { 52 | HAL_UNLOCKED = 0x00U, 53 | HAL_LOCKED = 0x01U 54 | } HAL_LockTypeDef; 55 | 56 | /* Exported macro ------------------------------------------------------------*/ 57 | 58 | #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ 59 | 60 | #define HAL_MAX_DELAY 0xFFFFFFFFU 61 | 62 | #define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) 63 | #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) 64 | 65 | #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ 66 | do{ \ 67 | (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ 68 | (__DMA_HANDLE__).Parent = (__HANDLE__); \ 69 | } while(0U) 70 | 71 | /** @brief Reset the Handle's State field. 72 | * @param __HANDLE__ specifies the Peripheral Handle. 73 | * @note This macro can be used for the following purpose: 74 | * - When the Handle is declared as local variable; before passing it as parameter 75 | * to HAL_PPP_Init() for the first time, it is mandatory to use this macro 76 | * to set to 0 the Handle's "State" field. 77 | * Otherwise, "State" field may have any random value and the first time the function 78 | * HAL_PPP_Init() is called, the low level hardware initialization will be missed 79 | * (i.e. HAL_PPP_MspInit() will not be executed). 80 | * - When there is a need to reconfigure the low level hardware: instead of calling 81 | * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). 82 | * In this later function, when the Handle's "State" field is set to 0, it will execute the function 83 | * HAL_PPP_MspInit() which will reconfigure the low level hardware. 84 | * @retval None 85 | */ 86 | #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U) 87 | 88 | #if (USE_RTOS == 1U) 89 | /* Reserved for future use */ 90 | #error " USE_RTOS should be 0 in the current HAL release " 91 | #else 92 | #define __HAL_LOCK(__HANDLE__) \ 93 | do{ \ 94 | if((__HANDLE__)->Lock == HAL_LOCKED) \ 95 | { \ 96 | return HAL_BUSY; \ 97 | } \ 98 | else \ 99 | { \ 100 | (__HANDLE__)->Lock = HAL_LOCKED; \ 101 | } \ 102 | }while (0U) 103 | 104 | #define __HAL_UNLOCK(__HANDLE__) \ 105 | do{ \ 106 | (__HANDLE__)->Lock = HAL_UNLOCKED; \ 107 | }while (0U) 108 | #endif /* USE_RTOS */ 109 | 110 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 111 | #ifndef __weak 112 | #define __weak __attribute__((weak)) 113 | #endif 114 | #ifndef __packed 115 | #define __packed __attribute__((packed)) 116 | #endif 117 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 118 | #ifndef __weak 119 | #define __weak __attribute__((weak)) 120 | #endif /* __weak */ 121 | #ifndef __packed 122 | #define __packed __attribute__((__packed__)) 123 | #endif /* __packed */ 124 | #endif /* __GNUC__ */ 125 | 126 | 127 | /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ 128 | #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ 129 | #ifndef __ALIGN_BEGIN 130 | #define __ALIGN_BEGIN 131 | #endif 132 | #ifndef __ALIGN_END 133 | #define __ALIGN_END __attribute__ ((aligned (4))) 134 | #endif 135 | #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ 136 | #ifndef __ALIGN_END 137 | #define __ALIGN_END __attribute__ ((aligned (4))) 138 | #endif /* __ALIGN_END */ 139 | #ifndef __ALIGN_BEGIN 140 | #define __ALIGN_BEGIN 141 | #endif /* __ALIGN_BEGIN */ 142 | #else 143 | #ifndef __ALIGN_END 144 | #define __ALIGN_END 145 | #endif /* __ALIGN_END */ 146 | #ifndef __ALIGN_BEGIN 147 | #if defined (__CC_ARM) /* ARM Compiler V5*/ 148 | #define __ALIGN_BEGIN __align(4) 149 | #elif defined (__ICCARM__) /* IAR Compiler */ 150 | #define __ALIGN_BEGIN 151 | #endif /* __CC_ARM */ 152 | #endif /* __ALIGN_BEGIN */ 153 | #endif /* __GNUC__ */ 154 | 155 | /** 156 | * @brief __NOINLINE definition 157 | */ 158 | #if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) 159 | /* ARM V4/V5 and V6 & GNU Compiler 160 | ------------------------------- 161 | */ 162 | #define __NOINLINE __attribute__ ( (noinline) ) 163 | 164 | #elif defined ( __ICCARM__ ) 165 | /* ICCARM Compiler 166 | --------------- 167 | */ 168 | #define __NOINLINE _Pragma("optimize = no_inline") 169 | 170 | #endif 171 | 172 | #ifdef __cplusplus 173 | } 174 | #endif 175 | 176 | #endif /* ___STM32F0xx_HAL_DEF */ 177 | 178 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 179 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_flash.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_flash.h 4 | * @author MCD Application Team 5 | * @brief Header file of Flash HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F0xx_HAL_FLASH_H 22 | #define __STM32F0xx_HAL_FLASH_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f0xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F0xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup FLASH 36 | * @{ 37 | */ 38 | 39 | /** @addtogroup FLASH_Private_Constants 40 | * @{ 41 | */ 42 | #define FLASH_TIMEOUT_VALUE (50000U) /* 50 s */ 43 | /** 44 | * @} 45 | */ 46 | 47 | /** @addtogroup FLASH_Private_Macros 48 | * @{ 49 | */ 50 | 51 | #define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_HALFWORD) || \ 52 | ((VALUE) == FLASH_TYPEPROGRAM_WORD) || \ 53 | ((VALUE) == FLASH_TYPEPROGRAM_DOUBLEWORD)) 54 | 55 | #define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \ 56 | ((__LATENCY__) == FLASH_LATENCY_1)) 57 | 58 | /** 59 | * @} 60 | */ 61 | 62 | /* Exported types ------------------------------------------------------------*/ 63 | /** @defgroup FLASH_Exported_Types FLASH Exported Types 64 | * @{ 65 | */ 66 | 67 | /** 68 | * @brief FLASH Procedure structure definition 69 | */ 70 | typedef enum 71 | { 72 | FLASH_PROC_NONE = 0U, 73 | FLASH_PROC_PAGEERASE = 1U, 74 | FLASH_PROC_MASSERASE = 2U, 75 | FLASH_PROC_PROGRAMHALFWORD = 3U, 76 | FLASH_PROC_PROGRAMWORD = 4U, 77 | FLASH_PROC_PROGRAMDOUBLEWORD = 5U 78 | } FLASH_ProcedureTypeDef; 79 | 80 | /** 81 | * @brief FLASH handle Structure definition 82 | */ 83 | typedef struct 84 | { 85 | __IO FLASH_ProcedureTypeDef ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not in IT context */ 86 | 87 | __IO uint32_t DataRemaining; /*!< Internal variable to save the remaining pages to erase or half-word to program in IT context */ 88 | 89 | __IO uint32_t Address; /*!< Internal variable to save address selected for program or erase */ 90 | 91 | __IO uint64_t Data; /*!< Internal variable to save data to be programmed */ 92 | 93 | HAL_LockTypeDef Lock; /*!< FLASH locking object */ 94 | 95 | __IO uint32_t ErrorCode; /*!< FLASH error code 96 | This parameter can be a value of @ref FLASH_Error_Codes */ 97 | } FLASH_ProcessTypeDef; 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /* Exported constants --------------------------------------------------------*/ 104 | /** @defgroup FLASH_Exported_Constants FLASH Exported Constants 105 | * @{ 106 | */ 107 | 108 | /** @defgroup FLASH_Error_Codes FLASH Error Codes 109 | * @{ 110 | */ 111 | 112 | #define HAL_FLASH_ERROR_NONE 0x00U /*!< No error */ 113 | #define HAL_FLASH_ERROR_PROG 0x01U /*!< Programming error */ 114 | #define HAL_FLASH_ERROR_WRP 0x02U /*!< Write protection error */ 115 | 116 | /** 117 | * @} 118 | */ 119 | 120 | /** @defgroup FLASH_Type_Program FLASH Type Program 121 | * @{ 122 | */ 123 | #define FLASH_TYPEPROGRAM_HALFWORD (0x01U) /*!ACR = (FLASH->ACR&(~FLASH_ACR_LATENCY)) | (__LATENCY__)) 186 | 187 | 188 | /** 189 | * @brief Get the FLASH Latency. 190 | * @retval FLASH Latency 191 | * The value of this parameter depend on device used within the same series 192 | */ 193 | #define __HAL_FLASH_GET_LATENCY() (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)) 194 | 195 | /** 196 | * @} 197 | */ 198 | 199 | /** @defgroup FLASH_Prefetch FLASH Prefetch 200 | * @brief macros to handle FLASH Prefetch buffer 201 | * @{ 202 | */ 203 | /** 204 | * @brief Enable the FLASH prefetch buffer. 205 | * @retval None 206 | */ 207 | #define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() (FLASH->ACR |= FLASH_ACR_PRFTBE) 208 | 209 | /** 210 | * @brief Disable the FLASH prefetch buffer. 211 | * @retval None 212 | */ 213 | #define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() (FLASH->ACR &= (~FLASH_ACR_PRFTBE)) 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /** @defgroup FLASH_Interrupt FLASH Interrupts 220 | * @brief macros to handle FLASH interrupts 221 | * @{ 222 | */ 223 | 224 | /** 225 | * @brief Enable the specified FLASH interrupt. 226 | * @param __INTERRUPT__ FLASH interrupt 227 | * This parameter can be any combination of the following values: 228 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 229 | * @arg @ref FLASH_IT_ERR Error Interrupt 230 | * @retval none 231 | */ 232 | #define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) SET_BIT((FLASH->CR), (__INTERRUPT__)) 233 | 234 | /** 235 | * @brief Disable the specified FLASH interrupt. 236 | * @param __INTERRUPT__ FLASH interrupt 237 | * This parameter can be any combination of the following values: 238 | * @arg @ref FLASH_IT_EOP End of FLASH Operation Interrupt 239 | * @arg @ref FLASH_IT_ERR Error Interrupt 240 | * @retval none 241 | */ 242 | #define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) CLEAR_BIT((FLASH->CR), (uint32_t)(__INTERRUPT__)) 243 | 244 | /** 245 | * @brief Get the specified FLASH flag status. 246 | * @param __FLAG__ specifies the FLASH flag to check. 247 | * This parameter can be one of the following values: 248 | * @arg @ref FLASH_FLAG_BSY FLASH Busy flag 249 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 250 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 251 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag 252 | * @retval The new state of __FLAG__ (SET or RESET). 253 | */ 254 | #define __HAL_FLASH_GET_FLAG(__FLAG__) (((FLASH->SR) & (__FLAG__)) == (__FLAG__)) 255 | 256 | /** 257 | * @brief Clear the specified FLASH flag. 258 | * @param __FLAG__ specifies the FLASH flags to clear. 259 | * This parameter can be any combination of the following values: 260 | * @arg @ref FLASH_FLAG_EOP FLASH End of Operation flag 261 | * @arg @ref FLASH_FLAG_WRPERR FLASH Write protected error flag 262 | * @arg @ref FLASH_FLAG_PGERR FLASH Programming error flag 263 | * @retval none 264 | */ 265 | #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) ((FLASH->SR) = (__FLAG__)) 266 | 267 | /** 268 | * @} 269 | */ 270 | 271 | /** 272 | * @} 273 | */ 274 | 275 | /* Include FLASH HAL Extended module */ 276 | #include "stm32f0xx_hal_flash_ex.h" 277 | 278 | /* Exported functions --------------------------------------------------------*/ 279 | /** @addtogroup FLASH_Exported_Functions 280 | * @{ 281 | */ 282 | 283 | /** @addtogroup FLASH_Exported_Functions_Group1 284 | * @{ 285 | */ 286 | /* IO operation functions *****************************************************/ 287 | HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 288 | HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data); 289 | 290 | /* FLASH IRQ handler function */ 291 | void HAL_FLASH_IRQHandler(void); 292 | /* Callbacks in non blocking modes */ 293 | void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); 294 | void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /** @addtogroup FLASH_Exported_Functions_Group2 301 | * @{ 302 | */ 303 | /* Peripheral Control functions ***********************************************/ 304 | HAL_StatusTypeDef HAL_FLASH_Unlock(void); 305 | HAL_StatusTypeDef HAL_FLASH_Lock(void); 306 | HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); 307 | HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); 308 | HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); 309 | 310 | /** 311 | * @} 312 | */ 313 | 314 | /** @addtogroup FLASH_Exported_Functions_Group3 315 | * @{ 316 | */ 317 | /* Peripheral State and Error functions ***************************************/ 318 | uint32_t HAL_FLASH_GetError(void); 319 | 320 | /** 321 | * @} 322 | */ 323 | 324 | /** 325 | * @} 326 | */ 327 | 328 | /* Private function -------------------------------------------------*/ 329 | /** @addtogroup FLASH_Private_Functions 330 | * @{ 331 | */ 332 | HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); 333 | 334 | /** 335 | * @} 336 | */ 337 | 338 | /** 339 | * @} 340 | */ 341 | 342 | /** 343 | * @} 344 | */ 345 | 346 | #ifdef __cplusplus 347 | } 348 | #endif 349 | 350 | #endif /* __STM32F0xx_HAL_FLASH_H */ 351 | 352 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 353 | 354 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_i2c_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_i2c_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of I2C HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32F0xx_HAL_I2C_EX_H 22 | #define STM32F0xx_HAL_I2C_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f0xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F0xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup I2CEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | 42 | /** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants 43 | * @{ 44 | */ 45 | 46 | /** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter 47 | * @{ 48 | */ 49 | #define I2C_ANALOGFILTER_ENABLE 0x00000000U 50 | #define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 51 | /** 52 | * @} 53 | */ 54 | 55 | /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus 56 | * @{ 57 | */ 58 | #define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */ 59 | #if defined(SYSCFG_CFGR1_I2C_FMP_PA9) 60 | #define I2C_FASTMODEPLUS_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /*!< Enable Fast Mode Plus on PA9 */ 61 | #define I2C_FASTMODEPLUS_PA10 SYSCFG_CFGR1_I2C_FMP_PA10 /*!< Enable Fast Mode Plus on PA10 */ 62 | #else 63 | #define I2C_FASTMODEPLUS_PA9 (uint32_t)(0x00000001U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA9 not supported */ 64 | #define I2C_FASTMODEPLUS_PA10 (uint32_t)(0x00000002U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus PA10 not supported */ 65 | #endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */ 66 | #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /*!< Enable Fast Mode Plus on PB6 */ 67 | #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /*!< Enable Fast Mode Plus on PB7 */ 68 | #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /*!< Enable Fast Mode Plus on PB8 */ 69 | #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /*!< Enable Fast Mode Plus on PB9 */ 70 | #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) 71 | #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /*!< Enable Fast Mode Plus on I2C1 pins */ 72 | #else 73 | #define I2C_FASTMODEPLUS_I2C1 (uint32_t)(0x00000100U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C1 not supported */ 74 | #endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */ 75 | #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) 76 | #define I2C_FASTMODEPLUS_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /*!< Enable Fast Mode Plus on I2C2 pins */ 77 | #else 78 | #define I2C_FASTMODEPLUS_I2C2 (uint32_t)(0x00000200U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C2 not supported */ 79 | #endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */ 80 | /** 81 | * @} 82 | */ 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | /* Exported macro ------------------------------------------------------------*/ 89 | /* Exported functions --------------------------------------------------------*/ 90 | 91 | /** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions 92 | * @{ 93 | */ 94 | 95 | /** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions 96 | * @brief Extended features functions 97 | * @{ 98 | */ 99 | 100 | /** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions 101 | * @{ 102 | */ 103 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, 104 | uint32_t AnalogFilter); 105 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, 106 | uint32_t DigitalFilter); 107 | /** 108 | * @} 109 | */ 110 | #if defined(I2C_CR1_WUPEN) 111 | 112 | /** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions 113 | * @{ 114 | */ 115 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); 116 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); 117 | /** 118 | * @} 119 | */ 120 | #endif /* I2C_CR1_WUPEN */ 121 | 122 | /** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions 123 | * @{ 124 | */ 125 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus); 126 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus); 127 | /** 128 | * @} 129 | */ 130 | 131 | /* Private constants ---------------------------------------------------------*/ 132 | /** @defgroup I2CEx_Private_Constants I2C Extended Private Constants 133 | * @{ 134 | */ 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /* Private macros ------------------------------------------------------------*/ 141 | /** @defgroup I2CEx_Private_Macro I2C Extended Private Macros 142 | * @{ 143 | */ 144 | #define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ 145 | ((FILTER) == I2C_ANALOGFILTER_DISABLE)) 146 | 147 | #define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 148 | 149 | #define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FMP_NOT_SUPPORTED) != I2C_FMP_NOT_SUPPORTED) && \ 150 | ((((__CONFIG__) & (I2C_FASTMODEPLUS_PA9)) == I2C_FASTMODEPLUS_PA9) || \ 151 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PA10)) == I2C_FASTMODEPLUS_PA10) || \ 152 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB6)) == I2C_FASTMODEPLUS_PB6) || \ 153 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB7)) == I2C_FASTMODEPLUS_PB7) || \ 154 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB8)) == I2C_FASTMODEPLUS_PB8) || \ 155 | (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ 156 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ 157 | (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C2)) == I2C_FASTMODEPLUS_I2C2))) 158 | /** 159 | * @} 160 | */ 161 | 162 | /* Private Functions ---------------------------------------------------------*/ 163 | /** @defgroup I2CEx_Private_Functions I2C Extended Private Functions 164 | * @{ 165 | */ 166 | /* Private functions are defined in stm32f0xx_hal_i2c_ex.c file */ 167 | /** 168 | * @} 169 | */ 170 | 171 | /** 172 | * @} 173 | */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** 184 | * @} 185 | */ 186 | 187 | #ifdef __cplusplus 188 | } 189 | #endif 190 | 191 | #endif /* STM32F0xx_HAL_I2C_EX_H */ 192 | 193 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 194 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_pwr.h 4 | * @author MCD Application Team 5 | * @brief Header file of PWR HAL module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef __STM32F0xx_HAL_PWR_H 22 | #define __STM32F0xx_HAL_PWR_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f0xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F0xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup PWR PWR 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | 42 | /** @defgroup PWR_Exported_Constants PWR Exported Constants 43 | * @{ 44 | */ 45 | 46 | /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in STOP mode 47 | * @{ 48 | */ 49 | #define PWR_MAINREGULATOR_ON (0x00000000U) 50 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS 51 | 52 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ 53 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry 59 | * @{ 60 | */ 61 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U) 62 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U) 63 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry 69 | * @{ 70 | */ 71 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01U) 72 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02U) 73 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) 74 | /** 75 | * @} 76 | */ 77 | 78 | 79 | /** 80 | * @} 81 | */ 82 | 83 | /* Exported macro ------------------------------------------------------------*/ 84 | /** @defgroup PWR_Exported_Macro PWR Exported Macro 85 | * @{ 86 | */ 87 | 88 | /** @brief Check PWR flag is set or not. 89 | * @param __FLAG__ specifies the flag to check. 90 | * This parameter can be one of the following values: 91 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 92 | * was received from the WKUP pin or from the RTC alarm (Alarm A), 93 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. 94 | * An additional wakeup event is detected if the WKUP pin is enabled 95 | * (by setting the EWUP bit) when the WKUP pin level is already high. 96 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was 97 | * resumed from StandBy mode. 98 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 99 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode 100 | * For this reason, this bit is equal to 0 after Standby or reset 101 | * until the PVDE bit is set. 102 | * Warning: this Flag is not available on STM32F030x8 products 103 | * @arg PWR_FLAG_VREFINTRDY: This flag indicates that the internal reference 104 | * voltage VREFINT is ready. 105 | * Warning: this Flag is not available on STM32F030x8 products 106 | * @retval The new state of __FLAG__ (TRUE or FALSE). 107 | */ 108 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) 109 | 110 | /** @brief Clear the PWR's pending flags. 111 | * @param __FLAG__ specifies the flag to clear. 112 | * This parameter can be one of the following values: 113 | * @arg PWR_FLAG_WU: Wake Up flag 114 | * @arg PWR_FLAG_SB: StandBy flag 115 | */ 116 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2U) 117 | 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /* Include PWR HAL Extension module */ 124 | #include "stm32f0xx_hal_pwr_ex.h" 125 | 126 | /* Exported functions --------------------------------------------------------*/ 127 | 128 | /** @addtogroup PWR_Exported_Functions PWR Exported Functions 129 | * @{ 130 | */ 131 | 132 | /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 133 | * @{ 134 | */ 135 | 136 | /* Initialization and de-initialization functions *****************************/ 137 | void HAL_PWR_DeInit(void); 138 | 139 | /** 140 | * @} 141 | */ 142 | 143 | /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 144 | * @{ 145 | */ 146 | 147 | /* Peripheral Control functions **********************************************/ 148 | void HAL_PWR_EnableBkUpAccess(void); 149 | void HAL_PWR_DisableBkUpAccess(void); 150 | 151 | /* WakeUp pins configuration functions ****************************************/ 152 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); 153 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); 154 | 155 | /* Low Power modes configuration functions ************************************/ 156 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); 157 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); 158 | void HAL_PWR_EnterSTANDBYMode(void); 159 | 160 | void HAL_PWR_EnableSleepOnExit(void); 161 | void HAL_PWR_DisableSleepOnExit(void); 162 | void HAL_PWR_EnableSEVOnPend(void); 163 | void HAL_PWR_DisableSEVOnPend(void); 164 | 165 | /** 166 | * @} 167 | */ 168 | 169 | /** 170 | * @} 171 | */ 172 | 173 | /** 174 | * @} 175 | */ 176 | 177 | /** 178 | * @} 179 | */ 180 | 181 | #ifdef __cplusplus 182 | } 183 | #endif 184 | 185 | 186 | #endif /* __STM32F0xx_HAL_PWR_H */ 187 | 188 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 189 | 190 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_hal_tim_ex.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_tim_ex.h 4 | * @author MCD Application Team 5 | * @brief Header file of TIM HAL Extended module. 6 | ****************************************************************************** 7 | * @attention 8 | * 9 | *

© Copyright (c) 2016 STMicroelectronics. 10 | * All rights reserved.

11 | * 12 | * This software component is licensed by ST under BSD 3-Clause license, 13 | * the "License"; You may not use this file except in compliance with the 14 | * License. You may obtain a copy of the License at: 15 | * opensource.org/licenses/BSD-3-Clause 16 | * 17 | ****************************************************************************** 18 | */ 19 | 20 | /* Define to prevent recursive inclusion -------------------------------------*/ 21 | #ifndef STM32F0xx_HAL_TIM_EX_H 22 | #define STM32F0xx_HAL_TIM_EX_H 23 | 24 | #ifdef __cplusplus 25 | extern "C" { 26 | #endif 27 | 28 | /* Includes ------------------------------------------------------------------*/ 29 | #include "stm32f0xx_hal_def.h" 30 | 31 | /** @addtogroup STM32F0xx_HAL_Driver 32 | * @{ 33 | */ 34 | 35 | /** @addtogroup TIMEx 36 | * @{ 37 | */ 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /** @defgroup TIMEx_Exported_Types TIM Extended Exported Types 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @brief TIM Hall sensor Configuration Structure definition 46 | */ 47 | 48 | typedef struct 49 | { 50 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. 51 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ 52 | 53 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. 54 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ 55 | 56 | uint32_t IC1Filter; /*!< Specifies the input capture filter. 57 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ 58 | 59 | uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 60 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ 61 | } TIM_HallSensor_InitTypeDef; 62 | /** 63 | * @} 64 | */ 65 | /* End of exported types -----------------------------------------------------*/ 66 | 67 | /* Exported constants --------------------------------------------------------*/ 68 | /** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants 69 | * @{ 70 | */ 71 | 72 | /** @defgroup TIMEx_Remap TIM Extended Remapping 73 | * @{ 74 | */ 75 | #define TIM_TIM14_GPIO (0x00000000U) /*!< TIM14 TI1 is connected to GPIO */ 76 | #define TIM_TIM14_RTC (0x00000001U) /*!< TIM14 TI1 is connected to RTC_clock */ 77 | #define TIM_TIM14_HSE (0x00000002U) /*!< TIM14 TI1 is connected to HSE/32U */ 78 | #define TIM_TIM14_MCO (0x00000003U) /*!< TIM14 TI1 is connected to MCO */ 79 | /** 80 | * @} 81 | */ 82 | 83 | /** 84 | * @} 85 | */ 86 | /* End of exported constants -------------------------------------------------*/ 87 | 88 | /* Exported macro ------------------------------------------------------------*/ 89 | /** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros 90 | * @{ 91 | */ 92 | 93 | /** 94 | * @} 95 | */ 96 | /* End of exported macro -----------------------------------------------------*/ 97 | 98 | /* Private macro -------------------------------------------------------------*/ 99 | /** @defgroup TIMEx_Private_Macros TIM Extended Private Macros 100 | * @{ 101 | */ 102 | #define IS_TIM_REMAP(__INSTANCE__, __REMAP__) \ 103 | (((__INSTANCE__) == TIM14) && (((__REMAP__) & 0xFFFFFFFCU) == 0x00000000U)) 104 | 105 | /** 106 | * @} 107 | */ 108 | /* End of private macro ------------------------------------------------------*/ 109 | 110 | /* Exported functions --------------------------------------------------------*/ 111 | /** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions 112 | * @{ 113 | */ 114 | 115 | /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions 116 | * @brief Timer Hall Sensor functions 117 | * @{ 118 | */ 119 | /* Timer Hall Sensor functions **********************************************/ 120 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); 121 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); 122 | 123 | void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); 124 | void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); 125 | 126 | /* Blocking mode: Polling */ 127 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); 128 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); 129 | /* Non-Blocking mode: Interrupt */ 130 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); 131 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); 132 | /* Non-Blocking mode: DMA */ 133 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); 134 | HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); 135 | /** 136 | * @} 137 | */ 138 | 139 | /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions 140 | * @brief Timer Complementary Output Compare functions 141 | * @{ 142 | */ 143 | /* Timer Complementary Output Compare functions *****************************/ 144 | /* Blocking mode: Polling */ 145 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 146 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 147 | 148 | /* Non-Blocking mode: Interrupt */ 149 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 150 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 151 | 152 | /* Non-Blocking mode: DMA */ 153 | HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 154 | HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 155 | /** 156 | * @} 157 | */ 158 | 159 | /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions 160 | * @brief Timer Complementary PWM functions 161 | * @{ 162 | */ 163 | /* Timer Complementary PWM functions ****************************************/ 164 | /* Blocking mode: Polling */ 165 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); 166 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); 167 | 168 | /* Non-Blocking mode: Interrupt */ 169 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 170 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); 171 | /* Non-Blocking mode: DMA */ 172 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); 173 | HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); 174 | /** 175 | * @} 176 | */ 177 | 178 | /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions 179 | * @brief Timer Complementary One Pulse functions 180 | * @{ 181 | */ 182 | /* Timer Complementary One Pulse functions **********************************/ 183 | /* Blocking mode: Polling */ 184 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 185 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 186 | 187 | /* Non-Blocking mode: Interrupt */ 188 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 189 | HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); 190 | /** 191 | * @} 192 | */ 193 | 194 | /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions 195 | * @brief Peripheral Control functions 196 | * @{ 197 | */ 198 | /* Extended Control functions ************************************************/ 199 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 200 | uint32_t CommutationSource); 201 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 202 | uint32_t CommutationSource); 203 | HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, 204 | uint32_t CommutationSource); 205 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, 206 | TIM_MasterConfigTypeDef *sMasterConfig); 207 | HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, 208 | TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); 209 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); 210 | /** 211 | * @} 212 | */ 213 | 214 | /** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions 215 | * @brief Extended Callbacks functions 216 | * @{ 217 | */ 218 | /* Extended Callback **********************************************************/ 219 | void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); 220 | void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); 221 | void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); 222 | /** 223 | * @} 224 | */ 225 | 226 | /** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions 227 | * @brief Extended Peripheral State functions 228 | * @{ 229 | */ 230 | /* Extended Peripheral State functions ***************************************/ 231 | HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim); 232 | HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim, uint32_t ChannelN); 233 | /** 234 | * @} 235 | */ 236 | 237 | /** 238 | * @} 239 | */ 240 | /* End of exported functions -------------------------------------------------*/ 241 | 242 | /* Private functions----------------------------------------------------------*/ 243 | /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions 244 | * @{ 245 | */ 246 | void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); 247 | void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); 248 | /** 249 | * @} 250 | */ 251 | /* End of private functions --------------------------------------------------*/ 252 | 253 | /** 254 | * @} 255 | */ 256 | 257 | /** 258 | * @} 259 | */ 260 | 261 | #ifdef __cplusplus 262 | } 263 | #endif 264 | 265 | 266 | #endif /* STM32F0xx_HAL_TIM_EX_H */ 267 | 268 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 269 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_cortex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_cortex.c 4 | * @author MCD Application Team 5 | * @brief CORTEX HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the CORTEX: 8 | * + Initialization and de-initialization functions 9 | * + Peripheral Control functions 10 | * 11 | * @verbatim 12 | ============================================================================== 13 | ##### How to use this driver ##### 14 | ============================================================================== 15 | 16 | [..] 17 | *** How to configure Interrupts using CORTEX HAL driver *** 18 | =========================================================== 19 | [..] 20 | This section provides functions allowing to configure the NVIC interrupts (IRQ). 21 | The Cortex-M0 exceptions are managed by CMSIS functions. 22 | (#) Enable and Configure the priority of the selected IRQ Channels. 23 | The priority can be 0..3. 24 | 25 | -@- Lower priority values gives higher priority. 26 | -@- Priority Order: 27 | (#@) Lowest priority. 28 | (#@) Lowest hardware priority (IRQn position). 29 | 30 | (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() 31 | 32 | (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 33 | 34 | -@- Negative value of IRQn_Type are not allowed. 35 | 36 | 37 | [..] 38 | *** How to configure Systick using CORTEX HAL driver *** 39 | ======================================================== 40 | [..] 41 | Setup SysTick Timer for time base. 42 | 43 | (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which 44 | is a CMSIS function that: 45 | (++) Configures the SysTick Reload register with value passed as function parameter. 46 | (++) Configures the SysTick IRQ priority to the lowest value (0x03). 47 | (++) Resets the SysTick Counter register. 48 | (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). 49 | (++) Enables the SysTick Interrupt. 50 | (++) Starts the SysTick Counter. 51 | 52 | (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro 53 | HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the 54 | HAL_SYSTICK_Config() function call. The HAL_SYSTICK_CLKSourceConfig() macro is defined 55 | inside the stm32f0xx_hal_cortex.h file. 56 | 57 | (+) You can change the SysTick IRQ priority by calling the 58 | HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 59 | call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. 60 | 61 | (+) To adjust the SysTick time base, use the following formula: 62 | 63 | Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) 64 | (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function 65 | (++) Reload Value should not exceed 0xFFFFFF 66 | 67 | @endverbatim 68 | ****************************************************************************** 69 | * @attention 70 | * 71 | *

© Copyright (c) 2016 STMicroelectronics. 72 | * All rights reserved.

73 | * 74 | * This software component is licensed by ST under BSD 3-Clause license, 75 | * the "License"; You may not use this file except in compliance with the 76 | * License. You may obtain a copy of the License at: 77 | * opensource.org/licenses/BSD-3-Clause 78 | * 79 | ****************************************************************************** 80 | */ 81 | 82 | /* Includes ------------------------------------------------------------------*/ 83 | #include "stm32f0xx_hal.h" 84 | 85 | /** @addtogroup STM32F0xx_HAL_Driver 86 | * @{ 87 | */ 88 | 89 | /** @defgroup CORTEX CORTEX 90 | * @brief CORTEX CORTEX HAL module driver 91 | * @{ 92 | */ 93 | 94 | #ifdef HAL_CORTEX_MODULE_ENABLED 95 | 96 | /* Private typedef -----------------------------------------------------------*/ 97 | /* Private define ------------------------------------------------------------*/ 98 | /* Private macro -------------------------------------------------------------*/ 99 | /* Private variables ---------------------------------------------------------*/ 100 | /* Private function prototypes -----------------------------------------------*/ 101 | /* Exported functions ---------------------------------------------------------*/ 102 | 103 | /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 104 | * @{ 105 | */ 106 | 107 | 108 | /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions 109 | * @brief Initialization and Configuration functions 110 | * 111 | @verbatim 112 | ============================================================================== 113 | ##### Initialization and de-initialization functions ##### 114 | ============================================================================== 115 | [..] 116 | This section provides the CORTEX HAL driver functions allowing to configure Interrupts 117 | Systick functionalities 118 | 119 | @endverbatim 120 | * @{ 121 | */ 122 | 123 | /** 124 | * @brief Sets the priority of an interrupt. 125 | * @param IRQn External interrupt number . 126 | * This parameter can be an enumerator of IRQn_Type enumeration 127 | * (For the complete STM32 Devices IRQ Channels list, please refer to stm32f0xx.h file) 128 | * @param PreemptPriority The preemption priority for the IRQn channel. 129 | * This parameter can be a value between 0 and 3. 130 | * A lower priority value indicates a higher priority 131 | * @param SubPriority the subpriority level for the IRQ channel. 132 | * with stm32f0xx devices, this parameter is a dummy value and it is ignored, because 133 | * no subpriority supported in Cortex M0 based products. 134 | * @retval None 135 | */ 136 | void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) 137 | { 138 | /* Check the parameters */ 139 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); 140 | NVIC_SetPriority(IRQn,PreemptPriority); 141 | } 142 | 143 | /** 144 | * @brief Enables a device specific interrupt in the NVIC interrupt controller. 145 | * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 146 | * function should be called before. 147 | * @param IRQn External interrupt number. 148 | * This parameter can be an enumerator of IRQn_Type enumeration 149 | * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) 150 | * @retval None 151 | */ 152 | void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) 153 | { 154 | /* Check the parameters */ 155 | assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 156 | 157 | /* Enable interrupt */ 158 | NVIC_EnableIRQ(IRQn); 159 | } 160 | 161 | /** 162 | * @brief Disables a device specific interrupt in the NVIC interrupt controller. 163 | * @param IRQn External interrupt number. 164 | * This parameter can be an enumerator of IRQn_Type enumeration 165 | * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) 166 | * @retval None 167 | */ 168 | void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) 169 | { 170 | /* Check the parameters */ 171 | assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 172 | 173 | /* Disable interrupt */ 174 | NVIC_DisableIRQ(IRQn); 175 | } 176 | 177 | /** 178 | * @brief Initiates a system reset request to reset the MCU. 179 | * @retval None 180 | */ 181 | void HAL_NVIC_SystemReset(void) 182 | { 183 | /* System Reset */ 184 | NVIC_SystemReset(); 185 | } 186 | 187 | /** 188 | * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. 189 | * Counter is in free running mode to generate periodic interrupts. 190 | * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. 191 | * @retval status: - 0 Function succeeded. 192 | * - 1 Function failed. 193 | */ 194 | uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) 195 | { 196 | return SysTick_Config(TicksNumb); 197 | } 198 | /** 199 | * @} 200 | */ 201 | 202 | /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 203 | * @brief Cortex control functions 204 | * 205 | @verbatim 206 | ============================================================================== 207 | ##### Peripheral Control functions ##### 208 | ============================================================================== 209 | [..] 210 | This subsection provides a set of functions allowing to control the CORTEX 211 | (NVIC, SYSTICK) functionalities. 212 | 213 | 214 | @endverbatim 215 | * @{ 216 | */ 217 | 218 | 219 | /** 220 | * @brief Gets the priority of an interrupt. 221 | * @param IRQn External interrupt number. 222 | * This parameter can be an enumerator of IRQn_Type enumeration 223 | * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) 224 | * @retval None 225 | */ 226 | uint32_t HAL_NVIC_GetPriority(IRQn_Type IRQn) 227 | { 228 | /* Get priority for Cortex-M system or device specific interrupts */ 229 | return NVIC_GetPriority(IRQn); 230 | } 231 | 232 | /** 233 | * @brief Sets Pending bit of an external interrupt. 234 | * @param IRQn External interrupt number 235 | * This parameter can be an enumerator of IRQn_Type enumeration 236 | * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) 237 | * @retval None 238 | */ 239 | void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) 240 | { 241 | /* Check the parameters */ 242 | assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 243 | 244 | /* Set interrupt pending */ 245 | NVIC_SetPendingIRQ(IRQn); 246 | } 247 | 248 | /** 249 | * @brief Gets Pending Interrupt (reads the pending register in the NVIC 250 | * and returns the pending bit for the specified interrupt). 251 | * @param IRQn External interrupt number. 252 | * This parameter can be an enumerator of IRQn_Type enumeration 253 | * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) 254 | * @retval status: - 0 Interrupt status is not pending. 255 | * - 1 Interrupt status is pending. 256 | */ 257 | uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) 258 | { 259 | /* Check the parameters */ 260 | assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 261 | 262 | /* Return 1 if pending else 0 */ 263 | return NVIC_GetPendingIRQ(IRQn); 264 | } 265 | 266 | /** 267 | * @brief Clears the pending bit of an external interrupt. 268 | * @param IRQn External interrupt number. 269 | * This parameter can be an enumerator of IRQn_Type enumeration 270 | * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f0xxxx.h)) 271 | * @retval None 272 | */ 273 | void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) 274 | { 275 | /* Check the parameters */ 276 | assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 277 | 278 | /* Clear pending interrupt */ 279 | NVIC_ClearPendingIRQ(IRQn); 280 | } 281 | 282 | /** 283 | * @brief Configures the SysTick clock source. 284 | * @param CLKSource specifies the SysTick clock source. 285 | * This parameter can be one of the following values: 286 | * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. 287 | * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 288 | * @retval None 289 | */ 290 | void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) 291 | { 292 | /* Check the parameters */ 293 | assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); 294 | if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 295 | { 296 | SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 297 | } 298 | else 299 | { 300 | SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 301 | } 302 | } 303 | 304 | /** 305 | * @brief This function handles SYSTICK interrupt request. 306 | * @retval None 307 | */ 308 | void HAL_SYSTICK_IRQHandler(void) 309 | { 310 | HAL_SYSTICK_Callback(); 311 | } 312 | 313 | /** 314 | * @brief SYSTICK callback. 315 | * @retval None 316 | */ 317 | __weak void HAL_SYSTICK_Callback(void) 318 | { 319 | /* NOTE : This function Should not be modified, when the callback is needed, 320 | the HAL_SYSTICK_Callback could be implemented in the user file 321 | */ 322 | } 323 | 324 | /** 325 | * @} 326 | */ 327 | 328 | /** 329 | * @} 330 | */ 331 | 332 | #endif /* HAL_CORTEX_MODULE_ENABLED */ 333 | /** 334 | * @} 335 | */ 336 | 337 | /** 338 | * @} 339 | */ 340 | 341 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 342 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_i2c_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_i2c_ex.c 4 | * @author MCD Application Team 5 | * @brief I2C Extended HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of I2C Extended peripheral: 8 | * + Filter Mode Functions 9 | * + WakeUp Mode Functions 10 | * + FastModePlus Functions 11 | * 12 | @verbatim 13 | ============================================================================== 14 | ##### I2C peripheral Extended features ##### 15 | ============================================================================== 16 | 17 | [..] Comparing to other previous devices, the I2C interface for STM32F0xx 18 | devices contains the following additional features 19 | 20 | (+) Possibility to disable or enable Analog Noise Filter 21 | (+) Use of a configured Digital Noise Filter 22 | (+) Disable or enable wakeup from Stop mode(s) 23 | (+) Disable or enable Fast Mode Plus 24 | 25 | ##### How to use this driver ##### 26 | ============================================================================== 27 | [..] This driver provides functions to configure Noise Filter and Wake Up Feature 28 | (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() 29 | (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() 30 | (#) Configure the enable or disable of I2C Wake Up Mode using the functions : 31 | (++) HAL_I2CEx_EnableWakeUp() 32 | (++) HAL_I2CEx_DisableWakeUp() 33 | (#) Configure the enable or disable of fast mode plus driving capability using the functions : 34 | (++) HAL_I2CEx_EnableFastModePlus() 35 | (++) HAL_I2CEx_DisableFastModePlus() 36 | @endverbatim 37 | ****************************************************************************** 38 | * @attention 39 | * 40 | *

© Copyright (c) 2016 STMicroelectronics. 41 | * All rights reserved.

42 | * 43 | * This software component is licensed by ST under BSD 3-Clause license, 44 | * the "License"; You may not use this file except in compliance with the 45 | * License. You may obtain a copy of the License at: 46 | * opensource.org/licenses/BSD-3-Clause 47 | * 48 | ****************************************************************************** 49 | */ 50 | 51 | /* Includes ------------------------------------------------------------------*/ 52 | #include "stm32f0xx_hal.h" 53 | 54 | /** @addtogroup STM32F0xx_HAL_Driver 55 | * @{ 56 | */ 57 | 58 | /** @defgroup I2CEx I2CEx 59 | * @brief I2C Extended HAL module driver 60 | * @{ 61 | */ 62 | 63 | #ifdef HAL_I2C_MODULE_ENABLED 64 | 65 | /* Private typedef -----------------------------------------------------------*/ 66 | /* Private define ------------------------------------------------------------*/ 67 | /* Private macro -------------------------------------------------------------*/ 68 | /* Private variables ---------------------------------------------------------*/ 69 | /* Private function prototypes -----------------------------------------------*/ 70 | /* Private functions ---------------------------------------------------------*/ 71 | 72 | /** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions 73 | * @{ 74 | */ 75 | 76 | /** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions 77 | * @brief Filter Mode Functions 78 | * 79 | @verbatim 80 | =============================================================================== 81 | ##### Filter Mode Functions ##### 82 | =============================================================================== 83 | [..] This section provides functions allowing to: 84 | (+) Configure Noise Filters 85 | 86 | @endverbatim 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @brief Configure I2C Analog noise filter. 92 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 93 | * the configuration information for the specified I2Cx peripheral. 94 | * @param AnalogFilter New state of the Analog filter. 95 | * @retval HAL status 96 | */ 97 | HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) 98 | { 99 | /* Check the parameters */ 100 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 101 | assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); 102 | 103 | if (hi2c->State == HAL_I2C_STATE_READY) 104 | { 105 | /* Process Locked */ 106 | __HAL_LOCK(hi2c); 107 | 108 | hi2c->State = HAL_I2C_STATE_BUSY; 109 | 110 | /* Disable the selected I2C peripheral */ 111 | __HAL_I2C_DISABLE(hi2c); 112 | 113 | /* Reset I2Cx ANOFF bit */ 114 | hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); 115 | 116 | /* Set analog filter bit*/ 117 | hi2c->Instance->CR1 |= AnalogFilter; 118 | 119 | __HAL_I2C_ENABLE(hi2c); 120 | 121 | hi2c->State = HAL_I2C_STATE_READY; 122 | 123 | /* Process Unlocked */ 124 | __HAL_UNLOCK(hi2c); 125 | 126 | return HAL_OK; 127 | } 128 | else 129 | { 130 | return HAL_BUSY; 131 | } 132 | } 133 | 134 | /** 135 | * @brief Configure I2C Digital noise filter. 136 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 137 | * the configuration information for the specified I2Cx peripheral. 138 | * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. 139 | * @retval HAL status 140 | */ 141 | HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) 142 | { 143 | uint32_t tmpreg; 144 | 145 | /* Check the parameters */ 146 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); 147 | assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); 148 | 149 | if (hi2c->State == HAL_I2C_STATE_READY) 150 | { 151 | /* Process Locked */ 152 | __HAL_LOCK(hi2c); 153 | 154 | hi2c->State = HAL_I2C_STATE_BUSY; 155 | 156 | /* Disable the selected I2C peripheral */ 157 | __HAL_I2C_DISABLE(hi2c); 158 | 159 | /* Get the old register value */ 160 | tmpreg = hi2c->Instance->CR1; 161 | 162 | /* Reset I2Cx DNF bits [11:8] */ 163 | tmpreg &= ~(I2C_CR1_DNF); 164 | 165 | /* Set I2Cx DNF coefficient */ 166 | tmpreg |= DigitalFilter << 8U; 167 | 168 | /* Store the new register value */ 169 | hi2c->Instance->CR1 = tmpreg; 170 | 171 | __HAL_I2C_ENABLE(hi2c); 172 | 173 | hi2c->State = HAL_I2C_STATE_READY; 174 | 175 | /* Process Unlocked */ 176 | __HAL_UNLOCK(hi2c); 177 | 178 | return HAL_OK; 179 | } 180 | else 181 | { 182 | return HAL_BUSY; 183 | } 184 | } 185 | /** 186 | * @} 187 | */ 188 | #if defined(I2C_CR1_WUPEN) 189 | 190 | /** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions 191 | * @brief WakeUp Mode Functions 192 | * 193 | @verbatim 194 | =============================================================================== 195 | ##### WakeUp Mode Functions ##### 196 | =============================================================================== 197 | [..] This section provides functions allowing to: 198 | (+) Configure Wake Up Feature 199 | 200 | @endverbatim 201 | * @{ 202 | */ 203 | 204 | /** 205 | * @brief Enable I2C wakeup from Stop mode(s). 206 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 207 | * the configuration information for the specified I2Cx peripheral. 208 | * @retval HAL status 209 | */ 210 | HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) 211 | { 212 | /* Check the parameters */ 213 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 214 | 215 | if (hi2c->State == HAL_I2C_STATE_READY) 216 | { 217 | /* Process Locked */ 218 | __HAL_LOCK(hi2c); 219 | 220 | hi2c->State = HAL_I2C_STATE_BUSY; 221 | 222 | /* Disable the selected I2C peripheral */ 223 | __HAL_I2C_DISABLE(hi2c); 224 | 225 | /* Enable wakeup from stop mode */ 226 | hi2c->Instance->CR1 |= I2C_CR1_WUPEN; 227 | 228 | __HAL_I2C_ENABLE(hi2c); 229 | 230 | hi2c->State = HAL_I2C_STATE_READY; 231 | 232 | /* Process Unlocked */ 233 | __HAL_UNLOCK(hi2c); 234 | 235 | return HAL_OK; 236 | } 237 | else 238 | { 239 | return HAL_BUSY; 240 | } 241 | } 242 | 243 | /** 244 | * @brief Disable I2C wakeup from Stop mode(s). 245 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains 246 | * the configuration information for the specified I2Cx peripheral. 247 | * @retval HAL status 248 | */ 249 | HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) 250 | { 251 | /* Check the parameters */ 252 | assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); 253 | 254 | if (hi2c->State == HAL_I2C_STATE_READY) 255 | { 256 | /* Process Locked */ 257 | __HAL_LOCK(hi2c); 258 | 259 | hi2c->State = HAL_I2C_STATE_BUSY; 260 | 261 | /* Disable the selected I2C peripheral */ 262 | __HAL_I2C_DISABLE(hi2c); 263 | 264 | /* Enable wakeup from stop mode */ 265 | hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); 266 | 267 | __HAL_I2C_ENABLE(hi2c); 268 | 269 | hi2c->State = HAL_I2C_STATE_READY; 270 | 271 | /* Process Unlocked */ 272 | __HAL_UNLOCK(hi2c); 273 | 274 | return HAL_OK; 275 | } 276 | else 277 | { 278 | return HAL_BUSY; 279 | } 280 | } 281 | /** 282 | * @} 283 | */ 284 | #endif /* I2C_CR1_WUPEN */ 285 | 286 | /** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions 287 | * @brief Fast Mode Plus Functions 288 | * 289 | @verbatim 290 | =============================================================================== 291 | ##### Fast Mode Plus Functions ##### 292 | =============================================================================== 293 | [..] This section provides functions allowing to: 294 | (+) Configure Fast Mode Plus 295 | 296 | @endverbatim 297 | * @{ 298 | */ 299 | 300 | /** 301 | * @brief Enable the I2C fast mode plus driving capability. 302 | * @param ConfigFastModePlus Selects the pin. 303 | * This parameter can be one of the @ref I2CEx_FastModePlus values 304 | * @note For I2C1, fast mode plus driving capability can be enabled on all selected 305 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 306 | * on each one of the following pins PB6, PB7, PB8 and PB9. 307 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 308 | * can be enabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 309 | * @note For all I2C2 pins fast mode plus driving capability can be enabled 310 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 311 | * @retval None 312 | */ 313 | void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus) 314 | { 315 | /* Check the parameter */ 316 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 317 | 318 | /* Enable SYSCFG clock */ 319 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 320 | 321 | /* Enable fast mode plus driving capability for selected pin */ 322 | SET_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 323 | } 324 | 325 | /** 326 | * @brief Disable the I2C fast mode plus driving capability. 327 | * @param ConfigFastModePlus Selects the pin. 328 | * This parameter can be one of the @ref I2CEx_FastModePlus values 329 | * @note For I2C1, fast mode plus driving capability can be disabled on all selected 330 | * I2C1 pins using I2C_FASTMODEPLUS_I2C1 parameter or independently 331 | * on each one of the following pins PB6, PB7, PB8 and PB9. 332 | * @note For remaining I2C1 pins (PA14, PA15...) fast mode plus driving capability 333 | * can be disabled only by using I2C_FASTMODEPLUS_I2C1 parameter. 334 | * @note For all I2C2 pins fast mode plus driving capability can be disabled 335 | * only by using I2C_FASTMODEPLUS_I2C2 parameter. 336 | * @retval None 337 | */ 338 | void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus) 339 | { 340 | /* Check the parameter */ 341 | assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus)); 342 | 343 | /* Enable SYSCFG clock */ 344 | __HAL_RCC_SYSCFG_CLK_ENABLE(); 345 | 346 | /* Disable fast mode plus driving capability for selected pin */ 347 | CLEAR_BIT(SYSCFG->CFGR1, (uint32_t)ConfigFastModePlus); 348 | } 349 | /** 350 | * @} 351 | */ 352 | /** 353 | * @} 354 | */ 355 | 356 | #endif /* HAL_I2C_MODULE_ENABLED */ 357 | /** 358 | * @} 359 | */ 360 | 361 | /** 362 | * @} 363 | */ 364 | 365 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 366 | -------------------------------------------------------------------------------- /Software/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_pwr_ex.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_hal_pwr_ex.c 4 | * @author MCD Application Team 5 | * @brief Extended PWR HAL module driver. 6 | * This file provides firmware functions to manage the following 7 | * functionalities of the Power Controller (PWR) peripheral: 8 | * + Extended Initialization and de-initialization functions 9 | * + Extended Peripheral Control functions 10 | * 11 | ****************************************************************************** 12 | * @attention 13 | * 14 | *

© Copyright (c) 2016 STMicroelectronics. 15 | * All rights reserved.

16 | * 17 | * This software component is licensed by ST under BSD 3-Clause license, 18 | * the "License"; You may not use this file except in compliance with the 19 | * License. You may obtain a copy of the License at: 20 | * opensource.org/licenses/BSD-3-Clause 21 | * 22 | ****************************************************************************** 23 | */ 24 | 25 | /* Includes ------------------------------------------------------------------*/ 26 | #include "stm32f0xx_hal.h" 27 | 28 | /** @addtogroup STM32F0xx_HAL_Driver 29 | * @{ 30 | */ 31 | 32 | /** @defgroup PWREx PWREx 33 | * @brief PWREx HAL module driver 34 | * @{ 35 | */ 36 | 37 | #ifdef HAL_PWR_MODULE_ENABLED 38 | 39 | /* Private typedef -----------------------------------------------------------*/ 40 | /* Private define ------------------------------------------------------------*/ 41 | /** @defgroup PWREx_Private_Constants PWREx Private Constants 42 | * @{ 43 | */ 44 | #define PVD_MODE_IT (0x00010000U) 45 | #define PVD_MODE_EVT (0x00020000U) 46 | #define PVD_RISING_EDGE (0x00000001U) 47 | #define PVD_FALLING_EDGE (0x00000002U) 48 | /** 49 | * @} 50 | */ 51 | 52 | /* Private macro -------------------------------------------------------------*/ 53 | /* Private variables ---------------------------------------------------------*/ 54 | /* Private function prototypes -----------------------------------------------*/ 55 | /* Exported functions ---------------------------------------------------------*/ 56 | 57 | /** @defgroup PWREx_Exported_Functions PWREx Exported Functions 58 | * @{ 59 | */ 60 | 61 | /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Control Functions 62 | * @brief Extended Peripheral Control functions 63 | * 64 | @verbatim 65 | 66 | =============================================================================== 67 | ##### Peripheral extended control functions ##### 68 | =============================================================================== 69 | 70 | *** PVD configuration *** 71 | ========================= 72 | [..] 73 | (+) The PVD is used to monitor the VDD power supply by comparing it to a 74 | threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR). 75 | (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower 76 | than the PVD threshold. This event is internally connected to the EXTI 77 | line16 and can generate an interrupt if enabled. This is done through 78 | HAL_PWR_ConfigPVD(), HAL_PWR_EnablePVD() functions. 79 | (+) The PVD is stopped in Standby mode. 80 | -@- PVD is not available on STM32F030x4/x6/x8 81 | 82 | *** VDDIO2 Monitor Configuration *** 83 | ==================================== 84 | [..] 85 | (+) VDDIO2 monitor is used to monitor the VDDIO2 power supply by comparing it 86 | to VREFInt Voltage 87 | (+) This monitor is internally connected to the EXTI line31 88 | and can generate an interrupt if enabled. This is done through 89 | HAL_PWREx_EnableVddio2Monitor() function. 90 | -@- VDDIO2 is available on STM32F07x/09x/04x 91 | 92 | @endverbatim 93 | * @{ 94 | */ 95 | 96 | #if defined (STM32F031x6) || defined (STM32F051x8) || \ 97 | defined (STM32F071xB) || defined (STM32F091xC) || \ 98 | defined (STM32F042x6) || defined (STM32F072xB) 99 | /** 100 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 101 | * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration 102 | * information for the PVD. 103 | * @note Refer to the electrical characteristics of your device datasheet for 104 | * more details about the voltage threshold corresponding to each 105 | * detection level. 106 | * @retval None 107 | */ 108 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) 109 | { 110 | /* Check the parameters */ 111 | assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); 112 | assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode)); 113 | 114 | /* Set PLS[7:5] bits according to PVDLevel value */ 115 | MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel); 116 | 117 | /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 118 | __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); 119 | __HAL_PWR_PVD_EXTI_DISABLE_IT(); 120 | __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); 121 | 122 | /* Configure interrupt mode */ 123 | if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) 124 | { 125 | __HAL_PWR_PVD_EXTI_ENABLE_IT(); 126 | } 127 | 128 | /* Configure event mode */ 129 | if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) 130 | { 131 | __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); 132 | } 133 | 134 | /* Configure the edge */ 135 | if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) 136 | { 137 | __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); 138 | } 139 | 140 | if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) 141 | { 142 | __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); 143 | } 144 | } 145 | 146 | /** 147 | * @brief Enables the Power Voltage Detector(PVD). 148 | * @retval None 149 | */ 150 | void HAL_PWR_EnablePVD(void) 151 | { 152 | PWR->CR |= (uint32_t)PWR_CR_PVDE; 153 | } 154 | 155 | /** 156 | * @brief Disables the Power Voltage Detector(PVD). 157 | * @retval None 158 | */ 159 | void HAL_PWR_DisablePVD(void) 160 | { 161 | PWR->CR &= ~((uint32_t)PWR_CR_PVDE); 162 | } 163 | 164 | /** 165 | * @brief This function handles the PWR PVD interrupt request. 166 | * @note This API should be called under the PVD_IRQHandler() or PVD_VDDIO2_IRQHandler(). 167 | * @retval None 168 | */ 169 | void HAL_PWR_PVD_IRQHandler(void) 170 | { 171 | /* Check PWR exti flag */ 172 | if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 173 | { 174 | /* PWR PVD interrupt user callback */ 175 | HAL_PWR_PVDCallback(); 176 | 177 | /* Clear PWR Exti pending bit */ 178 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 179 | } 180 | } 181 | 182 | /** 183 | * @brief PWR PVD interrupt callback 184 | * @retval None 185 | */ 186 | __weak void HAL_PWR_PVDCallback(void) 187 | { 188 | /* NOTE : This function Should not be modified, when the callback is needed, 189 | the HAL_PWR_PVDCallback could be implemented in the user file 190 | */ 191 | } 192 | 193 | #endif /* defined (STM32F031x6) || defined (STM32F051x8) || */ 194 | /* defined (STM32F071xB) || defined (STM32F091xC) || */ 195 | /* defined (STM32F042x6) || defined (STM32F072xB) */ 196 | 197 | #if defined (STM32F042x6) || defined (STM32F048xx) || \ 198 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ 199 | defined (STM32F091xC) || defined (STM32F098xx) 200 | /** 201 | * @brief Enable VDDIO2 monitor: enable Exti 31 and falling edge detection. 202 | * @note If Exti 31 is enable correlty and VDDIO2 voltage goes below Vrefint, 203 | an interrupt is generated Irq line 1. 204 | NVIS has to be enable by user. 205 | * @retval None 206 | */ 207 | void HAL_PWREx_EnableVddio2Monitor(void) 208 | { 209 | __HAL_PWR_VDDIO2_EXTI_ENABLE_IT(); 210 | __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE(); 211 | } 212 | 213 | /** 214 | * @brief Disable the Vddio2 Monitor. 215 | * @retval None 216 | */ 217 | void HAL_PWREx_DisableVddio2Monitor(void) 218 | { 219 | __HAL_PWR_VDDIO2_EXTI_DISABLE_IT(); 220 | __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE(); 221 | 222 | } 223 | 224 | /** 225 | * @brief This function handles the PWR Vddio2 monitor interrupt request. 226 | * @note This API should be called under the VDDIO2_IRQHandler() PVD_VDDIO2_IRQHandler(). 227 | * @retval None 228 | */ 229 | void HAL_PWREx_Vddio2Monitor_IRQHandler(void) 230 | { 231 | /* Check PWR exti flag */ 232 | if(__HAL_PWR_VDDIO2_EXTI_GET_FLAG() != RESET) 233 | { 234 | /* PWR Vddio2 monitor interrupt user callback */ 235 | HAL_PWREx_Vddio2MonitorCallback(); 236 | 237 | /* Clear PWR Exti pending bit */ 238 | __HAL_PWR_VDDIO2_EXTI_CLEAR_FLAG(); 239 | } 240 | } 241 | 242 | /** 243 | * @brief PWR Vddio2 Monitor interrupt callback 244 | * @retval None 245 | */ 246 | __weak void HAL_PWREx_Vddio2MonitorCallback(void) 247 | { 248 | /* NOTE : This function Should not be modified, when the callback is needed, 249 | the HAL_PWREx_Vddio2MonitorCallback could be implemented in the user file 250 | */ 251 | } 252 | 253 | #endif /* defined (STM32F042x6) || defined (STM32F048xx) || \ 254 | defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) || \ 255 | defined (STM32F091xC) || defined (STM32F098xx) */ 256 | 257 | /** 258 | * @} 259 | */ 260 | 261 | /** 262 | * @} 263 | */ 264 | 265 | #endif /* HAL_PWR_MODULE_ENABLED */ 266 | /** 267 | * @} 268 | */ 269 | 270 | /** 271 | * @} 272 | */ 273 | 274 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 275 | -------------------------------------------------------------------------------- /Software/STM32F042K6TX_FLASH.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** @file : LinkerScript.ld 5 | ** 6 | ** @author : Auto-generated by STM32CubeIDE 7 | ** 8 | ** @brief : Linker script for STM32F042K6Tx Device from STM32F0 series 9 | ** 32Kbytes FLASH 10 | ** 6Kbytes RAM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed as is, without any warranty 20 | ** of any kind. 21 | ** 22 | ****************************************************************************** 23 | ** @attention 24 | ** 25 | **

© Copyright (c) 2021 STMicroelectronics. 26 | ** All rights reserved.

27 | ** 28 | ** This software component is licensed by ST under BSD 3-Clause license, 29 | ** the "License"; You may not use this file except in compliance with the 30 | ** License. You may obtain a copy of the License at: 31 | ** opensource.org/licenses/BSD-3-Clause 32 | ** 33 | ****************************************************************************** 34 | */ 35 | 36 | /* Entry Point */ 37 | ENTRY(Reset_Handler) 38 | 39 | /* Highest address of the user mode stack */ 40 | _estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */ 41 | 42 | _Min_Heap_Size = 0x200 ; /* required amount of heap */ 43 | _Min_Stack_Size = 0x400 ; /* required amount of stack */ 44 | 45 | /* Memories definition */ 46 | MEMORY 47 | { 48 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 6K 49 | FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 32K 50 | } 51 | 52 | /* Sections */ 53 | SECTIONS 54 | { 55 | /* The startup code into "FLASH" Rom type memory */ 56 | .isr_vector : 57 | { 58 | . = ALIGN(4); 59 | KEEP(*(.isr_vector)) /* Startup code */ 60 | . = ALIGN(4); 61 | } >FLASH 62 | 63 | /* The program code and other data into "FLASH" Rom type memory */ 64 | .text : 65 | { 66 | . = ALIGN(4); 67 | *(.text) /* .text sections (code) */ 68 | *(.text*) /* .text* sections (code) */ 69 | *(.glue_7) /* glue arm to thumb code */ 70 | *(.glue_7t) /* glue thumb to arm code */ 71 | *(.eh_frame) 72 | 73 | KEEP (*(.init)) 74 | KEEP (*(.fini)) 75 | 76 | . = ALIGN(4); 77 | _etext = .; /* define a global symbols at end of code */ 78 | } >FLASH 79 | 80 | /* Constant data into "FLASH" Rom type memory */ 81 | .rodata : 82 | { 83 | . = ALIGN(4); 84 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 85 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 86 | . = ALIGN(4); 87 | } >FLASH 88 | 89 | .ARM.extab : { 90 | . = ALIGN(4); 91 | *(.ARM.extab* .gnu.linkonce.armextab.*) 92 | . = ALIGN(4); 93 | } >FLASH 94 | 95 | .ARM : { 96 | . = ALIGN(4); 97 | __exidx_start = .; 98 | *(.ARM.exidx*) 99 | __exidx_end = .; 100 | . = ALIGN(4); 101 | } >FLASH 102 | 103 | .preinit_array : 104 | { 105 | . = ALIGN(4); 106 | PROVIDE_HIDDEN (__preinit_array_start = .); 107 | KEEP (*(.preinit_array*)) 108 | PROVIDE_HIDDEN (__preinit_array_end = .); 109 | . = ALIGN(4); 110 | } >FLASH 111 | 112 | .init_array : 113 | { 114 | . = ALIGN(4); 115 | PROVIDE_HIDDEN (__init_array_start = .); 116 | KEEP (*(SORT(.init_array.*))) 117 | KEEP (*(.init_array*)) 118 | PROVIDE_HIDDEN (__init_array_end = .); 119 | . = ALIGN(4); 120 | } >FLASH 121 | 122 | .fini_array : 123 | { 124 | . = ALIGN(4); 125 | PROVIDE_HIDDEN (__fini_array_start = .); 126 | KEEP (*(SORT(.fini_array.*))) 127 | KEEP (*(.fini_array*)) 128 | PROVIDE_HIDDEN (__fini_array_end = .); 129 | . = ALIGN(4); 130 | } >FLASH 131 | 132 | /* Used by the startup to initialize data */ 133 | _sidata = LOADADDR(.data); 134 | 135 | /* Initialized data sections into "RAM" Ram type memory */ 136 | .data : 137 | { 138 | . = ALIGN(4); 139 | _sdata = .; /* create a global symbol at data start */ 140 | *(.data) /* .data sections */ 141 | *(.data*) /* .data* sections */ 142 | *(.RamFunc) /* .RamFunc sections */ 143 | *(.RamFunc*) /* .RamFunc* sections */ 144 | 145 | . = ALIGN(4); 146 | _edata = .; /* define a global symbol at data end */ 147 | 148 | } >RAM AT> FLASH 149 | 150 | /* Uninitialized data section into "RAM" Ram type memory */ 151 | . = ALIGN(4); 152 | .bss : 153 | { 154 | /* This is used by the startup in order to initialize the .bss section */ 155 | _sbss = .; /* define a global symbol at bss start */ 156 | __bss_start__ = _sbss; 157 | *(.bss) 158 | *(.bss*) 159 | *(COMMON) 160 | 161 | . = ALIGN(4); 162 | _ebss = .; /* define a global symbol at bss end */ 163 | __bss_end__ = _ebss; 164 | } >RAM 165 | 166 | /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */ 167 | ._user_heap_stack : 168 | { 169 | . = ALIGN(8); 170 | PROVIDE ( end = . ); 171 | PROVIDE ( _end = . ); 172 | . = . + _Min_Heap_Size; 173 | . = . + _Min_Stack_Size; 174 | . = ALIGN(8); 175 | } >RAM 176 | 177 | /* Remove information from the compiler libraries */ 178 | /DISCARD/ : 179 | { 180 | libc.a ( * ) 181 | libm.a ( * ) 182 | libgcc.a ( * ) 183 | } 184 | 185 | .ARM.attributes 0 : { *(.ARM.attributes) } 186 | } 187 | -------------------------------------------------------------------------------- /Software/SensorlessESC.ioc: -------------------------------------------------------------------------------- 1 | #MicroXplorer Configuration settings - do not modify 2 | File.Version=6 3 | KeepUserPlacement=false 4 | Mcu.Family=STM32F0 5 | Mcu.IP0=NVIC 6 | Mcu.IP1=RCC 7 | Mcu.IP2=SYS 8 | Mcu.IP3=TIM2 9 | Mcu.IP4=TIM3 10 | Mcu.IPNb=5 11 | Mcu.Name=STM32F042K(4-6)Tx 12 | Mcu.Package=LQFP32 13 | Mcu.Pin0=PA0 14 | Mcu.Pin1=PA1 15 | Mcu.Pin10=PB7 16 | Mcu.Pin11=VP_SYS_VS_Systick 17 | Mcu.Pin2=PA2 18 | Mcu.Pin3=PA3 19 | Mcu.Pin4=PA4 20 | Mcu.Pin5=PA5 21 | Mcu.Pin6=PA6 22 | Mcu.Pin7=PB3 23 | Mcu.Pin8=PB5 24 | Mcu.Pin9=PB6 25 | Mcu.PinsNb=12 26 | Mcu.ThirdPartyNb=0 27 | Mcu.UserConstants= 28 | Mcu.UserName=STM32F042K6Tx 29 | MxCube.Version=6.3.0 30 | MxDb.Version=DB.6.0.30 31 | NVIC.EXTI4_15_IRQn=true\:2\:0\:true\:false\:true\:true\:true 32 | NVIC.ForceEnableDMAVector=true 33 | NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false 34 | NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false 35 | NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false 36 | NVIC.SVC_IRQn=true\:0\:0\:false\:false\:true\:false\:false 37 | NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true 38 | NVIC.TIM2_IRQn=true\:1\:0\:true\:false\:true\:true\:true 39 | NVIC.TIM3_IRQn=true\:0\:0\:false\:false\:true\:true\:true 40 | PA0.GPIOParameters=GPIO_Label 41 | PA0.GPIO_Label=PWM_A 42 | PA0.Signal=S_TIM2_CH1_ETR 43 | PA1.GPIOParameters=GPIO_Label 44 | PA1.GPIO_Label=PWM_B 45 | PA1.Signal=S_TIM2_CH2 46 | PA2.GPIOParameters=GPIO_Label 47 | PA2.GPIO_Label=PWM_C 48 | PA2.Signal=S_TIM2_CH3 49 | PA3.GPIOParameters=GPIO_Label 50 | PA3.GPIO_Label=OD_A 51 | PA3.Locked=true 52 | PA3.Signal=GPIO_Output 53 | PA4.GPIOParameters=GPIO_Label 54 | PA4.GPIO_Label=OD_B 55 | PA4.Locked=true 56 | PA4.Signal=GPIO_Output 57 | PA5.GPIOParameters=GPIO_Label 58 | PA5.GPIO_Label=OD_C 59 | PA5.Locked=true 60 | PA5.Signal=GPIO_Output 61 | PA6.Signal=S_TIM3_CH1 62 | PB3.GPIOParameters=GPIO_Label 63 | PB3.GPIO_Label=LED 64 | PB3.Locked=true 65 | PB3.Signal=GPIO_Output 66 | PB5.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI 67 | PB5.GPIO_Label=BEMF_A 68 | PB5.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING 69 | PB5.Locked=true 70 | PB5.Signal=GPXTI5 71 | PB6.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI 72 | PB6.GPIO_Label=BEMF_B 73 | PB6.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING 74 | PB6.Locked=true 75 | PB6.Signal=GPXTI6 76 | PB7.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI 77 | PB7.GPIO_Label=BEMF_C 78 | PB7.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_RISING_FALLING 79 | PB7.Locked=true 80 | PB7.Signal=GPXTI7 81 | PinOutPanel.RotationAngle=0 82 | ProjectManager.AskForMigrate=true 83 | ProjectManager.BackupPrevious=false 84 | ProjectManager.CompilerOptimize=6 85 | ProjectManager.ComputerToolchain=false 86 | ProjectManager.CoupleFile=true 87 | ProjectManager.CustomerFirmwarePackage= 88 | ProjectManager.DefaultFWLocation=true 89 | ProjectManager.DeletePrevious=true 90 | ProjectManager.DeviceId=STM32F042K6Tx 91 | ProjectManager.FirmwarePackage=STM32Cube FW_F0 V1.11.3 92 | ProjectManager.FreePins=false 93 | ProjectManager.HalAssertFull=false 94 | ProjectManager.HeapSize=0x200 95 | ProjectManager.KeepUserCode=true 96 | ProjectManager.LastFirmware=true 97 | ProjectManager.LibraryCopy=1 98 | ProjectManager.MainLocation=Core/Src 99 | ProjectManager.NoMain=false 100 | ProjectManager.PreviousToolchain= 101 | ProjectManager.ProjectBuild=false 102 | ProjectManager.ProjectFileName=SensorlessESC.ioc 103 | ProjectManager.ProjectName=SensorlessESC 104 | ProjectManager.RegisterCallBack= 105 | ProjectManager.StackSize=0x400 106 | ProjectManager.TargetToolchain=STM32CubeIDE 107 | ProjectManager.ToolChainLocation= 108 | ProjectManager.UnderRoot=true 109 | ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM2_Init-TIM2-false-HAL-true,4-MX_TIM14_Init-TIM14-false-HAL-true 110 | RCC.CECFreq_Value=32786.88524590164 111 | RCC.FamilyName=M 112 | RCC.HSICECFreq_Value=32786.88524590164 113 | RCC.IPParameters=CECFreq_Value,FamilyName,HSICECFreq_Value,PLLCLKFreq_Value,PLLMCOFreq_Value,TimSysFreq_Value,VCOOutput2Freq_Value 114 | RCC.PLLCLKFreq_Value=16000000 115 | RCC.PLLMCOFreq_Value=16000000 116 | RCC.TimSysFreq_Value=8000000 117 | RCC.VCOOutput2Freq_Value=8000000 118 | SH.GPXTI5.0=GPIO_EXTI5 119 | SH.GPXTI5.ConfNb=1 120 | SH.GPXTI6.0=GPIO_EXTI6 121 | SH.GPXTI6.ConfNb=1 122 | SH.GPXTI7.0=GPIO_EXTI7 123 | SH.GPXTI7.ConfNb=1 124 | SH.S_TIM2_CH1_ETR.0=TIM2_CH1,PWM Generation1 CH1 125 | SH.S_TIM2_CH1_ETR.ConfNb=1 126 | SH.S_TIM2_CH2.0=TIM2_CH2,PWM Generation2 CH2 127 | SH.S_TIM2_CH2.ConfNb=1 128 | SH.S_TIM2_CH3.0=TIM2_CH3,PWM Generation3 CH3 129 | SH.S_TIM2_CH3.ConfNb=1 130 | SH.S_TIM3_CH1.0=TIM3_CH1,PWM_Input_1 131 | SH.S_TIM3_CH1.ConfNb=1 132 | TIM2.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1 133 | TIM2.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2 134 | TIM2.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3 135 | TIM2.IPParameters=Prescaler,Period,Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3 136 | TIM2.Period=100 137 | TIM2.Prescaler=8-1 138 | VP_SYS_VS_Systick.Mode=SysTick 139 | VP_SYS_VS_Systick.Signal=SYS_VS_Systick 140 | board=custom 141 | isbadioc=false 142 | -------------------------------------------------------------------------------- /Software/scripts/format.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | echo "Running clang-format" 4 | 5 | clang-format --version 6 | 7 | clang-format -style=file -i Core/Src/bldc.c Core/Src/pwm.c Core/Inc/bldc.h Core/Inc/pwm.h 8 | -------------------------------------------------------------------------------- /Software/scripts/test_format.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | clang-format -style=file -Werror --dry-run -i Core/Src/bldc.c Core/Src/pwm.c Core/Inc/bldc.h Core/Inc/pwm.h 4 | --------------------------------------------------------------------------------