├── LD-Final-Project ├── FinalProject │ ├── BCDTest.v │ ├── CPUTest.v │ ├── CPUTester.v │ ├── FinalProject.v │ ├── FinalProject_summary.html │ ├── FrequencyDivider.v │ ├── HextoBCD.v │ ├── IMEM.v │ ├── IMEM_description.pdf │ └── TestingModule.v └── README.md ├── Microprocessor ├── ALU.v ├── ClockDivider.v ├── Control.v ├── ControlTest.v ├── DataMemory.v ├── DataMemoryTest.v ├── HexDecoder.v ├── IntegrationTest.v ├── Microprocessor.v ├── MicroprocessorWithTestInst.v ├── OpDecoder.v ├── Registers.v ├── RegistersTest.v └── TestProcessorTest.v └── stopwatch_verilog ├── README.md ├── bin2bcd.v ├── buttonStateMachine.v ├── ledbar.v ├── seg7Display.v ├── seg7dec.v ├── seg7dec2.v ├── timer.v └── watch.v /LD-Final-Project/FinalProject/BCDTest.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sally20921/LogicDesignFinalProject/HEAD/LD-Final-Project/FinalProject/BCDTest.v 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