├── LD-Final-Project ├── FinalProject │ ├── BCDTest.v │ ├── CPUTest.v │ ├── CPUTester.v │ ├── FinalProject.v │ ├── FinalProject_summary.html │ ├── FrequencyDivider.v │ ├── HextoBCD.v │ ├── IMEM.v │ ├── IMEM_description.pdf │ └── TestingModule.v └── README.md ├── Microprocessor ├── ALU.v ├── ClockDivider.v ├── Control.v ├── ControlTest.v ├── DataMemory.v ├── DataMemoryTest.v ├── HexDecoder.v ├── IntegrationTest.v ├── Microprocessor.v ├── MicroprocessorWithTestInst.v ├── OpDecoder.v ├── Registers.v ├── RegistersTest.v └── TestProcessorTest.v └── stopwatch_verilog ├── README.md ├── bin2bcd.v ├── buttonStateMachine.v ├── ledbar.v ├── seg7Display.v ├── seg7dec.v ├── seg7dec2.v ├── timer.v └── watch.v /LD-Final-Project/FinalProject/BCDTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 11:54:16 06/15/2018 8 | // Design Name: HextoBCD 9 | // Module Name: /csehome/calofmijuck/LDFP/BCDTest.v 10 | // Project Name: LDFP 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: HextoBCD 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module BCDTest; 26 | 27 | // Inputs 28 | reg [3:0] bcd; 29 | 30 | // Outputs 31 | wire [6:0] segout; 32 | 33 | // Instantiate the Unit Under Test (UUT) 34 | HextoBCD uut ( 35 | .bcd(bcd), 36 | .segout(segout) 37 | ); 38 | 39 | initial begin 40 | // Initialize Inputs 41 | bcd = 0; 42 | #50; 43 | bcd = 1; 44 | #50; 45 | bcd = 2; 46 | #50; 47 | bcd = 3; 48 | #50; 49 | bcd = 4; 50 | #50; 51 | bcd = 5; 52 | #50; 53 | bcd = 6; 54 | #50; 55 | bcd = 7; 56 | #50; 57 | bcd = 8; 58 | #50; 59 | bcd = 9; 60 | #50; 61 | bcd = 10; 62 | #50; 63 | bcd = 11; 64 | #50; 65 | bcd = 12; 66 | #50; 67 | bcd = 13; 68 | #50; 69 | bcd = 14; 70 | #50; 71 | bcd = 15; 72 | #50; 73 | bcd = 0; 74 | 75 | 76 | 77 | // Add stimulus here 78 | 79 | end 80 | 81 | endmodule 82 | 83 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/CPUTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | //////////////////////////////////////////////////////////////////////////////// 4 | // Company: 5 | // Engineer: 6 | // 7 | // Create Date: 13:17:36 06/14/2018 8 | // Design Name: FinalProject 9 | // Module Name: /csehome/calofmijuck/Downloads/LD/tester.v 10 | // Project Name: LD 11 | // Target Device: 12 | // Tool versions: 13 | // Description: 14 | // 15 | // Verilog Test Fixture created by ISE for module: FinalProject 16 | // 17 | // Dependencies: 18 | // 19 | // Revision: 20 | // Revision 0.01 - File Created 21 | // Additional Comments: 22 | // 23 | //////////////////////////////////////////////////////////////////////////////// 24 | 25 | module tester; 26 | 27 | // Inputs 28 | reg CLK; 29 | reg reset; 30 | wire [7:0] instruction; 31 | reg showPC; 32 | reg showReg0; 33 | reg showReg1; 34 | reg showReg2; 35 | reg showReg3; 36 | 37 | // Outputs 38 | wire [6:0] seg1; 39 | wire [6:0] seg2; 40 | wire [6:0] seg3; 41 | wire [6:0] seg4; 42 | wire [7:0] readingAddress; 43 | wire runningLED; 44 | 45 | // Instantiate the Unit Under Test (UUT) 46 | FinalProject uut ( 47 | .CLK(CLK), 48 | .reset(reset), 49 | .instruction(instruction), 50 | .showPC(showPC), 51 | .showReg0(showReg0), 52 | .showReg1(showReg1), 53 | .showReg2(showReg2), 54 | .showReg3(showReg3), 55 | .seg1(seg1), 56 | .seg2(seg2), 57 | .seg3(seg3), 58 | .seg4(seg4), 59 | .readingAddress(readingAddress), 60 | .runningLED(runningLED) 61 | ); 62 | 63 | wire [7:0] MemByte[20:0]; 64 | 65 | assign MemByte[0] = 8'b01000100; 66 | assign MemByte[1] = 8'b01001001; 67 | assign MemByte[2] = 8'b00011001; 68 | assign MemByte[3] = 8'b10000100; 69 | 70 | assign MemByte[4] = 8'b01000100; 71 | assign MemByte[5] = 8'b01001001; 72 | assign MemByte[6] = 8'b00011001; 73 | assign MemByte[7] = 8'b10000100; 74 | 75 | assign MemByte[8] = 8'b01000100; 76 | assign MemByte[9] = 8'b01001001; 77 | assign MemByte[10] = 8'b00011001; 78 | assign MemByte[11] = 8'b10000100; 79 | 80 | assign MemByte[12] = 8'b01000100; 81 | assign MemByte[13] = 8'b01001001; 82 | assign MemByte[14] = 8'b00011001; 83 | assign MemByte[15] = 8'b10000100; 84 | 85 | assign MemByte[16] = 8'b01000100; 86 | assign MemByte[17] = 8'b01001001; 87 | assign MemByte[18] = 8'b00011001; 88 | assign MemByte[19] = 8'b10000100; 89 | 90 | assign MemByte[20] = 8'b11000011; 91 | 92 | assign instruction = MemByte[readingAddress]; 93 | 94 | 95 | initial begin 96 | // Initialize Inputs 97 | CLK = 0; 98 | reset = 1; 99 | #50; 100 | reset = 0; 101 | 102 | 103 | 104 | // Add stimulus here 105 | 106 | end 107 | 108 | always #10 109 | CLK = ~CLK; 110 | endmodule 111 | 112 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/CPUTester.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module CPUTester; 3 | // Inputs 4 | reg CLK; 5 | reg reset; 6 | wire [7:0] instruction; 7 | reg showPC; 8 | reg showReg0; 9 | reg showReg1; 10 | reg showReg2; 11 | reg showReg3; 12 | reg [4:0] showData; 13 | 14 | // Outputs 15 | wire DCLED; 16 | wire [6:0] seg1; 17 | wire [6:0] seg2; 18 | wire [6:0] seg3; 19 | wire [6:0] seg4; 20 | wire [6:0] seg5; 21 | wire [6:0] seg6; 22 | wire [7:0] readingAddress; 23 | wire runningLED; 24 | wire [7:0] MemByte[20:0]; 25 | 26 | assign MemByte[0] = 8'b01000100; 27 | assign MemByte[1] = 8'b01001001; 28 | assign MemByte[2] = 8'b00011001; 29 | assign MemByte[3] = 8'b10000100; 30 | assign MemByte[4] = 8'b01000100; 31 | assign MemByte[5] = 8'b01001001; 32 | assign MemByte[6] = 8'b00011001; 33 | assign MemByte[7] = 8'b10000100; 34 | assign MemByte[8] = 8'b01000100; 35 | assign MemByte[9] = 8'b01001001; 36 | assign MemByte[10] = 8'b00011001; 37 | assign MemByte[11] = 8'b10000100; 38 | assign MemByte[12] = 8'b01000100; 39 | assign MemByte[13] = 8'b01001001; 40 | assign MemByte[14] = 8'b00011001; 41 | assign MemByte[15] = 8'b10000100; 42 | assign MemByte[16] = 8'b01000100; 43 | assign MemByte[17] = 8'b01001001; 44 | assign MemByte[18] = 8'b00011001; 45 | assign MemByte[19] = 8'b10000100; 46 | assign MemByte[20] = 8'b11000011; 47 | assign instruction = MemByte[readingAddress]; 48 | 49 | // Instantiate the Unit Under Test (UUT) 50 | FinalProject uut ( .CLK(CLK), .reset(reset), .instruction(instruction), .showPC(showPC), 51 | .showReg0(showReg0), .showReg1(showReg1), .showReg2(showReg2), .showReg3(showReg3), .showData(showData), 52 | .seg1(seg1), .seg2(seg2), .seg3(seg3), .seg4(seg4), .seg5(seg5), .seg6(seg6), 53 | .readingAddress(readingAddress), .runningLED(runningLED), .DCLED(DCLED), 54 | ); 55 | 56 | initial begin 57 | CLK = 0; 58 | reset = 1; 59 | #50; 60 | reset = 0; 61 | end 62 | always #10 63 | CLK = ~CLK; 64 | endmodule 65 | 66 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/FinalProject.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module FinalProject( 3 | input CLK, //machine clock (50MHz) 4 | input reset, //reset button 5 | input [7:0] instruction, //instruction input 6 | input showPC, 7 | input showReg0, 8 | input showReg1, 9 | input showReg2, 10 | input showReg3, 11 | input [4:0] showData, 12 | output reg DCLED, 13 | output [6:0] seg1, 14 | output [6:0] seg2, 15 | output [6:0] seg3, 16 | output [6:0] seg4, 17 | output [6:0] seg5, 18 | output [6:0] seg6, //hex segments 19 | output [7:0] readingAddress, //instruction address output 20 | output runningLED 21 | ); 22 | 23 | wire contCLK; //controlled Clock (1Hz) 24 | reg [7:0] regWrite; //regWrite 25 | reg [7:0] pc; //pc value 26 | assign readingAddress = pc; 27 | reg [7:0] data[31:0]; //data memory 28 | reg [7:0] registers[3:0]; //4 registers 29 | reg [5:0] counting; 30 | reg [7:0] display1 = 8'b00000000; 31 | reg [7:0] display2 = 8'b00000000; 32 | eg [7:0] readData; 33 | wire [4:0] showButton; 34 | assign showButton = {showReg0, showReg1, showReg2, showReg3, showPC}; 35 | 36 | FrequencyDivider freqdiv (.CLKin(CLK), .clr(reset), .CLKout(contCLK)); 37 | HextoBCD HBCD1 (.bcd(regWrite[7:4]), .segout(seg1)); 38 | HextoBCD HBCD2 (.bcd(regWrite[3:0]), .segout(seg2)); 39 | HextoBCD HBCD3 (.bcd(display1[7:4]), .segout(seg3)); 40 | HextoBCD HBCD4 (.bcd(display1[3:0]), .segout(seg4)); 41 | HextoBCD HBCD5 (.bcd(display2[7:4]), .segout(seg5)); 42 | HextoBCD HBCD6 (.bcd(display2[3:0]), .segout(seg6)); 43 | 44 | initial begin 45 | pc = 8'b00000000; 46 | for(counting = 0; counting < 32; counting = counting + 1) begin 47 | data[counting] = counting[3:0]; 48 | end 49 | end 50 | 51 | assign runningLED = contCLK; 52 | 53 | always @(showData) begin 54 | display2 = data[showData]; 55 | end 56 | 57 | always @(showButton) begin 58 | case(showButton) 59 | 5'b10000 : display1 = registers[0]; 60 | 5'b01000 : display1 = registers[1]; 61 | 5'b00100 : display1 = registers[2]; 62 | 5'b00010 : display1 = registers[3]; 63 | default : display1 = pc; 64 | endcase 65 | end 66 | 67 | always @(posedge reset or posedge contCLK) begin 68 | if(reset == 1'b1) begin //reset 69 | pc = 8'b00000000; 70 | for(counting = 0; counting < 4; counting = counting + 1) begin 71 | registers[counting] = 8'b00000000; 72 | end 73 | for(counting = 0; counting < 32; counting = counting + 1) begin 74 | data[counting] = counting[3:0]; 75 | end 76 | end 77 | else begin 78 | case(instruction[7:6]) 79 | 2'b00 : begin //add 80 | registers[instruction[1:0]] = registers[instruction[3:2]] + registers[instruction[5:4]]; 81 | regWrite = registers[instruction[1:0]]; 82 | pc = pc + 1; 83 | DCLED = 1'b1; 84 | end 85 | 2'b01 : begin //load 86 | registers[instruction[3:2]] = data[registers[instruction[5:4]] + instruction[1:0]]; 87 | regWrite = registers[instruction[3:2]]; 88 | pc = pc + 1; 89 | DCLED = 1'b1; 90 | end 91 | 2'b10 : begin //store 92 | data[registers[instruction[5:4]] + instruction[1:0]] = registers[instruction[3:2]]; 93 | pc = pc + 1; 94 | DCLED = 1'b0; 95 | end 96 | 2'b11 : begin //jump 97 | case(instruction[1:0]) 98 | 2'b00 : pc = pc + 1; 99 | 2'b01 : pc = pc + 2; 100 | 2'b10 : pc = pc - 1; 101 | 2'b11 : pc = pc; 102 | endcase 103 | DCLED = 1'b0; 104 | end 105 | endcase 106 | end 107 | end 108 | endmodule 109 | 110 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/FinalProject_summary.html: -------------------------------------------------------------------------------- 1 | Xilinx Design Summary 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 |
FinalProject Project Status
Project File:FinalProject.xiseParser Errors: No Errors
Module Name:FinalProjectImplementation State:New
Target Device:xc3s50an-4tqg144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 34 |  
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 |  
61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 |
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
72 |  
73 | 74 | 75 |
Secondary Reports [-]
Report NameStatusGenerated
76 | 77 | 78 |
Date Generated: 06/13/2018 - 18:49:48
79 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/FrequencyDivider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module FrequencyDivider( 3 | input CLKin, 4 | input clr, 5 | output reg CLKout 6 | ); 7 | reg [31:0] cnt; 8 | always @(posedge CLKin) begin 9 | if(clr) begin 10 | cnt <= 32'd0; 11 | CLKout <= 1'b0; 12 | end 13 | else if(cnt == 32'd25000000) begin 14 | cnt <= 32'd0; 15 | CLKout <= ~CLKout; 16 | end 17 | else begin 18 | cnt <= cnt+1; 19 | end 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/HextoBCD.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module HextoBCD( 3 | input [3:0] bcd, 4 | output [6:0] segout 5 | ); 6 | reg [6:0] seg; 7 | assign segout = seg; 8 | 9 | always @(bcd) begin 10 | case(bcd) 11 | 4'b0000: seg = 7'b0111111; 12 | 4'b0001: seg = 7'b0000110; 13 | 4'b0010: seg = 7'b1011011; 14 | 4'b0011: seg = 7'b1001111; 15 | 4'b0100: seg = 7'b1100110; 16 | 4'b0101: seg = 7'b1101101; 17 | 4'b0110: seg = 7'b1111101; 18 | 4'b0111: seg = 7'b0000111; 19 | 4'b1000: seg = 7'b1111111; 20 | 4'b1001: seg = 7'b1101111; 21 | 4'b1010: seg = 7'b1110111; 22 | 4'b1011: seg = 7'b1111100; 23 | 4'b1100: seg = 7'b0111001; 24 | 4'b1101: seg = 7'b1011110; 25 | 4'b1110: seg = 7'b1111001; 26 | 4'b1111: seg = 7'b1110001; 27 | endcase 28 | end 29 | endmodule 30 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/IMEM.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IMEM( 4 | output [7:0] Instruction, 5 | input [7:0] Read_Address 6 | ); 7 | 8 | wire [7:0] MemByte[20:0]; 9 | 10 | assign MemByte[0] = 8'b01000100; 11 | assign MemByte[1] = 8'b01001001; 12 | assign MemByte[2] = 8'b00011001; 13 | assign MemByte[3] = 8'b10000100; 14 | 15 | assign MemByte[4] = 8'b01000100; 16 | assign MemByte[5] = 8'b01001001; 17 | assign MemByte[6] = 8'b00011001; 18 | assign MemByte[7] = 8'b10000100; 19 | 20 | assign MemByte[8] = 8'b01000100; 21 | assign MemByte[9] = 8'b01001001; 22 | assign MemByte[10] = 8'b00011001; 23 | assign MemByte[11] = 8'b10000100; 24 | 25 | assign MemByte[12] = 8'b01000100; 26 | assign MemByte[13] = 8'b01001001; 27 | assign MemByte[14] = 8'b00011001; 28 | assign MemByte[15] = 8'b10000100; 29 | 30 | assign MemByte[16] = 8'b01000100; 31 | assign MemByte[17] = 8'b01001001; 32 | assign MemByte[18] = 8'b00011001; 33 | assign MemByte[19] = 8'b10000100; 34 | 35 | assign MemByte[20] = 8'b11000011; 36 | 37 | assign Instruction = MemByte[Read_Address]; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/IMEM_description.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sally20921/LogicDesignFinalProject/4c977a51b982e72442359df8b4bcabcd34917f79/LD-Final-Project/FinalProject/IMEM_description.pdf -------------------------------------------------------------------------------- /LD-Final-Project/FinalProject/TestingModule.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | ////////////////////////////////////////////////////////////////////////////////// 3 | // Company: 4 | // Engineer: 5 | // 6 | // Create Date: 19:05:07 06/13/2018 7 | // Design Name: 8 | // Module Name: TestingModule 9 | // Project Name: 10 | // Target Devices: 11 | // Tool versions: 12 | // Description: 13 | // 14 | // Dependencies: 15 | // 16 | // Revision: 17 | // Revision 0.01 - File Created 18 | // Additional Comments: 19 | // 20 | ////////////////////////////////////////////////////////////////////////////////// 21 | module TestingModule( 22 | input [7:0] Read_Address, 23 | output [7:0] Instruction 24 | ); 25 | 26 | wire [7:0] MemByte[5:0]; // 27 | 28 | // OPERATION TEST SET // 29 | // lw $s1, 0($s0)s 30 | assign MemByte[0] = { 2'b01, 2'b00, 2'b01, 2'b00 }; 31 | 32 | // lw $s2, 1($s0) 33 | assign MemByte[1] = { 2'b01, 2'b00, 2'b10, 2'b01 }; 34 | 35 | // add $s0, $s1, $s2 36 | assign MemByte[2] = { 2'b00, 2'b01, 2'b10, 2'b00 }; 37 | 38 | // sw $s2, 1($s0) 39 | assign MemByte[3] = { 2'b10, 2'b00, 2'b10, 2'b01 }; 40 | 41 | // j -1 42 | assign MemByte[4] = { 2'b11, 4'b0000, 2'b11 }; 43 | 44 | // Assign address 45 | assign Instruction = MemByte[Read_Address]; 46 | 47 | 48 | endmodule -------------------------------------------------------------------------------- /LD-Final-Project/README.md: -------------------------------------------------------------------------------- 1 | # Login Degisn Final Project 2 | 2018 Spring Logic Design Final Project 3 | 4 | Microprocessor Design 5 | 6 | SNUCSE 17 Sungchan Yi, Dongwoo Kim 7 | -------------------------------------------------------------------------------- /Microprocessor/ALU.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ALU( 4 | input [7:0] operand1, 5 | input [7:0] operand2, 6 | output [7:0] result 7 | ); 8 | 9 | assign result = operand1 + operand2; 10 | endmodule 11 | -------------------------------------------------------------------------------- /Microprocessor/ClockDivider.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ClockDivider( 4 | input clk_in, 5 | input reset, 6 | output reg clk_out 7 | ); 8 | 9 | reg [31:0] cnt; 10 | 11 | initial begin 12 | clk_out <= 1'b0; 13 | cnt <= 0; 14 | end 15 | 16 | always @(posedge reset or posedge clk_in) begin 17 | if (reset) begin 18 | clk_out <= 1'b0; 19 | cnt <= 0; 20 | end else if (cnt >= 32'd25000000) begin 21 | // end else if (cnt >= 32'd10) begin 22 | cnt <= 32'b0; 23 | clk_out <= ~clk_out; 24 | end else begin 25 | cnt <= cnt + 1; 26 | end 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /Microprocessor/Control.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Control( 4 | input [1:0] op, 5 | output reg_dst, 6 | output reg_write, 7 | output alu_src, 8 | output branch, 9 | output mem_read, 10 | output mem_write, 11 | output mem_to_reg, 12 | output alu_op 13 | ); 14 | 15 | wire [7:0] out; 16 | assign {reg_dst, reg_write, alu_src, branch, mem_read, mem_write, mem_to_reg, alu_op} = out; 17 | 18 | assign out = op == 2'b00 ? 8'b11000001 : // 11000001 19 | op == 2'b01 ? 8'b01101010 : // 01101010 20 | op == 2'b10 ? 8'b00100100 : // x01001x0 21 | 8'b00010000; // x00100x0 22 | endmodule 23 | -------------------------------------------------------------------------------- /Microprocessor/ControlTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module ControlTest; 4 | reg [1:0] op; 5 | wire reg_dst; 6 | wire reg_write; 7 | wire alu_src; 8 | wire branch; 9 | wire mem_read; 10 | wire mem_write; 11 | wire mem_to_reg; 12 | wire alu_op; 13 | 14 | Control uut ( 15 | .op(op), 16 | .reg_dst(reg_dst), 17 | .reg_write(reg_write), 18 | .alu_src(alu_src), 19 | .branch(branch), 20 | .mem_read(mem_read), 21 | .mem_write(mem_write), 22 | .mem_to_reg(mem_to_reg), 23 | .alu_op(alu_op) 24 | ); 25 | 26 | initial begin 27 | op = 0; 28 | end 29 | 30 | always begin 31 | #100; 32 | op <= op + 1; 33 | end 34 | endmodule 35 | 36 | -------------------------------------------------------------------------------- /Microprocessor/DataMemory.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DataMemory( 4 | input clk, 5 | input reset, 6 | input [7:0] address, 7 | input write, 8 | input [7:0] data_inputs, 9 | output [7:0] data_outputs 10 | ); 11 | 12 | reg [7:0] registers[31:0]; 13 | integer i; 14 | 15 | assign data_outputs = registers[address[4:0]]; 16 | 17 | initial begin 18 | for (i = 0; i < 16; i = i + 1) begin 19 | registers[i] <= i; 20 | end 21 | for (i = 0; i < 16; i = i + 1) begin 22 | registers[i + 16] <= -i; 23 | end 24 | end 25 | 26 | always @(posedge reset or posedge clk) begin 27 | if (reset) begin 28 | for (i = 0; i < 16; i = i + 1) begin 29 | registers[i] <= i; 30 | end 31 | for (i = 0; i < 16; i = i + 1) begin 32 | registers[i + 16] <= -i; 33 | end 34 | end else begin 35 | if (write) 36 | registers[address[4:0]] <= data_inputs; 37 | end 38 | end 39 | endmodule 40 | -------------------------------------------------------------------------------- /Microprocessor/DataMemoryTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module DataMemoryTest; 4 | reg clk; 5 | reg reset; 6 | reg [7:0] address; 7 | reg write; 8 | reg [7:0] data_inputs; 9 | wire [7:0] data_outputs; 10 | 11 | DataMemory uut ( 12 | .clk(clk), 13 | .reset(reset), 14 | .address(address), 15 | .write(write), 16 | .data_inputs(data_inputs), 17 | .data_outputs(data_outputs) 18 | ); 19 | 20 | initial begin 21 | clk = 0; 22 | reset = 0; 23 | address = 0; 24 | write = 0; 25 | data_inputs = 0; 26 | 27 | #100; 28 | 29 | address = 8'b00000010; 30 | data_inputs = 8'b01010101; 31 | write = 1; 32 | clk = 1; 33 | #50; 34 | clk = 0; 35 | #50; 36 | 37 | address = 8'b00001010; 38 | data_inputs = 8'b11001100; 39 | write = 1; 40 | clk = 1; 41 | #50; 42 | clk = 0; 43 | #50; 44 | 45 | address = 8'b00000010; 46 | write = 0; 47 | clk = 1; 48 | #50; 49 | clk = 0; 50 | #50; 51 | 52 | address = 8'b00001010; 53 | write = 0; 54 | clk = 1; 55 | #50; 56 | clk = 0; 57 | #50; 58 | end 59 | endmodule 60 | -------------------------------------------------------------------------------- /Microprocessor/HexDecoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module HexDecoder( 4 | input [3:0] bcd, 5 | output [6:0] seg 6 | ); 7 | 8 | assign seg = bcd == 4'd0 ? 7'b0111111 : 9 | bcd == 4'd1 ? 7'b0000110 : 10 | bcd == 4'd2 ? 7'b1011011 : 11 | bcd == 4'd3 ? 7'b1001111 : 12 | bcd == 4'd4 ? 7'b1100110 : 13 | bcd == 4'd5 ? 7'b1101101 : 14 | bcd == 4'd6 ? 7'b1111101 : 15 | bcd == 4'd7 ? 7'b0000111 : 16 | bcd == 4'd8 ? 7'b1111111 : 17 | bcd == 4'd9 ? 7'b1101111 : 18 | bcd == 4'd10 ? 7'b1110111 : 19 | bcd == 4'd11 ? 7'b1111100 : 20 | bcd == 4'd12 ? 7'b0111001 : 21 | bcd == 4'd13 ? 7'b1011110 : 22 | bcd == 4'd14 ? 7'b1111001 : 23 | 7'b1110001; 24 | endmodule 25 | -------------------------------------------------------------------------------- /Microprocessor/IntegrationTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module IntegrationTest; 4 | reg origclk; 5 | reg reset; 6 | reg [7:0] instruction; 7 | wire [7:0] pc; 8 | wire [6:0] display_low; 9 | wire [6:0] display_high; 10 | wire [6:0] display_op; 11 | wire [6:0] display_rs; 12 | wire [6:0] display_rt; 13 | wire [6:0] display_rd; 14 | wire [4:0] display_pc; 15 | wire display_clock; 16 | 17 | wire [7:0] MemByte[20:0]; 18 | 19 | assign MemByte[0] = 8'b01000100; 20 | assign MemByte[1] = 8'b01001001; 21 | assign MemByte[2] = 8'b00011001; 22 | assign MemByte[3] = 8'b10000100; 23 | 24 | assign MemByte[4] = 8'b01000100; 25 | assign MemByte[5] = 8'b01001001; 26 | assign MemByte[6] = 8'b00011001; 27 | assign MemByte[7] = 8'b10000100; 28 | 29 | assign MemByte[8] = 8'b01000100; 30 | assign MemByte[9] = 8'b01001001; 31 | assign MemByte[10] = 8'b00011001; 32 | assign MemByte[11] = 8'b10000100; 33 | 34 | assign MemByte[12] = 8'b01000100; 35 | assign MemByte[13] = 8'b01001001; 36 | assign MemByte[14] = 8'b00011001; 37 | assign MemByte[15] = 8'b10000100; 38 | 39 | assign MemByte[16] = 8'b01000100; 40 | assign MemByte[17] = 8'b01001001; 41 | assign MemByte[18] = 8'b00011001; 42 | assign MemByte[19] = 8'b10000100; 43 | 44 | assign MemByte[20] = 8'b11000011; 45 | 46 | Microprocessor uut ( 47 | .origclk(origclk), 48 | .reset(reset), 49 | .instruction(instruction), 50 | .pc(pc), 51 | .display_low(display_low), 52 | .display_high(display_high), 53 | .display_op(display_op), 54 | .display_rs(display_rs), 55 | .display_rt(display_rt), 56 | .display_rd(display_rd), 57 | .display_pc(display_pc), 58 | .display_clock(display_clock) 59 | ); 60 | 61 | initial begin 62 | origclk = 0; 63 | instruction = MemByte[0]; 64 | reset = 0; 65 | #10; 66 | reset = 1; 67 | #10; 68 | reset = 0; 69 | end 70 | 71 | always begin 72 | origclk = 1; 73 | #1; 74 | origclk = 0; 75 | #1; 76 | end 77 | 78 | always @(pc) begin 79 | instruction <= MemByte[pc]; 80 | end 81 | endmodule 82 | -------------------------------------------------------------------------------- /Microprocessor/Microprocessor.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Microprocessor( 4 | input origclk, 5 | input reset, 6 | input [7:0] instruction, 7 | output reg [7:0] pc, 8 | output [6:0] display_low, 9 | output [6:0] display_high, 10 | output [6:0] display_op, 11 | output [6:0] display_rs, 12 | output [6:0] display_rt, 13 | output [6:0] display_rd, 14 | output [4:0] display_pc, 15 | output display_clock 16 | ); 17 | 18 | wire [1:0] op = instruction[7:6]; 19 | wire [1:0] rs = instruction[5:4]; 20 | wire [1:0] rt = instruction[3:2]; 21 | wire [1:0] rd = instruction[1:0]; 22 | wire [7:0] imm = { 23 | instruction[1], 24 | instruction[1], 25 | instruction[1], 26 | instruction[1], 27 | instruction[1], 28 | instruction[1], 29 | instruction[1], 30 | instruction[0] 31 | }; 32 | 33 | wire clk; 34 | 35 | wire reg_dst; 36 | wire reg_write; 37 | wire alu_src; 38 | wire branch; 39 | wire mem_read; 40 | wire mem_write; 41 | wire mem_to_reg; 42 | wire alu_op; 43 | 44 | wire [7:0] reg_data1; 45 | wire [7:0] reg_data2; 46 | 47 | wire [7:0] alu_result; 48 | wire [7:0] alu_operand2 = 49 | alu_src == 0 50 | ? reg_data2 51 | : imm; 52 | 53 | wire [7:0] memory_output; 54 | 55 | wire [1:0] reg_write_reg = 56 | reg_dst == 0 57 | ? rt 58 | : rd; 59 | wire [7:0] reg_write_data = 60 | mem_to_reg == 0 61 | ? alu_result 62 | : memory_output; 63 | 64 | reg [7:0] display_write_data; 65 | assign display_pc = pc; 66 | assign display_clock = clk; 67 | 68 | ClockDivider divider( 69 | .clk_in(origclk), 70 | .reset(reset), 71 | .clk_out(clk) 72 | ); 73 | 74 | Control control( 75 | .op(op), 76 | .reg_dst(reg_dst), 77 | .reg_write(reg_write), 78 | .alu_src(alu_src), 79 | .branch(branch), 80 | .mem_read(mem_read), 81 | .mem_write(mem_write), 82 | .mem_to_reg(mem_to_reg), 83 | .alu_op(alu_op) 84 | ); 85 | 86 | Registers registers( 87 | .clk(clk), 88 | .reset(reset), 89 | .read_reg1(rs), 90 | .read_reg2(rt), 91 | .write(reg_write), 92 | .write_reg(reg_write_reg), 93 | .write_data(reg_write_data), 94 | .read_data1(reg_data1), 95 | .read_data2(reg_data2) 96 | ); 97 | 98 | HexDecoder ssdecoder_high( 99 | .bcd(display_write_data[3:0]), 100 | .seg(display_low) 101 | ); 102 | HexDecoder ssdecoder_low( 103 | .bcd(display_write_data[7:4]), 104 | .seg(display_high) 105 | ); 106 | OpDecoder ssdecoder_op( 107 | .op(op), 108 | .seg(display_op) 109 | ); 110 | HexDecoder ssdecoder_rs( 111 | .bcd(rs), 112 | .seg(display_rs) 113 | ); 114 | HexDecoder ssdecoder_rt( 115 | .bcd(rt), 116 | .seg(display_rt) 117 | ); 118 | HexDecoder ssdecoder_rd( 119 | .bcd(rd), 120 | .seg(display_rd) 121 | ); 122 | 123 | ALU alu( 124 | .operand1(reg_data1), 125 | .operand2(alu_operand2), 126 | .result(alu_result) 127 | ); 128 | 129 | DataMemory memory( 130 | .clk(clk), 131 | .reset(reset), 132 | .address(alu_result), 133 | .write(mem_write), 134 | .data_inputs(reg_data2), 135 | .data_outputs(memory_output) 136 | ); 137 | 138 | initial begin 139 | pc = 0; 140 | display_write_data = 0; 141 | end 142 | 143 | always @(posedge reset or negedge clk) begin 144 | if (reset) 145 | pc <= 0; 146 | else 147 | pc <= 148 | branch == 0 149 | ? pc + 1 150 | : pc + 1 + imm; 151 | end 152 | 153 | always @(posedge reset or posedge clk) begin 154 | if (reset) 155 | display_write_data <= 0; 156 | else 157 | display_write_data <= reg_write_data; 158 | end 159 | endmodule 160 | -------------------------------------------------------------------------------- /Microprocessor/MicroprocessorWithTestInst.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module MicroprocessorWithTestInst( 4 | input origclk, 5 | input reset, 6 | input [7:0] instruction, 7 | output [7:0] pc, 8 | output [7:0] test_instruction, 9 | input [7:0] test_pc, 10 | output [6:0] display_low, 11 | output [6:0] display_high, 12 | output [6:0] display_op, 13 | output [6:0] display_rs, 14 | output [6:0] display_rt, 15 | output [6:0] display_rd, 16 | output [5:0] display_pc 17 | ); 18 | 19 | Microprocessor processer( 20 | .origclk(origclk), 21 | .reset(reset), 22 | .instruction(instruction), 23 | .pc(pc), 24 | .display_low(display_low), 25 | .display_high(display_high), 26 | .display_pc(display_pc), 27 | .display_op(display_op), 28 | .display_rs(display_rs), 29 | .display_rt(display_rt), 30 | .display_rd(display_rd) 31 | ); 32 | 33 | wire [7:0] MemByte[20:0]; 34 | 35 | assign MemByte[0] = 8'b01000100; 36 | assign MemByte[1] = 8'b01001001; 37 | assign MemByte[2] = 8'b00011001; 38 | assign MemByte[3] = 8'b10000100; 39 | 40 | assign MemByte[4] = 8'b01000100; 41 | assign MemByte[5] = 8'b01001001; 42 | assign MemByte[6] = 8'b00011001; 43 | assign MemByte[7] = 8'b10000100; 44 | 45 | assign MemByte[8] = 8'b01000100; 46 | assign MemByte[9] = 8'b01001001; 47 | assign MemByte[10] = 8'b00011001; 48 | assign MemByte[11] = 8'b10000100; 49 | 50 | assign MemByte[12] = 8'b01000100; 51 | assign MemByte[13] = 8'b01001001; 52 | assign MemByte[14] = 8'b00011001; 53 | assign MemByte[15] = 8'b10000100; 54 | 55 | assign MemByte[16] = 8'b01000100; 56 | assign MemByte[17] = 8'b01001001; 57 | assign MemByte[18] = 8'b00011001; 58 | assign MemByte[19] = 8'b10000100; 59 | 60 | assign MemByte[20] = 8'b11000011; 61 | 62 | assign test_instruction = MemByte[test_pc]; 63 | endmodule 64 | -------------------------------------------------------------------------------- /Microprocessor/OpDecoder.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module OpDecoder( 4 | input [1:0] op, 5 | output reg [6:0] seg 6 | ); 7 | 8 | always @(op) begin 9 | case (op) 10 | 2'd0: seg <= 7'b1110111; // A 11 | 2'd1: seg <= 7'b0111000; // L 12 | 2'd2: seg <= 7'b1101101; // S 13 | 2'd3: seg <= 7'b0001110; // J 14 | endcase 15 | end 16 | endmodule 17 | 18 | -------------------------------------------------------------------------------- /Microprocessor/Registers.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module Registers( 4 | input clk, 5 | input reset, 6 | input [1:0] read_reg1, 7 | input [1:0] read_reg2, 8 | input write, 9 | input [1:0] write_reg, 10 | input [7:0] write_data, 11 | output [7:0] read_data1, 12 | output [7:0] read_data2 13 | ); 14 | 15 | reg [7:0] registers[3:0]; 16 | integer i; 17 | 18 | assign read_data1 = registers[read_reg1]; 19 | assign read_data2 = registers[read_reg2]; 20 | 21 | initial begin 22 | for (i = 0; i < 4; i = i + 1) 23 | registers[i] <= 0; 24 | end 25 | 26 | always @(posedge reset or posedge clk) begin 27 | if (reset) begin 28 | for (i = 0; i < 4; i = i + 1) 29 | registers[i] <= 0; 30 | end else begin 31 | if (write) 32 | registers[write_reg] <= write_data; 33 | end 34 | end 35 | endmodule 36 | -------------------------------------------------------------------------------- /Microprocessor/RegistersTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module RegistersTest; 4 | reg clk; 5 | reg reset; 6 | reg [1:0] read_reg1; 7 | reg [1:0] read_reg2; 8 | reg write; 9 | reg [1:0] write_reg; 10 | reg [7:0] write_data; 11 | 12 | wire [7:0] read_data1; 13 | wire [7:0] read_data2; 14 | 15 | Registers uut ( 16 | .clk(clk), 17 | .reset(reset), 18 | .read_reg1(read_reg1), 19 | .read_reg2(read_reg2), 20 | .write(write), 21 | .write_reg(write_reg), 22 | .write_data(write_data), 23 | .read_data1(read_data1), 24 | .read_data2(read_data2) 25 | ); 26 | 27 | initial begin 28 | read_reg1 = 0; 29 | read_reg2 = 0; 30 | write = 0; 31 | write_reg = 0; 32 | write_data = 0; 33 | reset = 1; 34 | clk = 0; 35 | #50; 36 | reset = 0; 37 | clk = 1; 38 | #50; 39 | clk = 0; 40 | #50; 41 | 42 | write_reg = 2'b10; 43 | write_data = 8'b01010101; 44 | write = 1; 45 | clk = 1; 46 | #50; 47 | clk = 0; 48 | #50; 49 | 50 | read_reg1 = 2'b11; 51 | write_reg = 2'b11; 52 | write_data = 8'b11001100; 53 | write = 1; 54 | clk = 1; 55 | #50; 56 | clk = 0; 57 | #50; 58 | 59 | read_reg2 = 2'b11; 60 | write = 0; 61 | clk = 1; 62 | #50; 63 | clk = 0; 64 | #50; 65 | end 66 | endmodule 67 | 68 | -------------------------------------------------------------------------------- /Microprocessor/TestProcessorTest.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | module TestProcessorTest; 4 | reg origclk; 5 | reg reset; 6 | reg [7:0] instruction; 7 | reg [7:0] test_pc; 8 | 9 | wire [7:0] pc; 10 | wire [7:0] test_instruction; 11 | wire [6:0] display_low; 12 | wire [6:0] display_high; 13 | wire [6:0] display_op; 14 | wire [6:0] display_rs; 15 | wire [6:0] display_rt; 16 | wire [6:0] display_rd; 17 | wire [5:0] display_pc; 18 | 19 | MicroprocessorWithTestInst uut ( 20 | .origclk(origclk), 21 | .reset(reset), 22 | .instruction(instruction), 23 | .pc(pc), 24 | .test_instruction(test_instruction), 25 | .test_pc(test_pc), 26 | .display_low(display_low), 27 | .display_high(display_high), 28 | .display_op(display_op), 29 | .display_rs(display_rs), 30 | .display_rt(display_rt), 31 | .display_rd(display_rd), 32 | .display_pc(display_pc) 33 | ); 34 | 35 | initial begin 36 | origclk = 0; 37 | reset = 0; 38 | instruction = 0; 39 | test_pc = 0; 40 | #10; 41 | reset = 1; 42 | #10; 43 | reset = 0; 44 | end 45 | 46 | always begin 47 | origclk = 1; 48 | #1; 49 | origclk = 0; 50 | #1; 51 | end 52 | 53 | always @(pc) begin 54 | test_pc <= pc; 55 | end 56 | 57 | always @(test_instruction) begin 58 | instruction <= test_instruction; 59 | end 60 | endmodule 61 | 62 | -------------------------------------------------------------------------------- /stopwatch_verilog/README.md: -------------------------------------------------------------------------------- 1 | # Implement stopwatch with verilog HDL 2 | 3 | This article is a wiki about the stopwatch implemented using verilog HDL. 4 | 5 | _ChoYG_ 6 | whdlgp@gmail.com 7 | 8 | Seoultech 9 | 10 | ## A summary diagram of the status of the stopwatch 11 | ![](http://i.imgur.com/B7xNtIz.png) 12 | 13 | ## Wiki 14 | 15 | [Home](https://github.com/whdlgp/stopwatch_verilog/wiki) 16 | -------------------------------------------------------------------------------- /stopwatch_verilog/bin2bcd.v: -------------------------------------------------------------------------------- 1 | module bin2bcd 2 | ( 3 | input [7:0] binary, 4 | output reg [3:0] Hundreds, 5 | output reg [3:0] Tens, 6 | output reg [3:0] Ones 7 | ); 8 | 9 | integer i; 10 | 11 | always @(binary) 12 | begin 13 | Hundreds = 4'b0; 14 | Tens = 4'b0; 15 | Ones = 4'b0; 16 | 17 | for(i=7; i>=0; i=i-1) 18 | begin 19 | if(Hundreds >= 5) 20 | Hundreds = Hundreds + 3; 21 | if(Tens >= 5) 22 | Tens = Tens + 3; 23 | if(Ones >= 5) 24 | Ones = Ones + 3; 25 | 26 | Hundreds = Hundreds << 1; 27 | Hundreds[0] = Tens[3]; 28 | Tens = Tens << 1; 29 | Tens[0] = Ones[3]; 30 | Ones = Ones << 1; 31 | Ones[0] = binary[i]; 32 | end 33 | end 34 | 35 | endmodule -------------------------------------------------------------------------------- /stopwatch_verilog/buttonStateMachine.v: -------------------------------------------------------------------------------- 1 | module buttonStateMachine 2 | ( 3 | input mclk, 4 | 5 | input b0, 6 | input b1, 7 | input b2, 8 | input reset, 9 | 10 | output run, 11 | 12 | output b1pos, 13 | output b2pos, 14 | output resetAll 15 | ); 16 | 17 | //버튼 시간지연을 이용한 디바운싱, positive edge 감지 18 | 19 | reg b0Delayed0 = 1'b0; 20 | reg b0Delayed1 = 1'b0; 21 | reg b0Delayed2 = 1'b0; 22 | wire posedgeDetect0; 23 | 24 | reg rsDelayed0 = 1'b0; 25 | reg rsDelayed1 = 1'b0; 26 | reg rsDelayed2 = 1'b0; 27 | wire posedgeDetectrs; 28 | 29 | //디바운싱 30 | always @(posedge mclk) 31 | begin 32 | rsDelayed0 <= reset; 33 | rsDelayed1 <= rsDelayed0; 34 | rsDelayed2 <= rsDelayed1; 35 | 36 | if(rsDelayed2 == 1'b1) 37 | begin 38 | b0Delayed0 <= 1'b0; 39 | b0Delayed1 <= 1'b0; 40 | b0Delayed2 <= 1'b0; 41 | end 42 | else 43 | begin 44 | b0Delayed0 <= b0; 45 | b0Delayed1 <= b0Delayed0; 46 | b0Delayed2 <= b0Delayed1; 47 | end 48 | end 49 | //디바운싱 end 50 | 51 | //positive edge 감지 52 | assign posedgeDetect0 = ~b0Delayed2 & b0Delayed1; 53 | //positive edge 감지 end 54 | 55 | //나머지 버튼은 그대로 출력 56 | assign b1pos = b1; 57 | assign b2pos = b2; 58 | 59 | //버튼 시간지연을 이용한 디바운싱, positive edge 감지 end 60 | 61 | reg runState = 1'b0; 62 | 63 | always @(posedge mclk) 64 | begin 65 | if(rsDelayed2 == 1'b1) 66 | begin 67 | runState <= 1'b0; 68 | end 69 | else 70 | begin 71 | if(posedgeDetect0) //RUN, STOP 상태 결정 72 | begin 73 | runState <= ~runState; 74 | end 75 | end 76 | end 77 | 78 | assign run = runState; //RUN STOP 상태 토글되서 출력 79 | assign resetAll = rsDelayed2; //디바운싱 되서 모두 리셋 출력 80 | 81 | endmodule -------------------------------------------------------------------------------- /stopwatch_verilog/ledbar.v: -------------------------------------------------------------------------------- 1 | module ledbar 2 | ( 3 | input mclk, 4 | 5 | input b1, 6 | input reset, 7 | input run, 8 | 9 | output reg [3:0] led = 4'b0000 10 | ); 11 | 12 | //디바운싱, 엣지 검출용 13 | reg b1Delayed0 = 1'b0; 14 | reg b1Delayed1 = 1'b0; 15 | reg b1Delayed2 = 1'b0; 16 | wire posedgeDetect1; 17 | 18 | //positive edge 감지 19 | assign posedgeDetect1 = ~b1Delayed2 & b1Delayed1; 20 | //positive edge 감지 end 21 | 22 | //분주용 23 | reg [19:0] clk100hz = 20'h0_0000; 24 | 25 | reg [2:0] ledState = 3'h0; 26 | 27 | always @(posedge mclk) 28 | begin 29 | if(reset == 1'b1) 30 | begin 31 | led <= 4'b0000; 32 | clk100hz <= 20'h0_0000; 33 | ledState <= 3'h0; 34 | 35 | b1Delayed0 <= 1'b0; 36 | b1Delayed1 <= 1'b0; 37 | b1Delayed2 <= 1'b0; 38 | end 39 | else 40 | begin 41 | //디바운싱, 엣지 검출 42 | b1Delayed0 <= b1; 43 | b1Delayed1 <= b1Delayed0; 44 | b1Delayed2 <= b1Delayed1; 45 | //디바운싱, 엣지 검출 end 46 | 47 | if(run == 1'b1) 48 | begin 49 | clk100hz <= clk100hz + 20'h0_0001; 50 | if(clk100hz >= 20'h3_0D40) //실제 돌릴때 30D40, 시뮬레이션 4E20, 0.2초마다 51 | begin 52 | clk100hz <= 20'h0_0000; 53 | 54 | case (ledState[2:0]) 55 | 3'h0: 56 | begin 57 | led <= 4'b0001; 58 | ledState <= 3'h1; 59 | end 60 | 3'h1: 61 | begin 62 | led <= 4'b0011; 63 | ledState <= 3'h2; 64 | end 65 | 3'h2: 66 | begin 67 | led <= 4'b0111; 68 | ledState <= 3'h3; 69 | end 70 | 3'h3: 71 | begin 72 | led <= 4'b1111; 73 | ledState <= 3'h4; 74 | end 75 | default: 76 | begin 77 | led <= 4'b0000; 78 | ledState <= 3'h0; 79 | end 80 | endcase 81 | end 82 | end 83 | else 84 | begin 85 | if(posedgeDetect1) 86 | begin 87 | led <= 4'b0000; 88 | clk100hz <= 20'h0_0000; 89 | ledState <= 3'h0; 90 | end 91 | end 92 | end 93 | end 94 | 95 | endmodule -------------------------------------------------------------------------------- /stopwatch_verilog/seg7Display.v: -------------------------------------------------------------------------------- 1 | module seg7Display 2 | ( 3 | input mclk, 4 | input reset, 5 | 6 | input run, 7 | input b2Posedge, 8 | 9 | input [7:0] min, //분 10 | input [7:0] sec, //초 11 | input [7:0] mil, //0.01초단위 12 | 13 | output [6:0] minHigh, //분단위 10자리 수 14 | output [6:0] minLow, //분단위 1자리 수 15 | 16 | output [6:0] secHigh, //초단위 10자리 수 17 | output [6:0] secLow, //초단위 1자리 수 18 | 19 | output [6:0] milHigh, //0.1초 20 | output [6:0] milLow //0.01초 21 | ); 22 | 23 | reg laptimeState = 1'b0; //상태 저장용 24 | reg [7:0] minBuf = 8'b0000_0000; //분 단위 한번 저장용 25 | reg [7:0] secBuf = 8'b0000_0000; //초 단위 한번 저장용 26 | reg [7:0] milBuf = 8'b0000_0000; //0.01초 단위 한번 저장용 27 | 28 | //최종 출력용 29 | reg [7:0] outputMin = 8'b0000_0000; 30 | reg [7:0] outputSec = 8'b0000_0000; 31 | reg [7:0] outputMil = 8'b0000_0000; 32 | 33 | //디바운싱, 엣지 검출용 34 | reg b2Delayed0 = 1'b0; 35 | reg b2Delayed1 = 1'b0; 36 | reg b2Delayed2 = 1'b0; 37 | wire posedgeDetect2; 38 | 39 | //positive edge 감지 40 | assign posedgeDetect2 = ~b2Delayed2 & b2Delayed1; 41 | //positive edge 감지 end 42 | 43 | always @(posedge mclk) 44 | begin 45 | if(reset == 1'b1) 46 | begin 47 | laptimeState = 1'b0; //상태 저장용 48 | minBuf = 8'b0000_0000; //분 단위 한번 저장용 49 | secBuf = 8'b0000_0000; //초 단위 한번 저장용 50 | milBuf = 8'b0000_0000; //0.01초 단위 한번 저장용 51 | 52 | //최종 출력용 53 | outputMin = 8'b0000_0000; 54 | outputSec = 8'b0000_0000; 55 | outputMil = 8'b0000_0000; 56 | 57 | //디바운싱, 엣지 검출용 58 | b2Delayed0 = 1'b0; 59 | b2Delayed1 = 1'b0; 60 | b2Delayed2 = 1'b0; 61 | end 62 | else 63 | begin 64 | //디바운싱, 엣지 검출 65 | b2Delayed0 <= b2Posedge; 66 | b2Delayed1 <= b2Delayed0; 67 | b2Delayed2 <= b2Delayed1; 68 | //디바운싱, 엣지 검출 end 69 | if(posedgeDetect2 && (run == 1'b1)) 70 | begin 71 | laptimeState = 1'b1; 72 | minBuf[7:0] <= min[7:0]; 73 | secBuf[7:0] <= sec[7:0]; 74 | milBuf[7:0] <= mil[7:0]; 75 | end 76 | if((run == 1'b1) && (laptimeState == 1'b1)) //버퍼에 한번 저장된 시간 출력 77 | begin 78 | outputMin[7:0] <= minBuf[7:0]; 79 | outputSec[7:0] <= secBuf[7:0]; 80 | outputMil[7:0] <= milBuf[7:0]; 81 | end 82 | else if(run == 1'b0) //RUN상태가 아니면 LAPTIME 상태 초기화, 시간 그대로 출력 83 | begin 84 | laptimeState <= 1'b0; 85 | outputMin[7:0] <= min[7:0]; 86 | outputSec[7:0] <= sec[7:0]; 87 | outputMil[7:0] <= mil[7:0]; 88 | end 89 | else //그 이외에는 시간 그대로 출력만 함 90 | begin 91 | outputMin[7:0] <= min[7:0]; 92 | outputSec[7:0] <= sec[7:0]; 93 | outputMil[7:0] <= mil[7:0]; 94 | end 95 | end 96 | end 97 | 98 | seg7dec2 minseg(.val(outputMin), .highDigit(minHigh), .lowDigit(minLow)); //분단위 출력 99 | seg7dec2 secseg(.val(outputSec), .highDigit(secHigh), .lowDigit(secLow)); //초단위 출력 100 | seg7dec2 milseg(.val(outputMil), .highDigit(milHigh), .lowDigit(milLow)); //0.01초단위 출력 101 | 102 | endmodule -------------------------------------------------------------------------------- /stopwatch_verilog/seg7dec.v: -------------------------------------------------------------------------------- 1 | module seg7dec 2 | ( 3 | input [3:0] val, 4 | output reg [6:0] seg // from MSB {A, B, C, D, E, F, G} 5 | ); 6 | 7 | always @(*) 8 | begin 9 | case (val[3:0]) 10 | 4'h0: seg[6:0] = 7'b111_1110; 11 | 4'h1: seg[6:0] = 7'b011_0000; 12 | 4'h2: seg[6:0] = 7'b110_1101; 13 | 4'h3: seg[6:0] = 7'b111_1001; 14 | 4'h4: seg[6:0] = 7'b011_0011; 15 | 4'h5: seg[6:0] = 7'b101_1011; 16 | 4'h6: seg[6:0] = 7'b101_1111; 17 | 4'h7: seg[6:0] = 7'b111_0010; 18 | 4'h8: seg[6:0] = 7'b111_1111; 19 | 4'h9: seg[6:0] = 7'b111_1011; 20 | 4'hA: seg[6:0] = 7'b111_0111; 21 | 4'hB: seg[6:0] = 7'b111_1111; 22 | 4'hC: seg[6:0] = 7'b100_1110; 23 | 4'hD: seg[6:0] = 7'b111_1110; 24 | 4'hE: seg[6:0] = 7'b100_1111; 25 | default: seg[6:0] = 7'b100_0111; // 4'hF 26 | endcase 27 | end 28 | 29 | endmodule -------------------------------------------------------------------------------- /stopwatch_verilog/seg7dec2.v: -------------------------------------------------------------------------------- 1 | module seg7dec2 2 | ( 3 | input [7:0] val, 4 | output [6:0] highDigit, 5 | output [6:0] lowDigit 6 | ); 7 | 8 | wire [3:0] hundreds; 9 | wire [3:0] tens; 10 | wire [3:0] ones; 11 | 12 | bin2bcd bcd(.binary(val), .Hundreds(hundreds), .Tens(tens), .Ones(ones)); 13 | 14 | seg7dec high(.val(tens), .seg(highDigit)); 15 | seg7dec low(.val(ones), .seg(lowDigit)); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /stopwatch_verilog/timer.v: -------------------------------------------------------------------------------- 1 | module timer 2 | ( 3 | input mclk, 4 | input reset, 5 | 6 | input run, 7 | input b1Posedge, 8 | 9 | output reg [7:0] minute = 8'b0, 10 | output reg [7:0] second = 8'b0, 11 | output reg [7:0] ms10 = 8'b0 12 | ); 13 | 14 | //디바운싱, 엣지 검출용 15 | reg b1Delayed0 = 1'b0; 16 | reg b1Delayed1 = 1'b0; 17 | reg b1Delayed2 = 1'b0; 18 | wire posedgeDetect1; 19 | 20 | //positive edge 감지 21 | assign posedgeDetect1 = ~b1Delayed2 & b1Delayed1; 22 | //positive edge 감지 end 23 | 24 | //RESET 상태 저장용 25 | reg resetState = 1'b0; 26 | 27 | //분주용 28 | reg [19:0] clk100hz = 20'h0_0000; 29 | 30 | always @(posedge mclk) 31 | begin 32 | if(reset == 1'b1) //리셋신호 처리 33 | begin 34 | b1Delayed0 = 1'b0; 35 | b1Delayed1 = 1'b0; 36 | b1Delayed2 = 1'b0; 37 | 38 | resetState = 1'b0; 39 | 40 | clk100hz = 20'h0_0000; 41 | 42 | minute[7:0] <= 8'b0000_0000; 43 | second[7:0] <= 8'b0000_0000; 44 | ms10[7:0] <= 8'b0000_0000; 45 | end 46 | else 47 | begin 48 | //디바운싱, 엣지 검출 49 | b1Delayed0 <= b1Posedge; 50 | b1Delayed1 <= b1Delayed0; 51 | b1Delayed2 <= b1Delayed1; 52 | //디바운싱, 엣지 검출 end 53 | if((run == 1'b0) && posedgeDetect1) 54 | begin 55 | resetState <= 1'b1; 56 | end 57 | 58 | if((run == 1'b0) && (resetState == 1'b1)) //RESET상태일 경우 59 | begin 60 | minute[7:0] <= 8'b0000_0000; 61 | second[7:0] <= 8'b0000_0000; 62 | ms10[7:0] <= 8'b0000_0000; 63 | resetState <= 1'b0; 64 | clk100hz <= 20'h0_0000; 65 | end 66 | else if(run == 1'b1)//RUN 상태에서 67 | begin 68 | clk100hz <= clk100hz + 20'h0_0001; 69 | if(clk100hz >= 20'h0_2710) //실제 돌릴때 2710, 시뮬레이션 3E8, 0.01초마다 70 | begin 71 | clk100hz <= 20'h0_0000; 72 | if(minute == 8'b0110_0100) //100 73 | begin 74 | minute[7:0] <= 8'b0000_0000; 75 | end 76 | 77 | if(second == 8'b0011_1100) //60 78 | begin 79 | minute[7:0] <= minute[7:0] + 8'b1; 80 | second[7:0] <= 8'b0000_0000; 81 | end 82 | 83 | if(ms10 == 8'b0110_0011) //99 84 | begin 85 | second[7:0] <= second[7:0] + 8'b1; 86 | ms10[7:0] <= 8'b0000_0000; 87 | end 88 | else 89 | begin 90 | ms10[7:0] <= ms10[7:0] + 8'b1; 91 | end 92 | end 93 | end 94 | end 95 | end 96 | 97 | endmodule -------------------------------------------------------------------------------- /stopwatch_verilog/watch.v: -------------------------------------------------------------------------------- 1 | module watch 2 | ( 3 | input mclk, 4 | 5 | input b0, 6 | input b1, 7 | input b2, 8 | input reset, 9 | 10 | output [6:0] segMin1, //분단위 10자리 수 11 | output [6:0] segMin2, //분단위 1자리 수 12 | 13 | output [6:0] segSec1, //초단위 10자리 수 14 | output [6:0] segSec2, //초단위 1자리 수 15 | 16 | output [6:0] segmil1, //0.1초 17 | output [6:0] segmil2, //0.01초 18 | 19 | output [3:0] led 20 | ); 21 | 22 | wire runState; 23 | wire b1Posedge; 24 | wire b2Posedge; 25 | wire resetAll; 26 | 27 | wire resetin; 28 | assign resetin = ~reset; 29 | 30 | buttonStateMachine bsm( .mclk(mclk), .b0(b0), .b1(b1), .b2(b2), .reset(resetin) 31 | , .run(runState), .b1pos(b1Posedge), .b2pos(b2Posedge), .resetAll(resetAll)); 32 | 33 | 34 | wire [7:0] min; //분 35 | wire [7:0] sec; //초 36 | wire [7:0] mil; //0.01초단위 37 | 38 | timer gettimer( .mclk(mclk), .reset(resetAll) 39 | , .run(runState), .b1Posedge(b1Posedge) 40 | , .minute(min), .second(sec), .ms10(mil)); //분, 초, 0.01초 받음 41 | 42 | ledbar ledb(.mclk(mclk), .b1(b1Posedge), .reset(resetAll), .run(runState), .led(led)); 43 | 44 | seg7Display seg(.mclk(mclk), .reset(resetAll) 45 | , .run(runState), .b2Posedge(b2Posedge) //상태정보 46 | , .min(min), .sec(sec), .mil(mil) //시간 정보 47 | , .minHigh(segMin1), .minLow(segMin2) //출력할 디스플레이 48 | , .secHigh(segSec1), .secLow(segSec2) 49 | , .milHigh(segmil1), .milLow(segmil2)); 50 | 51 | endmodule --------------------------------------------------------------------------------