├── .gitignore
├── LICENSE
├── README.md
├── svm.sln
├── svm
├── common-includes.hpp
├── main.cpp
├── svm.vcxproj
├── svm.vcxproj.filters
├── svm.vcxproj.user
└── svm
│ ├── def
│ ├── cpu.hpp
│ ├── descriptors-info.hpp
│ ├── virtual-memory.hpp
│ ├── vmcb.hpp
│ ├── vmexit.hpp
│ └── vprocessor-data.hpp
│ ├── handlers
│ ├── cpuid.cpp
│ ├── handlers.hpp
│ ├── msr.cpp
│ ├── rdtsc.cpp
│ └── vmexit.cpp
│ ├── svm.cpp
│ ├── svm.hpp
│ ├── util
│ ├── util.cpp
│ └── util.hpp
│ └── vmenter.asm
└── usermode
├── main.cpp
├── usermode.vcxproj
├── usermode.vcxproj.filters
└── usermode.vcxproj.user
/.gitignore:
--------------------------------------------------------------------------------
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674 | .
675 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | ## amd-hypervisor
2 |
3 | ### credits:
4 | - [not-matthias](https://github.com/not-matthias)
5 | - [MellowNight](https://github.com/MellowNight)
6 |
7 | ### references:
8 | - [amd manual chapter 15](https://www.amd.com/system/files/TechDocs/24593.pdf#page=564&zoom=100,84,240)
9 | - [amd's nested paging whitepaper](http://developer.amd.com/wordpress/media/2012/10/NPT-WP-1%201-final-TM.pdf)
10 | - [tandasat's hypervisor](https://github.com/tandasat/SimpleSvm)
11 | - [not-matthias's hypervisor](https://github.com/not-matthias/amd_hypervisor)
12 | - [medievalghoul's hypervisor](https://github.com/medievalghoul/krakensvm-mg)
13 | - [daax's blog](https://revers.engineering/7-days-to-virtualization-a-series-on-hypervisor-development/)
14 |
15 | ### tools:
16 | - [osr loader]()
17 | - [not-matthias's rdtsc benchmarking tool](https://github.com/not-matthias/rdtsc_bench)
18 |
--------------------------------------------------------------------------------
/svm.sln:
--------------------------------------------------------------------------------
1 |
2 | Microsoft Visual Studio Solution File, Format Version 12.00
3 | # Visual Studio Version 16
4 | VisualStudioVersion = 16.0.31729.503
5 | MinimumVisualStudioVersion = 10.0.40219.1
6 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "svm", "svm\svm.vcxproj", "{C5EF5BD4-724D-4DCF-809E-04D44AE08334}"
7 | EndProject
8 | Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "usermode", "usermode\usermode.vcxproj", "{0198AA0B-C30A-4A07-AA52-C955A228BC39}"
9 | EndProject
10 | Global
11 | GlobalSection(SolutionConfigurationPlatforms) = preSolution
12 | Debug|ARM = Debug|ARM
13 | Debug|ARM64 = Debug|ARM64
14 | Debug|x64 = Debug|x64
15 | Debug|x86 = Debug|x86
16 | Release|ARM = Release|ARM
17 | Release|ARM64 = Release|ARM64
18 | Release|x64 = Release|x64
19 | Release|x86 = Release|x86
20 | EndGlobalSection
21 | GlobalSection(ProjectConfigurationPlatforms) = postSolution
22 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|ARM.ActiveCfg = Debug|ARM
23 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|ARM.Build.0 = Debug|ARM
24 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|ARM.Deploy.0 = Debug|ARM
25 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|ARM64.ActiveCfg = Debug|ARM64
26 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|ARM64.Build.0 = Debug|ARM64
27 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|ARM64.Deploy.0 = Debug|ARM64
28 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|x64.ActiveCfg = Debug|x64
29 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|x64.Build.0 = Debug|x64
30 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|x64.Deploy.0 = Debug|x64
31 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|x86.ActiveCfg = Debug|Win32
32 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|x86.Build.0 = Debug|Win32
33 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Debug|x86.Deploy.0 = Debug|Win32
34 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|ARM.ActiveCfg = Release|ARM
35 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|ARM.Build.0 = Release|ARM
36 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|ARM.Deploy.0 = Release|ARM
37 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|ARM64.ActiveCfg = Release|ARM64
38 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|ARM64.Build.0 = Release|ARM64
39 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|ARM64.Deploy.0 = Release|ARM64
40 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|x64.ActiveCfg = Release|x64
41 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|x64.Build.0 = Release|x64
42 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|x64.Deploy.0 = Release|x64
43 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|x86.ActiveCfg = Release|Win32
44 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|x86.Build.0 = Release|Win32
45 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}.Release|x86.Deploy.0 = Release|Win32
46 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Debug|ARM.ActiveCfg = Debug|Win32
47 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Debug|ARM64.ActiveCfg = Debug|Win32
48 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Debug|x64.ActiveCfg = Debug|x64
49 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Debug|x64.Build.0 = Debug|x64
50 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Debug|x86.ActiveCfg = Debug|Win32
51 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Debug|x86.Build.0 = Debug|Win32
52 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Release|ARM.ActiveCfg = Release|Win32
53 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Release|ARM64.ActiveCfg = Release|Win32
54 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Release|x64.ActiveCfg = Release|x64
55 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Release|x64.Build.0 = Release|x64
56 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Release|x86.ActiveCfg = Release|Win32
57 | {0198AA0B-C30A-4A07-AA52-C955A228BC39}.Release|x86.Build.0 = Release|Win32
58 | EndGlobalSection
59 | GlobalSection(SolutionProperties) = preSolution
60 | HideSolutionNode = FALSE
61 | EndGlobalSection
62 | GlobalSection(ExtensibilityGlobals) = postSolution
63 | SolutionGuid = {148D4B22-0242-4ECB-B175-74B313527186}
64 | EndGlobalSection
65 | EndGlobal
66 |
--------------------------------------------------------------------------------
/svm/common-includes.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include
3 | #include
4 | #include
5 | #include
6 | #include
7 | #include
8 | #pragma warning (disable : 4201)
9 | #pragma warning (disable : 4083)
10 | #pragma warning (disable : 4005)
11 | #pragma warning (disable : 4100)
12 | #pragma warning (disable : 5040)
13 | #pragma warning (disable : 4083)
14 | #include
15 | #include
16 |
17 | #define debug_log(text, ...) (DbgPrintEx(0, 0, /*xs*/(text), ##__VA_ARGS__))
18 |
19 | #define debug_break() __debugbreak();
--------------------------------------------------------------------------------
/svm/main.cpp:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/sariaki/amd-hypervisor/99224ea59e8e6a616b03faabcb8cf2ac5228abd5/svm/main.cpp
--------------------------------------------------------------------------------
/svm/svm.vcxproj:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 | Debug
6 | Win32
7 |
8 |
9 | Release
10 | Win32
11 |
12 |
13 | Debug
14 | x64
15 |
16 |
17 | Release
18 | x64
19 |
20 |
21 | Debug
22 | ARM
23 |
24 |
25 | Release
26 | ARM
27 |
28 |
29 | Debug
30 | ARM64
31 |
32 |
33 | Release
34 | ARM64
35 |
36 |
37 |
38 | {C5EF5BD4-724D-4DCF-809E-04D44AE08334}
39 | {1bc93793-694f-48fe-9372-81e2b05556fd}
40 | v4.5
41 | 12.0
42 | Debug
43 | Win32
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/svm/svm/def/cpu.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include
3 | #include "../../common-includes.hpp"
4 |
5 | #define SVM_MSR_PERMISSIONS_MAP_SIZE (PAGE_SIZE * 2)
6 | #define SVM_MSR_VM_HSAVE_PA 0xC0010117
7 |
8 | // extended feature enable register (EFER)
9 | #define IA32_MSR_EFER 0xC0000080
10 | #define IA32_MSR_EFER_SVME (1UL << 12) // this will set the 13 bit of EFER (if we're counting starting from 1),
11 | #define IA32_MSR_PAT 0x00000277
12 | #define SVM_MSR_VM_CR 0xc0010114
13 | #define SVM_MSR_VM_HSAVE_PA 0xc0010117
14 |
15 | // long system target-address register (LSTAR)
16 | #define IA32_LSTAR 0xC0000082
17 |
18 | #define POOL_NX_OPTIN 1
19 | #define SVM_VM_CR_SVMDIS (1UL << 4)
20 | #define SVM_NP_ENABLE_NP_ENABLE (1UL << 0)
21 |
22 | #define EFER_SVME (1UL << 12)
23 |
24 | #define IA32_APIC_BASE 0x0000001b
25 |
26 | namespace svm
27 | {
28 | enum class cpuid : uint32_t
29 | {
30 | cpu_vendor_string = 0x00000000,
31 | processor_feature_id = 0x00000001,
32 | hypervisor_present_ex = 0x80000000,
33 | processor_feature_id_ex = 0x80000001,
34 | svm_features = 0x8000000a,
35 | svm_features_ex = 0x80000001,
36 | hypervisor_vendor_id = 0x40000000,
37 | hypervisor_interface = 0x40000001,
38 |
39 | cpu_ecx_svm = 0x4,
40 | cpu_edx_np = 0x1,
41 | };
42 |
43 | enum class msr : uint32_t
44 | {
45 | svm_vm_cr = 0xc0010114,
46 | svm_vm_cr_svmdis = 0x10,
47 | };
48 |
49 | typedef union _cr3
50 | {
51 | uint64_t flags;
52 | struct
53 | {
54 | uint64_t reserved1 : 3;
55 | uint64_t page_level_write_through : 1;
56 | uint64_t page_level_cache_disable : 1;
57 | uint64_t reserved2 : 7;
58 | uint64_t dirbase : 36;
59 | uint64_t reserved3 : 16;
60 | };
61 | } cr3;
62 |
63 | extern "C" void _sgdt(PVOID descriptor);
64 | }
--------------------------------------------------------------------------------
/svm/svm/def/descriptors-info.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include
3 | #pragma pack(push, 1)
4 |
5 | namespace svm
6 | {
7 | typedef struct
8 | {
9 | uint16_t limit;
10 | uintptr_t base;
11 | } descriptor_table_register_t, * pdescriptor_table_register_t;
12 | static_assert(sizeof(descriptor_table_register_t) == 10,
13 | "descriptor_table_register size mismatch");
14 |
15 | typedef struct
16 | {
17 | union
18 | {
19 | uint64_t value;
20 | struct
21 | {
22 | uint16_t limit_low;
23 | uint16_t base_low;
24 | uint32_t base_middle : 8;
25 | uint32_t type : 4;
26 | uint32_t system : 1;
27 | uint32_t dpl : 2;
28 | uint32_t present : 1;
29 | uint32_t limit_high : 4;
30 | uint32_t avl : 1;
31 | uint32_t long_mode : 1;
32 | uint32_t default_bit : 1;
33 | uint32_t granularity : 1;
34 | uint32_t base_high : 8;
35 | } fields;
36 | };
37 | } segment_descriptor_t, * psegment_descriptor_t;
38 | static_assert(sizeof(segment_descriptor_t) == 8,
39 | "segment_descriptor size mismatch");
40 |
41 | typedef struct
42 | {
43 | union
44 | {
45 | uint16_t value;
46 | struct
47 | {
48 | uint16_t type : 4;
49 | uint16_t system : 1;
50 | uint16_t dpl : 2;
51 | uint16_t present : 1;
52 | uint16_t avl : 1;
53 | uint16_t long_mode : 1;
54 | uint16_t default_bit : 1;
55 | uint16_t granularity : 1;
56 | uint16_t reserved1 : 4;
57 | } fields;
58 | };
59 | } segment_attributes_t, * psegment_attributes_t;
60 | static_assert(sizeof(segment_attributes_t) == 2,
61 | "segment_attributes size mismatch");
62 | }
63 |
64 | #pragma pack (pop)
--------------------------------------------------------------------------------
/svm/svm/def/virtual-memory.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "../../common-includes.hpp"
3 |
4 | namespace svm
5 | {
6 | // // http://developer.amd.com/wordpress/media/2012/10/NPT-WP-1%201-final-TM.pdf
7 | typedef struct
8 | {
9 | union
10 | {
11 | UINT64 value;
12 | struct
13 | {
14 | UINT64 reserved1 : 8;
15 | UINT64 bootstrap_processor : 1;
16 | UINT64 reserved2 : 1;
17 | UINT64 enable_x2_apic_mode : 1;
18 | UINT64 enable_x_api_global : 1;
19 | UINT64 apic_base : 24;
20 | } fields;
21 | };
22 | } apic_base_t, * papic_base_t;
23 | static_assert(sizeof(apic_base_t) == 8, "apic base size mismatch");
24 |
25 | typedef struct
26 | {
27 | union
28 | {
29 | UINT64 value;
30 | struct
31 | {
32 | UINT64 valid : 1;
33 | UINT64 write : 1;
34 | UINT64 user : 1;
35 | UINT64 write_through : 1;
36 | UINT64 cache_disable : 1;
37 | UINT64 accessed : 1;
38 | UINT64 dirty : 1;
39 | UINT64 pat : 1;
40 | UINT64 global : 1;
41 | UINT64 avl : 3;
42 | UINT64 page_frame_nr : 40;
43 | UINT64 reserved1 : 11;
44 | UINT64 no_execute : 1;
45 | } fields;
46 | };
47 | } pt_entry_4kb_t, * ppt_entry_4kb_t;
48 | static_assert(sizeof(pt_entry_4kb_t) == 8, "page table enty 4kb size mismatch");
49 |
50 | typedef struct
51 | {
52 | union
53 | {
54 | uint64_t value;
55 | struct
56 | {
57 | uint64_t valid : 1;
58 | uint64_t write : 1;
59 | uint64_t user : 1;
60 | uint64_t write_through : 1;
61 | uint64_t cache_disable : 1;
62 | uint64_t accessed : 1;
63 | uint64_t reserved1 : 3;
64 | uint64_t avl : 3;
65 | uint64_t page_frame_nr : 40;
66 | uint64_t reserved2 : 11;
67 | uint64_t no_execute : 1;
68 | } fields;
69 | };
70 | } pml4_entry_4kb_t, * ppml4_entry_4kb_t,
71 | pdp_entry_4kb_t, * ppdp_entry_4kb_t;
72 | static_assert(sizeof(pml4_entry_4kb_t) == 8,
73 | "pml4 entry 4kb size mismatch");
74 |
75 | typedef struct
76 | {
77 | union
78 | {
79 | uint64_t value;
80 | struct
81 | {
82 | uint64_t valid : 1;
83 | uint64_t write : 1;
84 | uint64_t user : 1;
85 | uint64_t write_through : 1;
86 | uint64_t cache_disable : 1;
87 | uint64_t accessed : 1;
88 | uint64_t dirty : 1;
89 | uint64_t large_page : 1;
90 | uint64_t global : 1;
91 | uint64_t avl : 3;
92 | uint64_t pat : 1;
93 | uint64_t reserved1 : 8;
94 | uint64_t page_frame_nr : 31;
95 | uint64_t reserved2 : 11;
96 | uint64_t no_execute : 1;
97 | } fields;
98 | };
99 | } pd_entry_4kb_t, * ppd_entry_4kb_t;
100 | static_assert(sizeof(pd_entry_4kb_t) == 8,
101 | "pd entry 4kb size mismatch");
102 |
103 | typedef union
104 | {
105 | PVOID value;
106 | struct
107 | {
108 | uint64_t offset : 12;
109 | uint64_t pt_index : 9;
110 | uint64_t pd_index : 9;
111 | uint64_t pdpt_index : 9;
112 | uint64_t pml4_index : 9;
113 | uint64_t reserved1 : 16;
114 | };
115 | } virtual_address_t, * pvirtual_address_t;
116 | static_assert(sizeof(virtual_address_t) == 8,
117 | "virtual address size mismatch");
118 | }
--------------------------------------------------------------------------------
/svm/svm/def/vmcb.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "../../common-includes.hpp"
3 |
4 | namespace svm
5 | {
6 | typedef union
7 | {
8 | uint16_t value;
9 |
10 | struct
11 | {
12 | uint16_t type : 4;
13 | uint16_t system : 1;
14 | uint16_t dpl : 2;
15 | uint16_t present : 1;
16 | uint16_t avl : 1;
17 | uint16_t longmode : 1;
18 | uint16_t default_bit : 1;
19 | uint16_t granularity : 1;
20 | uint16_t reserved : 4;
21 | };
22 | } segment_attribute_64_t, * psegment_attribute_64_t;
23 | static_assert(sizeof(segment_attribute_64_t) == 2,
24 | "segment_attribute_64 size mismatch");
25 |
26 | struct seg_register
27 | {
28 | uint16_t selector;
29 | segment_attribute_64_t attribute;
30 | uint32_t limit;
31 | uint64_t base;
32 | };
33 | static_assert(sizeof(seg_register) == 0x10,
34 | "seg_register size mismatch");
35 |
36 | // Table B-1. VMCB Layout, Control Area
37 | typedef struct
38 | {
39 | uint16_t intercept_cr_read; // +0x000
40 | uint16_t intercept_cr_write; // +0x002
41 | uint16_t intercept_dr_read; // +0x004
42 | uint16_t intercept_dr_write; // +0x006
43 | uint32_t intercept_exeption; // +0x008
44 | uint32_t intercept_misc1; // +0x00c
45 | uint32_t intercept_misc2; // +0x010
46 | uint8_t reserved1[0x03c - 0x014]; // +0x014
47 | uint16_t pause_filter_threshhold; // +0x03c
48 | uint16_t pause_filter_count; // +0x03e
49 | uint64_t iopm_base_pa; // +0x040
50 | uint64_t msrpm_base_pa; // +0x048
51 | uint64_t tsc_offset; // +0x050
52 | uint32_t guest_asid; // +0x058
53 | uint32_t tlb_control; // +0x05c
54 | uint64_t vintr; // +0x060
55 | uint64_t interrupt_shadow; // +0x068
56 | uint64_t exit_code; // +0x070
57 | uint64_t exit_info1; // +0x078
58 | uint64_t exit_info2; // +0x080
59 | uint64_t exit_int_info; // +0x088
60 | uint64_t np_enable; // +0x090
61 | uint64_t avic_apic_bar; // +0x098
62 | uint64_t guest_pa_of_ghcb; // +0x0a0
63 | uint64_t event_inj; // +0x0a8
64 | uint64_t ncr3; // +0x0b0
65 | uint64_t lbr_virtualization_enable; // +0x0b8
66 | uint64_t vmcb_clean; // +0x0c0
67 | uint64_t next_rip; // +0x0c8
68 | uint8_t num_of_bytes_fetched; // +0x0d0
69 | uint8_t guest_instruction_bytes[15]; // +0x0d1
70 | uint64_t avic_apic_backing_page_ptr; // +0x0e0
71 | uint64_t reserved2; // +0x0e8
72 | uint64_t avic_logical_table_ptr; // +0x0f0
73 | uint64_t avic_physical_table_ptr; // +0x0f8
74 | uint64_t reserved3; // +0x100
75 | uint64_t vmcb_save_state_ptr; // +0x108
76 | uint8_t reserved4[0x400 - 0x110]; // +0x110
77 | } vmcb_ctrl_area_t, * pvmcb_ctrl_area_t;
78 | static_assert(sizeof(vmcb_ctrl_area_t) == 0x400,
79 | "vmcb_ctrl_area size mismatch");
80 |
81 | // Table B-2. VMCB Layout, State Save Area
82 | typedef struct
83 | {
84 | seg_register es; // +0x000
85 | seg_register cs; // +0x010
86 | seg_register ss; // +0x020
87 | seg_register ds; // +0x030
88 | seg_register fs; // +0x040
89 | seg_register gs; // +0x050
90 | seg_register gdtr; // +0x060
91 | seg_register ldtr; // +0x070
92 | seg_register idtr; // +0x080
93 | seg_register tr; // +0x090
94 | uint8_t reserved1[0x0cb - 0x0a0]; // +0x0a0
95 | uint8_t cpl; // +0x0cb
96 | uint32_t reserved2; // +0x0cc
97 | uint64_t efer; // +0x0d0
98 | uint8_t reserved3[0x148 - 0x0d8]; // +0x0d8
99 | uint64_t cr4; // +0x148
100 | uint64_t cr3; // +0x150
101 | uint64_t cr0; // +0x158
102 | uint64_t dr7; // +0x160
103 | uint64_t dr6; // +0x168
104 | uint64_t rflags; // +0x170
105 | uint64_t rip; // +0x178
106 | uint8_t reserved4[0x1d8 - 0x180]; // +0x180
107 | uint64_t rsp; // +0x1d8
108 | uint8_t reserved5[0x1f8 - 0x1e0]; // +0x1e0
109 | uint64_t rax; // +0x1f8
110 | uint64_t star; // +0x200
111 | uint64_t lstar; // +0x208
112 | uint64_t cstar; // +0x210
113 | uint64_t sfmask; // +0x218
114 | uint64_t kernel_gs_base; // +0x220
115 | uint64_t sysenter_cs; // +0x228
116 | uint64_t sysenter_esp; // +0x230
117 | uint64_t sysenter_eip; // +0x238
118 | uint64_t cr2; // +0x240
119 | uint8_t reserved6[0x268 - 0x248]; // +0x248
120 | uint64_t gpat; // +0x268
121 | uint64_t dbg_ctl; // +0x270
122 | uint64_t br_from; // +0x278
123 | uint64_t br_to; // +0x280
124 | uint64_t last_excep_from; // +0x288
125 | uint64_t last_exep_to; // +0x290
126 | } vmcb_state_save_area_t, * pvmcb_state_save_area_t;
127 | static_assert(sizeof(vmcb_state_save_area_t) == 0x298,
128 | "vmcb_state_save_area size mismatch");
129 |
130 | typedef struct
131 | {
132 | vmcb_ctrl_area_t control_area;
133 | vmcb_state_save_area_t state_save_area;
134 | uint8_t reserved1[0x1000 - sizeof(vmcb_ctrl_area_t) - sizeof(vmcb_state_save_area_t)];
135 | } vmcb_t, * pvmcb_t;
136 | static_assert(sizeof(vmcb_t) == 0x1000,
137 | "vmcb size mismatch");
138 |
139 | typedef struct
140 | {
141 | uint64_t r15;
142 | uint64_t r14;
143 | uint64_t r13;
144 | uint64_t r12;
145 | uint64_t r11;
146 | uint64_t r10;
147 | uint64_t r9;
148 | uint64_t r8;
149 | uint64_t rdi;
150 | uint64_t rsi;
151 | uint64_t rbp;
152 | uint64_t rsp;
153 | uint64_t rbx;
154 | uint64_t rdx;
155 | uint64_t rcx;
156 | uint64_t rax;
157 | } guest_registers_t, * pguest_registers_t;
158 |
159 | typedef struct
160 | {
161 | pguest_registers_t vprocessor_registers;
162 | bool should_exit;
163 | } guest_ctx_t, * pguest_ctx_t;
164 | }
--------------------------------------------------------------------------------
/svm/svm/def/vmexit.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #pragma warning (disable : 4369)
3 | #pragma warning (disable : 4309)
4 |
5 | #define RPL_MASK 3
6 | #define DPL_SYSTEM 0
7 |
8 | #define CPUID_UNLOAD 0xB16D1C
9 |
10 | // Table B-1. VMCB Layout, Control Area
11 | enum misc1_intercept : uint32_t
12 | {
13 | intercept_intr = (1UL << 0),
14 | intercept_nmi = (1UL << 1),
15 | intercept_smi = (1UL << 2),
16 | intercept_init = (1UL << 3),
17 | intercept_vintr = (1UL << 4),
18 | intercept_cr0_ = (1UL << 5),
19 |
20 | intercept_read_idtr = (1UL << 6),
21 | intercept_read_gdtr = (1UL << 7),
22 | intercept_read_ldtr = (1UL << 8),
23 | intercept_read_tr = (1UL << 9),
24 |
25 | intercept_write_idtr = (1UL << 10),
26 | intercept_write_gdtr = (1UL << 11),
27 | intercept_write_ldtr = (1UL << 12),
28 | intercept_write_tr = (1UL << 13),
29 |
30 | intercept_rdtsc = (1UL << 14),
31 | intercept_rdpmc = (1UL << 15),
32 | intercept_pushf = (1UL << 16),
33 | intercept_popf = (1UL << 17),
34 | intercept_cpuid = (1UL << 18),
35 | intercept_rsm = (1UL << 19),
36 | intercept_iret = (1UL << 20),
37 | intercept_intn = (1UL << 21),
38 | intercept_invd= (1UL << 22),
39 | intercept_pause = (1UL << 23),
40 | intercept_hlt = (1UL << 24),
41 | intercept_invldpg = (1UL << 25),
42 | intercept_invlpga = (1UL << 26),
43 | intercept_ioio_prot = (1UL << 27),
44 | intercept_msr_prot = (1UL << 28),
45 | intercept_task_switches = (1UL << 29),
46 | intercept_ferr_freeze = (1UL << 30),
47 | intercept_shutdown = (1UL << 31),
48 | };
49 |
50 | enum misc2_intercept : uint32_t
51 | {
52 | intercept_vmrun = (1UL << 0),
53 | intercept_vmcall = (1UL << 1),
54 | intercept_vmload = (1UL << 2),
55 | intercept_vmsave = (1UL << 3),
56 |
57 | intercept_stgi = (1UL << 4),
58 | intercept_clgi = (1UL << 5),
59 | intercept_skinit = (1UL << 6),
60 | intercept_rdtscp = (1UL << 7),
61 | intercept_incebp = (1UL << 8),
62 | intercept_wbinvd = (1UL << 9),
63 | intercept_monitor = (1UL << 10),
64 | intercept_mwait = (1UL << 11),
65 | intercept_mwait_conditional = (1UL << 12),
66 | intercept_xsetbv = (1UL << 13),
67 | intercept_rdpru = (1UL << 14),
68 | intercept_efer = (1UL << 15),
69 |
70 | intercept_cr0 = (1UL << 16),
71 | intercept_cr1 = (1UL << 17),
72 | intercept_cr2 = (1UL << 18),
73 | intercept_cr3 = (1UL << 19),
74 | intercept_cr4 = (1UL << 20),
75 | intercept_cr5 = (1UL << 21),
76 | intercept_cr6 = (1UL << 22),
77 | intercept_cr7 = (1UL << 23),
78 | intercept_cr8 = (1UL << 24),
79 | intercept_cr9 = (1UL << 25),
80 | intercept_cr10 = (1UL << 26),
81 | intercept_cr11 = (1UL << 27),
82 | intercept_cr12 = (1UL << 28),
83 | intercept_cr13 = (1UL << 29),
84 | intercept_cr14 = (1UL << 30),
85 | intercept_cr15 = (1UL << 31),
86 | };
87 |
88 | enum exception_intercept : int16_t
89 | {
90 |
91 | };
92 |
93 | typedef struct
94 | {
95 | union
96 | {
97 | uint64_t value;
98 | struct
99 | {
100 | uint64_t vector : 8;
101 | uint64_t type : 3;
102 | uint64_t error_code_valid : 1;
103 | uint64_t reserved1 : 19;
104 | uint64_t valid : 1;
105 | uint64_t error_code : 32;
106 | } fields;
107 | };
108 | } event_inj_t, * pevent_inj_t;
109 | static_assert(sizeof(event_inj_t) == 8,
110 | "event_inj size mismatch");
111 |
112 | // Table C-1. SVM Intercept Codes
113 | enum vmexit : int16_t
114 | {
115 | cr0_read = 0x0,
116 | cr1_read = 0x1,
117 | cr2_read = 0x2,
118 | cr3_read = 0x3,
119 | cr4_read = 0x4,
120 | cr5_read = 0x5,
121 | cr6_read = 0x6,
122 | cr7_read = 0x7,
123 | cr8_read = 0x8,
124 | cr9_read = 0x9,
125 | cr10_read = 0xa,
126 | cr11_read = 0xb,
127 | cr12_read = 0xc,
128 | cr13_read = 0xd,
129 | cr14_read = 0xe,
130 | cr15_read = 0xf,
131 |
132 | cr0_write = 0x10,
133 | cr1_write = 0x11,
134 | cr2_write = 0x12,
135 | cr3_write = 0x13,
136 | cr4_write = 0x14,
137 | cr5_write = 0x15,
138 | cr6_write = 0x16,
139 | cr7_write = 0x17,
140 | cr8_write = 0x18,
141 | cr9_write = 0x19,
142 | cr10_write = 0x1a,
143 | cr11_write = 0x1b,
144 | cr12_write = 0x1c,
145 | cr13_write = 0x1d,
146 | cr14_write = 0x1e,
147 | cr15_write = 0x1f,
148 |
149 | dr0_read = 0x20,
150 | dr1_read = 0x21,
151 | dr2_read = 0x22,
152 | dr3_read = 0x23,
153 | dr4_read = 0x24,
154 | dr5_read = 0x25,
155 | dr6_read = 0x26,
156 | dr7_read = 0x27,
157 | dr8_read = 0x28,
158 | dr9_read = 0x29,
159 | dr10_read = 0x2a,
160 | dr11_read = 0x2b,
161 | dr12_read = 0x2c,
162 | dr13_read = 0x2d,
163 | dr14_read = 0x2e,
164 | dr15_read = 0x2f,
165 |
166 | dr0_write = 0x30,
167 | dr1_write = 0x31,
168 | dr2_write = 0x32,
169 | dr3_write = 0x33,
170 | dr4_write = 0x34,
171 | dr5_write = 0x35,
172 | dr6_write = 0x36,
173 | dr7_write = 0x37,
174 | dr8_write = 0x38,
175 | dr9_write = 0x39,
176 | dr10_write = 0x3a,
177 | dr11_write = 0x3b,
178 | dr12_write = 0x3c,
179 | dr13_write = 0x3d,
180 | dr14_write = 0x3e,
181 | dr15_write = 0x3f,
182 |
183 | excp0_write = 0x40,
184 | excp1_write = 0x41,
185 | excp2_write = 0x42,
186 | excp3_write = 0x43,
187 | excp4_write = 0x44,
188 | excp5_write = 0x45,
189 | excp6_write = 0x46,
190 | excp7_write = 0x47,
191 | excp8_write = 0x48,
192 | excp9_write = 0x49,
193 | excp10_write = 0x4a,
194 | excp11_write = 0x4b,
195 | excp12_write = 0x4c,
196 | excp13_write = 0x4d,
197 | excp14_write = 0x4e,
198 | excp15_write = 0x4f,
199 | excp16_write = 0x50,
200 | excp17_write = 0x51,
201 | excp18_write = 0x52,
202 | excp19write = 0x53,
203 | excp20_write = 0x54,
204 | excp21_write = 0x55,
205 | excp22_write = 0x56,
206 | excp23_write = 0x57,
207 | excp24_write = 0x58,
208 | excp25_write = 0x59,
209 | excp26_write = 0x5a,
210 | excp27_write = 0x5b,
211 | excp28_write = 0x5c,
212 | excp29_write = 0x5d,
213 | excp30_write = 0x5e,
214 | excp31_write = 0x5f,
215 |
216 | intr = 0x60,
217 | nmi = 0x61,
218 | smi = 0x62,
219 | init = 0x63,
220 | vintr = 0x64,
221 | cr0_sel_write = 0x65,
222 | idtr_read = 0x66,
223 | gdtr_read = 0x67,
224 | ldtr_read = 0x68,
225 | tr_read = 0x69,
226 | idtr_write = 0x6A,
227 | gftr_write = 0x6B,
228 | ldtr_write = 0x6C,
229 | tr_write = 0x6D,
230 | rdtsc = 0x6E,
231 | rdpmc = 0x6F,
232 | pushf = 0x70,
233 | popf = 0x71,
234 | cpuid = 0x72,
235 | rsm = 0x73,
236 | iret = 0x74,
237 | swint = 0x75,
238 | invd = 0x76,
239 | pause = 0x77,
240 | hlt = 0x78,
241 | invlpg = 0x79,
242 | invlpga = 0x7A,
243 | ioio = 0x7B,
244 | msr = 0x7C,
245 | task_switch = 0x7D,
246 | ferr_freeze = 0x7E,
247 | shutdown = 0x7F,
248 | vmrun = 0x80,
249 | vmcall = 0x81,
250 | vmload = 0x82,
251 | vmsave = 0x83,
252 | sigi = 0x84,
253 | clgi = 0x85,
254 | skinit = 0x86,
255 | rdtscp = 0x87,
256 | icebp = 0x88,
257 | wbinvd = 0x89,
258 | monitor = 0x8A,
259 | mwait = 0x8B,
260 | mwait_conditional = 0x8C,
261 | rdpru = 0x8D,
262 | xsetbv = 0x8E,
263 | efer_write_trap = 0x8F,
264 |
265 | cr0_write_trap = 0x90,
266 | cr1_write_trap = 0x91,
267 | cr2_write_trap= 0x92,
268 | cr3_write_trap= 0x93,
269 | cr4_write_trap= 0x94,
270 | cr5_write_trap= 0x95,
271 | cr6_write_trap= 0x96,
272 | cr7_write_trap= 0x97,
273 | cr8_write_trap= 0x98,
274 | cr9_write_trap= 0x99,
275 | cr10_write_trap = 0x9a,
276 | cr11_write_trap = 0x9b,
277 | cr12_write_trap = 0x9c,
278 | cr13_write_trap = 0x9d,
279 | cr14_write_trap = 0x9e,
280 | cr15_write_trap = 0x9f,
281 |
282 | invlpgb = 0xA0,
283 | invlpgb_illegal = 0xA1,
284 | invpcid = 0xA2,
285 | mcommit = 0xA3,
286 | tlbsync = 0xA4,
287 | npf = 0x400,
288 | incomplete_ipi = 0x401,
289 | avic_noaccel = 0x402,
290 | vmgexit = 0x403,
291 | invalid = -1,
292 | busy = -2
293 | };
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/svm/svm/def/vprocessor-data.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "../../common-includes.hpp"
3 | #include "vmcb.hpp"
4 | #include "virtual-memory.hpp"
5 |
6 | namespace svm
7 | {
8 | typedef struct
9 | {
10 | PVOID msr_permissions_map;
11 | DECLSPEC_ALIGN(PAGE_SIZE) pml4_entry_4kb_t pml4_entries[1]; // 512 gb
12 | DECLSPEC_ALIGN(PAGE_SIZE) pdp_entry_4kb_t pdp_entries[512];
13 | DECLSPEC_ALIGN(PAGE_SIZE) pd_entry_4kb_t pd_entries[512][512];
14 | } shared_vcpu_t, * pshared_vcpu_t;
15 |
16 | typedef struct _vprocessor_data
17 | {
18 | union
19 | {
20 | DECLSPEC_ALIGN(PAGE_SIZE) uint8_t host_stack_limit[KERNEL_STACK_SIZE];
21 | struct
22 | {
23 | uint8_t stack_contents[KERNEL_STACK_SIZE - (sizeof(PVOID) * 6) - sizeof(KTRAP_FRAME)];
24 | KTRAP_FRAME trap_frame;
25 | uint64_t guest_vmcb_pa; // host rsp
26 | uint64_t host_vmcb_pa;
27 | _vprocessor_data* self;
28 | pshared_vcpu_t shared_vcpu;
29 | uint64_t padding1; // keep host rsp 16 bytes aligned
30 | uint64_t reserved1;
31 | } host_stack_layout;
32 | };
33 |
34 | DECLSPEC_ALIGN(PAGE_SIZE) vmcb_t guest_vmcb;
35 | DECLSPEC_ALIGN(PAGE_SIZE) vmcb_t host_vmcb;
36 | DECLSPEC_ALIGN(PAGE_SIZE) uint8_t host_state_area[PAGE_SIZE];
37 | } vcpu_t, * pvcpu_t;
38 | static_assert(sizeof(vcpu_t) == KERNEL_STACK_SIZE + PAGE_SIZE * 3,
39 | "vcpu_t size mismatch");
40 | }
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/svm/svm/handlers/cpuid.cpp:
--------------------------------------------------------------------------------
1 | #include "handlers.hpp"
2 | #include "../util/util.hpp"
3 | #pragma warning (disable : 4293)
4 | #pragma warning (disable : 26451)
5 |
6 | namespace svm
7 | {
8 | namespace handle
9 | {
10 | void cpuid(pvcpu_t vcpu, pguest_ctx_t guest_ctx)
11 | {
12 | int registers[4]; // eax ebx ecx edx
13 | int leaf, sub_leaf;
14 | segment_attributes_t attribute;
15 |
16 | // execute cpuid for request
17 | leaf = static_cast(guest_ctx->vprocessor_registers->rax);
18 | sub_leaf = static_cast(guest_ctx->vprocessor_registers->rcx);
19 | __cpuidex(registers, leaf, sub_leaf);
20 |
21 | switch (leaf)
22 | {
23 | //case static_cast(cpuid::processor_feature_id):
24 | // // specify hypervisor presence
25 | // registers[2] |= static_cast(cpuid::hypervisor_present_ex);
26 | // break;
27 |
28 | case static_cast(cpuid::hypervisor_vendor_id):
29 | // this is used in util::is_hypervisor_vendor_installed()
30 | // to check if the hypervisor is running
31 | registers[0] = static_cast(cpuid::hypervisor_vendor_id); // CPUID_HV_MAX
32 | registers[1] = ' mvs';
33 | registers[2] = ' ';
34 | registers[3] = ' ';
35 | break;
36 |
37 | case static_cast(cpuid::hypervisor_interface):
38 | // specify that our hypervisor does not
39 | // conform to the Microsoft hypervisor interface
40 | registers[0] = '0#vH'; // Hv#0
41 | registers[1] = registers[2] = registers[3] = 0;
42 | break;
43 |
44 | case CPUID_UNLOAD:
45 | if (sub_leaf == CPUID_UNLOAD)
46 | {
47 | // unload
48 | attribute.value = vcpu->guest_vmcb.state_save_area.ss.attribute.value;
49 | if (attribute.fields.dpl == DPL_SYSTEM)
50 | guest_ctx->should_exit = true;
51 | }
52 | break;
53 |
54 | default:
55 | break;
56 | }
57 |
58 | // update the guest's gpr's used by cpuid
59 | guest_ctx->vprocessor_registers->rax = registers[0];
60 | guest_ctx->vprocessor_registers->rbx = registers[1];
61 | guest_ctx->vprocessor_registers->rcx = registers[2];
62 | guest_ctx->vprocessor_registers->rdx = registers[3];
63 |
64 | next_instruction;
65 | }
66 | }
67 | }
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/svm/svm/handlers/handlers.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "../../common-includes.hpp"
3 | #include "../def/cpu.hpp"
4 | #include "../def/cpu.hpp"
5 | #include "../def/descriptors-info.hpp"
6 | #include "../def/vmexit.hpp"
7 | #include "../def/virtual-memory.hpp"
8 | #include "../def/vprocessor-data.hpp"
9 | #include "../util/util.hpp"
10 |
11 | #pragma warning (disable : 4244)
12 | #pragma warning (disable : 4293)
13 | #pragma warning (disable : 26451)
14 |
15 | #define next_instruction vcpu->guest_vmcb.state_save_area.rip = vcpu->guest_vmcb.control_area.next_rip
16 |
17 | namespace svm
18 | {
19 | namespace handle
20 | {
21 | void cpuid(pvcpu_t vprocessor_data, pguest_ctx_t guest_ctx);
22 |
23 | void msr(pvcpu_t vprocessor_data, pguest_ctx_t guest_ctx);
24 |
25 | void rdtsc(pvcpu_t vcpu, pguest_ctx_t guest_ctx);
26 |
27 | extern "C" bool __stdcall handle_vmexit(pvcpu_t vprocessor_data, pguest_registers_t guest_registers);
28 | }
29 | }
--------------------------------------------------------------------------------
/svm/svm/handlers/msr.cpp:
--------------------------------------------------------------------------------
1 | #include "handlers.hpp"
2 | #include "../util/util.hpp"
3 | #pragma warning (disable : 4293)
4 | #pragma warning (disable : 26451)
5 |
6 | namespace svm
7 | {
8 | namespace handle
9 | {
10 | void msr(pvcpu_t vcpu, pguest_ctx_t guest_ctx)
11 | {
12 | ULARGE_INTEGER value;
13 | uint32_t msr;
14 | bool write_access;
15 |
16 | msr = guest_ctx->vprocessor_registers->rcx & MAXUINT;
17 | write_access = (vcpu->guest_vmcb.control_area.exit_info1 != 0);
18 |
19 | if (msr == IA32_MSR_EFER)
20 | {
21 | // vmexit on EFER access should only occur on write access.
22 | NT_ASSERT(write_access);
23 |
24 | value.LowPart = guest_ctx->vprocessor_registers->rax & MAXUINT;
25 | value.HighPart = guest_ctx->vprocessor_registers->rdx & MAXUINT;
26 |
27 | if ((value.QuadPart & EFER_SVME) == 0)
28 | util::invalid_opcode_exception(vcpu); // protect EFER.SVME bit by causing exeption
29 |
30 | // otherwise return the physical address of the value
31 | vcpu->guest_vmcb.state_save_area.efer = value.QuadPart;
32 | }
33 | else
34 | {
35 | if (write_access)
36 | {
37 | value.LowPart = guest_ctx->vprocessor_registers->rax & MAXUINT;
38 | value.HighPart = guest_ctx->vprocessor_registers->rdx & MAXUINT;
39 | __writemsr(msr, value.QuadPart);
40 | }
41 | else
42 | {
43 | value.QuadPart = __readmsr(msr);
44 | guest_ctx->vprocessor_registers->rax = value.LowPart;
45 | guest_ctx->vprocessor_registers->rdx = value.HighPart;
46 | }
47 | }
48 |
49 | next_instruction;
50 | }
51 | }
52 | }
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/svm/svm/handlers/rdtsc.cpp:
--------------------------------------------------------------------------------
1 | #include "handlers.hpp"
2 | #include "../util/util.hpp"
3 | #pragma warning (disable : 4293)
4 | #pragma warning (disable : 26451)
5 |
6 | namespace svm
7 | {
8 | namespace handle
9 | {
10 | void rdtsc(pvcpu_t vcpu, pguest_ctx_t guest_ctx)
11 | {
12 | guest_ctx->vprocessor_registers->rax = static_cast(__rdtsc());
13 | guest_ctx->vprocessor_registers->rdx = __rdtsc() >> 32;
14 |
15 | next_instruction;
16 | }
17 | }
18 | }
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/svm/svm/handlers/vmexit.cpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "handlers.hpp"
3 |
4 | namespace svm
5 | {
6 | namespace handle
7 | {
8 | extern "C" bool __stdcall handle_vmexit(pvcpu_t vcpu, pguest_registers_t guest_registers)
9 | {
10 | guest_ctx_t guest_ctx;
11 | KIRQL old_irql;
12 |
13 | guest_ctx.vprocessor_registers = guest_registers;
14 | guest_ctx.should_exit = false;
15 |
16 | // load some of the host state which isn't loaded on vmexit
17 | __svm_vmload(vcpu->host_stack_layout.host_vmcb_pa);
18 |
19 | NT_ASSERT(vcpu->host_stack_layout.reserved1 == MAXUINT64);
20 |
21 | // not needed
22 | old_irql = KeGetCurrentIrql();
23 | if (old_irql < DISPATCH_LEVEL)
24 | KeRaiseIrqlToDpcLevel();
25 |
26 | // the guest's rax is overwritten by the hosts on vmexit
27 | // and saved in the vmcb instead
28 | guest_registers->rax = vcpu->guest_vmcb.state_save_area.rax;
29 |
30 | // update the _KTRAP_FRAME struct values in hypervisor stack,
31 | // so that windbg can reconstruct the guests stack frame
32 | vcpu->host_stack_layout.trap_frame.Rsp = vcpu->guest_vmcb.state_save_area.rsp;
33 | vcpu->host_stack_layout.trap_frame.Rip = vcpu->guest_vmcb.control_area.next_rip;
34 |
35 | // vmexit handling
36 | switch (vcpu->guest_vmcb.control_area.exit_code)
37 | {
38 | case vmexit::cpuid:
39 | handle::cpuid(vcpu, &guest_ctx);
40 | break;
41 |
42 | case vmexit::msr:
43 | handle::msr(vcpu, &guest_ctx);
44 | break;
45 |
46 | case vmexit::vmrun:
47 | util::general_protection_exeption(vcpu);
48 | break;
49 |
50 | case vmexit::vmload:
51 | util::general_protection_exeption(vcpu);
52 | break;
53 |
54 | case vmexit::vmsave:
55 | util::general_protection_exeption(vcpu);
56 | break;
57 |
58 | case vmexit::rdtsc:
59 | handle::rdtsc(vcpu, &guest_ctx);
60 | break;
61 |
62 | default:
63 | KeBugCheck(0xB16B00B5UL);
64 | }
65 |
66 | if (old_irql < DISPATCH_LEVEL)
67 | KeLowerIrql(old_irql);
68 |
69 | // terminate hypervisor
70 | if (guest_ctx.should_exit)
71 | {
72 | // RBX : address to return
73 | // RCX : stack pointer to restore
74 | // EDX:EAX : address of per processor data to be freed by the caller
75 | guest_ctx.vprocessor_registers->rax = reinterpret_cast(vcpu) & MAXUINT;
76 | guest_ctx.vprocessor_registers->rbx = vcpu->guest_vmcb.control_area.next_rip;
77 | guest_ctx.vprocessor_registers->rcx = vcpu->guest_vmcb.state_save_area.rsp;
78 | guest_ctx.vprocessor_registers->rdx = reinterpret_cast(vcpu) >> 32;
79 |
80 | // load guest state
81 | __svm_vmload(MmGetPhysicalAddress(&vcpu->guest_vmcb).QuadPart);
82 |
83 | // set the global interrupt flag (GIF), but still disable interrupts by
84 | // clearing IF. GIF must be set to return to the normal execution, but
85 | // interruptions are unwanted untill SVM is disabled as it would
86 | // execute random kernel-code in the host context.
87 | _disable();
88 | __svm_stgi();
89 |
90 |
91 | // disable svm and restore the guest rflags
92 | // this may enable interrupts
93 | __writemsr(IA32_MSR_EFER,
94 | __readmsr(IA32_MSR_EFER) & ~EFER_SVME);
95 |
96 | __writeeflags(vcpu->guest_vmcb.state_save_area.rflags);
97 | NT_ASSERT(vcpu->host_stack_layout.reserved1 == MAXUINT64);
98 | return guest_ctx.should_exit;
99 | }
100 |
101 | // update rax
102 | vcpu->guest_vmcb.state_save_area.rax = guest_ctx.vprocessor_registers->rax;
103 | NT_ASSERT(vcpu->host_stack_layout.reserved1 == MAXUINT64);
104 | return guest_ctx.should_exit;
105 | }
106 | }
107 | }
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/svm/svm/svm.cpp:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/sariaki/amd-hypervisor/99224ea59e8e6a616b03faabcb8cf2ac5228abd5/svm/svm/svm.cpp
--------------------------------------------------------------------------------
/svm/svm/svm.hpp:
--------------------------------------------------------------------------------
1 | #pragma once
2 | #include "def/cpu.hpp"
3 | #include "def/descriptors-info.hpp"
4 | #include "def/vmexit.hpp"
5 | #include "def/virtual-memory.hpp"
6 | #include "def/vmcb.hpp"
7 | #include "def/vprocessor-data.hpp"
8 | #include "../common-includes.hpp"
9 | #include "util/util.hpp"
10 | #include "handlers/handlers.hpp"
11 | #pragma warning (disable : 4245)
12 | #pragma warning (disable : 4390)
13 |
14 | namespace svm
15 | {
16 | __declspec(noreturn) extern "C" void __stdcall vmenter(PVOID host_rsp);
17 |
18 | bool check_support();
19 |
20 | void virtualize(PVOID);
21 |
22 | void devirtualize();
23 | }
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/svm/svm/util/util.cpp:
--------------------------------------------------------------------------------
1 | #include "util.hpp"
2 |
3 | namespace svm
4 | {
5 | namespace util
6 | {
7 | PVOID alloc_nonpaged_pool(size_t size)
8 | {
9 | PVOID memory;
10 |
11 | memory = ExAllocatePoolWithTag(NonPagedPool, size, 'vmm');
12 |
13 | if (memory)
14 | {
15 | NT_ASSERT(PAGE_ALIGN(memory) == memory);
16 | RtlZeroMemory(memory, size);
17 | }
18 |
19 | return memory;
20 | }
21 |
22 | void free_nonpaged_pool(PVOID base)
23 | {
24 | ExFreePoolWithTag(base, 'vmm');
25 | }
26 |
27 | PVOID alloc_contiguous_memory(size_t size)
28 | {
29 | PVOID memory;
30 | PHYSICAL_ADDRESS boundary, lowest, highest;
31 |
32 | boundary.QuadPart = lowest.QuadPart = 0;
33 | highest.QuadPart = -1;
34 |
35 | memory = MmAllocateContiguousMemorySpecifyCacheNode(size,
36 | lowest,
37 | highest,
38 | boundary,
39 | MmCached,
40 | MM_ANY_NODE_OK);
41 |
42 | if (memory)
43 | RtlZeroMemory(memory, size);
44 |
45 | return memory;
46 | }
47 |
48 | void free_contiguous_memory(PVOID base)
49 | {
50 | MmFreeContiguousMemory(base);
51 | }
52 |
53 | void setup_npt(pshared_vcpu_t shared_vprocessor_data)
54 | {
55 | uint64_t pdp_base_pa, pde_base_pa, translation_pa;
56 |
57 | // build one pml4 entry with subtables that control up to 512 gb of physical memory.
58 | // the pfn here points to a base physical address of the page directory pointer table
59 | pdp_base_pa = MmGetPhysicalAddress(&shared_vprocessor_data->pdp_entries).QuadPart;
60 | shared_vprocessor_data->pml4_entries[0].fields.page_frame_nr = pdp_base_pa >> PAGE_SHIFT;
61 |
62 | shared_vprocessor_data->pml4_entries[0].fields.valid = 1;
63 | shared_vprocessor_data->pml4_entries[0].fields.write = 1;
64 | shared_vprocessor_data->pml4_entries[0].fields.user = 1;
65 |
66 | // one pml4 entry controls 512 page directory pointer entries
67 | for (uint64_t i = 0; i < 512; i++)
68 | {
69 | // make the pfn point to the base physical address of the page directory table
70 | pde_base_pa = MmGetPhysicalAddress(&shared_vprocessor_data->pd_entries[i][0]).QuadPart;
71 | shared_vprocessor_data->pdp_entries[i].fields.page_frame_nr = pde_base_pa >> PAGE_SHIFT;
72 | shared_vprocessor_data->pdp_entries[i].fields.valid = 1;
73 | shared_vprocessor_data->pdp_entries[i].fields.write = 1;
74 | shared_vprocessor_data->pdp_entries[i].fields.user = 1;
75 |
76 | for (uint64_t j = 0; j < 512; j++)
77 | {
78 | // the page frame number points to a base physical address of
79 | // the system phyiscal address to be translated froma a guest physical address
80 | translation_pa = (i * 512) + j;
81 | shared_vprocessor_data->pd_entries[i][j].fields.page_frame_nr = translation_pa;
82 | shared_vprocessor_data->pd_entries[i][j].fields.valid = 1;
83 | shared_vprocessor_data->pd_entries[i][j].fields.write = 1;
84 | shared_vprocessor_data->pd_entries[i][j].fields.user = 1;
85 | shared_vprocessor_data->pd_entries[i][j].fields.large_page = 1;
86 | }
87 | }
88 | }
89 |
90 | void setup_msr_permissions_bitmap(PVOID msr_permissions)
91 | {
92 | RTL_BITMAP msr_bitmap;
93 | constexpr uint16_t bits_per_msr = 2;
94 | constexpr uint32_t msr_range_base = 0xC0000000;
95 | constexpr uint16_t bitmap_vector_size = 0x800 * CHAR_BIT; // 0x4000
96 |
97 | // initialize bitmap & clear bits
98 | // the AMD MSR bitmap is made up of four seperate bit vectors,
99 | // which are all 16 kbits (2 kbytes) or 0x4000 bytes in size
100 | RtlInitializeBitMap(&msr_bitmap,
101 | static_cast(msr_permissions),
102 | SVM_MSR_PERMISSIONS_MAP_SIZE * CHAR_BIT);
103 | RtlClearAllBits(&msr_bitmap);
104 |
105 | // write access interception for EFER MSR
106 | constexpr uint64_t offset_2nd_base = (IA32_MSR_EFER - msr_range_base) * bits_per_msr;
107 | constexpr uint64_t offset = offset_2nd_base + bitmap_vector_size;
108 | RtlSetBits(&msr_bitmap, offset + 1, 1);
109 | }
110 |
111 | typedef bool (*callback)(PVOID ctx);
112 |
113 | uint16_t execute_on_each_processor(callback callback, PVOID ctx)
114 | {
115 | NTSTATUS status;
116 | PROCESSOR_NUMBER processor_number;
117 | GROUP_AFFINITY affinity, previous_affinity;
118 | uint16_t i, processors;
119 |
120 | processors = KeQueryActiveProcessorCountEx(ALL_PROCESSOR_GROUPS);
121 |
122 | for (i = 0; i < processors; i++)
123 | {
124 | // get processor(s)
125 | status = KeGetProcessorNumberFromIndex(i, &processor_number);
126 | if (!NT_SUCCESS(status))
127 | return 0;
128 |
129 | // switch code execution from processor i
130 | affinity.Group = processor_number.Group;
131 | affinity.Mask = 1ULL << processor_number.Number;
132 | affinity.Reserved[0] = affinity.Reserved[1] = affinity.Reserved[2] = 0;
133 | KeSetSystemGroupAffinityThread(&affinity, &previous_affinity);
134 |
135 | bool success = callback(ctx);
136 |
137 | // continue previously executed code
138 | KeRevertToUserGroupAffinityThread(&previous_affinity);
139 |
140 | if (!success)
141 | return i;
142 |
143 | }
144 |
145 | return i;
146 | }
147 |
148 | bool is_hypervisor_vendor_installed()
149 | {
150 | int registers[4]; // eax ebx ecx edx
151 | char vedor_id[13];
152 |
153 | // when hypervisor is active, CPUID leaf 0x40000000
154 | // will return our own hypervisor vendor
155 | __cpuid(registers, static_cast(cpuid::hypervisor_vendor_id));
156 | RtlCopyMemory(vedor_id + 0, ®isters[1], sizeof(registers[1]));
157 | RtlCopyMemory(vedor_id + 4, ®isters[2], sizeof(registers[2]));
158 | RtlCopyMemory(vedor_id + 8, ®isters[3], sizeof(registers[3]));
159 | vedor_id[12] = ANSI_NULL;
160 |
161 | return (strcmp(vedor_id, "svm ") == 0);
162 | }
163 |
164 | uint16_t get_segment_access_rights(uint16_t segment_selector, ULONG_PTR gdt_base)
165 | {
166 | psegment_descriptor_t descriptor;
167 | segment_attributes_t attribute;
168 |
169 | // get a corresponding segment desciptor to segment selector
170 | descriptor = reinterpret_cast(
171 | gdt_base + (segment_selector & ~RPL_MASK));
172 |
173 | // get all attribute fields in the segment descriptor
174 | attribute.fields.type = descriptor->fields.type;
175 | attribute.fields.system = descriptor->fields.system;
176 | attribute.fields.dpl = descriptor->fields.dpl;
177 | attribute.fields.present = descriptor->fields.present;
178 | attribute.fields.avl = descriptor->fields.avl;
179 | attribute.fields.long_mode = descriptor->fields.long_mode;
180 | attribute.fields.default_bit = descriptor->fields.default_bit;
181 | attribute.fields.granularity = descriptor->fields.granularity;
182 | attribute.fields.reserved1 = 0;
183 |
184 | return attribute.value;
185 | }
186 |
187 | // https://wiki.osdev.org/Exceptions
188 | void general_protection_exeption(pvcpu_t vprocessor_data)
189 | {
190 | event_inj_t event;
191 |
192 | event.value = 0;
193 | event.fields.vector = 13;
194 | event.fields.type = 3;
195 | event.fields.error_code_valid = 1;
196 | event.fields.valid = 1;
197 | vprocessor_data->guest_vmcb.control_area.event_inj = event.value;
198 | }
199 |
200 | void invalid_opcode_exception(pvcpu_t vprocessor_data)
201 | {
202 | event_inj_t event;
203 |
204 | event.value = 0;
205 | event.fields.vector = 6;
206 | event.fields.type = 3;
207 | event.fields.error_code_valid = 1;
208 | event.fields.valid = 1;
209 | vprocessor_data->guest_vmcb.control_area.event_inj = event.value;
210 | }
211 | }
212 | }
--------------------------------------------------------------------------------
/svm/svm/util/util.hpp:
--------------------------------------------------------------------------------
1 | #include "../def/cpu.hpp"
2 | #include "../../common-includes.hpp"
3 | #include "../def/descriptors-info.hpp"
4 | #include "../def/vmcb.hpp"
5 | #include "../def/vprocessor-data.hpp"
6 | #include "../def/vmexit.hpp"
7 |
8 | #pragma warning (disable : 4244)
9 |
10 | namespace svm
11 | {
12 | namespace util
13 | {
14 | typedef bool (*callback)(PVOID ctx);
15 |
16 | PVOID alloc_nonpaged_pool(size_t size);
17 |
18 | void free_nonpaged_pool(PVOID base);
19 |
20 | PVOID alloc_contiguous_memory(size_t size);
21 |
22 | void free_contiguous_memory(PVOID base);
23 |
24 | void setup_npt(pshared_vcpu_t shared_vprocessor_data);
25 |
26 | void setup_msr_permissions_bitmap(PVOID msr_permissions);
27 |
28 | uint16_t execute_on_each_processor(callback callback, PVOID ctx);
29 |
30 | bool is_hypervisor_vendor_installed();
31 |
32 | uint16_t get_segment_access_rights(uint16_t segment_selector, ULONG_PTR gdt_base);
33 |
34 | void general_protection_exeption(pvcpu_t vprocessor_data);
35 |
36 | void invalid_opcode_exception(pvcpu_t vprocessor_data);
37 |
38 | uintptr_t get_kernel_dir_base();
39 |
40 | uint64_t random(int min, int max);
41 |
42 | PPHYSICAL_MEMORY_DESCRIPTOR get_physical_memory_ranges_descriptor();
43 | }
44 | }
--------------------------------------------------------------------------------
/svm/svm/vmenter.asm:
--------------------------------------------------------------------------------
1 |
2 | .const
3 |
4 | KTRAP_FRAME_SIZE equ 190h
5 | MACHINE_FRAME_SIZE equ 28h
6 |
7 | .code
8 |
9 | extern handle_vmexit : proc
10 |
11 | PUSHAQ macro
12 | push rax
13 | push rcx
14 | push rdx
15 | push rbx
16 | push -1
17 | push rbp
18 | push rsi
19 | push rdi
20 | push r8
21 | push r9
22 | push r10
23 | push r11
24 | push r12
25 | push r13
26 | push r14
27 | push r15
28 | endm
29 |
30 | POPAQ macro
31 | pop r15
32 | pop r14
33 | pop r13
34 | pop r12
35 | pop r11
36 | pop r10
37 | pop r9
38 | pop r8
39 | pop rdi
40 | pop rsi
41 | pop rbp
42 | pop rbx
43 | pop rbx
44 | pop rdx
45 | pop rcx
46 | pop rax
47 | endm
48 |
49 | ; __stdcall uses RCX, RDX, R8, R9 in this order
50 | vmenter proc frame
51 | ; update the current stack pointer with the host RSP. this protects
52 | ; values stored on stack for the hypervisor from being overwritten by
53 | ; the guest due to a use of the same stack memory.
54 | mov rsp, rcx
55 |
56 | svm_loop:
57 | ; run the loop to executed the guest and handle vmexit.
58 | ; below is the current stack layout.
59 |
60 | ; rsp -> 0x...fd0 guest_vmcb_pa
61 | ; 0x...fd8 host_vmcb_pa
62 | ; 0x...fe0 self
63 | ; 0x...fe8 shared_vcpu_data
64 | ; 0x...ff0 padding1
65 | ; 0x...ff8 reserved1
66 |
67 | ; load previously saved guest state passed as a parameter from VMCB
68 | mov rax, [rsp] ; physical address of the guest vmcb
69 | vmload rax
70 |
71 | ; execute guest utill vmexit gets called
72 | vmrun rax ; switch to guest
73 |
74 | ; when vmexit does occur, save guest state to the vmcb
75 | ; make sure this is saved because host code will destroy it
76 | vmsave rax
77 |
78 | ; optionally, allocate the trap frame so that windbg can display a stack trace of the guest
79 | .pushframe
80 | sub rsp, KTRAP_FRAME_SIZE
81 | .allocstack KTRAP_FRAME_SIZE - MACHINE_FRAME_SIZE + 100h
82 |
83 | ; push all guest's GPRs since those are not saved anywhere by the
84 | ; processor on vmexit and will thereby otherwise be lost
85 | PUSHAQ ; stack pointer decreased 8 * 16
86 |
87 | ; prepare parameters for handle_vmexit.
88 | mov rdx, rsp ; rdx <= guest registers
89 | mov rcx, [rsp + 8 * 18 + KTRAP_FRAME_SIZE] ; rcx <= virtual processor data
90 |
91 | ; allocate stack for homing space (0x20)
92 | ; and volatile XMM registers(0x60)
93 | sub rsp, 80h
94 |
95 | ; save those registers because host code may destroy
96 | ; any of those registers.
97 | ; XMM6-15 are not saved because those should be
98 | ; preserved (those are non volatile registers).
99 | movaps xmmword ptr [rsp + 20h], xmm0
100 | movaps xmmword ptr [rsp + 30h], xmm1
101 | movaps xmmword ptr [rsp + 40h], xmm2
102 | movaps xmmword ptr [rsp + 50h], xmm3
103 | movaps xmmword ptr [rsp + 60h], xmm4
104 | movaps xmmword ptr [rsp + 70h], xmm5
105 | .endprolog
106 |
107 | ; call our vmexit handler with the args we prepared
108 | call handle_vmexit
109 |
110 | ; restore all xmm registers we saved
111 | movaps xmm5, xmmword ptr [rsp + 70h]
112 | movaps xmm4, xmmword ptr [rsp + 60h]
113 | movaps xmm3, xmmword ptr [rsp + 50h]
114 | movaps xmm2, xmmword ptr [rsp + 40h]
115 | movaps xmm1, xmmword ptr [rsp + 30h]
116 | movaps xmm0, xmmword ptr [rsp + 20h]
117 | add rsp, 80h
118 |
119 |
120 | ; check if handle_vmexit was successfull
121 | test al, al
122 | ; restore all gpr's we saved
123 | POPAQ
124 |
125 | ; If guest_ctx.ExitVm is true, this function exits the loop
126 | ; otherwise we continue the loop and resume the guest
127 | jnz vmexit ; if (ExitVm) jmp SvLV20
128 | ; else { restore rsp and go back into loop }
129 | add rsp, KTRAP_FRAME_SIZE
130 | jmp svm_loop
131 |
132 | vmexit:
133 | ; an exit has been requested
134 | ; restore the original stack ptr and return to the next instruction of cpuid
135 | ; RBX : address to return
136 | ; RCX : original stack pointer to restore
137 | ; EDX:EAX : address of per processor data for this processor
138 | mov rsp, rcx
139 |
140 | ; update RCX with the magic value
141 | mov ecx, 'svm'
142 |
143 | ; return to the next instruction of CPUID
144 | jmp rbx
145 | vmenter endp
146 |
147 | end
--------------------------------------------------------------------------------
/usermode/main.cpp:
--------------------------------------------------------------------------------
1 | #include
2 | #include
3 | #include
4 |
5 | std::string get_vendor_id()
6 | {
7 | int registers[4]; // eax ebx ecx edx
8 | char vedor_id[13];
9 |
10 | // when hypervisor is active, CPUID leaf 0x40000000
11 | // should return our own hypervisor vendor
12 | __cpuid(registers, 0x40000000);
13 | RtlCopyMemory(vedor_id + 0, ®isters[1], sizeof(registers[1]));
14 | RtlCopyMemory(vedor_id + 4, ®isters[2], sizeof(registers[2]));
15 | RtlCopyMemory(vedor_id + 8, ®isters[3], sizeof(registers[3]));
16 | vedor_id[12] = ANSI_NULL;
17 |
18 | return vedor_id;
19 | }
20 |
21 | int main()
22 | {
23 | std::printf("[§] initializing\n");
24 | std::printf("[§] hypervisor vendor -> %s\n", get_vendor_id());
25 | std::getchar();
26 | return 0;
27 | }
28 |
--------------------------------------------------------------------------------
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