├── README.md ├── VariantSubsystemModel1 ├── ARXML files │ ├── VariantSubsystemModel1_component.arxml │ ├── VariantSubsystemModel1_datatype.arxml │ ├── VariantSubsystemModel1_implementation.arxml │ └── VariantSubsystemModel1_interface.arxml ├── C source code files │ ├── VariantSubsystemModel1.c │ └── VariantSubsystemModel1.h ├── VariantSubsystemModel1.c ├── VariantSubsystemModel1.h ├── VariantSubsystemModel1.slx └── VariantSubsystemModel1.zip ├── VariantSubsystemModel2 ├── ARXML files │ ├── VariantSubsystemModel2_component.arxml │ ├── VariantSubsystemModel2_datatype.arxml │ ├── VariantSubsystemModel2_implementation.arxml │ └── VariantSubsystemModel2_interface.arxml ├── C source code files │ ├── VariantSubsystemModel2.c │ └── VariantSubsystemModel2.h ├── VariantSubsystemModel2.c ├── VariantSubsystemModel2.h ├── VariantSubsystemModel2.slx └── VariantSubsystemModel2.zip └── VariantSubsystemModel3 ├── ARXML files ├── VariantSubsystemModel3_component.arxml ├── VariantSubsystemModel3_datatype.arxml ├── VariantSubsystemModel3_implementation.arxml └── VariantSubsystemModel3_interface.arxml ├── C source code files ├── VariantSubsystemModel3.c └── VariantSubsystemModel3.h ├── VariantSubsystemModel3.c ├── VariantSubsystemModel3.h ├── VariantSubsystemModel3.slx └── VariantSubsystemModel3.zip /README.md: -------------------------------------------------------------------------------- 1 | # Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs 2 | 3 | [![Codacy Badge](https://api.codacy.com/project/badge/Grade/3147275907024c0b977b4630c313ea40)](https://www.codacy.com/manual/saurabhyadav789/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs?utm_source=github.com&utm_medium=referral&utm_content=saurabhyadav789/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs&utm_campaign=Badge_Grade) 4 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/ARXML files/VariantSubsystemModel1_component.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | variant_subsystems_pkg 13 | 14 | 15 | variant_subsystems_swc 16 | 17 | 18 | variant_subsystems 19 | 20 | 21 | Out1 22 | 23 | 24 | /variant_subsystems_pkg/variant_subsystems_if/Out1/Out1 25 | NONE 26 | false 27 | 28 | 29 | DefaultInitValue_Double 30 | /variant_subsystems_pkg/variant_subsystems_dt/Ground/DefaultInitValue_Double 31 | 32 | 33 | 34 | 35 | /variant_subsystems_pkg/variant_subsystems_if/Out1 36 | 37 | 38 | 39 | 40 | variant_subsystems 41 | 42 | 43 | Event_Runnable_Step 44 | /variant_subsystems_pkg/variant_subsystems_swc/variant_subsystems/variant_subsystems/Runnable_Step 45 | 1 46 | 47 | 48 | NO-SUPPORT 49 | 50 | 51 | Runnable_Init 52 | 0 53 | false 54 | Runnable_Init 55 | 56 | 57 | Runnable_Step 58 | 0 59 | false 60 | 61 | 62 | OUT_Out1_Out1 63 | 64 | 65 | /variant_subsystems_pkg/variant_subsystems_swc/variant_subsystems/Out1 66 | /variant_subsystems_pkg/variant_subsystems_if/Out1/Out1 67 | 68 | 69 | 70 | 71 | Runnable_Step 72 | 73 | 74 | false 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/ARXML files/VariantSubsystemModel1_datatype.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | variant_subsystems_pkg 13 | 14 | 15 | variant_subsystems_dt 16 | 17 | 18 | Double 19 | VALUE 20 | 21 | 22 | 23 | /variant_subsystems_pkg/variant_subsystems_dt/SwBaseTypes/float64 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | Ground 32 | 33 | 34 | DefaultInitValue_Double 35 | 36 | 37 | DefaultInitValue_Double 38 | 0 39 | 40 | 41 | 42 | 43 | 44 | 45 | SwBaseTypes 46 | 47 | 48 | float64 49 | FIXED_LENGTH 50 | 64 51 | IEEE754 52 | float64 53 | 54 | 55 | 56 | 57 | 58 | 59 | variant_subsystems_imp 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/ARXML files/VariantSubsystemModel1_implementation.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | variant_subsystems_pkg 13 | 14 | 15 | variant_subsystems_imp 16 | 17 | 18 | variant_subsystems 19 | 20 | 21 | Code 22 | 23 | 24 | VariantSubsystemModel1_c 25 | SWSRC 26 | 27 | 28 | VariantSubsystemModel1_h 29 | SWHDR 30 | 31 | 32 | rtwtypes_h 33 | SWHDR 34 | 35 | 36 | 37 | 38 | C 39 | 40 | RsrcCons_VariantSubsystemModel1 41 | 42 | 1.54.1 43 | Embedded Coder 6.12 (R2017a) 16-Feb-2017 44 | 0 45 | /variant_subsystems_pkg/variant_subsystems_swc/variant_subsystems/variant_subsystems 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/ARXML files/VariantSubsystemModel1_interface.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | variant_subsystems_pkg 13 | 14 | 15 | variant_subsystems_if 16 | 17 | 18 | Out1 19 | false 20 | 21 | 22 | Out1 23 | VALUE 24 | 25 | 26 | 27 | READ-ONLY 28 | STANDARD 29 | 30 | 31 | 32 | /variant_subsystems_pkg/variant_subsystems_dt/Double 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/C source code files/VariantSubsystemModel1.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel1.c 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel1'. 5 | * 6 | * Model version : 1.54 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 15:46:08 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #include "VariantSubsystemModel1.h" 19 | 20 | /* Block signals and states (auto storage) */ 21 | DW rtDW; 22 | 23 | /* Model step function */ 24 | void Runnable_Step(void) 25 | { 26 | int32_T rtb_Sensor2; 27 | 28 | /* DiscretePulseGenerator: '/Sensor2' */ 29 | rtb_Sensor2 = ((rtDW.clockTickCounter < 5) && (rtDW.clockTickCounter >= 0)); 30 | if (rtDW.clockTickCounter >= 9) { 31 | rtDW.clockTickCounter = 0; 32 | } else { 33 | rtDW.clockTickCounter++; 34 | } 35 | 36 | /* End of DiscretePulseGenerator: '/Sensor2' */ 37 | 38 | /* Outport: '/Out1' incorporates: 39 | * Product: '/Heater Switch' 40 | */ 41 | Rte_IWrite_Runnable_Step_Out1_Out1((real_T)rtb_Sensor2 * 9.0486E+7); 42 | } 43 | 44 | /* Model initialize function */ 45 | void Runnable_Init(void) 46 | { 47 | /* (no initialization code required) */ 48 | } 49 | 50 | /* 51 | * File trailer for generated code. 52 | * 53 | * [EOF] 54 | */ 55 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/C source code files/VariantSubsystemModel1.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel1.h 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel1'. 5 | * 6 | * Model version : 1.54 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 15:46:08 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_VariantSubsystemModel1_h_ 19 | #define RTW_HEADER_VariantSubsystemModel1_h_ 20 | #ifndef VariantSubsystemModel1_COMMON_INCLUDES_ 21 | # define VariantSubsystemModel1_COMMON_INCLUDES_ 22 | #include "rtwtypes.h" 23 | #include "Rte_variant_subsystems.h" 24 | #endif /* VariantSubsystemModel1_COMMON_INCLUDES_ */ 25 | 26 | /* Macros for accessing real-time model data structure */ 27 | 28 | /* Block signals and states (auto storage) for system '' */ 29 | typedef struct tag_DW { 30 | int32_T clockTickCounter; /* '/Sensor2' */ 31 | } DW; 32 | 33 | /* Block signals and states (auto storage) */ 34 | extern DW rtDW; 35 | 36 | /*- 37 | * These blocks were eliminated from the model due to optimizations: 38 | * 39 | * Block '/Scope' : Unused code path elimination 40 | * Block '/Sensor1' : Unused code path elimination 41 | */ 42 | 43 | /*- 44 | * The generated code includes comments that allow you to trace directly 45 | * back to the appropriate location in the model. The basic format 46 | * is /block_name, where system is the system number (uniquely 47 | * assigned by Simulink) and block_name is the name of the block. 48 | * 49 | * Use the MATLAB hilite_system command to trace the generated code back 50 | * to the model. For example, 51 | * 52 | * hilite_system('') - opens system 3 53 | * hilite_system('/Kp') - opens and selects block Kp which resides in S3 54 | * 55 | * Here is the system hierarchy for this model 56 | * 57 | * '' : 'VariantSubsystemModel1' 58 | * '' : 'VariantSubsystemModel1/Controller' 59 | * '' : 'VariantSubsystemModel1/Controller/Heater' 60 | * '' : 'VariantSubsystemModel1/Controller/Thermostat' 61 | */ 62 | #endif /* RTW_HEADER_VariantSubsystemModel1_h_ */ 63 | 64 | /* 65 | * File trailer for generated code. 66 | * 67 | * [EOF] 68 | */ 69 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/VariantSubsystemModel1.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel1.c 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel1'. 5 | * 6 | * Model version : 1.54 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 15:46:08 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #include "VariantSubsystemModel1.h" 19 | 20 | /* Block signals and states (auto storage) */ 21 | DW rtDW; 22 | 23 | /* Model step function */ 24 | void Runnable_Step(void) 25 | { 26 | int32_T rtb_Sensor2; 27 | 28 | /* DiscretePulseGenerator: '/Sensor2' */ 29 | rtb_Sensor2 = ((rtDW.clockTickCounter < 5) && (rtDW.clockTickCounter >= 0)); 30 | if (rtDW.clockTickCounter >= 9) { 31 | rtDW.clockTickCounter = 0; 32 | } else { 33 | rtDW.clockTickCounter++; 34 | } 35 | 36 | /* End of DiscretePulseGenerator: '/Sensor2' */ 37 | 38 | /* Outport: '/Out1' incorporates: 39 | * Product: '/Heater Switch' 40 | */ 41 | Rte_IWrite_Runnable_Step_Out1_Out1((real_T)rtb_Sensor2 * 9.0486E+7); 42 | } 43 | 44 | /* Model initialize function */ 45 | void Runnable_Init(void) 46 | { 47 | /* (no initialization code required) */ 48 | } 49 | 50 | /* 51 | * File trailer for generated code. 52 | * 53 | * [EOF] 54 | */ 55 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/VariantSubsystemModel1.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel1.h 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel1'. 5 | * 6 | * Model version : 1.54 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 15:46:08 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_VariantSubsystemModel1_h_ 19 | #define RTW_HEADER_VariantSubsystemModel1_h_ 20 | #ifndef VariantSubsystemModel1_COMMON_INCLUDES_ 21 | # define VariantSubsystemModel1_COMMON_INCLUDES_ 22 | #include "rtwtypes.h" 23 | #include "Rte_variant_subsystems.h" 24 | #endif /* VariantSubsystemModel1_COMMON_INCLUDES_ */ 25 | 26 | /* Macros for accessing real-time model data structure */ 27 | 28 | /* Block signals and states (auto storage) for system '' */ 29 | typedef struct tag_DW { 30 | int32_T clockTickCounter; /* '/Sensor2' */ 31 | } DW; 32 | 33 | /* Block signals and states (auto storage) */ 34 | extern DW rtDW; 35 | 36 | /*- 37 | * These blocks were eliminated from the model due to optimizations: 38 | * 39 | * Block '/Scope' : Unused code path elimination 40 | * Block '/Sensor1' : Unused code path elimination 41 | */ 42 | 43 | /*- 44 | * The generated code includes comments that allow you to trace directly 45 | * back to the appropriate location in the model. The basic format 46 | * is /block_name, where system is the system number (uniquely 47 | * assigned by Simulink) and block_name is the name of the block. 48 | * 49 | * Use the MATLAB hilite_system command to trace the generated code back 50 | * to the model. For example, 51 | * 52 | * hilite_system('') - opens system 3 53 | * hilite_system('/Kp') - opens and selects block Kp which resides in S3 54 | * 55 | * Here is the system hierarchy for this model 56 | * 57 | * '' : 'VariantSubsystemModel1' 58 | * '' : 'VariantSubsystemModel1/Controller' 59 | * '' : 'VariantSubsystemModel1/Controller/Heater' 60 | * '' : 'VariantSubsystemModel1/Controller/Thermostat' 61 | */ 62 | #endif /* RTW_HEADER_VariantSubsystemModel1_h_ */ 63 | 64 | /* 65 | * File trailer for generated code. 66 | * 67 | * [EOF] 68 | */ 69 | -------------------------------------------------------------------------------- /VariantSubsystemModel1/VariantSubsystemModel1.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/saurabh-iiitu/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs/867657a4efff85a22009dc2083d62a6203d12b11/VariantSubsystemModel1/VariantSubsystemModel1.slx -------------------------------------------------------------------------------- /VariantSubsystemModel1/VariantSubsystemModel1.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/saurabh-iiitu/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs/867657a4efff85a22009dc2083d62a6203d12b11/VariantSubsystemModel1/VariantSubsystemModel1.zip -------------------------------------------------------------------------------- /VariantSubsystemModel2/ARXML files/VariantSubsystemModel2_component.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel2_pkg 13 | 14 | 15 | VariantSubsystemModel2_swc 16 | 17 | 18 | VariantSubsystemModel2 19 | 20 | 21 | Out1 22 | 23 | 24 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_if/Out1/Out1 25 | NONE 26 | false 27 | 28 | 29 | DefaultInitValue_Double 30 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_dt/Ground/DefaultInitValue_Double 31 | 32 | 33 | 34 | 35 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_if/Out1 36 | 37 | 38 | 39 | 40 | VariantSubsystemModel2 41 | 42 | 43 | Event_Runnable_Step 44 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_swc/VariantSubsystemModel2/VariantSubsystemModel2/Runnable_Step 45 | 1 46 | 47 | 48 | NO-SUPPORT 49 | 50 | 51 | Runnable_Init 52 | 0 53 | false 54 | Runnable_Init 55 | 56 | 57 | Runnable_Step 58 | 0 59 | false 60 | 61 | 62 | OUT_Out1_Out1 63 | 64 | 65 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_swc/VariantSubsystemModel2/Out1 66 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_if/Out1/Out1 67 | 68 | 69 | 70 | 71 | Runnable_Step 72 | 73 | 74 | false 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/ARXML files/VariantSubsystemModel2_datatype.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel2_pkg 13 | 14 | 15 | VariantSubsystemModel2_dt 16 | 17 | 18 | Double 19 | VALUE 20 | 21 | 22 | 23 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_dt/SwBaseTypes/float64 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | Ground 32 | 33 | 34 | DefaultInitValue_Double 35 | 36 | 37 | DefaultInitValue_Double 38 | 0 39 | 40 | 41 | 42 | 43 | 44 | 45 | SwBaseTypes 46 | 47 | 48 | float64 49 | FIXED_LENGTH 50 | 64 51 | IEEE754 52 | float64 53 | 54 | 55 | 56 | 57 | 58 | 59 | VariantSubsystemModel2_imp 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/ARXML files/VariantSubsystemModel2_implementation.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel2_pkg 13 | 14 | 15 | VariantSubsystemModel2_imp 16 | 17 | 18 | VariantSubsystemModel2 19 | 20 | 21 | Code 22 | 23 | 24 | VariantSubsystemModel2_c 25 | SWSRC 26 | 27 | 28 | VariantSubsystemModel2_h 29 | SWHDR 30 | 31 | 32 | rtwtypes_h 33 | SWHDR 34 | 35 | 36 | 37 | 38 | C 39 | 40 | RsrcCons_VariantSubsystemModel2 41 | 42 | 1.5.1 43 | Embedded Coder 6.12 (R2017a) 16-Feb-2017 44 | 0 45 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_swc/VariantSubsystemModel2/VariantSubsystemModel2 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/ARXML files/VariantSubsystemModel2_interface.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel2_pkg 13 | 14 | 15 | VariantSubsystemModel2_if 16 | 17 | 18 | Out1 19 | false 20 | 21 | 22 | Out1 23 | VALUE 24 | 25 | 26 | 27 | READ-ONLY 28 | STANDARD 29 | 30 | 31 | 32 | /VariantSubsystemModel2_pkg/VariantSubsystemModel2_dt/Double 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/C source code files/VariantSubsystemModel2.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel2.c 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel2'. 5 | * 6 | * Model version : 1.5 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:26:29 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #include "VariantSubsystemModel2.h" 19 | 20 | /* Block signals and states (auto storage) */ 21 | DW rtDW; 22 | 23 | /* Model step function */ 24 | void Runnable_Step(void) 25 | { 26 | int32_T rtb_In1; 27 | 28 | /* Outport: '/Out1' incorporates: 29 | * DiscreteIntegrator: '/Discrete-Time Integrator' 30 | */ 31 | Rte_IWrite_Runnable_Step_Out1_Out1(rtDW.DiscreteTimeIntegrator_DSTATE); 32 | 33 | /* DiscretePulseGenerator: '/In1' */ 34 | rtb_In1 = ((rtDW.clockTickCounter < 5) && (rtDW.clockTickCounter >= 0)); 35 | if (rtDW.clockTickCounter >= 9) { 36 | rtDW.clockTickCounter = 0; 37 | } else { 38 | rtDW.clockTickCounter++; 39 | } 40 | 41 | /* End of DiscretePulseGenerator: '/In1' */ 42 | 43 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator' incorporates: 44 | * DiscreteIntegrator: '/Discrete-Time Integrator1' 45 | */ 46 | rtDW.DiscreteTimeIntegrator_DSTATE += rtDW.DiscreteTimeIntegrator1_DSTATE; 47 | 48 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator1' incorporates: 49 | * Gain: '/Gain' 50 | */ 51 | rtDW.DiscreteTimeIntegrator1_DSTATE += 2.0 * (real_T)rtb_In1; 52 | } 53 | 54 | /* Model initialize function */ 55 | void Runnable_Init(void) 56 | { 57 | /* (no initialization code required) */ 58 | } 59 | 60 | /* 61 | * File trailer for generated code. 62 | * 63 | * [EOF] 64 | */ 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/C source code files/VariantSubsystemModel2.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel2.h 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel2'. 5 | * 6 | * Model version : 1.5 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:26:29 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_VariantSubsystemModel2_h_ 19 | #define RTW_HEADER_VariantSubsystemModel2_h_ 20 | #ifndef VariantSubsystemModel2_COMMON_INCLUDES_ 21 | # define VariantSubsystemModel2_COMMON_INCLUDES_ 22 | #include "rtwtypes.h" 23 | #include "Rte_VariantSubsystemModel2.h" 24 | #endif /* VariantSubsystemModel2_COMMON_INCLUDES_ */ 25 | 26 | /* Macros for accessing real-time model data structure */ 27 | 28 | /* Block signals and states (auto storage) for system '' */ 29 | typedef struct tag_DW { 30 | real_T DiscreteTimeIntegrator_DSTATE;/* '/Discrete-Time Integrator' */ 31 | real_T DiscreteTimeIntegrator1_DSTATE;/* '/Discrete-Time Integrator1' */ 32 | int32_T clockTickCounter; /* '/In1' */ 33 | } DW; 34 | 35 | /* Block signals and states (auto storage) */ 36 | extern DW rtDW; 37 | 38 | /*- 39 | * These blocks were eliminated from the model due to optimizations: 40 | * 41 | * Block '/In2' : Unused code path elimination 42 | * Block '/Scope' : Unused code path elimination 43 | */ 44 | 45 | /*- 46 | * The generated code includes comments that allow you to trace directly 47 | * back to the appropriate location in the model. The basic format 48 | * is /block_name, where system is the system number (uniquely 49 | * assigned by Simulink) and block_name is the name of the block. 50 | * 51 | * Use the MATLAB hilite_system command to trace the generated code back 52 | * to the model. For example, 53 | * 54 | * hilite_system('') - opens system 3 55 | * hilite_system('/Kp') - opens and selects block Kp which resides in S3 56 | * 57 | * Here is the system hierarchy for this model 58 | * 59 | * '' : 'VariantSubsystemModel2' 60 | * '' : 'VariantSubsystemModel2/Variant Subsystem' 61 | * '' : 'VariantSubsystemModel2/Variant Subsystem/Car' 62 | * '' : 'VariantSubsystemModel2/Variant Subsystem/Thermostat' 63 | */ 64 | #endif /* RTW_HEADER_VariantSubsystemModel2_h_ */ 65 | 66 | /* 67 | * File trailer for generated code. 68 | * 69 | * [EOF] 70 | */ 71 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/VariantSubsystemModel2.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel2.c 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel2'. 5 | * 6 | * Model version : 1.5 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:26:29 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #include "VariantSubsystemModel2.h" 19 | 20 | /* Block signals and states (auto storage) */ 21 | DW rtDW; 22 | 23 | /* Model step function */ 24 | void Runnable_Step(void) 25 | { 26 | int32_T rtb_In1; 27 | 28 | /* Outport: '/Out1' incorporates: 29 | * DiscreteIntegrator: '/Discrete-Time Integrator' 30 | */ 31 | Rte_IWrite_Runnable_Step_Out1_Out1(rtDW.DiscreteTimeIntegrator_DSTATE); 32 | 33 | /* DiscretePulseGenerator: '/In1' */ 34 | rtb_In1 = ((rtDW.clockTickCounter < 5) && (rtDW.clockTickCounter >= 0)); 35 | if (rtDW.clockTickCounter >= 9) { 36 | rtDW.clockTickCounter = 0; 37 | } else { 38 | rtDW.clockTickCounter++; 39 | } 40 | 41 | /* End of DiscretePulseGenerator: '/In1' */ 42 | 43 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator' incorporates: 44 | * DiscreteIntegrator: '/Discrete-Time Integrator1' 45 | */ 46 | rtDW.DiscreteTimeIntegrator_DSTATE += rtDW.DiscreteTimeIntegrator1_DSTATE; 47 | 48 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator1' incorporates: 49 | * Gain: '/Gain' 50 | */ 51 | rtDW.DiscreteTimeIntegrator1_DSTATE += 2.0 * (real_T)rtb_In1; 52 | } 53 | 54 | /* Model initialize function */ 55 | void Runnable_Init(void) 56 | { 57 | /* (no initialization code required) */ 58 | } 59 | 60 | /* 61 | * File trailer for generated code. 62 | * 63 | * [EOF] 64 | */ 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/VariantSubsystemModel2.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel2.h 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel2'. 5 | * 6 | * Model version : 1.5 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:26:29 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_VariantSubsystemModel2_h_ 19 | #define RTW_HEADER_VariantSubsystemModel2_h_ 20 | #ifndef VariantSubsystemModel2_COMMON_INCLUDES_ 21 | # define VariantSubsystemModel2_COMMON_INCLUDES_ 22 | #include "rtwtypes.h" 23 | #include "Rte_VariantSubsystemModel2.h" 24 | #endif /* VariantSubsystemModel2_COMMON_INCLUDES_ */ 25 | 26 | /* Macros for accessing real-time model data structure */ 27 | 28 | /* Block signals and states (auto storage) for system '' */ 29 | typedef struct tag_DW { 30 | real_T DiscreteTimeIntegrator_DSTATE;/* '/Discrete-Time Integrator' */ 31 | real_T DiscreteTimeIntegrator1_DSTATE;/* '/Discrete-Time Integrator1' */ 32 | int32_T clockTickCounter; /* '/In1' */ 33 | } DW; 34 | 35 | /* Block signals and states (auto storage) */ 36 | extern DW rtDW; 37 | 38 | /*- 39 | * These blocks were eliminated from the model due to optimizations: 40 | * 41 | * Block '/In2' : Unused code path elimination 42 | * Block '/Scope' : Unused code path elimination 43 | */ 44 | 45 | /*- 46 | * The generated code includes comments that allow you to trace directly 47 | * back to the appropriate location in the model. The basic format 48 | * is /block_name, where system is the system number (uniquely 49 | * assigned by Simulink) and block_name is the name of the block. 50 | * 51 | * Use the MATLAB hilite_system command to trace the generated code back 52 | * to the model. For example, 53 | * 54 | * hilite_system('') - opens system 3 55 | * hilite_system('/Kp') - opens and selects block Kp which resides in S3 56 | * 57 | * Here is the system hierarchy for this model 58 | * 59 | * '' : 'VariantSubsystemModel2' 60 | * '' : 'VariantSubsystemModel2/Variant Subsystem' 61 | * '' : 'VariantSubsystemModel2/Variant Subsystem/Car' 62 | * '' : 'VariantSubsystemModel2/Variant Subsystem/Thermostat' 63 | */ 64 | #endif /* RTW_HEADER_VariantSubsystemModel2_h_ */ 65 | 66 | /* 67 | * File trailer for generated code. 68 | * 69 | * [EOF] 70 | */ 71 | -------------------------------------------------------------------------------- /VariantSubsystemModel2/VariantSubsystemModel2.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/saurabh-iiitu/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs/867657a4efff85a22009dc2083d62a6203d12b11/VariantSubsystemModel2/VariantSubsystemModel2.slx -------------------------------------------------------------------------------- /VariantSubsystemModel2/VariantSubsystemModel2.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/saurabh-iiitu/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs/867657a4efff85a22009dc2083d62a6203d12b11/VariantSubsystemModel2/VariantSubsystemModel2.zip -------------------------------------------------------------------------------- /VariantSubsystemModel3/ARXML files/VariantSubsystemModel3_component.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel3_pkg 13 | 14 | 15 | VariantSubsystemModel3_swc 16 | 17 | 18 | VariantSubsystemModel3 19 | 20 | 21 | Out1 22 | 23 | 24 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_if/Out1/Out1 25 | NONE 26 | false 27 | 28 | 29 | DefaultInitValue_Double 30 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_dt/Ground/DefaultInitValue_Double 31 | 32 | 33 | 34 | 35 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_if/Out1 36 | 37 | 38 | 39 | 40 | VariantSubsystemModel3 41 | 42 | 43 | Event_Runnable_Step 44 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_swc/VariantSubsystemModel3/VariantSubsystemModel3/Runnable_Step 45 | 1 46 | 47 | 48 | NO-SUPPORT 49 | 50 | 51 | Runnable_Init 52 | 0 53 | false 54 | Runnable_Init 55 | 56 | 57 | Runnable_Step 58 | 0 59 | false 60 | 61 | 62 | OUT_Out1_Out1 63 | 64 | 65 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_swc/VariantSubsystemModel3/Out1 66 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_if/Out1/Out1 67 | 68 | 69 | 70 | 71 | Runnable_Step 72 | 73 | 74 | false 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/ARXML files/VariantSubsystemModel3_datatype.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel3_pkg 13 | 14 | 15 | VariantSubsystemModel3_dt 16 | 17 | 18 | Double 19 | VALUE 20 | 21 | 22 | 23 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_dt/SwBaseTypes/float64 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | Ground 32 | 33 | 34 | DefaultInitValue_Double 35 | 36 | 37 | DefaultInitValue_Double 38 | 0 39 | 40 | 41 | 42 | 43 | 44 | 45 | SwBaseTypes 46 | 47 | 48 | float64 49 | FIXED_LENGTH 50 | 64 51 | IEEE754 52 | float64 53 | 54 | 55 | 56 | 57 | 58 | 59 | VariantSubsystemModel3_imp 60 | 61 | 62 | 63 | 64 | 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/ARXML files/VariantSubsystemModel3_implementation.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel3_pkg 13 | 14 | 15 | VariantSubsystemModel3_imp 16 | 17 | 18 | VariantSubsystemModel3 19 | 20 | 21 | Code 22 | 23 | 24 | VariantSubsystemModel3_c 25 | SWSRC 26 | 27 | 28 | VariantSubsystemModel3_h 29 | SWHDR 30 | 31 | 32 | rtwtypes_h 33 | SWHDR 34 | 35 | 36 | 37 | 38 | C 39 | 40 | RsrcCons_VariantSubsystemModel3 41 | 42 | 1.2.1 43 | Embedded Coder 6.12 (R2017a) 16-Feb-2017 44 | 0 45 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_swc/VariantSubsystemModel3/VariantSubsystemModel3 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/ARXML files/VariantSubsystemModel3_interface.arxml: -------------------------------------------------------------------------------- 1 | 2 | 9 | 10 | 11 | 12 | VariantSubsystemModel3_pkg 13 | 14 | 15 | VariantSubsystemModel3_if 16 | 17 | 18 | Out1 19 | false 20 | 21 | 22 | Out1 23 | VALUE 24 | 25 | 26 | 27 | READ-ONLY 28 | STANDARD 29 | 30 | 31 | 32 | /VariantSubsystemModel3_pkg/VariantSubsystemModel3_dt/Double 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/C source code files/VariantSubsystemModel3.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel3.c 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel3'. 5 | * 6 | * Model version : 1.2 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:33:13 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #include "VariantSubsystemModel3.h" 19 | 20 | /* Block signals and states (auto storage) */ 21 | DW rtDW; 22 | 23 | /* Model step function */ 24 | void Runnable_Step(void) 25 | { 26 | int32_T rtb_In; 27 | 28 | /* Outport: '/Out1' incorporates: 29 | * DiscreteIntegrator: '/Discrete-Time Integrator' 30 | */ 31 | Rte_IWrite_Runnable_Step_Out1_Out1(rtDW.DiscreteTimeIntegrator_DSTATE); 32 | 33 | /* DiscretePulseGenerator: '/In' */ 34 | rtb_In = ((rtDW.clockTickCounter < 5) && (rtDW.clockTickCounter >= 0)); 35 | if (rtDW.clockTickCounter >= 9) { 36 | rtDW.clockTickCounter = 0; 37 | } else { 38 | rtDW.clockTickCounter++; 39 | } 40 | 41 | /* End of DiscretePulseGenerator: '/In' */ 42 | 43 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator' incorporates: 44 | * DiscreteIntegrator: '/Discrete-Time Integrator1' 45 | */ 46 | rtDW.DiscreteTimeIntegrator_DSTATE += rtDW.DiscreteTimeIntegrator1_DSTATE; 47 | 48 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator1' incorporates: 49 | * Gain: '/Gain' 50 | */ 51 | rtDW.DiscreteTimeIntegrator1_DSTATE += 2.0 * (real_T)rtb_In; 52 | } 53 | 54 | /* Model initialize function */ 55 | void Runnable_Init(void) 56 | { 57 | /* (no initialization code required) */ 58 | } 59 | 60 | /* 61 | * File trailer for generated code. 62 | * 63 | * [EOF] 64 | */ 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/C source code files/VariantSubsystemModel3.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel3.h 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel3'. 5 | * 6 | * Model version : 1.2 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:33:13 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_VariantSubsystemModel3_h_ 19 | #define RTW_HEADER_VariantSubsystemModel3_h_ 20 | #ifndef VariantSubsystemModel3_COMMON_INCLUDES_ 21 | # define VariantSubsystemModel3_COMMON_INCLUDES_ 22 | #include "rtwtypes.h" 23 | #include "Rte_VariantSubsystemModel3.h" 24 | #endif /* VariantSubsystemModel3_COMMON_INCLUDES_ */ 25 | 26 | /* Macros for accessing real-time model data structure */ 27 | 28 | /* Block signals and states (auto storage) for system '' */ 29 | typedef struct tag_DW { 30 | real_T DiscreteTimeIntegrator_DSTATE;/* '/Discrete-Time Integrator' */ 31 | real_T DiscreteTimeIntegrator1_DSTATE;/* '/Discrete-Time Integrator1' */ 32 | int32_T clockTickCounter; /* '/In' */ 33 | } DW; 34 | 35 | /* Block signals and states (auto storage) */ 36 | extern DW rtDW; 37 | 38 | /*- 39 | * These blocks were eliminated from the model due to optimizations: 40 | * 41 | * Block '/Scope' : Unused code path elimination 42 | */ 43 | 44 | /*- 45 | * The generated code includes comments that allow you to trace directly 46 | * back to the appropriate location in the model. The basic format 47 | * is /block_name, where system is the system number (uniquely 48 | * assigned by Simulink) and block_name is the name of the block. 49 | * 50 | * Use the MATLAB hilite_system command to trace the generated code back 51 | * to the model. For example, 52 | * 53 | * hilite_system('') - opens system 3 54 | * hilite_system('/Kp') - opens and selects block Kp which resides in S3 55 | * 56 | * Here is the system hierarchy for this model 57 | * 58 | * '' : 'VariantSubsystemModel3' 59 | * '' : 'VariantSubsystemModel3/Variant Subsystem' 60 | * '' : 'VariantSubsystemModel3/Variant Subsystem/Car' 61 | * '' : 'VariantSubsystemModel3/Variant Subsystem/CarRefined' 62 | * '' : 'VariantSubsystemModel3/Variant Subsystem/CarRefined/Band-Limited White Noise' 63 | */ 64 | #endif /* RTW_HEADER_VariantSubsystemModel3_h_ */ 65 | 66 | /* 67 | * File trailer for generated code. 68 | * 69 | * [EOF] 70 | */ 71 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/VariantSubsystemModel3.c: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel3.c 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel3'. 5 | * 6 | * Model version : 1.2 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:33:13 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #include "VariantSubsystemModel3.h" 19 | 20 | /* Block signals and states (auto storage) */ 21 | DW rtDW; 22 | 23 | /* Model step function */ 24 | void Runnable_Step(void) 25 | { 26 | int32_T rtb_In; 27 | 28 | /* Outport: '/Out1' incorporates: 29 | * DiscreteIntegrator: '/Discrete-Time Integrator' 30 | */ 31 | Rte_IWrite_Runnable_Step_Out1_Out1(rtDW.DiscreteTimeIntegrator_DSTATE); 32 | 33 | /* DiscretePulseGenerator: '/In' */ 34 | rtb_In = ((rtDW.clockTickCounter < 5) && (rtDW.clockTickCounter >= 0)); 35 | if (rtDW.clockTickCounter >= 9) { 36 | rtDW.clockTickCounter = 0; 37 | } else { 38 | rtDW.clockTickCounter++; 39 | } 40 | 41 | /* End of DiscretePulseGenerator: '/In' */ 42 | 43 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator' incorporates: 44 | * DiscreteIntegrator: '/Discrete-Time Integrator1' 45 | */ 46 | rtDW.DiscreteTimeIntegrator_DSTATE += rtDW.DiscreteTimeIntegrator1_DSTATE; 47 | 48 | /* Update for DiscreteIntegrator: '/Discrete-Time Integrator1' incorporates: 49 | * Gain: '/Gain' 50 | */ 51 | rtDW.DiscreteTimeIntegrator1_DSTATE += 2.0 * (real_T)rtb_In; 52 | } 53 | 54 | /* Model initialize function */ 55 | void Runnable_Init(void) 56 | { 57 | /* (no initialization code required) */ 58 | } 59 | 60 | /* 61 | * File trailer for generated code. 62 | * 63 | * [EOF] 64 | */ 65 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/VariantSubsystemModel3.h: -------------------------------------------------------------------------------- 1 | /* 2 | * File: VariantSubsystemModel3.h 3 | * 4 | * Code generated for Simulink model 'VariantSubsystemModel3'. 5 | * 6 | * Model version : 1.2 7 | * Simulink Coder version : 8.12 (R2017a) 16-Feb-2017 8 | * C/C++ source code generated on : Fri Jun 15 16:33:13 2018 9 | * 10 | * Target selection: autosar.tlc 11 | * Embedded hardware selection: Intel->x86-64 (Windows64) 12 | * Code generation objectives: 13 | * 1. Execution efficiency 14 | * 2. RAM efficiency 15 | * Validation result: Not run 16 | */ 17 | 18 | #ifndef RTW_HEADER_VariantSubsystemModel3_h_ 19 | #define RTW_HEADER_VariantSubsystemModel3_h_ 20 | #ifndef VariantSubsystemModel3_COMMON_INCLUDES_ 21 | # define VariantSubsystemModel3_COMMON_INCLUDES_ 22 | #include "rtwtypes.h" 23 | #include "Rte_VariantSubsystemModel3.h" 24 | #endif /* VariantSubsystemModel3_COMMON_INCLUDES_ */ 25 | 26 | /* Macros for accessing real-time model data structure */ 27 | 28 | /* Block signals and states (auto storage) for system '' */ 29 | typedef struct tag_DW { 30 | real_T DiscreteTimeIntegrator_DSTATE;/* '/Discrete-Time Integrator' */ 31 | real_T DiscreteTimeIntegrator1_DSTATE;/* '/Discrete-Time Integrator1' */ 32 | int32_T clockTickCounter; /* '/In' */ 33 | } DW; 34 | 35 | /* Block signals and states (auto storage) */ 36 | extern DW rtDW; 37 | 38 | /*- 39 | * These blocks were eliminated from the model due to optimizations: 40 | * 41 | * Block '/Scope' : Unused code path elimination 42 | */ 43 | 44 | /*- 45 | * The generated code includes comments that allow you to trace directly 46 | * back to the appropriate location in the model. The basic format 47 | * is /block_name, where system is the system number (uniquely 48 | * assigned by Simulink) and block_name is the name of the block. 49 | * 50 | * Use the MATLAB hilite_system command to trace the generated code back 51 | * to the model. For example, 52 | * 53 | * hilite_system('') - opens system 3 54 | * hilite_system('/Kp') - opens and selects block Kp which resides in S3 55 | * 56 | * Here is the system hierarchy for this model 57 | * 58 | * '' : 'VariantSubsystemModel3' 59 | * '' : 'VariantSubsystemModel3/Variant Subsystem' 60 | * '' : 'VariantSubsystemModel3/Variant Subsystem/Car' 61 | * '' : 'VariantSubsystemModel3/Variant Subsystem/CarRefined' 62 | * '' : 'VariantSubsystemModel3/Variant Subsystem/CarRefined/Band-Limited White Noise' 63 | */ 64 | #endif /* RTW_HEADER_VariantSubsystemModel3_h_ */ 65 | 66 | /* 67 | * File trailer for generated code. 68 | * 69 | * [EOF] 70 | */ 71 | -------------------------------------------------------------------------------- /VariantSubsystemModel3/VariantSubsystemModel3.slx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/saurabh-iiitu/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs/867657a4efff85a22009dc2083d62a6203d12b11/VariantSubsystemModel3/VariantSubsystemModel3.slx -------------------------------------------------------------------------------- /VariantSubsystemModel3/VariantSubsystemModel3.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/saurabh-iiitu/Variant-Models-for-Variability-Management-in-AUTOSAR-SWCs/867657a4efff85a22009dc2083d62a6203d12b11/VariantSubsystemModel3/VariantSubsystemModel3.zip --------------------------------------------------------------------------------