├── .gitignore ├── 2-bit-comparator ├── 2-bit-comparator.v ├── design1.png ├── execute ├── stimulus_tb.v └── test.vcd ├── 24_bit_counter ├── Makefile ├── counter.pcf ├── counter.v └── counter_tb.v ├── 2_to_1_multiplexer ├── Makefile ├── mux2.pcf ├── mux2.v └── mux2_tb.v ├── 4_bit_counter ├── Makefile ├── four_bit_counter.pcf ├── four_bit_counter.v └── four_bit_counter_tb.v ├── 4_bit_register ├── Makefile ├── four_bit_register.pcf └── four_bit_register.v ├── Makefile ├── README.md ├── adder ├── adder.v ├── adder.vcd ├── adder_gate.v ├── adder_gate_tb.v ├── adder_tb.v ├── adder_udp ├── adder_udp.v ├── adder_udp.vcd ├── adder_udp_tb.v └── execute ├── always ├── a.out ├── always.v ├── always_tb.v ├── comp └── test.vcd ├── baud_tx ├── Makefile ├── baud_tx.pcf ├── baud_tx.v ├── baud_tx_cont.pcf ├── baud_tx_cont.v ├── baud_tx_tb.v └── divM.v ├── binary_counter ├── Makefile ├── binary_counter.pcf ├── binary_counter.v └── binary_counter_tb.v ├── binary_decoder ├── decoder.v └── decoder_tb.v ├── blocking ├── Makefile ├── blocking.v └── blocking_tb.v ├── comparator ├── comparator.v ├── comparator_tb.v └── design1.png ├── comparator_bitwise ├── comparator ├── comparator.v ├── comparator.vcd ├── comparator_tb.v ├── design1.png ├── execute └── visualize ├── echowire ├── Makefile ├── echowire.pcf ├── echowire.v └── echowire_tb.v ├── freq_divider ├── Makefile ├── div3.v ├── div3_tb.v ├── divM.pcf ├── divM.v ├── divM_tb.v └── prescaler.v ├── fsmtx ├── Makefile ├── baudgen.v ├── baudgen.vh ├── fsmtx.out ├── fsmtx.pcf ├── fsmtx.v ├── fsmtx_tb.v └── fsmtx_tb.vcd ├── gate_level_modeling ├── a.out ├── design1.png ├── execute ├── gate.v ├── gate_tb.v └── test.vcd ├── generic_rom ├── Makefile ├── divider.vh ├── dividerp1.v ├── genrom.v ├── genromleds.pcf ├── genromleds.v ├── genromleds_tb.gtkw ├── genromleds_tb.v ├── imperial.list ├── notas_gen.py ├── notegen.v ├── notegen.vh ├── rom1.list ├── romnotes.pcf ├── romnotes.v ├── romnotes_tb.gtkw └── romnotes_tb.v ├── hello ├── a.out └── hello.v ├── icestick_pinout.png ├── icestickusermanual.pdf ├── if-statement ├── execute.sh ├── priority_encoder.v └── priority_encoder_tb.v ├── initializer ├── Makefile ├── initializer.pcf ├── initializer.v └── initializer_tb.v ├── m_to_1_multiplexer ├── Makefile ├── muxm.pcf ├── muxm.v └── muxm_tb.v ├── multiple_prescalers ├── Makefile ├── multiple_prescaler.pcf ├── multiple_prescaler.v └── multiple_prescaler_tb.v ├── multiplexer ├── mux_2_1.v ├── mux_2_1_tb.v ├── mux_4_2 ├── mux_4_2.v ├── mux_4_2.vcd └── mux_4_2_tb.v ├── mux_case ├── mux_case.v └── mux_case_tb.v ├── n_bits_register ├── Makefile ├── prescaler.v ├── register.v ├── regreset.pcf └── regreset.v ├── notes_seq ├── Makefile ├── divM.v ├── divider.vh ├── notes_seq.pcf ├── notes_seq.v ├── notes_seq_tb.v └── tone_gen.v ├── prescaler ├── Makefile ├── prescaler.pcf ├── prescaler.v └── prescaler_tb.v ├── ram_mem ├── .gitignore ├── .travis.yml ├── lib │ └── readme.txt ├── platformio.ini └── src │ ├── Makefile │ ├── ram_mem.out │ ├── ram_mem.pcf │ ├── ram_mem.v │ ├── ram_mem_tb.v │ └── ram_mem_tb.vcd ├── reg_init ├── Makefile ├── reg_init.pcf ├── reg_init.v └── reg_init_tb.v ├── ring_counter ├── Makefile ├── ring_counter.pcf ├── ring_counter.v └── ring_counter_tb.v ├── rom_mem ├── .gitignore ├── .travis.yml ├── lib │ └── readme.txt ├── platformio.ini └── src │ ├── Makefile │ ├── dividerp1.v │ ├── rom_const_val.pcf │ ├── rom_const_val.v │ ├── rom_mem.pcf │ ├── rom_mem.v │ ├── rom_mem_tb.v │ ├── rom_seq.v │ ├── sequencer.bin │ ├── sequencer.blif │ ├── sequencer.pcf │ ├── sequencer.txt │ └── sequencer.v ├── rom_memory ├── Makefile ├── divider.vh ├── dividerp1.v ├── rom1.list ├── rom32x4.pcf ├── rom32x4.v ├── rom_file.v ├── rom_leds.v ├── rom_seq.pcf ├── rom_seq.v ├── romfile.bin ├── romfile.blif ├── romfile.pcf ├── romfile.txt ├── romfile.v └── romhw.v ├── second_counter ├── Makefile ├── divM.v ├── four_bit_counter.v ├── second_counter.bin ├── second_counter.blif ├── second_counter.pcf ├── second_counter.txt └── second_counter.v ├── sequential_circuits ├── Makefile ├── d_ff.v └── d_ff_tb.v ├── seven-seg ├── Makefile ├── digits.vh ├── seven.v ├── seven_seg_display.v ├── seven_tb.v └── test.v ├── shift_register ├── Makefile ├── shift_register.out ├── shift_register.v ├── shift_register_tb.v └── shift_register_tb.vcd ├── shifter ├── Makefile ├── shifter.pcf ├── shifter.v └── shifter_tb.v ├── sync_baud_tx ├── Makefile ├── baud_tx.v ├── divM.v ├── divM0.v ├── sync_baud_tx.pcf ├── sync_baud_tx.v └── sync_baud_tx_tb.v ├── sync_rules ├── Makefile ├── baudgen.v ├── baudgen.vh ├── baudgen_tb.v ├── divider.v ├── divider.vh ├── txtest.pcf ├── txtest.v ├── txtest2.pcf ├── txtest2.v ├── txtest2_tb.v ├── txtest3.pcf ├── txtest3.v ├── txtest3_tb.v └── txtest_tb.v ├── tone_generator ├── Makefile ├── divM.v ├── tone_gen.pcf ├── tone_gen.v └── tone_gen_tb.v └── udp ├── a.out ├── execute ├── udp.v └── udp_tb.v /.gitignore: -------------------------------------------------------------------------------- 1 | */*.vcd 2 | */*.out 3 | */*.bin 4 | -------------------------------------------------------------------------------- /2-bit-comparator/2-bit-comparator.v: -------------------------------------------------------------------------------- 1 | module two_bit_comparator( 2 | input [1:0] input0, 3 | input [1:0] input1, 4 | output output0 5 | ); 6 | 7 | assign output0 = (input0[0] & input1[0] & input0[1] & input1[1]) | 8 | (~input0[0] & ~input1[0] & ~input0[1] & ~input1[1]) | 9 | (~input0[0] & ~input1[0] & input0[1] & input1[1]) | 10 | (input0[0] & input1[0] & ~input0[1] & ~input1[1]); 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /2-bit-comparator/design1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/2-bit-comparator/design1.png -------------------------------------------------------------------------------- /2-bit-comparator/execute: -------------------------------------------------------------------------------- 1 | iverilog 2-bit-comparator.v stimulus_tb.v; ./a.out 2 | -------------------------------------------------------------------------------- /2-bit-comparator/stimulus_tb.v: -------------------------------------------------------------------------------- 1 | module two_bit_comparator_tb; 2 | reg[1:0] input0; 3 | reg[1:0] input1; 4 | 5 | wire outpu0; 6 | 7 | two_bit_comparator uut ( 8 | .input0(input0), 9 | .input1(input1), 10 | .output0(output0) 11 | ); 12 | 13 | initial begin 14 | $dumpfile("test.vcd"); 15 | $dumpvars(0, two_bit_comparator_tb); 16 | 17 | //Initialize inputs 18 | input0 = 0; 19 | input1 = 0; 20 | 21 | //As a reminder 22 | /* 23 | 00- **** = 1 <- 24 | 01- ***1 = 0 25 | 02- **10 = 0 26 | 03- **11 = 0 27 | 04- *100 = 0 28 | 05- *101 = 1 <- 29 | 06- *110 = 0 30 | 07- *111 = 0 31 | 08- 1000 = 0 32 | 09- 1001 = 0 33 | 10- 1010 = 1 <- 34 | 11- 1011 = 0 35 | 12- 1100 = 0 36 | 13- 1101 = 0 37 | 14- 1110 = 0 38 | 15- 1111 = 1 <- 39 | */ 40 | 41 | //Current state is 0000 42 | #20 input0 = 1; //0100 43 | #20 input1 = 1; //0101 44 | #20 input1 = 3; //0111 45 | #20 input0 = 3; //1111 46 | #20 input1 = 1; //1101 47 | #20 input1 = 0; //1100 48 | #20 input0 = 2; //1000 49 | #20 input1 = 2; //1010 50 | #40 ; 51 | 52 | end 53 | 54 | initial begin 55 | $monitor("TIME=%3d: x=%d y=%d z=%b \n",$time,input0,input1,output0, ); 56 | end 57 | endmodule 58 | -------------------------------------------------------------------------------- /2-bit-comparator/test.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri May 6 22:32:32 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module two_bit_comparator_tb $end 11 | $var wire 1 ! output0 $end 12 | $var reg 2 " input0 [1:0] $end 13 | $var reg 2 # input1 [1:0] $end 14 | $scope module uut $end 15 | $var wire 2 $ input0 [1:0] $end 16 | $var wire 2 % input1 [1:0] $end 17 | $var wire 1 ! output0 $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | b0 % 24 | b0 $ 25 | b0 # 26 | b0 " 27 | 1! 28 | $end 29 | #20 30 | 0! 31 | b1 " 32 | b1 $ 33 | #40 34 | 1! 35 | b1 # 36 | b1 % 37 | #60 38 | 0! 39 | b11 # 40 | b11 % 41 | #80 42 | 1! 43 | b11 " 44 | b11 $ 45 | #100 46 | 0! 47 | b1 # 48 | b1 % 49 | #120 50 | b0 # 51 | b0 % 52 | #140 53 | b10 " 54 | b10 $ 55 | #160 56 | 1! 57 | b10 # 58 | b10 % 59 | #200 60 | -------------------------------------------------------------------------------- /24_bit_counter/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------- 2 | #-- Objetivo por defecto: hacer simulacion y sintesis 3 | #------------------------------------------------------- 4 | all: sint 5 | 6 | #---------------------------------------------- 7 | #-- make sim 8 | #---------------------------------------------- 9 | #-- Objetivo para hacer la simulacion del 10 | #-- banco de pruebas 11 | #---------------------------------------------- 12 | sim: counter_tb.vcd 13 | 14 | #----------------------------------------------- 15 | #- make sint 16 | #----------------------------------------------- 17 | #- Objetivo para realizar la sintetis completa 18 | #- y dejar el diseno listo para su grabacion en 19 | #- la FPGA 20 | #----------------------------------------------- 21 | sint: counter.bin 22 | 23 | #------------------------------- 24 | #-- Compilacion y simulacion 25 | #------------------------------- 26 | counter_tb.vcd: counter.v counter_tb.v 27 | 28 | #-- Compilar 29 | iverilog -o counter.out counter.v counter_tb.v 30 | 31 | #-- Simular 32 | ./counter.out 33 | 34 | #-- Crear VCD 35 | vvp counter.out 36 | 37 | #-- Ver visualmente la simulacion con gtkwave 38 | gtkwave counter.vcd & 39 | 40 | #------------------------------ 41 | #-- Sintesis completa 42 | #------------------------------ 43 | counter.bin: counter.v counter.pcf 44 | 45 | #-- Sintesis 46 | /usr/local/bin/yosys -p "synth_ice40 -blif counter.blif" counter.v 47 | 48 | #-- Place & route 49 | arachne-pnr -d 1k -p counter.pcf counter.blif -o counter.txt 50 | 51 | #-- Generar binario final, listo para descargar en fgpa 52 | icepack counter.txt counter.bin 53 | 54 | #-- Cargar en FPGA 55 | load: 56 | iceprog counter.bin 57 | 58 | #-- Limpiar todo 59 | clean: 60 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 61 | 62 | .PHONY: all clean 63 | -------------------------------------------------------------------------------- /24_bit_counter/counter.pcf: -------------------------------------------------------------------------------- 1 | set_io out[23] 96 2 | set_io out[22] 97 3 | set_io out[21] 98 4 | set_io out[20] 99 5 | set_io clk 21 6 | -------------------------------------------------------------------------------- /24_bit_counter/counter.v: -------------------------------------------------------------------------------- 1 | module bit_counter(input wire clk, output [23:0] out); 2 | reg [23:0] out = 0; 3 | 4 | initial begin 5 | out = 0; 6 | end 7 | 8 | always @ ( posedge clk ) begin 9 | out <= out + 1; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /24_bit_counter/counter_tb.v: -------------------------------------------------------------------------------- 1 | module bit_counter_tb; 2 | reg clk; 3 | wire [23:0] out; 4 | 5 | bit_counter uut ( 6 | .clk(clk), 7 | .out(out) 8 | ); 9 | 10 | initial begin 11 | clk = 0; 12 | end 13 | 14 | always #1 clk = ~clk; 15 | 16 | initial begin 17 | $dumpfile("counter.vcd"); 18 | $dumpvars(0, bit_counter_tb); 19 | 20 | $monitor($time, ": %b clk:%b\n", out, clk); 21 | 22 | # 99 $display("END of simulation"); 23 | # 100 $finish; 24 | end 25 | 26 | endmodule 27 | -------------------------------------------------------------------------------- /2_to_1_multiplexer/Makefile: -------------------------------------------------------------------------------- 1 | NAME=mux2 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /2_to_1_multiplexer/mux2.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io out_data[0] 99 3 | set_io out_data[1] 98 4 | set_io out_data[2] 97 5 | set_io out_data[3] 96 6 | -------------------------------------------------------------------------------- /2_to_1_multiplexer/mux2.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 22; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | 14 | module mux2(input wire clk, output reg[3:0]out_data); 15 | wire [3:0] in1 = 4'b1001; 16 | wire [3:0] in2 = 4'b0110; 17 | 18 | wire clk_prescaled; 19 | 20 | prescaler #(.BITS(22)) 21 | Pres1(.clk_in(clk), .clk_out(clk_prescaled)); 22 | 23 | always @ ( in1 or in2 or clk_prescaled ) begin 24 | if (clk_prescaled == 0) 25 | out_data <= in1; 26 | else 27 | out_data <= in2; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /2_to_1_multiplexer/mux2_tb.v: -------------------------------------------------------------------------------- 1 | module mux2_tb; 2 | reg clk = 0; 3 | reg in1; 4 | reg in2; 5 | reg sel; 6 | wire [3:0] data; 7 | 8 | mux2 uut(.clk(clk), .out_data(data)); 9 | 10 | always #1 clk = ~clk; 11 | 12 | always #5 sel = ~sel; 13 | 14 | initial begin 15 | $dumpfile("mux2_tb.vcd"); 16 | $dumpvars(0, mux2_tb); 17 | 18 | $monitor($time, " clk=%1b sel=%1b out=%4b in1=%4b in2=$4b", clk, sel, data, in1, in2); 19 | #99 $display("Finishing simulation"); 20 | #1 $finish; 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /4_bit_counter/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------- 2 | #-- Objetivo por defecto: hacer simulacion y sintesis 3 | #------------------------------------------------------- 4 | all: sint 5 | 6 | #---------------------------------------------- 7 | #-- make sim 8 | #---------------------------------------------- 9 | #-- Objetivo para hacer la simulacion del 10 | #-- banco de pruebas 11 | #---------------------------------------------- 12 | sim: four_bit_counter_tb.vcd 13 | 14 | #----------------------------------------------- 15 | #- make sint 16 | #----------------------------------------------- 17 | #- Objetivo para realizar la sintetis completa 18 | #- y dejar el diseno listo para su grabacion en 19 | #- la FPGA 20 | #----------------------------------------------- 21 | sint: four_bit_counter.bin 22 | 23 | #------------------------------- 24 | #-- Compilacion y simulacion 25 | #------------------------------- 26 | four_bit_counter_tb.vcd: four_bit_counter.v four_bit_counter_tb.v 27 | 28 | #-- Compilar 29 | iverilog -o four_bit_counter.out four_bit_counter.v four_bit_counter_tb.v 30 | 31 | #-- Simular 32 | ./four_bit_counter.out 33 | 34 | #-- Crear VCD 35 | vvp four_bit_counter.out 36 | 37 | #-- Ver visualmente la simulacion con gtkwave 38 | gtkwave four_bit_counter.vcd & 39 | 40 | #------------------------------ 41 | #-- Sintesis completa 42 | #------------------------------ 43 | four_bit_counter.bin: four_bit_counter.v four_bit_counter.pcf 44 | 45 | #-- Sintesis 46 | /usr/local/bin/yosys -p "synth_ice40 -blif four_bit_counter.blif" four_bit_counter.v 47 | 48 | #-- Place & route 49 | arachne-pnr -d 1k -p four_bit_counter.pcf four_bit_counter.blif -o four_bit_counter.txt 50 | 51 | #-- Generar binario final, listo para descargar en fgpa 52 | icepack four_bit_counter.txt four_bit_counter.bin 53 | 54 | #-- Cargar en FPGA 55 | load: 56 | iceprog four_bit_counter.bin 57 | 58 | #-- Limpiar todo 59 | clean: 60 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 61 | 62 | .PHONY: all clean 63 | -------------------------------------------------------------------------------- /4_bit_counter/four_bit_counter.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_in 21 2 | set_io data[3] 99 3 | set_io data[2] 98 4 | set_io data[1] 97 5 | set_io data[0] 96 6 | -------------------------------------------------------------------------------- /4_bit_counter/four_bit_counter.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 30; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | 14 | module four_bit_counter(input wire clk_in, output reg [3:0] data = 0); 15 | parameter BITS = 22; 16 | 17 | wire clk_pres; 18 | 19 | prescaler #(.BITS(BITS)) 20 | pres1( 21 | .clk_in(clk_in), 22 | .clk_out(clk_pres) 23 | ); 24 | 25 | always @ ( posedge(clk_pres) ) begin 26 | data <= data + 1; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /4_bit_counter/four_bit_counter_tb.v: -------------------------------------------------------------------------------- 1 | //-- counter4_tb.v 2 | module four_bit_counter_tb(); 3 | 4 | //-- Registro para generar la señal de reloj 5 | reg clk = 0; 6 | 7 | //-- Datos de salida del contador 8 | wire [3:0] data; 9 | 10 | //-- Registro para comprobar si el contador cuenta correctamente 11 | reg [3:0] counter_check = 0; 12 | 13 | //-- Instanciar el contador, con prescaler de 1 bit (para la simulacion) 14 | four_bit_counter #(.BITS(1)) 15 | C1( 16 | .clk_in(clk), 17 | .data(data) 18 | ); 19 | 20 | //-- Generador de reloj. Periodo 2 unidades 21 | always #1 clk = ~clk; 22 | 23 | //-- Proceso de comprobación. Cada vez que hay un cambio en 24 | //-- el contador se comprueba con el valor de prueba 25 | always @(data) begin 26 | 27 | if (counter_check != data) 28 | $display("-->ERROR!. Esperado: %d. Leido: %d",counter_check, data); 29 | 30 | counter_check = counter_check + 1; 31 | end 32 | 33 | //-- Proceso al inicio 34 | initial begin 35 | 36 | //-- Fichero donde almacenar los resultados 37 | $dumpfile("four_bit_counter.vcd"); 38 | $dumpvars(0, four_bit_counter_tb); 39 | 40 | //-- Comprobación del reset. 41 | # 0.5 if (data != 0) 42 | $display("ERROR! Contador NO está a 0!"); 43 | else 44 | $display("Contador inicializado. OK."); 45 | 46 | # 99 $display("FIN de la simulacion"); 47 | # 100 $finish; 48 | end 49 | 50 | endmodule 51 | -------------------------------------------------------------------------------- /4_bit_register/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------- 2 | #-- Objetivo por defecto: hacer simulacion y sintesis 3 | #------------------------------------------------------- 4 | all: sint 5 | 6 | #---------------------------------------------- 7 | #-- make sim 8 | #---------------------------------------------- 9 | #-- Objetivo para hacer la simulacion del 10 | #-- banco de pruebas 11 | #---------------------------------------------- 12 | sim: four_bit_register_tb.vcd 13 | 14 | #----------------------------------------------- 15 | #- make sint 16 | #----------------------------------------------- 17 | #- Objetivo para realizar la sintetis completa 18 | #- y dejar el diseno listo para su grabacion en 19 | #- la FPGA 20 | #----------------------------------------------- 21 | sint: four_bit_register.bin 22 | 23 | #------------------------------- 24 | #-- Compilacion y simulacion 25 | #------------------------------- 26 | four_bit_register_tb.vcd: four_bit_register.v four_bit_register_tb.v 27 | 28 | #-- Compilar 29 | iverilog -o four_bit_register.out four_bit_register.v four_bit_register_tb.v 30 | 31 | #-- Simular 32 | ./four_bit_register.out 33 | 34 | #-- Crear VCD 35 | vvp four_bit_register.out 36 | 37 | #-- Ver visualmente la simulacion con gtkwave 38 | gtkwave four_bit_register.vcd & 39 | 40 | #------------------------------ 41 | #-- Sintesis completa 42 | #------------------------------ 43 | four_bit_register.bin: four_bit_register.v four_bit_register.pcf 44 | 45 | #-- Sintesis 46 | /usr/local/bin/yosys -p "synth_ice40 -blif four_bit_register.blif" four_bit_register.v 47 | 48 | #-- Place & route 49 | arachne-pnr -d 1k -p four_bit_register.pcf four_bit_register.blif -o four_bit_register.txt 50 | 51 | #-- Generar binario final, listo para descargar en fgpa 52 | icepack four_bit_register.txt four_bit_register.bin 53 | 54 | #-- Cargar en FPGA 55 | load: 56 | iceprog four_bit_register.bin 57 | 58 | #-- Limpiar todo 59 | clean: 60 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 61 | 62 | .PHONY: all clean 63 | -------------------------------------------------------------------------------- /4_bit_register/four_bit_register.pcf: -------------------------------------------------------------------------------- 1 | set_io dout[0] 96 2 | set_io dout[1] 97 3 | set_io dout[2] 98 4 | set_io dout[3] 99 5 | set_io GREEN 95 6 | set_io clk_in 21 7 | -------------------------------------------------------------------------------- /4_bit_register/four_bit_register.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 30; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | module blink4(input wire clk_in, output reg [3:0] dout = 0, output wire GREEN); 14 | parameter BITS = 22; 15 | 16 | wire clk_base; 17 | 18 | wire [3:0] din; 19 | 20 | prescaler #(.BITS(BITS)) 21 | PRES( 22 | .clk_in(clk_in), 23 | .clk_out(clk_base) 24 | ); 25 | 26 | always @ ( posedge(clk_base) ) begin 27 | dout <= din; 28 | end 29 | 30 | assign din = ~dout; 31 | 32 | assign GREEN = ~dout[0]; 33 | 34 | assign data = dout; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | NAME=echowire 2 | DEPS = 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /adder/adder.v: -------------------------------------------------------------------------------- 1 | module adder(input x, input y, input cin, output res, output cout); 2 | 3 | assign {cout, res} = cin + y + x; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /adder/adder.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri May 6 23:41:24 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 100ps 9 | $end 10 | $scope module adder_gate_tb $end 11 | $var wire 1 ! res $end 12 | $var wire 1 " carryout $end 13 | $var reg 1 # carryin $end 14 | $var reg 1 $ input1 $end 15 | $var reg 1 % input2 $end 16 | $scope module uut $end 17 | $var wire 1 # cin $end 18 | $var wire 1 " cout $end 19 | $var wire 1 & p $end 20 | $var wire 1 ' r $end 21 | $var wire 1 ! res $end 22 | $var wire 1 ( s $end 23 | $var wire 1 $ x $end 24 | $var wire 1 % y $end 25 | $upscope $end 26 | $upscope $end 27 | $enddefinitions $end 28 | #0 29 | $dumpvars 30 | 0( 31 | 0' 32 | 0& 33 | 0% 34 | 0$ 35 | 0# 36 | 0" 37 | 0! 38 | $end 39 | #200 40 | 1! 41 | 1& 42 | 1$ 43 | #400 44 | 0! 45 | 1" 46 | 0& 47 | 1( 48 | 1% 49 | #600 50 | 1! 51 | 0" 52 | 1& 53 | 0( 54 | 0$ 55 | #800 56 | 1" 57 | 1' 58 | 0! 59 | 1# 60 | #1000 61 | 0" 62 | 0' 63 | 1! 64 | 0& 65 | 0% 66 | #1200 67 | 1" 68 | 1' 69 | 0! 70 | 1& 71 | 1$ 72 | #1400 73 | 0' 74 | 1! 75 | 0& 76 | 1( 77 | 1% 78 | #1800 79 | -------------------------------------------------------------------------------- /adder/adder_gate.v: -------------------------------------------------------------------------------- 1 | module adder_gate(input x, input y, input cin, output res, output cout); 2 | 3 | wire p, s, r; 4 | 5 | xor(p, x, y); 6 | and(s, x, y); 7 | and(r, p, cin); 8 | or(cout, r, s); 9 | xor(res, p, cin); 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /adder/adder_gate_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module adder_gate_tb; 4 | 5 | reg input1; 6 | reg input2; 7 | reg carryin; 8 | 9 | wire out; 10 | wire carryout; 11 | 12 | adder_gate uut ( 13 | .x(input1), 14 | .y(input2), 15 | .cin(carryin), 16 | .res(res), 17 | .cout(carryout) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("adder.vcd"); 22 | $dumpvars(0,adder_gate_tb); 23 | input1 = 0; 24 | input2 = 0; 25 | carryin = 0; 26 | 27 | #20 input1 = 1; 28 | #20; input2 = 1; 29 | #20; input1 = 0; 30 | #20; carryin = 1; 31 | #20; input2 = 0; 32 | #20; input1 = 1; 33 | #20; input2 = 1; 34 | #40; 35 | end 36 | 37 | initial begin 38 | $monitor("time = %2d, CIN =%1b, IN1=%1b, IN2=%1b, COUT=%1b, OUT_A=%1b", $time,carryin,input2, input1,carryout,res); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /adder/adder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module adder_tb; 4 | 5 | reg input1; 6 | reg input2; 7 | reg carryin; 8 | 9 | wire out; 10 | wire carryout; 11 | 12 | adder uut ( 13 | .x(input1), 14 | .y(input2), 15 | .cin(carryin), 16 | .res(res), 17 | .cout(carryout) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("adder.vcd"); 22 | $dumpvars(0,adder_tb); 23 | input1 = 0; 24 | input2 = 0; 25 | carryin = 0; 26 | 27 | #20 input1 = 1; 28 | #20; input2 = 1; 29 | #20; input1 = 0; 30 | #20; carryin = 1; 31 | #20; input2 = 0; 32 | #20; input1 = 1; 33 | #20; input2 = 1; 34 | #40; 35 | end 36 | 37 | initial begin 38 | $monitor("time = %2d, CIN =%1b, IN1=%1b, IN2=%1b, COUT=%1b, OUT_A=%1b", $time,carryin,input2, input1,carryout,res); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /adder/adder_udp: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 10; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0xe1eab0 .scope module, "adder_udp_tb" "adder_udp_tb" 2 3; 10 | .timescale -9 -10; 11 | v0xe32440_0 .var "cin", 0 0; 12 | v0xe32530_0 .net "cout", 0 0, L_0xe42b70; 1 drivers 13 | v0xe32600_0 .net "res", 0 0, L_0xe328c0; 1 drivers 14 | v0xe32700_0 .var "x", 0 0; 15 | v0xe327d0_0 .var "y", 0 0; 16 | S_0xe1ec30 .scope module, "uut" "adder_udp" 2 12, 3 1 0, S_0xe1eab0; 17 | .timescale 0 0; 18 | .port_info 0 /INPUT 1 "x" 19 | .port_info 1 /INPUT 1 "y" 20 | .port_info 2 /INPUT 1 "cin" 21 | .port_info 3 /OUTPUT 1 "res" 22 | .port_info 4 /OUTPUT 1 "cout" 23 | UDP_addresult .udp/comb "addresult", 3 24 | ,"0000" 25 | ,"0011" 26 | ,"0101" 27 | ,"0110" 28 | ,"1001" 29 | ,"1010" 30 | ,"1100" 31 | ,"1111"; 32 | L_0xe328c0 .udp UDP_addresult, v0xe32440_0, v0xe32700_0, v0xe327d0_0; 33 | UDP_addcarry .udp/comb "addcarry", 3 34 | ,"0000" 35 | ,"0010" 36 | ,"0100" 37 | ,"0111" 38 | ,"1000" 39 | ,"1011" 40 | ,"1101" 41 | ,"1111"; 42 | L_0xe42b70 .udp UDP_addcarry, v0xe32440_0, v0xe32700_0, v0xe327d0_0; 43 | v0xe1c280_0 .net "cin", 0 0, v0xe32440_0; 1 drivers 44 | v0xe32040_0 .net "cout", 0 0, L_0xe42b70; alias, 1 drivers 45 | v0xe32100_0 .net "res", 0 0, L_0xe328c0; alias, 1 drivers 46 | v0xe321d0_0 .net "x", 0 0, v0xe32700_0; 1 drivers 47 | v0xe32290_0 .net "y", 0 0, v0xe327d0_0; 1 drivers 48 | .scope S_0xe1eab0; 49 | T_0 ; 50 | %vpi_call 2 21 "$dumpfile", "adder_udp.vcd" {0 0 0}; 51 | %vpi_call 2 22 "$dumpvars", 32'sb00000000000000000000000000000000, S_0xe1eab0 {0 0 0}; 52 | %pushi/vec4 0, 0, 1; 53 | %store/vec4 v0xe32700_0, 0, 1; 54 | %pushi/vec4 0, 0, 1; 55 | %store/vec4 v0xe327d0_0, 0, 1; 56 | %pushi/vec4 0, 0, 1; 57 | %store/vec4 v0xe32440_0, 0, 1; 58 | %delay 200, 0; 59 | %pushi/vec4 1, 0, 1; 60 | %store/vec4 v0xe32700_0, 0, 1; 61 | %delay 200, 0; 62 | %pushi/vec4 1, 0, 1; 63 | %store/vec4 v0xe327d0_0, 0, 1; 64 | %delay 200, 0; 65 | %pushi/vec4 0, 0, 1; 66 | %store/vec4 v0xe32700_0, 0, 1; 67 | %delay 200, 0; 68 | %pushi/vec4 1, 0, 1; 69 | %store/vec4 v0xe32440_0, 0, 1; 70 | %delay 200, 0; 71 | %pushi/vec4 0, 0, 1; 72 | %store/vec4 v0xe327d0_0, 0, 1; 73 | %delay 200, 0; 74 | %pushi/vec4 1, 0, 1; 75 | %store/vec4 v0xe32700_0, 0, 1; 76 | %delay 200, 0; 77 | %pushi/vec4 1, 0, 1; 78 | %store/vec4 v0xe327d0_0, 0, 1; 79 | %delay 400, 0; 80 | %end; 81 | .thread T_0; 82 | .scope S_0xe1eab0; 83 | T_1 ; 84 | %vpi_call 2 38 "$monitor", "time = %2d, CIN =%1b, X=%1b, Y=%1b, COUT=%1b, RES=%1b", $time, v0xe32440_0, v0xe327d0_0, v0xe32700_0, v0xe32530_0, v0xe32600_0 {0 0 0}; 85 | %end; 86 | .thread T_1; 87 | # The file index is used to find the file name in the following table. 88 | :file_names 4; 89 | "N/A"; 90 | ""; 91 | "adder_udp_tb.v"; 92 | "adder_udp.v"; 93 | -------------------------------------------------------------------------------- /adder/adder_udp.v: -------------------------------------------------------------------------------- 1 | module adder_udp(input x, input y, input cin, output res, output cout); 2 | 3 | addresult(res, cin, x, y); 4 | addcarry(cout, cin, x, y); 5 | 6 | endmodule 7 | 8 | 9 | primitive addresult(res, cin, x, y); 10 | output res; 11 | input cin,x,y; 12 | 13 | table 14 | //cin x y res 15 | 0 0 0 : 0 ; 16 | 0 0 1 : 1 ; 17 | 0 1 0 : 1 ; 18 | 0 1 1 : 0 ; 19 | 1 0 0 : 1 ; 20 | 1 0 1 : 0 ; 21 | 1 1 0 : 0 ; 22 | 1 1 1 : 1 ; 23 | endtable 24 | endprimitive 25 | 26 | primitive addcarry(cout, cin, x, y); 27 | output cout; 28 | input cin, x, y; 29 | 30 | table 31 | //cin x y : cout 32 | 0 0 0 : 0 ; 33 | 0 0 1 : 0 ; 34 | 0 1 0 : 0 ; 35 | 0 1 1 : 1 ; 36 | 1 0 0 : 0 ; 37 | 1 0 1 : 1 ; 38 | 1 1 0 : 1 ; 39 | 1 1 1 : 1 ; 40 | endtable 41 | endprimitive 42 | -------------------------------------------------------------------------------- /adder/adder_udp.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri May 6 23:42:00 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 100ps 9 | $end 10 | $scope module adder_udp_tb $end 11 | $var wire 1 ! res $end 12 | $var wire 1 " cout $end 13 | $var reg 1 # cin $end 14 | $var reg 1 $ x $end 15 | $var reg 1 % y $end 16 | $scope module uut $end 17 | $var wire 1 # cin $end 18 | $var wire 1 " cout $end 19 | $var wire 1 ! res $end 20 | $var wire 1 $ x $end 21 | $var wire 1 % y $end 22 | $upscope $end 23 | $upscope $end 24 | $enddefinitions $end 25 | #0 26 | $dumpvars 27 | 0% 28 | 0$ 29 | 0# 30 | 0" 31 | 0! 32 | $end 33 | #200 34 | 1! 35 | 1$ 36 | #400 37 | 0! 38 | 1" 39 | 1% 40 | #600 41 | 1! 42 | 0" 43 | 0$ 44 | #800 45 | 0! 46 | 1" 47 | 1# 48 | #1000 49 | 1! 50 | 0" 51 | 0% 52 | #1200 53 | 0! 54 | 1" 55 | 1$ 56 | #1400 57 | 1! 58 | 1% 59 | #1800 60 | -------------------------------------------------------------------------------- /adder/adder_udp_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module adder_udp_tb; 4 | 5 | reg x; 6 | reg y; 7 | reg cin; 8 | 9 | wire res; 10 | wire cout; 11 | 12 | adder_udp uut ( 13 | .x(x), 14 | .y(y), 15 | .cin(cin), 16 | .res(res), 17 | .cout(cout) 18 | ); 19 | 20 | initial begin 21 | $dumpfile("adder_udp.vcd"); 22 | $dumpvars(0, adder_udp_tb); 23 | x = 0; 24 | y = 0; 25 | cin = 0; 26 | 27 | #20 x = 1; 28 | #20; y = 1; 29 | #20; x = 0; 30 | #20; cin = 1; 31 | #20; y = 0; 32 | #20; x = 1; 33 | #20; y = 1; 34 | #40; 35 | end 36 | 37 | initial begin 38 | $monitor("time = %2d, CIN =%1b, X=%1b, Y=%1b, COUT=%1b, RES=%1b", $time, cin, y, x, cout, res); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /adder/execute: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | iverilog -o adder adder.v adder_tb.v 3 | -------------------------------------------------------------------------------- /always/a.out: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 12; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0x13d4280 .scope module, "stimulus" "stimulus" 2 2; 10 | .timescale -9 -12; 11 | v0x13e8500_0 .net "out", 0 0, v0x13d5be0_0; 1 drivers 12 | v0x13e85a0_0 .var "x", 0 0; 13 | v0x13e8670_0 .var "y", 0 0; 14 | S_0x13d4400 .scope module, "uut" "comparator" 2 9, 3 1 0, S_0x13d4280; 15 | .timescale 0 0; 16 | .port_info 0 /INPUT 1 "x" 17 | .port_info 1 /INPUT 1 "y" 18 | .port_info 2 /OUTPUT 1 "out" 19 | v0x13d5be0_0 .var "out", 0 0; 20 | v0x13e8120_0 .var "p", 0 0; 21 | v0x13e81e0_0 .var "q", 0 0; 22 | v0x13e82b0_0 .net "x", 0 0, v0x13e85a0_0; 1 drivers 23 | v0x13e8370_0 .net "y", 0 0, v0x13e8670_0; 1 drivers 24 | E_0x13d60c0 .event edge, v0x13e8370_0, v0x13e82b0_0; 25 | .scope S_0x13d4400; 26 | T_0 ; 27 | %wait E_0x13d60c0; 28 | %load/vec4 v0x13e82b0_0; 29 | %inv; 30 | %load/vec4 v0x13e8370_0; 31 | %inv; 32 | %and; 33 | %store/vec4 v0x13e8120_0, 0, 1; 34 | %load/vec4 v0x13e82b0_0; 35 | %load/vec4 v0x13e8370_0; 36 | %and; 37 | %store/vec4 v0x13e81e0_0, 0, 1; 38 | %load/vec4 v0x13e8120_0; 39 | %load/vec4 v0x13e81e0_0; 40 | %or; 41 | %store/vec4 v0x13d5be0_0, 0, 1; 42 | %jmp T_0; 43 | .thread T_0, $push; 44 | .scope S_0x13d4280; 45 | T_1 ; 46 | %vpi_call 2 16 "$dumpfile", "test.vcd" {0 0 0}; 47 | %vpi_call 2 17 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x13d4280 {0 0 0}; 48 | %pushi/vec4 0, 0, 1; 49 | %store/vec4 v0x13e85a0_0, 0, 1; 50 | %pushi/vec4 0, 0, 1; 51 | %store/vec4 v0x13e8670_0, 0, 1; 52 | %delay 20000, 0; 53 | %pushi/vec4 1, 0, 1; 54 | %store/vec4 v0x13e85a0_0, 0, 1; 55 | %delay 20000, 0; 56 | %pushi/vec4 1, 0, 1; 57 | %store/vec4 v0x13e8670_0, 0, 1; 58 | %delay 20000, 0; 59 | %pushi/vec4 0, 0, 1; 60 | %store/vec4 v0x13e8670_0, 0, 1; 61 | %delay 20000, 0; 62 | %pushi/vec4 1, 0, 1; 63 | %store/vec4 v0x13e85a0_0, 0, 1; 64 | %delay 40000, 0; 65 | %end; 66 | .thread T_1; 67 | .scope S_0x13d4280; 68 | T_2 ; 69 | %vpi_call 2 31 "$monitor", "t=%3d x=%d,y=%d,z=%d \012", $time, v0x13e85a0_0, v0x13e8670_0, v0x13e8500_0, " " {0 0 0}; 70 | %end; 71 | .thread T_2; 72 | # The file index is used to find the file name in the following table. 73 | :file_names 4; 74 | "N/A"; 75 | ""; 76 | "always_tb.v"; 77 | "always.v"; 78 | -------------------------------------------------------------------------------- /always/always.v: -------------------------------------------------------------------------------- 1 | module comparator( 2 | input x, 3 | input y, 4 | output reg out 5 | ); 6 | 7 | reg p,q; 8 | always @(x,y) 9 | begin 10 | 11 | p = (~x & ~y); 12 | q = x & y; 13 | 14 | out = p |q; 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /always/always_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module stimulus; 3 | // Inputs 4 | reg x; 5 | reg y; 6 | // Outputs 7 | wire out; 8 | // Instantiate the Unit Under Test (UUT) 9 | comparator uut ( 10 | .x(x), 11 | .y(y), 12 | .out(out) 13 | ); 14 | 15 | initial begin 16 | $dumpfile("test.vcd"); 17 | $dumpvars(0,stimulus); 18 | // Initialize Inputs 19 | x = 0; 20 | y = 0; 21 | 22 | #20 x = 1; 23 | #20 y = 1; 24 | #20 y = 0; 25 | #20 x = 1; 26 | #40 ; 27 | 28 | end 29 | 30 | initial begin 31 | $monitor("t=%3d x=%d,y=%d,z=%d \n",$time,x,y,out, ); 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /always/comp: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 12; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0x2844280 .scope module, "stimulus" "stimulus" 2 2; 10 | .timescale -9 -12; 11 | v0x2858500_0 .var "x", 0 0; 12 | v0x28585a0_0 .var "y", 0 0; 13 | v0x2858670_0 .net "z", 0 0, v0x2858370_0; 1 drivers 14 | S_0x2844400 .scope module, "uut" "comparator" 2 9, 3 1 0, S_0x2844280; 15 | .timescale 0 0; 16 | .port_info 0 /INPUT 1 "x" 17 | .port_info 1 /INPUT 1 "y" 18 | .port_info 2 /OUTPUT 1 "z" 19 | v0x2845be0_0 .var "p", 0 0; 20 | v0x2858120_0 .var "q", 0 0; 21 | v0x28581e0_0 .net "x", 0 0, v0x2858500_0; 1 drivers 22 | v0x28582b0_0 .net "y", 0 0, v0x28585a0_0; 1 drivers 23 | v0x2858370_0 .var "z", 0 0; 24 | E_0x2846240 .event edge, v0x28582b0_0, v0x28581e0_0; 25 | .scope S_0x2844400; 26 | T_0 ; 27 | %wait E_0x2846240; 28 | %load/vec4 v0x28581e0_0; 29 | %inv; 30 | %load/vec4 v0x28582b0_0; 31 | %inv; 32 | %and; 33 | %store/vec4 v0x2845be0_0, 0, 1; 34 | %load/vec4 v0x28581e0_0; 35 | %load/vec4 v0x28582b0_0; 36 | %and; 37 | %store/vec4 v0x2858120_0, 0, 1; 38 | %load/vec4 v0x2845be0_0; 39 | %load/vec4 v0x2858120_0; 40 | %or; 41 | %store/vec4 v0x2858370_0, 0, 1; 42 | %jmp T_0; 43 | .thread T_0, $push; 44 | .scope S_0x2844280; 45 | T_1 ; 46 | %vpi_call 2 16 "$dumpfile", "test.vcd" {0 0 0}; 47 | %vpi_call 2 17 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x2844280 {0 0 0}; 48 | %pushi/vec4 0, 0, 1; 49 | %store/vec4 v0x2858500_0, 0, 1; 50 | %pushi/vec4 0, 0, 1; 51 | %store/vec4 v0x28585a0_0, 0, 1; 52 | %delay 20000, 0; 53 | %pushi/vec4 1, 0, 1; 54 | %store/vec4 v0x2858500_0, 0, 1; 55 | %delay 20000, 0; 56 | %pushi/vec4 1, 0, 1; 57 | %store/vec4 v0x28585a0_0, 0, 1; 58 | %delay 20000, 0; 59 | %pushi/vec4 0, 0, 1; 60 | %store/vec4 v0x28585a0_0, 0, 1; 61 | %delay 20000, 0; 62 | %pushi/vec4 1, 0, 1; 63 | %store/vec4 v0x2858500_0, 0, 1; 64 | %delay 40000, 0; 65 | %end; 66 | .thread T_1; 67 | .scope S_0x2844280; 68 | T_2 ; 69 | %vpi_call 2 31 "$monitor", "t=%3d x=%d,y=%d,z=%d \012", $time, v0x2858500_0, v0x28585a0_0, v0x2858670_0, " " {0 0 0}; 70 | %end; 71 | .thread T_2; 72 | # The file index is used to find the file name in the following table. 73 | :file_names 4; 74 | "N/A"; 75 | ""; 76 | "always_tb.v"; 77 | "always.v"; 78 | -------------------------------------------------------------------------------- /always/test.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat May 7 09:12:37 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module stimulus $end 11 | $var wire 1 ! z $end 12 | $var reg 1 " x $end 13 | $var reg 1 # y $end 14 | $scope module uut $end 15 | $var wire 1 " x $end 16 | $var wire 1 # y $end 17 | $var reg 1 $ p $end 18 | $var reg 1 % q $end 19 | $var reg 1 ! z $end 20 | $upscope $end 21 | $upscope $end 22 | $enddefinitions $end 23 | #0 24 | $dumpvars 25 | 0% 26 | 1$ 27 | 0# 28 | 0" 29 | 1! 30 | $end 31 | #20000 32 | 0! 33 | 0$ 34 | 1" 35 | #40000 36 | 1! 37 | 1% 38 | 1# 39 | #60000 40 | 0! 41 | 0% 42 | 0# 43 | #120000 44 | -------------------------------------------------------------------------------- /baud_tx/Makefile: -------------------------------------------------------------------------------- 1 | NAME=baud_tx_cont 2 | DEPS = divM.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /baud_tx/baud_tx.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io load 3 3 | set_io tx 8 4 | -------------------------------------------------------------------------------- /baud_tx/baud_tx.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module baud_tx( 4 | input wire clk, 5 | input wire load, 6 | output wire tx 7 | ); 8 | 9 | //115200 baud 10 | parameter BAUD = 104; 11 | 12 | wire clk_baud; 13 | 14 | //Generate a pulse to the specified baud frequency 15 | divM #(BAUD) 16 | BAUD0( 17 | .clk_in(clk), 18 | .clk_out(clk_baud) 19 | ); 20 | 21 | //Holds the 10 bit value that we'll pass 22 | reg [9:0] shifter; 23 | 24 | always @ (posedge clk_baud) begin 25 | if (load == 0) 26 | //Don't transmit. Set value to send (shifter) to "K" 01001011 + 01 27 | shifter <= {"K",2'b01}; 28 | else 29 | //Transmission is activated. Shift to the left (leftmost bit to the first and shift the other 9 to left) 30 | shifter <= {shifter[0], shifter[9:1]}; 31 | end 32 | 33 | assign tx = (load) ? shifter[0] : 1; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /baud_tx/baud_tx_cont.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io load 3 3 | set_io tx 8 4 | -------------------------------------------------------------------------------- /baud_tx/baud_tx_cont.v: -------------------------------------------------------------------------------- 1 | module baud_tx_cont( 2 | input wire clk, 3 | input wire load, 4 | output wire tx 5 | ); 6 | 7 | //115200 8 | parameter BAUD =104; 9 | 10 | wire clk_baud; 11 | 12 | divM #(BAUD) BAUD0(.clk_in(clk), .clk_out(clk_baud)); 13 | 14 | reg [9:0] shifter; 15 | 16 | always @ ( posedge clk_baud ) begin 17 | shifter <= (load == 0) ? {"K", 2'b01} : {shifter[0], shifter[9:1]}; 18 | end 19 | 20 | assign tx = (load) ? shifter[0] : 1; 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /baud_tx/baud_tx_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | 3 | module baud_tx_tb; 4 | reg clk = 0; 5 | wire tx; 6 | reg load = 0; 7 | 8 | baud_tx #(3) uut(.clk(clk), .load(load), .tx(tx)); 9 | 10 | always #1 clk = !clk; 11 | 12 | initial begin 13 | $dumpfile("baud_tx_tb.vcd"); 14 | $dumpvars; 15 | 16 | $monitor($time, ": clk=%b tx=%b load=%b", clk, tx, load); 17 | 18 | #5 load = !load; 19 | 20 | #100 load = !load; 21 | 22 | #5 load = !load; 23 | 24 | #100 load = !load; 25 | 26 | #5 load = !load; 27 | 28 | 29 | #100 $finish; 30 | end 31 | endmodule 32 | -------------------------------------------------------------------------------- /baud_tx/divM.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /binary_counter/Makefile: -------------------------------------------------------------------------------- 1 | NAME=binary_counter 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /binary_counter/binary_counter.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/binary_counter/binary_counter.pcf -------------------------------------------------------------------------------- /binary_counter/binary_counter.v: -------------------------------------------------------------------------------- 1 | module binary_counter 2 | #(parameter BITS=4) 3 | ( 4 | input wire clk, reset, 5 | output reg [BITS-1:0] binary 6 | ); 7 | 8 | always @ ( posedge(clk), negedge(reset) ) 9 | begin 10 | if(~reset) 11 | binary <= 0; 12 | else 13 | binary <= binary + 1; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /binary_counter/binary_counter_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module binary_counter_tb; 3 | // Inputs 4 | reg clk ; 5 | reg reset; 6 | 7 | // Output 8 | wire[3:0] binary; 9 | 10 | // Instantiate the Binary Counter 11 | binary_counter #(4) s1 ( 12 | .clk(clk), 13 | .reset(reset), 14 | .binary(binary) 15 | ); 16 | 17 | integer i; 18 | initial begin 19 | 20 | clk = 0; 21 | for(i =0; i<=40; i=i+1) 22 | begin 23 | #10 clk = ~clk; 24 | end 25 | end 26 | 27 | initial begin 28 | 29 | $dumpfile("binary_counter_tb.vcd"); 30 | $dumpvars(0, binary_counter_tb); 31 | 32 | reset = 1; 33 | #2 reset = 0; 34 | #2 reset =1; 35 | end 36 | 37 | 38 | initial begin 39 | $monitor("clk=%d binary=%4b",clk,binary); 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /binary_decoder/decoder.v: -------------------------------------------------------------------------------- 1 | module decoder(input wire enable, input wire [1:0] in, output reg [3:0] out); 2 | 3 | always @ ( enable, in[0], in[1] ) begin 4 | if (enable == 1'b0) 5 | out = 4'b0000; 6 | else 7 | case (in) 8 | 2'b00: 9 | out = 4'b0001; 10 | 2'b01: 11 | out = 4'b0010; 12 | 2'b10: 13 | out = 4'b0100; 14 | 2'b11: 15 | out = 4'b1000; 16 | endcase 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /binary_decoder/decoder_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module stimulus; 3 | reg[1:0] in_; 4 | reg enable_; 5 | wire[3:0] out_; 6 | // Instantiate the Unit Under Test (UUT) 7 | decoder uut ( 8 | .in(in_), 9 | .enable(enable_), 10 | .out(out_) 11 | ); 12 | 13 | initial begin 14 | $dumpfile("dump.vcd"); 15 | $dumpvars(0, stimulus); 16 | 17 | // Initialize Inputs 18 | in_ = 4'b0000; 19 | enable_ = 0; 20 | 21 | #20 enable_ = 1; 22 | #20 in_ = 2'b01; 23 | #20 in_ = 2'b10; 24 | #20 in_ = 2'b11; 25 | #40 ; 26 | 27 | end 28 | 29 | initial begin 30 | $monitor("t=%3d enable_=%1b,in=%2b, out_=%4b",$time,enable_,in_,out_ ); 31 | end 32 | 33 | endmodule 34 | -------------------------------------------------------------------------------- /blocking/Makefile: -------------------------------------------------------------------------------- 1 | NAME=blocking 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /blocking/blocking.v: -------------------------------------------------------------------------------- 1 | module blocking( 2 | input wire in, 3 | input wire clk, 4 | output reg out 5 | ); 6 | 7 | always @(posedge clk) begin 8 | out <= in; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /blocking/blocking_tb.v: -------------------------------------------------------------------------------- 1 | module delete_tb; 2 | reg clk=0; 3 | reg in = 1; 4 | wire out1; 5 | 6 | blocking uut( 7 | .in(in), 8 | .clk(clk), 9 | .out(out1) 10 | ); 11 | 12 | always #1 clk = ~clk; 13 | 14 | always #5 in = ~in; 15 | 16 | initial begin 17 | $dumpfile("blocking_tb.vcd"); 18 | $dumpvars(0, delete_tb); 19 | 20 | $monitor($time, " clock=%1b in=%1b out=%4b", clk, in, out1); 21 | #99 $display("Finishing simulation"); 22 | #1 $finish; 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /comparator/comparator.v: -------------------------------------------------------------------------------- 1 | module comparator( 2 | input input1, 3 | input input2, 4 | output out 5 | ); 6 | 7 | assign out = (~input1 & ~input2) | (input1 & input2); 8 | endmodule 9 | -------------------------------------------------------------------------------- /comparator/comparator_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module stimulus; 3 | //Inputs 4 | reg input1; 5 | reg input2; 6 | 7 | //Outputs 8 | wire out; 9 | 10 | //Instantiate the Unit Under Test (UUT) 11 | comparator uut ( 12 | .input1(input1), 13 | .input2(input2), 14 | .out(out) 15 | ); 16 | 17 | initial 18 | begin 19 | //initialioute Inputs 20 | input1 = 0; 21 | input2 = 0; 22 | 23 | #20 input2 = 1; 24 | #20 input1 = 1; input2 = 0; 25 | #20 input2 = 1; 26 | #40; 27 | end 28 | initial 29 | begin 30 | $monitor("%d,%d = %d \n", input1, input2, out); 31 | end 32 | endmodule 33 | -------------------------------------------------------------------------------- /comparator/design1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/comparator/design1.png -------------------------------------------------------------------------------- /comparator_bitwise/comparator: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 12; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0xe91050 .scope module, "stimulus" "stimulus" 2 2; 10 | .timescale -9 -12; 11 | v0xec43b0_0 .var "input1", 0 0; 12 | v0xec4450_0 .var "input2", 0 0; 13 | v0xec4520_0 .net "out", 0 0, L_0xec4950; 1 drivers 14 | S_0xeb1280 .scope module, "uut" "comparator" 2 11, 3 1 0, S_0xe91050; 15 | .timescale 0 0; 16 | .port_info 0 /INPUT 1 "input1" 17 | .port_info 1 /INPUT 1 "input2" 18 | .port_info 2 /OUTPUT 1 "out" 19 | L_0xec4620 .functor NOT 1, v0xec43b0_0, C4<0>, C4<0>, C4<0>; 20 | L_0xec4710 .functor NOT 1, v0xec4450_0, C4<0>, C4<0>, C4<0>; 21 | L_0xec47d0 .functor AND 1, L_0xec4620, L_0xec4710, C4<1>, C4<1>; 22 | L_0xec48e0 .functor AND 1, v0xec43b0_0, v0xec4450_0, C4<1>, C4<1>; 23 | L_0xec4950 .functor OR 1, L_0xec47d0, L_0xec48e0, C4<0>, C4<0>; 24 | v0xeb14a0_0 .net *"_s0", 0 0, L_0xec4620; 1 drivers 25 | v0xec3df0_0 .net *"_s2", 0 0, L_0xec4710; 1 drivers 26 | v0xec3ed0_0 .net *"_s4", 0 0, L_0xec47d0; 1 drivers 27 | v0xec3fc0_0 .net *"_s6", 0 0, L_0xec48e0; 1 drivers 28 | v0xec40a0_0 .net "input1", 0 0, v0xec43b0_0; 1 drivers 29 | v0xec41b0_0 .net "input2", 0 0, v0xec4450_0; 1 drivers 30 | v0xec4270_0 .net "out", 0 0, L_0xec4950; alias, 1 drivers 31 | .scope S_0xe91050; 32 | T_0 ; 33 | %vpi_call 2 19 "$dumpfile", "comparator.vcd" {0 0 0}; 34 | %vpi_call 2 20 "$dumpvars", 32'sb00000000000000000000000000000000, S_0xe91050 {0 0 0}; 35 | %pushi/vec4 0, 0, 1; 36 | %store/vec4 v0xec43b0_0, 0, 1; 37 | %pushi/vec4 0, 0, 1; 38 | %store/vec4 v0xec4450_0, 0, 1; 39 | %delay 20000, 0; 40 | %pushi/vec4 1, 0, 1; 41 | %store/vec4 v0xec4450_0, 0, 1; 42 | %delay 20000, 0; 43 | %pushi/vec4 1, 0, 1; 44 | %store/vec4 v0xec43b0_0, 0, 1; 45 | %pushi/vec4 0, 0, 1; 46 | %store/vec4 v0xec4450_0, 0, 1; 47 | %delay 20000, 0; 48 | %pushi/vec4 1, 0, 1; 49 | %store/vec4 v0xec4450_0, 0, 1; 50 | %delay 40000, 0; 51 | %end; 52 | .thread T_0; 53 | .scope S_0xe91050; 54 | T_1 ; 55 | %vpi_call 2 32 "$monitor", "%d,%d = %d \012", v0xec43b0_0, v0xec4450_0, v0xec4520_0 {0 0 0}; 56 | %end; 57 | .thread T_1; 58 | # The file index is used to find the file name in the following table. 59 | :file_names 4; 60 | "N/A"; 61 | ""; 62 | "comparator_tb.v"; 63 | "comparator.v"; 64 | -------------------------------------------------------------------------------- /comparator_bitwise/comparator.v: -------------------------------------------------------------------------------- 1 | module comparator( 2 | input input1, 3 | input input2, 4 | output out 5 | ); 6 | 7 | assign out = (~input1 & ~input2) | (input1 & input2); 8 | endmodule 9 | -------------------------------------------------------------------------------- /comparator_bitwise/comparator.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri May 6 22:40:21 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module stimulus $end 11 | $var wire 1 ! out $end 12 | $var reg 1 " input1 $end 13 | $var reg 1 # input2 $end 14 | $scope module uut $end 15 | $var wire 1 " input1 $end 16 | $var wire 1 # input2 $end 17 | $var wire 1 ! out $end 18 | $upscope $end 19 | $upscope $end 20 | $enddefinitions $end 21 | #0 22 | $dumpvars 23 | 0# 24 | 0" 25 | 1! 26 | $end 27 | #20000 28 | 0! 29 | 1# 30 | #40000 31 | 0# 32 | 1" 33 | #60000 34 | 1! 35 | 1# 36 | #100000 37 | -------------------------------------------------------------------------------- /comparator_bitwise/comparator_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module stimulus; 3 | //Inputs 4 | reg input1; 5 | reg input2; 6 | 7 | //Outputs 8 | wire out; 9 | 10 | //Instantiate the Unit Under Test (UUT) 11 | comparator uut ( 12 | .input1(input1), 13 | .input2(input2), 14 | .out(out) 15 | ); 16 | 17 | initial 18 | begin 19 | $dumpfile("comparator.vcd"); 20 | $dumpvars(0,stimulus); 21 | //initialioute Inputs 22 | input1 = 0; 23 | input2 = 0; 24 | 25 | #20 input2 = 1; 26 | #20 input1 = 1; input2 = 0; 27 | #20 input2 = 1; 28 | #40; 29 | end 30 | initial 31 | begin 32 | $monitor("%d,%d = %d \n", input1, input2, out); 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /comparator_bitwise/design1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/comparator_bitwise/design1.png -------------------------------------------------------------------------------- /comparator_bitwise/execute: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | iverilog -o comparator comparator.v comparator_tb.v 3 | -------------------------------------------------------------------------------- /comparator_bitwise/visualize: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | gtkwave comparator.vcd 3 | -------------------------------------------------------------------------------- /echowire/Makefile: -------------------------------------------------------------------------------- 1 | NAME=echowire 2 | DEPS = 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /echowire/echowire.pcf: -------------------------------------------------------------------------------- 1 | set_io tx 8 2 | set_io rx 9 3 | set_io rts 7 4 | set_io dtr 3 5 | set_io l2 98 6 | set_io l1 99 7 | -------------------------------------------------------------------------------- /echowire/echowire.v: -------------------------------------------------------------------------------- 1 | module echowire( 2 | input wire rx, 3 | input wire dtr, 4 | input wire rts, 5 | output wire tx, 6 | output wire l1, 7 | output wire l2 8 | ); 9 | 10 | assign tx = rx; 11 | assign l1 = dtr; 12 | assign l2 = rts; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /echowire/echowire_tb.v: -------------------------------------------------------------------------------- 1 | module echowire_tb; 2 | reg clk = 0; 3 | reg rts = 0; 4 | reg dtr = 0; 5 | reg rx = 0; 6 | 7 | wire tx, l1, l2; 8 | 9 | echowire uut( 10 | .rx(rx), 11 | .dtr(dtr), 12 | .rts(rts), 13 | .tx(tx), 14 | .l1(l1), 15 | .l2(l2) 16 | ); 17 | 18 | always #1 clk = !clk; 19 | 20 | initial begin 21 | $dumpfile("echowire_tb.vcd"); 22 | $dumpvars; 23 | 24 | $monitor($time, " rts=%b dtr=%b rx=%b tx=%b l1=%b l2=%b", rts, dtr, rx, tx, l1, l2); 25 | 26 | #1 rx <= 1; 27 | #5 rx <= 0; dtr <= 1; 28 | #5 rts <= 1; rx <= 0; 29 | #5 rts <= 0; rx <= 1; 30 | 31 | 32 | #5 $finish; 33 | end 34 | endmodule 35 | -------------------------------------------------------------------------------- /freq_divider/Makefile: -------------------------------------------------------------------------------- 1 | NAME=divM 2 | DEPS = 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | #-- Limpiar todo 62 | clean: 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /freq_divider/div3.v: -------------------------------------------------------------------------------- 1 | module div3(input wire clk_in, output wire clk_out); 2 | reg [1:0] divcounter = 0; 3 | 4 | //-- Modulus 3 counter 5 | always @(posedge clk_in) begin 6 | divcounter <= (divcounter == 2) ? 0 : divcounter + 1; 7 | end 8 | 9 | //Take out MSB 10 | assign clk_out = divcounter[1]; 11 | endmodule 12 | -------------------------------------------------------------------------------- /freq_divider/div3_tb.v: -------------------------------------------------------------------------------- 1 | module div3_tb; 2 | 3 | reg clk_in = 0; 4 | wire clk_out; 5 | 6 | div3 uut(.clk_in(clk_in), .clk_out(clk_out)); 7 | 8 | //Clock generator 9 | always #1 clk_in = ~clk_in; 10 | 11 | initial begin 12 | $dumpfile("div3_tb.vcd"); 13 | $dumpvars; 14 | 15 | #30 $display("Simulation finished"); 16 | $finish; 17 | end 18 | endmodule 19 | -------------------------------------------------------------------------------- /freq_divider/divM.pcf: -------------------------------------------------------------------------------- 1 | set_io out[0] 99 2 | set_io out[1] 98 3 | set_io out[2] 97 4 | set_io out[3] 96 5 | set_io clk_in 21 6 | -------------------------------------------------------------------------------- /freq_divider/divM.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /freq_divider/divM_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 100ps 2 | module divM_tb; 3 | 4 | reg clk_in = 0; 5 | wire clk_out; 6 | 7 | divM #(.number(2)) 8 | uut(.clk_in(clk_in), .clk_out(clk_out)); 9 | 10 | //Clock generator 11 | always #1 clk_in = ~clk_in; 12 | 13 | initial begin 14 | $dumpfile("divM_tb.vcd"); 15 | $dumpvars; 16 | 17 | #30 $display("Simulation finished"); 18 | $finish; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /freq_divider/prescaler.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 30; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /fsmtx/Makefile: -------------------------------------------------------------------------------- 1 | NAME=fsmtx 2 | DEPS=baudgen.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: clean sint load 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /fsmtx/baudgen.v: -------------------------------------------------------------------------------- 1 | //-- Fichero baudgen.v 2 | `include "baudgen.vh" 3 | 4 | //-- ENTRADAS: 5 | //-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick) 6 | //-- -clk_ena: Habilitacion. 7 | //-- 1. funcionamiento normal. Emitiendo pulsos 8 | //-- 0: Inicializado y parado. No se emiten pulsos 9 | // 10 | //-- SALIDAS: 11 | //-- - clk_out. Señal de salida que marca el tiempo entre bits 12 | //-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA 13 | module baudgen(input wire clk, 14 | input wire clk_ena, 15 | output wire clk_out); 16 | 17 | parameter M = `B115200; //Default baud rate. 104 18 | 19 | //-- Numero de bits para almacenar el divisor de baudios 20 | localparam N = $clog2(M); 21 | 22 | //-- Registro para implementar el contador modulo M 23 | reg [N-1:0] divcounter = 0; 24 | 25 | //-- Counter 26 | always @(posedge clk) 27 | if (clk_ena) 28 | divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; //Normal work 29 | else 30 | divcounter <= M - 1; //Counter freezed to maximum value 31 | 32 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 33 | //-- esta habilitado (clk_ena == 1) en caso contrario se saca 0 34 | assign clk_out = (divcounter == 0) ? clk_ena : 0; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /fsmtx/baudgen.vh: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Constantes para el modulo de generacion de baudios para comunicaciones serie 3 | //------------------------------------------------------------------------------ 4 | //-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan) 5 | //------------------------------------------------------------------------------ 6 | 7 | //-- Para la icestick el calculo es el siguiente: 8 | //-- Divisor = 12000000 / BAUDIOS (Y se redondea a numero entero) 9 | 10 | //-- Valores de los divisores para conseguir estos BAUDIOS: 11 | 12 | `define B115200 104 13 | `define B57600 208 14 | `define B38400 313 15 | 16 | `define B19200 625 17 | `define B9600 1250 18 | `define B4800 2500 19 | `define B2400 5000 20 | `define B1200 10000 21 | `define B600 20000 22 | `define B300 40000 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /fsmtx/fsmtx.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io start 3 3 | set_io tx 8 4 | -------------------------------------------------------------------------------- /fsmtx/fsmtx.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | `include "baudgen.vh" 4 | 5 | module fsmtx(input wire clk, 6 | input wire start, 7 | output reg tx 8 | ); 9 | 10 | parameter BAUD = `B300; 11 | parameter CHAR = "A"; 12 | 13 | reg [9:0] shifter; //10 bits reg to store the bits array 14 | reg start_r; //Start signal 15 | wire clk_baud; //Baud out clock 16 | reg reset = 0; 17 | reg [3:0] bitCounter; //Bit counter 18 | 19 | //Microorders 20 | wire load; //Load shifter. Activated when state is START 21 | wire baud_en; //Enable baud generator. Activated when state isn't IDLE 22 | 23 | 24 | //--DATA ROUTE 25 | 26 | //Pass the start wire into a register so that we follow sync rules 27 | always @(posedge clk) begin 28 | start_r <= start; 29 | end 30 | 31 | //Loads shifter reg with either the default value, the char or displaces 32 | //shifter one bit 33 | always @ (posedge clk) begin 34 | if (reset == 0) 35 | shifter <= 10'b11_111_111; 36 | else if (load == 1) 37 | shifter <= {CHAR, 2'b01}; 38 | else if (load == 0 && clk_baud == 1) 39 | shifter <= {1'b1, shifter[9:1]}; 40 | end 41 | 42 | //Resets bitcounter when load or add 1 to it. 43 | always @(posedge clk) begin 44 | if (load == 1) 45 | bitCounter <= 0; 46 | else if (load == 0 && clk_baud == 1) 47 | bitCounter <= bitCounter + 1; 48 | end 49 | 50 | //Shifter mode 51 | always @(posedge clk) begin 52 | tx <= shifter[0]; 53 | end 54 | 55 | baudgen #(BAUD) 56 | BAUD0 ( 57 | .clk(clk), 58 | .clk_ena(baud_en), 59 | .clk_out(clk_baud) 60 | ); 61 | 62 | //-- 63 | //-- CONTROLLER 64 | //-- 65 | localparam IDLE = 0; 66 | localparam START = 1; 67 | localparam TRANS = 2; 68 | 69 | reg [1:0] state; 70 | 71 | // Define state transitions 72 | // IDLE--> START--> TRANS --> IDLE 73 | always @(posedge clk) begin 74 | if (reset == 0) begin 75 | state <= IDLE; 76 | end else begin 77 | case (state) 78 | IDLE: 79 | if (start_r == 1) begin 80 | state <= START; 81 | end else begin 82 | state <= IDLE; 83 | end 84 | START: 85 | state <= TRANS; 86 | TRANS: 87 | if (bitCounter == 11) begin 88 | state <= IDLE; 89 | end else begin 90 | state <= TRANS; 91 | end 92 | default: 93 | state <= IDLE; 94 | endcase 95 | end 96 | end 97 | 98 | //Orders assign 99 | assign load = (state == START) ? 1 : 0; 100 | assign baud_en = (state == IDLE) ? 0 : 1; 101 | 102 | //Init 103 | always @(posedge clk) 104 | reset <= 1; 105 | 106 | endmodule 107 | -------------------------------------------------------------------------------- /fsmtx/fsmtx_tb.v: -------------------------------------------------------------------------------- 1 | //-- Fichero: fsmtx.v 2 | `include "baudgen.vh" 3 | 4 | module fsmtx_tb(); 5 | 6 | //-- Baudios con los que realizar la simulacion 7 | //-- A 300 baudios, la simulacion tarda mas en realizarse porque los 8 | //-- tiempos son mas largos. A 115200 baudios la simulacion es mucho 9 | //-- mas rapida 10 | localparam BAUD = `B115200; 11 | 12 | //-- Tics de reloj para envio de datos a esa velocidad 13 | //-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades 14 | localparam BITRATE = (BAUD << 1); 15 | 16 | //-- Tics necesarios para enviar una trama serie completa, mas un bit adicional 17 | localparam FRAME = (BITRATE * 11); 18 | 19 | //-- Tiempo entre dos bits enviados 20 | localparam FRAME_WAIT = (BITRATE * 4); 21 | 22 | //-- Registro para generar la señal de reloj 23 | reg clk = 0; 24 | 25 | //-- Linea de tranmision 26 | wire tx; 27 | 28 | //-- Simulacion de la señal start 29 | reg start = 0; 30 | 31 | //-- Instanciar el componente 32 | fsmtx #(.BAUD(BAUD)) 33 | dut( 34 | .clk(clk), 35 | .start(start), 36 | .tx(tx) 37 | ); 38 | 39 | //-- Generador de reloj. Periodo 2 unidades 40 | always 41 | # 1 clk <= ~clk; 42 | 43 | 44 | //-- Proceso al inicio 45 | initial begin 46 | 47 | //-- Fichero donde almacenar los resultados 48 | $dumpfile("fsmtx_tb.vcd"); 49 | $dumpvars(0, fsmtx_tb); 50 | 51 | #1 start <= 0; 52 | 53 | //-- Enviar primer caracter 54 | #FRAME_WAIT start <= 1; 55 | #(BITRATE * 2) start <=0; 56 | 57 | //-- Segundo envio (2 caracteres mas) 58 | #(FRAME_WAIT * 2) start <=1; 59 | #(FRAME * 1) start <=0; 60 | 61 | #(FRAME_WAIT * 4) $display("FIN de la simulacion"); 62 | $finish; 63 | end 64 | 65 | endmodule 66 | -------------------------------------------------------------------------------- /gate_level_modeling/a.out: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0x1af4010 .scope module, "my_gate_tb" "my_gate_tb" 2 1; 10 | .timescale 0 0; 11 | v0x1b27f00_0 .var "x", 0 0; 12 | v0x1b27fa0_0 .var "y", 0 0; 13 | v0x1b28070_0 .net "z", 0 0, L_0x1b284d0; 1 drivers 14 | S_0x1b14280 .scope module, "uut" "my_gate" 2 7, 3 1 0, S_0x1af4010; 15 | .timescale 0 0; 16 | .port_info 0 /INPUT 1 "x" 17 | .port_info 1 /INPUT 1 "y" 18 | .port_info 2 /OUTPUT 1 "z" 19 | L_0x1b28170 .functor NOT 1, v0x1b27f00_0, C4<0>, C4<0>, C4<0>; 20 | L_0x1b28260 .functor NOT 1, v0x1b27fa0_0, C4<0>, C4<0>, C4<0>; 21 | L_0x1b28320 .functor AND 1, v0x1b27f00_0, v0x1b27fa0_0, C4<1>, C4<1>; 22 | L_0x1b28390 .functor AND 1, L_0x1b28170, L_0x1b28260, C4<1>, C4<1>; 23 | L_0x1b284d0 .functor OR 1, L_0x1b28320, L_0x1b28390, C4<0>, C4<0>; 24 | v0x1b14450_0 .net "p", 0 0, L_0x1b28320; 1 drivers 25 | v0x1b279a0_0 .net "q", 0 0, L_0x1b28390; 1 drivers 26 | v0x1b27a60_0 .net "x", 0 0, v0x1b27f00_0; 1 drivers 27 | v0x1b27b30_0 .net "x_", 0 0, L_0x1b28170; 1 drivers 28 | v0x1b27bf0_0 .net "y", 0 0, v0x1b27fa0_0; 1 drivers 29 | v0x1b27d00_0 .net "y_", 0 0, L_0x1b28260; 1 drivers 30 | v0x1b27dc0_0 .net "z", 0 0, L_0x1b284d0; alias, 1 drivers 31 | .scope S_0x1af4010; 32 | T_0 ; 33 | %pushi/vec4 0, 0, 1; 34 | %store/vec4 v0x1b27f00_0, 0, 1; 35 | %pushi/vec4 0, 0, 1; 36 | %store/vec4 v0x1b27fa0_0, 0, 1; 37 | %delay 20, 0; 38 | %delay 20, 0; 39 | %pushi/vec4 1, 0, 1; 40 | %store/vec4 v0x1b27fa0_0, 0, 1; 41 | %delay 20, 0; 42 | %pushi/vec4 1, 0, 1; 43 | %store/vec4 v0x1b27f00_0, 0, 1; 44 | %delay 20, 0; 45 | %pushi/vec4 0, 0, 1; 46 | %store/vec4 v0x1b27fa0_0, 0, 1; 47 | %delay 20, 0; 48 | %end; 49 | .thread T_0; 50 | .scope S_0x1af4010; 51 | T_1 ; 52 | %vpi_call 2 24 "$monitor", "TIME=%3d: x=%2b y=%2b z=%d \012", $time, v0x1b27f00_0, v0x1b27fa0_0, v0x1b28070_0, " " {0 0 0}; 53 | %end; 54 | .thread T_1; 55 | # The file index is used to find the file name in the following table. 56 | :file_names 4; 57 | "N/A"; 58 | ""; 59 | "gate_tb.v"; 60 | "gate.v"; 61 | -------------------------------------------------------------------------------- /gate_level_modeling/design1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/gate_level_modeling/design1.png -------------------------------------------------------------------------------- /gate_level_modeling/execute: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog gate.v gate_tb.v; ./a.out 4 | -------------------------------------------------------------------------------- /gate_level_modeling/gate.v: -------------------------------------------------------------------------------- 1 | module my_gate( 2 | input x, 3 | input y, 4 | output z 5 | ); 6 | wire x_, y_, p,q; 7 | not(x_, x); 8 | not(y_, y); 9 | and(p, x,y); 10 | and(q, x_,y_); 11 | or(z,p,q); 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /gate_level_modeling/gate_tb.v: -------------------------------------------------------------------------------- 1 | module my_gate_tb; 2 | reg x; 3 | reg y; 4 | 5 | wire z; 6 | 7 | my_gate uut (.x(x), .y(y), .z(z)); 8 | 9 | initial begin 10 | // Initialize Inputs 11 | x = 0; 12 | y = 0; 13 | 14 | // Wait 100 ns for global reset to finish 15 | #20; 16 | //Current state is 00 17 | #20 y = 1; //01 18 | #20 x = 1; //11 19 | #20 y = 0; //10 20 | #20 ; 21 | end 22 | 23 | initial begin 24 | $monitor("TIME=%3d: x=%2b y=%2b z=%d \n",$time,x,y,z, ); 25 | end 26 | endmodule 27 | -------------------------------------------------------------------------------- /gate_level_modeling/test.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri May 6 22:00:33 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module gate_tb $end 11 | $var wire 1 ! output0 $end 12 | $var reg 2 " input0 [1:0] $end 13 | $var reg 2 # input1 [1:0] $end 14 | $scope module uut $end 15 | $var wire 1 $ input0 $end 16 | $var wire 1 % input0_ $end 17 | $var wire 1 & input1 $end 18 | $var wire 1 ' input1_ $end 19 | $var wire 1 ! output0 $end 20 | $var wire 1 ( p $end 21 | $var wire 1 ) q $end 22 | $upscope $end 23 | $upscope $end 24 | $enddefinitions $end 25 | #0 26 | $dumpvars 27 | 1) 28 | 0( 29 | 1' 30 | 0& 31 | 1% 32 | 0$ 33 | b0 # 34 | b0 " 35 | 1! 36 | $end 37 | #150 38 | 0! 39 | 0) 40 | 0% 41 | 1$ 42 | b1 " 43 | #210 44 | 1! 45 | 0' 46 | 1( 47 | 1& 48 | b1 # 49 | #360 50 | 0! 51 | 1% 52 | 0( 53 | 0$ 54 | b0 " 55 | -------------------------------------------------------------------------------- /generic_rom/dividerp1.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Divisor de reloj 3 | //-- Señal de periodo igual al indicado 4 | //-- El ancho del pulso positivo es de 1 ciclo de reloj 5 | //-- 6 | //-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan) 7 | //----------------------------------------------------------------------------- 8 | //-- GPL license 9 | //----------------------------------------------------------------------------- 10 | `include "divider.vh" 11 | 12 | //-- ENTRADAS: 13 | //-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick) 14 | // 15 | //-- SALIDAS: 16 | //-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada 17 | //-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA 18 | module dividerp1(input wire clk, 19 | output wire clk_out); 20 | 21 | //-- Valor por defecto de la velocidad en baudios 22 | parameter M = `T_100ms; 23 | 24 | //-- Numero de bits para almacenar el divisor de baudios 25 | localparam N = $clog2(M); 26 | 27 | //-- Registro para implementar el contador modulo M 28 | reg [N-1:0] divcounter = 0; 29 | 30 | //-- Contador módulo M 31 | always @(posedge clk) 32 | divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; 33 | 34 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 35 | assign clk_out = (divcounter == 0) ? 1 : 0; 36 | 37 | 38 | endmodule 39 | 40 | 41 | 42 | 43 | -------------------------------------------------------------------------------- /generic_rom/genrom.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | //-- Memoria ROM genérica 3 | //------------------------------------------ 4 | //-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan) 5 | //-- GPL license 6 | //---------------------------------------------------------------------------- 7 | //-- Memoria con los siguientes parametros: 8 | //-- * AW: Numero de bits de las direcciones 9 | //-- * DW: Numero de bits de los datos 10 | //-- * ROMFILE: Fichero a usar para cargar la memoria 11 | //-- 12 | //-- Con este componente podemos hacer memorias rom de cualquier tamaño 13 | //---------------------------------------------------------------------------- 14 | 15 | module genrom #( //-- Parametros 16 | parameter AW = 5, //-- Bits de las direcciones (Adress width) 17 | parameter DW = 4) //-- Bits de los datos (Data witdh) 18 | 19 | ( //-- Puertos 20 | input clk, //-- Señal de reloj global 21 | input wire [AW-1: 0] addr, //-- Direcciones 22 | output reg [DW-1: 0] data); //-- Dato de salida 23 | 24 | //-- Parametro: Nombre del fichero con el contenido de la ROM 25 | parameter ROMFILE = "rom1.list"; 26 | 27 | //-- Calcular el numero de posiciones totales de memoria 28 | localparam NPOS = 2 ** AW; 29 | 30 | //-- Memoria 31 | reg [DW-1: 0] rom [0: NPOS-1]; 32 | 33 | //-- Lectura de la memoria 34 | always @(posedge clk) begin 35 | data <= rom[addr]; 36 | end 37 | 38 | //-- Cargar en la memoria el fichero ROMFILE 39 | //-- Los valores deben estan dados en hexadecimal 40 | initial begin 41 | $readmemh(ROMFILE, rom); 42 | end 43 | 44 | 45 | endmodule 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /generic_rom/genromleds.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io leds[0] 99 3 | set_io leds[1] 98 4 | set_io leds[2] 97 5 | set_io leds[3] 96 6 | set_io leds[4] 95 7 | set_io clk 21 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | -------------------------------------------------------------------------------- /generic_rom/genromleds.v: -------------------------------------------------------------------------------- 1 | //---------------------------------------------------------------------------- 2 | //-- Ejemplo de uso de una memoria rom generica 3 | //-- Se reproduce en los leds la secuencia definida en el fichero rom1.list 4 | //------------------------------------------ 5 | //-- (C) BQ. October 2015. Written by Juan Gonzalez (Obijuan) 6 | //-- GPL license 7 | //---------------------------------------------------------------------------- 8 | `default_nettype none 9 | 10 | `include "divider.vh" 11 | 12 | module genromleds (input wire clk, 13 | output wire [4:0] leds); 14 | 15 | //- Tiempo de envio 16 | parameter DELAY = `T_500ms; 17 | 18 | //-- Fichero con la rom 19 | parameter ROMFILE = "rom1.list"; 20 | 21 | //-- Numero de bits de la direccione 22 | parameter AW = 5; 23 | parameter DW = 5; 24 | 25 | //-- Cable para direccionar la memoria 26 | reg [AW-1: 0] addr; 27 | 28 | reg rstn = 0; 29 | wire clk_delay; 30 | 31 | //-- Instanciar la memoria rom 32 | genrom 33 | #( .ROMFILE(ROMFILE), 34 | .AW(AW), 35 | .DW(DW)) 36 | ROM ( 37 | .clk(clk), 38 | .addr(addr), 39 | .data(leds) 40 | ); 41 | 42 | //-- Contador 43 | always @(negedge clk) 44 | if (rstn == 0) 45 | addr <= 0; 46 | else if (clk_delay) 47 | addr <= addr + 1; 48 | 49 | //--------------------------- 50 | //-- Temporizador 51 | //--------------------------- 52 | dividerp1 #(.M(DELAY)) 53 | DIV0 ( .clk(clk), 54 | .clk_out(clk_delay) 55 | ); 56 | 57 | //-- Inicializador 58 | always @(negedge clk) 59 | rstn <= 1; 60 | 61 | endmodule 62 | 63 | -------------------------------------------------------------------------------- /generic_rom/genromleds_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI 3 | [*] Sun Oct 18 18:49:52 2015 4 | [*] 5 | [dumpfile] "/home/obijuan/development/open-fpga-verilog-tutorial/tutorial/T27-rom-param/genromleds_tb.vcd" 6 | [dumpfile_mtime] "Sun Oct 18 18:49:41 2015" 7 | [dumpfile_size] 3896 8 | [savefile] "/home/obijuan/development/open-fpga-verilog-tutorial/tutorial/T27-rom-param/genromleds_tb.gtkw" 9 | [timestart] 0 10 | [size] 1000 600 11 | [pos] -1 -1 12 | *-5.468258 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] genromleds_tb. 14 | [treeopen] genromleds_tb.dut. 15 | [sst_width] 223 16 | [signals_width] 102 17 | [sst_expanded] 1 18 | [sst_vpaned_height] 160 19 | @28 20 | genromleds_tb.clk 21 | @23 22 | genromleds_tb.leds[4:0] 23 | [pattern_trace] 1 24 | [pattern_trace] 0 25 | -------------------------------------------------------------------------------- /generic_rom/genromleds_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- genromleds_tb.v 3 | //-- Banco de pruebas para el secuenciador de luces, implementado con 4 | //-- una memoria rom generica 5 | //------------------------------------------------------------------- 6 | //-- BQ August 2015. Written by Juan Gonzalez (Obijuan) 7 | //------------------------------------------------------------------- 8 | 9 | module genromleds_tb(); 10 | 11 | //-- Para la simulacion se usa un retraso de 2 ciclos de reloj 12 | parameter DELAY = 2; 13 | parameter ROMFILE = "rom1.list"; 14 | 15 | //-- Registro para generar la señal de reloj 16 | reg clk = 0; 17 | 18 | //-- Datos de salida del componente 19 | wire [4:0] leds; 20 | 21 | //-- Instanciar el componente 22 | genromleds #(.DELAY(DELAY), .ROMFILE(ROMFILE)) 23 | dut( 24 | .clk(clk), 25 | .leds(leds) 26 | ); 27 | 28 | //-- Generador de reloj. Periodo 2 unidades 29 | always #1 clk = ~clk; 30 | 31 | 32 | //-- Proceso al inicio 33 | initial begin 34 | 35 | //-- Fichero donde almacenar los resultados 36 | $dumpfile("genromleds_tb.vcd"); 37 | $dumpvars(0, genromleds_tb); 38 | 39 | # 140 $display("FIN de la simulacion"); 40 | $finish; 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /generic_rom/imperial.list: -------------------------------------------------------------------------------- 1 | //-- Marcha imperial 2 | 0 //-- Un 0 es un SILENCIO 3 | 0 4 | 0 5 | 0 6 | 0 7 | 0 8 | 0 9 | 0 10 | 0 11 | 471A //-- MI_4 12 | 471A 13 | 0 14 | 471A //-- MI_4 15 | 471A 16 | 0 17 | 471A //-- MI_4 18 | 471A 19 | 0 20 | 5996 //-- DO_4 21 | 5996 22 | 3BCA //-- SOL_4 23 | 471A //-- MI_4 24 | 471A 25 | 0 26 | 5996 //-- DO_4 27 | 5996 28 | 3BCA //-- SOL_4 29 | 471A //-- MI_4 30 | 471A 31 | //----------- Segundo trozo 32 | 0 33 | 0 34 | 0 35 | 2F75 //-- SI_4 36 | 2F75 37 | 0 38 | 2F75 //-- SI_4 39 | 2F75 40 | 0 41 | 2F75 //-- SI_4 42 | 2F75 43 | 0 44 | 2CCB //-- DO_5 45 | 2CCB 46 | 3BCA //-- SOL_4 47 | 471A //-- MI_4 48 | 471A 49 | 0 50 | 5996 //-- DO_4 51 | 5996 52 | 3BCA //-- SOL_4 53 | 471A //-- MI_4 54 | 471A 55 | 56 | -------------------------------------------------------------------------------- /generic_rom/notas_gen.py: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------------------------------ 2 | #-- Generacion automatica de las tablas con las frecuencias y valores 3 | #-- de los divisores para tocas todas las notas musicales en la iCEstick 4 | #-- 5 | #-- Genera todas las constantes en formato Verilog, para poder incluir 6 | #-- la tabla directametne en nuestros programas 7 | #------------------------------------------------------------------------------ 8 | #-- (C) BQ. September-2015. Written by Juan Gonzalez (Obijuan) 9 | #------------------------------------------------------------------------------ 10 | import math as m 11 | 12 | #--------------------------------------------- 13 | #-- octavas: 0 - 10 14 | #-- Notas: 1 - 12 15 | #-- 1 - DO 16 | #-- 2 - DO# 17 | #-- 3 - RE 18 | #-- 4 - RE# 19 | #-- 5 - MI 20 | #-- 6 - FA 21 | #-- 7 - FA# 22 | #-- 8 - SOL 23 | #-- 9 - SOL# 24 | #-- 10 - LA 25 | #-- 11 - LA# 26 | #-- 12 - SI 27 | 28 | ##-- Diccionario con los nombres de las notas 29 | nname = {1: 'DO', 2: 'DOs', 3: 'RE', 4 : 'REs', 30 | 5: 'MI', 6: 'FA', 7: 'FAs', 8: 'SOL', 31 | 9: 'SOLs', 10: 'LA', 11: 'LAs', 12: 'SI'}; 32 | 33 | #-- Calcular la frecuencia de una nota de una octava 34 | def freq(note, octave = 4): 35 | return 440.0 * m.exp(((octave-4)+(note-10)/12.0) * m.log(2)) 36 | 37 | #-- Calcular el valor del divisor para tocar la nota en la FPGA 38 | #-- de la placa iCEstick 39 | def divisor(note, octave = 4): 40 | return int(round(12000000 / (2*freq(note, octave)))) 41 | 42 | #-- Imprimir la table, con salida verilog 43 | def print_table(octave = 4): 44 | print("//-- Octava: {}".format(octave)) 45 | for note in range(12): 46 | #-- Print table in verilog sintax 47 | print("`define {}_{} {:X} //-- {:.3f} Hz".format( 48 | nname[note + 1], 49 | octave, 50 | divisor(note+1, octave), 51 | freq(note+1, octave))) 52 | print("\n") 53 | 54 | #-- Programa principal 55 | #-- Sacar la tabla por la pantalla 56 | for oct in range(11): 57 | print_table(oct) 58 | 59 | 60 | 61 | 62 | 63 | -------------------------------------------------------------------------------- /generic_rom/notegen.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Divisor de frecuencias para generacion de notas musicales 3 | //-- (c) BQ. October 2015. written by Juan Gonzalez (obijuan) 4 | //----------------------------------------------------------------------------- 5 | //-- GPL license 6 | //----------------------------------------------------------------------------- 7 | //-- Esta formado por dos divisores en cadena. El primero genera un pulso 8 | //-- de anchura 1 ciclo de reloj, y frecuencia de la nota 2 * note 9 | //-- Esta señal se pasa por un divisor entre 2, para generar una señal con 10 | //-- ciclo de trabajo del 50% y frecuencia note 11 | //----------------------------------------------------------------------------- 12 | 13 | module notegen(input wire clk, //-- Senal de reloj global 14 | input wire rstn, //-- Reset 15 | input wire [15:0] note, //-- Divisor 16 | output reg clk_out); //-- Señal de salida 17 | 18 | wire clk_tmp; 19 | 20 | //-- Registro para implementar el contador modulo note 21 | reg [15:0] divcounter = 0; 22 | 23 | //-- Contador módulo note 24 | always @(posedge clk) 25 | 26 | //-- Reset 27 | if (rstn == 0) 28 | divcounter <= 0; 29 | 30 | //-- Si la nota es 0 no se incrementa contador 31 | else if (note == 0) 32 | divcounter <= 0; 33 | 34 | //-- Si se alcanza el tope, poner a 0 35 | else if (divcounter == note - 1) 36 | divcounter <= 0; 37 | 38 | //-- Incrementar contador 39 | else 40 | divcounter <= divcounter + 1; 41 | 42 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 43 | assign clk_tmp = (divcounter == 0) ? 1 : 0; 44 | 45 | //-- Divisor de frecuencia entre 2, para obtener como salida una señal 46 | //-- con un ciclo de trabajo del 50% 47 | always @(posedge clk) 48 | if (rstn == 0) 49 | clk_out <= 0; 50 | 51 | else if (note == 0) 52 | clk_out <= 0; 53 | 54 | else if (clk_tmp == 1) 55 | clk_out <= ~clk_out; 56 | 57 | endmodule 58 | 59 | 60 | 61 | -------------------------------------------------------------------------------- /generic_rom/rom1.list: -------------------------------------------------------------------------------- 1 | //-- Fichero rom1.list 2 | //-- Cada linea se corresponde con una posicion de memoria 3 | //-- Se pueden poner comentarios 4 | //-- ROM1: contiene los numeros del 0 al 31 (en hexadecimal) 5 | 0 //-- Posicion 0 6 | 1 //-- Posicion 1 7 | 2 8 | 3 9 | 4 10 | 5 11 | 6 12 | 7 13 | 8 14 | 9 15 | A 16 | B 17 | C 18 | D 19 | E 20 | F 21 | 10 22 | 11 23 | 12 24 | 13 25 | 14 26 | 15 27 | 16 28 | 17 29 | 18 30 | 19 31 | 1A 32 | 1B 33 | 1C 34 | 1D 35 | 1E 36 | 1F 37 | 38 | -------------------------------------------------------------------------------- /generic_rom/romnotes.pcf: -------------------------------------------------------------------------------- 1 | set_io leds[0] 99 2 | set_io leds[1] 98 3 | set_io leds[2] 97 4 | set_io leds[3] 96 5 | set_io leds[4] 95 6 | set_io ch_out 44 7 | set_io clk 21 8 | 9 | 10 | 11 | 12 | 13 | -------------------------------------------------------------------------------- /generic_rom/romnotes.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Reproductor de melodias almacenadas en memoria rom 3 | //-- Los 5 bits menos significativos de la nota se sacan por los leds 4 | //----------------------------------------------------------------------------- 5 | //-- (C) BQ. October 2015. Written by Juan Gonzalez 6 | //----------------------------------------------------------------------------- 7 | //-- GPL license 8 | //----------------------------------------------------------------------------- 9 | 10 | //-- Incluir las constantes del modulo del divisor 11 | `include "divider.vh" 12 | 13 | //-- Parameteros: 14 | //-- clk: Reloj de entrada de la placa iCEstick 15 | //-- ch_out: Canal de salida 16 | module romnotes(input wire clk, 17 | output wire [4:0] leds, 18 | output wire ch_out); 19 | 20 | //-- Parametros 21 | //-- Duracion de las notas 22 | parameter DUR = `T_200ms; 23 | 24 | //-- Fichero con las notas para cargar en la rom 25 | parameter ROMFILE = "imperial.list"; 26 | 27 | //-- Tamaño del bus de direcciones de la rom 28 | parameter AW = 6; 29 | 30 | //-- Tamaño de las notas 31 | parameter DW = 16; 32 | 33 | //-- Cables de salida de los canales 34 | wire ch0, ch1, ch2; 35 | 36 | //-- Selección del canal del multiplexor 37 | reg [AW-1: 0] addr = 0; 38 | 39 | //-- Reloj con la duracion de la nota 40 | wire clk_dur; 41 | reg rstn = 0; 42 | 43 | wire [DW-1: 0] note; 44 | 45 | //-- Instanciar la memoria rom 46 | genrom 47 | #( .ROMFILE(ROMFILE), 48 | .AW(AW), 49 | .DW(DW)) 50 | ROM ( 51 | .clk(clk), 52 | .addr(addr), 53 | .data(note) 54 | ); 55 | 56 | 57 | //-- Generador de notas 58 | notegen 59 | CH0 ( 60 | .clk(clk), 61 | .rstn(rstn), 62 | .note(note), 63 | .clk_out(ch_out) 64 | ); 65 | 66 | //-- Sacar los 5 bits menos significativos de la nota por los leds 67 | assign leds = note[4:0]; 68 | 69 | //-- Inicializador 70 | always @(posedge clk) 71 | rstn <= 1; 72 | 73 | 74 | //-- Contador para seleccion de nota 75 | always @(posedge clk) 76 | if (clk_dur) 77 | addr <= addr + 1; 78 | 79 | //-- Divisor para marcar la duración de cada nota 80 | dividerp1 #(DUR) 81 | TIMER0 ( 82 | .clk(clk), 83 | .clk_out(clk_dur) 84 | ); 85 | 86 | 87 | endmodule 88 | 89 | 90 | 91 | -------------------------------------------------------------------------------- /generic_rom/romnotes_tb.gtkw: -------------------------------------------------------------------------------- 1 | [*] 2 | [*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI 3 | [*] Wed Oct 21 07:01:09 2015 4 | [*] 5 | [dumpfile] "/home/obijuan/development/open-fpga-verilog-tutorial/tutorial/T27-rom-param/romnotes_tb.vcd" 6 | [dumpfile_mtime] "Wed Oct 21 07:00:07 2015" 7 | [dumpfile_size] 6508 8 | [savefile] "/home/obijuan/development/open-fpga-verilog-tutorial/tutorial/T27-rom-param/romnotes_tb.gtkw" 9 | [timestart] 28 10 | [size] 1018 316 11 | [pos] -856 -429 12 | *-4.421464 97 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 13 | [treeopen] romnotes_tb. 14 | [sst_width] 223 15 | [signals_width] 102 16 | [sst_expanded] 1 17 | [sst_vpaned_height] 60 18 | @29 19 | romnotes_tb.clk 20 | @28 21 | romnotes_tb.ch_out 22 | @22 23 | romnotes_tb.dut.leds[4:0] 24 | [pattern_trace] 1 25 | [pattern_trace] 0 26 | -------------------------------------------------------------------------------- /generic_rom/romnotes_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- romnotes_tb.v 3 | //-- Banco de pruebas para el reproductor de melodias 4 | //------------------------------------------------------------------- 5 | //-- BQ October 2015. Written by Juan Gonzalez (Obijuan) 6 | //------------------------------------------------------------------- 7 | //-- GPL License 8 | //------------------------------------------------------------------- 9 | 10 | module romnotes_tb(); 11 | 12 | //-- Registro para generar la señal de reloj 13 | reg clk = 0; 14 | 15 | //-- Salidas de los canales 16 | wire ch_out; 17 | 18 | 19 | //-- Instanciar el componente y establecer el valor del divisor 20 | //-- Se pone un valor bajo para simular (de lo contrario tardaria mucho) 21 | romnotes #(.DUR(2)) 22 | dut( 23 | .clk(clk), 24 | .ch_out(ch_out) 25 | ); 26 | 27 | //-- Generador de reloj. Periodo 2 unidades 28 | always 29 | # 1 clk <= ~clk; 30 | 31 | 32 | //-- Proceso al inicio 33 | initial begin 34 | 35 | //-- Fichero donde almacenar los resultados 36 | $dumpfile("romnotes_tb.vcd"); 37 | $dumpvars(0, romnotes_tb); 38 | 39 | # 200 $display("FIN de la simulacion"); 40 | $finish; 41 | end 42 | 43 | endmodule 44 | 45 | -------------------------------------------------------------------------------- /hello/a.out: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision + 0; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0xf41340 .scope module, "hello" "hello" 2 1; 10 | .timescale 0 0; 11 | .scope S_0xf41340; 12 | T_0 ; 13 | %vpi_call 2 4 "$display", "Hello Mario" {0 0 0}; 14 | %vpi_call 2 5 "$finish" {0 0 0}; 15 | %end; 16 | .thread T_0; 17 | # The file index is used to find the file name in the following table. 18 | :file_names 3; 19 | "N/A"; 20 | ""; 21 | "hello.v"; 22 | -------------------------------------------------------------------------------- /hello/hello.v: -------------------------------------------------------------------------------- 1 | module hello; 2 | initial 3 | begin 4 | $display("Hello Mario"); 5 | $finish ; 6 | end 7 | endmodule 8 | -------------------------------------------------------------------------------- /icestick_pinout.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/icestick_pinout.png -------------------------------------------------------------------------------- /icestickusermanual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/icestickusermanual.pdf -------------------------------------------------------------------------------- /if-statement/execute.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog -o encoder priority_encoder.v priority_encoder_tb.v 4 | vvp encoder 5 | gtkwave dump.vcd 6 | -------------------------------------------------------------------------------- /if-statement/priority_encoder.v: -------------------------------------------------------------------------------- 1 | // Code your design here 2 | module priority_encoder(input wire [3:0] in, output reg [2:0] out); 3 | 4 | always @(in[3], in[2], in[1], in[0]) 5 | begin 6 | if (in[3] == 1'b1) 7 | out = 3'b100; 8 | else if (in[2] == 1'b1) 9 | out = 3'b011; 10 | else if (in[1] == 1'b1) 11 | out = 3'b010; 12 | else 13 | out = 3'b001; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /if-statement/priority_encoder_tb.v: -------------------------------------------------------------------------------- 1 | // Code your testbench here 2 | // or browse Einamples 3 | module priority_encoder_tb; 4 | reg [3:0] in; 5 | wire [2:0] out; 6 | 7 | priority_encoder uut( 8 | .in(in), 9 | .out(out) 10 | ); 11 | 12 | 13 | initial begin 14 | $dumpfile("dump.vcd"); 15 | $dumpvars(0, priority_encoder_tb); 16 | 17 | in = 4'b0000; 18 | 19 | #20 in = 4'b0001; 20 | #20 in = 4'b0010; 21 | #20 in = 4'b0011; 22 | #20 in = 4'b0100; 23 | #20 in = 4'b0101; 24 | #20 in = 4'b0110; 25 | #20 in = 4'b0111; 26 | #20 in = 4'b1000; 27 | #20 in = 4'b1001; 28 | #20 in = 4'b1010; 29 | #20 in = 4'b1011; 30 | #20 in = 4'b1100; 31 | #20 in = 4'b1101; 32 | #20 in = 4'b1110; 33 | #20 in = 4'b1111; 34 | #40 ; 35 | end 36 | 37 | initial begin 38 | $monitor("t=%3d in=%4b,out=%3b", $time, in, out); 39 | end 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /initializer/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------- 2 | #-- Objetivo por defecto: hacer simulacion y sintesis 3 | #------------------------------------------------------- 4 | all: sint 5 | 6 | #---------------------------------------------- 7 | #-- make sim 8 | #---------------------------------------------- 9 | #-- Objetivo para hacer la simulacion del 10 | #-- banco de pruebas 11 | #---------------------------------------------- 12 | sim: initializer_tb.vcd 13 | 14 | #----------------------------------------------- 15 | #- make sint 16 | #----------------------------------------------- 17 | #- Objetivo para realizar la sintetis completa 18 | #- y dejar el diseno listo para su grabacion en 19 | #- la FPGA 20 | #----------------------------------------------- 21 | sint: initializer.bin 22 | 23 | #------------------------------- 24 | #-- Compilacion y simulacion 25 | #------------------------------- 26 | initializer_tb.vcd: initializer.v initializer_tb.v 27 | 28 | #-- Compilar 29 | iverilog -o initializer.out initializer.v initializer_tb.v 30 | 31 | #-- Simular 32 | ./initializer.out 33 | 34 | #-- Crear VCD 35 | vvp initializer.out 36 | 37 | #-- Ver visualmente la simulacion con gtkwave 38 | gtkwave initializer.vcd & 39 | 40 | #------------------------------ 41 | #-- Sintesis completa 42 | #------------------------------ 43 | initializer.bin: initializer.v initializer.pcf 44 | 45 | #-- Sintesis 46 | /usr/local/bin/yosys -p "synth_ice40 -blif initializer.blif" initializer.v 47 | 48 | #-- Place & route 49 | arachne-pnr -d 1k -p initializer.pcf initializer.blif -o initializer.txt 50 | 51 | #-- Generar binario final, listo para descargar en fgpa 52 | icepack initializer.txt initializer.bin 53 | 54 | #-- Cargar en FPGA 55 | load: 56 | iceprog initializer.bin 57 | 58 | #-- Limpiar todo 59 | clean: 60 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 61 | 62 | .PHONY: all clean 63 | -------------------------------------------------------------------------------- /initializer/initializer.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io ini 95 3 | -------------------------------------------------------------------------------- /initializer/initializer.v: -------------------------------------------------------------------------------- 1 | module init(input wire clk, output wire ini); 2 | wire din; 3 | reg dout = 0; 4 | 5 | always @ ( posedge(clk) ) 6 | dout <= din; 7 | 8 | assign din = 1; 9 | 10 | assign ini = dout; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /initializer/initializer_tb.v: -------------------------------------------------------------------------------- 1 | module initializer_tb; 2 | reg clk = 0; 3 | 4 | wire ini; 5 | 6 | init 7 | INIT( 8 | .clk(clk), 9 | .ini(ini) 10 | ); 11 | 12 | always #2 clk = ~clk; 13 | 14 | initial begin 15 | $dumpfile("initializer.vcd"); 16 | $dumpvars; 17 | 18 | #20 $display("End of simulation"); 19 | $finish; 20 | end 21 | endmodule 22 | -------------------------------------------------------------------------------- /m_to_1_multiplexer/Makefile: -------------------------------------------------------------------------------- 1 | NAME=muxm 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /m_to_1_multiplexer/muxm.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io out_data[0] 99 3 | set_io out_data[1] 98 4 | set_io out_data[2] 97 5 | set_io out_data[3] 96 6 | -------------------------------------------------------------------------------- /m_to_1_multiplexer/muxm.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 22; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | 14 | module muxm(input wire clk, output reg[3:0]out_data); 15 | parameter BITS = 22; 16 | wire [3:0] in1 = 4'b0000; 17 | wire [3:0] in2 = 4'b1010; 18 | wire [3:0] in3 = 4'b1111; 19 | wire [3:0] in4 = 4'b0101; 20 | 21 | reg [1:0] sel = 0; 22 | 23 | wire clk_prescaled; 24 | 25 | prescaler #(.BITS(BITS)) 26 | Pres1(.clk_in(clk), .clk_out(clk_prescaled)); 27 | 28 | always @* begin 29 | case (sel) 30 | 0: out_data <= in1; 31 | 1: out_data <= in2; 32 | 2: out_data <= in3; 33 | 3: out_data <= in4; 34 | default: out_data <= 0; 35 | endcase 36 | end 37 | 38 | always @ ( posedge(clk_prescaled) ) begin 39 | sel <= sel + 1; 40 | end 41 | 42 | endmodule 43 | -------------------------------------------------------------------------------- /m_to_1_multiplexer/muxm_tb.v: -------------------------------------------------------------------------------- 1 | //------------------------------------------------------------------- 2 | //-- mux4_tb.v 3 | //-- Banco de pruebas para el secuenciador de 4 estados con multiplexor 4 | //-- de 4 a 1 5 | //------------------------------------------------------------------- 6 | //-- BQ August 2015. Written by Juan Gonzalez (Obijuan) 7 | //------------------------------------------------------------------- 8 | 9 | module mux4_tb(); 10 | 11 | //-- Registro para generar la señal de reloj 12 | reg clk = 0; 13 | 14 | //-- Datos de salida del componente 15 | wire [3:0] data; 16 | 17 | //-- Instanciar el componente, con prescaler de 1 bit (para la simulacion) 18 | muxm #(.BITS(1)) 19 | dut( 20 | .clk(clk), 21 | .out_data(data) 22 | ); 23 | 24 | //-- Generador de reloj. Periodo 2 unidades 25 | always #1 clk = ~clk; 26 | 27 | 28 | //-- Proceso al inicio 29 | initial begin 30 | 31 | //-- Fichero donde almacenar los resultados 32 | $dumpfile("muxm_tb.vcd"); 33 | $dumpvars(0, mux4_tb); 34 | 35 | # 30 $display("FIN de la simulacion"); 36 | $finish; 37 | end 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /multiple_prescalers/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------- 2 | #-- Objetivo por defecto: hacer simulacion y sintesis 3 | #------------------------------------------------------- 4 | all: sint 5 | 6 | #---------------------------------------------- 7 | #-- make sim 8 | #---------------------------------------------- 9 | #-- Objetivo para hacer la simulacion del 10 | #-- banco de pruebas 11 | #---------------------------------------------- 12 | sim: multiple_prescaler_tb.vcd 13 | 14 | #----------------------------------------------- 15 | #- make sint 16 | #----------------------------------------------- 17 | #- Objetivo para realizar la sintetis completa 18 | #- y dejar el diseno listo para su grabacion en 19 | #- la FPGA 20 | #----------------------------------------------- 21 | sint: multiple_prescaler.bin 22 | 23 | #------------------------------- 24 | #-- Compilacion y simulacion 25 | #------------------------------- 26 | multiple_prescaler_tb.vcd: multiple_prescaler.v multiple_prescaler_tb.v 27 | 28 | #-- Compilar 29 | iverilog -o multiple_prescaler.out multiple_prescaler.v multiple_prescaler_tb.v 30 | 31 | #-- Simular 32 | ./multiple_prescaler.out 33 | 34 | #-- Crear VCD 35 | vvp multiple_prescaler.out 36 | 37 | #-- Ver visualmente la simulacion con gtkwave 38 | gtkwave multiple_prescaler.vcd & 39 | 40 | #------------------------------ 41 | #-- Sintesis completa 42 | #------------------------------ 43 | multiple_prescaler.bin: multiple_prescaler.v multiple_prescaler.pcf 44 | 45 | #-- Sintesis 46 | /usr/local/bin/yosys -p "synth_ice40 -blif multiple_prescaler.blif" multiple_prescaler.v 47 | 48 | #-- Place & route 49 | arachne-pnr -d 1k -p multiple_prescaler.pcf multiple_prescaler.blif -o multiple_prescaler.txt 50 | 51 | #-- Generar binario final, listo para descargar en fgpa 52 | icepack multiple_prescaler.txt multiple_prescaler.bin 53 | 54 | #-- Cargar en FPGA 55 | load: 56 | iceprog multiple_prescaler.bin 57 | 58 | #-- Limpiar todo 59 | clean: 60 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 61 | 62 | .PHONY: all clean 63 | -------------------------------------------------------------------------------- /multiple_prescalers/multiple_prescaler.pcf: -------------------------------------------------------------------------------- 1 | set_io LED1 99 2 | set_io LED2 98 3 | set_io LED3 97 4 | set_io LED4 96 5 | set_io GREEN 95 6 | set_io clk_in 21 7 | -------------------------------------------------------------------------------- /multiple_prescalers/multiple_prescaler.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 30; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | module mpres ( 14 | input wire clk_in, 15 | output wire LED1, 16 | output wire LED2, 17 | output wire LED3, 18 | output wire LED4, 19 | output GREEN 20 | ); 21 | 22 | parameter BITS0 = 22; //--Prescaler base 23 | parameter BITS1 = 1; 24 | parameter BITS2 = 2; 25 | parameter BITS3 = 3; 26 | parameter BITS4 = 4; 27 | 28 | wire clk_base; 29 | 30 | wire GREEN = 1'b1; 31 | 32 | prescaler #(.BITS(BITS0)) 33 | Pres0(.clk_in(clk_in), .clk_out(clk_base)); 34 | 35 | prescaler #(.BITS(BITS1)) 36 | Pres1(.clk_in(clk_base), .clk_out(LED1)); 37 | 38 | prescaler #(.BITS(BITS2)) 39 | Pres2(.clk_in(clk_base), .clk_out(LED2)); 40 | 41 | prescaler #(.BITS(BITS3)) 42 | Pres3(.clk_in(clk_base), .clk_out(LED3)); 43 | 44 | prescaler #(.BITS(BITS4)) 45 | Pres4(.clk_in(clk_base), .clk_out(LED4)); 46 | 47 | endmodule // mpres 48 | -------------------------------------------------------------------------------- /multiple_prescalers/multiple_prescaler_tb.v: -------------------------------------------------------------------------------- 1 | module mpres_tb(); 2 | parameter BITS0 = 1; 3 | parameter BITS1 = 1; 4 | parameter BITS2 = 2; 5 | parameter BITS3 = 3; 6 | parameter BITS4 = 4; 7 | 8 | reg clk = 0; 9 | 10 | wire LED1, LED2, LED3, LED4, GREEN; 11 | 12 | mpres 13 | #( 14 | .BITS0(BITS0), 15 | .BITS1(BITS1), 16 | .BITS2(BITS2), 17 | .BITS3(BITS3), 18 | .BITS4(BITS4), 19 | .GREEN(1) 20 | ) 21 | dut( 22 | .clk_in(clk), 23 | .LED1(LED1), 24 | .LED2(LED2), 25 | .LED3(LED3), 26 | .LED4(LED4) 27 | ); 28 | 29 | always #1 clk = ~clk; 30 | 31 | initial begin 32 | $dumpfile("multiple_prescaler.vcd"); 33 | $dumpvars; 34 | 35 | #20 $display("End of simulation"); 36 | #21 $finish; 37 | end 38 | endmodule 39 | -------------------------------------------------------------------------------- /multiplexer/mux_2_1.v: -------------------------------------------------------------------------------- 1 | module Mux2_1(out,cntrl,in1,in2); 2 | input cntrl,in1,in2; 3 | output out; 4 | assign out = cntrl ? in1 : in2; 5 | endmodule 6 | -------------------------------------------------------------------------------- /multiplexer/mux_2_1_tb.v: -------------------------------------------------------------------------------- 1 | module mux2tb; 2 | wire out; 3 | reg cntrl,in1,in2; 4 | 5 | Mux2_1 uut(out,cntrl,in1,in2); 6 | 7 | initial begin 8 | $monitor("in1=%b in2=%b cntrl=%b out=%b",in1,in2,cntrl,out); 9 | cntrl=0;in1=0;in2=0; 10 | #1 in1=1;in2=0; 11 | #1 in1=0;in2=1; 12 | #1 in1=1; in2=1; 13 | #1 cntrl=1; 14 | #1 in1=0;in2=0; 15 | #1 in1=1;in2=0; 16 | #1 in1=0;in2=1; 17 | #1 in1=1; in2=1; 18 | #10 $finish; 19 | end 20 | endmodule 21 | -------------------------------------------------------------------------------- /multiplexer/mux_4_2.v: -------------------------------------------------------------------------------- 1 | module Mux4_2(out, control1, control2, in1, in2, in3, in4); 2 | input control1, control2, in1, in2, in3, in4; 3 | output out; 4 | assign out = control1 ? (control2 ? in4 : in3) : (control2 ? in2 : in1); 5 | endmodule 6 | -------------------------------------------------------------------------------- /multiplexer/mux_4_2.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sat May 7 00:11:27 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 100ps 9 | $end 10 | $scope module mux_4_2_tb $end 11 | $var wire 1 ! out $end 12 | $var reg 1 " control1 $end 13 | $var reg 1 # control2 $end 14 | $var reg 1 $ in1 $end 15 | $var reg 1 % in2 $end 16 | $var reg 1 & in3 $end 17 | $var reg 1 ' in4 $end 18 | $scope module uut $end 19 | $var wire 1 " control1 $end 20 | $var wire 1 # control2 $end 21 | $var wire 1 $ in1 $end 22 | $var wire 1 % in2 $end 23 | $var wire 1 & in3 $end 24 | $var wire 1 ' in4 $end 25 | $var wire 1 ! out $end 26 | $upscope $end 27 | $upscope $end 28 | $enddefinitions $end 29 | #0 30 | $dumpvars 31 | 0' 32 | 0& 33 | 0% 34 | 0$ 35 | 0# 36 | 0" 37 | 0! 38 | $end 39 | #10 40 | 1' 41 | #20 42 | 0' 43 | 1& 44 | #30 45 | 1' 46 | #40 47 | 0' 48 | 0& 49 | 1% 50 | #50 51 | 1' 52 | #60 53 | 0' 54 | 1& 55 | #70 56 | 1' 57 | #80 58 | 1! 59 | 0' 60 | 0& 61 | 0% 62 | 1$ 63 | #90 64 | 1' 65 | #100 66 | 0' 67 | 1& 68 | #110 69 | 1' 70 | #120 71 | 0' 72 | 0& 73 | 1% 74 | #130 75 | 1' 76 | #140 77 | 0' 78 | 1& 79 | #150 80 | 1' 81 | #160 82 | 0! 83 | 0' 84 | 0& 85 | 0% 86 | 0$ 87 | 1# 88 | #170 89 | 1' 90 | #180 91 | 0' 92 | 1& 93 | #190 94 | 1' 95 | #200 96 | 1! 97 | 0' 98 | 0& 99 | 1% 100 | #210 101 | 1' 102 | #220 103 | 0' 104 | 1& 105 | #230 106 | 1' 107 | #240 108 | 0! 109 | 0' 110 | 0& 111 | 0% 112 | 1$ 113 | #250 114 | 1' 115 | #260 116 | 0' 117 | 1& 118 | #270 119 | 1' 120 | #280 121 | 1! 122 | 0' 123 | 0& 124 | 1% 125 | #290 126 | 1' 127 | #300 128 | 0' 129 | 1& 130 | #310 131 | 1' 132 | #320 133 | 0! 134 | 0' 135 | 0& 136 | 0% 137 | 0$ 138 | 0# 139 | 1" 140 | #330 141 | 1' 142 | #340 143 | 1! 144 | 0' 145 | 1& 146 | #350 147 | 1' 148 | #360 149 | 0! 150 | 0' 151 | 0& 152 | 1% 153 | #370 154 | 1' 155 | #380 156 | 1! 157 | 0' 158 | 1& 159 | #390 160 | 1' 161 | #400 162 | 0! 163 | 0' 164 | 0& 165 | 0% 166 | 1$ 167 | #410 168 | 1' 169 | #420 170 | 1! 171 | 0' 172 | 1& 173 | #430 174 | 1' 175 | #440 176 | 0! 177 | 0' 178 | 0& 179 | 1% 180 | #450 181 | 1' 182 | #460 183 | 1! 184 | 0' 185 | 1& 186 | #470 187 | 1' 188 | #480 189 | 0! 190 | 0' 191 | 0& 192 | 0% 193 | 0$ 194 | 1# 195 | #490 196 | 1! 197 | 1' 198 | #500 199 | 0! 200 | 0' 201 | 1& 202 | #510 203 | 1! 204 | 1' 205 | #520 206 | 0! 207 | 0' 208 | 0& 209 | 1% 210 | #530 211 | 1! 212 | 1' 213 | #540 214 | 0! 215 | 0' 216 | 1& 217 | #550 218 | 1! 219 | 1' 220 | #560 221 | 0! 222 | 0' 223 | 0& 224 | 0% 225 | 1$ 226 | #570 227 | 1! 228 | 1' 229 | #580 230 | 0! 231 | 0' 232 | 1& 233 | #590 234 | 1! 235 | 1' 236 | #600 237 | 0! 238 | 0' 239 | 0& 240 | 1% 241 | #610 242 | 1! 243 | 1' 244 | #620 245 | 0! 246 | 0' 247 | 1& 248 | #630 249 | 1! 250 | 1' 251 | #730 252 | -------------------------------------------------------------------------------- /mux_case/mux_case.v: -------------------------------------------------------------------------------- 1 | module mux_case(input wire [1:0] in, input control, output reg out); 2 | 3 | always @ ( * ) begin 4 | case(control) 5 | 1'b0: 6 | out = in[0]; 7 | 1'b1: 8 | out = in[1]; 9 | endcase 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /mux_case/mux_case_tb.v: -------------------------------------------------------------------------------- 1 | module mux_case_tb; 2 | wire out; 3 | reg control; 4 | reg [1:0] in; 5 | 6 | mux_case uut(.in(in), .control(control), .out(out)); 7 | 8 | initial begin 9 | $monitor($time, ": IN_1=%b IN_2=%b CTRL=%b OUT=%b", in[0], in[1], control, out); 10 | control=0; in = 2'b00; 11 | 12 | #1 in=2'b10; 13 | #1 in=2'b01; 14 | #1 in=2'b11; 15 | #1 control=1; 16 | #1 in=2'b00; 17 | #1 in=2'b01; 18 | #1 in=2'b10; 19 | #1 in=2'b11; 20 | #10; $finish; 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /n_bits_register/Makefile: -------------------------------------------------------------------------------- 1 | NAME=regreset 2 | DEPS = prescaler.v register.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | #-- Limpiar todo 62 | clean: 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /n_bits_register/prescaler.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 28; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /n_bits_register/register.v: -------------------------------------------------------------------------------- 1 | //register.v 2 | 3 | //N bits register 4 | module register(clk, reset, din, out_data); 5 | 6 | parameter BITS = 4; 7 | parameter INI = 0; 8 | 9 | input wire clk; 10 | input wire reset; 11 | input wire [BITS-1:0] din; 12 | output reg [BITS-1:0] out_data; 13 | 14 | always @(posedge clk) begin 15 | out_data <= (reset == 0) ? INI : din; 16 | end 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /n_bits_register/regreset.pcf: -------------------------------------------------------------------------------- 1 | set_io out_data[0] 99 2 | set_io out_data[1] 98 3 | set_io out_data[2] 97 4 | set_io out_data[3] 96 5 | set_io clk 21 6 | -------------------------------------------------------------------------------- /n_bits_register/regreset.v: -------------------------------------------------------------------------------- 1 | //-- regreset.v 2 | module regreset(input wire clk, output wire [3:0] out_data); 3 | parameter BITS = 24; 4 | parameter INI0 = 4'b1001; 5 | parameter INI1 = 4'b0110; 6 | 7 | wire clk_prescaled; 8 | 9 | wire [3:0] dout0; 10 | wire [3:0] dout1; 11 | 12 | reg reset = 0; 13 | 14 | //-- Inicializador 15 | always @(posedge(clk_prescaled)) 16 | reset <= 1; 17 | 18 | //0 Register 19 | register #(.INI(INI0), .BITS(4)) 20 | REG0( 21 | .clk(clk_prescaled), 22 | .reset(reset), 23 | .din(dout1), 24 | .out_data(dout0) 25 | ); 26 | //1 Register 27 | register #(.INI(INI1), .BITS(4)) 28 | REG1( 29 | .clk(clk_prescaled), 30 | .reset(reset), 31 | .din(dout0), 32 | .out_data(dout1) 33 | ); 34 | 35 | assign out_data = dout0; 36 | 37 | prescaler #(.BITS(BITS)) 38 | Pres1(.clk_in(clk), .clk_out(clk_prescaled)); 39 | endmodule 40 | -------------------------------------------------------------------------------- /notes_seq/Makefile: -------------------------------------------------------------------------------- 1 | # NAME=notes_seq 2 | # DEPS=muxm.v divM.v 2_bit_counter.v tone_gen.v 3 | NAME=notes_seq 4 | DEPS=divM.v tone_gen.v 5 | 6 | #------------------------------------------------------- 7 | #-- Objetivo por defecto: hacer simulacion y sintesis 8 | #------------------------------------------------------- 9 | all: sint 10 | 11 | #---------------------------------------------- 12 | #-- make sim 13 | #---------------------------------------------- 14 | #-- Objetivo para hacer la simulacion del 15 | #-- banco de pruebas 16 | #---------------------------------------------- 17 | sim: $(NAME)_tb.vcd 18 | 19 | #----------------------------------------------- 20 | #- make sint 21 | #----------------------------------------------- 22 | #- Objetivo para realizar la sintetis completa 23 | #- y dejar el diseno listo para su grabacion en 24 | #- la FPGA 25 | #----------------------------------------------- 26 | sint: $(NAME).bin 27 | 28 | #------------------------------- 29 | #-- Compilacion y simulacion 30 | #------------------------------- 31 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Compilar 34 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 35 | 36 | #-- Simular 37 | ./$(NAME).out 38 | 39 | #-- Crear VCD 40 | vvp $(NAME).out 41 | 42 | #-- Ver visualmente la simulacion con gtkwave 43 | gtkwave $(NAME)_tb.vcd 44 | 45 | #------------------------------ 46 | #-- Sintesis completa 47 | #------------------------------ 48 | $(NAME).bin: $(NAME).v $(NAME).pcf 49 | 50 | #-- Sintesis 51 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 52 | 53 | #-- Place & route 54 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 55 | 56 | #-- Generar binario final, listo para descargar en fgpa 57 | icepack $(NAME).txt $(NAME).bin 58 | 59 | #-- Cargar en FPGA 60 | load: 61 | iceprog $(NAME).bin 62 | 63 | #-- Limpiar todo 64 | clean: 65 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 66 | 67 | .PHONY: all clean 68 | -------------------------------------------------------------------------------- /notes_seq/divM.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /notes_seq/notes_seq.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_in 21 2 | set_io tone 44 3 | -------------------------------------------------------------------------------- /notes_seq/notes_seq.v: -------------------------------------------------------------------------------- 1 | //-- Incluir las constantes del modulo del divisor 2 | `include "divider.vh" 3 | 4 | module notes_seq(input wire clk_in, output wire tone); 5 | parameter TIME = 3_000_000; 6 | reg ch_out = 0; 7 | 8 | //Wire to take the output of the following divisor that'll generate a 250ms clock 9 | wire time_delay; 10 | 11 | divM #(`T_1s) DURATION(.clk_in(clk_in), .clk_out(time_delay)); 12 | 13 | //Output of the tones 14 | wire ch0, ch1, ch2; 15 | 16 | //Create the three tones 17 | tone_gen #(.freq(`DO_4)) CH0(.clk_in(clk_in), .tone(ch0)); 18 | tone_gen #(.freq(`RE_4)) CH1(.clk_in(clk_in), .tone(ch1)); 19 | tone_gen #(.freq(`MI_4)) CH2(.clk_in(clk_in), .tone(ch2)); 20 | 21 | //Mux channel selector 22 | reg [1:0] chSel = 0; 23 | 24 | //-- Multiplexor de seleccion del canal de salida 25 | always @* 26 | case (chSel) 27 | 0 : ch_out <= ch0; 28 | 1 : ch_out <= ch1; 29 | 2 : ch_out <= ch2; 30 | 3 : ch_out <= 0; 31 | endcase 32 | 33 | always @ ( posedge time_delay ) begin 34 | chSel <= chSel + 1; 35 | end 36 | 37 | assign tone = ch_out; 38 | 39 | endmodule 40 | -------------------------------------------------------------------------------- /notes_seq/notes_seq_tb.v: -------------------------------------------------------------------------------- 1 | module notes_seq_tb; 2 | reg clk = 0; 3 | wire out; 4 | 5 | parameter TIME = 5; 6 | 7 | notes_seq #(.TIME(TIME)) uut(.clk_in(clk), .tone(out)); 8 | 9 | always #1 clk = !clk; 10 | 11 | initial begin 12 | $dumpfile("notes_seq_tb.vcd"); 13 | $dumpvars; 14 | 15 | $monitor($time, ": clk=%b out=%d", clk, out); 16 | 17 | #1000 $finish; 18 | end 19 | endmodule 20 | -------------------------------------------------------------------------------- /notes_seq/tone_gen.v: -------------------------------------------------------------------------------- 1 | module tone_gen(input wire clk_in, output wire tone); 2 | parameter freq = 1000; 3 | wire clk_out; 4 | 5 | divM #(.number(freq)) divider(.clk_in(clk_in), .clk_out(clk_out)); 6 | 7 | assign tone = clk_out; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /prescaler/Makefile: -------------------------------------------------------------------------------- 1 | #------------------------------------------------------- 2 | #-- Objetivo por defecto: hacer simulacion y sintesis 3 | #------------------------------------------------------- 4 | all: sint 5 | 6 | #---------------------------------------------- 7 | #-- make sim 8 | #---------------------------------------------- 9 | #-- Objetivo para hacer la simulacion del 10 | #-- banco de pruebas 11 | #---------------------------------------------- 12 | sim: prescaler_tb.vcd 13 | 14 | #----------------------------------------------- 15 | #- make sint 16 | #----------------------------------------------- 17 | #- Objetivo para realizar la sintetis completa 18 | #- y dejar el diseno listo para su grabacion en 19 | #- la FPGA 20 | #----------------------------------------------- 21 | sint: prescaler.bin 22 | 23 | #------------------------------- 24 | #-- Compilacion y simulacion 25 | #------------------------------- 26 | prescaler_tb.vcd: prescaler.v prescaler_tb.v 27 | 28 | #-- Compilar 29 | iverilog -o prescaler.out prescaler.v prescaler_tb.v 30 | 31 | #-- Simular 32 | ./prescaler.out 33 | 34 | #-- Crear VCD 35 | vvp prescaler.out 36 | 37 | #-- Ver visualmente la simulacion con gtkwave 38 | gtkwave prescaler.vcd & 39 | 40 | #------------------------------ 41 | #-- Sintesis completa 42 | #------------------------------ 43 | prescaler.bin: prescaler.v prescaler.pcf 44 | 45 | #-- Sintesis 46 | /usr/local/bin/yosys -p "synth_ice40 -blif prescaler.blif" prescaler.v 47 | 48 | #-- Place & route 49 | arachne-pnr -d 1k -p prescaler.pcf prescaler.blif -o prescaler.txt 50 | 51 | #-- Generar binario final, listo para descargar en fgpa 52 | icepack prescaler.txt prescaler.bin 53 | 54 | #-- Cargar en FPGA 55 | load: 56 | iceprog prescaler.bin 57 | 58 | #-- Limpiar todo 59 | clean: 60 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 61 | 62 | .PHONY: all clean 63 | -------------------------------------------------------------------------------- /prescaler/prescaler.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_out 99 2 | set_io clk 21 3 | -------------------------------------------------------------------------------- /prescaler/prescaler.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 30; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /prescaler/prescaler_tb.v: -------------------------------------------------------------------------------- 1 | module prescaler_tb; 2 | reg clk = 0; 3 | wire out; 4 | 5 | reg [1:0] count = 0; 6 | 7 | parameter BITS = 2; 8 | 9 | prescaler #(.BITS(BITS)) 10 | Pres1( 11 | .clk(clk), 12 | .clk_out(out) 13 | ); 14 | 15 | always #1 clk = ~clk; 16 | 17 | always @ ( posedge clk ) begin 18 | count <= count + 1; 19 | 20 | $monitor($time, ": count=%d, clk=%b, out=%b", count, clk, out); 21 | end 22 | 23 | initial begin 24 | $dumpfile("prescaler.vcd"); 25 | $dumpvars(0, prescaler_tb); 26 | #20 $finish; 27 | end 28 | endmodule 29 | -------------------------------------------------------------------------------- /ram_mem/.gitignore: -------------------------------------------------------------------------------- 1 | .pioenvs -------------------------------------------------------------------------------- /ram_mem/.travis.yml: -------------------------------------------------------------------------------- 1 | # Continuous Integration (CI) is the practice, in software 2 | # engineering, of merging all developer working copies with a shared mainline 3 | # several times a day < http://docs.platformio.org/en/latest/ci/index.html > 4 | # 5 | # Documentation: 6 | # 7 | # * Travis CI Embedded Builds with PlatformIO 8 | # < https://docs.travis-ci.com/user/integration/platformio/ > 9 | # 10 | # * PlatformIO integration with Travis CI 11 | # < http://docs.platformio.org/en/latest/ci/travis.html > 12 | # 13 | # * User Guide for `platformio ci` command 14 | # < http://docs.platformio.org/en/latest/userguide/cmd_ci.html > 15 | # 16 | # 17 | # Please choice one of the following templates (proposed below) and uncomment 18 | # it (remove "# " before each line) or use own configuration according to the 19 | # Travis CI documentation (see above). 20 | # 21 | 22 | 23 | # 24 | # Template #1: General project. Test it using existing `platformio.ini`. 25 | # 26 | 27 | # language: python 28 | # python: 29 | # - "2.7" 30 | # 31 | # sudo: false 32 | # cache: 33 | # directories: 34 | # - "~/.platformio" 35 | # 36 | # install: 37 | # - pip install -U platformio 38 | # 39 | # script: 40 | # - platformio run 41 | 42 | 43 | # 44 | # Template #2: The project is intended to by used as a library with examples 45 | # 46 | 47 | # language: python 48 | # python: 49 | # - "2.7" 50 | # 51 | # sudo: false 52 | # cache: 53 | # directories: 54 | # - "~/.platformio" 55 | # 56 | # env: 57 | # - PLATFORMIO_CI_SRC=path/to/test/file.c 58 | # - PLATFORMIO_CI_SRC=examples/file.ino 59 | # - PLATFORMIO_CI_SRC=path/to/test/directory 60 | # 61 | # install: 62 | # - pip install -U platformio 63 | # 64 | # script: 65 | # - platformio ci --lib="." --board=TYPE_1 --board=TYPE_2 --board=TYPE_N 66 | -------------------------------------------------------------------------------- /ram_mem/lib/readme.txt: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for the project specific (private) libraries. 3 | PlatformIO will compile them to static libraries and link to executable file. 4 | 5 | The source code of each library should be placed in separate directory, like 6 | "lib/private_lib/[here are source files]". 7 | 8 | For example, see how can be organized `Foo` and `Bar` libraries: 9 | 10 | |--lib 11 | | |--Bar 12 | | | |--docs 13 | | | |--examples 14 | | | |--src 15 | | | |- Bar.c 16 | | | |- Bar.h 17 | | |--Foo 18 | | | |- Foo.c 19 | | | |- Foo.h 20 | | |- readme.txt --> THIS FILE 21 | |- platformio.ini 22 | |--src 23 | |- main.c 24 | 25 | Then in `src/main.c` you should use: 26 | 27 | #include 28 | #include 29 | 30 | // rest H/C/CPP code 31 | 32 | PlatformIO will find your libraries automatically, configure preprocessor's 33 | include paths and build them. 34 | 35 | See additional options for PlatformIO Library Dependency Finder `lib_*`: 36 | 37 | http://docs.platformio.org/en/latest/projectconf.html#lib-install 38 | 39 | -------------------------------------------------------------------------------- /ram_mem/platformio.ini: -------------------------------------------------------------------------------- 1 | # 2 | # Project Configuration File 3 | # 4 | # A detailed documentation with the EXAMPLES is located here: 5 | # http://docs.platformio.org/en/latest/projectconf.html 6 | # 7 | 8 | # A sign `#` at the beginning of the line indicates a comment 9 | # Comment lines are ignored. 10 | 11 | # Simple and base environment 12 | # [env:mybaseenv] 13 | # platform = %INSTALLED_PLATFORM_NAME_HERE% 14 | # framework = 15 | # board = 16 | # 17 | # Automatic targets - enable auto-uploading 18 | # targets = upload 19 | 20 | [env:icestick] 21 | platform = lattice_ice40 22 | framework = icestorm 23 | board = icestick 24 | -------------------------------------------------------------------------------- /ram_mem/src/Makefile: -------------------------------------------------------------------------------- 1 | NAME=ram_mem 2 | DEPS = 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /ram_mem/src/ram_mem.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | -------------------------------------------------------------------------------- /ram_mem/src/ram_mem.v: -------------------------------------------------------------------------------- 1 | module ram_mem( 2 | input wire clk, 3 | input wire [3:0] address, 4 | input wire mode, 5 | input wire [3:0] data, 6 | output reg [3:0] out 7 | ); 8 | 9 | reg [3:0] ram [0:15]; 10 | 11 | initial begin 12 | ram[0] = 4'd0; 13 | ram[1] = 4'd1; 14 | ram[2] = 4'd2; 15 | ram[3] = 4'd3; 16 | ram[4] = 4'd4; 17 | ram[5] = 4'd5; 18 | ram[6] = 4'd6; 19 | ram[7] = 4'd7; 20 | ram[8] = 4'd8; 21 | ram[9] = 4'd9; 22 | ram[10] = 4'd10; 23 | ram[11] = 4'd11; 24 | ram[12] = 4'd12; 25 | ram[13] = 4'd13; 26 | ram[14] = 4'd14; 27 | ram[15] = 4'd15; 28 | end 29 | 30 | always @ ( posedge clk ) begin 31 | if(mode == 0) begin //Read 32 | out <= ram[address]; 33 | end 34 | end 35 | 36 | always @ ( posedge clk ) begin 37 | if (mode == 1) begin //Write 38 | ram[address] <= data; 39 | out <= 0; 40 | end 41 | end 42 | 43 | endmodule 44 | -------------------------------------------------------------------------------- /ram_mem/src/ram_mem_tb.v: -------------------------------------------------------------------------------- 1 | module ram_mem_tb; 2 | 3 | reg clk = 0; 4 | reg [3:0] address = 4'd0; 5 | reg [3:0] data; 6 | reg mode; 7 | wire [3:0] out; 8 | 9 | ram_mem uut(.clk(clk), .address(address), .data(data), .mode(mode), .out(out)); 10 | 11 | always #1 clk = !clk; 12 | 13 | initial begin 14 | $dumpfile("ram_mem_tb.vcd"); 15 | $dumpvars; 16 | 17 | $monitor($time, ": clk=%b data=%b address=%b mode=%b out=%d", clk, data, address, mode, out); 18 | 19 | #1 mode=0; data=4'b0; address=0; 20 | #1 mode=0; data=4'b0; address=1; 21 | #1 mode=0; data=4'b0; address=2; 22 | #1 mode=0; data=4'b0; address=5; 23 | #1 mode=0; data=4'b0; address=10; 24 | #1 mode=0; data=4'b0; address=12; 25 | #1 mode=0; data=4'b0; address=15; 26 | #2 mode=1; 27 | data=4'd9; address=0; 28 | #2 mode=0; 29 | data=4'b0; address=0; 30 | #2 mode=1; 31 | data=4'd11; address=0; 32 | #2 mode=0; 33 | data=4'b0; address=0; 34 | #2 mode=0; 35 | data=4'b0; address=0; 36 | #2 mode=1; 37 | data=4'd13; address=0; 38 | #2 mode=0; 39 | data=4'b0; address=0; 40 | 41 | $finish; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /ram_mem/src/ram_mem_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Fri May 20 22:34:43 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1s 9 | $end 10 | $scope module ram_mem_tb $end 11 | $var wire 4 ! out [3:0] $end 12 | $var reg 4 " address [3:0] $end 13 | $var reg 1 # clk $end 14 | $var reg 4 $ data [3:0] $end 15 | $var reg 1 % mode $end 16 | $scope module uut $end 17 | $var wire 4 & address [3:0] $end 18 | $var wire 1 # clk $end 19 | $var wire 4 ' data [3:0] $end 20 | $var wire 1 % mode $end 21 | $var reg 4 ( out [3:0] $end 22 | $upscope $end 23 | $upscope $end 24 | $enddefinitions $end 25 | #0 26 | $dumpvars 27 | bx ( 28 | bx ' 29 | b0 & 30 | x% 31 | bx $ 32 | 0# 33 | b0 " 34 | bx ! 35 | $end 36 | #1 37 | b0 ! 38 | b0 ( 39 | b0 $ 40 | b0 ' 41 | 0% 42 | 1# 43 | #2 44 | b1 " 45 | b1 & 46 | 0# 47 | #3 48 | b10 ! 49 | b10 ( 50 | b10 " 51 | b10 & 52 | 1# 53 | #4 54 | b101 " 55 | b101 & 56 | 0# 57 | #5 58 | b1010 ! 59 | b1010 ( 60 | b1010 " 61 | b1010 & 62 | 1# 63 | #6 64 | b1100 " 65 | b1100 & 66 | 0# 67 | #7 68 | b1111 ! 69 | b1111 ( 70 | b1111 " 71 | b1111 & 72 | 1# 73 | #8 74 | 0# 75 | #9 76 | b0 ! 77 | b0 ( 78 | 1# 79 | b0 " 80 | b0 & 81 | b1001 $ 82 | b1001 ' 83 | 1% 84 | #10 85 | 0# 86 | #11 87 | b1001 ! 88 | b1001 ( 89 | 1# 90 | b0 $ 91 | b0 ' 92 | 0% 93 | #12 94 | 0# 95 | #13 96 | b0 ! 97 | b0 ( 98 | 1# 99 | b1011 $ 100 | b1011 ' 101 | 1% 102 | #14 103 | 0# 104 | #15 105 | b1011 ! 106 | b1011 ( 107 | 1# 108 | b0 $ 109 | b0 ' 110 | 0% 111 | #16 112 | 0# 113 | #17 114 | 1# 115 | #18 116 | 0# 117 | #19 118 | b0 ! 119 | b0 ( 120 | 1# 121 | b1101 $ 122 | b1101 ' 123 | 1% 124 | #20 125 | 0# 126 | #21 127 | b1101 ! 128 | b1101 ( 129 | 1# 130 | b0 $ 131 | b0 ' 132 | 0% 133 | -------------------------------------------------------------------------------- /reg_init/Makefile: -------------------------------------------------------------------------------- 1 | NAME=reg_init 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /reg_init/reg_init.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io out_data[0] 99 3 | set_io out_data[1] 98 4 | set_io out_data[2] 97 5 | set_io out_data[3] 96 6 | set_io green 95 7 | -------------------------------------------------------------------------------- /reg_init/reg_init.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 22; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | 14 | module reg_init(input wire clk, output wire[3:0]out_data, output reg green = 1); 15 | parameter INI = 4'b0011; 16 | parameter BITS = 25; 17 | reg sel = 0; 18 | 19 | wire clk_prescaled; 20 | 21 | wire [3:0] din; 22 | reg [3:0] dout; 23 | 24 | //Register 25 | always @(posedge clk_prescaled ) begin 26 | dout <= din; 27 | end 28 | 29 | //Connect register with data out 30 | assign out_data = dout; 31 | 32 | //Multiplexer 33 | assign din = (sel == 0) ? INI : ~dout; 34 | 35 | //Init 36 | always @( posedge clk_prescaled ) begin 37 | sel <= 1; 38 | green = 0; 39 | end 40 | 41 | prescaler #(.BITS(BITS)) 42 | Pres1(.clk_in(clk), .clk_out(clk_prescaled)); 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /reg_init/reg_init_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/reg_init/reg_init_tb.v -------------------------------------------------------------------------------- /ring_counter/Makefile: -------------------------------------------------------------------------------- 1 | NAME=ring_counter 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /ring_counter/ring_counter.pcf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/ring_counter/ring_counter.pcf -------------------------------------------------------------------------------- /ring_counter/ring_counter.v: -------------------------------------------------------------------------------- 1 | module ring_counter(input clock, input reset, output reg [3:0] out); 2 | 3 | always @ ( posedge(clock) ) begin 4 | if(reset) 5 | out = 4'b0001; 6 | else 7 | begin 8 | out <= out<<1; 9 | out[0] <= out[3]; 10 | end 11 | end 12 | endmodule 13 | -------------------------------------------------------------------------------- /ring_counter/ring_counter_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module stimulus; 3 | // Inputs 4 | reg clock; 5 | reg reset; 6 | 7 | // Outputs 8 | wire[3:0] q; 9 | 10 | // Instantiate the Unit Under Test (UUT) 11 | ring_counter r1 ( 12 | .clock(clock), 13 | .reset(reset), 14 | .out(q) 15 | ); 16 | 17 | always #10 clock = ~clock; 18 | 19 | initial begin 20 | // Initialize Inputs 21 | clock = 0; 22 | reset = 0; 23 | 24 | #5 reset = 1; 25 | #20 reset = 0; 26 | #500 $finish; 27 | end 28 | 29 | initial begin 30 | $dumpfile("ring_counter_tb.vcd"); 31 | $dumpvars; 32 | $monitor($time, " clock=%1b,reset=%1b,q=%4b",clock,reset,q); 33 | end 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /rom_mem/.gitignore: -------------------------------------------------------------------------------- 1 | .pioenvs 2 | .clang_complete 3 | .gcc-flags.json 4 | -------------------------------------------------------------------------------- /rom_mem/.travis.yml: -------------------------------------------------------------------------------- 1 | # Continuous Integration (CI) is the practice, in software 2 | # engineering, of merging all developer working copies with a shared mainline 3 | # several times a day < http://docs.platformio.org/en/latest/ci/index.html > 4 | # 5 | # Documentation: 6 | # 7 | # * Travis CI Embedded Builds with PlatformIO 8 | # < https://docs.travis-ci.com/user/integration/platformio/ > 9 | # 10 | # * PlatformIO integration with Travis CI 11 | # < http://docs.platformio.org/en/latest/ci/travis.html > 12 | # 13 | # * User Guide for `platformio ci` command 14 | # < http://docs.platformio.org/en/latest/userguide/cmd_ci.html > 15 | # 16 | # 17 | # Please choice one of the following templates (proposed below) and uncomment 18 | # it (remove "# " before each line) or use own configuration according to the 19 | # Travis CI documentation (see above). 20 | # 21 | 22 | 23 | # 24 | # Template #1: General project. Test it using existing `platformio.ini`. 25 | # 26 | 27 | # language: python 28 | # python: 29 | # - "2.7" 30 | # 31 | # sudo: false 32 | # cache: 33 | # directories: 34 | # - "~/.platformio" 35 | # 36 | # install: 37 | # - pip install -U platformio 38 | # 39 | # script: 40 | # - platformio run 41 | 42 | 43 | # 44 | # Template #2: The project is intended to by used as a library with examples 45 | # 46 | 47 | # language: python 48 | # python: 49 | # - "2.7" 50 | # 51 | # sudo: false 52 | # cache: 53 | # directories: 54 | # - "~/.platformio" 55 | # 56 | # env: 57 | # - PLATFORMIO_CI_SRC=path/to/test/file.c 58 | # - PLATFORMIO_CI_SRC=examples/file.ino 59 | # - PLATFORMIO_CI_SRC=path/to/test/directory 60 | # 61 | # install: 62 | # - pip install -U platformio 63 | # 64 | # script: 65 | # - platformio ci --lib="." --board=TYPE_1 --board=TYPE_2 --board=TYPE_N 66 | -------------------------------------------------------------------------------- /rom_mem/lib/readme.txt: -------------------------------------------------------------------------------- 1 | 2 | This directory is intended for the project specific (private) libraries. 3 | PlatformIO will compile them to static libraries and link to executable file. 4 | 5 | The source code of each library should be placed in separate directory, like 6 | "lib/private_lib/[here are source files]". 7 | 8 | For example, see how can be organized `Foo` and `Bar` libraries: 9 | 10 | |--lib 11 | | |--Bar 12 | | | |--docs 13 | | | |--examples 14 | | | |--src 15 | | | |- Bar.c 16 | | | |- Bar.h 17 | | |--Foo 18 | | | |- Foo.c 19 | | | |- Foo.h 20 | | |- readme.txt --> THIS FILE 21 | |- platformio.ini 22 | |--src 23 | |- main.c 24 | 25 | Then in `src/main.c` you should use: 26 | 27 | #include 28 | #include 29 | 30 | // rest H/C/CPP code 31 | 32 | PlatformIO will find your libraries automatically, configure preprocessor's 33 | include paths and build them. 34 | 35 | See additional options for PlatformIO Library Dependency Finder `lib_*`: 36 | 37 | http://docs.platformio.org/en/latest/projectconf.html#lib-install 38 | 39 | -------------------------------------------------------------------------------- /rom_mem/platformio.ini: -------------------------------------------------------------------------------- 1 | # 2 | # Project Configuration File 3 | # 4 | # A detailed documentation with the EXAMPLES is located here: 5 | # http://docs.platformio.org/en/latest/projectconf.html 6 | # 7 | 8 | # A sign `#` at the beginning of the line indicates a comment 9 | # Comment lines are ignored. 10 | 11 | # Simple and base environment 12 | # [env:mybaseenv] 13 | # platform = %INSTALLED_PLATFORM_NAME_HERE% 14 | # framework = 15 | # board = 16 | # 17 | # Automatic targets - enable auto-uploading 18 | # targets = upload 19 | 20 | [env:icestick] 21 | platform = lattice_ice40 22 | framework = icestorm 23 | board = icestick 24 | -------------------------------------------------------------------------------- /rom_mem/src/Makefile: -------------------------------------------------------------------------------- 1 | NAME=sequencer 2 | DEPS = rom_mem.v dividerp1.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | $(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ *.out *.vcd 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /rom_mem/src/dividerp1.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Divisor de reloj 3 | //-- Señal de periodo igual al indicado 4 | //-- El ancho del pulso positivo es de 1 ciclo de reloj 5 | //-- 6 | //-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan) 7 | //----------------------------------------------------------------------------- 8 | //-- GPL license 9 | //----------------------------------------------------------------------------- 10 | 11 | //-- ENTRADAS: 12 | //-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick) 13 | // 14 | //-- SALIDAS: 15 | //-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada 16 | //-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA 17 | module dividerp1(input wire clk, 18 | output wire clk_out); 19 | 20 | //-- Valor por defecto de la velocidad en baudios 21 | parameter M = 12_000_000; //one sec 22 | 23 | //-- Numero de bits para almacenar el divisor de baudios 24 | localparam N = $clog2(M); 25 | 26 | //-- Registro para implementar el contador modulo M 27 | reg [N-1:0] divcounter = 0; 28 | 29 | //-- Contador módulo M 30 | always @(posedge clk) 31 | divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; 32 | 33 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 34 | assign clk_out = (divcounter == 0) ? 1 : 0; 35 | 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /rom_mem/src/rom_const_val.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | 3 | set_io leds[0] 99 4 | set_io leds[1] 98 5 | set_io leds[2] 97 6 | set_io leds[3] 96 7 | set_io leds[4] 95 8 | -------------------------------------------------------------------------------- /rom_mem/src/rom_const_val.v: -------------------------------------------------------------------------------- 1 | module rom_const_val( 2 | input wire clk, 3 | output wire [3:0] leds 4 | ); 5 | 6 | localparam ADDR = 5'h6; 7 | 8 | rom_32x4 ROM(.clk(clk), .address(ADDR), .data(leds)); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /rom_mem/src/rom_mem.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io data[0] 99 3 | set_io data[1] 98 4 | set_io data[2] 97 5 | set_io data[3] 96 6 | set_io data[4] 95 7 | -------------------------------------------------------------------------------- /rom_mem/src/rom_mem.v: -------------------------------------------------------------------------------- 1 | module rom_32x4( 2 | input wire clk, 3 | input wire [4:0] address, 4 | output reg [4:0] data 5 | ); 6 | 7 | //ROM registers 8 | reg [3:0] rom [0:31]; 9 | 10 | //ROM initialization 11 | initial begin 12 | rom[0] = 4'h1; 13 | rom[1] = 4'h2; 14 | rom[2] = 4'h4; 15 | rom[3] = 4'h8; 16 | rom[4] = 4'h1; 17 | rom[5] = 4'h8; 18 | rom[6] = 4'h4; 19 | rom[7] = 4'h2; 20 | rom[8] = 4'h1; 21 | rom[9] = 4'hF; 22 | rom[10] = 4'h0; 23 | rom[11] = 4'hF; 24 | rom[12] = 4'hC; 25 | rom[13] = 4'h3; 26 | rom[14] = 4'hC; 27 | rom[15] = 4'h3; 28 | rom[16] = 4'h1; 29 | rom[17] = 4'h2; 30 | rom[18] = 4'h4; 31 | rom[19] = 4'h3; 32 | rom[20] = 4'h1; 33 | rom[21] = 4'h2; 34 | rom[21] = 4'h5; 35 | rom[21] = 4'h2; 36 | rom[23] = 4'h1; 37 | rom[24] = 4'hF; 38 | rom[25] = 4'h1; 39 | rom[26] = 4'hF; 40 | rom[27] = 4'hC; 41 | rom[28] = 4'h3; 42 | rom[29] = 4'hC; 43 | rom[30] = 4'h2; 44 | rom[31] = 4'h3; 45 | end 46 | 47 | always @ (negedge clk ) begin 48 | data <= rom[address]; 49 | end 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /rom_mem/src/rom_mem_tb.v: -------------------------------------------------------------------------------- 1 | module rom_32x4_tb; 2 | 3 | reg clk = 0; 4 | reg [4:0] address = 5'b0; 5 | wire [3:0] data; 6 | 7 | always #1 clk = !clk; 8 | 9 | rom_32x4 uut(.clk(clk), .address(address), .data(data) ); 10 | 11 | initial begin 12 | $dumpfile("src/rom_mem_tb.vcd"); 13 | $dumpvars; 14 | 15 | $monitor($time, ": clk=%b address=%b data=%b", clk, address, data); 16 | 17 | #2 address = 1; 18 | #2 address = 2; 19 | #2 address = 3; 20 | #2 address = 4; 21 | #2 address = 5; 22 | #2 address = 6; 23 | #2 address = 7; 24 | #2 address = 8; 25 | 26 | #2 $finish; 27 | end 28 | 29 | endmodule 30 | -------------------------------------------------------------------------------- /rom_mem/src/rom_seq.v: -------------------------------------------------------------------------------- 1 | module rom_seq( 2 | input wire clk, 3 | input wire [4:0] address, 4 | output reg [3:0] leds 5 | ); 6 | 7 | //ROM memory 8 | reg [4:0] rom [0:31]; 9 | 10 | always @(negedge clk) begin 11 | leds <= rom[address]; 12 | end 13 | 14 | //-- ROM2: sequence 15 | initial begin 16 | rom[0] = 4'h1; 17 | rom[1] = 4'h2; 18 | rom[2] = 4'h4; 19 | rom[3] = 4'h8; 20 | rom[4] = 4'h1; 21 | rom[5] = 4'h8; 22 | rom[6] = 4'h4; 23 | rom[7] = 4'h2; 24 | rom[8] = 4'h1; 25 | rom[9] = 4'hF; 26 | rom[10] = 4'h0; 27 | rom[11] = 4'hF; 28 | rom[12] = 4'hC; 29 | rom[13] = 4'h3; 30 | rom[14] = 4'hC; 31 | rom[15] = 4'h3; 32 | end 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /rom_mem/src/sequencer.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/rom_mem/src/sequencer.bin -------------------------------------------------------------------------------- /rom_mem/src/sequencer.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io leds[0] 99 3 | set_io leds[1] 98 4 | set_io leds[2] 97 5 | set_io leds[3] 96 6 | set_io leds[4] 95 7 | -------------------------------------------------------------------------------- /rom_mem/src/sequencer.v: -------------------------------------------------------------------------------- 1 | module sequencer( 2 | input wire clk, 3 | output wire [4:0] leds 4 | ); 5 | 6 | parameter DELAY = 3_000_000; //500ms as the clock runs at 12mhz 7 | 8 | reg [4:0] address; 9 | reg reset = 0; 10 | wire clk_delay; 11 | 12 | rom_32x4 ROM(.clk(clk_delay), .address(address), .data(leds)); 13 | 14 | //Counter 15 | always @ (posedge clk) begin 16 | if(reset == 0) begin 17 | address <= 0; 18 | end else if (clk_delay) begin 19 | address <= address + 1; 20 | end 21 | end 22 | 23 | //Timer 24 | dividerp1 #(.M(DELAY)) TIMER(.clk(clk), .clk_out(clk_delay)); 25 | 26 | always @ (negedge clk) begin 27 | reset <= 1; 28 | end 29 | 30 | endmodule 31 | -------------------------------------------------------------------------------- /rom_memory/Makefile: -------------------------------------------------------------------------------- 1 | NAME=romfile 2 | DEPS=rom_leds.v dividerp1.v rom_seq.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /rom_memory/dividerp1.v: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Divisor de reloj 3 | //-- Señal de periodo igual al indicado 4 | //-- El ancho del pulso positivo es de 1 ciclo de reloj 5 | //-- 6 | //-- (c) BQ. September 2015. written by Juan Gonzalez (obijuan) 7 | //----------------------------------------------------------------------------- 8 | //-- GPL license 9 | //----------------------------------------------------------------------------- 10 | `include "divider.vh" 11 | 12 | //-- ENTRADAS: 13 | //-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick) 14 | // 15 | //-- SALIDAS: 16 | //-- - clk_out. Señal de salida para lograr la velocidad en baudios indicada 17 | //-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA 18 | module dividerp1(input wire clk, 19 | output wire clk_out); 20 | 21 | //-- Valor por defecto de la velocidad en baudios 22 | parameter M = `T_100ms; 23 | 24 | //-- Numero de bits para almacenar el divisor de baudios 25 | localparam N = $clog2(M); 26 | 27 | //-- Registro para implementar el contador modulo M 28 | reg [N-1:0] divcounter = 0; 29 | 30 | //-- Contador módulo M 31 | always @(posedge clk) 32 | divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; 33 | 34 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 35 | assign clk_out = (divcounter == 0) ? 1 : 0; 36 | 37 | 38 | endmodule -------------------------------------------------------------------------------- /rom_memory/rom1.list: -------------------------------------------------------------------------------- 1 | //-- Fichero rom1.list 2 | //-- Cada linea se corresponde con una posicion de memoria 3 | //-- Se pueden poner comentarios 4 | //-- ROM1: contiene los numeros del 0 al 15 (en hexadecimal) 5 | 0 //-- Posicion 0 6 | 1 //-- Posicion 1 7 | 2 8 | 3 9 | 4 10 | 5 11 | 6 12 | 7 13 | 8 14 | 9 15 | A 16 | B 17 | C 18 | D 19 | E 20 | F //-- Posicion 15 -------------------------------------------------------------------------------- /rom_memory/rom32x4.pcf: -------------------------------------------------------------------------------- 1 | set_io leds[0] 99 2 | set_io leds[1] 98 3 | set_io leds[2] 97 4 | set_io leds[3] 96 5 | set_io clk 21 -------------------------------------------------------------------------------- /rom_memory/rom32x4.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module rom32x4 (input clk, 4 | input wire [4:0] addr, 5 | output reg [3:0]data); 6 | 7 | reg [3:0] rom [0:31]; 8 | 9 | always @(negedge clk) begin 10 | data <= rom[addr]; 11 | end 12 | 13 | initial begin 14 | rom[0] = 4'h0; 15 | rom[1] = 4'h1; 16 | rom[2] = 4'h2; 17 | rom[3] = 4'h3; 18 | rom[4] = 4'h4; 19 | rom[5] = 4'h5; 20 | rom[6] = 4'h6; 21 | rom[7] = 4'h7; 22 | end 23 | 24 | endmodule -------------------------------------------------------------------------------- /rom_memory/rom_file.v: -------------------------------------------------------------------------------- 1 | //-- Fichero romleds2.v 2 | `default_nettype none 3 | 4 | `include "divider.vh" 5 | 6 | module romleds2 (input wire clk, 7 | output wire [3:0] leds); 8 | 9 | //-- Parametros: 10 | //- Tiempo de envio 11 | parameter DELAY = `T_500ms; //`T_1s; 12 | 13 | //-- Fichero para cargar la rom 14 | parameter ROMFILE = "rom1.list"; //-- rom2.list 15 | 16 | reg [3:0] addr; 17 | reg rstn = 0; 18 | wire clk_delay; 19 | 20 | //-- Instanciar la memoria rom 21 | romfile16x4 #(ROMFILE) 22 | ROM ( 23 | .clk(clk), 24 | .addr(addr), 25 | .data(leds) 26 | ); 27 | 28 | //-- Contador 29 | always @(negedge clk) 30 | if (rstn == 0) 31 | addr <= 0; 32 | else if (clk_delay) 33 | addr <= addr + 1; 34 | 35 | //--------------------------- 36 | //-- Temporizador 37 | //--------------------------- 38 | dividerp1 #(.M(DELAY)) 39 | DIV0 ( .clk(clk), 40 | .clk_out(clk_delay) 41 | ); 42 | 43 | //-- Inicializador 44 | always @(negedge clk) 45 | rstn <= 1; 46 | 47 | endmodule -------------------------------------------------------------------------------- /rom_memory/rom_leds.v: -------------------------------------------------------------------------------- 1 | //-- Fichero: romleds.v 2 | `default_nettype none 3 | 4 | `include "divider.vh" 5 | 6 | module romleds (input wire clk, 7 | output wire [3:0] leds); 8 | 9 | //- Tiempo de envio 10 | parameter DELAY = `T_500ms; //`T_1s; 11 | 12 | reg [3:0] addr; 13 | reg rstn = 0; 14 | wire clk_delay; 15 | 16 | //-- Instanciar la memoria rom 17 | rom16x4 18 | ROM ( 19 | .clk(clk), 20 | .addr(addr), 21 | .data(leds) 22 | ); 23 | 24 | //-- Contador 25 | always @(negedge clk) 26 | if (rstn == 0) 27 | addr <= 0; 28 | else if (clk_delay) 29 | addr <= addr + 1; 30 | 31 | //--------------------------- 32 | //-- Temporizador 33 | //--------------------------- 34 | dividerp1 #(.M(DELAY)) 35 | DIV0 ( .clk(clk), 36 | .clk_out(clk_delay) 37 | ); 38 | 39 | //-- Inicializador 40 | always @(negedge clk) 41 | rstn <= 1; 42 | 43 | endmodule -------------------------------------------------------------------------------- /rom_memory/rom_seq.pcf: -------------------------------------------------------------------------------- 1 | set_io leds[0] 99 2 | set_io leds[1] 98 3 | set_io leds[2] 97 4 | set_io leds[3] 96 5 | set_io clk 21 -------------------------------------------------------------------------------- /rom_memory/rom_seq.v: -------------------------------------------------------------------------------- 1 | //-- Fichero: rom16x4.v 2 | module rom16x4 (input clk, 3 | input wire [3:0] addr, 4 | output reg [3:0] data); 5 | 6 | //-- Memoria 7 | reg [3:0] rom [0:31]; 8 | 9 | always @(negedge clk) begin 10 | data <= rom[addr]; 11 | end 12 | 13 | 14 | //-- ROM2: Secuencia 15 | initial begin 16 | rom[0] = 4'h1; 17 | rom[1] = 4'h2; 18 | rom[2] = 4'h4; 19 | rom[3] = 4'h8; 20 | rom[4] = 4'h1; 21 | rom[5] = 4'h8; 22 | rom[6] = 4'h4; 23 | rom[7] = 4'h2; 24 | rom[8] = 4'h1; 25 | rom[9] = 4'hF; 26 | rom[10] = 4'h0; 27 | rom[11] = 4'hF; 28 | rom[12] = 4'hC; 29 | rom[13] = 4'h3; 30 | rom[14] = 4'hC; 31 | rom[15] = 4'h3; 32 | end 33 | 34 | endmodule -------------------------------------------------------------------------------- /rom_memory/romfile.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/rom_memory/romfile.bin -------------------------------------------------------------------------------- /rom_memory/romfile.pcf: -------------------------------------------------------------------------------- 1 | set_io leds[0] 99 2 | set_io leds[1] 98 3 | set_io leds[2] 97 4 | set_io leds[3] 96 5 | set_io clk 21 -------------------------------------------------------------------------------- /rom_memory/romfile.v: -------------------------------------------------------------------------------- 1 | //-- Fichero romfile16x4 2 | module romfile16x4 (input clk, 3 | input wire [3:0] addr, 4 | output reg [3:0] data); 5 | 6 | //-- Parametro: Nombre del fichero con el contenido de la ROM 7 | parameter ROMFILE = "rom1.list"; 8 | 9 | //-- Memoria 10 | reg [3:0] rom [0:31]; 11 | 12 | //-- Lectura de la memoria 13 | always @(negedge clk) begin 14 | data <= rom[addr]; 15 | end 16 | 17 | //-- Cargar en la memoria el fichero ROMFILE 18 | //-- Los valores deben estan dados en hexadecimal 19 | initial begin 20 | $readmemh(ROMFILE, rom); 21 | end 22 | 23 | endmodule -------------------------------------------------------------------------------- /rom_memory/romhw.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module romhw(input wire clk, 4 | output wire [3:0] leds); 5 | 6 | localparam ADDR = 4'h5; 7 | 8 | rom32x4 ROM(.clk(clk), .addr(ADDR), .data(leds)); 9 | 10 | endmodule -------------------------------------------------------------------------------- /second_counter/Makefile: -------------------------------------------------------------------------------- 1 | NAME=second_counter 2 | DEPS = divM.v four_bit_counter.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | #-- Limpiar todo 62 | clean: 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /second_counter/divM.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out, output reg [3:0] out = 0); 2 | parameter BITS = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(BITS); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | //-- Modulus 3 counter 13 | always @(posedge clk_in) begin 14 | divcounter <= (divcounter == BITS - 1) ? 0 : divcounter + 1; 15 | end 16 | 17 | //Take out MSB 18 | assign clk_out = divcounter[N-1]; 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /second_counter/four_bit_counter.v: -------------------------------------------------------------------------------- 1 | module four_bit_counter(input wire clk_in, output wire [3:0] counter); 2 | 3 | reg [3:0] count; 4 | 5 | always @ ( posedge clk_in ) begin 6 | count <= count + 1; 7 | end 8 | 9 | assign counter = count; 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /second_counter/second_counter.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/second_counter/second_counter.bin -------------------------------------------------------------------------------- /second_counter/second_counter.pcf: -------------------------------------------------------------------------------- 1 | set_io data[0] 99 2 | set_io data[1] 98 3 | set_io data[2] 97 4 | set_io data[3] 96 5 | set_io clk_in 21 6 | -------------------------------------------------------------------------------- /second_counter/second_counter.v: -------------------------------------------------------------------------------- 1 | module seccount(input wire clk_in, output wire [3:0] data); 2 | 3 | wire clk_1HZ; 4 | wire [3:0] out_data; 5 | 6 | divM divisor(.clk_in(clk_in), .clk_out(clk_1HZ)); 7 | 8 | four_bit_counter count(.clk_in(clk_1HZ), .counter(out_data)); 9 | 10 | assign data = out_data; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /sequential_circuits/Makefile: -------------------------------------------------------------------------------- 1 | NAME=d_ff 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /sequential_circuits/d_ff.v: -------------------------------------------------------------------------------- 1 | module d_ff( 2 | input wire clk, 3 | input wire d, 4 | input reset, 5 | output reg out 6 | ); 7 | 8 | always @ ( negedge(reset) or posedge(clk) ) begin 9 | begin 10 | if(!reset) 11 | out = 0; 12 | else 13 | out = d; 14 | end 15 | end 16 | endmodule 17 | -------------------------------------------------------------------------------- /sequential_circuits/d_ff_tb.v: -------------------------------------------------------------------------------- 1 | module d_ff_tb; 2 | reg clk; 3 | reg d; 4 | reg reset; 5 | wire out; 6 | 7 | d_ff uut(.clk(clk), .d(d), .reset(reset), .out(out)); 8 | 9 | integer i; 10 | 11 | initial begin 12 | $dumpfile("d_ff_tb.vcd"); 13 | $dumpvars; 14 | 15 | d = 0; reset=1; 16 | 17 | #8 d=1; 18 | #10 d=0; 19 | #10 d=0; reset=0; 20 | #1 d=0; reset=1; 21 | #10 d=1; 22 | #10 d=0; 23 | #10 d=1; reset=1; 24 | #10 d=0; 25 | #10 d=0; 26 | #10 d=1; 27 | #10 d=1; reset=0; 28 | #40; 29 | end 30 | 31 | initial begin 32 | clk = 0; 33 | for (i=0; i<=10; i= i+1) 34 | #10 clk = ~clk; 35 | end 36 | 37 | initial begin 38 | $monitor($time, ": clk=%d d=%d out=%d\n", clk, d, out); 39 | end 40 | endmodule 41 | -------------------------------------------------------------------------------- /seven-seg/Makefile: -------------------------------------------------------------------------------- 1 | NAME=seven 2 | DEPS = 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /seven-seg/digits.vh: -------------------------------------------------------------------------------- 1 | //7 segments digits 2 | 3 | `define ZERO 8'b10001000 4 | `define ONE 8'b11111001 5 | `define TWO 8'b01001100 6 | `define THREE 8'b01101000 7 | `define FOUR 8'b10011001 8 | `define FIVE 8'b00101010 9 | `define SIX 8'b00001010 10 | `define SEVEN 8'b11111000 11 | `define EIGHT 8'b00001000 12 | `define NINE 8'b00101000 13 | -------------------------------------------------------------------------------- /seven-seg/seven.v: -------------------------------------------------------------------------------- 1 | // Add 7 segment digits 2 | `include "digits.vh" 3 | 4 | module seven( 5 | input wire clk, 6 | output wire [7:0] SevenSegment, 7 | output wire [2:0] SevenSegmentEnable 8 | ); 9 | 10 | //#################################################################### 11 | //Iterates over every 7segment to activate them sequentially 12 | reg [2:0] iter; 13 | 14 | initial begin 15 | iter = 3'b001; 16 | end 17 | 18 | always @ ( posedge clk ) begin 19 | iter <= {iter[0], iter[2:1]}; 20 | end 21 | 22 | assign SevenSegmentEnable = iter; 23 | //#################################################################### 24 | 25 | //Assign a different number every time we change the "ON" led. 26 | reg [7:0] number; 27 | initial begin 28 | number = 0; 29 | end 30 | 31 | always @ ( posedge clk ) begin 32 | case (iter) 33 | 3'b001: number <= `ONE; 34 | 3'b010: number <= `TWO; 35 | 3'b100: number <= `THREE; 36 | endcase 37 | end 38 | 39 | assign SevenSegment = number; 40 | 41 | endmodule 42 | -------------------------------------------------------------------------------- /seven-seg/seven_seg_display.v: -------------------------------------------------------------------------------- 1 | // Add 7 segment digits 2 | `include "digits.vh" 3 | 4 | module seven_seg_display( 5 | input wire clk, 6 | input wire [9:0] number, 7 | output wire [7:0] SevenSegment, 8 | output wire [2:0] SevenSegmentEnable 9 | ); 10 | 11 | //#################################################################### 12 | //Iterates over every 7segment to activate them sequentially 13 | reg [2:0] iter; 14 | 15 | initial begin 16 | iter = 3'b001; 17 | end 18 | 19 | always @ ( posedge clk ) begin 20 | iter <= {iter[0], iter[2:1]}; 21 | end 22 | 23 | assign SevenSegmentEnable = iter; 24 | //#################################################################### 25 | 26 | //Assign a different number every time we change the "ON" led. 27 | reg [7:0] out; 28 | initial begin 29 | out = 0; 30 | end 31 | 32 | reg cent; 33 | reg dec; 34 | reg uni; 35 | 36 | reg n = 0; 37 | 38 | always @ ( posedge clk ) begin 39 | cent = number / 100; 40 | dec = (number - (cent*100)) / 10; 41 | uni = number - (cent + dec); 42 | 43 | case (iter) 44 | 3'b001: n = cent; 45 | 3'b010: n = dec; 46 | 3'b100: n = uni; 47 | endcase 48 | end 49 | 50 | always @ ( posedge clk ) begin 51 | case (n) 52 | 0: out = `ZERO; 53 | 1: out = `ONE; 54 | 2: out = `TWO; 55 | 3: out = `THREE; 56 | 4: out = `FOUR; 57 | 5: out = `FIVE; 58 | 6: out = `SIX; 59 | 7: out = `SEVEN; 60 | 8: out = `EIGHT; 61 | 9: out = `NINE; 62 | endcase 63 | end 64 | 65 | assign SevenSegment = out; 66 | endmodule 67 | -------------------------------------------------------------------------------- /seven-seg/seven_tb.v: -------------------------------------------------------------------------------- 1 | module seven_seg_display_tb; 2 | reg clk; 3 | wire [7:0] SevenSegment; 4 | wire [2:0] SevenSegmentEnable; 5 | reg [9:0] number; 6 | 7 | seven_seg_display uut( 8 | .clk(clk), 9 | .number(number), 10 | .SevenSegment(SevenSegment), 11 | .SevenSegmentEnable(SevenSegmentEnable) 12 | ); 13 | 14 | always #1 clk = !clk; 15 | 16 | initial begin 17 | clk = 0; 18 | 19 | $dumpfile("seven_tb.vcd"); 20 | $dumpvars; 21 | 22 | $monitor($time, ": clk=%b 7seg=%b 7segEna=%b, num=%d", clk, SevenSegment, SevenSegmentEnable, number); 23 | 24 | #10 number = 345; 25 | #10 number = 995; 26 | #10 number = 476; 27 | 28 | #1 $finish; 29 | end 30 | 31 | endmodule 32 | -------------------------------------------------------------------------------- /seven-seg/test.v: -------------------------------------------------------------------------------- 1 | module test_tb; 2 | reg [9:0] r; 3 | 4 | reg [9:0] number = 345; 5 | reg [4:0] cent; 6 | reg [4:0] dec; 7 | reg [4:0] uni; 8 | 9 | initial begin 10 | r = 0; 11 | end 12 | 13 | initial begin 14 | $dumpfile("test_tv.vcd"); 15 | $dumpvars; 16 | 17 | $monitor($time, ": r=%d cent=%d dec=%d uni=%d", r, cent, dec, uni); 18 | 19 | #1 20 | cent = number / 100; 21 | dec = (number - (cent*100)) / 10; 22 | uni = number - ((cent*100) + (dec*10)); 23 | end 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /shift_register/Makefile: -------------------------------------------------------------------------------- 1 | NAME=shift_register 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /shift_register/shift_register.v: -------------------------------------------------------------------------------- 1 | module shift_register 2 | #(parameter BITS = 8) 3 | ( 4 | input wire clk, reset, s_in, 5 | output wire s_out 6 | ); 7 | 8 | reg [BITS-1:0] r_reg; 9 | wire [BITS-1:0] r_next; 10 | 11 | always @ ( posedge clk, negedge reset ) begin 12 | if (~reset) 13 | r_reg <= 0; 14 | else 15 | r_reg <= r_next; 16 | end 17 | 18 | assign r_next = {s_in, r_reg[BITS-1:1]}; 19 | assign s_out = r_reg[0]; 20 | endmodule 21 | -------------------------------------------------------------------------------- /shift_register/shift_register_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | module stimulus; 3 | // Inputs 4 | reg clk ; 5 | reg reset; 6 | // Outputs 7 | reg s_in; 8 | wire s_out; 9 | // Instantiate the Unit Under Test (UUT) 10 | shift_register #(2) s1 ( 11 | .clk(clk), 12 | .reset(reset), 13 | .s_in(s_in), 14 | .s_out(s_out) 15 | ); 16 | 17 | integer i, j; 18 | initial 19 | begin 20 | 21 | clk = 0; 22 | for(i =0; i<=40; i=i+1) 23 | begin 24 | #10 clk = ~clk; 25 | end 26 | end 27 | 28 | initial 29 | begin 30 | 31 | $dumpfile("shift_register_tb.vcd"); 32 | $dumpvars(0,stimulus); 33 | 34 | s_in = 0; reset =1; 35 | #2 s_in = 0 ; reset = 0; 36 | #2 reset =1; 37 | for(i =0; i<=10; i=i+1) 38 | begin 39 | #20 s_in = ~s_in; 40 | end 41 | #20 s_in =1; 42 | #20 s_in = 1; 43 | #20 s_in =0; 44 | #20 s_in =1; 45 | #20 s_in = 1; 46 | #20 s_in =0; 47 | #20 s_in =1; 48 | #20 s_in = 1; 49 | #20 s_in =0; 50 | end 51 | 52 | initial begin 53 | $monitor("clk=%d s_in=%d,s_out=%d", clk, s_in, s_out); 54 | end 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /shift_register/shift_register_tb.vcd: -------------------------------------------------------------------------------- 1 | $date 2 | Sun May 8 15:34:28 2016 3 | $end 4 | $version 5 | Icarus Verilog 6 | $end 7 | $timescale 8 | 1ps 9 | $end 10 | $scope module stimulus $end 11 | $var wire 1 ! s_out $end 12 | $var reg 1 " clk $end 13 | $var reg 1 # reset $end 14 | $var reg 1 $ s_in $end 15 | $var integer 32 % i [31:0] $end 16 | $scope module s1 $end 17 | $var wire 1 " clk $end 18 | $var wire 1 # reset $end 19 | $var wire 1 $ s_in $end 20 | $var wire 1 ! s_out $end 21 | $var wire 2 & r_next [1:0] $end 22 | $var reg 2 ' r_reg [1:0] $end 23 | $upscope $end 24 | $upscope $end 25 | $enddefinitions $end 26 | #0 27 | $dumpvars 28 | bx ' 29 | b0x & 30 | b0 % 31 | 0$ 32 | 1# 33 | 0" 34 | x! 35 | $end 36 | #2000 37 | b0 & 38 | 0! 39 | b0 ' 40 | 0# 41 | #4000 42 | 1# 43 | #10000 44 | b1 % 45 | 1" 46 | #20000 47 | b10 % 48 | 0" 49 | #24000 50 | b11 % 51 | b10 & 52 | 1$ 53 | #30000 54 | b11 & 55 | b10 ' 56 | b100 % 57 | 1" 58 | #40000 59 | b101 % 60 | 0" 61 | #44000 62 | b110 % 63 | b1 & 64 | 0$ 65 | #50000 66 | b0 & 67 | 1! 68 | b1 ' 69 | b111 % 70 | 1" 71 | #60000 72 | b1000 % 73 | 0" 74 | #64000 75 | b1001 % 76 | b10 & 77 | 1$ 78 | #70000 79 | b11 & 80 | 0! 81 | b10 ' 82 | b1010 % 83 | 1" 84 | #80000 85 | b1011 % 86 | 0" 87 | #84000 88 | b1100 % 89 | b1 & 90 | 0$ 91 | #90000 92 | b0 & 93 | 1! 94 | b1 ' 95 | b1101 % 96 | 1" 97 | #100000 98 | b1110 % 99 | 0" 100 | #104000 101 | b10 & 102 | 1$ 103 | #110000 104 | b11 & 105 | 0! 106 | b10 ' 107 | b1111 % 108 | 1" 109 | #120000 110 | b10000 % 111 | 0" 112 | #130000 113 | 1! 114 | b11 ' 115 | b10001 % 116 | 1" 117 | #140000 118 | b10010 % 119 | 0" 120 | #144000 121 | b1 & 122 | 0$ 123 | #150000 124 | b0 & 125 | b1 ' 126 | b10011 % 127 | 1" 128 | #160000 129 | b10100 % 130 | 0" 131 | #164000 132 | b10 & 133 | 1$ 134 | #170000 135 | b11 & 136 | 0! 137 | b10 ' 138 | b10101 % 139 | 1" 140 | #180000 141 | b10110 % 142 | 0" 143 | #190000 144 | 1! 145 | b11 ' 146 | b10111 % 147 | 1" 148 | #200000 149 | b11000 % 150 | 0" 151 | #204000 152 | b1 & 153 | 0$ 154 | #210000 155 | b0 & 156 | b1 ' 157 | b11001 % 158 | 1" 159 | #220000 160 | b11010 % 161 | 0" 162 | #224000 163 | b10 & 164 | 1$ 165 | #230000 166 | b11 & 167 | 0! 168 | b10 ' 169 | b11011 % 170 | 1" 171 | #240000 172 | b11100 % 173 | 0" 174 | #250000 175 | 1! 176 | b11 ' 177 | b11101 % 178 | 1" 179 | #260000 180 | b11110 % 181 | 0" 182 | #264000 183 | b1 & 184 | 0$ 185 | #270000 186 | b0 & 187 | b1 ' 188 | b11111 % 189 | 1" 190 | #280000 191 | b100000 % 192 | 0" 193 | #290000 194 | 0! 195 | b0 ' 196 | b100001 % 197 | 1" 198 | #300000 199 | b100010 % 200 | 0" 201 | #310000 202 | b100011 % 203 | 1" 204 | #320000 205 | b100100 % 206 | 0" 207 | #330000 208 | b100101 % 209 | 1" 210 | #340000 211 | b100110 % 212 | 0" 213 | #350000 214 | b100111 % 215 | 1" 216 | #360000 217 | b101000 % 218 | 0" 219 | #370000 220 | b101001 % 221 | 1" 222 | -------------------------------------------------------------------------------- /shifter/Makefile: -------------------------------------------------------------------------------- 1 | NAME=shifter 2 | 3 | #------------------------------------------------------- 4 | #-- Objetivo por defecto: hacer simulacion y sintesis 5 | #------------------------------------------------------- 6 | all: sint 7 | 8 | #---------------------------------------------- 9 | #-- make sim 10 | #---------------------------------------------- 11 | #-- Objetivo para hacer la simulacion del 12 | #-- banco de pruebas 13 | #---------------------------------------------- 14 | sim: $(NAME)_tb.vcd 15 | 16 | #----------------------------------------------- 17 | #- make sint 18 | #----------------------------------------------- 19 | #- Objetivo para realizar la sintetis completa 20 | #- y dejar el diseno listo para su grabacion en 21 | #- la FPGA 22 | #----------------------------------------------- 23 | sint: $(NAME).bin 24 | 25 | #------------------------------- 26 | #-- Compilacion y simulacion 27 | #------------------------------- 28 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 29 | 30 | #-- Compilar 31 | iverilog -o $(NAME).out $(NAME).v $(NAME)_tb.v 32 | 33 | #-- Simular 34 | ./$(NAME).out 35 | 36 | #-- Crear VCD 37 | vvp $(NAME).out 38 | 39 | #-- Ver visualmente la simulacion con gtkwave 40 | gtkwave $(NAME)_tb.vcd 41 | 42 | #------------------------------ 43 | #-- Sintesis completa 44 | #------------------------------ 45 | $(NAME).bin: $(NAME).v $(NAME).pcf 46 | 47 | #-- Sintesis 48 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v 49 | 50 | #-- Place & route 51 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 52 | 53 | #-- Generar binario final, listo para descargar en fgpa 54 | icepack $(NAME).txt $(NAME).bin 55 | 56 | #-- Cargar en FPGA 57 | load: 58 | iceprog $(NAME).bin 59 | 60 | #-- Limpiar todo 61 | clean: 62 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 63 | 64 | .PHONY: all clean 65 | -------------------------------------------------------------------------------- /shifter/shifter.pcf: -------------------------------------------------------------------------------- 1 | set_io data[0] 99 2 | set_io data[1] 98 3 | set_io data[2] 97 4 | set_io data[3] 96 5 | set_io clk 21 6 | -------------------------------------------------------------------------------- /shifter/shifter.v: -------------------------------------------------------------------------------- 1 | module prescaler(input wire clk_in, output wire clk_out); 2 | parameter BITS = 28; 3 | 4 | reg [BITS-1:0] count = 0; 5 | 6 | assign clk_out = count[BITS-1]; 7 | 8 | always @ ( posedge(clk_in) ) begin 9 | count <= count + 1; 10 | end 11 | endmodule 12 | 13 | module shifter(input wire clk, output reg [3:0] data); 14 | parameter BITS = 22; 15 | parameter INI = 1; 16 | 17 | wire clk_prescaled; 18 | wire ser_in; 19 | 20 | reg load_shift = 0; 21 | 22 | prescaler #(.BITS(BITS)) 23 | Pres1(.clk_in(clk), .clk_out(clk_prescaled)); 24 | 25 | //Init 26 | always @(posedge(clk_prescaled)) begin 27 | load_shift <= 1; 28 | end 29 | 30 | //Shifter 31 | always @ ( posedge(clk_prescaled) ) begin 32 | if(load_shift == 0) 33 | data <= INI; //As they're 4 bits, it'll pass 0001 34 | else 35 | data <= {data[2:0], ser_in}; 36 | end 37 | 38 | assign ser_in = data[3]; 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /shifter/shifter_tb.v: -------------------------------------------------------------------------------- 1 | module shifter_tb; 2 | reg clk = 0; 3 | wire [3:0] data; 4 | 5 | always #1 clk = ~clk; 6 | 7 | shifter #(.BITS(1), .INI(4'b1001)) 8 | Shifter(.clk(clk), .data(data)); 9 | 10 | initial begin 11 | $dumpfile("shifter_tb.vcd"); 12 | $dumpvars(0, shifter_tb); 13 | $monitor($time, ": %b", data); 14 | 15 | #100 $finish; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /sync_baud_tx/Makefile: -------------------------------------------------------------------------------- 1 | NAME=sync_baud_tx 2 | DEPS = divM.v baud_tx.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /sync_baud_tx/baud_tx.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module baud_tx( 4 | input wire clk, 5 | input wire load, 6 | output wire tx 7 | ); 8 | 9 | //115200 baud 10 | parameter BAUD = 104; 11 | 12 | wire clk_baud; 13 | 14 | //Generate a pulse to the specified baud frequency 15 | divM #(BAUD) 16 | BAUD0( 17 | .clk_in(clk), 18 | .clk_out(clk_baud) 19 | ); 20 | 21 | //Holds the 10 bit value that we'll pass 22 | reg [9:0] shifter; 23 | 24 | always @ (posedge clk_baud) begin 25 | if (load == 0) 26 | //Don't transmit. Set value to send (shifter) to "K" 01001011 + 01 27 | shifter <= {"K",2'b01}; 28 | else 29 | //Transmission is activated. Shift to the left (leftmost bit to the first and shift the other 9 to left) 30 | shifter <= {shifter[0], shifter[9:1]}; 31 | end 32 | 33 | assign tx = (load) ? shifter[0] : 1; 34 | 35 | endmodule 36 | -------------------------------------------------------------------------------- /sync_baud_tx/divM.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /sync_baud_tx/divM0.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /sync_baud_tx/sync_baud_tx.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io load 3 3 | set_io tx 8 4 | -------------------------------------------------------------------------------- /sync_baud_tx/sync_baud_tx.v: -------------------------------------------------------------------------------- 1 | //-- Fichero: txtest.v 2 | `default_nettype none 3 | 4 | //--- Modulo que envia un caracter cuando load esta a 1 5 | //--- La salida tx ESTA REGISTRADA 6 | module txtest(input wire clk, //-- Reloj del sistema (12MHz en ICEstick) 7 | input wire load, //-- Señal de cargar / desplazamiento 8 | output reg tx //-- Salida de datos serie (hacia el PC) 9 | ); 10 | 11 | //-- Parametro: velocidad de transmision 12 | //-- Pruebas del caso peor: a 300 baudios 13 | parameter BAUD = 40000; 14 | 15 | //-- Registro de 10 bits para almacenar la trama a enviar: 16 | //-- 1 bit start + 8 bits datos + 1 bit stop 17 | reg [9:0] shifter; 18 | 19 | //-- Señal de load registrada 20 | reg load_r; 21 | 22 | //-- Reloj para la transmision 23 | wire clk_baud; 24 | 25 | //-- Registrar la entrada load 26 | //-- (para cumplir con las reglas de diseño sincrono) 27 | always @(posedge clk) 28 | load_r <= load; 29 | 30 | //-- Registro de desplazamiento, con carga paralela 31 | //-- Cuando load_r es 0, se carga la trama 32 | //-- Cuando load_r es 1 y el reloj de baudios esta a 1 se desplaza hacia 33 | //-- la derecha, enviando el siguiente bit 34 | //-- Se introducen '1's por la izquierda 35 | always @(posedge clk) 36 | //-- Modo carga 37 | if (load_r == 0) 38 | shifter <= {"K",2'b01}; 39 | 40 | //-- Modo desplazamiento 41 | else if (load_r == 1 && clk_baud == 1) 42 | shifter <= {shifter[0], shifter[9:1]}; 43 | 44 | //-- Sacar por tx el bit menos significativo del registros de desplazamiento 45 | //-- Cuando estamos en modo carga (load_r == 0), se saca siempre un 1 para 46 | //-- que la linea este siempre a un estado de reposo. De esta forma en el 47 | //-- inicio tx esta en reposo, aunque el valor del registro de desplazamiento 48 | //-- sea desconocido 49 | //-- ES UNA SALIDA REGISTRADA, puesto que tx se conecta a un bus sincrono 50 | //-- y hay que evitar que salgan pulsos espureos (glitches) 51 | always @(posedge clk) 52 | tx <= (load_r) ? shifter[0] : 1; 53 | 54 | //-- Divisor para obtener el reloj de transmision 55 | divider #(BAUD) 56 | BAUD0 ( 57 | .clk_in(clk), 58 | .clk_out(clk_baud) 59 | ); 60 | 61 | endmodule 62 | -------------------------------------------------------------------------------- /sync_baud_tx/sync_baud_tx_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/sync_baud_tx/sync_baud_tx_tb.v -------------------------------------------------------------------------------- /sync_rules/Makefile: -------------------------------------------------------------------------------- 1 | NAME=txtest3 2 | DEPS=baudgen.v divider.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: clean sint load 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: clean $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: clean $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | clean: 62 | #-- Clean everything 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /sync_rules/baudgen.v: -------------------------------------------------------------------------------- 1 | //-- Fichero baudgen.v 2 | `include "baudgen.vh" 3 | 4 | //-- ENTRADAS: 5 | //-- -clk: Senal de reloj del sistema (12 MHZ en la iceStick) 6 | //-- -clk_ena: Habilitacion. 7 | //-- 1. funcionamiento normal. Emitiendo pulsos 8 | //-- 0: Inicializado y parado. No se emiten pulsos 9 | // 10 | //-- SALIDAS: 11 | //-- - clk_out. Señal de salida que marca el tiempo entre bits 12 | //-- Anchura de 1 periodo de clk. SALIDA NO REGISTRADA 13 | module baudgen(input wire clk, 14 | input wire clk_ena, 15 | output wire clk_out); 16 | 17 | parameter M = `B115200; //Default baud rate. 104 18 | 19 | //-- Numero de bits para almacenar el divisor de baudios 20 | localparam N = $clog2(M); 21 | 22 | //-- Registro para implementar el contador modulo M 23 | reg [N-1:0] divcounter = 0; 24 | 25 | //-- Counter 26 | always @(posedge clk) 27 | if (clk_ena) 28 | divcounter <= (divcounter == M - 1) ? 0 : divcounter + 1; //Normal work 29 | else 30 | divcounter <= M - 1; //Counter freezed to maximum value 31 | 32 | //-- Sacar un pulso de anchura 1 ciclo de reloj si el generador 33 | //-- esta habilitado (clk_ena == 1) en caso contrario se saca 0 34 | assign clk_out = (divcounter == 0) ? clk_ena : 0; 35 | 36 | endmodule 37 | -------------------------------------------------------------------------------- /sync_rules/baudgen.vh: -------------------------------------------------------------------------------- 1 | //----------------------------------------------------------------------------- 2 | //-- Constantes para el modulo de generacion de baudios para comunicaciones serie 3 | //------------------------------------------------------------------------------ 4 | //-- (C) BQ. September 2015. Written by Juan Gonzalez (Obijuan) 5 | //------------------------------------------------------------------------------ 6 | 7 | //-- Para la icestick el calculo es el siguiente: 8 | //-- Divisor = 12000000 / BAUDIOS (Y se redondea a numero entero) 9 | 10 | //-- Valores de los divisores para conseguir estos BAUDIOS: 11 | 12 | `define B115200 104 13 | `define B57600 208 14 | `define B38400 313 15 | 16 | `define B19200 625 17 | `define B9600 1250 18 | `define B4800 2500 19 | `define B2400 5000 20 | `define B1200 10000 21 | `define B600 20000 22 | `define B300 40000 23 | 24 | 25 | 26 | 27 | 28 | -------------------------------------------------------------------------------- /sync_rules/baudgen_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sayden/verilog-tutorials/550466b9b3e41655f79c3735b253f3c5cc6cacf1/sync_rules/baudgen_tb.v -------------------------------------------------------------------------------- /sync_rules/divider.v: -------------------------------------------------------------------------------- 1 | module divider(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /sync_rules/txtest.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io load 3 3 | set_io tx 8 4 | -------------------------------------------------------------------------------- /sync_rules/txtest.v: -------------------------------------------------------------------------------- 1 | //-- txtest.v file 2 | `default_nettype none 3 | 4 | `include "baudgen.vh" 5 | 6 | module txtest( 7 | input wire clk, 8 | input wire load, 9 | output reg tx 10 | ); 11 | 12 | parameter BAUD = `B300; 13 | 14 | reg [9:0] shifter; 15 | 16 | reg load_r; 17 | 18 | wire clk_baud; 19 | 20 | always @( posedge clk ) begin 21 | load_r <= load; 22 | end 23 | 24 | always @ ( posedge clk ) begin 25 | if(load_r == 0) 26 | shifter <= {"K", 2'b01}; 27 | else if (load_r == 1 && clk_baud == 1) 28 | shifter <= {1'b1, shifter[9:1]}; 29 | end 30 | 31 | always @ ( posedge clk ) begin 32 | tx <= (load_r) ? shifter[0] : 1; 33 | end 34 | 35 | baudgen #(BAUD) BAUD0(.clk(clk), .clk_ena(load_r), .clk_out(clk_baud)); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /sync_rules/txtest2.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io load 3 3 | set_io tx 8 4 | -------------------------------------------------------------------------------- /sync_rules/txtest2.v: -------------------------------------------------------------------------------- 1 | //-- txtest.v file 2 | `default_nettype none 3 | 4 | `include "baudgen.vh" 5 | 6 | module txtest2( 7 | input wire clk, 8 | input wire load, 9 | output reg tx 10 | ); 11 | 12 | parameter BAUD = `B300; 13 | 14 | reg [9:0] shifter; 15 | 16 | reg load_r; 17 | 18 | wire clk_baud; 19 | 20 | always @( posedge clk ) begin 21 | load_r <= load; 22 | end 23 | 24 | always @ ( posedge clk ) begin 25 | if(load_r == 0) 26 | shifter <= {"K", 2'b01}; 27 | else if (load_r == 1 && clk_baud == 1) 28 | shifter <= {shifter[0], shifter[9:1]}; 29 | end 30 | 31 | always @ ( posedge clk ) begin 32 | tx <= (load_r) ? shifter[0] : 1; 33 | end 34 | 35 | baudgen #(BAUD) BAUD0(.clk(clk), .clk_ena(load_r), .clk_out(clk_baud)); 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /sync_rules/txtest2_tb.v: -------------------------------------------------------------------------------- 1 | `include "baudgen.vh" 2 | 3 | module txtest2_tb(); 4 | 5 | //-- Baudios con los que realizar la simulacion 6 | //-- A 300 baudios, la simulacion tarda mas en realizarse porque los 7 | //-- tiempos son mas largos. A 115200 baudios la simulacion es mucho 8 | //-- mas rapida 9 | localparam BAUD = `B115200; 10 | 11 | //-- Tics de reloj para envio de datos a esa velocidad 12 | //-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades 13 | localparam BITRATE = (BAUD << 1); 14 | 15 | //-- Tics necesarios para enviar una trama serie completa, mas un bit adicional 16 | localparam FRAME = (BITRATE * 11); 17 | 18 | //-- Tiempo entre dos bits enviados 19 | localparam FRAME_WAIT = (BITRATE * 4); 20 | 21 | //-- Registro para generar la señal de reloj 22 | reg clk = 0; 23 | 24 | //-- Linea de tranmision 25 | wire tx; 26 | 27 | //-- Simulacion de la señal dtr 28 | reg dtr = 0; 29 | 30 | //-- Instanciar el componente 31 | txtest2 #(.BAUD(BAUD)) 32 | dut( 33 | .clk(clk), 34 | .load(dtr), 35 | .tx(tx) 36 | ); 37 | 38 | //-- Generador de reloj. Periodo 2 unidades 39 | always 40 | # 1 clk <= ~clk; 41 | 42 | //-- Proceso al inicio 43 | initial begin 44 | 45 | //-- Fichero donde almacenar los resultados 46 | $dumpfile("txtest2_tb.vcd"); 47 | $dumpvars(0, txtest2_tb); 48 | 49 | #1 dtr <= 0; 50 | 51 | //-- Enviar primer caracter 52 | #FRAME_WAIT dtr <= 1; 53 | #(FRAME * 3) dtr <=0; 54 | 55 | //-- Segundo envio 56 | #FRAME_WAIT dtr <=1; 57 | #(FRAME * 3) dtr <=0; 58 | 59 | #FRAME_WAIT $display("FIN de la simulacion"); 60 | $finish; 61 | end 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /sync_rules/txtest3.pcf: -------------------------------------------------------------------------------- 1 | set_io clk 21 2 | set_io tx 8 3 | -------------------------------------------------------------------------------- /sync_rules/txtest3.v: -------------------------------------------------------------------------------- 1 | //-- txtest.v file 2 | `default_nettype none 3 | 4 | `include "baudgen.vh" 5 | `include "divider.vh" 6 | 7 | module txtest2( 8 | input wire clk, 9 | output reg tx 10 | ); 11 | 12 | parameter BAUD = `B300; 13 | parameter DELAY = `T_250ms; 14 | 15 | reg [9:0] shifter; 16 | reg load_r; 17 | 18 | wire clk_baud; 19 | wire load; 20 | 21 | always @( posedge clk ) begin 22 | load_r <= load; 23 | end 24 | 25 | always @ ( posedge clk ) begin 26 | if(load_r == 0) 27 | shifter <= {"K", 2'b01}; 28 | else if (load_r == 1 && clk_baud == 1) 29 | shifter <= {1'b1, shifter[9:1]}; 30 | end 31 | 32 | always @ ( posedge clk ) begin 33 | tx <= (load_r) ? shifter[0] : 1; 34 | end 35 | 36 | baudgen #(BAUD) BAUD0(.clk(clk), .clk_ena(load_r), .clk_out(clk_baud)); 37 | 38 | divider #(DELAY) DIV0(.clk_in(clk), .clk_out(load)); 39 | 40 | endmodule 41 | -------------------------------------------------------------------------------- /sync_rules/txtest3_tb.v: -------------------------------------------------------------------------------- 1 | `include "baudgen.vh" 2 | 3 | module txtest2_tb(); 4 | 5 | //-- Baudios con los que realizar la simulacion 6 | //-- A 300 baudios, la simulacion tarda mas en realizarse porque los 7 | //-- tiempos son mas largos. A 115200 baudios la simulacion es mucho 8 | //-- mas rapida 9 | localparam BAUD = `B115200; 10 | 11 | //-- Tics de reloj para envio de datos a esa velocidad 12 | //-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades 13 | localparam BITRATE = (BAUD << 1); 14 | 15 | //-- Tics necesarios para enviar una trama serie completa, mas un bit adicional 16 | localparam FRAME = (BITRATE * 11); 17 | 18 | //-- Tiempo entre dos bits enviados 19 | localparam FRAME_WAIT = (BITRATE * 4); 20 | 21 | //-- Registro para generar la señal de reloj 22 | reg clk = 0; 23 | 24 | //-- Linea de tranmision 25 | wire tx; 26 | 27 | //-- Simulacion de la señal dtr 28 | reg dtr = 0; 29 | 30 | //-- Instanciar el componente 31 | txtest2 #(.BAUD(BAUD)) 32 | dut( 33 | .clk(clk), 34 | .load(dtr), 35 | .tx(tx) 36 | ); 37 | 38 | //-- Generador de reloj. Periodo 2 unidades 39 | always 40 | # 1 clk <= ~clk; 41 | 42 | //-- Proceso al inicio 43 | initial begin 44 | 45 | //-- Fichero donde almacenar los resultados 46 | $dumpfile("txtest2_tb.vcd"); 47 | $dumpvars(0, txtest2_tb); 48 | 49 | #1 dtr <= 0; 50 | 51 | //-- Enviar primer caracter 52 | #FRAME_WAIT dtr <= 1; 53 | #(FRAME * 3) dtr <=0; 54 | 55 | //-- Segundo envio 56 | #FRAME_WAIT dtr <=1; 57 | #(FRAME * 3) dtr <=0; 58 | 59 | #FRAME_WAIT $display("FIN de la simulacion"); 60 | $finish; 61 | end 62 | 63 | endmodule 64 | -------------------------------------------------------------------------------- /sync_rules/txtest_tb.v: -------------------------------------------------------------------------------- 1 | `include "baudgen.vh" 2 | 3 | module txtest_tb(); 4 | 5 | reg clk = 0; 6 | localparam BAUD = `B115200; 7 | 8 | //-- Tics de reloj para envio de datos a esa velocidad 9 | //-- Se multiplica por 2 porque el periodo del reloj es de 2 unidades 10 | localparam BITRATE = (BAUD << 1); 11 | 12 | //-- Tics necesarios para enviar una trama serie completa, mas un bit adicional 13 | localparam FRAME = (BITRATE * 11); 14 | 15 | //-- Tiempo entre dos bits enviados 16 | localparam FRAME_WAIT = (BITRATE * 4); 17 | 18 | //-- Linea de tranmision 19 | wire tx; 20 | 21 | //-- Simulacion de la señal dtr 22 | reg dtr = 0; 23 | 24 | //-- Instanciar el componente 25 | txtest #(.BAUD(BAUD)) 26 | dut(.clk(clk), 27 | .load(dtr), 28 | .tx(tx) 29 | ); 30 | 31 | //-- Generador de reloj. Periodo 2 unidades 32 | always #1 clk <= ~clk; 33 | 34 | initial begin 35 | //-- Fichero donde almacenar los resultados 36 | $dumpfile("txtest_tb.vcd"); 37 | $dumpvars(0, txtest_tb); 38 | 39 | #1 dtr <= 0; 40 | 41 | //-- Enviar primer caracter 42 | #FRAME_WAIT dtr <= 1; 43 | #FRAME dtr <=0; 44 | 45 | //-- Segundo envio 46 | #FRAME_WAIT dtr <=1; 47 | #FRAME dtr <=0; 48 | 49 | #FRAME_WAIT $display("FIN de la simulacion"); 50 | $finish; 51 | end 52 | 53 | endmodule 54 | -------------------------------------------------------------------------------- /tone_generator/Makefile: -------------------------------------------------------------------------------- 1 | NAME=tone_gen 2 | DEPS = divM.v 3 | 4 | #------------------------------------------------------- 5 | #-- Objetivo por defecto: hacer simulacion y sintesis 6 | #------------------------------------------------------- 7 | all: sint 8 | 9 | #---------------------------------------------- 10 | #-- make sim 11 | #---------------------------------------------- 12 | #-- Objetivo para hacer la simulacion del 13 | #-- banco de pruebas 14 | #---------------------------------------------- 15 | sim: $(NAME)_tb.vcd 16 | 17 | #----------------------------------------------- 18 | #- make sint 19 | #----------------------------------------------- 20 | #- Objetivo para realizar la sintetis completa 21 | #- y dejar el diseno listo para su grabacion en 22 | #- la FPGA 23 | #----------------------------------------------- 24 | sint: $(NAME).bin 25 | 26 | #------------------------------- 27 | #-- Compilacion y simulacion 28 | #------------------------------- 29 | $(NAME)_tb.vcd: $(NAME).v $(NAME)_tb.v 30 | 31 | #-- Compilar 32 | iverilog -o $(NAME).out $(NAME).v $(DEPS) $(NAME)_tb.v 33 | 34 | #-- Simular 35 | ./$(NAME).out 36 | 37 | #-- Crear VCD 38 | vvp $(NAME).out 39 | 40 | #-- Ver visualmente la simulacion con gtkwave 41 | gtkwave $(NAME)_tb.vcd 42 | 43 | #------------------------------ 44 | #-- Sintesis completa 45 | #------------------------------ 46 | $(NAME).bin: $(NAME).v $(NAME).pcf 47 | 48 | #-- Sintesis 49 | /usr/local/bin/yosys -p "synth_ice40 -blif $(NAME).blif" $(NAME).v $(DEPS) 50 | 51 | #-- Place & route 52 | arachne-pnr -d 1k -p $(NAME).pcf $(NAME).blif -o $(NAME).txt 53 | 54 | #-- Generar binario final, listo para descargar en fgpa 55 | icepack $(NAME).txt $(NAME).bin 56 | 57 | #-- Cargar en FPGA 58 | load: 59 | iceprog $(NAME).bin 60 | 61 | #-- Limpiar todo 62 | clean: 63 | rm -f *.bin *.txt *.blif *.out *.vcd *~ 64 | 65 | .PHONY: all clean 66 | -------------------------------------------------------------------------------- /tone_generator/divM.v: -------------------------------------------------------------------------------- 1 | module divM(input wire clk_in, output wire clk_out); 2 | parameter number = 12_000_000; 3 | //-- Numero de bits para almacenar el divisor 4 | //-- Se calculan con la funcion de verilog $clog2, que nos devuelve el 5 | //-- numero de bits necesarios para representar el numero M 6 | //-- Es un parametro local, que no se puede modificar al instanciar 7 | localparam N = $clog2(number); 8 | 9 | //-- Registro para implementar el contador modulo M 10 | reg [N-1:0] divcounter = 0; 11 | 12 | always @(posedge clk_in) begin 13 | divcounter <= (divcounter == number - 1) ? 0 : divcounter + 1; 14 | end 15 | 16 | //Take out MSB 17 | assign clk_out = divcounter[N-1]; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /tone_generator/tone_gen.pcf: -------------------------------------------------------------------------------- 1 | set_io clk_in 21 2 | set_io tone 44 3 | -------------------------------------------------------------------------------- /tone_generator/tone_gen.v: -------------------------------------------------------------------------------- 1 | module tone_gen(input wire clk_in, output wire tone); 2 | parameter freq = 1000; 3 | wire clk_out; 4 | 5 | divM #(.number(freq)) divider(.clk_in(clk_in), .clk_out(clk_out)); 6 | 7 | assign tone = clk_out; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /tone_generator/tone_gen_tb.v: -------------------------------------------------------------------------------- 1 | module tone_gen_tb; 2 | reg clk=0; 3 | wire out_freq3; 4 | wire out_freq5; 5 | wire out_freq7; 6 | wire out_freq10; 7 | 8 | tone_gen #(.freq(3)) uut(.clk_in(clk), .tone(out_freq3)); 9 | tone_gen #(.freq(5)) uut2(.clk_in(clk), .tone(out_freq5)); 10 | tone_gen #(.freq(7)) uut3(.clk_in(clk), .tone(out_freq7)); 11 | tone_gen #(.freq(10)) uut4(.clk_in(clk), .tone(out_freq10)); 12 | 13 | always #1 clk <= !clk; 14 | 15 | initial begin 16 | $dumpfile("tone_gen_tb.vcd"); 17 | $dumpvars; 18 | 19 | $monitor($time, ": clk=%b out3=%d out5=%d out7=%d out10=%d", clk, out_freq3, out_freq5, out_freq7, out_freq10); 20 | 21 | #100 $finish; 22 | end 23 | endmodule 24 | -------------------------------------------------------------------------------- /udp/a.out: -------------------------------------------------------------------------------- 1 | #! /usr/bin/vvp 2 | :ivl_version "10.0 (stable)"; 3 | :ivl_delay_selection "TYPICAL"; 4 | :vpi_time_precision - 12; 5 | :vpi_module "system"; 6 | :vpi_module "vhdl_sys"; 7 | :vpi_module "v2005_math"; 8 | :vpi_module "va_math"; 9 | S_0x1d3c280 .scope module, "udp_tb" "udp_tb" 2 8; 10 | .timescale -9 -12; 11 | v0x1d4da80_0 .var "x", 0 0; 12 | v0x1d4db50_0 .var "y", 0 0; 13 | v0x1d4dc20_0 .net "z", 0 0, L_0x1d4dd20; 1 drivers 14 | S_0x1d3c400 .scope module, "uut" "udp" 2 15, 3 1 0, S_0x1d3c280; 15 | .timescale 0 0; 16 | .port_info 0 /INPUT 1 "x" 17 | .port_info 1 /INPUT 1 "y" 18 | .port_info 2 /OUTPUT 1 "z" 19 | UDP_compare .udp/comb "compare", 2 20 | ,"001" 21 | ,"010" 22 | ,"100" 23 | ,"111"; 24 | L_0x1d4dd20 .udp UDP_compare, v0x1d4da80_0, v0x1d4db50_0; 25 | v0x1d3d820_0 .net "x", 0 0, v0x1d4da80_0; 1 drivers 26 | v0x1d4d870_0 .net "y", 0 0, v0x1d4db50_0; 1 drivers 27 | v0x1d4d930_0 .net "z", 0 0, L_0x1d4dd20; alias, 1 drivers 28 | .scope S_0x1d3c280; 29 | T_0 ; 30 | %pushi/vec4 0, 0, 1; 31 | %store/vec4 v0x1d4da80_0, 0, 1; 32 | %pushi/vec4 0, 0, 1; 33 | %store/vec4 v0x1d4db50_0, 0, 1; 34 | %delay 100000, 0; 35 | %delay 20000, 0; 36 | %pushi/vec4 1, 0, 1; 37 | %store/vec4 v0x1d4db50_0, 0, 1; 38 | %delay 20000, 0; 39 | %pushi/vec4 1, 0, 1; 40 | %store/vec4 v0x1d4da80_0, 0, 1; 41 | %delay 20000, 0; 42 | %pushi/vec4 0, 0, 1; 43 | %store/vec4 v0x1d4db50_0, 0, 1; 44 | %delay 20000, 0; 45 | %end; 46 | .thread T_0; 47 | .scope S_0x1d3c280; 48 | T_1 ; 49 | %vpi_call 2 32 "$monitor", "x=%d,y=%d,z=%d \012", v0x1d4da80_0, v0x1d4db50_0, v0x1d4dc20_0 {0 0 0}; 50 | %end; 51 | .thread T_1; 52 | # The file index is used to find the file name in the following table. 53 | :file_names 4; 54 | "N/A"; 55 | ""; 56 | "udp_tb.v"; 57 | "udp.v"; 58 | -------------------------------------------------------------------------------- /udp/execute: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | iverilog udp.v udp_tb.v; ./a.out 4 | -------------------------------------------------------------------------------- /udp/udp.v: -------------------------------------------------------------------------------- 1 | module udp(input x, input y, output z); 2 | 3 | compare c0(z, x, y); 4 | 5 | endmodule 6 | 7 | primitive compare(out, in1, in2); 8 | output out; 9 | input in1, in2; 10 | 11 | table 12 | //in1 in2: out 13 | 0 0 : 1; 14 | 0 1 : 0; 15 | 1 0 : 0; 16 | 1 1 : 1; 17 | endtable 18 | endprimitive 19 | -------------------------------------------------------------------------------- /udp/udp_tb.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | /* Stimulus 4 | Example showing two bit comparator 5 | referencedesigner.com 6 | */ 7 | 8 | module udp_tb; 9 | 10 | reg x; 11 | reg y; 12 | wire z; 13 | 14 | // Instantiate the Unit Under Test (UUT) 15 | udp uut (.x(x), .y(y), .z(z)); 16 | 17 | initial begin 18 | // Initialize Inputs 19 | x = 0; 20 | y = 0; 21 | 22 | // Wait 100 ns for global reset to finish 23 | #100; 24 | #20 y = 1; //01 25 | #20 x = 1; //11 26 | #20 y = 0; //10 27 | #20 ; 28 | end 29 | 30 | 31 | initial begin 32 | $monitor("x=%d,y=%d,z=%d \n",x,y,z); 33 | end 34 | 35 | endmodule 36 | --------------------------------------------------------------------------------