├── .DS_Store ├── All_Digital_VTSensor ├── 1st_version │ ├── Digital_Sensor_Verilog │ │ ├── DigitalVTSensor_Top.v │ │ ├── LICENSE │ │ ├── README.md │ │ ├── RO_MUX.v │ │ ├── RO_inv_lvt.v │ │ ├── RO_inv_rvt.v │ │ ├── RO_inv_slvt.v │ │ ├── RO_nand4_lvt.v │ │ ├── RO_nand4_rvt.v │ │ ├── RO_nand4_slvt.v │ │ ├── Ripple_Counter.v │ │ ├── SPI.v │ │ └── TDC_48step.v │ ├── Hard_Macro │ │ ├── Brown_PVTSensor.lef │ │ ├── Brown_PVTSensor.v │ │ ├── LICENSE │ │ ├── README.md │ │ └── Sensor_Compiler.py │ ├── LICENSE │ ├── README.md │ ├── Spice_Netlist │ │ ├── BGR.sp │ │ ├── LICENSE │ │ ├── README.md │ │ ├── Tosc.sp │ │ └── Vosc.sp │ └── Testbench │ │ ├── Analog_Sensor_Testbench.sp │ │ ├── Digital_Sensor_Testbench.sp │ │ ├── LICENSE │ │ └── README.md ├── 2nd_version │ ├── LICENSE │ ├── README.md │ └── Verilog_65nm_RTL │ │ ├── DigitalSensor_65_quadsensors.v │ │ ├── DigitalVTSensor_Top_V3_WDummy.v │ │ ├── DigitalVTSesnor_testbench.v │ │ ├── Dummy_RO_Top.v │ │ ├── Dummy_RO_cell.v │ │ ├── Images │ │ ├── LICENSE │ │ ├── spi_miso_code.png │ │ └── spi_mosi_code.png │ │ ├── LICENSE │ │ ├── README.md │ │ ├── RO_MUX.v │ │ ├── RO_inv_hvt.v │ │ ├── RO_inv_lvt.v │ │ ├── RO_inv_rvt.v │ │ ├── RO_nand4_hvt.v │ │ ├── RO_nand4_lvt.v │ │ ├── RO_nand4_rvt.v │ │ ├── RO_nor4_hvt.v │ │ ├── RO_nor4_lvt.v │ │ ├── RO_nor4_rvt.v │ │ ├── Ripple_Counter_RO.v │ │ ├── Ripple_Counter_SPIClkCnt.v │ │ ├── SPI.v │ │ ├── Scripts │ │ ├── LICENSE │ │ ├── README.md │ │ ├── Script_Dummy_RO_Top.py │ │ ├── Script_Main_RO_Writing.py │ │ ├── Script_TDC.py │ │ └── Script_testbench.py │ │ ├── TDC_48step.v │ │ └── testbench_RTL.v ├── LICENSE └── README.md ├── LICENSE ├── Microcontroller ├── FPGA │ ├── .DS_Store │ ├── .gitignore │ ├── .gitlab-ci.yml │ ├── LICENSE │ ├── README.md │ ├── ci │ │ ├── install-verilator.csh │ │ ├── rtl-basic-rvc.csh │ │ ├── rtl-basic.csh │ │ ├── rtl-ml-rvc.csh │ │ ├── rtl-ml.csh │ │ ├── rtl-sequential-rvc.csh │ │ ├── rtl-sequential.csh │ │ ├── setup_micro.csh │ │ ├── setup_riscy.csh │ │ ├── setup_riscy_fp.csh │ │ ├── setup_zero.csh │ │ ├── verilator-rvc.csh │ │ └── verilator.csh │ ├── create-archive.py │ ├── doc │ │ ├── api │ │ │ ├── .gitignore │ │ │ ├── api_doc.conf │ │ │ ├── conf │ │ │ ├── customdoxygen.css │ │ │ ├── footer.html │ │ │ └── header.html │ │ └── datasheet │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── README.md │ │ │ ├── content │ │ │ ├── adv_dbg_unit.tex │ │ │ ├── core.tex │ │ │ ├── memorymap.tex │ │ │ ├── overview.tex │ │ │ ├── peripherals.tex │ │ │ ├── peripherals_debug_unit.tex │ │ │ ├── peripherals_event_unit.tex │ │ │ ├── peripherals_gpio.tex │ │ │ ├── peripherals_i2c.tex │ │ │ ├── peripherals_pulpino_ctrl.tex │ │ │ ├── peripherals_spi.tex │ │ │ ├── peripherals_timer.tex │ │ │ ├── spi_slave.tex │ │ │ └── title.tex │ │ │ ├── datasheet.tex │ │ │ ├── figures │ │ │ ├── .gitignore │ │ │ ├── imperio_layout.jpg │ │ │ ├── pulpino_logo_inline1.png │ │ │ ├── riscy_archi.png │ │ │ └── zeroriscy_archi.png │ │ │ ├── figures_raw │ │ │ ├── adv_dbg_unit.obj │ │ │ ├── event_lines.obj │ │ │ ├── event_unit.obj │ │ │ ├── memory_map.obj │ │ │ ├── pulpino_block.obj │ │ │ └── riscv_overview.obj │ │ │ └── preamble │ │ │ └── preamble.tex │ ├── fpga │ │ ├── .DS_Store │ │ ├── .gitignore │ │ ├── Makefile │ │ ├── common │ │ │ └── messages.tcl │ │ ├── ips │ │ │ ├── xilinx_clock_manager │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ └── tcl │ │ │ │ │ └── run.tcl │ │ │ ├── xilinx_fp_fma │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ └── tcl │ │ │ │ │ └── run.tcl │ │ │ ├── xilinx_mem_32768x32 │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ └── tcl │ │ │ │ │ └── run.tcl │ │ │ ├── xilinx_mem_32768x32_dp │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ └── tcl │ │ │ │ │ └── run.tcl │ │ │ └── xilinx_mem_8192x32 │ │ │ │ ├── .gitignore │ │ │ │ ├── Makefile │ │ │ │ └── tcl │ │ │ │ └── run.tcl │ │ ├── pulpemu │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ └── tcl │ │ │ │ ├── impl.tcl │ │ │ │ ├── ps7_bd.tcl │ │ │ │ └── run.tcl │ │ ├── pulpino │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── constraints.xdc │ │ │ └── tcl │ │ │ │ ├── .gitignore │ │ │ │ ├── run.tcl │ │ │ │ └── src_files.tcl │ │ ├── rtl │ │ │ ├── clk_rst_gen.v │ │ │ ├── pulpemu_top.v │ │ │ └── pulpino_wrap.v │ │ └── sw │ │ │ ├── .gitignore │ │ │ ├── Makefile │ │ │ ├── apps │ │ │ ├── gpio_access │ │ │ │ ├── Makefile │ │ │ │ └── main.c │ │ │ └── spiload │ │ │ │ ├── Makefile │ │ │ │ ├── arg_parsing.c │ │ │ │ ├── console_read.c │ │ │ │ ├── main.c │ │ │ │ └── spiloader.h │ │ │ ├── boot.bif │ │ │ ├── buildroot.config │ │ │ ├── busybox.config │ │ │ ├── device-tree │ │ │ ├── pl.dtsi │ │ │ ├── skeleton.dtsi │ │ │ ├── system.dts │ │ │ ├── zybo │ │ │ │ ├── pl.dtsi │ │ │ │ ├── ps.dtsi │ │ │ │ └── system.dts │ │ │ └── zynq-7000.dtsi │ │ │ ├── hsi │ │ │ ├── Makefile │ │ │ └── fsbl.tcl │ │ │ ├── kernel.config │ │ │ ├── u-boot-xlnx-def-env.patch │ │ │ ├── u-boot.config │ │ │ └── u-boot.config.zybo │ ├── generate-scripts.py │ ├── ips │ │ └── .gitignore │ ├── ips_list.yml │ ├── rtl │ │ ├── apb_mock_uart.sv │ │ ├── axi2apb_wrap.sv │ │ ├── axi_mem_if_SP_wrap.sv │ │ ├── axi_node_intf_wrap.sv │ │ ├── axi_slice_wrap.sv │ │ ├── axi_spi_slave_wrap.sv │ │ ├── boot_code.sv │ │ ├── boot_rom_wrap.sv │ │ ├── clk_rst_gen.sv │ │ ├── components │ │ │ ├── cluster_clock_gating.sv │ │ │ ├── cluster_clock_inverter.sv │ │ │ ├── cluster_clock_mux2.sv │ │ │ ├── dp_ram.sv │ │ │ ├── generic_fifo.sv │ │ │ ├── pulp_clock_gating.sv │ │ │ ├── pulp_clock_inverter.sv │ │ │ ├── pulp_clock_mux2.sv │ │ │ ├── rstgen.sv │ │ │ └── sp_ram.sv │ │ ├── core2axi_wrap.sv │ │ ├── core_region.sv │ │ ├── dp_ram_wrap.sv │ │ ├── includes │ │ │ ├── apb_bus.sv │ │ │ ├── apu_defines.sv │ │ │ ├── axi_bus.sv │ │ │ ├── config.sv │ │ │ └── debug_bus.sv │ │ ├── instr_ram_wrap.sv │ │ ├── periph_bus_wrap.sv │ │ ├── peripherals.sv │ │ ├── pulpino_top.sv │ │ ├── ram_mux.sv │ │ ├── random_stalls.sv │ │ └── sp_ram_wrap.sv │ ├── sw │ │ ├── .DS_Store │ │ ├── CMakeLists.txt │ │ ├── README.md │ │ ├── apps │ │ │ ├── .DS_Store │ │ │ ├── .gitignore │ │ │ ├── Arduino_tests │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── GPIO_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── GPIO_test.cpp │ │ │ │ ├── PWM_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── PWM_test.cpp │ │ │ │ ├── PulseIn_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── PulseIn_test.cpp │ │ │ │ ├── SPI_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── SPI_test.cpp │ │ │ │ ├── UART_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── UART_test.cpp │ │ │ │ ├── int_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── int_test.cpp │ │ │ │ ├── shift_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── shift_test.cpp │ │ │ │ ├── timer_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── timer_test.cpp │ │ │ │ └── wire_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── wire_test.cpp │ │ │ ├── CMakeLists.txt │ │ │ ├── CMakeSim.txt │ │ │ ├── bench │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── aes_cbc │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── aes_cbc.c │ │ │ │ │ └── aes_cbc_test.c │ │ │ │ ├── common.h │ │ │ │ ├── conv2d │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── conv2d.c │ │ │ │ │ └── conv2d_test.c │ │ │ │ ├── crc32.c │ │ │ │ ├── fdctfst │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── fdctfst.c │ │ │ │ │ └── fdctfst_test.c │ │ │ │ ├── fft │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── fft.c │ │ │ │ │ └── fft_test.c │ │ │ │ ├── fir │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── fir.c │ │ │ │ │ └── fir_test.c │ │ │ │ ├── ipm │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── ipm.c │ │ │ │ │ ├── ipm.h │ │ │ │ │ └── ipm_test.c │ │ │ │ ├── keccak │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── keccak.c │ │ │ │ │ └── keccak_test.c │ │ │ │ ├── main.c │ │ │ │ ├── matmul │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── matmul16.cpp │ │ │ │ │ ├── matmul16_test.c │ │ │ │ │ ├── matmul32.cpp │ │ │ │ │ ├── matmul32_test.c │ │ │ │ │ ├── matmul8.cpp │ │ │ │ │ ├── matmul8_test.c │ │ │ │ │ └── matmul_impl.h │ │ │ │ └── sha │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── sha.c │ │ │ │ │ ├── sha.h │ │ │ │ │ └── sha_test.c │ │ │ ├── boot_code │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── boot_code.c │ │ │ ├── compressed │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── compressed.S │ │ │ │ └── main.c │ │ │ ├── fpga │ │ │ │ ├── .DS_Store │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── fpga_test │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ ├── gpio_demo │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ └── led_demo │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ ├── freertos │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── FreeRTOSConfig.h │ │ │ │ ├── Source │ │ │ │ │ ├── croutine.c │ │ │ │ │ ├── event_groups.c │ │ │ │ │ ├── include │ │ │ │ │ │ ├── FreeRTOS.h │ │ │ │ │ │ ├── StackMacros.h │ │ │ │ │ │ ├── croutine.h │ │ │ │ │ │ ├── deprecated_definitions.h │ │ │ │ │ │ ├── event_groups.h │ │ │ │ │ │ ├── list.h │ │ │ │ │ │ ├── mpu_wrappers.h │ │ │ │ │ │ ├── portable.h │ │ │ │ │ │ ├── projdefs.h │ │ │ │ │ │ ├── queue.h │ │ │ │ │ │ ├── semphr.h │ │ │ │ │ │ ├── stdint.readme │ │ │ │ │ │ ├── task.h │ │ │ │ │ │ └── timers.h │ │ │ │ │ ├── list.c │ │ │ │ │ ├── portable │ │ │ │ │ │ ├── GCC │ │ │ │ │ │ │ └── RI5CY │ │ │ │ │ │ │ │ ├── port.c │ │ │ │ │ │ │ │ └── portmacro.h │ │ │ │ │ │ └── MemMang │ │ │ │ │ │ │ ├── heap_1.c │ │ │ │ │ │ │ ├── heap_2.c │ │ │ │ │ │ │ ├── heap_3.c │ │ │ │ │ │ │ ├── heap_4.c │ │ │ │ │ │ │ └── heap_5.c │ │ │ │ │ ├── queue.c │ │ │ │ │ ├── readme.txt │ │ │ │ │ ├── tasks.c │ │ │ │ │ └── timers.c │ │ │ │ └── main.c │ │ │ ├── helloworld │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── helloworld.c │ │ │ │ └── helloworld.cpp │ │ │ ├── imperio_tests │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── testGPIO │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ └── testGPIO.c │ │ │ │ ├── testI2C │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── testI2C.c │ │ │ │ ├── testInterrupt │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ ├── testSPIMaster │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── testSPIMaster.c │ │ │ │ └── testUART │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── testUART.c │ │ │ ├── ml_tests │ │ │ │ ├── .gitignore │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── mlAxpy │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlAxpy.c │ │ │ │ │ ├── mlAxpy.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlBilat │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlBilat.c │ │ │ │ │ ├── mlBilat.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlButter │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlButter.c │ │ │ │ │ ├── mlButter.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlChol │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlChol.c │ │ │ │ │ ├── mlChol.h │ │ │ │ │ ├── mlShared.h │ │ │ │ │ └── mlsave │ │ │ │ ├── mlDct │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlDct.c │ │ │ │ │ ├── mlDct.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlDist │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlDist.c │ │ │ │ │ ├── mlDist.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlDotp │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlDotp.c │ │ │ │ │ ├── mlDotp.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlFir │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlFir.c │ │ │ │ │ ├── mlFir.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlGemm │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlGemm.c │ │ │ │ │ ├── mlGemm.h │ │ │ │ │ ├── mlShared.h │ │ │ │ │ └── stimuli.h │ │ │ │ ├── mlGemv │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlGemv.c │ │ │ │ │ ├── mlGemv.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlGivens │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlGivens.c │ │ │ │ │ ├── mlGivens.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlGrad │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlGrad.c │ │ │ │ │ ├── mlGrad.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlGradDir │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlGradDir.c │ │ │ │ │ ├── mlGradDir.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlHom │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlHom.c │ │ │ │ │ ├── mlHom.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlHomErr │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlHomErr.c │ │ │ │ │ ├── mlHomErr.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlLog │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlLog.c │ │ │ │ │ ├── mlLog.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlQr │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlQr.c │ │ │ │ │ ├── mlQr.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlRbf │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlRbf.c │ │ │ │ │ ├── mlRbf.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlSchur │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── mlSchur.c │ │ │ │ │ ├── mlSchur.h │ │ │ │ │ └── mlShared.h │ │ │ │ ├── mlSin │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlShared.h │ │ │ │ │ ├── mlSin.c │ │ │ │ │ └── mlSin.h │ │ │ │ ├── mlSvd │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlShared.h │ │ │ │ │ ├── mlSvd.c │ │ │ │ │ └── mlSvd.h │ │ │ │ ├── mlWdotp │ │ │ │ │ ├── .gitignore │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── Makefile │ │ │ │ │ ├── mlShared.h │ │ │ │ │ ├── mlWdotp.c │ │ │ │ │ └── mlWdotp.h │ │ │ │ └── ml_shared │ │ │ │ │ └── mlShared.h │ │ │ ├── riscv_tests │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── basic │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── basic.c │ │ │ │ ├── includes │ │ │ │ │ └── riscv_test.h │ │ │ │ ├── official │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── riscv_test.h │ │ │ │ │ ├── test_macros.h │ │ │ │ │ ├── test_print.c │ │ │ │ │ ├── tests.S │ │ │ │ │ └── tests │ │ │ │ │ │ ├── NOTE │ │ │ │ │ │ ├── add.S │ │ │ │ │ │ ├── addi.S │ │ │ │ │ │ ├── and.S │ │ │ │ │ │ ├── andi.S │ │ │ │ │ │ ├── auipc.S │ │ │ │ │ │ ├── beq.S │ │ │ │ │ │ ├── bge.S │ │ │ │ │ │ ├── bgeu.S │ │ │ │ │ │ ├── blt.S │ │ │ │ │ │ ├── bltu.S │ │ │ │ │ │ ├── bne.S │ │ │ │ │ │ ├── j.S │ │ │ │ │ │ ├── jal.S │ │ │ │ │ │ ├── jalr.S │ │ │ │ │ │ ├── lui.S │ │ │ │ │ │ ├── mul.S │ │ │ │ │ │ ├── or.S │ │ │ │ │ │ ├── ori.S │ │ │ │ │ │ ├── riscv_test.h │ │ │ │ │ │ ├── simple.S │ │ │ │ │ │ ├── sll.S │ │ │ │ │ │ ├── slli.S │ │ │ │ │ │ ├── slt.S │ │ │ │ │ │ ├── slti.S │ │ │ │ │ │ ├── sra.S │ │ │ │ │ │ ├── srai.S │ │ │ │ │ │ ├── srl.S │ │ │ │ │ │ ├── srli.S │ │ │ │ │ │ ├── sub.S │ │ │ │ │ │ ├── test_macros.h │ │ │ │ │ │ ├── xor.S │ │ │ │ │ │ └── xori.S │ │ │ │ ├── testALU │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testALU.c │ │ │ │ │ └── testALU_stimuli.h │ │ │ │ ├── testALUExt │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testALUExt.c │ │ │ │ │ └── testALUExt_stimuli.h │ │ │ │ ├── testAddSubNorm │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testAddSubNorm.c │ │ │ │ │ └── testAddSubNorm_stimuli.h │ │ │ │ ├── testBitManipulation │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testBitManipulation.c │ │ │ │ │ ├── testBitManipulation_stimuli.h │ │ │ │ │ └── testBitManipulation_stimuli_riscv.h │ │ │ │ ├── testCSR │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testCSR.c │ │ │ │ │ └── testCSR_stimuli.h │ │ │ │ ├── testClip │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testClip.c │ │ │ │ │ └── testClip_stimuli.h │ │ │ │ ├── testCnt │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── testCnt.c │ │ │ │ ├── testDebug │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ ├── testDivRem │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── stimuli.h │ │ │ │ │ ├── stimuli │ │ │ │ │ │ ├── Makefile │ │ │ │ │ │ └── stimuli_gen.c │ │ │ │ │ └── testDivRem.c │ │ │ │ ├── testDotMul │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── testDotMul.c │ │ │ │ │ ├── testDotMul_stimuli.h │ │ │ │ │ └── testDotMul_stimuli_riscv.h │ │ │ │ ├── testEvents │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── testEvents.c │ │ │ │ ├── testExceptions │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ ├── testFPU │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── mlShared.h │ │ │ │ │ ├── testFPU.c │ │ │ │ │ └── testFPU.h │ │ │ │ ├── testIRQ │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ ├── testMUL │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── stimuli.h │ │ │ │ │ ├── stimuli │ │ │ │ │ │ └── main.c │ │ │ │ │ └── testMUL.c │ │ │ │ ├── testMacNorm │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testMacNorm.c │ │ │ │ │ └── testMacNorm_stimuli.h │ │ │ │ ├── testMisaligned │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── main.c │ │ │ │ ├── testPriv │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ └── testPriv.c │ │ │ │ ├── testShufflePack │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testShufflePack.c │ │ │ │ │ ├── testShufflePack_stimuli.h │ │ │ │ │ └── testShufflePack_stimuli_riscv.h │ │ │ │ ├── testVecArith │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testVecArith.c │ │ │ │ │ ├── testVecArith_stimuli.h │ │ │ │ │ └── testVecArith_stimuli_riscv.h │ │ │ │ └── testVecCmp │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── gen_stimuli.py │ │ │ │ │ ├── testVecCmp.c │ │ │ │ │ └── testVecCmp_stimuli_riscv.h │ │ │ └── sequential_tests │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── bitDescriptor │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── bitDescriptor.c │ │ │ │ ├── bubblesort │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ └── bubblesort.c │ │ │ │ ├── cnn_layer │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── cnn_kernels.c │ │ │ │ ├── cnn_kernels_fused.c │ │ │ │ ├── cnn_layer.c │ │ │ │ ├── cnn_layer.h │ │ │ │ ├── config.h │ │ │ │ ├── data_image.h │ │ │ │ └── gen_stimuli.m │ │ │ │ ├── convolution │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── README.md │ │ │ │ ├── config.h │ │ │ │ ├── conv_kernels.c │ │ │ │ ├── convolution.c │ │ │ │ ├── convolution.h │ │ │ │ ├── data_image.h │ │ │ │ └── gen_stimuli.m │ │ │ │ ├── crc32 │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── crc.h │ │ │ │ ├── crc_32.c │ │ │ │ └── jrand.c │ │ │ │ ├── dct │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ └── dct.c │ │ │ │ ├── fdct │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── fdct.c │ │ │ │ └── fdct.h │ │ │ │ ├── fdtd-1d │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ └── fdtd-1d.c │ │ │ │ ├── fft │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── _kiss_fft_guts.h │ │ │ │ ├── expresp.h │ │ │ │ ├── fft_precomputed.c │ │ │ │ ├── kiss_fft.c │ │ │ │ ├── kiss_fft.h │ │ │ │ ├── kiss_fftr.c │ │ │ │ ├── kiss_fftr.h │ │ │ │ ├── main.c │ │ │ │ └── stimuli.h │ │ │ │ ├── fibonacci │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ └── fibonacci.c │ │ │ │ ├── gauss-2d │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ └── gauss.c │ │ │ │ ├── jacobi-1d-imper │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ └── jacobi-1d-imper.c │ │ │ │ ├── jacobi-2d-imper │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── jacobi-2d-imper.c │ │ │ │ └── util.h │ │ │ │ ├── matrixAdd │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── gen_stimuli.py │ │ │ │ ├── matrixAdd.c │ │ │ │ ├── matrixAdd16.h │ │ │ │ ├── matrixAdd32.h │ │ │ │ └── matrixAdd8.h │ │ │ │ ├── matrixMul16 │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── gen_stimuli.py │ │ │ │ ├── matrixMul.c │ │ │ │ └── parMatrixMul16_stimuli.h │ │ │ │ ├── matrixMul16_dotp │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── dotMatrixMul16_stimuli.h │ │ │ │ ├── gen_stimuli.py │ │ │ │ ├── matmul_kernels.c │ │ │ │ └── matrixMul.c │ │ │ │ ├── matrixMul32 │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── gen_stimuli.py │ │ │ │ ├── matrixMul.c │ │ │ │ └── parMatrixMul32_stimuli.h │ │ │ │ ├── matrixMul8 │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── gen_stimuli.py │ │ │ │ ├── matrixMul.c │ │ │ │ └── parMatrixMul8_stimuli.h │ │ │ │ ├── matrixMul8_dotp │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── dotMatrixMul8_stimuli.h │ │ │ │ ├── gen_stimuli.py │ │ │ │ ├── matmul_kernels.c │ │ │ │ └── matrixMul.c │ │ │ │ ├── motion_detection │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── conv_fast.c │ │ │ │ ├── golden │ │ │ │ │ ├── background_80_60.h │ │ │ │ │ ├── motion_detection.c │ │ │ │ │ └── test_omino_80_60.h │ │ │ │ ├── img_10_10.h │ │ │ │ ├── img_20_20.h │ │ │ │ ├── img_40_40.h │ │ │ │ ├── motion_detection.c │ │ │ │ ├── motion_detection.h │ │ │ │ ├── test_20_20.h │ │ │ │ └── test_5_5.h │ │ │ │ ├── non_separable_2d_filter │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── non_separable_2d_filter.c │ │ │ │ ├── pooling │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── config.h │ │ │ │ ├── data.h │ │ │ │ ├── gen_stimuli.m │ │ │ │ ├── pool_kernels.c │ │ │ │ ├── pooling.c │ │ │ │ └── pooling.h │ │ │ │ ├── rijndael │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── aes.c │ │ │ │ ├── aes.h │ │ │ │ ├── aestab.h │ │ │ │ └── aesxam.c │ │ │ │ ├── stencil │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── matlab │ │ │ │ │ └── stencil.m │ │ │ │ ├── stencil.c │ │ │ │ └── stencil.h │ │ │ │ ├── stencil_vect │ │ │ │ ├── CMakeLists.txt │ │ │ │ └── stencil_vect.c │ │ │ │ ├── sudokusolver │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── matlab │ │ │ │ │ └── sudokusolver.m │ │ │ │ ├── sudokusolver.c │ │ │ │ └── sudokusolver.h │ │ │ │ ├── towerofhanoi │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── Makefile │ │ │ │ ├── matlab │ │ │ │ │ └── towerofhanoi.m │ │ │ │ └── towerofhanoi.c │ │ │ │ └── tracking-seq │ │ │ │ ├── Makefile │ │ │ │ ├── image.h │ │ │ │ ├── result.h │ │ │ │ ├── tracking.c │ │ │ │ ├── tracking.h │ │ │ │ └── tracking_functions.c │ │ ├── cmake_configure.microriscy.gcc.sh │ │ ├── cmake_configure.riscv.gcc.sh │ │ ├── cmake_configure.riscvfloat.gcc.sh │ │ ├── cmake_configure.zeroriscy.gcc.sh │ │ ├── libs │ │ │ ├── Arduino_lib │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── README.md │ │ │ │ ├── core_libs │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── inc │ │ │ │ │ │ ├── Arduino.h │ │ │ │ │ │ ├── Client.h │ │ │ │ │ │ ├── HardwareSerial.h │ │ │ │ │ │ ├── HardwareSerial_private.h │ │ │ │ │ │ ├── IPAddress.h │ │ │ │ │ │ ├── Print.h │ │ │ │ │ │ ├── Printable.h │ │ │ │ │ │ ├── Server.h │ │ │ │ │ │ ├── Stream.h │ │ │ │ │ │ ├── Udp.h │ │ │ │ │ │ ├── WCharacter.h │ │ │ │ │ │ ├── WString.h │ │ │ │ │ │ ├── binary.h │ │ │ │ │ │ ├── main.cpp │ │ │ │ │ │ ├── new.h │ │ │ │ │ │ ├── pins_arduino.h │ │ │ │ │ │ └── wiring_private.h │ │ │ │ │ └── src │ │ │ │ │ │ ├── HardwareSerial.cpp │ │ │ │ │ │ ├── HardwareSerial0.cpp │ │ │ │ │ │ ├── IPAddress.cpp │ │ │ │ │ │ ├── Print.cpp │ │ │ │ │ │ ├── Stream.cpp │ │ │ │ │ │ ├── WInterrupts.c │ │ │ │ │ │ ├── WMath.cpp │ │ │ │ │ │ ├── WString.cpp │ │ │ │ │ │ ├── abi.cpp │ │ │ │ │ │ ├── hooks.c │ │ │ │ │ │ ├── new.cpp │ │ │ │ │ │ ├── wiring.c │ │ │ │ │ │ ├── wiring_analog.c │ │ │ │ │ │ ├── wiring_digital.c │ │ │ │ │ │ ├── wiring_pulse.c │ │ │ │ │ │ └── wiring_shift.c │ │ │ │ └── separate_libs │ │ │ │ │ ├── CMakeLists.txt │ │ │ │ │ ├── inc │ │ │ │ │ ├── SPI.h │ │ │ │ │ ├── Wire.h │ │ │ │ │ └── twi.h │ │ │ │ │ └── src │ │ │ │ │ ├── SPI.cpp │ │ │ │ │ ├── Wire.cpp │ │ │ │ │ └── twi.c │ │ │ ├── bench_lib │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── inc │ │ │ │ │ └── bench.h │ │ │ │ └── src │ │ │ │ │ └── bench.c │ │ │ ├── math_fns_lib │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── inc │ │ │ │ │ └── math_fns.h │ │ │ │ └── src │ │ │ │ │ └── math_fns.c │ │ │ ├── string_lib │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── inc │ │ │ │ │ └── string_lib.h │ │ │ │ └── src │ │ │ │ │ └── qprintf.c │ │ │ └── sys_lib │ │ │ │ ├── CMakeLists.txt │ │ │ │ ├── inc │ │ │ │ ├── bar.h │ │ │ │ ├── cpu_hal.h │ │ │ │ ├── event.h │ │ │ │ ├── gpio.h │ │ │ │ ├── i2c.h │ │ │ │ ├── int.h │ │ │ │ ├── pulpino.h │ │ │ │ ├── spi.h │ │ │ │ ├── spr-defs.h │ │ │ │ ├── timer.h │ │ │ │ ├── uart.h │ │ │ │ └── utils.h │ │ │ │ └── src │ │ │ │ ├── exceptions.c │ │ │ │ ├── gpio.c │ │ │ │ ├── i2c.c │ │ │ │ ├── int.c │ │ │ │ ├── spi.c │ │ │ │ ├── timer.c │ │ │ │ ├── uart.c │ │ │ │ └── utils.c │ │ ├── ref │ │ │ ├── crt0.boot.S │ │ │ ├── crt0.boot_E.S │ │ │ ├── crt0.or1k.S │ │ │ ├── crt0.riscv.S │ │ │ ├── crt0.riscv_E.S │ │ │ ├── link.boot.ld │ │ │ ├── link.common.ld │ │ │ ├── link.or1k.ld │ │ │ └── link.riscv.ld │ │ └── utils │ │ │ ├── annotate.py │ │ │ ├── parse_s19.pl │ │ │ ├── run-on-fpga.sh │ │ │ ├── s19toboot.py │ │ │ └── s19toslm.py │ ├── tb │ │ ├── .gitignore │ │ ├── i2c_eeprom_model.sv │ │ ├── if_spi_master.sv │ │ ├── if_spi_slave.sv │ │ ├── jtag_dpi.sv │ │ ├── jtag_dpi │ │ │ ├── .gitignore │ │ │ └── jtag_dpi.c │ │ ├── mem_dpi.svh │ │ ├── mem_dpi │ │ │ ├── .gitignore │ │ │ └── mem_dpi.c │ │ ├── pkg_spi.sv │ │ ├── spi_debug_test.svh │ │ ├── tb.sv │ │ ├── tb_jtag_pkg.sv │ │ ├── tb_mem_pkg.sv │ │ ├── tb_spi_pkg.sv │ │ └── uart.sv │ ├── update-ips.py │ └── vsim │ │ ├── .gitignore │ │ ├── tcl_files │ │ ├── config │ │ │ ├── vsim.tcl │ │ │ └── vsim_zero.tcl │ │ ├── run.tcl │ │ ├── run_debug.tcl │ │ ├── run_debug_irq.tcl │ │ ├── run_mem_dpi.tcl │ │ ├── run_memdpi.tcl │ │ ├── run_spi.tcl │ │ └── run_zero-riscy_spi.tcl │ │ ├── vcompile │ │ ├── build_rtl_sim.csh │ │ ├── colors.csh │ │ ├── rtl │ │ │ ├── vcompile_pulpino.sh │ │ │ └── vcompile_tb.sh │ │ ├── setup.csh │ │ ├── vcompile_riscv.csh │ │ └── vcompile_zero-riscy.csh │ │ ├── verilator │ │ └── .gitignore │ │ └── waves │ │ ├── .gitingore │ │ ├── micro_riscy_core.tcl │ │ ├── riscy_core.tcl │ │ ├── zero_riscy_core_fastMul.tcl │ │ └── zero_riscy_core_slowMul.tcl ├── Interface │ ├── .DS_Store │ └── interface .pdf ├── LICENSE ├── README.md └── SPI_Slave_Verilog │ ├── Cnt_SPI_diagram.PNG │ ├── Counter.v │ ├── README.md │ ├── SPIMaster_Arduino.ino │ └── SPI_Slave.v ├── PVT_Sensor ├── .DS_Store ├── Images │ ├── CPM_Sch_WhBG.png │ ├── tsensor_comp.png │ ├── uW_TSensor.JPG │ ├── uW_VSensor.JPG │ └── vsensor_comp.png ├── LICENSE ├── README.md ├── SpiceNetlist │ ├── LICENSE │ ├── README.md │ ├── uW_TSensor │ └── uW_VSensor ├── Testbench │ ├── LICENSE │ ├── README.md │ ├── TSesnor_Testbench.sp │ └── VSesnor_Testbench.sp ├── VerilogCode │ ├── CPM_Verilog │ │ ├── CPL.v │ │ ├── CPM.v │ │ ├── LICENSE │ │ ├── README.md │ │ ├── SC.v │ │ └── TDC.v │ ├── LICENSE │ ├── README.md │ └── VT_VerilogAMS │ │ ├── LICENSE │ │ ├── README.md │ │ ├── uW_TSensor.vams │ │ └── uW_VSensor.vams └── pyXyce │ ├── ANALYSIS.inc │ ├── BrownPVT.ipynb │ ├── MODELS.lib │ ├── PVT.py │ ├── README.md │ └── uW_TSensor.netlist ├── README.md └── Software ├── LICENSE ├── PIDNN ├── LICENSE ├── README.md ├── genann.c ├── genann.h └── pidnn.c └── README.md /.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/.DS_Store -------------------------------------------------------------------------------- /All_Digital_VTSensor/1st_version/Digital_Sensor_Verilog/RO_MUX.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 100fs 2 | 3 | module RO_MUX( 4 | input wire [5:0]RO_IN, 5 | input wire [3:1]S, 6 | output wire RO_OUT 7 | ); 8 | 9 | wire [4:0]MUX_Conn; 10 | 11 | /// S1 12 | assign MUX_Conn[0] = S[1] ? RO_IN[0] : RO_IN[1]; 13 | assign MUX_Conn[1] = S[1] ? RO_IN[2] : RO_IN[3]; 14 | assign MUX_Conn[2] = S[1] ? RO_IN[4] : RO_IN[5]; 15 | /// S2 16 | assign MUX_Conn[3] = S[2] ? MUX_Conn[0] : MUX_Conn[1]; 17 | assign MUX_Conn[4] = S[2] ? MUX_Conn[2] : 1'b0; 18 | /// S3 19 | assign RO_OUT = S[3] ? MUX_Conn[3] : MUX_Conn[4]; 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /All_Digital_VTSensor/1st_version/Hard_Macro/Brown_PVTSensor.v: -------------------------------------------------------------------------------- 1 | `timescale 10ps / 1ps 2 | 3 | module Brown_PVTSensor( 4 | input i_Clk, 5 | input A_BGR_PS, 6 | input i_CntWin, 7 | input i_Rst_n, 8 | input i_SPI_CS_n, 9 | input i_SPI_Clk, 10 | input i_SPI_MOSI, 11 | 12 | output o_SPI_MISO, 13 | 14 | inout AVDD, 15 | inout DVDD, 16 | inout GND 17 | ); 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /All_Digital_VTSensor/1st_version/Spice_Netlist/README.md: -------------------------------------------------------------------------------- 1 | ## General Overview 2 | 3 | This folder contains Netlist files for the following circuits: 4 | 5 | - Bandgap Reference Circuit 6 | 7 | - Analog Voltage Sensor 8 | 9 | - Analog Temeprature Sensor 10 | 11 | 12 | Designs were verified in GF12 technology. 13 | 14 | Model names used are listed below: 15 | 16 | - 'nfet' stands for N-type FinFET 17 | 18 | - 'pfet' stands for P-type FinFET 19 | 20 | - 'egnfet' stands for Extended Gate N-type FinFET 21 | 22 | - 'egpfet' stands for Extended Gate P-type FinFET 23 | 24 | - 'rmres' stands for Metal Resistor 25 | 26 | - 'egtdpdnw' stands for N-well diode 27 | 28 | - 'mimcap' stands for MIM capacitor 29 | -------------------------------------------------------------------------------- /All_Digital_VTSensor/1st_version/Testbench/README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # General Overview 4 | 5 | This folder contains testbench SPICE files for the analog sensor and digital sensor seperately. 6 | 7 | # Setup 8 | 9 | There are 2 ways to use the testbench: 10 | - __Copy the spice netlist__: 11 | 12 | The first option is to copy the netlist the corresponding blocks 13 | 14 | 15 | To run the analog sensor testbench, please copy the netlist from 'BGR.sp', 'Tosc.sp' and 'Vosc.sp' into Analog_Sensor_Testbench.sp between 16 | ``` 17 | parameters vdd=0.8 wireopt=9 18 | ``` 19 | and 20 | ``` 21 | I0 (GND IREFT TOsc_TB\<0\> TOsc_TB\<1\> TOsc_TB\<2\> TOsc_TB\<3\> \ 22 | ``` 23 | 24 | 25 | To run the digital sensor testbench, please copy the netlist in DigitalSensor.sp from 26 | ``` 27 | subckt INV_X0P5N_A9PP84TR_C14 A VDD VNW VPW VSS Y 28 | ``` 29 | to 30 | ``` 31 | VDD VSS VTMUX) Module_RippleCnt_A_V2 32 | ``` 33 | and insert the netlist into Digital_Sensor_Testbench.sp between 34 | ``` 35 | parameters DLYD=90n vdd=0.8 wireopt=9 36 | ``` 37 | and 38 | ``` 39 | I0 (RO_EN net016 RO_OUT\<2\> RO_Sel\<2\> VDD VSS) \ 40 | ``` 41 | 42 | 43 | - __Add sensor as sub-circuit__: 44 | 45 | If you are using Virtuoso(or similar simulator), you can import both the sensor and its testbench, and add the sensor block into the testbench as a subcircuit. 46 | -------------------------------------------------------------------------------- /All_Digital_VTSensor/2nd_version/README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # General Overview 4 | 5 | This folder contains the following: 6 | 7 | - Verilog_65nm_RTL: RTL netlist and testbench of the all-digital VT sensor. 8 | 9 | # Prerequisites 10 | 11 | These circuits were designed using Cadence® Virtuoso®, Synopsys® Design Compiler®, Cadence® Innovus® and Mentor® Modelsim®. You must also separately obtain the TSMC 65/55nm GP PDK and ARM 65/55nm GP-based standard cell library, through MOSIS or a commercial license. 12 | 13 | 14 | -------------------------------------------------------------------------------- /All_Digital_VTSensor/2nd_version/Verilog_65nm_RTL/Images/spi_miso_code.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/All_Digital_VTSensor/2nd_version/Verilog_65nm_RTL/Images/spi_miso_code.png -------------------------------------------------------------------------------- /All_Digital_VTSensor/2nd_version/Verilog_65nm_RTL/Images/spi_mosi_code.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/All_Digital_VTSensor/2nd_version/Verilog_65nm_RTL/Images/spi_mosi_code.png -------------------------------------------------------------------------------- /All_Digital_VTSensor/2nd_version/Verilog_65nm_RTL/RO_MUX.v: -------------------------------------------------------------------------------- 1 | `timescale 1ps / 100fs 2 | 3 | module RO_MUX( 4 | input wire [15:0]RO_IN, 5 | input wire [4:1]S, 6 | output wire RO_OUT 7 | ); 8 | 9 | ///////////////// 2^3 + 2^2 + 2 = 14 connection wires needed ///////////////// 10 | wire [13:0]MUX_Conn; 11 | 12 | /// S1 13 | assign MUX_Conn[0] = S[1] ? RO_IN[1] : RO_IN[0]; 14 | assign MUX_Conn[1] = S[1] ? RO_IN[3] : RO_IN[2]; 15 | assign MUX_Conn[2] = S[1] ? RO_IN[5] : RO_IN[4]; 16 | assign MUX_Conn[3] = S[1] ? RO_IN[7] : RO_IN[6]; 17 | assign MUX_Conn[4] = S[1] ? RO_IN[9] : RO_IN[8]; 18 | assign MUX_Conn[5] = S[1] ? RO_IN[11] : RO_IN[10]; 19 | assign MUX_Conn[6] = S[1] ? RO_IN[13] : RO_IN[12]; 20 | assign MUX_Conn[7] = S[1] ? RO_IN[15] : RO_IN[14]; 21 | /// S2 22 | assign MUX_Conn[8] = S[2] ? MUX_Conn[1] : MUX_Conn[0]; 23 | assign MUX_Conn[9] = S[2] ? MUX_Conn[3] : MUX_Conn[2]; 24 | assign MUX_Conn[10] = S[2] ? MUX_Conn[5] : MUX_Conn[4]; 25 | assign MUX_Conn[11] = S[2] ? MUX_Conn[7] : MUX_Conn[6]; 26 | /// S3 27 | assign MUX_Conn[12] = S[3] ? MUX_Conn[9] : MUX_Conn[8]; 28 | assign MUX_Conn[13] = S[3] ? MUX_Conn[11] : MUX_Conn[10]; 29 | /// S4 30 | assign RO_OUT = S[4] ? MUX_Conn[13] : MUX_Conn[12]; 31 | 32 | endmodule 33 | -------------------------------------------------------------------------------- /All_Digital_VTSensor/2nd_version/Verilog_65nm_RTL/Scripts/Script_Dummy_RO_Top.py: -------------------------------------------------------------------------------- 1 | ####################################### 2 | # Define variable 3 | ####################################### 4 | # define how many dummy ROs needed, maximum 32*8 5 | dummy_cnt = 512 6 | 7 | ####################################### 8 | # Create file 9 | ####################################### 10 | # Create a new file 11 | f = open("Dummy_RO_Top.v","w") 12 | 13 | # write the top of the module 14 | f.write("`timescale 1ps / 100fs\n\n") 15 | f.write("module Dummy_RO_Top(\n") 16 | f.write("input wire i_Enable,\n") 17 | f.write("input wire [31:0] i_Sel\n") 18 | f.write(");\n\n") 19 | 20 | f.write("//////////////// Dummy ROs ////////////////\n\n") 21 | wire_share = int(dummy_cnt/32) 22 | for i in range(32): 23 | for j in range(wire_share): 24 | f.write("Dummy_RO_cell D" + str(j+i*wire_share) + "(\n") 25 | f.write(".i_Enable(Enable_Dummy_RO),\n") 26 | f.write(".i_Sel(i_Sel[" + str(i) + "])\n") 27 | f.write(");\n\n") 28 | 29 | f.write("endmodule \n\n") 30 | 31 | f.close() -------------------------------------------------------------------------------- /All_Digital_VTSensor/README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/All_Digital_VTSensor/README.md -------------------------------------------------------------------------------- /Microcontroller/FPGA/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/.DS_Store -------------------------------------------------------------------------------- /Microcontroller/FPGA/.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | sw/build/* 3 | imperio 4 | ipstools 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/install-verilator.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | 4 | wget http://www.veripool.org/ftp/verilator-3.884.tgz 5 | tar -xzvf verilator-3.884.tgz && cd verilator-3.884/ && mkdir build 6 | autoconf && ./configure --prefix="${PWD}/build/" && make && make test && make install 7 | 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/rtl-basic-rvc.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build-rvc 4 | ctest -L riscv_test -j4 --timeout 3000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/rtl-basic.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build 4 | ctest -L riscv_test -j4 --timeout 3000 --output-on-failure 5 | 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/rtl-ml-rvc.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build-rvc 4 | ctest -L ml_tests -j4 --timeout 3000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/rtl-ml.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build 4 | ctest -L ml_tests -j4 --timeout 3000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/rtl-sequential-rvc.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build-rvc 4 | ctest -L sequential_test -j4 --timeout 4000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/rtl-sequential.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build 4 | ctest -L sequential_test -j4 --timeout 4000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/verilator-rvc.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build-rvc_riscy 4 | ctest -L verilator_tests -j4 --timeout 3000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ci/verilator.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | cd ./sw/build_riscy 4 | ctest -L verilator_tests -j4 --timeout 3000 --output-on-failure 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/api/.gitignore: -------------------------------------------------------------------------------- 1 | html/* 2 | latex/* -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/api/footer.html: -------------------------------------------------------------------------------- 1 |
2 | Generated on $datetime for $projectname by doxygen $doxygenversion
3 | 4 | 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/api/header.html: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | $title 7 | 8 | 9 | 12 | 13 | 15 | 16 | 19 | 20 | 21 | 22 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/.gitignore: -------------------------------------------------------------------------------- 1 | *.aux 2 | *.log 3 | *.toc 4 | datasheet.pdf 5 | fig*/*.pdf 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/README.md: -------------------------------------------------------------------------------- 1 | # PDF version 2 | 3 | A precompiled version of this data sheet is available on our [website](http://www.pulp-platform.org/documentation/) 4 | 5 | Direct link: [PULPino Data Sheet](http://www.pulp-platform.org/wp-content/uploads/2016/02/pulpino_datasheet.pdf) 6 | 7 | # Compile Steps 8 | 9 | If you want to build the documentation from source, you can use `make all` to 10 | compile the LaTeX sources. This also takes care of preparing some of the 11 | figures that are generated on-demand. 12 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/content/adv_dbg_unit.tex: -------------------------------------------------------------------------------- 1 | \chapter{Advanced Debug Unit} 2 | 3 | The advanced debug unit has an AXI master interface to access peripherals and 4 | memories. In contrast to PulpinoV1 the adv. debug unit does no longer feature 5 | a specialized debug interface to readout all core registers. 6 | 7 | All core registers are now memory mapped which means that they can be read over 8 | the AXI interface. Hence, debugging is not only possible over JTAG, but also SPI 9 | or any other interface. 10 | 11 | The JTAG signals are connected to pins of the SoC. 12 | 13 | \begin{figure}[H] 14 | \centering 15 | \includegraphics[width=0.5\textwidth]{./figures/adv_dbg_unit.eps} 16 | \caption{Advanced Debug Unit.} 17 | \label{fig:adv_dbg_unit} 18 | \end{figure} 19 | 20 | For more details please take a look at the documentation of the advanced debug unit. 21 | 22 | 23 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/content/overview.tex: -------------------------------------------------------------------------------- 1 | \chapter{Overview} 2 | 3 | \pulpino is a single-core System-on-a-Chip built for the \riscv \rvcore and \zerocore core. 4 | \pulpino reuses most components from its bigger brother \pulp. 5 | It uses separate single-port data and instruction RAMs. It includes a boot ROM 6 | that contains a boot loader that can load a program via SPI from an external 7 | flash device. 8 | 9 | Figure~\ref{fig:pulpino_overview} shows a block diagram of the SoC. 10 | The SoC uses a AXI as its main interconnect with a bridge to APB for simple 11 | peripherals. Both the AXI and the APB buses feature 32 bit wide data channels. 12 | For debugging purposes the SoC includes an advanced debug unit 13 | which enables access to core registers, the two RAMs and memory-mapped IO via JTAG. 14 | Both RAMs are connected to the AXI bus via bus adapters. 15 | 16 | \begin{figure}[H] 17 | \centering 18 | \includegraphics[width=0.9\textwidth]{./figures/pulpino_block.eps} 19 | \caption{\pulpino Overview.} 20 | \label{fig:pulpino_overview} 21 | \end{figure} 22 | 23 | 24 | \pulpino is mainly targeted at RTL simulation and ASICs, although there is also 25 | an FPGA version. The FPGA versions is not specifically optimal in terms of 26 | performance as we mainly use it as a emulation platform rather than a standalone 27 | platform. 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/content/title.tex: -------------------------------------------------------------------------------- 1 | \makeatletter 2 | \begin{titlepage} 3 | 4 | % Remove the page number in the footer. 5 | \thispagestyle{empty} 6 | 7 | \begin{center} 8 | 9 | \begin{spacing}{2.0} 10 | {\Huge\textbf{\@title}} 11 | \end{spacing} 12 | 13 | \vspace{0.2cm} 14 | 15 | \vfill 16 | 17 | \includegraphics[height = 12cm]{figures/imperio_layout} \\ 18 | {\textit{Imperio: The first PULPino ASIC}} 19 | 20 | \vfill 21 | 22 | {\Large \@author}\\ 23 | {\{atraber, gautschi\}@iis.ee.ethz.ch} 24 | \vfill 25 | \@date 26 | 27 | \end{center} 28 | \end{titlepage} 29 | \makeatother 30 | 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/figures/.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/doc/datasheet/figures/.gitignore -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/figures/imperio_layout.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/doc/datasheet/figures/imperio_layout.jpg -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/figures/pulpino_logo_inline1.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/doc/datasheet/figures/pulpino_logo_inline1.png -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/figures/riscy_archi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/doc/datasheet/figures/riscy_archi.png -------------------------------------------------------------------------------- /Microcontroller/FPGA/doc/datasheet/figures/zeroriscy_archi.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/doc/datasheet/figures/zeroriscy_archi.png -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/fpga/.DS_Store -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/.gitignore: -------------------------------------------------------------------------------- 1 | simu 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/Makefile: -------------------------------------------------------------------------------- 1 | all: ips pulpino pulpemu sw 2 | 3 | 4 | 5 | .PHONY: ips 6 | ips: clk mem fp_fma 7 | 8 | 9 | .PHONY: clk 10 | clk: ips/xilinx_clock_manager/ip/xilinx_clock_manager.dcp 11 | 12 | ips/xilinx_clock_manager/ip/xilinx_clock_manager.dcp: 13 | make -C ips/xilinx_clock_manager/ clean all 14 | 15 | 16 | .PHONY: mem 17 | mem: ips/xilinx_mem_8192x32/ip/xilinx_mem_8192x32.dcp 18 | 19 | ips/xilinx_mem_8192x32/ip/xilinx_mem_8192x32.dcp: 20 | make -C ips/xilinx_mem_8192x32/ clean all 21 | 22 | 23 | .PHONY: mem_dp 24 | mem_dp: ips/xilinx_mem_32768x32_dp/ip/xilinx_mem_32768x32_dp.dcp 25 | 26 | ips/xilinx_mem_32768x32_dp/ip/xilinx_mem_32768x32_dp.dcp: 27 | make -C ips/xilinx_mem_32768x32_dp/ clean all 28 | 29 | .PHONY: fp_fma 30 | fp_fma: ips/xilinx_fp_fma/ip/xilinx_fp_fma.dcp 31 | 32 | ips/xilinx_fp_fma/ip/xilinx_fp_fma.dcp: 33 | make -C ips/xilinx_fp_fma/ clean all 34 | 35 | .PHONY: pulpino 36 | pulpino: pulpino/pulpino.edf 37 | 38 | pulpino/pulpino.edf: 39 | make -C pulpino clean all 40 | 41 | 42 | .PHONY: pulpemu 43 | pulpemu: pulpemu/pulpemu_top.bit 44 | 45 | pulpemu/pulpemu_top.bit: 46 | make -C pulpemu clean all 47 | 48 | 49 | .PHONY: sw 50 | sw: 51 | make -C sw all 52 | 53 | 54 | .PHONY: clean 55 | clean: 56 | make -C ips/xilinx_clock_manager/ clean 57 | make -C ips/xilinx_mem_8192x32/ clean 58 | make -C ips/xilinx_mem_32768x32_dp/ clean 59 | make -C ips/xilinx_fp_fma/ clean 60 | make -C pulpino clean 61 | make -C pulpemu clean 62 | make -C sw clean 63 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/common/messages.tcl: -------------------------------------------------------------------------------- 1 | # sets up Vivado messages in a more sensible way 2 | 3 | set_msg_config -id {[Synth 8-3352]} -new_severity "critical warning" 4 | set_msg_config -id {[Synth 8-350]} -new_severity "critical warning" 5 | set_msg_config -id {[Synth 8-2490]} -new_severity "warning" 6 | set_msg_config -id {[Synth 8-2306]} -new_severity "info" 7 | set_msg_config -id {[Synth 8-3331]} -new_severity "critical warning" 8 | set_msg_config -id {[Synth 8-3332]} -new_severity "info" 9 | set_msg_config -id {[Synth 8-2715]} -new_severity "error" 10 | set_msg_config -id {[Opt 31-35]} -new_severity "info" 11 | set_msg_config -id {[Opt 31-32]} -new_severity "info" 12 | set_msg_config -id {[Shape Builder 18-119]} -new_severity "warning" 13 | set_msg_config -id {[Filemgmt 20-742]} -new_severity "error" 14 | 15 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_clock_manager/.gitignore: -------------------------------------------------------------------------------- 1 | ip/ 2 | vivado.jou 3 | vivado.log 4 | vivado*.backup.jou 5 | vivado*.backup.log 6 | *.cache/ 7 | *.hw/ 8 | *.runs/ 9 | *.srcs/ 10 | *.xpr 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_clock_manager/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xilinx_clock_manager 2 | 3 | all: 4 | vivado -mode batch -source tcl/run.tcl 5 | mkdir -p ip 6 | cp ${PROJECT}.runs/${PROJECT}_synth_1/${PROJECT}.dcp ip/ 7 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}_stub.v ip/ 8 | 9 | gui: 10 | vivado -mode gui -source tcl/run.tcl & 11 | 12 | clean: 13 | rm -rf ip/* 14 | mkdir -p ip 15 | rm -rf ${PROJECT}.xpr 16 | rm -rf ${PROJECT}.hw 17 | rm -rf ${PROJECT}.data 18 | rm -rf ${PROJECT}.runs 19 | rm -rf ${PROJECT}.srcs 20 | rm -rf ${PROJECT}.cache 21 | rm -rf component.xml 22 | rm -rf vivado*.jou 23 | rm -rf vivado*.log 24 | rm -rf vivado*.str 25 | rm -rf xgui 26 | rm -rf .Xil 27 | 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_fp_fma/.gitignore: -------------------------------------------------------------------------------- 1 | ip/ 2 | vivado.jou 3 | vivado.log 4 | vivado*.backup.jou 5 | vivado*.backup.log 6 | *.cache/ 7 | *.hw/ 8 | *.runs/ 9 | *.srcs/ 10 | *.xpr 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_fp_fma/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xilinx_fp_fma 2 | 3 | all: 4 | vivado -mode batch -source tcl/run.tcl 5 | mkdir -p ip 6 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}_stub.v ./ip 7 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}_stub.vhdl ./ip 8 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.xci ./ip 9 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.veo ./ip 10 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.dcp ./ip 11 | 12 | gui: 13 | vivado -mode gui -source tcl/run.tcl & 14 | 15 | clean: 16 | rm -rf ip/* 17 | mkdir -p ip 18 | rm -rf ${PROJECT}.xpr 19 | rm -rf ${PROJECT}.hw 20 | rm -rf ${PROJECT}.data 21 | rm -rf ${PROJECT}.runs 22 | rm -rf ${PROJECT}.srcs 23 | rm -rf ${PROJECT}.cache 24 | rm -rf component.xml 25 | rm -rf vivado*.jou 26 | rm -rf vivado*.log 27 | rm -rf vivado*.str 28 | rm -rf xgui 29 | 30 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_fp_fma/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | 2 | if { ![info exists ::env(XILINX_PART)] } { 3 | set ::env(XILINX_PART) "xc7z020clg484-1" 4 | } 5 | 6 | if { ![info exists ::env(XILINX_BOARD)] } { 7 | set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c" 8 | } 9 | 10 | set partNumber $::env(XILINX_PART) 11 | set boardName $::env(XILINX_BOARD) 12 | 13 | create_project xilinx_fp_fma . -part $partNumber 14 | set_property board $boardName [current_project] 15 | create_ip -name floating_point -vendor xilinx.com -library ip -version 7.0 -module_name xilinx_fp_fma 16 | set_property -dict [list CONFIG.Operation_Type {FMA} CONFIG.Flow_Control {NonBlocking} CONFIG.Axi_Optimize_Goal {Resources} CONFIG.Has_RESULT_TREADY {false} CONFIG.Maximum_Latency {false} CONFIG.Has_ARESETn {true} CONFIG.C_Has_UNDERFLOW {true} CONFIG.C_Has_OVERFLOW {true} CONFIG.C_Has_INVALID_OP {true} CONFIG.A_Precision_Type {Single} CONFIG.C_A_Exponent_Width {8} CONFIG.C_A_Fraction_Width {24} CONFIG.Result_Precision_Type {Single} CONFIG.C_Result_Exponent_Width {8} CONFIG.C_Result_Fraction_Width {24} CONFIG.C_Mult_Usage {Medium_Usage} CONFIG.C_Latency {2} CONFIG.C_Rate {1}] [get_ips xilinx_fp_fma] 17 | generate_target all [get_files ./xilinx_fp_fma.srcs/sources_1/ip/xilinx_fp_fma/xilinx_fp_fma.xci] 18 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_fp_fma.srcs/sources_1/ip/xilinx_fp_fma/xilinx_fp_fma.xci] 19 | launch_run -jobs 8 xilinx_fp_fma_synth_1 20 | wait_on_run xilinx_fp_fma_synth_1 21 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_32768x32/.gitignore: -------------------------------------------------------------------------------- 1 | ip/ 2 | vivado.jou 3 | vivado.log 4 | vivado*.backup.jou 5 | vivado*.backup.log 6 | *.cache/ 7 | *.hw/ 8 | *.runs/ 9 | *.srcs/ 10 | *.xpr 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_32768x32/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xilinx_mem_32768x32 2 | 3 | all: 4 | vivado -mode batch -source tcl/run.tcl 5 | mkdir -p ip 6 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}_stub.v ./ip 7 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.xci ./ip 8 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.veo ./ip 9 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.dcp ./ip 10 | 11 | gui: 12 | vivado -mode gui -source tcl/run.tcl & 13 | 14 | clean: 15 | rm -rf ip/* 16 | mkdir -p ip 17 | rm -rf ${PROJECT}.xpr 18 | rm -rf ${PROJECT}.hw 19 | rm -rf ${PROJECT}.data 20 | rm -rf ${PROJECT}.runs 21 | rm -rf ${PROJECT}.srcs 22 | rm -rf ${PROJECT}.cache 23 | rm -rf component.xml 24 | rm -rf vivado*.jou 25 | rm -rf vivado*.log 26 | rm -rf vivado*.str 27 | rm -rf xgui 28 | 29 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_32768x32/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | 2 | if { ![info exists ::env(XILINX_PART)] } { 3 | set ::env(XILINX_PART) "xc7z020clg484-1" 4 | } 5 | 6 | if { ![info exists ::env(XILINX_BOARD)] } { 7 | set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c" 8 | } 9 | 10 | set partNumber $::env(XILINX_PART) 11 | set boardName $::env(XILINX_BOARD) 12 | 13 | create_project xilinx_mem_32768x32 . -part $partNumber 14 | set_property board $boardName [current_project] 15 | create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_32768x32 16 | set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {32768} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_mem_32768x32] 17 | generate_target all [get_files ./xilinx_mem_32768x32.srcs/sources_1/ip/xilinx_mem_32768x32/xilinx_mem_32768x32.xci] 18 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_mem_32768x32.srcs/sources_1/ip/xilinx_mem_32768x32/xilinx_mem_32768x32.xci] 19 | launch_run -jobs 8 xilinx_mem_32768x32_synth_1 20 | wait_on_run xilinx_mem_32768x32_synth_1 21 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_32768x32_dp/.gitignore: -------------------------------------------------------------------------------- 1 | ip/ 2 | vivado.jou 3 | vivado.log 4 | vivado*.backup.jou 5 | vivado*.backup.log 6 | *.cache/ 7 | *.hw/ 8 | *.runs/ 9 | *.srcs/ 10 | *.xpr 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_32768x32_dp/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xilinx_mem_32768x32_dp 2 | 3 | all: 4 | vivado -mode batch -source tcl/run.tcl 5 | cp xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp_stub.v ./ip 6 | cp xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp.xci ./ip 7 | cp xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp.veo ./ip 8 | cp xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp.dcp ./ip 9 | 10 | gui: 11 | vivado -mode gui -source tcl/run.tcl & 12 | 13 | clean: 14 | rm -rf ip/* 15 | mkdir -p ip 16 | rm -rf ${PROJECT}.xpr 17 | rm -rf ${PROJECT}.hw 18 | rm -rf ${PROJECT}.data 19 | rm -rf ${PROJECT}.runs 20 | rm -rf ${PROJECT}.srcs 21 | rm -rf ${PROJECT}.cache 22 | rm -rf component.xml 23 | rm -rf vivado*.jou 24 | rm -rf vivado*.log 25 | rm -rf vivado*.str 26 | rm -rf xgui 27 | 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_32768x32_dp/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | 2 | if { ![info exists ::env(XILINX_PART)] } { 3 | set ::env(XILINX_PART) "xc7z020clg484-1" 4 | } 5 | 6 | if { ![info exists ::env(XILINX_BOARD)] } { 7 | set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c" 8 | } 9 | 10 | set partNumber $::env(XILINX_PART) 11 | set boardName $::env(XILINX_BOARD) 12 | 13 | create_project xilinx_mem_32768x32_dp . -part $partNumber 14 | set_property board $boardName [current_project] 15 | create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_32768x32_dp 16 | set_property -dict [list CONFIG.Memory_Type {True_Dual_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {32768} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Primitives {false} CONFIG.Register_PortB_Output_of_Memory_Core {false} CONFIG.Use_RSTA_Pin {true} CONFIG.Use_RSTB_Pin {true}] [get_ips xilinx_mem_32768x32_dp] 17 | generate_target all [get_files ./xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp.xci] 18 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_mem_32768x32_dp.srcs/sources_1/ip/xilinx_mem_32768x32_dp/xilinx_mem_32768x32_dp.xci] 19 | launch_run -jobs 8 xilinx_mem_32768x32_dp_synth_1 20 | wait_on_run xilinx_mem_32768x32_dp_synth_1 21 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_8192x32/.gitignore: -------------------------------------------------------------------------------- 1 | ip/ 2 | vivado.jou 3 | vivado.log 4 | vivado*.backup.jou 5 | vivado*.backup.log 6 | *.cache/ 7 | *.hw/ 8 | *.runs/ 9 | *.srcs/ 10 | *.xpr 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_8192x32/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=xilinx_mem_8192x32 2 | 3 | all: 4 | vivado -mode batch -source tcl/run.tcl 5 | mkdir -p ip 6 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}_stub.v ./ip 7 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.xci ./ip 8 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.veo ./ip 9 | cp ${PROJECT}.srcs/sources_1/ip/${PROJECT}/${PROJECT}.dcp ./ip 10 | 11 | gui: 12 | vivado -mode gui -source tcl/run.tcl & 13 | 14 | clean: 15 | rm -rf ip/* 16 | mkdir -p ip 17 | rm -rf ${PROJECT}.xpr 18 | rm -rf ${PROJECT}.hw 19 | rm -rf ${PROJECT}.data 20 | rm -rf ${PROJECT}.runs 21 | rm -rf ${PROJECT}.srcs 22 | rm -rf ${PROJECT}.cache 23 | rm -rf component.xml 24 | rm -rf vivado*.jou 25 | rm -rf vivado*.log 26 | rm -rf vivado*.str 27 | rm -rf xgui 28 | 29 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/ips/xilinx_mem_8192x32/tcl/run.tcl: -------------------------------------------------------------------------------- 1 | 2 | if { ![info exists ::env(XILINX_PART)] } { 3 | set ::env(XILINX_PART) "xc7z020clg484-1" 4 | } 5 | 6 | if { ![info exists ::env(XILINX_BOARD)] } { 7 | set ::env(XILINX_BOARD) "em.avnet.com:zynq:zed:c" 8 | } 9 | 10 | set partNumber $::env(XILINX_PART) 11 | set boardName $::env(XILINX_BOARD) 12 | 13 | create_project xilinx_mem_8192x32 . -part $partNumber 14 | set_property board $boardName [current_project] 15 | create_ip -name blk_mem_gen -vendor xilinx.com -library ip -module_name xilinx_mem_8192x32 16 | set_property -dict [list CONFIG.Memory_Type {Single_Port_RAM} CONFIG.Use_Byte_Write_Enable {true} CONFIG.Byte_Size {8} CONFIG.Write_Width_A {32} CONFIG.Write_Depth_A {8192} CONFIG.Register_PortA_Output_of_Memory_Primitives {false} CONFIG.Use_RSTA_Pin {true}] [get_ips xilinx_mem_8192x32] 17 | generate_target all [get_files ./xilinx_mem_8192x32.srcs/sources_1/ip/xilinx_mem_8192x32/xilinx_mem_8192x32.xci] 18 | create_ip_run [get_files -of_objects [get_fileset sources_1] ./xilinx_mem_8192x32.srcs/sources_1/ip/xilinx_mem_8192x32/xilinx_mem_8192x32.xci] 19 | launch_run -jobs 8 xilinx_mem_8192x32_synth_1 20 | wait_on_run xilinx_mem_8192x32_synth_1 21 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpemu/.gitignore: -------------------------------------------------------------------------------- 1 | ip/ 2 | vivado.jou 3 | vivado.log 4 | vivado*.backup.jou 5 | vivado*.backup.log 6 | *.cache/ 7 | *.hw/ 8 | *.runs/ 9 | *.srcs/ 10 | *.xpr 11 | *.hwdef 12 | *.txt 13 | .Xil 14 | pulpemu_top.bit -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpemu/Makefile: -------------------------------------------------------------------------------- 1 | PROJECT:=pulpemu 2 | 3 | all: synth 4 | 5 | synth: 6 | vivado -mode batch -source tcl/run.tcl 7 | cp pulpemu.runs/impl_1/pulpemu_top.bit pulpemu_top.bit 8 | 9 | impl: 10 | rm -rf .Xil 11 | vivado -mode batch -source tcl/impl.tcl 12 | cp pulpemu_top.runs/impl_1/pulpemu_top.bit . 13 | cp pulpemu_top.runs/impl_1/*.dcp . 14 | 15 | gui-synth: 16 | vivado -mode gui -source tcl/run.tcl & 17 | 18 | gui-impl: 19 | vivado -mode gui -source tcl/impl.tcl & 20 | 21 | continue: 22 | vivado -mode gui pulpemu_top.xpr 23 | 24 | clean-impl: 25 | rm -rf pulpemu_top* 26 | 27 | clean: 28 | rm -rf ${PROJECT}.hw 29 | rm -rf ${PROJECT}.xpr 30 | rm -rf ${PROJECT}.data 31 | rm -rf ${PROJECT}.runs 32 | rm -rf ${PROJECT}.srcs 33 | rm -rf ${PROJECT}.sim 34 | rm -rf ${PROJECT}.sdk 35 | rm -rf ${PROJECT}.cache 36 | rm -rf ${PROJECT}.ioplanning 37 | rm -rf ${PROJECT}.hwdef 38 | rm -rf *.log 39 | rm -rf ulpsoc.txt 40 | rm -rf ulpcluster.txt 41 | rm -rf component.xml 42 | rm -rf vivado* 43 | rm -rf xgui 44 | rm -rf .Xil 45 | rm -rf ps_clock* 46 | rm -rf pulpemu_top* 47 | rm -rf pulpemu.edf 48 | 49 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpino/.gitignore: -------------------------------------------------------------------------------- 1 | pulpino.cache/ 2 | pulpino.edf 3 | pulpino.hw/ 4 | pulpino.runs/ 5 | pulpino.xpr 6 | pulpino_funcsim.v 7 | pulpino_stub.v 8 | vivado.jou 9 | vivado.log 10 | reports -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpino/Makefile: -------------------------------------------------------------------------------- 1 | NAME:=RISCY 2 | PROJECT:=pulpino 3 | 4 | all: 5 | vivado -mode batch -source tcl/run.tcl 6 | # ./postsynth_names.py 7 | 8 | gui: 9 | vivado -mode gui -source tcl/run.tcl & 10 | 11 | clean: 12 | rm -rf ${PROJECT}.xpr 13 | rm -rf ${PROJECT}.data 14 | rm -rf ${PROJECT}.runs 15 | rm -rf ${PROJECT}.srcs 16 | rm -rf ${PROJECT}.sim 17 | rm -rf ${PROJECT}.cache 18 | rm -rf ${PROJECT}.ioplanning 19 | rm -rf ${PROJECT}.hw 20 | rm -rf component.xml 21 | rm -rf vivado* 22 | rm -rf .Xil 23 | rm -rf xgui 24 | rm -rf ${PROJECT}.edn 25 | rm -rf ${PROJECT}_stub.v 26 | rm -rf ${PROJECT}_funcsim.v 27 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpino/constraints.xdc: -------------------------------------------------------------------------------- 1 | create_clock -period 50.000 -name clk [get_nets {clk}] 2 | create_clock -period 40.000 -name spi_sck [get_nets {spi_clk_i}] 3 | create_clock -period 40.000 -name tck [get_nets {tck_i}] 4 | 5 | # define false paths between all clocks 6 | set_clock_groups -asynchronous \ 7 | -group { clk } \ 8 | -group { spi_sck } \ 9 | -group { tck } 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpino/tcl/.gitignore: -------------------------------------------------------------------------------- 1 | ips_add_files.tcl 2 | ips_inc_dirs.tcl 3 | ips_src_files.tcl -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/pulpino/tcl/src_files.tcl: -------------------------------------------------------------------------------- 1 | set RTL ../../rtl 2 | set IPS ../../ips 3 | set FPGA_IPS ../ips 4 | set FPGA_RTL ../rtl 5 | 6 | # components 7 | set SRC_COMPONENTS " \ 8 | $RTL/components/pulp_clock_gating.sv \ 9 | $RTL/components/cluster_clock_gating.sv \ 10 | $RTL/components/cluster_clock_inverter.sv \ 11 | $RTL/components/cluster_clock_mux2.sv \ 12 | $RTL/components/rstgen.sv \ 13 | $RTL/components/pulp_clock_inverter.sv \ 14 | $RTL/components/pulp_clock_mux2.sv \ 15 | $RTL/components/generic_fifo.sv \ 16 | $RTL/components/sp_ram.sv \ 17 | " 18 | 19 | # pulpino 20 | set SRC_PULPINO " \ 21 | $RTL/axi2apb_wrap.sv \ 22 | $RTL/periph_bus_wrap.sv \ 23 | $RTL/core2axi_wrap.sv \ 24 | $RTL/axi_node_intf_wrap.sv \ 25 | $RTL/axi_spi_slave_wrap.sv \ 26 | $RTL/axi_slice_wrap.sv \ 27 | $RTL/axi_mem_if_SP_wrap.sv \ 28 | $RTL/core_region.sv \ 29 | $RTL/instr_ram_wrap.sv \ 30 | $RTL/sp_ram_wrap.sv \ 31 | $RTL/boot_code.sv \ 32 | $RTL/boot_rom_wrap.sv \ 33 | $RTL/peripherals.sv \ 34 | $RTL/ram_mux.sv \ 35 | $RTL/pulpino_top.sv \ 36 | $RTL/clk_rst_gen.sv \ 37 | $FPGA_RTL/pulpino_wrap.v \ 38 | " 39 | 40 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/.gitignore: -------------------------------------------------------------------------------- 1 | linux-xlnx 2 | sd_image 3 | u-boot-xlnx 4 | buildroot 5 | hsi/fsbl/ 6 | hsi/ps7_bd.tcl 7 | hsi/ps7_init.c 8 | hsi/ps7_init.h 9 | hsi/ps7_init.html 10 | hsi/ps7_init.tcl 11 | hsi/ps7_init_gpl.c 12 | hsi/ps7_init_gpl.h 13 | hsi/hsi.jou 14 | hsi/hsi.log 15 | hsi/pulpemu_top.bit 16 | hsi/pulpemu_top.sysdef -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/apps/gpio_access/Makefile: -------------------------------------------------------------------------------- 1 | CC=arm-xilinx-linux-gnueabi-gcc 2 | 3 | 4 | all: gpio_access 5 | 6 | gpio_access: main.c 7 | $(CC) -o $@ $^ 8 | 9 | 10 | push: gpio_access 11 | scp ./gpio_access root@$(FPGA_HOSTNAME):/root/ 12 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/apps/spiload/Makefile: -------------------------------------------------------------------------------- 1 | CC = arm-xilinx-linux-gnueabi-gcc 2 | CFLAGS = 3 | 4 | ifeq ($(BOARD),zybo) 5 | CFLAGS += -DZYBO 6 | endif 7 | 8 | all: spiload 9 | 10 | spiload: main.c arg_parsing.c console_read.c 11 | $(CC) $(CFLAGS) -pthread -o $@ $^ 12 | 13 | push: spiload 14 | scp ./spiload root@$(FPGA_HOSTNAME):/root/ 15 | 16 | clean: 17 | @rm -f ./*.o spiload 18 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/apps/spiload/spiloader.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #ifndef SPILOADER_H 12 | #define SPILOADER_H 13 | 14 | #include 15 | 16 | static inline struct timespec timespec_sub(struct timespec lhs, struct timespec rhs) { 17 | struct timespec ret; 18 | 19 | if (rhs.tv_nsec > lhs.tv_nsec) { 20 | ret.tv_sec = lhs.tv_sec - 1 - rhs.tv_sec; 21 | ret.tv_nsec = 1000000000 + lhs.tv_nsec - rhs.tv_nsec; 22 | } 23 | else 24 | { 25 | ret.tv_sec = lhs.tv_sec - rhs.tv_sec; 26 | ret.tv_nsec = lhs.tv_nsec - rhs.tv_nsec; 27 | } 28 | 29 | return ret; 30 | } 31 | 32 | struct cmd_arguments_t { 33 | char* stim; 34 | unsigned int timeout; 35 | }; 36 | 37 | void* console_thread(void* ptr); 38 | void console_thread_stop(); 39 | 40 | #endif 41 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/boot.bif: -------------------------------------------------------------------------------- 1 | the_ROM_image: 2 | { 3 | [bootloader]./sd_image/fsbl.elf 4 | ./sd_image/pulpemu_top.bit 5 | ./sd_image/u-boot.elf 6 | } 7 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/device-tree/skeleton.dtsi: -------------------------------------------------------------------------------- 1 | /* 2 | * Skeleton device tree; the bare minimum needed to boot; just include and 3 | * add a compatible value. The bootloader will typically populate the memory 4 | * node. 5 | */ 6 | 7 | / { 8 | #address-cells = <1>; 9 | #size-cells = <1>; 10 | chosen { }; 11 | aliases { }; 12 | memory { device_type = "memory"; reg = <0 0>; }; 13 | }; 14 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/device-tree/zybo/pl.dtsi: -------------------------------------------------------------------------------- 1 | ../pl.dtsi -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/device-tree/zybo/system.dts: -------------------------------------------------------------------------------- 1 | /* 2 | * CAUTION: This file is automatically generated by Xilinx. 3 | * Version: 4 | * Today is: Sat Dec 13 21:06:50 2014 5 | */ 6 | 7 | /dts-v1/; 8 | /include/ "ps.dtsi" 9 | /include/ "pl.dtsi" 10 | /{ 11 | chosen { 12 | bootargs = "console=ttyPS0,115200 ip=on root=/dev/mmcblk0p2 rw earlyprintk"; 13 | linux,stdout-path = &ps7_uart_1; 14 | } ; 15 | aliases { 16 | ethernet0 = &ps7_ethernet_0; 17 | i2c0 = &ps7_i2c_0; 18 | serial0 = &ps7_uart_1; 19 | spi0 = &ps7_qspi_0; 20 | } ; 21 | ps7_ddr_0: memory@00100000 { 22 | device_type = "memory"; 23 | reg = <0x0 0x20000000>; 24 | } ; 25 | }; 26 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/hsi/Makefile: -------------------------------------------------------------------------------- 1 | 2 | fsbl/executable.elf: 3 | hsi -mode tcl -source ./fsbl.tcl 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/hsi/fsbl.tcl: -------------------------------------------------------------------------------- 1 | open_hw_design ./pulpemu_top.sysdef 2 | generate_app -hw pulpemu_top -os standalone -proc ps7_cortexa9_0 -app zynq_fsbl -compile -sw fsbl -dir ./fsbl 3 | exit 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/fpga/sw/u-boot-xlnx-def-env.patch: -------------------------------------------------------------------------------- 1 | diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h 2 | index 6c37909..2ac5005 100644 3 | --- a/include/configs/zynq-common.h 4 | +++ b/include/configs/zynq-common.h 5 | @@ -240,7 +240,6 @@ 6 | 7 | /* Default environment */ 8 | #define CONFIG_EXTRA_ENV_SETTINGS \ 9 | - "ethaddr=00:0a:35:00:01:22\0" \ 10 | "kernel_image=uImage\0" \ 11 | "kernel_load_address=0x2080000\0" \ 12 | "ramdisk_image=uramdisk.image.gz\0" \ 13 | @@ -292,8 +291,7 @@ 14 | "echo Copying Linux from SD to RAM... && " \ 15 | "load mmc 0 ${kernel_load_address} ${kernel_image} && " \ 16 | "load mmc 0 ${devicetree_load_address} ${devicetree_image} && " \ 17 | - "load mmc 0 ${ramdisk_load_address} ${ramdisk_image} && " \ 18 | - "bootm ${kernel_load_address} ${ramdisk_load_address} ${devicetree_load_address}; " \ 19 | + "bootm ${kernel_load_address} - ${devicetree_load_address}; " \ 20 | "fi\0" \ 21 | "usbboot=if usb start; then " \ 22 | "run uenvboot; " \ 23 | @@ -338,8 +336,6 @@ 24 | DFU_ALT_INFO 25 | 26 | /* Default environment */ 27 | -#define CONFIG_IPADDR 10.10.70.102 28 | -#define CONFIG_SERVERIP 10.10.70.101 29 | 30 | /* default boot is according to the bootmode switch settings */ 31 | #if defined(CONFIG_CMD_ZYNQ_RSA) 32 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/ips/.gitignore: -------------------------------------------------------------------------------- 1 | adv_dbg_if 2 | apb 3 | axi 4 | riscv 5 | zero-riscy 6 | or10n 7 | fpu -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/boot_rom_wrap.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | `include "config.sv" 13 | 14 | module boot_rom_wrap 15 | #( 16 | parameter ADDR_WIDTH = `ROM_ADDR_WIDTH, 17 | parameter DATA_WIDTH = 32 18 | )( 19 | // Clock and Reset 20 | input logic clk, 21 | input logic rst_n, 22 | input logic en_i, 23 | input logic [ADDR_WIDTH-1:0] addr_i, 24 | output logic [DATA_WIDTH-1:0] rdata_o 25 | ); 26 | 27 | boot_code 28 | boot_code_i 29 | ( 30 | .CLK ( clk ), 31 | .RSTN ( rst_n ), 32 | .CSN ( ~en_i ), 33 | .A ( addr_i[ADDR_WIDTH-1:2] ), 34 | .Q ( rdata_o ) 35 | ); 36 | endmodule 37 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/components/cluster_clock_gating.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module cluster_clock_gating 12 | ( 13 | input logic clk_i, 14 | input logic en_i, 15 | input logic test_en_i, 16 | output logic clk_o 17 | ); 18 | 19 | `ifdef PULP_FPGA_EMUL 20 | // no clock gates in FPGA flow 21 | assign clk_o = clk_i; 22 | `else 23 | logic clk_en; 24 | 25 | always_latch 26 | begin 27 | if (clk_i == 1'b0) 28 | clk_en <= en_i | test_en_i; 29 | end 30 | 31 | assign clk_o = clk_i & clk_en; 32 | `endif 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/components/cluster_clock_inverter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module cluster_clock_inverter 12 | ( 13 | input logic clk_i, 14 | output logic clk_o 15 | ); 16 | 17 | assign clk_o = ~clk_i; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/components/cluster_clock_mux2.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module cluster_clock_mux2 12 | ( 13 | input logic clk0_i, 14 | input logic clk1_i, 15 | input logic clk_sel_i, 16 | output logic clk_o 17 | ); 18 | 19 | always_comb 20 | begin 21 | if (clk_sel_i == 1'b0) 22 | clk_o = clk0_i; 23 | else 24 | clk_o = clk1_i; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/components/pulp_clock_gating.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module pulp_clock_gating 12 | ( 13 | input logic clk_i, 14 | input logic en_i, 15 | input logic test_en_i, 16 | output logic clk_o 17 | ); 18 | 19 | `ifdef PULP_FPGA_EMUL 20 | // no clock gates in FPGA flow 21 | assign clk_o = clk_i; 22 | `else 23 | logic clk_en; 24 | 25 | always_latch 26 | begin 27 | if (clk_i == 1'b0) 28 | clk_en <= en_i | test_en_i; 29 | end 30 | 31 | assign clk_o = clk_i & clk_en; 32 | `endif 33 | 34 | endmodule 35 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/components/pulp_clock_inverter.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module pulp_clock_inverter 12 | ( 13 | input logic clk_i, 14 | output logic clk_o 15 | ); 16 | 17 | assign clk_o = ~clk_i; 18 | 19 | endmodule 20 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/components/pulp_clock_mux2.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | module pulp_clock_mux2 12 | ( 13 | input logic clk0_i, 14 | input logic clk1_i, 15 | input logic clk_sel_i, 16 | output logic clk_o 17 | ); 18 | 19 | always_comb 20 | begin 21 | if (clk_sel_i == 1'b0) 22 | clk_o = clk0_i; 23 | else 24 | clk_o = clk1_i; 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/includes/apu_defines.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | //`define SHARED_APU 12 | `define APU -------------------------------------------------------------------------------- /Microcontroller/FPGA/rtl/includes/config.sv: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | `ifndef CONFIG_SV 12 | `define CONFIG_SV 13 | `define RISCV 14 | // always define ASIC when we do a synthesis run 15 | `ifndef PULP_FPGA_EMUL 16 | `ifdef SYNTHESIS 17 | `define ASIC 18 | `endif 19 | `endif 20 | 21 | // data and instruction RAM address and word width 22 | `define ROM_ADDR_WIDTH 12 23 | `define ROM_START_ADDR 32'h8000 24 | 25 | // Simulation only stuff 26 | `ifndef SYNTHESIS 27 | //`define DATA_STALL_RANDOM 28 | //`define INSTR_STALL_RANDOM 29 | `endif 30 | 31 | `endif 32 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/sw/.DS_Store -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/sw/apps/.DS_Store -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/.gitignore: -------------------------------------------------------------------------------- 1 | scratch 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | add_subdirectory(GPIO_test) 3 | add_subdirectory(int_test) 4 | add_subdirectory(timer_test) 5 | add_subdirectory(PWM_test) 6 | add_subdirectory(UART_test) 7 | add_subdirectory(PulseIn_test) 8 | add_subdirectory(shift_test) 9 | add_subdirectory(wire_test) 10 | add_subdirectory(SPI_test) 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/GPIO_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(GPIO_test GPIO_test.cpp LABELS "arduino" TB_TEST "ARDUINO_GPIO") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/PWM_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(PWM_test PWM_test.cpp LABELS "arduino") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/PWM_test/PWM_test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include 12 | 13 | 14 | void setup(){ 15 | pinMode(0,OUTPUT); 16 | pinMode(1,OUTPUT); 17 | pinMode(2,OUTPUT); 18 | } 19 | 20 | 21 | void loop(){ 22 | digitalWrite(0,HIGH); 23 | analogWrite(1,50); 24 | analogWrite(2,200); 25 | delay(20); 26 | analogWrite(0,125); 27 | analogWrite(1,300); 28 | digitalWrite(2,LOW); 29 | delay(20); 30 | exit(0); //to end simulation properly 31 | } 32 | 33 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/PulseIn_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(PulseIn_test PulseIn_test.cpp LABELS "arduino" TB_TEST "ARDUINO_PULSEIN") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/PulseIn_test/PulseIn_test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include 12 | 13 | unsigned int x; 14 | 15 | void setup() 16 | { 17 | Serial.begin(781250); 18 | 19 | 20 | pinMode(4,INPUT); 21 | 22 | pinMode(0,OUTPUT); //used to intiate test bench stimulus (for simulation only) 23 | digitalWrite(0,HIGH); 24 | 25 | } 26 | 27 | void loop() 28 | { 29 | x= pulseIn(4,1); 30 | Serial.print("Calculated\t"); 31 | Serial.print(x); 32 | Serial.print("\texpected\t"); 33 | Serial.println("500"); 34 | 35 | 36 | x= pulseInLong(4,1); 37 | Serial.print("Calculated\t"); 38 | Serial.print(x); 39 | Serial.print("\texpected\t"); 40 | Serial.println("500"); 41 | 42 | delay(1); 43 | 44 | exit(0); //to end simulation properly 45 | } 46 | 47 | 48 | 49 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/SPI_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(SPI_test SPI_test.cpp LABELS "arduino" TB_TEST "ARDUINO_SPI") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/SPI_test/SPI_test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include "SPI.h" 12 | 13 | #include 14 | 15 | 16 | int y; 17 | 18 | void setup() 19 | { 20 | Serial.begin(781250); 21 | SPI.begin(); 22 | } 23 | 24 | void loop() 25 | { 26 | SPISettings mySettings(4000000, MSBFIRST, SPI_MODE0); 27 | SPI.beginTransaction(mySettings); 28 | y=SPI.transfer(0xA1); 29 | Serial.print("Received="); 30 | Serial.print(y); 31 | Serial.print("\tExpected="); 32 | Serial.println("28"); 33 | SPI.endTransaction(); 34 | delay(1); 35 | 36 | if (y == 28) { 37 | Serial.print("Test Success\n"); 38 | delay(1); 39 | exit(0); 40 | } 41 | else { 42 | Serial.print("Test Fail\n"); 43 | delay(1); 44 | exit(1); 45 | } 46 | } 47 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/UART_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(UART_test UART_test.cpp LABELS "arduino" TB_TEST "ARDUINO_UART") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/int_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(int_test int_test.cpp LABELS "arduino" TB_TEST "ARDUINO_INT") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/shift_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(shift_test shift_test.cpp LABELS "arduino" TB_TEST "ARDUINO_SHIFT") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/shift_test/shift_test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include 12 | 13 | volatile uint8_t x; 14 | 15 | void setup() 16 | { 17 | Serial.begin(781250); 18 | pinMode(0,OUTPUT); //used to intiate test bench stimulus (for simulation only) 19 | pinMode(1,OUTPUT); 20 | pinMode(2,OUTPUT); 21 | pinMode(3,INPUT); 22 | pinMode(4,OUTPUT); 23 | } 24 | 25 | void loop() 26 | { 27 | shiftOut(1, 2, 0, 5); 28 | digitalWrite(0,HIGH); 29 | x=shiftIn(3, 4, 0); 30 | Serial.print("Received\t"); 31 | Serial.print(x); 32 | Serial.print("\texpected\t"); 33 | Serial.println("147"); 34 | 35 | delay(1); 36 | 37 | exit(0); //to end simulation properly 38 | 39 | } 40 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/timer_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(timer_test timer_test.cpp LABELS "arduino") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/timer_test/timer_test.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include 12 | 13 | 14 | 15 | void setup() { 16 | // initialize digital pin 13 as an output. 17 | pinMode(13, OUTPUT); 18 | } 19 | 20 | // the loop function runs over and over again forever 21 | void loop() { 22 | digitalWrite(13, HIGH); // turn the LED on (HIGH is the voltage level) 23 | delay(3); 24 | digitalWrite(13, LOW); // turn the LED off by making the voltage LOW 25 | delay(3); 26 | 27 | exit(0); //to end simulation properly 28 | } 29 | 30 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/Arduino_tests/wire_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(wire_test wire_test.cpp LABELS "arduino") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | # hack to make sure the perfbench.* libraries compile 2 | include_directories( 3 | ${CMAKE_SOURCE_DIR}/libs/bench_lib/inc 4 | ${CMAKE_SOURCE_DIR}/libs/stdio_lib/inc 5 | ${CMAKE_SOURCE_DIR}/libs/string_lib/inc 6 | ${CMAKE_SOURCE_DIR}/libs/sys_lib/inc 7 | . 8 | ) 9 | 10 | 11 | set(PERFBENCH_CORE_SOURCES main.c) 12 | set(PERFBENCH_EXTRAS_SOURCES crc32.c) 13 | 14 | add_library(perfbench.core STATIC ${PERFBENCH_CORE_SOURCES}) 15 | add_library(perfbench.extras STATIC ${PERFBENCH_EXTRAS_SOURCES}) 16 | 17 | 18 | # vlsi soc paper compile flags: 19 | # base "-mno-hwlp -mno-idxls -mno-rrls -mno-lv32 -mno_unalign-ls -mno-mac3" 20 | # full "-midxls -mrrls -mhwlp -mmax-hwloops=2 -mlv32 -munalign-ls -mmac3" 21 | # note: base still includes min/max/cnt instructions (-mno-crtl missing) 22 | 23 | # TODO: -fno-builtin was used to build, check if needed 24 | 25 | 26 | add_subdirectory(conv2d) 27 | add_subdirectory(fdctfst) 28 | add_subdirectory(ipm) 29 | #add_subdirectory(matmul) 30 | add_subdirectory(fir) 31 | add_subdirectory(fft) 32 | add_subdirectory(aes_cbc) 33 | add_subdirectory(keccak) 34 | add_subdirectory(sha) 35 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/aes_cbc/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.aes_cbc_SOURCES aes_cbc.c aes_cbc_test.c) 2 | add_application(perfbench.aes_cbc "${perfbench.aes_cbc_SOURCES}" 3 | LABELS "perfbench" LIBS perfbench.core) 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/conv2d/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.conv2d_SOURCES conv2d.c conv2d_test.c) 2 | add_application(perfbench.conv2d "${perfbench.conv2d_SOURCES}" 3 | LABELS "perfbench" LIBS perfbench.core) 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/conv2d/conv2d.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #include "common.h" 11 | 12 | void conv2d(int16_t *restrict mat, int16_t * restrict res, 13 | const int16_t * restrict coeffs, 14 | int W, int H, int K, uint16_t scf) { 15 | int R = K >> 1; 16 | int index = R * W; 17 | 18 | for(int j = R; j < H - R; j++) { 19 | for(int i = R; i < W - R; i++) { 20 | int index2 = index - R * W; 21 | int c = 0; 22 | int val = 0; 23 | for(int y = -R; y <= R; ++y) { 24 | val += coeffs[c++] * mat[index2 + i - 2]; 25 | val += coeffs[c++] * mat[index2 + i -1]; 26 | val += coeffs[c++] * mat[index2 + i]; 27 | val += coeffs[c++] * mat[index2 + i + 1]; 28 | val += coeffs[c++] * mat[index2 + i + 2]; 29 | index2 += W; 30 | } 31 | res[index+i] = val >> scf; 32 | } 33 | index += W; 34 | } 35 | } 36 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/fdctfst/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.fdctfst_SOURCES fdctfst.c fdctfst_test.c) 2 | add_application(perfbench.fdctfst "${perfbench.fdctfst_SOURCES}" 3 | LABELS "perfbench" LIBS perfbench.core) 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/fft/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.fft_SOURCES fft.c fft_test.c) 2 | add_application(perfbench.fft "${perfbench.fft_SOURCES}" 3 | LABELS "perfbench" LIBS "perfbench.core") 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/fir/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(libs perfbench.core perfbench.extras) 2 | set(perfbench.fir_SOURCES fir.c fir_test.c) 3 | 4 | add_application(perfbench.fir "${perfbench.fir_SOURCES}" 5 | LABELS "perfbench" LIBS "${libs}") 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/fir/fir.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #include "../common.h" 11 | 12 | void fir(const int16_t *arr, const int16_t *coeff, int16_t *output, 13 | unsigned arr_length, unsigned coeff_len) { 14 | 15 | for (unsigned i = 0; i < arr_length - coeff_len; ++i) { 16 | uint16_t sum = 0; 17 | for (unsigned j = 0; j < coeff_len; ++j) { 18 | sum += arr[i+j] * coeff[j]; 19 | } 20 | 21 | output[i] = sum; 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/ipm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.ipm_SOURCES ipm.c ipm_test.c) 2 | add_application(perfbench.ipm "${perfbench.ipm_SOURCES}" 3 | LABELS "perfbench" LIBS perfbench.core) 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/ipm/ipm.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef IPM_H 11 | 12 | #define N 5 13 | #define M 3 14 | 15 | #endif 16 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/keccak/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.keccak_SOURCES keccak.c keccak_test.c) 2 | add_application(perfbench.keccak "${perfbench.keccak_SOURCES}" 3 | LABELS "perfbench" LIBS "perfbench.core") 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/main.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | #include 13 | #include "timer.h" 14 | #include "utils.h" 15 | 16 | #include "bench.h" 17 | 18 | #define NUM_ITER 5 19 | static unsigned samples[NUM_ITER]; 20 | 21 | extern void test_setup(); 22 | extern void test_clear(); 23 | extern void test_run(int); 24 | extern int test_check(); 25 | 26 | int main() { 27 | 28 | test_setup(); 29 | perf_start(); 30 | 31 | for (int i = 0; i < NUM_ITER; ++i) { 32 | test_clear(); 33 | 34 | reset_timer(); 35 | start_timer(); 36 | 37 | test_run(i); 38 | 39 | stop_timer(); 40 | 41 | samples[i] = get_time(); 42 | } 43 | 44 | perf_stop(); 45 | int check = test_check(); 46 | 47 | printf("Correct: %d\n", check); 48 | for (int i = 0; i < NUM_ITER; ++i) 49 | printf("TS[%d]: %d\n", i, samples[i]); 50 | 51 | perf_print_all(); 52 | 53 | return 0; 54 | } 55 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/matmul/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.matmul32_SOURCES matmul32.cpp matmul32_test.c) 2 | set(libs perfbench.core perfbench.extras) 3 | 4 | add_application(perfbench.matmul32 "${perfbench.matmul32_SOURCES}" 5 | SUBDIR matmul32 LABELS "perfbench" 6 | LIBS "${libs}") 7 | add_application(perfbench.matmul32_t "${perfbench.matmul32_SOURCES}" 8 | SUBDIR matmul32_t LABELS "perfbench" 9 | LIBS "${libs}" FLAGS "-DTRANSPOSE_B") 10 | 11 | 12 | set(perfbench.matmul16_SOURCES matmul16.cpp matmul16_test.c) 13 | 14 | add_application(perfbench.matmul16 "${perfbench.matmul16_SOURCES}" 15 | SUBDIR matmul16 LABELS "perfbench" 16 | LIBS "${libs}") 17 | add_application(perfbench.matmul16_t "${perfbench.matmul16_SOURCES}" 18 | SUBDIR matmul16_t LABELS "perfbench" 19 | LIBS "${libs}" FLAGS "-DTRANSPOSE_B") 20 | 21 | 22 | set(perfbench.matmul8_SOURCES matmul8.cpp matmul8_test.c) 23 | 24 | add_application(perfbench.matmul8 "${perfbench.matmul8_SOURCES}" 25 | SUBDIR matmul8 LABELS "perfbench" 26 | LIBS "${libs}") 27 | add_application(perfbench.matmul8_t "${perfbench.matmul8_SOURCES}" 28 | SUBDIR matmul8_t LABELS "perfbench" 29 | LIBS "${libs}" FLAGS "-DTRANSPOSE_B") 30 | 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/matmul/matmul16.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #include "matmul_impl.h" 11 | #include "common.h" 12 | #include "matmul_impl.h" 13 | 14 | typedef uint16_t elem_t; 15 | 16 | #ifndef TRANSPOSE_B 17 | extern "C" 18 | void matmul(const elem_t *__restrict__ A, const elem_t *__restrict__ B, 19 | elem_t *__restrict__ C, 20 | unsigned N, unsigned L, unsigned M) { 21 | matmul(A, B, C, N, L, M); 22 | } 23 | #else 24 | extern "C" 25 | void matmul(const elem_t *__restrict__ A, const elem_t *__restrict__ B, 26 | elem_t *__restrict__ Bt, elem_t *__restrict__ C, 27 | unsigned N, unsigned L, unsigned M) { 28 | matmul_t(A, B, Bt, C, N, L, M); 29 | } 30 | #endif 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/matmul/matmul32.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #include "matmul_impl.h" 11 | #include "common.h" 12 | #include "matmul_impl.h" 13 | 14 | typedef uint32_t elem_t; 15 | 16 | #ifndef TRANSPOSE_B 17 | extern "C" 18 | void matmul(const elem_t * __restrict__ A, const elem_t * __restrict__ B, 19 | elem_t * __restrict__ C, 20 | unsigned N, unsigned L, unsigned M) { 21 | matmul(A, B, C, N, L, M); 22 | } 23 | #else 24 | extern "C" 25 | void matmul(const elem_t * __restrict__ A, const elem_t * __restrict__ B, 26 | elem_t * __restrict__ Bt, elem_t * __restrict__ C, 27 | unsigned N, unsigned L, unsigned M) { 28 | matmul_t(A, B, Bt, C, N, L, M); 29 | } 30 | #endif 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/matmul/matmul8.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #include "matmul_impl.h" 11 | #include "common.h" 12 | #include "matmul_impl.h" 13 | 14 | typedef uint8_t elem_t; 15 | 16 | #ifndef TRANSPOSE_B 17 | extern "C" 18 | void matmul(const elem_t * __restrict__ A, const elem_t * __restrict__ B, 19 | elem_t * __restrict__ C, 20 | unsigned N, unsigned L, unsigned M) { 21 | matmul(A, B, C, N, L, M); 22 | } 23 | #else 24 | extern "C" 25 | void matmul(const elem_t * __restrict__ A, const elem_t * __restrict__ B, 26 | elem_t * __restrict__ Bt, elem_t * __restrict__ C, 27 | unsigned N, unsigned L, unsigned M) { 28 | matmul_t(A, B, Bt, C, N, L, M); 29 | } 30 | #endif 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/sha/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(perfbench.sha_SOURCES sha.c sha_test.c) 2 | add_application(perfbench.sha "${perfbench.sha_SOURCES}" 3 | LABELS "perfbench" LIBS "perfbench.core") 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/sha/sha.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef SHA_H 11 | #define SHA_H 12 | 13 | #include 14 | 15 | /* NIST Secure Hash Algorithm */ 16 | /* heavily modified from Peter C. Gutmann's implementation */ 17 | 18 | /* Useful defines & typedefs */ 19 | 20 | #define SHA_BLOCKSIZE 64 21 | #define SHA_DIGESTSIZE 20 22 | 23 | typedef struct { 24 | uint32_t digest[5]; /* message digest */ 25 | uint32_t count_lo, count_hi; /* 64-bit bit count */ 26 | uint32_t data[16]; /* SHA data buffer */ 27 | } SHA_INFO; 28 | 29 | void sha_init(SHA_INFO *); 30 | void sha_update(SHA_INFO *, uint8_t *, int); 31 | void sha_final(SHA_INFO *); 32 | 33 | void sha_stream(SHA_INFO *); 34 | void sha_print(SHA_INFO *); 35 | 36 | #endif /* SHA_H */ 37 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/bench/sha/sha_test.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #include "sha.h" 11 | #include "common.h" 12 | 13 | SHA_INFO sha_info __sram; 14 | uint8_t data[256+16] __sram; 15 | 16 | void test_setup() { 17 | for (int i = 0; i != 256; ++i) 18 | data[i] = i; 19 | } 20 | 21 | void test_clear() {} 22 | 23 | void test_run() { 24 | sha_init(&sha_info); 25 | for(int n = 0; n < 4; ++n) { 26 | sha_update(&sha_info, data + 4 * n, 256); 27 | } 28 | sha_final(&sha_info); 29 | } 30 | 31 | int test_check() { 32 | uint32_t check_digest[5] = { 33 | 0x6df33e84, 34 | 0xbfb762a3, 35 | 0xd55acf9e, 36 | 0xf2dd5e59, 37 | 0xf4d61769 38 | }; 39 | for (int i = 0; i < 5; i++) { 40 | if (sha_info.digest[i] != check_digest[i]) 41 | return 0; 42 | } 43 | return 1; 44 | } 45 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/boot_code/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_boot_code(boot_code boot_code.c) 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/compressed/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | #set_source_files_properties(compressed.S PROPERTIES LANGUAGE C) 2 | set(SOURCES compressed.S main.c) 3 | 4 | add_application(compressed "${SOURCES}" FLAGS "-mrvc") 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/fpga/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/sw/apps/fpga/.DS_Store -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/fpga/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(fpga_test) 2 | add_subdirectory(gpio_demo) 3 | add_subdirectory(led_demo) 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/fpga/fpga_test/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(fpga_test main.c) 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/fpga/gpio_demo/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(gpio_demo main.c) 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/fpga/led_demo/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(led_demo main.c) 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/freertos/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FREERTOS_SOURCES main.c Source/list.c Source/queue.c Source/tasks.c Source/portable/GCC/RI5CY/port.c Source/portable/MemMang/heap_1.c) 2 | 3 | include_directories(. Source/portable/GCC/RI5CY Source/include) 4 | 5 | add_application(freertos "${FREERTOS_SOURCES}") 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/freertos/Source/include/stdint.readme: -------------------------------------------------------------------------------- 1 | 2 | #ifndef FREERTOS_STDINT 3 | #define FREERTOS_STDINT 4 | 5 | /******************************************************************************* 6 | * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions 7 | * necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be 8 | * built using compilers that do not provide their own stdint.h definition. 9 | * 10 | * To use this file: 11 | * 12 | * 1) Copy this file into the directory that contains your FreeRTOSConfig.h 13 | * header file, as that directory will already be in the compilers include 14 | * path. 15 | * 16 | * 2) Rename the copied file stdint.h. 17 | * 18 | */ 19 | 20 | typedef signed char int8_t; 21 | typedef unsigned char uint8_t; 22 | typedef short int16_t; 23 | typedef unsigned short uint16_t; 24 | typedef long int32_t; 25 | typedef unsigned long uint32_t; 26 | 27 | #endif /* FREERTOS_STDINT */ 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/freertos/Source/readme.txt: -------------------------------------------------------------------------------- 1 | Each real time kernel port consists of three files that contain the core kernel 2 | components and are common to every port, and one or more files that are 3 | specific to a particular microcontroller and or compiler. 4 | 5 | + The FreeRTOS/Source directory contains the three files that are common to 6 | every port - list.c, queue.c and tasks.c. The kernel is contained within these 7 | three files. croutine.c implements the optional co-routine functionality - which 8 | is normally only used on very memory limited systems. 9 | 10 | + The FreeRTOS/Source/Portable directory contains the files that are specific to 11 | a particular microcontroller and or compiler. 12 | 13 | + The FreeRTOS/Source/include directory contains the real time kernel header 14 | files. 15 | 16 | See the readme file in the FreeRTOS/Source/Portable directory for more 17 | information. -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/helloworld/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(helloworld helloworld.c) 2 | 3 | add_application(helloworldcpp helloworld.cpp SUBDIR "../helloworldcpp") 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/helloworld/helloworld.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | #include 13 | 14 | int main() 15 | { 16 | printf("Hello World!!!!!\n"); 17 | return 0; 18 | } 19 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/helloworld/helloworld.cpp: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | #include 13 | 14 | int main() 15 | { 16 | printf("Hello World!!!!!\n"); 17 | 18 | return 0; 19 | } 20 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | 2 | #add_subdirectory(testTimer) 3 | add_subdirectory(testInterrupt) 4 | add_subdirectory(testUART) 5 | add_subdirectory(testI2C) 6 | add_subdirectory(testSPIMaster) 7 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testGPIO/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testGPIO testGPIO.c) -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testGPIO/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/ref/common.mk 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testGPIO/testGPIO.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | #include "utils.h" 13 | #include "string_lib.h" 14 | #include "bar.h" 15 | #include "gpio.h" 16 | 17 | int main() 18 | { 19 | set_pin_function(PIN_MSPI_CSN1, FUNC_EXT2); 20 | if (get_pin_function(PIN_MSPI_CSN1) == FUNC_EXT2) { 21 | printf("Successfully enabled func 2 on PIN_MSPI_CSN1\n"); 22 | } else { 23 | printf("ERROR on enabling func 2 on PIN_MSPI_CSN1\n"); 24 | } 25 | 26 | set_pin_function(PIN_MSPI_CSN2, FUNC_GPIO); 27 | set_gpio_pin_direction(PIN_MSPI_CSN2, DIR_OUT); 28 | if (get_gpio_pin_direction(PIN_MSPI_CSN2) == DIR_OUT) { 29 | printf("Successfully set out dir on PIN_MSPI_CSN2\n"); 30 | } else { 31 | printf("ERROR on setting out dir on PIN_MSPI_CSN2\n"); 32 | } 33 | 34 | printf("Done!!!\n"); 35 | 36 | return 0; 37 | } 38 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testI2C/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testI2C testI2C.c LABELS "imperio_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testInterrupt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testInterrupt main.c LABELS "imperio_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testSPIMaster/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testSPIMaster testSPIMaster.c LABELS "imperio_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/imperio_tests/testUART/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testUART testUART.c LABELS "imperio_tests") 2 | 3 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories(ml_shared) 2 | 3 | add_subdirectory(mlAxpy) 4 | add_subdirectory(mlBilat) 5 | add_subdirectory(mlButter) 6 | add_subdirectory(mlDct) 7 | add_subdirectory(mlDist) 8 | add_subdirectory(mlDotp) 9 | add_subdirectory(mlGemm) 10 | add_subdirectory(mlGemv) 11 | add_subdirectory(mlGivens) 12 | add_subdirectory(mlGrad) 13 | add_subdirectory(mlGradDir) 14 | add_subdirectory(mlHomErr) 15 | add_subdirectory(mlHom) 16 | add_subdirectory(mlQr) 17 | add_subdirectory(mlSin) 18 | add_subdirectory(mlWdotp) 19 | add_subdirectory(mlChol) 20 | add_subdirectory(mlFir) 21 | add_subdirectory(mlRbf) 22 | add_subdirectory(mlSvd) 23 | add_subdirectory(mlLog) 24 | add_subdirectory(mlSchur) 25 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlAxpy/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlAxpy.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlAxpy "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlAxpy/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlAxpy 2 | PULP_APP_SRCS = mlAxpy.c 3 | 4 | #PULP_CFLAGS += -O3 -DFP_SW_EMUL 5 | #stackSize = 8192 6 | 7 | PULP_CFLAGS += -O3 8 | stackSize = 4096 9 | 10 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlAxpy/mlAxpy.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_AXPY_H__ 11 | #define __ML_AXPY_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | 25 | ///////////////////////////////////////////////////////// 26 | // main testing function 27 | ///////////////////////////////////////////////////////// 28 | int main(int argc, const char * const argv[]); 29 | 30 | 31 | 32 | #endif 33 | 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlAxpy/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlBilat/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlBilat.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlBilat "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlBilat/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlBilat 2 | PULP_APP_SRCS = mlBilat.c math_fns.c 3 | PULP_CFLAGS += -O3 -fno-tree-loop-distribute-patterns 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | 9 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlBilat/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlButter/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlButter.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlButter "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlButter/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlButter 2 | PULP_APP_SRCS = mlButter.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlButter/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlChol/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlChol.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlChol "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlChol/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlChol 2 | PULP_APP_SRCS = mlChol.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlChol/mlChol.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_CHOL_H__ 11 | #define __ML_CHOL_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | 25 | ///////////////////////////////////////////////////////// 26 | // main testing function 27 | ///////////////////////////////////////////////////////// 28 | int main(int argc, const char * const argv[]); 29 | 30 | 31 | #endif 32 | 33 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlChol/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDct/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlDct.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlDct "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDct/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlDct 2 | PULP_APP_SRCS = mlDct.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDct/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDist/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlDist.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlDist "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDist/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlDist 2 | PULP_APP_SRCS = mlDist.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDist/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDotp/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlDotp.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlDotp "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDotp/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlDotp 2 | PULP_APP_SRCS = mlDotp.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDotp/mlDotp.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_DOTP_H__ 11 | #define __ML_DOTP_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | 25 | ///////////////////////////////////////////////////////// 26 | // main testing function 27 | ///////////////////////////////////////////////////////// 28 | int main(int argc, const char * const argv[]); 29 | 30 | 31 | 32 | #endif 33 | 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlDotp/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlFir/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlFir.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlFir "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlFir/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlFir 2 | PULP_APP_SRCS = mlFir.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlFir/mlFir.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_FIR_H__ 11 | #define __ML_FIR_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | void mlFir(const float img[225], float filt[225]); 25 | 26 | float sum(const float x[225]); 27 | 28 | float var(const float x[225]); 29 | 30 | ///////////////////////////////////////////////////////// 31 | // main testing function 32 | ///////////////////////////////////////////////////////// 33 | int main(int argc, const char * const argv[]); 34 | 35 | 36 | 37 | 38 | #endif 39 | 40 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlFir/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlGemm.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlGemm "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemm/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlGemm 2 | PULP_APP_SRCS = mlGemm.c 3 | 4 | 5 | #PULP_CFLAGS += -O3 -DFP_SW_EMUL 6 | #stackSize = 8192 7 | 8 | PULP_CFLAGS += -O3 9 | stackSize = 4096 10 | 11 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 12 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemm/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlGemv.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlGemv "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemv/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlGemv 2 | PULP_APP_SRCS = mlGemv.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemv/mlGemv.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_GEMV_H__ 11 | #define __ML_GEMV_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | 25 | ///////////////////////////////////////////////////////// 26 | // main testing function 27 | ///////////////////////////////////////////////////////// 28 | int main(int argc, const char * const argv[]); 29 | 30 | 31 | 32 | #endif 33 | 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGemv/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGivens/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlGivens.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlGivens "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGivens/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlGivens 2 | PULP_APP_SRCS = mlGivens.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | 8 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 9 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGivens/mlGivens.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_GIVENS_H__ 11 | #define __ML_GIVENS_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | void mlGivens(const float * axang, const float * vects, float * b_vects); 25 | 26 | ///////////////////////////////////////////////////////// 27 | // main testing function 28 | ///////////////////////////////////////////////////////// 29 | int main(int argc, const char * const argv[]); 30 | 31 | 32 | 33 | 34 | #endif 35 | 36 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGivens/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGrad/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlGrad.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlGrad "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGrad/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlGrad 2 | PULP_APP_SRCS = mlGrad.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGrad/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGradDir/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlGradDir.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlGradDir "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGradDir/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlGradDir 2 | PULP_APP_SRCS = mlGradDir.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlGradDir/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHom/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlHom.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlHom "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHom/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlHom 2 | PULP_APP_SRCS = mlHom.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHom/mlHom.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_HOM_H__ 11 | #define __ML_HOM_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | float var(const float x[50]); 25 | 26 | ///////////////////////////////////////////////////////// 27 | // main testing function 28 | ///////////////////////////////////////////////////////// 29 | int main(int argc, const char * const argv[]); 30 | 31 | 32 | 33 | #endif 34 | 35 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHom/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHomErr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlHomErr.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlHomErr "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHomErr/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlHomErr 2 | PULP_APP_SRCS = mlHomErr.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHomErr/mlHomErr.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_HOM_H__ 11 | #define __ML_HOM_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | float mlHomErr(const float H[9], const float x1[100], const float x2[100]); 25 | void repmat(const float a[50], float b[100]); 26 | 27 | 28 | ///////////////////////////////////////////////////////// 29 | // main testing function 30 | ///////////////////////////////////////////////////////// 31 | int main(int argc, const char * const argv[]); 32 | 33 | 34 | 35 | #endif 36 | 37 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlHomErr/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlLog/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlLog.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlLog "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlLog/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlLog 2 | PULP_APP_SRCS = mlLog.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlLog/mlLog.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_LOG_H__ 11 | #define __ML_LOG_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | 25 | ///////////////////////////////////////////////////////// 26 | // main testing function 27 | ///////////////////////////////////////////////////////// 28 | int main(int argc, const char * const argv[]); 29 | 30 | 31 | 32 | #endif 33 | 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlLog/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlQr/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlQr.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlQr "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlQr/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlQr 2 | PULP_APP_SRCS = mlQr.c math_fns.c 3 | PULP_CFLAGS += -O3 -fno-tree-loop-distribute-patterns 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlQr/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlRbf/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlRbf.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlRbf "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlRbf/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlRbf 2 | PULP_APP_SRCS = mlRbf.c math_fns.c 3 | PULP_CFLAGS += -O3 -fno-tree-loop-distribute-patterns 4 | 5 | stackSize = 4096 6 | 7 | 8 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 9 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlRbf/mlRbf.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_RBF_H__ 11 | #define __ML_RBF_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | ///////////////////////////////////////////////////////// 25 | // main testing function 26 | ///////////////////////////////////////////////////////// 27 | int main(int argc, const char * const argv[]); 28 | 29 | 30 | 31 | #endif 32 | 33 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlRbf/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSchur/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlSchur.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlSchur "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSchur/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSin/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlSin.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlSin "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSin/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlSin 2 | PULP_APP_SRCS = mlSin.c math_fns.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSin/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSin/mlSin.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_SIN_H__ 11 | #define __ML_SIN_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | ///////////////////////////////////////////////////////// 25 | // main testing function 26 | ///////////////////////////////////////////////////////// 27 | int main(int argc, const char * const argv[]); 28 | 29 | 30 | 31 | 32 | #endif 33 | 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSvd/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlSvd.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlSvd "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSvd/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlSvd 2 | PULP_APP_SRCS = mlSvd.c math_fns.c 3 | PULP_CFLAGS += -O3 -fno-tree-loop-distribute-patterns 4 | stackSize = 4096 5 | 6 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 7 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlSvd/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlWdotp/.gitignore: -------------------------------------------------------------------------------- 1 | *.o 2 | *.read 3 | *.out 4 | *.slm 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlWdotp/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES mlWdotp.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(mlWdotp "${FP_SOURCES}" LABELS "ml_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlWdotp/Makefile: -------------------------------------------------------------------------------- 1 | PULP_APP = mlWdotp 2 | PULP_APP_SRCS = mlWdotp.c 3 | PULP_CFLAGS += -O3 4 | 5 | stackSize = 4096 6 | 7 | include $(PULP_SDK_HOME)/install/rules/pulp.mk 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlWdotp/mlShared.h: -------------------------------------------------------------------------------- 1 | ../ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/ml_tests/mlWdotp/mlWdotp.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | #ifndef __ML_WDOTP_H__ 11 | #define __ML_WDOTP_H__ 12 | 13 | ///////////////////////////////////////////////////////// 14 | // defines 15 | ///////////////////////////////////////////////////////// 16 | 17 | // include the shared header for ml kernels 18 | #include "mlShared.h" 19 | 20 | ///////////////////////////////////////////////////////// 21 | // subfunctions 22 | ///////////////////////////////////////////////////////// 23 | 24 | 25 | ///////////////////////////////////////////////////////// 26 | // main testing function 27 | ///////////////////////////////////////////////////////// 28 | int main(int argc, const char * const argv[]); 29 | 30 | 31 | 32 | #endif 33 | 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | include_directories(includes) 2 | 3 | add_subdirectory(basic) 4 | add_subdirectory(official) 5 | 6 | # memory access 7 | add_subdirectory(testMisaligned) 8 | 9 | # interrupts and events 10 | add_subdirectory(testEvents) 11 | add_subdirectory(testExceptions) 12 | add_subdirectory(testIRQ) 13 | 14 | # arithmetic operations 15 | add_subdirectory(testALU) 16 | add_subdirectory(testALUExt) 17 | add_subdirectory(testMUL) 18 | add_subdirectory(testDivRem) 19 | add_subdirectory(testFPU) 20 | 21 | # ETH specific features 22 | add_subdirectory(testBitManipulation) 23 | add_subdirectory(testCnt) 24 | add_subdirectory(testClip) 25 | add_subdirectory(testVecArith) 26 | add_subdirectory(testVecCmp) 27 | add_subdirectory(testShufflePack) 28 | add_subdirectory(testAddSubNorm) 29 | add_subdirectory(testMacNorm) 30 | add_subdirectory(testDotMul) 31 | 32 | # other core features 33 | add_subdirectory(testCSR) 34 | add_subdirectory(testDebug) 35 | #add_subdirectory(testPriv) 36 | 37 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/basic/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(rv_basic basic.c LABELS "riscv_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/basic/basic.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include 12 | 13 | #include 14 | 15 | /* this test has no meaning on the PULPino platform - just ensure that the testing framework is working */ 16 | 17 | int main() { 18 | 19 | print_summary(0); 20 | 21 | return 0; 22 | } 23 | 24 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set_source_files_properties(tests.S PROPERTIES LANGUAGE C) 2 | 3 | set(SOURCES test_print.c tests.S) 4 | add_application(rv_official "${SOURCES}" LABELS riscv_tests) 5 | #add_spi_regression(rv_official "${SOURCES}") 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/test_print.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | 12 | #include "string_lib.h" 13 | #include "uart.h" 14 | #include "utils.h" 15 | 16 | unsigned int g_errors = 0; 17 | 18 | void print_okay(const int testnr, const char *testsuite) { 19 | printf("Test suite OK: %s\n", testsuite); 20 | } 21 | 22 | void print_fail(const int testnr, const char *testsuite) { 23 | g_errors++; 24 | printf("Test FAIL: %d (suite %s)\n", testnr, testsuite); 25 | } 26 | 27 | 28 | void print_test_summary() 29 | { 30 | 31 | printf("==== SUMMARY: "); 32 | 33 | if (g_errors == 0) { 34 | printf("OOOOOOK!!!!!!\n"); 35 | } else { 36 | printf("NOT OK!!!!!\n"); 37 | } 38 | 39 | uart_wait_tx_done(); 40 | 41 | // signal end of computation 42 | eoc(g_errors); 43 | } 44 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/NOTE: -------------------------------------------------------------------------------- 1 | Still missing: 2 | - All tests for load instructions 3 | - All tests for store instructions 4 | - Fence instruction tests 5 | 6 | Intentionally missing: 7 | - All tests for atomic instructions (include lr/sc) 8 | - All div/rem tests (not implemented) 9 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/auipc.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # auipc.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test auipc instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | TEST_CASE(2, a0, 10000, \ 17 | .align 3; \ 18 | lla a0, 1f + 10000; \ 19 | jal a1, 1f; \ 20 | 1: sub a0, a0, a1; \ 21 | ) 22 | 23 | TEST_CASE(3, a0, -10000, \ 24 | .align 3; \ 25 | lla a0, 1f - 10000; \ 26 | jal a1, 1f; \ 27 | 1: sub a0, a0, a1; \ 28 | ) 29 | 30 | TEST_PASSFAIL 31 | 32 | RVTEST_CODE_END 33 | 34 | .data 35 | RVTEST_DATA_BEGIN 36 | 37 | TEST_DATA 38 | 39 | RVTEST_DATA_END 40 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/j.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # j.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test j instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test basic 18 | #------------------------------------------------------------- 19 | 20 | li TESTNUM, 2; 21 | j test_2; 22 | j fail; 23 | test_2: 24 | 25 | #------------------------------------------------------------- 26 | # Test delay slot instructions not executed nor bypassed 27 | #------------------------------------------------------------- 28 | 29 | TEST_CASE( 3, x1, 3, \ 30 | li x1, 1; \ 31 | j 1f; \ 32 | addi x1, x1, 1; \ 33 | addi x1, x1, 1; \ 34 | addi x1, x1, 1; \ 35 | addi x1, x1, 1; \ 36 | 1: addi x1, x1, 1; \ 37 | addi x1, x1, 1; \ 38 | ) 39 | 40 | TEST_PASSFAIL 41 | 42 | RVTEST_CODE_END 43 | 44 | .data 45 | RVTEST_DATA_BEGIN 46 | 47 | TEST_DATA 48 | 49 | RVTEST_DATA_END 50 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/jal.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # jal.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test jal instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Test 2: Basic test 18 | #------------------------------------------------------------- 19 | 20 | test_2: 21 | li TESTNUM, 2 22 | li ra, 0 23 | 24 | linkaddr_2: 25 | jal target_2 26 | nop 27 | nop 28 | 29 | j fail 30 | 31 | target_2: 32 | la x2, linkaddr_2 33 | addi x2, x2, 4 34 | bne x2, ra, fail 35 | 36 | #------------------------------------------------------------- 37 | # Test delay slot instructions not executed nor bypassed 38 | #------------------------------------------------------------- 39 | 40 | TEST_CASE( 3, x2, 3, \ 41 | li x2, 1; \ 42 | jal 1f; \ 43 | addi x2, x2, 1; \ 44 | addi x2, x2, 1; \ 45 | addi x2, x2, 1; \ 46 | addi x2, x2, 1; \ 47 | 1: addi x2, x2, 1; \ 48 | addi x2, x2, 1; \ 49 | ) 50 | 51 | TEST_PASSFAIL 52 | 53 | RVTEST_CODE_END 54 | 55 | .data 56 | RVTEST_DATA_BEGIN 57 | 58 | TEST_DATA 59 | 60 | RVTEST_DATA_END 61 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/lui.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # lui.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # Test lui instruction. 8 | # 9 | 10 | #include "riscv_test.h" 11 | #include "test_macros.h" 12 | 13 | RVTEST_RV32U 14 | RVTEST_CODE_BEGIN 15 | 16 | #------------------------------------------------------------- 17 | # Basic tests 18 | #------------------------------------------------------------- 19 | 20 | TEST_CASE( 2, x1, 0x00000000, lui x1, 0x00000 ); 21 | TEST_CASE( 3, x1, 0xfffff800, lui x1, 0xfffff;sra x1,x1,1); 22 | TEST_CASE( 4, x1, 0x000007ff, lui x1, 0x7ffff;sra x1,x1,20); 23 | TEST_CASE( 5, x1, 0xfffff800, lui x1, 0x80000;sra x1,x1,20); 24 | 25 | TEST_CASE( 6, x0, 0, lui x0, 0x80000 ); 26 | 27 | TEST_PASSFAIL 28 | 29 | RVTEST_CODE_END 30 | 31 | .data 32 | RVTEST_DATA_BEGIN 33 | 34 | TEST_DATA 35 | 36 | RVTEST_DATA_END 37 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/riscv_test.h: -------------------------------------------------------------------------------- 1 | ../riscv_test.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/simple.S: -------------------------------------------------------------------------------- 1 | # See LICENSE for license details. 2 | 3 | #***************************************************************************** 4 | # simple.S 5 | #----------------------------------------------------------------------------- 6 | # 7 | # This is the most basic self checking test. If your simulator does not 8 | # pass thiss then there is little chance that it will pass any of the 9 | # more complicated self checking tests. 10 | # 11 | 12 | #include "riscv_test.h" 13 | #include "test_macros.h" 14 | 15 | RVTEST_RV32U 16 | RVTEST_CODE_BEGIN 17 | 18 | RVTEST_PASS 19 | 20 | RVTEST_CODE_END 21 | 22 | .data 23 | RVTEST_DATA_BEGIN 24 | 25 | TEST_DATA 26 | 27 | RVTEST_DATA_END 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/official/tests/test_macros.h: -------------------------------------------------------------------------------- 1 | ../test_macros.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testALU/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testALU testALU.c LABELS "riscv_tests") -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testALUExt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testALUExt testALUExt.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testAddSubNorm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testAddSubNorm testAddSubNorm.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testBitManipulation/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testBitManipulation testBitManipulation.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testCSR/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testCSR testCSR.c LABELS "riscv_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testClip/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testClip testClip.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testCnt/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testCnt testCnt.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testDebug/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | set(RISCV_FLAGS "-DUSE_MUL -DPULP_EXT") 3 | elseif(${GCC_MARCH} MATCHES "RV32IM") 4 | set(RISCV_FLAGS "-DUSE_MUL") 5 | else() 6 | set(RISCV_FLAGS "") 7 | endif() 8 | 9 | add_application(testDebug main.c TB run_debug.tcl FLAGS ${RISCV_FLAGS} LABELS "riscv_tests") 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testDivRem/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "RV32IM" OR ${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testDivRem testDivRem.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testDivRem/stimuli/Makefile: -------------------------------------------------------------------------------- 1 | 2 | all: generator 3 | ./generator 4 | 5 | generator: stimuli_gen.c 6 | gcc ./stimuli_gen.c -o ./generator -Wall -std=c99 7 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testDotMul/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testDotMul testDotMul.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testEvents/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testEvents testEvents.c LABELS "riscv_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testExceptions/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testExceptions main.c LABELS "riscv_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testFPU/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(FP_SOURCES testFPU.c) 2 | 3 | if (${RISCY_RV32F}) 4 | add_application(testFPU "${FP_SOURCES}" LABELS "riscv_tests") 5 | endif() 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testFPU/mlShared.h: -------------------------------------------------------------------------------- 1 | ../../ml_tests/ml_shared/mlShared.h -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testIRQ/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | set(RISCV_FLAGS "-DUSE_MUL -DPULP_EXT") 3 | elseif(${GCC_MARCH} MATCHES "RV32IM") 4 | set(RISCV_FLAGS "-DUSE_MUL") 5 | else() 6 | set(RISCV_FLAGS "") 7 | endif() 8 | 9 | add_application(testIRQ main.c FLAGS ${RISCV_FLAGS} LABELS "riscv_tests") 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testMUL/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "RV32IM" OR ${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testMUL testMUL.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testMacNorm/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testMacNorm testMacNorm.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testMisaligned/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(testMisaligned main.c LABELS "riscv_tests") 2 | 3 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testPriv/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testPriv testPriv.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testShufflePack/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testShufflePack testShufflePack.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testVecArith/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testVecArith testVecArith.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/riscv_tests/testVecCmp/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | if (${GCC_MARCH} MATCHES "[pulp]+") 2 | add_application(testVecCmp testVecCmp.c LABELS "riscv_tests") 3 | endif() 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_subdirectory(bitDescriptor) 2 | add_subdirectory(bubblesort) 3 | add_subdirectory(fibonacci) 4 | add_subdirectory(crc32) 5 | add_subdirectory(matrixAdd) 6 | add_subdirectory(sudokusolver) 7 | add_subdirectory(stencil_vect) 8 | add_subdirectory(towerofhanoi) 9 | add_subdirectory(matrixMul8) 10 | add_subdirectory(matrixMul8_dotp) 11 | add_subdirectory(matrixMul16) 12 | add_subdirectory(matrixMul16_dotp) 13 | add_subdirectory(matrixMul32) 14 | add_subdirectory(motion_detection) 15 | add_subdirectory(convolution) 16 | add_subdirectory(pooling) 17 | add_subdirectory(cnn_layer) 18 | add_subdirectory(stencil) 19 | add_subdirectory(dct) 20 | add_subdirectory(fdct) 21 | add_subdirectory(non_separable_2d_filter) 22 | 23 | # region `ram' overflowed by 15978072 bytes, N constant is way too big 24 | #add_subdirectory(fdtd-1d) 25 | # region `ram' overflowed by 3572 bytes 26 | #add_subdirectory(fft) 27 | # region `ram' overflowed by 63978248 bytes, N constant is way too big 28 | #add_subdirectory(jacobi-1d-imper) 29 | # region `ram' overflowed by 63978248 bytes, N constant is way too big 30 | #add_subdirectory(jacobi-2d-imper) 31 | # region `ram' overflowed by 1044 bytes 32 | #add_subdirectory(rijndael) -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/bitDescriptor/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(bitDescriptor bitDescriptor.c LABELS "sequential_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/bubblesort/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(bubblesort bubblesort.c LABELS "sequential_tests") 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/bubblesort/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/ref/common.mk 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/cnn_layer/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(CNN_SOURCES cnn_layer.c cnn_kernels.c cnn_kernels_fused.c) 2 | 3 | if (${GCC_MARCH} MATCHES "[pulp]+") 4 | add_application(cnn_layer "${CNN_SOURCES}" FLAGS "-DPROFILE -DVEC" LABELS "sequential_tests") 5 | else() 6 | add_application(cnn_layer "${CNN_SOURCES}" FLAGS "-DPROFILE" LABELS "sequential_tests") 7 | endif() 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/cnn_layer/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_CONV_ 2 | #define _CONFIG_CONV_ 3 | 4 | #define DATA_WIDTH 14 5 | #define DATA_TYPE 16 6 | #define IMG_ROW 64 7 | #define IMG_COL 64 8 | #define IMG_DIM IMG_ROW*IMG_COL 9 | 10 | #define CONV_DIM (IMG_ROW-4)*(IMG_COL-4) 11 | 12 | #define POOL_DIM CONV_DIM/4 13 | 14 | #define OUT_DIM POOL_DIM 15 | 16 | #define FILT_WIN 5 17 | #define FILT_DIM FILT_WIN*FILT_WIN 18 | 19 | #endif -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/convolution/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(CONV_SOURCES convolution.c conv_kernels.c) 2 | if (${GCC_MARCH} MATCHES "[pulp]+") 3 | add_application(convolution "${CONV_SOURCES}" FLAGS "-DPROFILE -DDOTP" LABELS "sequential_tests") 4 | else() 5 | add_application(convolution "${CONV_SOURCES}" FLAGS "-DPROFILE" LABELS "sequential_tests") 6 | endif() 7 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/convolution/README.md: -------------------------------------------------------------------------------- 1 | # General Overview 2 | 3 | 2D-Convolution application with a kernel window 3x3 or 5x5. 4 | Run on `octave` the script gen_stimuli.m to generate samples from a new random image or 5 | use your image to generate samples. 6 | A new file `data_image.h` is generated. It contains image samples, the used kernel and the 7 | golden output value. 8 | 9 | ## Setup 10 | 11 | Set `DATA_WIDTH` equal to 16 to have "short" values or 8 to have "char" ones. 12 | Set `RANDOM` equal to 1 to generate a random image. 13 | Modify `COL` and `ROW` to change the image size. 14 | Set `WRITE_FILE` equal to 1 to generate the `data_image.h` header file for RISC-V. 15 | Set `WIN` equal to 3 or 5 to choose your kernel size. -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/convolution/config.h: -------------------------------------------------------------------------------- 1 | #ifndef _CONFIG_CONV_ 2 | #define _CONFIG_CONV_ 3 | 4 | #define DATA_WIDTH 14 5 | #define DATA_TYPE 16 6 | #define IMG_ROW 32 7 | #define IMG_COL 32 8 | #define IMG_DIM IMG_ROW*IMG_COL 9 | 10 | #define FILT_WIN 5 11 | #define FILT_DIM FILT_WIN*FILT_WIN 12 | 13 | #endif -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/crc32/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(crc32 crc_32.c) -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/crc32/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | BENCH_LIB_PATH = $(SW_ROOT)/libs/bench_lib 4 | BENCH_LIB_NAME = bench_lib.a 5 | BENCH_LIB = $(BENCH_LIB_PATH)/$(BENCH_LIB_NAME) 6 | 7 | BENCH_LIB_FILES = 8 | 9 | BENCH_OBJ = 10 | 11 | include $(SW_ROOT)/ref/common.mk 12 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/crc32/jrand.c: -------------------------------------------------------------------------------- 1 | __attribute__ ((section(".heapsram"))) unsigned int next; 2 | 3 | int jrand() 4 | { 5 | next = next * 1103515245 + 12345; 6 | return next; 7 | } 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/dct/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(dct dct.c) -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/dct/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/ref/common.mk 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/fdct/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set_source_files_properties( 2 | fdct.c 3 | PROPERTIES COMPILE_FLAGS "-DOR10N_TESTS_PRINTF") 4 | 5 | add_application(fdct fdct.c) 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/fdct/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | CC_USER_FLAGS=-DOR10N_TESTS_PRINTF 4 | 5 | include $(SW_ROOT)/ref/common.mk 6 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/fdtd-1d/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | add_application(fdtd-1d fdtd-1d.c) -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/fdtd-1d/Makefile: -------------------------------------------------------------------------------- 1 | SW_ROOT=../../.. 2 | 3 | include $(SW_ROOT)/ref/common.mk 4 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/apps/sequential_tests/fdtd-1d/fdtd-1d.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #define N 1000000 12 | #define T 10000 13 | double h[N]; 14 | double e[N+1]; 15 | #define coeff1 0.5 16 | #define coeff2 0.7 17 | 18 | void init_array() 19 | { 20 | int i, j; 21 | 22 | for (j=0; j 12 | #include 13 | 14 | 15 | #define N 2000000 16 | #define T 1000 17 | 18 | double a[N]; 19 | double b[N]; 20 | 21 | void init_array() 22 | { 23 | int j; 24 | 25 | for (j=0; j 24 | 25 | class Print; 26 | 27 | /** The Printable class provides a way for new classes to allow themselves to be printed. 28 | By deriving from Printable and implementing the printTo method, it will then be possible 29 | for users to print out instances of this class by passing them into the usual 30 | Print::print and Print::println methods. 31 | */ 32 | 33 | class Printable 34 | { 35 | public: 36 | virtual size_t printTo(Print& p) const = 0; 37 | }; 38 | 39 | #endif 40 | 41 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/core_libs/inc/Server.h: -------------------------------------------------------------------------------- 1 | /* 2 | Server.h - Base class that provides Server 3 | Copyright (c) 2011 Adrian McEwen. All right reserved. 4 | 5 | This library is free software; you can redistribute it and/or 6 | modify it under the terms of the GNU Lesser General Public 7 | License as published by the Free Software Foundation; either 8 | version 2.1 of the License, or (at your option) any later version. 9 | 10 | This library is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | Lesser General Public License for more details. 14 | 15 | You should have received a copy of the GNU Lesser General Public 16 | License along with this library; if not, write to the Free Software 17 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | */ 19 | 20 | #ifndef server_h 21 | #define server_h 22 | 23 | #include "Print.h" 24 | 25 | class Server : public Print { 26 | public: 27 | virtual void begin() =0; 28 | }; 29 | 30 | #endif 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/core_libs/inc/main.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | main.cpp - Main loop for Arduino sketches 3 | Copyright (c) 2005-2013 Arduino Team. All right reserved. 4 | 5 | This library is free software; you can redistribute it and/or 6 | modify it under the terms of the GNU Lesser General Public 7 | License as published by the Free Software Foundation; either 8 | version 2.1 of the License, or (at your option) any later version. 9 | 10 | This library is distributed in the hope that it will be useful, 11 | but WITHOUT ANY WARRANTY; without even the implied warranty of 12 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 13 | Lesser General Public License for more details. 14 | 15 | You should have received a copy of the GNU Lesser General Public 16 | License along with this library; if not, write to the Free Software 17 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 18 | 19 | Modified 14 June 2016 by Mahmoud Elmohr (Ported to RISC-V PULPino) 20 | */ 21 | 22 | #include 23 | 24 | // Declared weak in Arduino.h to allow user redefinitions. 25 | int atexit(void (* /*func*/ )()) { return 0; } 26 | 27 | // Weak empty variant initialization function. 28 | // May be redefined by variant files. 29 | void initVariant() __attribute__((weak)); 30 | void initVariant() { } 31 | 32 | int main(void) 33 | { 34 | init(); 35 | 36 | initVariant(); 37 | setup(); 38 | 39 | for (;;) { 40 | loop(); 41 | if (serialEventRun) serialEventRun(); 42 | } 43 | 44 | return 0; 45 | } 46 | 47 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/core_libs/inc/new.h: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2014 Arduino. All right reserved. 3 | 4 | This library is free software; you can redistribute it and/or 5 | modify it under the terms of the GNU Lesser General Public 6 | License as published by the Free Software Foundation; either 7 | version 2.1 of the License, or (at your option) any later version. 8 | 9 | This library is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 | See the GNU Lesser General Public License for more details. 13 | 14 | You should have received a copy of the GNU Lesser General Public 15 | License along with this library; if not, write to the Free Software 16 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 | */ 18 | 19 | #ifndef NEW_H 20 | #define NEW_H 21 | 22 | #include 23 | 24 | void * operator new(size_t size); 25 | void * operator new[](size_t size); 26 | void operator delete(void * ptr); 27 | void operator delete[](void * ptr); 28 | 29 | #endif 30 | 31 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/core_libs/src/abi.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2014 Arduino. All right reserved. 3 | 4 | This library is free software; you can redistribute it and/or 5 | modify it under the terms of the GNU Lesser General Public 6 | License as published by the Free Software Foundation; either 7 | version 2.1 of the License, or (at your option) any later version. 8 | 9 | This library is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 | See the GNU Lesser General Public License for more details. 13 | 14 | You should have received a copy of the GNU Lesser General Public 15 | License along with this library; if not, write to the Free Software 16 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 | */ 18 | 19 | #include 20 | 21 | extern "C" void __cxa_pure_virtual(void) __attribute__ ((__noreturn__)); 22 | extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__)); 23 | 24 | void __cxa_pure_virtual(void) { 25 | // We might want to write some diagnostics to uart in this case 26 | //std::terminate(); 27 | abort(); 28 | } 29 | 30 | void __cxa_deleted_virtual(void) { 31 | // We might want to write some diagnostics to uart in this case 32 | //std::terminate(); 33 | abort(); 34 | } 35 | 36 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/core_libs/src/hooks.c: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2012 Arduino. All right reserved. 3 | 4 | This library is free software; you can redistribute it and/or 5 | modify it under the terms of the GNU Lesser General Public 6 | License as published by the Free Software Foundation; either 7 | version 2.1 of the License, or (at your option) any later version. 8 | 9 | This library is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 | See the GNU Lesser General Public License for more details. 13 | 14 | You should have received a copy of the GNU Lesser General Public 15 | License along with this library; if not, write to the Free Software 16 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 | */ 18 | 19 | /** 20 | * Empty yield() hook. 21 | * 22 | * This function is intended to be used by library writers to build 23 | * libraries or sketches that supports cooperative threads. 24 | * 25 | * Its defined as a weak symbol and it can be redefined to implement a 26 | * real cooperative scheduler. 27 | */ 28 | static void __empty() { 29 | // Empty 30 | } 31 | void yield(void) __attribute__ ((weak, alias("__empty"))); 32 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/core_libs/src/new.cpp: -------------------------------------------------------------------------------- 1 | /* 2 | Copyright (c) 2014 Arduino. All right reserved. 3 | 4 | This library is free software; you can redistribute it and/or 5 | modify it under the terms of the GNU Lesser General Public 6 | License as published by the Free Software Foundation; either 7 | version 2.1 of the License, or (at your option) any later version. 8 | 9 | This library is distributed in the hope that it will be useful, 10 | but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 | See the GNU Lesser General Public License for more details. 13 | 14 | You should have received a copy of the GNU Lesser General Public 15 | License along with this library; if not, write to the Free Software 16 | Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 17 | */ 18 | 19 | #include 20 | 21 | void *operator new(size_t size) { 22 | return malloc(size); 23 | } 24 | 25 | void *operator new[](size_t size) { 26 | return malloc(size); 27 | } 28 | 29 | void operator delete(void * ptr) { 30 | free(ptr); 31 | } 32 | 33 | void operator delete[](void * ptr) { 34 | free(ptr); 35 | } 36 | 37 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/Arduino_lib/separate_libs/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(SOURCES 2 | src/twi.c 3 | src/Wire.cpp 4 | src/SPI.cpp 5 | ) 6 | 7 | set(HEADERS 8 | inc/twi.h 9 | inc/Wire.h 10 | inc/SPI.h 11 | ) 12 | 13 | include_directories(inc/) 14 | include_directories(../core_libs/inc) 15 | include_directories(../../sys_lib/inc) 16 | 17 | add_library(Arduino_separate STATIC ${SOURCES} ${HEADERS}) 18 | 19 | 20 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/bench_lib/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(SOURCES 2 | src/bench.c 3 | ) 4 | 5 | set(HEADERS 6 | inc/bench.h 7 | ) 8 | 9 | include_directories(inc/) 10 | include_directories(../string_lib/inc) 11 | 12 | add_library(bench STATIC ${SOURCES} ${HEADERS}) 13 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/math_fns_lib/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(SOURCES 2 | src/math_fns.c 3 | ) 4 | 5 | set(HEADERS 6 | inc/math_fns.h 7 | ) 8 | 9 | include_directories(inc/) 10 | 11 | add_library(math_fns STATIC ${SOURCES} ${HEADERS}) 12 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/string_lib/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(SOURCES 2 | src/qprintf.c 3 | ) 4 | 5 | set(HEADERS 6 | inc/string_lib.h 7 | ) 8 | 9 | include_directories(inc/) 10 | include_directories(../sys_lib/inc) 11 | 12 | add_library(string STATIC ${SOURCES} ${HEADERS}) 13 | #set_target_properties(string PROPERTIES COMPILE_FLAGS "-DPOWER_MES -fno-tree-loop-distribute-patterns") 14 | set_target_properties(string PROPERTIES COMPILE_FLAGS "-fno-tree-loop-distribute-patterns") 15 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/string_lib/inc/string_lib.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #ifndef STRING_LIB_H 12 | #define STRING_LIB_H 13 | 14 | #include 15 | 16 | #include "pulpino.h" 17 | 18 | // putchar is defined as a macro which gets in the way of our prototype below 19 | #ifdef putchar 20 | #undef putchar 21 | #endif 22 | 23 | size_t strlen (const char *str); 24 | int strcmp (const char *s1, const char *s2); 25 | char* strcpy (char *s1, const char *s2); 26 | int puts(const char *s); 27 | int printf(const char *format, ...); 28 | void * memset (void *dest, int val, size_t len); 29 | int putchar(int s); 30 | 31 | #endif 32 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/sys_lib/CMakeLists.txt: -------------------------------------------------------------------------------- 1 | set(SOURCES 2 | src/exceptions.c 3 | src/gpio.c 4 | src/int.c 5 | src/spi.c 6 | src/timer.c 7 | src/uart.c 8 | src/utils.c 9 | src/i2c.c 10 | ) 11 | 12 | set(HEADERS 13 | inc/bar.h 14 | inc/gpio.h 15 | inc/int.h 16 | inc/pulpino.h 17 | inc/spi.h 18 | inc/spr-defs.h 19 | inc/timer.h 20 | inc/uart.h 21 | inc/utils.h 22 | inc/i2c.h 23 | ) 24 | 25 | include_directories(inc/) 26 | include_directories(../string_lib/inc) 27 | 28 | add_library(sys STATIC ${SOURCES} ${HEADERS}) 29 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/sys_lib/inc/bar.h: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #ifndef __BAR_H__ 12 | #define __BAR_H__ 13 | 14 | #include "pulpino.h" 15 | #include "utils.h" 16 | 17 | // the following macros are for convenience and compatibility with existing 18 | // code only 19 | 20 | #define synch_barrier() 21 | #define synch_threads(num_threads) 22 | 23 | #endif 24 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/sys_lib/src/exceptions.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include 12 | #include "string_lib.h" 13 | #include "utils.h" 14 | 15 | // use weak attribute here, so we can overwrite this function to provide custom exception handlers, e.g. for tests 16 | __attribute__((interrupt)) __attribute__((weak)) 17 | void default_exception_handler_c(void) 18 | { 19 | for(;;); 20 | } 21 | 22 | // use weak attribute here, so we can overwrite this function to provide custom exception handlers, e.g. for tests 23 | __attribute__((interrupt)) __attribute__((weak)) 24 | void illegal_insn_handler_c(void) 25 | { 26 | for(;;); 27 | } 28 | // use weak attribute here, so we can overwrite this function to provide custom exception handlers, e.g. for tests 29 | __attribute__((interrupt)) __attribute__((weak)) 30 | void ecall_insn_handler_c(void) 31 | { 32 | for(;;); 33 | } 34 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/libs/sys_lib/src/timer.c: -------------------------------------------------------------------------------- 1 | // Copyright 2017 ETH Zurich and University of Bologna. 2 | // Copyright and related rights are licensed under the Solderpad Hardware 3 | // License, Version 0.51 (the “License”); you may not use this file except in 4 | // compliance with the License. You may obtain a copy of the License at 5 | // http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law 6 | // or agreed to in writing, software, hardware and materials distributed under 7 | // this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR 8 | // CONDITIONS OF ANY KIND, either express or implied. See the License for the 9 | // specific language governing permissions and limitations under the License. 10 | 11 | #include "timer.h" 12 | 13 | void reset_timer(void) { 14 | TIRA = 0; 15 | } 16 | 17 | void start_timer(void) { 18 | TPRA = 0x1; 19 | } 20 | 21 | void stop_timer(void) { 22 | TPRA = 0x0; 23 | } 24 | 25 | int get_time(void) { 26 | return TIRA; 27 | } 28 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/ref/link.or1k.ld: -------------------------------------------------------------------------------- 1 | /* not needed, but we need separate linker scripts anyway */ 2 | OUTPUT_ARCH(or1k) 3 | 4 | INCLUDE link.common.ld 5 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/ref/link.riscv.ld: -------------------------------------------------------------------------------- 1 | /* not needed, but we need separate linker scripts anyway */ 2 | OUTPUT_ARCH(riscv) 3 | 4 | /* required to correctly link newlib */ 5 | GROUP( -lc -lgloss -lgcc -lsupc++ ) 6 | 7 | INCLUDE link.common.ld 8 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/sw/utils/run-on-fpga.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | NAME=$1 4 | 5 | scp slm_files/spi_stim.txt root@$FPGA_HOSTNAME:/root/$NAME.spi 6 | ssh -t root@$FPGA_HOSTNAME /root/spiload --timeout=60 /root/$NAME.spi 7 | 8 | exit 0 9 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/tb/.gitignore: -------------------------------------------------------------------------------- 1 | minsoc_vpi/ 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/tb/jtag_dpi/.gitignore: -------------------------------------------------------------------------------- 1 | dpiheader.h 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/tb/mem_dpi/.gitignore: -------------------------------------------------------------------------------- 1 | dpiheader.h 2 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/.gitignore: -------------------------------------------------------------------------------- 1 | work/ 2 | modelsim_libs/ 3 | modelsim.ini 4 | transcript 5 | vcompile/ips/ 6 | vcompile/vcompile_ips.csh 7 | tcl_files/config/vsim_ips.tcl 8 | verilator_libs/ 9 | verilator/* -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/config/vsim.tcl: -------------------------------------------------------------------------------- 1 | source tcl_files/config/vsim_ips.tcl 2 | 3 | set cmd "vsim -quiet $TB \ 4 | -L pulpino_lib \ 5 | $VSIM_IP_LIBS \ 6 | +nowarnTRAN \ 7 | +nowarnTSCALE \ 8 | +nowarnTFMPC \ 9 | +MEMLOAD=$MEMLOAD \ 10 | -gUSE_ZERO_RISCY=$env(USE_ZERO_RISCY) \ 11 | -gRISCY_RV32F=$env(RISCY_RV32F) \ 12 | -gZERO_RV32M=$env(ZERO_RV32M) \ 13 | -gZERO_RV32E=$env(ZERO_RV32E) \ 14 | -t ps \ 15 | -voptargs=\"+acc -suppress 2103\" \ 16 | $VSIM_FLAGS" 17 | 18 | # set cmd "$cmd -sv_lib ./work/libri5cyv2sim" 19 | eval $cmd 20 | 21 | # check exit status in tb and quit the simulation accordingly 22 | proc run_and_exit {} { 23 | run -all 24 | quit -code [examine -radix decimal sim:/tb/exit_status] 25 | } 26 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/config/vsim_zero.tcl: -------------------------------------------------------------------------------- 1 | source tcl_files/config/vsim_ips.tcl 2 | 3 | set cmd "vsim -quiet $TB \ 4 | -L pulpino_lib \ 5 | $VSIM_IP_LIBS \ 6 | +nowarnTRAN \ 7 | +nowarnTSCALE \ 8 | +nowarnTFMPC \ 9 | +MEMLOAD=$MEMLOAD \ 10 | -gUSE_ZERO_RISCY=$env(USE_ZERO_RISCY) \ 11 | -t ps \ 12 | -voptargs=\"+acc -suppress 2103\" \ 13 | $VSIM_FLAGS" 14 | 15 | # set cmd "$cmd -sv_lib ./work/libri5cyv2sim" 16 | eval $cmd 17 | 18 | # check exit status in tb and quit the simulation accordingly 19 | proc run_and_exit {} { 20 | run -all 21 | quit -code [examine -radix decimal sim:/tb/exit_status] 22 | } 23 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB_TEST $::env(TB_TEST) 6 | set VSIM_FLAGS "-GTEST=\"$TB_TEST\"" 7 | 8 | set TB tb 9 | set MEMLOAD "PRELOAD" 10 | 11 | source ./tcl_files/config/vsim.tcl 12 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run_debug.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB tb 6 | set VSIM_FLAGS "-gTEST=\"DEBUG\"" 7 | set MEMLOAD "PRELOAD" 8 | 9 | source ./tcl_files/config/vsim.tcl 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run_debug_irq.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB tb 6 | set VSIM_FLAGS "-gTEST=\"DEBUG_IRQ\"" 7 | set MEMLOAD "PRELOAD" 8 | 9 | source ./tcl_files/config/vsim.tcl 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run_mem_dpi.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB tb 6 | set VSIM_FLAGS "-gTEST=\"MEM_DPI\"" 7 | set MEMLOAD "PRELOAD" 8 | 9 | source ./tcl_files/config/vsim.tcl 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run_memdpi.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB tb 6 | set VSIM_FLAGS "-gTEST=MEM_DPI" 7 | set MEMLOAD "PRELOAD" 8 | 9 | source ./tcl_files/config/vsim.tcl 10 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run_spi.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB tb 6 | set TB_TEST $::env(TB_TEST) 7 | set VSIM_FLAGS "-GTEST=\"$TB_TEST\"" 8 | set MEMLOAD "SPI" 9 | 10 | source ./tcl_files/config/vsim.tcl 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/tcl_files/run_zero-riscy_spi.tcl: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | # \ 3 | exec vsim -64 -do "$0" 4 | 5 | set TB tb 6 | set TB_TEST $::env(TB_TEST) 7 | set VSIM_FLAGS "-GTEST=\"$TB_TEST\"" 8 | set MEMLOAD "SPI" 9 | 10 | source ./tcl_files/config/vsim_zero.tcl 11 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/vcompile/build_rtl_sim.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | if (! $?VSIM_PATH ) then 4 | setenv VSIM_PATH `pwd` 5 | endif 6 | 7 | if (! $?PULP_PATH ) then 8 | setenv PULP_PATH `pwd`/../ 9 | endif 10 | 11 | setenv MSIM_LIBS_PATH ${VSIM_PATH}/modelsim_libs 12 | 13 | setenv IPS_PATH ${PULP_PATH}/ips 14 | setenv RTL_PATH ${PULP_PATH}/rtl 15 | setenv TB_PATH ${PULP_PATH}/tb 16 | 17 | clear 18 | source ${PULP_PATH}/vsim/vcompile/colors.csh 19 | 20 | rm -rf modelsim_libs 21 | vlib modelsim_libs 22 | 23 | rm -rf work 24 | vlib work 25 | 26 | echo "" 27 | echo "${Green}--> Compiling PULPino Platform... ${NC}" 28 | echo "" 29 | 30 | # IP blocks 31 | source ${PULP_PATH}/vsim/vcompile/vcompile_ips.csh || exit 1 32 | 33 | source ${PULP_PATH}/vsim/vcompile/rtl/vcompile_pulpino.sh || exit 1 34 | source ${PULP_PATH}/vsim/vcompile/rtl/vcompile_tb.sh || exit 1 35 | 36 | echo "" 37 | echo "${Green}--> PULPino platform compilation complete! ${NC}" 38 | echo "" 39 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/vcompile/colors.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | set Red='\e[0;31m' 4 | set Black='\e[0;30m' 5 | set Blue='\e[0;34m' 6 | set Green='\e[0;32m' 7 | set Cyan='\e[0;36m' 8 | set Red='\e[0;31m' 9 | set Purple='\e[0;35m' 10 | set Brown='\e[0;33m' 11 | set Yellow='\e[1;33m' 12 | set White='\e[1;37m' 13 | set NC='\e[0m' 14 | 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/vcompile/setup.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | if (! $?VSIM_PATH ) then 4 | setenv VSIM_PATH `pwd` 5 | endif 6 | 7 | if (! $?PULP_PATH ) then 8 | setenv PULP_PATH `pwd`/../../ 9 | endif 10 | 11 | setenv MSIM_LIBS_PATH ${VSIM_PATH}/modelsim_libs 12 | 13 | setenv IPS_PATH ${PULP_PATH}/ips 14 | setenv RTL_PATH ${PULP_PATH}/rtl 15 | setenv TB_PATH ${PULP_PATH}/tb 16 | 17 | source ${PULP_PATH}/vsim/vcompile/colors.csh 18 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/vcompile/vcompile_riscv.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | if (! $?VSIM_PATH ) then 4 | setenv VSIM_PATH `pwd` 5 | endif 6 | 7 | if (! $?PULP_PATH ) then 8 | setenv PULP_PATH `pwd`/.. 9 | endif 10 | 11 | setenv MSIM_LIBS_PATH ${VSIM_PATH}/modelsim_libs 12 | 13 | setenv IPS_PATH ${PULP_PATH}/ips 14 | 15 | source ${PULP_PATH}/vsim/vcompile/colors.csh 16 | 17 | echo "" 18 | echo "${Green}--> Compiling riscv core... ${NC}" 19 | 20 | source ${PULP_PATH}/vsim/vcompile/ips/vcompile_riscv.csh || exit 1 21 | 22 | echo "${Green}--> RiscV core compilation Complete! ${NC}" 23 | echo "" 24 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/vcompile/vcompile_zero-riscy.csh: -------------------------------------------------------------------------------- 1 | #!/bin/tcsh 2 | 3 | if (! $?VSIM_PATH ) then 4 | setenv VSIM_PATH `pwd` 5 | endif 6 | 7 | if (! $?PULP_PATH ) then 8 | setenv PULP_PATH `pwd`/.. 9 | endif 10 | 11 | setenv MSIM_LIBS_PATH ${VSIM_PATH}/modelsim_libs 12 | 13 | setenv IPS_PATH ${PULP_PATH}/ips 14 | 15 | source ${PULP_PATH}/vsim/vcompile/colors.csh 16 | 17 | echo "" 18 | echo "${Green}--> Compiling zero-riscy core... ${NC}" 19 | 20 | source ${PULP_PATH}/vsim/vcompile/ips/vcompile_zero-riscy.csh || exit 1 21 | 22 | echo "${Green}--> zero-riscy core compilation Complete! ${NC}" 23 | echo "" 24 | -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/verilator/.gitignore: -------------------------------------------------------------------------------- 1 | !.gitignore -------------------------------------------------------------------------------- /Microcontroller/FPGA/vsim/waves/.gitingore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/FPGA/vsim/waves/.gitingore -------------------------------------------------------------------------------- /Microcontroller/Interface/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/Interface/.DS_Store -------------------------------------------------------------------------------- /Microcontroller/Interface/interface .pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/Interface/interface .pdf -------------------------------------------------------------------------------- /Microcontroller/README.md: -------------------------------------------------------------------------------- 1 | # FPGA 2 | The FPGA folder contains all the files and instructions needed to implement the microcontroller on an FPGA board, it contains as well the needed instructions to setup the toolchain and compile c codes for the FPGA board 3 | 4 | # Interface 5 | The Interface folder contains a descrption of the preliminary interface of the microcontroller and its supported commands 6 | -------------------------------------------------------------------------------- /Microcontroller/SPI_Slave_Verilog/Cnt_SPI_diagram.PNG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/Microcontroller/SPI_Slave_Verilog/Cnt_SPI_diagram.PNG -------------------------------------------------------------------------------- /Microcontroller/SPI_Slave_Verilog/SPIMaster_Arduino.ino: -------------------------------------------------------------------------------- 1 | #include //Library for SPI . 2 | #define txload 6 3 | #define trdy 5 4 | int i=1; 5 | int dataready; 6 | byte x; 7 | 8 | void setup (void) 9 | 10 | { 11 | Serial.begin(115200); 12 | SPI.begin(); 13 | pinMode(txload,OUTPUT); 14 | pinMode(trdy,INPUT); 15 | digitalWrite(SS,HIGH); 16 | SPI.setClockDivider(SPI_CLOCK_DIV16); 17 | 18 | } 19 | 20 | void loop(void) 21 | { 22 | 23 | if(i<2) 24 | { 25 | 26 | int Mastereceive; 27 | double voltage = 0; 28 | //uint16_t buffer; //16 bits of data 29 | //uint8_t size = 2; //number of bytes 30 | 31 | digitalWrite(SS, LOW); //Starts communication with Slave connected to master 32 | delay(100); 33 | // Mastereceive=SPI.transfer(0); //Send the mastersend value to slave also receives value from slave 34 | 35 | //Serial.println(Mastereceive); 36 | Mastereceive = SPI.transfer16(0); 37 | Serial.println(Mastereceive); 38 | 39 | voltage = (1000000/Mastereceive - 39.25)/(36.5345); 40 | Serial.println(voltage); 41 | 42 | delay(100); 43 | digitalWrite(SS, HIGH); 44 | i=i+1; 45 | } 46 | 47 | delay(1000); 48 | } 49 | -------------------------------------------------------------------------------- /PVT_Sensor/.DS_Store: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/PVT_Sensor/.DS_Store -------------------------------------------------------------------------------- /PVT_Sensor/Images/CPM_Sch_WhBG.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/PVT_Sensor/Images/CPM_Sch_WhBG.png -------------------------------------------------------------------------------- /PVT_Sensor/Images/tsensor_comp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/PVT_Sensor/Images/tsensor_comp.png -------------------------------------------------------------------------------- /PVT_Sensor/Images/uW_TSensor.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/PVT_Sensor/Images/uW_TSensor.JPG -------------------------------------------------------------------------------- /PVT_Sensor/Images/uW_VSensor.JPG: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/PVT_Sensor/Images/uW_VSensor.JPG -------------------------------------------------------------------------------- /PVT_Sensor/Images/vsensor_comp.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/scale-lab/PVTsensors/e0111a8b63bb7ceccbb5ea0107a89c9ed80d3bad/PVT_Sensor/Images/vsensor_comp.png -------------------------------------------------------------------------------- /PVT_Sensor/SpiceNetlist/README.md: -------------------------------------------------------------------------------- 1 | ## General Overview 2 | 3 | This folder contains Netlist files for the Temperature Sensor and Supply Voltage Sensor. Designs were verified in tsmc 180nm technology. 4 | 5 | Model names used are listed below: 6 | 7 | - 'nch' stands for N-channel 8 | 9 | - 'pch' stands for P-channel 10 | 11 | - 'mimcap' stands for MIM capacitor 12 | 13 | - 'pdio' stands for P-diode 14 | 15 | -------------------------------------------------------------------------------- /PVT_Sensor/Testbench/README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | # General Overview 4 | 5 | This folder contains testbench SPICE files for the voltage sensor and temperature sensor seperately. 6 | 7 | # Setup 8 | 9 | There are 2 ways to use the testbench: 10 | - __Copy the spice netlist__: 11 | 12 | The first option is to copy the netlist of the corresponding sensor to its testbench. For example, to run the testbench for temperature sensor, you can copy the spice netlist of the temperature sensor from 13 | 14 | ``` 15 | .subckt NOR2 a1 a2 zn vdd vss 16 | ``` 17 | 18 | to 19 | 20 | ``` 21 | xc4 iref vdd mimcap lt=10e-6 wt=10e-6 mf=1 22 | ``` 23 | 24 | into the testbench spice file between 25 | ``` 26 | parameters vdd 27 | ``` 28 | and 29 | ``` 30 | V1 (gnd 0) vsource dc=0 type=dc 31 | ``` 32 | 33 | The same applies for the voltage sensor 34 | 35 | - __Add sensor as sub-circuit__: 36 | If you are using Virtuoso(or similar simulator), you can import both the sensor and its testbench, and add the sensor block into the testbench as a subcircuit. -------------------------------------------------------------------------------- /PVT_Sensor/Testbench/TSesnor_Testbench.sp: -------------------------------------------------------------------------------- 1 | // Generated for: spectre 2 | // Design view name: schematic 3 | simulator lang=spectre 4 | global 0 5 | parameters vdd 6 | // insest target netlist here 7 | V1 (gnd 0) vsource dc=0 type=dc 8 | V0 (vdd_pin 0) vsource dc=1.8 type=dc 9 | V8 (vdd 0) vsource type=pwl wave=[ 0 0 50n 0 50.05n vdd 52n vdd 52.05n 0 \ 10 | 70n 0 70.05n vdd ] 11 | I18 (IREF 0) isource dc=1u type=dc 12 | simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ 13 | tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ 14 | digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ 15 | checklimitdest=psf 16 | modelParameter info what=models where=rawfile 17 | element info what=inst where=rawfile 18 | outputParameter info what=output where=rawfile 19 | designParamVals info what=parameters where=rawfile 20 | primitives info what=primitives where=rawfile 21 | subckts info what=subckts where=rawfile 22 | saveOptions options save=allpub 23 | -------------------------------------------------------------------------------- /PVT_Sensor/Testbench/VSesnor_Testbench.sp: -------------------------------------------------------------------------------- 1 | // Generated for: spectre 2 | // Design view name: schematic 3 | simulator lang=spectre 4 | global 0 vdd! 5 | parameters VDD 6 | // insest target netlist here 7 | I9 (net2 0) isource dc=250n type=dc 8 | I0 (net2 Q QB QBP QP 0 vdd! vdd!) Layout_vdd_sensor_SN 9 | V0 (vdd! 0) vsource type=pwl wave=[ 0 0 50n 0 50.05n VDD 52n VDD 52.05n 0 \ 10 | 70n 0 70.05n VDD ] 11 | simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \ 12 | tnom=25 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ 13 | digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ 14 | checklimitdest=psf 15 | modelParameter info what=models where=rawfile 16 | element info what=inst where=rawfile 17 | outputParameter info what=output where=rawfile 18 | designParamVals info what=parameters where=rawfile 19 | primitives info what=primitives where=rawfile 20 | subckts info what=subckts where=rawfile 21 | saveOptions options save=allpub 22 | -------------------------------------------------------------------------------- /PVT_Sensor/VerilogCode/README.md: -------------------------------------------------------------------------------- 1 | ## Instruction: 2 | 3 | - __CPM Verilog__: This folder contains verilog code of CPM sensor (for ideal simulation only, detailed acknowledgement is in the folder) 4 | 5 | - __VerilogAMS__: This folder contains verilog ams code of uW Temperature/Voltage sensors 6 | -------------------------------------------------------------------------------- /PVT_Sensor/VerilogCode/VT_VerilogAMS/README.md: -------------------------------------------------------------------------------- 1 | ## General Overview 2 | 3 | This folder contains Verilog ams files for the Temperature Sensor and Supply Voltage Sensor 4 | 5 | Designs were verified on tsmc 180nm technology. Please replace '/*Target Process Technology*/' with your target technology library! 6 | 7 | Model names used are listed below: 8 | 9 | - 'nch' stands for N-channel 10 | 11 | - 'pch' stands for P-channel 12 | 13 | - 'mimcap' stands for MIM capacitor 14 | 15 | - 'pdio' stands for P-diode 16 | 17 | -------------------------------------------------------------------------------- /PVT_Sensor/pyXyce/ANALYSIS.inc: -------------------------------------------------------------------------------- 1 | .STEP LIN TEMP 0 100 25 2 | .TRAN 1e-10 1e-05 2e-06 1e-09 3 | .MEASURE TRAN Q_freq FREQ v(q) ON=0.9 OFF=0.9 PRECISION=12 4 | .INCLUDE MODELS.lib 5 | .print tran format=csv Q_freq 6 | V1 vdd gnd 1.8 7 | V2 vdd_pin gnd 1.8 8 | I1 iref gnd 1e-06 9 | .OPTIONS MEASURE MEASPRINT=STDOUT 10 | .OPTIONS DEVICE TEMP=27 11 | .RESULT {1/Q_freq} 12 | 13 | 14 | ; whitespace to overwrite ANALYSIS.inc correctly 15 | -------------------------------------------------------------------------------- /PVT_Sensor/pyXyce/README.md: -------------------------------------------------------------------------------- 1 | # pvt-dev 2 | Open **BrownPVT.ipynb** with Jupyter Notebook for more instructions for simulating 3 | BrownPVT sensors with python 4 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # PVTsensors 2 | This repository contains a collection of open-source circuits and software tools for PVT monitoring in custom ICs. This work was supported by the DARPA POSH open-source hardware program, under the umbrella of the Electronics Resurgence Initiative. 3 | 4 | ## Hardware Sensor Designs 5 | The Sensors folder contains CMOS circuit designs for (1) an area- and power-efficient temperature sensor, (2) an area- and power-efficient CMOS supply voltage monitor, and (3) a critical path monitor. 6 | 7 | ## Digital Infrastructure 8 | The PVT system contains both the sensor designs and an embedded lightweight RISC-V core based on the PULPino. The Microcontroller/FPGA folder contains a tutorial on how to implement this microcontroller on a Xilinx development board. 9 | 10 | ## System Software 11 | The Microcontroller/Interface folder contains a preliminary proposed specification for an external interface to the PVT system. 12 | 13 | ## Acknowledgements 14 | This work was supported by the DARPA POSH open-source hardware program, under the umbrella of the Electronics Resurgence Initiative. Contributors include: 15 | 16 | - Sherief Reda (PI) (http://scale.engin.brown.edu/) 17 | - Jacob Rosenstein (Co-PI) (http://rosenstein.engin.brown.edu) 18 | - Shanshan Dai (PhD student) 19 | - Sofiane Chetoui (PhD student) 20 | - Steven Lian (PhD student) 21 | - Caleb Tulloss (summer research assistant) 22 | -------------------------------------------------------------------------------- /Software/PIDNN/README.md: -------------------------------------------------------------------------------- 1 | # General Overview 2 | 3 | This folder contains the following files: 4 | 5 | - genann.c : C library file 6 | - genann.h : header library file 7 | - pidnn.c : PID neural network C file 8 | 9 | # PID NN hyperparameters 10 | 11 | - throtling_threshold : temperature throttling threshold 12 | - sampling_rate : controller update rate in us 13 | - save_samp : saving rate of the NN weights 14 | - PATHsx : path to the sensors 15 | - PATHfreq: path to the file that is used to control the operating frequency 16 | 17 | # Prerequisites 18 | 19 | GCC should be used as a compiler, the GCC version to be used depends on the microarchitecture of the target platform. 20 | 21 | # Adapting the code 22 | To integrate the code to your own system, the following parameters in the pidnn.c file should be edited: 23 | - PATHs1 to PATHs4: these files should indicate the path to the sensors to be used for the control 24 | - PATHfreq : this file should indicate the path to the file used to scale the frequency 25 | - freq : this table within the command_freq function should indicate the available frequency levels 26 | 27 | # Compilation 28 | 29 | Open terminal, change direction to your target folder and type the following code: 30 | 31 | ``` 32 | git clone https://github.com/scale-lab/PVTsensors 33 | cd PVTsensors/Software/PIDNN/ 34 | ``` 35 | then to compile the code you can use the following line : gcc -lm -o pidnn pidnn.c genann.c 36 | -------------------------------------------------------------------------------- /Software/README.md: -------------------------------------------------------------------------------- 1 | # General Overview 2 | 3 | This folder contains 1 folder: 4 | 5 | - PIDNN : Neural network PID thermal controller 6 | --------------------------------------------------------------------------------