├── README.md ├── interconnect.v ├── interconnect ├── addr_wdata_mux_m4.v ├── ar_mux_m4.v ├── interconnect.v ├── rdata_mux_m4.v └── wr_mux_s4.v ├── router_master ├── addr_wdata_mux_2to1.v ├── ar_mux_2to1.v ├── rdata_demux_1to2.v ├── router_master_2to1.v └── wr_demux_1to2.v ├── router_slave ├── addr_wdata_demux_1to2.v ├── ar_demux_1to2.v ├── rdata_mux_2to1.v ├── router_slave_1to2.v └── wr_mux_2to1.v ├── simulation ├── ncverilog.key ├── ncverilog.log ├── simvision16388.diag ├── sram0.txt ├── sram1.txt ├── sram2.txt └── sram3.txt ├── sram0.txt ├── sram1.txt ├── sram2.txt ├── sram3.txt └── testbench ├── master.v ├── sram_1024x32.v ├── sram_controller.v └── tb_topmodule.v /README.md: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/seonskim/verilog_axi-interconnect/HEAD/README.md -------------------------------------------------------------------------------- /interconnect.v: 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