├── .gitignore ├── img ├── stand.jpg └── uart.png ├── cmsis ├── stm32f10x.h └── system_stm32f10x.h ├── stdperiph ├── inc │ ├── stm32f10x_fsmc.h │ ├── stm32f10x_crc.h │ ├── stm32f10x_wwdg.h │ ├── stm32f10x_dbgmcu.h │ ├── stm32f10x_rtc.h │ ├── stm32f10x_iwdg.h │ ├── stm32f10x_pwr.h │ ├── stm32f10x_cec.h │ ├── stm32f10x_exti.h │ ├── stm32f10x_bkp.h │ ├── misc.h │ ├── stm32f10x_dac.h │ ├── stm32f10x_usart.h │ └── stm32f10x_spi.h └── src │ ├── stm32f10x_adc.c │ ├── stm32f10x_can.c │ ├── stm32f10x_dac.c │ ├── stm32f10x_dma.c │ ├── stm32f10x_exti.c │ ├── stm32f10x_flash.c │ ├── stm32f10x_fsmc.c │ ├── stm32f10x_i2c.c │ ├── stm32f10x_rcc.c │ ├── stm32f10x_rtc.c │ ├── stm32f10x_sdio.c │ ├── stm32f10x_tim.c │ ├── stm32f10x_usart.c │ ├── stm32f10x_crc.c │ ├── stm32f10x_iwdg.c │ ├── stm32f10x_dbgmcu.c │ ├── stm32f10x_wwdg.c │ ├── misc.c │ ├── stm32f10x_bkp.c │ ├── stm32f10x_pwr.c │ └── stm32f10x_cec.c ├── src ├── addrIntercept.h ├── stm32F10x_map.c ├── stm32f10x_it.h ├── stm32f10x_conf.h ├── stm32f10x_it.c └── main.c ├── README.md ├── Makefile └── LICENSE /.gitignore: -------------------------------------------------------------------------------- 1 | *.d 2 | *.o 3 | *.ld 4 | *.s 5 | *.elf 6 | *.user -------------------------------------------------------------------------------- /img/stand.jpg: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ser-mk/AddressIntercept-example-UART-DMA/HEAD/img/stand.jpg -------------------------------------------------------------------------------- /img/uart.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ser-mk/AddressIntercept-example-UART-DMA/HEAD/img/uart.png -------------------------------------------------------------------------------- /cmsis/stm32f10x.h: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/ser-mk/AddressIntercept-example-UART-DMA/HEAD/stdperiph/src/stm32f10x_sdio.c -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_tim.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ser-mk/AddressIntercept-example-UART-DMA/HEAD/stdperiph/src/stm32f10x_tim.c -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_usart.c: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/ser-mk/AddressIntercept-example-UART-DMA/HEAD/stdperiph/src/stm32f10x_usart.c -------------------------------------------------------------------------------- /src/addrIntercept.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Covered by Apache License 2.0 3 | * Copyright (C) 2018 Evgeny Chormonov (en.chormonov@gmail.com) 4 | * For more information https://github.com/ser-mk/AddressIntercept 5 | */ 6 | 7 | #include 8 | #pragma once 9 | 10 | #ifdef __cplusplus 11 | extern "C" { 12 | #endif 13 | 14 | typedef enum { 15 | NO_ERROR 16 | } ChipErrorType; 17 | 18 | #if defined(TARGET_IA32) 19 | typedef uint32_t * addr_t; 20 | #else 21 | typedef uint64_t * addr_t; 22 | #endif 23 | 24 | #if defined(__LP64__) || defined(_LP64) 25 | typedef uint64_t AddrType; 26 | #else 27 | typedef uint32_t AddrType; 28 | #endif 29 | 30 | typedef struct 31 | { 32 | addr_t start_addr; 33 | addr_t end_addr; 34 | addr_t reference_addr; 35 | } memoryTranslate; 36 | 37 | 38 | typedef uint32_t sizeMemoryTranslate_t; 39 | 40 | 41 | 42 | memoryTranslate * getMemoryMap(sizeMemoryTranslate_t * size); 43 | void freeMemoryMap(); 44 | 45 | void resetChip(); 46 | 47 | ChipErrorType showError(); 48 | 49 | 50 | #define NAME_MEMORY_MAP_FUNCTION "getMemoryMap" 51 | #define NAME_MEMORY_MAP_FREE_FUNCTION "freeMemoryMap" 52 | 53 | #define NAME_RESET_CHIP_FUNCTION "resetChip" 54 | #define NAME_ERROR_FUNCTION "showError" 55 | 56 | 57 | #ifdef __cplusplus 58 | } 59 | #endif 60 | -------------------------------------------------------------------------------- /src/stm32F10x_map.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Covered by Apache License 2.0 3 | * Copyright (C) 2018 Evgeny Chormonov (en.chormonov@gmail.com) 4 | * For more information https://github.com/ser-mk/AddressIntercept 5 | */ 6 | 7 | #include "addrIntercept.h" 8 | #include 9 | #include 10 | 11 | addr_t pAddrSRAM = NULL; 12 | addr_t pAddrPERIPH = NULL; 13 | 14 | 15 | #define QTY_REMOTE_REGION ((size_t)2U) 16 | static const addr_t REMOTE_PERIPHERAL_ADDR = (addr_t)0x40000000U; 17 | #define REMOTE_PERIPHERAL_SIZE ((size_t)0x30000U) 18 | 19 | static const addr_t REMOTE_MEMORY_ADDR = (addr_t)0x20000000U; 20 | #define REMOTE_MEMORY_SIZE ((size_t)96*1024) 21 | 22 | static char PERIPHERAL_BUFFER[REMOTE_PERIPHERAL_SIZE]; 23 | static char MEMORY_BUFFER[REMOTE_MEMORY_SIZE]; 24 | 25 | static memoryTranslate memoryMap[QTY_REMOTE_REGION]; 26 | static sizeMemoryTranslate_t sizeMemoryMap = 0; 27 | 28 | static void setAddr(memoryTranslate * const map, const char * buf, const size_t size, const addr_t remote_addr){ 29 | map->start_addr = (addr_t)buf; 30 | map->end_addr = memoryMap->start_addr + size; 31 | map->reference_addr = remote_addr; 32 | } 33 | 34 | memoryTranslate * getMemoryMap(sizeMemoryTranslate_t * size){ 35 | 36 | setAddr(memoryMap, PERIPHERAL_BUFFER, REMOTE_PERIPHERAL_SIZE, REMOTE_PERIPHERAL_ADDR); 37 | 38 | setAddr(memoryMap + 1, MEMORY_BUFFER, REMOTE_MEMORY_SIZE, REMOTE_MEMORY_ADDR); 39 | 40 | *size = sizeMemoryMap = QTY_REMOTE_REGION; 41 | 42 | return memoryMap; 43 | } 44 | 45 | void initPintoolClient(){ 46 | 47 | sizeMemoryTranslate_t s = 0; 48 | 49 | memoryTranslate *p = getMemoryMap(&s); 50 | 51 | pAddrPERIPH = p[0].start_addr; 52 | pAddrSRAM = p[1].start_addr; 53 | 54 | printf("Initializing Pintool client \n"); 55 | } 56 | -------------------------------------------------------------------------------- /src/stm32f10x_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 08-April-2011 7 | * @brief This file contains the headers of the interrupt handlers. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_IT_H 24 | #define __STM32F10x_IT_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /* Exported types ------------------------------------------------------------*/ 34 | /* Exported constants --------------------------------------------------------*/ 35 | /* Exported macro ------------------------------------------------------------*/ 36 | /* Exported functions ------------------------------------------------------- */ 37 | 38 | void NMI_Handler(void); 39 | void HardFault_Handler(void); 40 | void MemManage_Handler(void); 41 | void BusFault_Handler(void); 42 | void UsageFault_Handler(void); 43 | void SVC_Handler(void); 44 | void DebugMon_Handler(void); 45 | void PendSV_Handler(void); 46 | void SysTick_Handler(void); 47 | 48 | #ifdef __cplusplus 49 | } 50 | #endif 51 | 52 | #endif /* __STM32F10x_IT_H */ 53 | 54 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 55 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Address Intercept example UART-DMA 2 | 3 | Habrahabr articles https://habr.com/ru/post/433504/ & https://habr.com/ru/post/434080/ 4 | 5 | This is an example of using [AddressIntercept technology](https://github.com/ser-mk/AddressIntercept "AddressIntercept technology") to control microcontroller periphery from a host PC. The example tunes periphery of microcontroller STM32F103C8 , namely, UART1, UART2, DMA and GPIO LED (PC13 pin). Then UART1 sends byte message and UART2 receives it using DMA. Also the led blinks. At the end, received and sent message are checked. 6 | 7 | Here ​Standard Peripherals Library​ is applied for high-level interaction with MCU periphery. Thanks to [AddressIntercept](https://github.com/ser-mk/AddressIntercept) , we can use this MCU library on a host PC. There is nothing that can prevent linking any library from the host PC. 8 | 9 | My test stand 10 | ![alt text](img/stand.jpg "My stand") 11 | 12 | The green board is a Linux machine where OpenOCD server was ran. 13 | `You can run an OpenOCD server on host PC if you use another local USB JTAG/SWD adapter (example st-link, jlink, etc)` 14 | The blue board is a [bluepill](https://www.google.com/search?client=ubuntu&channel=fs&q=bluepill&ie=utf-8&oe=utf-8 "bluepill"). 15 | I connected Tx UART1 (PA9 pin) with Rx UART2 (PA3 pin) using the white wire. 16 | 17 | Let's build and run this example... 18 | My host PC is Ubuntu 16.04 64-bit and the test stand above (JTAG/SWD adapter and prepared STM32F103C8 (PA9 pin connected to PA3 pin). 19 | 20 | А simple way: 21 | 22 | 1. Download [pintool v3.7](https://software.intel.com/en-us/articles/pin-a-dynamic-binary-instrumentation-tool "pintool v3.7") 23 | 2. Unpack archive 24 | 3. cd pin-3.7-97619-g0d0c92f4f-gcc-linux/source/tools/ 25 | 4. git clone git@github.com:ser-mk/AddressIntercept.git 26 | 5. cd AddressIntercept 27 | 6. make TARGET=obj-ia32 # If you have 64-bit system, need to install some 32-bit packets 28 | 7. git clone git@github.com:ser-mk/AddressIntercept-example-UART-DMA.git 29 | 8. cd AddressIntercept-example-UART-DMA 30 | 9. make 31 | 10. cd - # to pin-3.7-97619-g0d0c92f4f-gcc-linux/source/tools/ 32 | 11. mkfifo in.fifo out.fifo 33 | 12. python3.5m OCDclient.py -ip $IP_YOUR_OPENOCD_SERVER & 34 | 13. ../../../pin -t obj-ia32/addrIntercept.so -- AddressIntercept-example-UART-DMA/test.elf 35 | 36 | and we'll have: 37 | ![alt text](img/uart.png "Show out") 38 | 39 | 40 | Article in Russian Language https://habr.com/post/434080/ 41 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CRC_H 24 | #define __STM32F10x_CRC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup CRC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup CRC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup CRC_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** 54 | * @} 55 | */ 56 | 57 | /** @defgroup CRC_Exported_Macros 58 | * @{ 59 | */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup CRC_Exported_Functions 66 | * @{ 67 | */ 68 | 69 | void CRC_ResetDR(void); 70 | uint32_t CRC_CalcCRC(uint32_t Data); 71 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 72 | uint32_t CRC_GetCRC(void); 73 | void CRC_SetIDRegister(uint8_t IDValue); 74 | uint8_t CRC_GetIDRegister(void); 75 | 76 | #ifdef __cplusplus 77 | } 78 | #endif 79 | 80 | #endif /* __STM32F10x_CRC_H */ 81 | /** 82 | * @} 83 | */ 84 | 85 | /** 86 | * @} 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 94 | -------------------------------------------------------------------------------- /cmsis/system_stm32f10x.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f10x.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 11-March-2011 7 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /** @addtogroup CMSIS 23 | * @{ 24 | */ 25 | 26 | /** @addtogroup stm32f10x_system 27 | * @{ 28 | */ 29 | 30 | /** 31 | * @brief Define to prevent recursive inclusion 32 | */ 33 | #ifndef __SYSTEM_STM32F10X_H 34 | #define __SYSTEM_STM32F10X_H 35 | 36 | #ifdef __cplusplus 37 | extern "C" { 38 | #endif 39 | 40 | /** @addtogroup STM32F10x_System_Includes 41 | * @{ 42 | */ 43 | 44 | /** 45 | * @} 46 | */ 47 | 48 | 49 | /** @addtogroup STM32F10x_System_Exported_types 50 | * @{ 51 | */ 52 | 53 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @addtogroup STM32F10x_System_Exported_Constants 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @addtogroup STM32F10x_System_Exported_Macros 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @addtogroup STM32F10x_System_Exported_Functions 76 | * @{ 77 | */ 78 | 79 | extern void SystemInit(void); 80 | extern void SystemCoreClockUpdate(void); 81 | /** 82 | * @} 83 | */ 84 | 85 | #ifdef __cplusplus 86 | } 87 | #endif 88 | 89 | #endif /*__SYSTEM_STM32F10X_H */ 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** 96 | * @} 97 | */ 98 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 99 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the WWDG firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_WWDG_H 24 | #define __STM32F10x_WWDG_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup WWDG 38 | * @{ 39 | */ 40 | 41 | /** @defgroup WWDG_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup WWDG_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup WWDG_Prescaler 54 | * @{ 55 | */ 56 | 57 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 58 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 59 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 60 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 61 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 62 | ((PRESCALER) == WWDG_Prescaler_2) || \ 63 | ((PRESCALER) == WWDG_Prescaler_4) || \ 64 | ((PRESCALER) == WWDG_Prescaler_8)) 65 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 66 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 67 | 68 | /** 69 | * @} 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup WWDG_Exported_Macros 77 | * @{ 78 | */ 79 | /** 80 | * @} 81 | */ 82 | 83 | /** @defgroup WWDG_Exported_Functions 84 | * @{ 85 | */ 86 | 87 | void WWDG_DeInit(void); 88 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 89 | void WWDG_SetWindowValue(uint8_t WindowValue); 90 | void WWDG_EnableIT(void); 91 | void WWDG_SetCounter(uint8_t Counter); 92 | void WWDG_Enable(uint8_t Counter); 93 | FlagStatus WWDG_GetFlagStatus(void); 94 | void WWDG_ClearFlag(void); 95 | 96 | #ifdef __cplusplus 97 | } 98 | #endif 99 | 100 | #endif /* __STM32F10x_WWDG_H */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | /** 111 | * @} 112 | */ 113 | 114 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 115 | -------------------------------------------------------------------------------- /src/stm32f10x_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_conf.h 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 08-April-2011 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2011 STMicroelectronics

19 | ****************************************************************************** 20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CONF_H 24 | #define __STM32F10x_CONF_H 25 | 26 | /* Includes ------------------------------------------------------------------*/ 27 | /* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ 28 | //#include "stm32f10x_adc.h" 29 | //#include "stm32f10x_bkp.h" 30 | //#include "stm32f10x_can.h" 31 | //#include "stm32f10x_cec.h" 32 | //#include "stm32f10x_crc.h" 33 | //#include "stm32f10x_dac.h" 34 | //#include "stm32f10x_dbgmcu.h" 35 | #include "stm32f10x_dma.h" 36 | //#include "stm32f10x_exti.h" 37 | //#include "stm32f10x_flash.h" 38 | //#include "stm32f10x_fsmc.h" 39 | #include "stm32f10x_gpio.h" 40 | //#include "stm32f10x_i2c.h" 41 | //#include "stm32f10x_iwdg.h" 42 | //#include "stm32f10x_pwr.h" 43 | #include "stm32f10x_rcc.h" 44 | //#include "stm32f10x_rtc.h" 45 | //#include "stm32f10x_sdio.h" 46 | //#include "stm32f10x_spi.h" 47 | //#include "stm32f10x_tim.h" 48 | #include "stm32f10x_usart.h" 49 | //#include "stm32f10x_wwdg.h" 50 | //#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 51 | 52 | /* Exported types ------------------------------------------------------------*/ 53 | /* Exported constants --------------------------------------------------------*/ 54 | /* Uncomment the line below to expanse the "assert_param" macro in the 55 | Standard Peripheral Library drivers code */ 56 | /* #define USE_FULL_ASSERT 1 */ 57 | 58 | /* Exported macro ------------------------------------------------------------*/ 59 | #ifdef USE_FULL_ASSERT 60 | 61 | /** 62 | * @brief The assert_param macro is used for function's parameters check. 63 | * @param expr: If expr is false, it calls assert_failed function which reports 64 | * the name of the source file and the source line number of the call 65 | * that failed. If expr is true, it returns no value. 66 | * @retval None 67 | */ 68 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 69 | /* Exported functions ------------------------------------------------------- */ 70 | void assert_failed(uint8_t* file, uint32_t line); 71 | #else 72 | #define assert_param(expr) ((void)0) 73 | #endif /* USE_FULL_ASSERT */ 74 | 75 | #endif /* __STM32F10x_CONF_H */ 76 | 77 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 78 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_crc.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the CRC firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_crc.h" 23 | 24 | /** @addtogroup STM32F10x_StdPeriph_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup CRC 29 | * @brief CRC driver modules 30 | * @{ 31 | */ 32 | 33 | /** @defgroup CRC_Private_TypesDefinitions 34 | * @{ 35 | */ 36 | 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup CRC_Private_Defines 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup CRC_Private_Macros 50 | * @{ 51 | */ 52 | 53 | /** 54 | * @} 55 | */ 56 | 57 | /** @defgroup CRC_Private_Variables 58 | * @{ 59 | */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup CRC_Private_FunctionPrototypes 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup CRC_Private_Functions 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @brief Resets the CRC Data register (DR). 79 | * @param None 80 | * @retval None 81 | */ 82 | void CRC_ResetDR(void) 83 | { 84 | /* Reset CRC generator */ 85 | CRC->CR = CRC_CR_RESET; 86 | } 87 | 88 | /** 89 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 90 | * @param Data: data word(32-bit) to compute its CRC 91 | * @retval 32-bit CRC 92 | */ 93 | uint32_t CRC_CalcCRC(uint32_t Data) 94 | { 95 | CRC->DR = Data; 96 | 97 | return (CRC->DR); 98 | } 99 | 100 | /** 101 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 102 | * @param pBuffer: pointer to the buffer containing the data to be computed 103 | * @param BufferLength: length of the buffer to be computed 104 | * @retval 32-bit CRC 105 | */ 106 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 107 | { 108 | uint32_t index = 0; 109 | 110 | for(index = 0; index < BufferLength; index++) 111 | { 112 | CRC->DR = pBuffer[index]; 113 | } 114 | return (CRC->DR); 115 | } 116 | 117 | /** 118 | * @brief Returns the current CRC value. 119 | * @param None 120 | * @retval 32-bit CRC 121 | */ 122 | uint32_t CRC_GetCRC(void) 123 | { 124 | return (CRC->DR); 125 | } 126 | 127 | /** 128 | * @brief Stores a 8-bit data in the Independent Data(ID) register. 129 | * @param IDValue: 8-bit value to be stored in the ID register 130 | * @retval None 131 | */ 132 | void CRC_SetIDRegister(uint8_t IDValue) 133 | { 134 | CRC->IDR = IDValue; 135 | } 136 | 137 | /** 138 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 139 | * @param None 140 | * @retval 8-bit value of the ID register 141 | */ 142 | uint8_t CRC_GetIDRegister(void) 143 | { 144 | return (CRC->IDR); 145 | } 146 | 147 | /** 148 | * @} 149 | */ 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 160 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the DBGMCU 8 | * firmware library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_DBGMCU_H 24 | #define __STM32F10x_DBGMCU_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup DBGMCU 38 | * @{ 39 | */ 40 | 41 | /** @defgroup DBGMCU_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup DBGMCU_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | #define DBGMCU_SLEEP ((uint32_t)0x00000001) 54 | #define DBGMCU_STOP ((uint32_t)0x00000002) 55 | #define DBGMCU_STANDBY ((uint32_t)0x00000004) 56 | #define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) 57 | #define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) 58 | #define DBGMCU_TIM1_STOP ((uint32_t)0x00000400) 59 | #define DBGMCU_TIM2_STOP ((uint32_t)0x00000800) 60 | #define DBGMCU_TIM3_STOP ((uint32_t)0x00001000) 61 | #define DBGMCU_TIM4_STOP ((uint32_t)0x00002000) 62 | #define DBGMCU_CAN1_STOP ((uint32_t)0x00004000) 63 | #define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) 64 | #define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) 65 | #define DBGMCU_TIM8_STOP ((uint32_t)0x00020000) 66 | #define DBGMCU_TIM5_STOP ((uint32_t)0x00040000) 67 | #define DBGMCU_TIM6_STOP ((uint32_t)0x00080000) 68 | #define DBGMCU_TIM7_STOP ((uint32_t)0x00100000) 69 | #define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) 70 | #define DBGMCU_TIM15_STOP ((uint32_t)0x00400000) 71 | #define DBGMCU_TIM16_STOP ((uint32_t)0x00800000) 72 | #define DBGMCU_TIM17_STOP ((uint32_t)0x01000000) 73 | #define DBGMCU_TIM12_STOP ((uint32_t)0x02000000) 74 | #define DBGMCU_TIM13_STOP ((uint32_t)0x04000000) 75 | #define DBGMCU_TIM14_STOP ((uint32_t)0x08000000) 76 | #define DBGMCU_TIM9_STOP ((uint32_t)0x10000000) 77 | #define DBGMCU_TIM10_STOP ((uint32_t)0x20000000) 78 | #define DBGMCU_TIM11_STOP ((uint32_t)0x40000000) 79 | 80 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0x800000F8) == 0x00) && ((PERIPH) != 0x00)) 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup DBGMCU_Exported_Macros 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @} 91 | */ 92 | 93 | /** @defgroup DBGMCU_Exported_Functions 94 | * @{ 95 | */ 96 | 97 | uint32_t DBGMCU_GetREVID(void); 98 | uint32_t DBGMCU_GetDEVID(void); 99 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 100 | 101 | #ifdef __cplusplus 102 | } 103 | #endif 104 | 105 | #endif /* __STM32F10x_DBGMCU_H */ 106 | /** 107 | * @} 108 | */ 109 | 110 | /** 111 | * @} 112 | */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 119 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_rtc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_rtc.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the RTC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_RTC_H 24 | #define __STM32F10x_RTC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup RTC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup RTC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup RTC_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup RTC_interrupts_define 54 | * @{ 55 | */ 56 | 57 | #define RTC_IT_OW ((uint16_t)0x0004) /*!< Overflow interrupt */ 58 | #define RTC_IT_ALR ((uint16_t)0x0002) /*!< Alarm interrupt */ 59 | #define RTC_IT_SEC ((uint16_t)0x0001) /*!< Second interrupt */ 60 | #define IS_RTC_IT(IT) ((((IT) & (uint16_t)0xFFF8) == 0x00) && ((IT) != 0x00)) 61 | #define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_OW) || ((IT) == RTC_IT_ALR) || \ 62 | ((IT) == RTC_IT_SEC)) 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup RTC_interrupts_flags 68 | * @{ 69 | */ 70 | 71 | #define RTC_FLAG_RTOFF ((uint16_t)0x0020) /*!< RTC Operation OFF flag */ 72 | #define RTC_FLAG_RSF ((uint16_t)0x0008) /*!< Registers Synchronized flag */ 73 | #define RTC_FLAG_OW ((uint16_t)0x0004) /*!< Overflow flag */ 74 | #define RTC_FLAG_ALR ((uint16_t)0x0002) /*!< Alarm flag */ 75 | #define RTC_FLAG_SEC ((uint16_t)0x0001) /*!< Second flag */ 76 | #define IS_RTC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFF0) == 0x00) && ((FLAG) != 0x00)) 77 | #define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_RTOFF) || ((FLAG) == RTC_FLAG_RSF) || \ 78 | ((FLAG) == RTC_FLAG_OW) || ((FLAG) == RTC_FLAG_ALR) || \ 79 | ((FLAG) == RTC_FLAG_SEC)) 80 | #define IS_RTC_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFFFF) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | /** 87 | * @} 88 | */ 89 | 90 | /** @defgroup RTC_Exported_Macros 91 | * @{ 92 | */ 93 | 94 | /** 95 | * @} 96 | */ 97 | 98 | /** @defgroup RTC_Exported_Functions 99 | * @{ 100 | */ 101 | 102 | void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); 103 | void RTC_EnterConfigMode(void); 104 | void RTC_ExitConfigMode(void); 105 | uint32_t RTC_GetCounter(void); 106 | void RTC_SetCounter(uint32_t CounterValue); 107 | void RTC_SetPrescaler(uint32_t PrescalerValue); 108 | void RTC_SetAlarm(uint32_t AlarmValue); 109 | uint32_t RTC_GetDivider(void); 110 | void RTC_WaitForLastTask(void); 111 | void RTC_WaitForSynchro(void); 112 | FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); 113 | void RTC_ClearFlag(uint16_t RTC_FLAG); 114 | ITStatus RTC_GetITStatus(uint16_t RTC_IT); 115 | void RTC_ClearITPendingBit(uint16_t RTC_IT); 116 | 117 | #ifdef __cplusplus 118 | } 119 | #endif 120 | 121 | #endif /* __STM32F10x_RTC_H */ 122 | /** 123 | * @} 124 | */ 125 | 126 | /** 127 | * @} 128 | */ 129 | 130 | /** 131 | * @} 132 | */ 133 | 134 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 135 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_IWDG_H 24 | #define __STM32F10x_IWDG_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup IWDG 38 | * @{ 39 | */ 40 | 41 | /** @defgroup IWDG_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup IWDG_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup IWDG_WriteAccess 54 | * @{ 55 | */ 56 | 57 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 58 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 59 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 60 | ((ACCESS) == IWDG_WriteAccess_Disable)) 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup IWDG_prescaler 66 | * @{ 67 | */ 68 | 69 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 70 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 71 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 72 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 73 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 74 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 75 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 76 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 77 | ((PRESCALER) == IWDG_Prescaler_8) || \ 78 | ((PRESCALER) == IWDG_Prescaler_16) || \ 79 | ((PRESCALER) == IWDG_Prescaler_32) || \ 80 | ((PRESCALER) == IWDG_Prescaler_64) || \ 81 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 82 | ((PRESCALER) == IWDG_Prescaler_256)) 83 | /** 84 | * @} 85 | */ 86 | 87 | /** @defgroup IWDG_Flag 88 | * @{ 89 | */ 90 | 91 | #define IWDG_FLAG_PVU ((uint16_t)0x0001) 92 | #define IWDG_FLAG_RVU ((uint16_t)0x0002) 93 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU)) 94 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 95 | /** 96 | * @} 97 | */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** @defgroup IWDG_Exported_Macros 104 | * @{ 105 | */ 106 | 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup IWDG_Exported_Functions 112 | * @{ 113 | */ 114 | 115 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 116 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 117 | void IWDG_SetReload(uint16_t Reload); 118 | void IWDG_ReloadCounter(void); 119 | void IWDG_Enable(void); 120 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 121 | 122 | #ifdef __cplusplus 123 | } 124 | #endif 125 | 126 | #endif /* __STM32F10x_IWDG_H */ 127 | /** 128 | * @} 129 | */ 130 | 131 | /** 132 | * @} 133 | */ 134 | 135 | /** 136 | * @} 137 | */ 138 | 139 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 140 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # App name 2 | #------------------------------------------------------------------------------- 3 | TARGET = test 4 | 5 | # peripherial driver 6 | #------------------------------------------------------------------------------- 7 | # PERIPHDRIVERS += stm32f10x_adc 8 | # PERIPHDRIVERS += stm32f10x_bkp 9 | # PERIPHDRIVERS += stm32f10x_can 10 | # PERIPHDRIVERS += stm32f10x_cec 11 | # PERIPHDRIVERS += stm32f10x_crc 12 | # PERIPHDRIVERS += stm32f10x_dbgmcu 13 | # PERIPHDRIVERS += stm32f10x_exti 14 | # PERIPHDRIVERS += stm32f10x_flash 15 | # PERIPHDRIVERS += stm32f10x_fsmc 16 | PERIPHDRIVERS += stm32f10x_gpio 17 | # PERIPHDRIVERS += stm32f10x_i2c 18 | # PERIPHDRIVERS += stm32f10x_iwdg 19 | # PERIPHDRIVERS += stm32f10x_pwr 20 | PERIPHDRIVERS += stm32f10x_rcc 21 | # PERIPHDRIVERS += stm32f10x_rtc 22 | # PERIPHDRIVERS += stm32f10x_sdio 23 | # PERIPHDRIVERS += stm32f10x_spi 24 | # PERIPHDRIVERS += stm32f10x_tim 25 | PERIPHDRIVERS += stm32f10x_usart 26 | # PERIPHDRIVERS += stm32f10x_wwdg 27 | PERIPHDRIVERS += stm32f10x_dma 28 | # PERIPHDRIVERS += misc.c 29 | 30 | # USE DEFINES 31 | #------------------------------------------------------------------------------- 32 | DEFINES += USE_STDPERIPH_DRIVER 33 | DEFINES += STM32F10X_MD 34 | 35 | CC = gcc 36 | LD = gcc 37 | CP = objcopy 38 | SZ = size 39 | 40 | 41 | RM = rm 42 | # PATH to CMSIS and StdPeriph Lib 43 | #------------------------------------------------------------------------------- 44 | CMSIS_PATH = cmsis 45 | STDPERIPH_INC_PATH = stdperiph/inc 46 | STDPERIPH_SRC_PATH = stdperiph/src 47 | 48 | # startup file 49 | #------------------------------------------------------------------------------- 50 | 51 | # PATH SOURCE 52 | #------------------------------------------------------------------------------- 53 | SOURCEDIRS := src 54 | SOURCEDIRS += $(CMSIS_PATH) 55 | 56 | # PATH HEADERS 57 | #------------------------------------------------------------------------------- 58 | INCLUDES += . 59 | INCLUDES += $(SOURCEDIRS) 60 | INCLUDES += $(CMSIS_PATH) 61 | INCLUDES += $(STDPERIPH_INC_PATH) 62 | 63 | # EXTRA LIBRARY 64 | #------------------------------------------------------------------------------- 65 | LIBPATH += 66 | LIBS += 67 | 68 | # TOOLCHAIN OPTIONS 69 | #------------------------------------------------------------------------------- 70 | CFLAGS += -m32 71 | CFLAGS += -g 72 | CFLAGS += -Wall -pedantic # Выводить все предупреждения 73 | CFLAGS += -Os # Оптимизация 74 | CFLAGS += -ggdb # Генерировать отладочную информацию для gdb 75 | 76 | CFLAGS += $(addprefix -I, $(INCLUDES)) 77 | CFLAGS += $(addprefix -D, $(DEFINES)) 78 | 79 | LDFLAGS += $(addprefix -L, $(LIBPATH)) 80 | LDFLAGS += $(LIBS) 81 | LDFLAGS += -m32 82 | 83 | # OBJECT FILES 84 | #------------------------------------------------------------------------------- 85 | OBJS += $(patsubst %.c, %.o, $(wildcard $(addsuffix /*.c, $(SOURCEDIRS)))) 86 | OBJS += $(addprefix $(STDPERIPH_SRC_PATH)/, $(addsuffix .o, $(PERIPHDRIVERS))) 87 | OBJS += $(patsubst %.s, %.o, $(STARTUP)) 88 | 89 | # list of directories that make should search 90 | #------------------------------------------------------------------------------- 91 | VPATH := $(SOURCEDIRS) 92 | 93 | # temp file 94 | #------------------------------------------------------------------------------- 95 | TOREMOVE += *.elf *.hex 96 | TOREMOVE += $(addsuffix /*.o, $(SOURCEDIRS)) 97 | TOREMOVE += $(addsuffix /*.d, $(SOURCEDIRS)) 98 | TOREMOVE += $(STDPERIPH_SRC_PATH)/*.o 99 | TOREMOVE += $(patsubst %.s, %.o, $(STARTUP)) 100 | TOREMOVE += $(TARGET) 101 | 102 | # general build 103 | #------------------------------------------------------------------------------- 104 | all: $(TARGET).elf size 105 | 106 | # Очистка 107 | #------------------------------------------------------------------------------- 108 | clean: 109 | @$(RM) -f $(TOREMOVE) 110 | 111 | # show size 112 | #------------------------------------------------------------------------------- 113 | size: 114 | @echo "---------------------------------------------------" 115 | @$(SZ) $(TARGET).elf 116 | 117 | # linking 118 | #------------------------------------------------------------------------------- 119 | $(TARGET).elf: $(OBJS) 120 | @$(LD) $(LDFLAGS) $^ -o $@ 121 | 122 | # compile 123 | #------------------------------------------------------------------------------- 124 | %.o: %.c 125 | @$(CC) $(CFLAGS) -MD -c $< -o $@ 126 | 127 | %.o: %.s 128 | @$(AS) $(AFLAGS) -c $< -o $@ 129 | 130 | # create d-files 131 | #------------------------------------------------------------------------------- 132 | include $(wildcart *.d) 133 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_PWR_H 24 | #define __STM32F10x_PWR_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup PWR 38 | * @{ 39 | */ 40 | 41 | /** @defgroup PWR_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup PWR_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup PVD_detection_level 54 | * @{ 55 | */ 56 | 57 | #define PWR_PVDLevel_2V2 ((uint32_t)0x00000000) 58 | #define PWR_PVDLevel_2V3 ((uint32_t)0x00000020) 59 | #define PWR_PVDLevel_2V4 ((uint32_t)0x00000040) 60 | #define PWR_PVDLevel_2V5 ((uint32_t)0x00000060) 61 | #define PWR_PVDLevel_2V6 ((uint32_t)0x00000080) 62 | #define PWR_PVDLevel_2V7 ((uint32_t)0x000000A0) 63 | #define PWR_PVDLevel_2V8 ((uint32_t)0x000000C0) 64 | #define PWR_PVDLevel_2V9 ((uint32_t)0x000000E0) 65 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_2V2) || ((LEVEL) == PWR_PVDLevel_2V3)|| \ 66 | ((LEVEL) == PWR_PVDLevel_2V4) || ((LEVEL) == PWR_PVDLevel_2V5)|| \ 67 | ((LEVEL) == PWR_PVDLevel_2V6) || ((LEVEL) == PWR_PVDLevel_2V7)|| \ 68 | ((LEVEL) == PWR_PVDLevel_2V8) || ((LEVEL) == PWR_PVDLevel_2V9)) 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup Regulator_state_is_STOP_mode 74 | * @{ 75 | */ 76 | 77 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 78 | #define PWR_Regulator_LowPower ((uint32_t)0x00000001) 79 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 80 | ((REGULATOR) == PWR_Regulator_LowPower)) 81 | /** 82 | * @} 83 | */ 84 | 85 | /** @defgroup STOP_mode_entry 86 | * @{ 87 | */ 88 | 89 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 90 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 91 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE)) 92 | 93 | /** 94 | * @} 95 | */ 96 | 97 | /** @defgroup PWR_Flag 98 | * @{ 99 | */ 100 | 101 | #define PWR_FLAG_WU ((uint32_t)0x00000001) 102 | #define PWR_FLAG_SB ((uint32_t)0x00000002) 103 | #define PWR_FLAG_PVDO ((uint32_t)0x00000004) 104 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 105 | ((FLAG) == PWR_FLAG_PVDO)) 106 | 107 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 108 | /** 109 | * @} 110 | */ 111 | 112 | /** 113 | * @} 114 | */ 115 | 116 | /** @defgroup PWR_Exported_Macros 117 | * @{ 118 | */ 119 | 120 | /** 121 | * @} 122 | */ 123 | 124 | /** @defgroup PWR_Exported_Functions 125 | * @{ 126 | */ 127 | 128 | void PWR_DeInit(void); 129 | void PWR_BackupAccessCmd(FunctionalState NewState); 130 | void PWR_PVDCmd(FunctionalState NewState); 131 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); 132 | void PWR_WakeUpPinCmd(FunctionalState NewState); 133 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 134 | void PWR_EnterSTANDBYMode(void); 135 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 136 | void PWR_ClearFlag(uint32_t PWR_FLAG); 137 | 138 | #ifdef __cplusplus 139 | } 140 | #endif 141 | 142 | #endif /* __STM32F10x_PWR_H */ 143 | /** 144 | * @} 145 | */ 146 | 147 | /** 148 | * @} 149 | */ 150 | 151 | /** 152 | * @} 153 | */ 154 | 155 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 156 | -------------------------------------------------------------------------------- /src/stm32f10x_it.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F10x_StdPeriph_Template/stm32f10x_it.c 4 | * @author MCD Application Team 5 | * @version V3.5.0 6 | * @date 08-April-2011 7 | * @brief Main Interrupt Service Routines. 8 | * This file provides template for all exceptions handler and 9 | * peripherals interrupt service routine. 10 | ****************************************************************************** 11 | * @attention 12 | * 13 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 14 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 15 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 16 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 17 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 18 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 19 | * 20 | *

© COPYRIGHT 2011 STMicroelectronics

21 | ****************************************************************************** 22 | */ 23 | 24 | /* Includes ------------------------------------------------------------------*/ 25 | #include "stm32f10x_it.h" 26 | 27 | /** @addtogroup STM32F10x_StdPeriph_Template 28 | * @{ 29 | */ 30 | 31 | /* Private typedef -----------------------------------------------------------*/ 32 | /* Private define ------------------------------------------------------------*/ 33 | /* Private macro -------------------------------------------------------------*/ 34 | /* Private variables ---------------------------------------------------------*/ 35 | /* Private function prototypes -----------------------------------------------*/ 36 | /* Private functions ---------------------------------------------------------*/ 37 | 38 | /******************************************************************************/ 39 | /* Cortex-M3 Processor Exceptions Handlers */ 40 | /******************************************************************************/ 41 | 42 | /** 43 | * @brief This function handles NMI exception. 44 | * @param None 45 | * @retval None 46 | */ 47 | void NMI_Handler(void) 48 | { 49 | } 50 | 51 | /** 52 | * @brief This function handles Hard Fault exception. 53 | * @param None 54 | * @retval None 55 | */ 56 | void HardFault_Handler(void) 57 | { 58 | /* Go to infinite loop when Hard Fault exception occurs */ 59 | while (1) 60 | { 61 | } 62 | } 63 | 64 | /** 65 | * @brief This function handles Memory Manage exception. 66 | * @param None 67 | * @retval None 68 | */ 69 | void MemManage_Handler(void) 70 | { 71 | /* Go to infinite loop when Memory Manage exception occurs */ 72 | while (1) 73 | { 74 | } 75 | } 76 | 77 | /** 78 | * @brief This function handles Bus Fault exception. 79 | * @param None 80 | * @retval None 81 | */ 82 | void BusFault_Handler(void) 83 | { 84 | /* Go to infinite loop when Bus Fault exception occurs */ 85 | while (1) 86 | { 87 | } 88 | } 89 | 90 | /** 91 | * @brief This function handles Usage Fault exception. 92 | * @param None 93 | * @retval None 94 | */ 95 | void UsageFault_Handler(void) 96 | { 97 | /* Go to infinite loop when Usage Fault exception occurs */ 98 | while (1) 99 | { 100 | } 101 | } 102 | 103 | /** 104 | * @brief This function handles SVCall exception. 105 | * @param None 106 | * @retval None 107 | */ 108 | void SVC_Handler(void) 109 | { 110 | } 111 | 112 | /** 113 | * @brief This function handles Debug Monitor exception. 114 | * @param None 115 | * @retval None 116 | */ 117 | void DebugMon_Handler(void) 118 | { 119 | } 120 | 121 | /** 122 | * @brief This function handles PendSVC exception. 123 | * @param None 124 | * @retval None 125 | */ 126 | void PendSV_Handler(void) 127 | { 128 | } 129 | 130 | /** 131 | * @brief This function handles SysTick Handler. 132 | * @param None 133 | * @retval None 134 | */ 135 | void SysTick_Handler(void) 136 | { 137 | } 138 | 139 | /******************************************************************************/ 140 | /* STM32F10x Peripherals Interrupt Handlers */ 141 | /* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */ 142 | /* available peripheral interrupt handler's name please refer to the startup */ 143 | /* file (startup_stm32f10x_xx.s). */ 144 | /******************************************************************************/ 145 | 146 | /** 147 | * @brief This function handles PPP interrupt request. 148 | * @param None 149 | * @retval None 150 | */ 151 | /*void PPP_IRQHandler(void) 152 | { 153 | }*/ 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | 160 | /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ 161 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_iwdg.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the IWDG firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_iwdg.h" 23 | 24 | /** @addtogroup STM32F10x_StdPeriph_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup IWDG 29 | * @brief IWDG driver modules 30 | * @{ 31 | */ 32 | 33 | /** @defgroup IWDG_Private_TypesDefinitions 34 | * @{ 35 | */ 36 | 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup IWDG_Private_Defines 42 | * @{ 43 | */ 44 | 45 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 46 | 47 | /* KR register bit mask */ 48 | #define KR_KEY_Reload ((uint16_t)0xAAAA) 49 | #define KR_KEY_Enable ((uint16_t)0xCCCC) 50 | 51 | /** 52 | * @} 53 | */ 54 | 55 | /** @defgroup IWDG_Private_Macros 56 | * @{ 57 | */ 58 | 59 | /** 60 | * @} 61 | */ 62 | 63 | /** @defgroup IWDG_Private_Variables 64 | * @{ 65 | */ 66 | 67 | /** 68 | * @} 69 | */ 70 | 71 | /** @defgroup IWDG_Private_FunctionPrototypes 72 | * @{ 73 | */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | /** @defgroup IWDG_Private_Functions 80 | * @{ 81 | */ 82 | 83 | /** 84 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 85 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 86 | * This parameter can be one of the following values: 87 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 88 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 89 | * @retval None 90 | */ 91 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 92 | { 93 | /* Check the parameters */ 94 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 95 | IWDG->KR = IWDG_WriteAccess; 96 | } 97 | 98 | /** 99 | * @brief Sets IWDG Prescaler value. 100 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 101 | * This parameter can be one of the following values: 102 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 103 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 104 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 105 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 106 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 107 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 108 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 109 | * @retval None 110 | */ 111 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 112 | { 113 | /* Check the parameters */ 114 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 115 | IWDG->PR = IWDG_Prescaler; 116 | } 117 | 118 | /** 119 | * @brief Sets IWDG Reload value. 120 | * @param Reload: specifies the IWDG Reload value. 121 | * This parameter must be a number between 0 and 0x0FFF. 122 | * @retval None 123 | */ 124 | void IWDG_SetReload(uint16_t Reload) 125 | { 126 | /* Check the parameters */ 127 | assert_param(IS_IWDG_RELOAD(Reload)); 128 | IWDG->RLR = Reload; 129 | } 130 | 131 | /** 132 | * @brief Reloads IWDG counter with value defined in the reload register 133 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 134 | * @param None 135 | * @retval None 136 | */ 137 | void IWDG_ReloadCounter(void) 138 | { 139 | IWDG->KR = KR_KEY_Reload; 140 | } 141 | 142 | /** 143 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 144 | * @param None 145 | * @retval None 146 | */ 147 | void IWDG_Enable(void) 148 | { 149 | IWDG->KR = KR_KEY_Enable; 150 | } 151 | 152 | /** 153 | * @brief Checks whether the specified IWDG flag is set or not. 154 | * @param IWDG_FLAG: specifies the flag to check. 155 | * This parameter can be one of the following values: 156 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 157 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 158 | * @retval The new state of IWDG_FLAG (SET or RESET). 159 | */ 160 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 161 | { 162 | FlagStatus bitstatus = RESET; 163 | /* Check the parameters */ 164 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 165 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 166 | { 167 | bitstatus = SET; 168 | } 169 | else 170 | { 171 | bitstatus = RESET; 172 | } 173 | /* Return the flag status */ 174 | return bitstatus; 175 | } 176 | 177 | /** 178 | * @} 179 | */ 180 | 181 | /** 182 | * @} 183 | */ 184 | 185 | /** 186 | * @} 187 | */ 188 | 189 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 190 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the DBGMCU firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_dbgmcu.h" 23 | 24 | /** @addtogroup STM32F10x_StdPeriph_Driver 25 | * @{ 26 | */ 27 | 28 | /** @defgroup DBGMCU 29 | * @brief DBGMCU driver modules 30 | * @{ 31 | */ 32 | 33 | /** @defgroup DBGMCU_Private_TypesDefinitions 34 | * @{ 35 | */ 36 | 37 | /** 38 | * @} 39 | */ 40 | 41 | /** @defgroup DBGMCU_Private_Defines 42 | * @{ 43 | */ 44 | 45 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 46 | /** 47 | * @} 48 | */ 49 | 50 | /** @defgroup DBGMCU_Private_Macros 51 | * @{ 52 | */ 53 | 54 | /** 55 | * @} 56 | */ 57 | 58 | /** @defgroup DBGMCU_Private_Variables 59 | * @{ 60 | */ 61 | 62 | /** 63 | * @} 64 | */ 65 | 66 | /** @defgroup DBGMCU_Private_FunctionPrototypes 67 | * @{ 68 | */ 69 | 70 | /** 71 | * @} 72 | */ 73 | 74 | /** @defgroup DBGMCU_Private_Functions 75 | * @{ 76 | */ 77 | 78 | /** 79 | * @brief Returns the device revision identifier. 80 | * @param None 81 | * @retval Device revision identifier 82 | */ 83 | uint32_t DBGMCU_GetREVID(void) 84 | { 85 | return(DBGMCU->IDCODE >> 16); 86 | } 87 | 88 | /** 89 | * @brief Returns the device identifier. 90 | * @param None 91 | * @retval Device identifier 92 | */ 93 | uint32_t DBGMCU_GetDEVID(void) 94 | { 95 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 96 | } 97 | 98 | /** 99 | * @brief Configures the specified peripheral and low power mode behavior 100 | * when the MCU under Debug mode. 101 | * @param DBGMCU_Periph: specifies the peripheral and low power mode. 102 | * This parameter can be any combination of the following values: 103 | * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode 104 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 105 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 106 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 107 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 108 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 109 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted 110 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 111 | * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted 112 | * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted 113 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted 114 | * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted 115 | * @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted 116 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 117 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted 118 | * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted 119 | * @arg DBGMCU_CAN2_STOP: Debug CAN2 stopped when Core is halted 120 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 121 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 122 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 123 | * @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted 124 | * @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted 125 | * @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted 126 | * @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted 127 | * @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted 128 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 129 | * @param NewState: new state of the specified peripheral in Debug mode. 130 | * This parameter can be: ENABLE or DISABLE. 131 | * @retval None 132 | */ 133 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 134 | { 135 | /* Check the parameters */ 136 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 137 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 138 | 139 | if (NewState != DISABLE) 140 | { 141 | DBGMCU->CR |= DBGMCU_Periph; 142 | } 143 | else 144 | { 145 | DBGMCU->CR &= ~DBGMCU_Periph; 146 | } 147 | } 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** 154 | * @} 155 | */ 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 162 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_wwdg.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the WWDG firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_wwdg.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup WWDG 30 | * @brief WWDG driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup WWDG_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup WWDG_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* ----------- WWDG registers bit address in the alias region ----------- */ 47 | #define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE) 48 | 49 | /* Alias word address of EWI bit */ 50 | #define CFR_OFFSET (WWDG_OFFSET + 0x04) 51 | #define EWI_BitNumber 0x09 52 | #define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4)) 53 | 54 | /* --------------------- WWDG registers bit mask ------------------------ */ 55 | 56 | /* CR register bit mask */ 57 | #define CR_WDGA_Set ((uint32_t)0x00000080) 58 | 59 | /* CFR register bit mask */ 60 | #define CFR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) 61 | #define CFR_W_Mask ((uint32_t)0xFFFFFF80) 62 | #define BIT_Mask ((uint8_t)0x7F) 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup WWDG_Private_Macros 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup WWDG_Private_Variables 77 | * @{ 78 | */ 79 | 80 | /** 81 | * @} 82 | */ 83 | 84 | /** @defgroup WWDG_Private_FunctionPrototypes 85 | * @{ 86 | */ 87 | 88 | /** 89 | * @} 90 | */ 91 | 92 | /** @defgroup WWDG_Private_Functions 93 | * @{ 94 | */ 95 | 96 | /** 97 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 98 | * @param None 99 | * @retval None 100 | */ 101 | void WWDG_DeInit(void) 102 | { 103 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 104 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 105 | } 106 | 107 | /** 108 | * @brief Sets the WWDG Prescaler. 109 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 110 | * This parameter can be one of the following values: 111 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 112 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 113 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 114 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 115 | * @retval None 116 | */ 117 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 118 | { 119 | uint32_t tmpreg = 0; 120 | /* Check the parameters */ 121 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 122 | /* Clear WDGTB[1:0] bits */ 123 | tmpreg = WWDG->CFR & CFR_WDGTB_Mask; 124 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 125 | tmpreg |= WWDG_Prescaler; 126 | /* Store the new value */ 127 | WWDG->CFR = tmpreg; 128 | } 129 | 130 | /** 131 | * @brief Sets the WWDG window value. 132 | * @param WindowValue: specifies the window value to be compared to the downcounter. 133 | * This parameter value must be lower than 0x80. 134 | * @retval None 135 | */ 136 | void WWDG_SetWindowValue(uint8_t WindowValue) 137 | { 138 | __IO uint32_t tmpreg = 0; 139 | 140 | /* Check the parameters */ 141 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 142 | /* Clear W[6:0] bits */ 143 | 144 | tmpreg = WWDG->CFR & CFR_W_Mask; 145 | 146 | /* Set W[6:0] bits according to WindowValue value */ 147 | tmpreg |= WindowValue & (uint32_t) BIT_Mask; 148 | 149 | /* Store the new value */ 150 | WWDG->CFR = tmpreg; 151 | } 152 | 153 | /** 154 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 155 | * @param None 156 | * @retval None 157 | */ 158 | void WWDG_EnableIT(void) 159 | { 160 | *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE; 161 | } 162 | 163 | /** 164 | * @brief Sets the WWDG counter value. 165 | * @param Counter: specifies the watchdog counter value. 166 | * This parameter must be a number between 0x40 and 0x7F. 167 | * @retval None 168 | */ 169 | void WWDG_SetCounter(uint8_t Counter) 170 | { 171 | /* Check the parameters */ 172 | assert_param(IS_WWDG_COUNTER(Counter)); 173 | /* Write to T[6:0] bits to configure the counter value, no need to do 174 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 175 | WWDG->CR = Counter & BIT_Mask; 176 | } 177 | 178 | /** 179 | * @brief Enables WWDG and load the counter value. 180 | * @param Counter: specifies the watchdog counter value. 181 | * This parameter must be a number between 0x40 and 0x7F. 182 | * @retval None 183 | */ 184 | void WWDG_Enable(uint8_t Counter) 185 | { 186 | /* Check the parameters */ 187 | assert_param(IS_WWDG_COUNTER(Counter)); 188 | WWDG->CR = CR_WDGA_Set | Counter; 189 | } 190 | 191 | /** 192 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 193 | * @param None 194 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET) 195 | */ 196 | FlagStatus WWDG_GetFlagStatus(void) 197 | { 198 | return (FlagStatus)(WWDG->SR); 199 | } 200 | 201 | /** 202 | * @brief Clears Early Wakeup interrupt flag. 203 | * @param None 204 | * @retval None 205 | */ 206 | void WWDG_ClearFlag(void) 207 | { 208 | WWDG->SR = (uint32_t)RESET; 209 | } 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /** 220 | * @} 221 | */ 222 | 223 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 224 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_CEC_H 24 | #define __STM32F10x_CEC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup CEC 38 | * @{ 39 | */ 40 | 41 | 42 | /** @defgroup CEC_Exported_Types 43 | * @{ 44 | */ 45 | 46 | /** 47 | * @brief CEC Init structure definition 48 | */ 49 | typedef struct 50 | { 51 | uint16_t CEC_BitTimingMode; /*!< Configures the CEC Bit Timing Error Mode. 52 | This parameter can be a value of @ref CEC_BitTiming_Mode */ 53 | uint16_t CEC_BitPeriodMode; /*!< Configures the CEC Bit Period Error Mode. 54 | This parameter can be a value of @ref CEC_BitPeriod_Mode */ 55 | }CEC_InitTypeDef; 56 | 57 | /** 58 | * @} 59 | */ 60 | 61 | /** @defgroup CEC_Exported_Constants 62 | * @{ 63 | */ 64 | 65 | /** @defgroup CEC_BitTiming_Mode 66 | * @{ 67 | */ 68 | #define CEC_BitTimingStdMode ((uint16_t)0x00) /*!< Bit timing error Standard Mode */ 69 | #define CEC_BitTimingErrFreeMode CEC_CFGR_BTEM /*!< Bit timing error Free Mode */ 70 | 71 | #define IS_CEC_BIT_TIMING_ERROR_MODE(MODE) (((MODE) == CEC_BitTimingStdMode) || \ 72 | ((MODE) == CEC_BitTimingErrFreeMode)) 73 | /** 74 | * @} 75 | */ 76 | 77 | /** @defgroup CEC_BitPeriod_Mode 78 | * @{ 79 | */ 80 | #define CEC_BitPeriodStdMode ((uint16_t)0x00) /*!< Bit period error Standard Mode */ 81 | #define CEC_BitPeriodFlexibleMode CEC_CFGR_BPEM /*!< Bit period error Flexible Mode */ 82 | 83 | #define IS_CEC_BIT_PERIOD_ERROR_MODE(MODE) (((MODE) == CEC_BitPeriodStdMode) || \ 84 | ((MODE) == CEC_BitPeriodFlexibleMode)) 85 | /** 86 | * @} 87 | */ 88 | 89 | 90 | /** @defgroup CEC_interrupts_definition 91 | * @{ 92 | */ 93 | #define CEC_IT_TERR CEC_CSR_TERR 94 | #define CEC_IT_TBTRF CEC_CSR_TBTRF 95 | #define CEC_IT_RERR CEC_CSR_RERR 96 | #define CEC_IT_RBTF CEC_CSR_RBTF 97 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TERR) || ((IT) == CEC_IT_TBTRF) || \ 98 | ((IT) == CEC_IT_RERR) || ((IT) == CEC_IT_RBTF)) 99 | /** 100 | * @} 101 | */ 102 | 103 | 104 | /** @defgroup CEC_Own_Addres 105 | * @{ 106 | */ 107 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 108 | /** 109 | * @} 110 | */ 111 | 112 | /** @defgroup CEC_Prescaler 113 | * @{ 114 | */ 115 | #define IS_CEC_PRESCALER(PRESCALER) ((PRESCALER) <= 0x3FFF) 116 | 117 | /** 118 | * @} 119 | */ 120 | 121 | /** @defgroup CEC_flags_definition 122 | * @{ 123 | */ 124 | 125 | /** 126 | * @brief ESR register flags 127 | */ 128 | #define CEC_FLAG_BTE ((uint32_t)0x10010000) 129 | #define CEC_FLAG_BPE ((uint32_t)0x10020000) 130 | #define CEC_FLAG_RBTFE ((uint32_t)0x10040000) 131 | #define CEC_FLAG_SBE ((uint32_t)0x10080000) 132 | #define CEC_FLAG_ACKE ((uint32_t)0x10100000) 133 | #define CEC_FLAG_LINE ((uint32_t)0x10200000) 134 | #define CEC_FLAG_TBTFE ((uint32_t)0x10400000) 135 | 136 | /** 137 | * @brief CSR register flags 138 | */ 139 | #define CEC_FLAG_TEOM ((uint32_t)0x00000002) 140 | #define CEC_FLAG_TERR ((uint32_t)0x00000004) 141 | #define CEC_FLAG_TBTRF ((uint32_t)0x00000008) 142 | #define CEC_FLAG_RSOM ((uint32_t)0x00000010) 143 | #define CEC_FLAG_REOM ((uint32_t)0x00000020) 144 | #define CEC_FLAG_RERR ((uint32_t)0x00000040) 145 | #define CEC_FLAG_RBTF ((uint32_t)0x00000080) 146 | 147 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF03) == 0x00) && ((FLAG) != 0x00)) 148 | 149 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_BTE) || ((FLAG) == CEC_FLAG_BPE) || \ 150 | ((FLAG) == CEC_FLAG_RBTFE) || ((FLAG)== CEC_FLAG_SBE) || \ 151 | ((FLAG) == CEC_FLAG_ACKE) || ((FLAG) == CEC_FLAG_LINE) || \ 152 | ((FLAG) == CEC_FLAG_TBTFE) || ((FLAG) == CEC_FLAG_TEOM) || \ 153 | ((FLAG) == CEC_FLAG_TERR) || ((FLAG) == CEC_FLAG_TBTRF) || \ 154 | ((FLAG) == CEC_FLAG_RSOM) || ((FLAG) == CEC_FLAG_REOM) || \ 155 | ((FLAG) == CEC_FLAG_RERR) || ((FLAG) == CEC_FLAG_RBTF)) 156 | 157 | /** 158 | * @} 159 | */ 160 | 161 | /** 162 | * @} 163 | */ 164 | 165 | /** @defgroup CEC_Exported_Macros 166 | * @{ 167 | */ 168 | 169 | /** 170 | * @} 171 | */ 172 | 173 | /** @defgroup CEC_Exported_Functions 174 | * @{ 175 | */ 176 | void CEC_DeInit(void); 177 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 178 | void CEC_Cmd(FunctionalState NewState); 179 | void CEC_ITConfig(FunctionalState NewState); 180 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 181 | void CEC_SetPrescaler(uint16_t CEC_Prescaler); 182 | void CEC_SendDataByte(uint8_t Data); 183 | uint8_t CEC_ReceiveDataByte(void); 184 | void CEC_StartOfMessage(void); 185 | void CEC_EndOfMessageCmd(FunctionalState NewState); 186 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG); 187 | void CEC_ClearFlag(uint32_t CEC_FLAG); 188 | ITStatus CEC_GetITStatus(uint8_t CEC_IT); 189 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 190 | 191 | #ifdef __cplusplus 192 | } 193 | #endif 194 | 195 | #endif /* __STM32F10x_CEC_H */ 196 | 197 | /** 198 | * @} 199 | */ 200 | 201 | /** 202 | * @} 203 | */ 204 | 205 | /** 206 | * @} 207 | */ 208 | 209 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 210 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_exti.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the EXTI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_EXTI_H 24 | #define __STM32F10x_EXTI_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup EXTI 38 | * @{ 39 | */ 40 | 41 | /** @defgroup EXTI_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief EXTI mode enumeration 47 | */ 48 | 49 | typedef enum 50 | { 51 | EXTI_Mode_Interrupt = 0x00, 52 | EXTI_Mode_Event = 0x04 53 | }EXTIMode_TypeDef; 54 | 55 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 56 | 57 | /** 58 | * @brief EXTI Trigger enumeration 59 | */ 60 | 61 | typedef enum 62 | { 63 | EXTI_Trigger_Rising = 0x08, 64 | EXTI_Trigger_Falling = 0x0C, 65 | EXTI_Trigger_Rising_Falling = 0x10 66 | }EXTITrigger_TypeDef; 67 | 68 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 69 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 70 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 71 | /** 72 | * @brief EXTI Init Structure definition 73 | */ 74 | 75 | typedef struct 76 | { 77 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 78 | This parameter can be any combination of @ref EXTI_Lines */ 79 | 80 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 81 | This parameter can be a value of @ref EXTIMode_TypeDef */ 82 | 83 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 84 | This parameter can be a value of @ref EXTIMode_TypeDef */ 85 | 86 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 87 | This parameter can be set either to ENABLE or DISABLE */ 88 | }EXTI_InitTypeDef; 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup EXTI_Exported_Constants 95 | * @{ 96 | */ 97 | 98 | /** @defgroup EXTI_Lines 99 | * @{ 100 | */ 101 | 102 | #define EXTI_Line0 ((uint32_t)0x00001) /*!< External interrupt line 0 */ 103 | #define EXTI_Line1 ((uint32_t)0x00002) /*!< External interrupt line 1 */ 104 | #define EXTI_Line2 ((uint32_t)0x00004) /*!< External interrupt line 2 */ 105 | #define EXTI_Line3 ((uint32_t)0x00008) /*!< External interrupt line 3 */ 106 | #define EXTI_Line4 ((uint32_t)0x00010) /*!< External interrupt line 4 */ 107 | #define EXTI_Line5 ((uint32_t)0x00020) /*!< External interrupt line 5 */ 108 | #define EXTI_Line6 ((uint32_t)0x00040) /*!< External interrupt line 6 */ 109 | #define EXTI_Line7 ((uint32_t)0x00080) /*!< External interrupt line 7 */ 110 | #define EXTI_Line8 ((uint32_t)0x00100) /*!< External interrupt line 8 */ 111 | #define EXTI_Line9 ((uint32_t)0x00200) /*!< External interrupt line 9 */ 112 | #define EXTI_Line10 ((uint32_t)0x00400) /*!< External interrupt line 10 */ 113 | #define EXTI_Line11 ((uint32_t)0x00800) /*!< External interrupt line 11 */ 114 | #define EXTI_Line12 ((uint32_t)0x01000) /*!< External interrupt line 12 */ 115 | #define EXTI_Line13 ((uint32_t)0x02000) /*!< External interrupt line 13 */ 116 | #define EXTI_Line14 ((uint32_t)0x04000) /*!< External interrupt line 14 */ 117 | #define EXTI_Line15 ((uint32_t)0x08000) /*!< External interrupt line 15 */ 118 | #define EXTI_Line16 ((uint32_t)0x10000) /*!< External interrupt line 16 Connected to the PVD Output */ 119 | #define EXTI_Line17 ((uint32_t)0x20000) /*!< External interrupt line 17 Connected to the RTC Alarm event */ 120 | #define EXTI_Line18 ((uint32_t)0x40000) /*!< External interrupt line 18 Connected to the USB Device/USB OTG FS 121 | Wakeup from suspend event */ 122 | #define EXTI_Line19 ((uint32_t)0x80000) /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */ 123 | 124 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFFF00000) == 0x00) && ((LINE) != (uint16_t)0x00)) 125 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 126 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 127 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 128 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 129 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 130 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 131 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 132 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 133 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 134 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19)) 135 | 136 | 137 | /** 138 | * @} 139 | */ 140 | 141 | /** 142 | * @} 143 | */ 144 | 145 | /** @defgroup EXTI_Exported_Macros 146 | * @{ 147 | */ 148 | 149 | /** 150 | * @} 151 | */ 152 | 153 | /** @defgroup EXTI_Exported_Functions 154 | * @{ 155 | */ 156 | 157 | void EXTI_DeInit(void); 158 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 159 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 160 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 161 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 162 | void EXTI_ClearFlag(uint32_t EXTI_Line); 163 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 164 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 165 | 166 | #ifdef __cplusplus 167 | } 168 | #endif 169 | 170 | #endif /* __STM32F10x_EXTI_H */ 171 | /** 172 | * @} 173 | */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 184 | -------------------------------------------------------------------------------- /stdperiph/src/misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Includes ------------------------------------------------------------------*/ 23 | #include "misc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup MISC 30 | * @brief MISC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup MISC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup MISC_Private_Defines 43 | * @{ 44 | */ 45 | 46 | #define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) 47 | /** 48 | * @} 49 | */ 50 | 51 | /** @defgroup MISC_Private_Macros 52 | * @{ 53 | */ 54 | 55 | /** 56 | * @} 57 | */ 58 | 59 | /** @defgroup MISC_Private_Variables 60 | * @{ 61 | */ 62 | 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup MISC_Private_FunctionPrototypes 68 | * @{ 69 | */ 70 | 71 | /** 72 | * @} 73 | */ 74 | 75 | /** @defgroup MISC_Private_Functions 76 | * @{ 77 | */ 78 | 79 | /** 80 | * @brief Configures the priority grouping: pre-emption priority and subpriority. 81 | * @param NVIC_PriorityGroup: specifies the priority grouping bits length. 82 | * This parameter can be one of the following values: 83 | * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority 84 | * 4 bits for subpriority 85 | * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority 86 | * 3 bits for subpriority 87 | * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority 88 | * 2 bits for subpriority 89 | * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority 90 | * 1 bits for subpriority 91 | * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority 92 | * 0 bits for subpriority 93 | * @retval None 94 | */ 95 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) 96 | { 97 | /* Check the parameters */ 98 | assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup)); 99 | 100 | /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */ 101 | SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup; 102 | } 103 | 104 | /** 105 | * @brief Initializes the NVIC peripheral according to the specified 106 | * parameters in the NVIC_InitStruct. 107 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 108 | * the configuration information for the specified NVIC peripheral. 109 | * @retval None 110 | */ 111 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 112 | { 113 | uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F; 114 | 115 | /* Check the parameters */ 116 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 117 | assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority)); 118 | assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority)); 119 | 120 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 121 | { 122 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 123 | tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08; 124 | tmppre = (0x4 - tmppriority); 125 | tmpsub = tmpsub >> tmppriority; 126 | 127 | tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre; 128 | tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub; 129 | tmppriority = tmppriority << 0x04; 130 | 131 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority; 132 | 133 | /* Enable the Selected IRQ Channels --------------------------------------*/ 134 | NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 135 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 136 | } 137 | else 138 | { 139 | /* Disable the Selected IRQ Channels -------------------------------------*/ 140 | NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] = 141 | (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 142 | } 143 | } 144 | 145 | /** 146 | * @brief Sets the vector table location and Offset. 147 | * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory. 148 | * This parameter can be one of the following values: 149 | * @arg NVIC_VectTab_RAM 150 | * @arg NVIC_VectTab_FLASH 151 | * @param Offset: Vector Table base offset field. This value must be a multiple of 0x100. 152 | * @retval None 153 | */ 154 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset) 155 | { 156 | /* Check the parameters */ 157 | assert_param(IS_NVIC_VECTTAB(NVIC_VectTab)); 158 | assert_param(IS_NVIC_OFFSET(Offset)); 159 | 160 | SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80); 161 | } 162 | 163 | /** 164 | * @brief Selects the condition for the system to enter low power mode. 165 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 166 | * This parameter can be one of the following values: 167 | * @arg NVIC_LP_SEVONPEND 168 | * @arg NVIC_LP_SLEEPDEEP 169 | * @arg NVIC_LP_SLEEPONEXIT 170 | * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE. 171 | * @retval None 172 | */ 173 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 174 | { 175 | /* Check the parameters */ 176 | assert_param(IS_NVIC_LP(LowPowerMode)); 177 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 178 | 179 | if (NewState != DISABLE) 180 | { 181 | SCB->SCR |= LowPowerMode; 182 | } 183 | else 184 | { 185 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 186 | } 187 | } 188 | 189 | /** 190 | * @brief Configures the SysTick clock source. 191 | * @param SysTick_CLKSource: specifies the SysTick clock source. 192 | * This parameter can be one of the following values: 193 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 194 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 195 | * @retval None 196 | */ 197 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 198 | { 199 | /* Check the parameters */ 200 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 201 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 202 | { 203 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 204 | } 205 | else 206 | { 207 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 208 | } 209 | } 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /** 220 | * @} 221 | */ 222 | 223 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 224 | -------------------------------------------------------------------------------- /src/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | #include 4 | #include 5 | #include 6 | #include 7 | 8 | #define USARTy USART1 9 | #define USARTy_GPIO GPIOA 10 | #define USARTy_CLK RCC_APB2Periph_USART1 11 | #define USARTy_GPIO_CLK RCC_APB2Periph_GPIOA 12 | #define USARTy_RxPin GPIO_Pin_10 13 | #define USARTy_TxPin GPIO_Pin_9 14 | #define USARTy_Tx_DMA_Channel DMA1_Channel4 15 | #define USARTy_Tx_DMA_FLAG DMA1_FLAG_TC4 16 | #define USARTy_Rx_DMA_Channel DMA1_Channel5 17 | #define USARTy_Rx_DMA_FLAG DMA1_FLAG_TC5 18 | #define USARTy_DR_Base 0x40013804 19 | 20 | #define USARTz USART2 21 | #define USARTz_GPIO GPIOA 22 | #define USARTz_CLK RCC_APB1Periph_USART2 23 | #define USARTz_GPIO_CLK RCC_APB2Periph_GPIOA 24 | #define USARTz_RxPin GPIO_Pin_3 25 | #define USARTz_TxPin GPIO_Pin_2 26 | #define USARTz_Tx_DMA_Channel DMA1_Channel7 27 | #define USARTz_Tx_DMA_FLAG DMA1_FLAG_TC7 28 | #define USARTz_Rx_DMA_Channel DMA1_Channel6 29 | #define USARTz_Rx_DMA_FLAG DMA1_FLAG_TC6 30 | #define USARTz_DR_Base 0x40004404 31 | 32 | const uint8_t * addrDMAbuf = (uint8_t *)0x20000000; 33 | const size_t sizeDMAbuf = 0x100; 34 | 35 | const char * message = "AddressIntercept PinTool UART DMA example"; 36 | 37 | void init(void); 38 | void initPintoolClient(); 39 | 40 | int main() 41 | { 42 | 43 | initPintoolClient(); 44 | 45 | init(); 46 | 47 | RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE); 48 | 49 | GPIO_InitTypeDef gpio; 50 | 51 | gpio.GPIO_Pin = GPIO_Pin_13; 52 | gpio.GPIO_Speed = GPIO_Speed_50MHz; 53 | gpio.GPIO_Mode = GPIO_Mode_Out_PP; 54 | GPIO_Init(GPIOC, &gpio); 55 | 56 | const size_t _SIZE_MESSAGE = strlen(message); 57 | 58 | printf("sending message "); 59 | 60 | for (int i = 0; i < _SIZE_MESSAGE; i++) { 61 | /* Send one byte from USARTy to USARTz */ 62 | USART_SendData(USARTy, message[i]); 63 | 64 | GPIO_SetBits(GPIOC, GPIO_Pin_13); 65 | 66 | /* Loop until USARTy DR register is empty */ 67 | while (USART_GetFlagStatus(USARTy, USART_FLAG_TXE) == RESET) 68 | ; 69 | 70 | printf("."); 71 | fflush(stdout); 72 | 73 | GPIO_ResetBits(GPIOC, GPIO_Pin_13); 74 | } 75 | printf("\n"); 76 | 77 | printf("qty of sent bytes %d\n", strlen(message)); 78 | 79 | const uint16_t rec = DMA_GetCurrDataCounter(USARTz_Rx_DMA_Channel); 80 | 81 | printf("qty of received byte using DMA : %d\n", sizeDMAbuf - rec); 82 | printf("read message from buffer DMA : "); 83 | const uint8_t *pM = (uint8_t *)pAddrSRAM; 84 | for (int r = 0; r < _SIZE_MESSAGE; r++) { 85 | printf("%c", pM[r]); 86 | fflush(stdout); 87 | } 88 | printf("\n"); 89 | 90 | assert(strncmp(message, (const char *)pM, _SIZE_MESSAGE) == 0); 91 | 92 | printf("Received and sent bytes are equal!\n"); 93 | 94 | return 0; 95 | } 96 | 97 | /** 98 | * @brief Configures the different system clocks. 99 | * @param None 100 | * @retval None 101 | */ 102 | void RCC_Configuration(void) 103 | { 104 | 105 | /* DMA clock enable */ 106 | RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); 107 | 108 | /* Enable GPIO clock */ 109 | RCC_APB2PeriphClockCmd(USARTy_GPIO_CLK | USARTz_GPIO_CLK | RCC_APB2Periph_AFIO, ENABLE); 110 | 111 | /* Enable USARTy Clock */ 112 | RCC_APB2PeriphClockCmd(USARTy_CLK, ENABLE); 113 | 114 | /* Enable USARTz Clock */ 115 | RCC_APB1PeriphClockCmd(USARTz_CLK, ENABLE); 116 | } 117 | 118 | /** 119 | * @brief Configures the different GPIO ports. 120 | * @param None 121 | * @retval None 122 | */ 123 | void GPIO_Configuration(void) 124 | { 125 | GPIO_InitTypeDef GPIO_InitStructure; 126 | 127 | /* Configure USARTy Rx as input floating */ 128 | GPIO_InitStructure.GPIO_Pin = USARTy_RxPin; 129 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; 130 | GPIO_Init(USARTy_GPIO, &GPIO_InitStructure); 131 | 132 | /* Configure USARTz Rx as input floating */ 133 | GPIO_InitStructure.GPIO_Pin = USARTz_RxPin; 134 | GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); 135 | 136 | /* Configure USARTy Tx as alternate function push-pull */ 137 | GPIO_InitStructure.GPIO_Pin = USARTy_TxPin; 138 | GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; 139 | GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; 140 | GPIO_Init(USARTy_GPIO, &GPIO_InitStructure); 141 | 142 | /* Configure USARTz Tx as alternate function push-pull */ 143 | GPIO_InitStructure.GPIO_Pin = USARTz_TxPin; 144 | GPIO_Init(USARTz_GPIO, &GPIO_InitStructure); 145 | } 146 | 147 | /** 148 | * @brief Configures the DMA. 149 | * @param None 150 | * @retval None 151 | */ 152 | void DMA_Configuration(void) 153 | { 154 | DMA_InitTypeDef DMA_InitStructure; 155 | 156 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; 157 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; 158 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; 159 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; 160 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; 161 | DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; 162 | DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; 163 | /* USARTz RX DMA1 Channel (triggered by USARTz Rx event) Config */ 164 | DMA_DeInit(USARTz_Rx_DMA_Channel); 165 | DMA_InitStructure.DMA_PeripheralBaseAddr = USARTz_DR_Base; 166 | DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)addrDMAbuf; 167 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; 168 | DMA_InitStructure.DMA_BufferSize = sizeDMAbuf; 169 | DMA_Init(USARTz_Rx_DMA_Channel, &DMA_InitStructure); 170 | } 171 | 172 | /** 173 | * @brief Compares two buffers. 174 | * @param pBuffer1, pBuffer2: buffers to be compared. 175 | * @param BufferLength: buffer's length 176 | * @retval PASSED: pBuffer1 identical to pBuffer2 177 | * FAILED: pBuffer1 differs from pBuffer2 178 | */ 179 | 180 | void init(void) 181 | { 182 | /*!< At this stage the microcontroller clock setting is already configured, 183 | this is done through SystemInit() function which is called from startup 184 | file (startup_stm32f10x_xx.s) before to branch to application main. 185 | To reconfigure the default setting of SystemInit() function, refer to 186 | system_stm32f10x.c file 187 | */ 188 | USART_InitTypeDef USART_InitStructure; 189 | /* System Clocks Configuration */ 190 | RCC_Configuration(); 191 | 192 | /* Configure the GPIO ports */ 193 | GPIO_Configuration(); 194 | 195 | /* Configure the DMA */ 196 | DMA_Configuration(); 197 | 198 | /* USARTy and USARTz configuration ------------------------------------------------------*/ 199 | /* USARTy and USARTz configured as follow: 200 | - BaudRate = 230400 baud 201 | - Word Length = 8 Bits 202 | - One Stop Bit 203 | - Even parity 204 | - Hardware flow control disabled (RTS and CTS signals) 205 | - Receive and transmit enabled 206 | */ 207 | USART_InitStructure.USART_BaudRate = 230400; 208 | USART_InitStructure.USART_WordLength = USART_WordLength_8b; 209 | USART_InitStructure.USART_StopBits = USART_StopBits_1; 210 | USART_InitStructure.USART_Parity = USART_Parity_No; //USART_Parity_Even; 211 | USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; 212 | USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; 213 | 214 | /* Configure USARTy */ 215 | USART_Init(USARTy, &USART_InitStructure); 216 | /* Configure USARTz */ 217 | USART_Init(USARTz, &USART_InitStructure); 218 | 219 | /* Enable USARTz DMA Rx and TX request */ 220 | USART_DMACmd(USARTz, USART_DMAReq_Rx, ENABLE); 221 | 222 | /* Enable USARTz RX DMA1 Channel */ 223 | DMA_Cmd(USARTz_Rx_DMA_Channel, ENABLE); 224 | 225 | /* Enable the USARTy */ 226 | USART_Cmd(USARTy, ENABLE); 227 | 228 | /* Enable the USARTz */ 229 | USART_Cmd(USARTz, ENABLE); 230 | 231 | } 232 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_bkp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the BKP firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_BKP_H 24 | #define __STM32F10x_BKP_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup BKP 38 | * @{ 39 | */ 40 | 41 | /** @defgroup BKP_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @} 47 | */ 48 | 49 | /** @defgroup BKP_Exported_Constants 50 | * @{ 51 | */ 52 | 53 | /** @defgroup Tamper_Pin_active_level 54 | * @{ 55 | */ 56 | 57 | #define BKP_TamperPinLevel_High ((uint16_t)0x0000) 58 | #define BKP_TamperPinLevel_Low ((uint16_t)0x0001) 59 | #define IS_BKP_TAMPER_PIN_LEVEL(LEVEL) (((LEVEL) == BKP_TamperPinLevel_High) || \ 60 | ((LEVEL) == BKP_TamperPinLevel_Low)) 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @defgroup RTC_output_source_to_output_on_the_Tamper_pin 66 | * @{ 67 | */ 68 | 69 | #define BKP_RTCOutputSource_None ((uint16_t)0x0000) 70 | #define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) 71 | #define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) 72 | #define BKP_RTCOutputSource_Second ((uint16_t)0x0300) 73 | #define IS_BKP_RTC_OUTPUT_SOURCE(SOURCE) (((SOURCE) == BKP_RTCOutputSource_None) || \ 74 | ((SOURCE) == BKP_RTCOutputSource_CalibClock) || \ 75 | ((SOURCE) == BKP_RTCOutputSource_Alarm) || \ 76 | ((SOURCE) == BKP_RTCOutputSource_Second)) 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @defgroup Data_Backup_Register 82 | * @{ 83 | */ 84 | 85 | #define BKP_DR1 ((uint16_t)0x0004) 86 | #define BKP_DR2 ((uint16_t)0x0008) 87 | #define BKP_DR3 ((uint16_t)0x000C) 88 | #define BKP_DR4 ((uint16_t)0x0010) 89 | #define BKP_DR5 ((uint16_t)0x0014) 90 | #define BKP_DR6 ((uint16_t)0x0018) 91 | #define BKP_DR7 ((uint16_t)0x001C) 92 | #define BKP_DR8 ((uint16_t)0x0020) 93 | #define BKP_DR9 ((uint16_t)0x0024) 94 | #define BKP_DR10 ((uint16_t)0x0028) 95 | #define BKP_DR11 ((uint16_t)0x0040) 96 | #define BKP_DR12 ((uint16_t)0x0044) 97 | #define BKP_DR13 ((uint16_t)0x0048) 98 | #define BKP_DR14 ((uint16_t)0x004C) 99 | #define BKP_DR15 ((uint16_t)0x0050) 100 | #define BKP_DR16 ((uint16_t)0x0054) 101 | #define BKP_DR17 ((uint16_t)0x0058) 102 | #define BKP_DR18 ((uint16_t)0x005C) 103 | #define BKP_DR19 ((uint16_t)0x0060) 104 | #define BKP_DR20 ((uint16_t)0x0064) 105 | #define BKP_DR21 ((uint16_t)0x0068) 106 | #define BKP_DR22 ((uint16_t)0x006C) 107 | #define BKP_DR23 ((uint16_t)0x0070) 108 | #define BKP_DR24 ((uint16_t)0x0074) 109 | #define BKP_DR25 ((uint16_t)0x0078) 110 | #define BKP_DR26 ((uint16_t)0x007C) 111 | #define BKP_DR27 ((uint16_t)0x0080) 112 | #define BKP_DR28 ((uint16_t)0x0084) 113 | #define BKP_DR29 ((uint16_t)0x0088) 114 | #define BKP_DR30 ((uint16_t)0x008C) 115 | #define BKP_DR31 ((uint16_t)0x0090) 116 | #define BKP_DR32 ((uint16_t)0x0094) 117 | #define BKP_DR33 ((uint16_t)0x0098) 118 | #define BKP_DR34 ((uint16_t)0x009C) 119 | #define BKP_DR35 ((uint16_t)0x00A0) 120 | #define BKP_DR36 ((uint16_t)0x00A4) 121 | #define BKP_DR37 ((uint16_t)0x00A8) 122 | #define BKP_DR38 ((uint16_t)0x00AC) 123 | #define BKP_DR39 ((uint16_t)0x00B0) 124 | #define BKP_DR40 ((uint16_t)0x00B4) 125 | #define BKP_DR41 ((uint16_t)0x00B8) 126 | #define BKP_DR42 ((uint16_t)0x00BC) 127 | 128 | #define IS_BKP_DR(DR) (((DR) == BKP_DR1) || ((DR) == BKP_DR2) || ((DR) == BKP_DR3) || \ 129 | ((DR) == BKP_DR4) || ((DR) == BKP_DR5) || ((DR) == BKP_DR6) || \ 130 | ((DR) == BKP_DR7) || ((DR) == BKP_DR8) || ((DR) == BKP_DR9) || \ 131 | ((DR) == BKP_DR10) || ((DR) == BKP_DR11) || ((DR) == BKP_DR12) || \ 132 | ((DR) == BKP_DR13) || ((DR) == BKP_DR14) || ((DR) == BKP_DR15) || \ 133 | ((DR) == BKP_DR16) || ((DR) == BKP_DR17) || ((DR) == BKP_DR18) || \ 134 | ((DR) == BKP_DR19) || ((DR) == BKP_DR20) || ((DR) == BKP_DR21) || \ 135 | ((DR) == BKP_DR22) || ((DR) == BKP_DR23) || ((DR) == BKP_DR24) || \ 136 | ((DR) == BKP_DR25) || ((DR) == BKP_DR26) || ((DR) == BKP_DR27) || \ 137 | ((DR) == BKP_DR28) || ((DR) == BKP_DR29) || ((DR) == BKP_DR30) || \ 138 | ((DR) == BKP_DR31) || ((DR) == BKP_DR32) || ((DR) == BKP_DR33) || \ 139 | ((DR) == BKP_DR34) || ((DR) == BKP_DR35) || ((DR) == BKP_DR36) || \ 140 | ((DR) == BKP_DR37) || ((DR) == BKP_DR38) || ((DR) == BKP_DR39) || \ 141 | ((DR) == BKP_DR40) || ((DR) == BKP_DR41) || ((DR) == BKP_DR42)) 142 | 143 | #define IS_BKP_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7F) 144 | /** 145 | * @} 146 | */ 147 | 148 | /** 149 | * @} 150 | */ 151 | 152 | /** @defgroup BKP_Exported_Macros 153 | * @{ 154 | */ 155 | 156 | /** 157 | * @} 158 | */ 159 | 160 | /** @defgroup BKP_Exported_Functions 161 | * @{ 162 | */ 163 | 164 | void BKP_DeInit(void); 165 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); 166 | void BKP_TamperPinCmd(FunctionalState NewState); 167 | void BKP_ITConfig(FunctionalState NewState); 168 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); 169 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); 170 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); 171 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); 172 | FlagStatus BKP_GetFlagStatus(void); 173 | void BKP_ClearFlag(void); 174 | ITStatus BKP_GetITStatus(void); 175 | void BKP_ClearITPendingBit(void); 176 | 177 | #ifdef __cplusplus 178 | } 179 | #endif 180 | 181 | #endif /* __STM32F10x_BKP_H */ 182 | /** 183 | * @} 184 | */ 185 | 186 | /** 187 | * @} 188 | */ 189 | 190 | /** 191 | * @} 192 | */ 193 | 194 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 195 | -------------------------------------------------------------------------------- /stdperiph/inc/misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file misc.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __MISC_H 24 | #define __MISC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup MISC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup MISC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief NVIC Init Structure definition 47 | */ 48 | 49 | typedef struct 50 | { 51 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 52 | This parameter can be a value of @ref IRQn_Type 53 | (For the complete STM32 Devices IRQ Channels list, please 54 | refer to stm32f10x.h file) */ 55 | 56 | uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel 57 | specified in NVIC_IRQChannel. This parameter can be a value 58 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 59 | 60 | uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified 61 | in NVIC_IRQChannel. This parameter can be a value 62 | between 0 and 15 as described in the table @ref NVIC_Priority_Table */ 63 | 64 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 65 | will be enabled or disabled. 66 | This parameter can be set either to ENABLE or DISABLE */ 67 | } NVIC_InitTypeDef; 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @defgroup NVIC_Priority_Table 74 | * @{ 75 | */ 76 | 77 | /** 78 | @code 79 | The table below gives the allowed values of the pre-emption priority and subpriority according 80 | to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function 81 | ============================================================================================================================ 82 | NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 83 | ============================================================================================================================ 84 | NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority 85 | | | | 4 bits for subpriority 86 | ---------------------------------------------------------------------------------------------------------------------------- 87 | NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority 88 | | | | 3 bits for subpriority 89 | ---------------------------------------------------------------------------------------------------------------------------- 90 | NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 91 | | | | 2 bits for subpriority 92 | ---------------------------------------------------------------------------------------------------------------------------- 93 | NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 94 | | | | 1 bits for subpriority 95 | ---------------------------------------------------------------------------------------------------------------------------- 96 | NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority 97 | | | | 0 bits for subpriority 98 | ============================================================================================================================ 99 | @endcode 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup MISC_Exported_Constants 107 | * @{ 108 | */ 109 | 110 | /** @defgroup Vector_Table_Base 111 | * @{ 112 | */ 113 | 114 | #define NVIC_VectTab_RAM ((uint32_t)0x20000000) 115 | #define NVIC_VectTab_FLASH ((uint32_t)0x08000000) 116 | #define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \ 117 | ((VECTTAB) == NVIC_VectTab_FLASH)) 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup System_Low_Power 123 | * @{ 124 | */ 125 | 126 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 127 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 128 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 129 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 130 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 131 | ((LP) == NVIC_LP_SLEEPONEXIT)) 132 | /** 133 | * @} 134 | */ 135 | 136 | /** @defgroup Preemption_Priority_Group 137 | * @{ 138 | */ 139 | 140 | #define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority 141 | 4 bits for subpriority */ 142 | #define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority 143 | 3 bits for subpriority */ 144 | #define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority 145 | 2 bits for subpriority */ 146 | #define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority 147 | 1 bits for subpriority */ 148 | #define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority 149 | 0 bits for subpriority */ 150 | 151 | #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \ 152 | ((GROUP) == NVIC_PriorityGroup_1) || \ 153 | ((GROUP) == NVIC_PriorityGroup_2) || \ 154 | ((GROUP) == NVIC_PriorityGroup_3) || \ 155 | ((GROUP) == NVIC_PriorityGroup_4)) 156 | 157 | #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 158 | 159 | #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 160 | 161 | #define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF) 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /** @defgroup SysTick_clock_source 168 | * @{ 169 | */ 170 | 171 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 172 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 173 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 174 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** @defgroup MISC_Exported_Macros 184 | * @{ 185 | */ 186 | 187 | /** 188 | * @} 189 | */ 190 | 191 | /** @defgroup MISC_Exported_Functions 192 | * @{ 193 | */ 194 | 195 | void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); 196 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 197 | void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset); 198 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 199 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 200 | 201 | #ifdef __cplusplus 202 | } 203 | #endif 204 | 205 | #endif /* __MISC_H */ 206 | 207 | /** 208 | * @} 209 | */ 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** 216 | * @} 217 | */ 218 | 219 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 220 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_bkp.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_bkp.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the BKP firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_bkp.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup BKP 30 | * @brief BKP driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup BKP_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup BKP_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* ------------ BKP registers bit address in the alias region --------------- */ 47 | #define BKP_OFFSET (BKP_BASE - PERIPH_BASE) 48 | 49 | /* --- CR Register ----*/ 50 | 51 | /* Alias word address of TPAL bit */ 52 | #define CR_OFFSET (BKP_OFFSET + 0x30) 53 | #define TPAL_BitNumber 0x01 54 | #define CR_TPAL_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPAL_BitNumber * 4)) 55 | 56 | /* Alias word address of TPE bit */ 57 | #define TPE_BitNumber 0x00 58 | #define CR_TPE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (TPE_BitNumber * 4)) 59 | 60 | /* --- CSR Register ---*/ 61 | 62 | /* Alias word address of TPIE bit */ 63 | #define CSR_OFFSET (BKP_OFFSET + 0x34) 64 | #define TPIE_BitNumber 0x02 65 | #define CSR_TPIE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TPIE_BitNumber * 4)) 66 | 67 | /* Alias word address of TIF bit */ 68 | #define TIF_BitNumber 0x09 69 | #define CSR_TIF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TIF_BitNumber * 4)) 70 | 71 | /* Alias word address of TEF bit */ 72 | #define TEF_BitNumber 0x08 73 | #define CSR_TEF_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEF_BitNumber * 4)) 74 | 75 | /* ---------------------- BKP registers bit mask ------------------------ */ 76 | 77 | /* RTCCR register bit mask */ 78 | #define RTCCR_CAL_MASK ((uint16_t)0xFF80) 79 | #define RTCCR_MASK ((uint16_t)0xFC7F) 80 | 81 | /** 82 | * @} 83 | */ 84 | 85 | 86 | /** @defgroup BKP_Private_Macros 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup BKP_Private_Variables 95 | * @{ 96 | */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** @defgroup BKP_Private_FunctionPrototypes 103 | * @{ 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | /** @defgroup BKP_Private_Functions 111 | * @{ 112 | */ 113 | 114 | /** 115 | * @brief Deinitializes the BKP peripheral registers to their default reset values. 116 | * @param None 117 | * @retval None 118 | */ 119 | void BKP_DeInit(void) 120 | { 121 | RCC_BackupResetCmd(ENABLE); 122 | RCC_BackupResetCmd(DISABLE); 123 | } 124 | 125 | /** 126 | * @brief Configures the Tamper Pin active level. 127 | * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. 128 | * This parameter can be one of the following values: 129 | * @arg BKP_TamperPinLevel_High: Tamper pin active on high level 130 | * @arg BKP_TamperPinLevel_Low: Tamper pin active on low level 131 | * @retval None 132 | */ 133 | void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) 134 | { 135 | /* Check the parameters */ 136 | assert_param(IS_BKP_TAMPER_PIN_LEVEL(BKP_TamperPinLevel)); 137 | *(__IO uint32_t *) CR_TPAL_BB = BKP_TamperPinLevel; 138 | } 139 | 140 | /** 141 | * @brief Enables or disables the Tamper Pin activation. 142 | * @param NewState: new state of the Tamper Pin activation. 143 | * This parameter can be: ENABLE or DISABLE. 144 | * @retval None 145 | */ 146 | void BKP_TamperPinCmd(FunctionalState NewState) 147 | { 148 | /* Check the parameters */ 149 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 150 | *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; 151 | } 152 | 153 | /** 154 | * @brief Enables or disables the Tamper Pin Interrupt. 155 | * @param NewState: new state of the Tamper Pin Interrupt. 156 | * This parameter can be: ENABLE or DISABLE. 157 | * @retval None 158 | */ 159 | void BKP_ITConfig(FunctionalState NewState) 160 | { 161 | /* Check the parameters */ 162 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 163 | *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; 164 | } 165 | 166 | /** 167 | * @brief Select the RTC output source to output on the Tamper pin. 168 | * @param BKP_RTCOutputSource: specifies the RTC output source. 169 | * This parameter can be one of the following values: 170 | * @arg BKP_RTCOutputSource_None: no RTC output on the Tamper pin. 171 | * @arg BKP_RTCOutputSource_CalibClock: output the RTC clock with frequency 172 | * divided by 64 on the Tamper pin. 173 | * @arg BKP_RTCOutputSource_Alarm: output the RTC Alarm pulse signal on 174 | * the Tamper pin. 175 | * @arg BKP_RTCOutputSource_Second: output the RTC Second pulse signal on 176 | * the Tamper pin. 177 | * @retval None 178 | */ 179 | void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) 180 | { 181 | uint16_t tmpreg = 0; 182 | /* Check the parameters */ 183 | assert_param(IS_BKP_RTC_OUTPUT_SOURCE(BKP_RTCOutputSource)); 184 | tmpreg = BKP->RTCCR; 185 | /* Clear CCO, ASOE and ASOS bits */ 186 | tmpreg &= RTCCR_MASK; 187 | 188 | /* Set CCO, ASOE and ASOS bits according to BKP_RTCOutputSource value */ 189 | tmpreg |= BKP_RTCOutputSource; 190 | /* Store the new value */ 191 | BKP->RTCCR = tmpreg; 192 | } 193 | 194 | /** 195 | * @brief Sets RTC Clock Calibration value. 196 | * @param CalibrationValue: specifies the RTC Clock Calibration value. 197 | * This parameter must be a number between 0 and 0x7F. 198 | * @retval None 199 | */ 200 | void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) 201 | { 202 | uint16_t tmpreg = 0; 203 | /* Check the parameters */ 204 | assert_param(IS_BKP_CALIBRATION_VALUE(CalibrationValue)); 205 | tmpreg = BKP->RTCCR; 206 | /* Clear CAL[6:0] bits */ 207 | tmpreg &= RTCCR_CAL_MASK; 208 | /* Set CAL[6:0] bits according to CalibrationValue value */ 209 | tmpreg |= CalibrationValue; 210 | /* Store the new value */ 211 | BKP->RTCCR = tmpreg; 212 | } 213 | 214 | /** 215 | * @brief Writes user data to the specified Data Backup Register. 216 | * @param BKP_DR: specifies the Data Backup Register. 217 | * This parameter can be BKP_DRx where x:[1, 42] 218 | * @param Data: data to write 219 | * @retval None 220 | */ 221 | void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) 222 | { 223 | __IO uint32_t tmp = 0; 224 | 225 | /* Check the parameters */ 226 | assert_param(IS_BKP_DR(BKP_DR)); 227 | 228 | tmp = (uint32_t)BKP_BASE; 229 | tmp += BKP_DR; 230 | 231 | *(__IO uint32_t *) tmp = Data; 232 | } 233 | 234 | /** 235 | * @brief Reads data from the specified Data Backup Register. 236 | * @param BKP_DR: specifies the Data Backup Register. 237 | * This parameter can be BKP_DRx where x:[1, 42] 238 | * @retval The content of the specified Data Backup Register 239 | */ 240 | uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) 241 | { 242 | __IO uint32_t tmp = 0; 243 | 244 | /* Check the parameters */ 245 | assert_param(IS_BKP_DR(BKP_DR)); 246 | 247 | tmp = (uint32_t)BKP_BASE; 248 | tmp += BKP_DR; 249 | 250 | return (*(__IO uint16_t *) tmp); 251 | } 252 | 253 | /** 254 | * @brief Checks whether the Tamper Pin Event flag is set or not. 255 | * @param None 256 | * @retval The new state of the Tamper Pin Event flag (SET or RESET). 257 | */ 258 | FlagStatus BKP_GetFlagStatus(void) 259 | { 260 | return (FlagStatus)(*(__IO uint32_t *) CSR_TEF_BB); 261 | } 262 | 263 | /** 264 | * @brief Clears Tamper Pin Event pending flag. 265 | * @param None 266 | * @retval None 267 | */ 268 | void BKP_ClearFlag(void) 269 | { 270 | /* Set CTE bit to clear Tamper Pin Event flag */ 271 | BKP->CSR |= BKP_CSR_CTE; 272 | } 273 | 274 | /** 275 | * @brief Checks whether the Tamper Pin Interrupt has occurred or not. 276 | * @param None 277 | * @retval The new state of the Tamper Pin Interrupt (SET or RESET). 278 | */ 279 | ITStatus BKP_GetITStatus(void) 280 | { 281 | return (ITStatus)(*(__IO uint32_t *) CSR_TIF_BB); 282 | } 283 | 284 | /** 285 | * @brief Clears Tamper Pin Interrupt pending bit. 286 | * @param None 287 | * @retval None 288 | */ 289 | void BKP_ClearITPendingBit(void) 290 | { 291 | /* Set CTI bit to clear Tamper Pin Interrupt pending bit */ 292 | BKP->CSR |= BKP_CSR_CTI; 293 | } 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /** 304 | * @} 305 | */ 306 | 307 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 308 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_pwr.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_pwr.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the PWR firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_pwr.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup PWR 30 | * @brief PWR driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup PWR_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | /** @defgroup PWR_Private_Defines 43 | * @{ 44 | */ 45 | 46 | /* --------- PWR registers bit address in the alias region ---------- */ 47 | #define PWR_OFFSET (PWR_BASE - PERIPH_BASE) 48 | 49 | /* --- CR Register ---*/ 50 | 51 | /* Alias word address of DBP bit */ 52 | #define CR_OFFSET (PWR_OFFSET + 0x00) 53 | #define DBP_BitNumber 0x08 54 | #define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4)) 55 | 56 | /* Alias word address of PVDE bit */ 57 | #define PVDE_BitNumber 0x04 58 | #define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4)) 59 | 60 | /* --- CSR Register ---*/ 61 | 62 | /* Alias word address of EWUP bit */ 63 | #define CSR_OFFSET (PWR_OFFSET + 0x04) 64 | #define EWUP_BitNumber 0x08 65 | #define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4)) 66 | 67 | /* ------------------ PWR registers bit mask ------------------------ */ 68 | 69 | /* CR register bit mask */ 70 | #define CR_DS_MASK ((uint32_t)0xFFFFFFFC) 71 | #define CR_PLS_MASK ((uint32_t)0xFFFFFF1F) 72 | 73 | 74 | /** 75 | * @} 76 | */ 77 | 78 | /** @defgroup PWR_Private_Macros 79 | * @{ 80 | */ 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | /** @defgroup PWR_Private_Variables 87 | * @{ 88 | */ 89 | 90 | /** 91 | * @} 92 | */ 93 | 94 | /** @defgroup PWR_Private_FunctionPrototypes 95 | * @{ 96 | */ 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** @defgroup PWR_Private_Functions 103 | * @{ 104 | */ 105 | 106 | /** 107 | * @brief Deinitializes the PWR peripheral registers to their default reset values. 108 | * @param None 109 | * @retval None 110 | */ 111 | void PWR_DeInit(void) 112 | { 113 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); 114 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); 115 | } 116 | 117 | /** 118 | * @brief Enables or disables access to the RTC and backup registers. 119 | * @param NewState: new state of the access to the RTC and backup registers. 120 | * This parameter can be: ENABLE or DISABLE. 121 | * @retval None 122 | */ 123 | void PWR_BackupAccessCmd(FunctionalState NewState) 124 | { 125 | /* Check the parameters */ 126 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 127 | *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState; 128 | } 129 | 130 | /** 131 | * @brief Enables or disables the Power Voltage Detector(PVD). 132 | * @param NewState: new state of the PVD. 133 | * This parameter can be: ENABLE or DISABLE. 134 | * @retval None 135 | */ 136 | void PWR_PVDCmd(FunctionalState NewState) 137 | { 138 | /* Check the parameters */ 139 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 140 | *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; 141 | } 142 | 143 | /** 144 | * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD). 145 | * @param PWR_PVDLevel: specifies the PVD detection level 146 | * This parameter can be one of the following values: 147 | * @arg PWR_PVDLevel_2V2: PVD detection level set to 2.2V 148 | * @arg PWR_PVDLevel_2V3: PVD detection level set to 2.3V 149 | * @arg PWR_PVDLevel_2V4: PVD detection level set to 2.4V 150 | * @arg PWR_PVDLevel_2V5: PVD detection level set to 2.5V 151 | * @arg PWR_PVDLevel_2V6: PVD detection level set to 2.6V 152 | * @arg PWR_PVDLevel_2V7: PVD detection level set to 2.7V 153 | * @arg PWR_PVDLevel_2V8: PVD detection level set to 2.8V 154 | * @arg PWR_PVDLevel_2V9: PVD detection level set to 2.9V 155 | * @retval None 156 | */ 157 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) 158 | { 159 | uint32_t tmpreg = 0; 160 | /* Check the parameters */ 161 | assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel)); 162 | tmpreg = PWR->CR; 163 | /* Clear PLS[7:5] bits */ 164 | tmpreg &= CR_PLS_MASK; 165 | /* Set PLS[7:5] bits according to PWR_PVDLevel value */ 166 | tmpreg |= PWR_PVDLevel; 167 | /* Store the new value */ 168 | PWR->CR = tmpreg; 169 | } 170 | 171 | /** 172 | * @brief Enables or disables the WakeUp Pin functionality. 173 | * @param NewState: new state of the WakeUp Pin functionality. 174 | * This parameter can be: ENABLE or DISABLE. 175 | * @retval None 176 | */ 177 | void PWR_WakeUpPinCmd(FunctionalState NewState) 178 | { 179 | /* Check the parameters */ 180 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 181 | *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; 182 | } 183 | 184 | /** 185 | * @brief Enters STOP mode. 186 | * @param PWR_Regulator: specifies the regulator state in STOP mode. 187 | * This parameter can be one of the following values: 188 | * @arg PWR_Regulator_ON: STOP mode with regulator ON 189 | * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode 190 | * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. 191 | * This parameter can be one of the following values: 192 | * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction 193 | * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction 194 | * @retval None 195 | */ 196 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) 197 | { 198 | uint32_t tmpreg = 0; 199 | /* Check the parameters */ 200 | assert_param(IS_PWR_REGULATOR(PWR_Regulator)); 201 | assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry)); 202 | 203 | /* Select the regulator state in STOP mode ---------------------------------*/ 204 | tmpreg = PWR->CR; 205 | /* Clear PDDS and LPDS bits */ 206 | tmpreg &= CR_DS_MASK; 207 | /* Set LPDS bit according to PWR_Regulator value */ 208 | tmpreg |= PWR_Regulator; 209 | /* Store the new value */ 210 | PWR->CR = tmpreg; 211 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 212 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 213 | 214 | /* Select STOP mode entry --------------------------------------------------*/ 215 | if(PWR_STOPEntry == PWR_STOPEntry_WFI) 216 | { 217 | /* Request Wait For Interrupt */ 218 | __WFI(); 219 | } 220 | else 221 | { 222 | /* Request Wait For Event */ 223 | __WFE(); 224 | } 225 | 226 | /* Reset SLEEPDEEP bit of Cortex System Control Register */ 227 | SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); 228 | } 229 | 230 | /** 231 | * @brief Enters STANDBY mode. 232 | * @param None 233 | * @retval None 234 | */ 235 | void PWR_EnterSTANDBYMode(void) 236 | { 237 | /* Clear Wake-up flag */ 238 | PWR->CR |= PWR_CR_CWUF; 239 | /* Select STANDBY mode */ 240 | PWR->CR |= PWR_CR_PDDS; 241 | /* Set SLEEPDEEP bit of Cortex System Control Register */ 242 | SCB->SCR |= SCB_SCR_SLEEPDEEP; 243 | /* This option is used to ensure that store operations are completed */ 244 | #if defined ( __CC_ARM ) 245 | __force_stores(); 246 | #endif 247 | /* Request Wait For Interrupt */ 248 | __WFI(); 249 | } 250 | 251 | /** 252 | * @brief Checks whether the specified PWR flag is set or not. 253 | * @param PWR_FLAG: specifies the flag to check. 254 | * This parameter can be one of the following values: 255 | * @arg PWR_FLAG_WU: Wake Up flag 256 | * @arg PWR_FLAG_SB: StandBy flag 257 | * @arg PWR_FLAG_PVDO: PVD Output 258 | * @retval The new state of PWR_FLAG (SET or RESET). 259 | */ 260 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) 261 | { 262 | FlagStatus bitstatus = RESET; 263 | /* Check the parameters */ 264 | assert_param(IS_PWR_GET_FLAG(PWR_FLAG)); 265 | 266 | if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) 267 | { 268 | bitstatus = SET; 269 | } 270 | else 271 | { 272 | bitstatus = RESET; 273 | } 274 | /* Return the flag status */ 275 | return bitstatus; 276 | } 277 | 278 | /** 279 | * @brief Clears the PWR's pending flags. 280 | * @param PWR_FLAG: specifies the flag to clear. 281 | * This parameter can be one of the following values: 282 | * @arg PWR_FLAG_WU: Wake Up flag 283 | * @arg PWR_FLAG_SB: StandBy flag 284 | * @retval None 285 | */ 286 | void PWR_ClearFlag(uint32_t PWR_FLAG) 287 | { 288 | /* Check the parameters */ 289 | assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG)); 290 | 291 | PWR->CR |= PWR_FLAG << 2; 292 | } 293 | 294 | /** 295 | * @} 296 | */ 297 | 298 | /** 299 | * @} 300 | */ 301 | 302 | /** 303 | * @} 304 | */ 305 | 306 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 307 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /stdperiph/src/stm32f10x_cec.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_cec.c 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file provides all the CEC firmware functions. 8 | ****************************************************************************** 9 | * @copy 10 | * 11 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 12 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 13 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 14 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 15 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 16 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 17 | * 18 | *

© COPYRIGHT 2010 STMicroelectronics

19 | */ 20 | 21 | /* Includes ------------------------------------------------------------------*/ 22 | #include "stm32f10x_cec.h" 23 | #include "stm32f10x_rcc.h" 24 | 25 | /** @addtogroup STM32F10x_StdPeriph_Driver 26 | * @{ 27 | */ 28 | 29 | /** @defgroup CEC 30 | * @brief CEC driver modules 31 | * @{ 32 | */ 33 | 34 | /** @defgroup CEC_Private_TypesDefinitions 35 | * @{ 36 | */ 37 | 38 | /** 39 | * @} 40 | */ 41 | 42 | 43 | /** @defgroup CEC_Private_Defines 44 | * @{ 45 | */ 46 | 47 | /* ------------ CEC registers bit address in the alias region ----------- */ 48 | #define CEC_OFFSET (CEC_BASE - PERIPH_BASE) 49 | 50 | /* --- CFGR Register ---*/ 51 | 52 | /* Alias word address of PE bit */ 53 | #define CFGR_OFFSET (CEC_OFFSET + 0x00) 54 | #define PE_BitNumber 0x00 55 | #define CFGR_PE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (PE_BitNumber * 4)) 56 | 57 | /* Alias word address of IE bit */ 58 | #define IE_BitNumber 0x01 59 | #define CFGR_IE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (IE_BitNumber * 4)) 60 | 61 | /* --- CSR Register ---*/ 62 | 63 | /* Alias word address of TSOM bit */ 64 | #define CSR_OFFSET (CEC_OFFSET + 0x10) 65 | #define TSOM_BitNumber 0x00 66 | #define CSR_TSOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TSOM_BitNumber * 4)) 67 | 68 | /* Alias word address of TEOM bit */ 69 | #define TEOM_BitNumber 0x01 70 | #define CSR_TEOM_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (TEOM_BitNumber * 4)) 71 | 72 | #define CFGR_CLEAR_Mask (uint8_t)(0xF3) /* CFGR register Mask */ 73 | #define FLAG_Mask ((uint32_t)0x00FFFFFF) /* CEC FLAG mask */ 74 | 75 | /** 76 | * @} 77 | */ 78 | 79 | 80 | /** @defgroup CEC_Private_Macros 81 | * @{ 82 | */ 83 | 84 | /** 85 | * @} 86 | */ 87 | 88 | 89 | /** @defgroup CEC_Private_Variables 90 | * @{ 91 | */ 92 | 93 | /** 94 | * @} 95 | */ 96 | 97 | 98 | /** @defgroup CEC_Private_FunctionPrototypes 99 | * @{ 100 | */ 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | 107 | /** @defgroup CEC_Private_Functions 108 | * @{ 109 | */ 110 | 111 | /** 112 | * @brief Deinitializes the CEC peripheral registers to their default reset 113 | * values. 114 | * @param None 115 | * @retval None 116 | */ 117 | void CEC_DeInit(void) 118 | { 119 | /* Enable CEC reset state */ 120 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE); 121 | /* Release CEC from reset state */ 122 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE); 123 | } 124 | 125 | 126 | /** 127 | * @brief Initializes the CEC peripheral according to the specified 128 | * parameters in the CEC_InitStruct. 129 | * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that 130 | * contains the configuration information for the specified 131 | * CEC peripheral. 132 | * @retval None 133 | */ 134 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct) 135 | { 136 | uint16_t tmpreg = 0; 137 | 138 | /* Check the parameters */ 139 | assert_param(IS_CEC_BIT_TIMING_ERROR_MODE(CEC_InitStruct->CEC_BitTimingMode)); 140 | assert_param(IS_CEC_BIT_PERIOD_ERROR_MODE(CEC_InitStruct->CEC_BitPeriodMode)); 141 | 142 | /*---------------------------- CEC CFGR Configuration -----------------*/ 143 | /* Get the CEC CFGR value */ 144 | tmpreg = CEC->CFGR; 145 | 146 | /* Clear BTEM and BPEM bits */ 147 | tmpreg &= CFGR_CLEAR_Mask; 148 | 149 | /* Configure CEC: Bit Timing Error and Bit Period Error */ 150 | tmpreg |= (uint16_t)(CEC_InitStruct->CEC_BitTimingMode | CEC_InitStruct->CEC_BitPeriodMode); 151 | 152 | /* Write to CEC CFGR register*/ 153 | CEC->CFGR = tmpreg; 154 | 155 | } 156 | 157 | /** 158 | * @brief Enables or disables the specified CEC peripheral. 159 | * @param NewState: new state of the CEC peripheral. 160 | * This parameter can be: ENABLE or DISABLE. 161 | * @retval None 162 | */ 163 | void CEC_Cmd(FunctionalState NewState) 164 | { 165 | /* Check the parameters */ 166 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 167 | 168 | *(__IO uint32_t *) CFGR_PE_BB = (uint32_t)NewState; 169 | 170 | if(NewState == DISABLE) 171 | { 172 | /* Wait until the PE bit is cleared by hardware (Idle Line detected) */ 173 | while((CEC->CFGR & CEC_CFGR_PE) != (uint32_t)RESET) 174 | { 175 | } 176 | } 177 | } 178 | 179 | /** 180 | * @brief Enables or disables the CEC interrupt. 181 | * @param NewState: new state of the CEC interrupt. 182 | * This parameter can be: ENABLE or DISABLE. 183 | * @retval None 184 | */ 185 | void CEC_ITConfig(FunctionalState NewState) 186 | { 187 | /* Check the parameters */ 188 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 189 | 190 | *(__IO uint32_t *) CFGR_IE_BB = (uint32_t)NewState; 191 | } 192 | 193 | /** 194 | * @brief Defines the Own Address of the CEC device. 195 | * @param CEC_OwnAddress: The CEC own address 196 | * @retval None 197 | */ 198 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress) 199 | { 200 | /* Check the parameters */ 201 | assert_param(IS_CEC_ADDRESS(CEC_OwnAddress)); 202 | 203 | /* Set the CEC own address */ 204 | CEC->OAR = CEC_OwnAddress; 205 | } 206 | 207 | /** 208 | * @brief Sets the CEC prescaler value. 209 | * @param CEC_Prescaler: CEC prescaler new value 210 | * @retval None 211 | */ 212 | void CEC_SetPrescaler(uint16_t CEC_Prescaler) 213 | { 214 | /* Check the parameters */ 215 | assert_param(IS_CEC_PRESCALER(CEC_Prescaler)); 216 | 217 | /* Set the Prescaler value*/ 218 | CEC->PRES = CEC_Prescaler; 219 | } 220 | 221 | /** 222 | * @brief Transmits single data through the CEC peripheral. 223 | * @param Data: the data to transmit. 224 | * @retval None 225 | */ 226 | void CEC_SendDataByte(uint8_t Data) 227 | { 228 | /* Transmit Data */ 229 | CEC->TXD = Data ; 230 | } 231 | 232 | 233 | /** 234 | * @brief Returns the most recent received data by the CEC peripheral. 235 | * @param None 236 | * @retval The received data. 237 | */ 238 | uint8_t CEC_ReceiveDataByte(void) 239 | { 240 | /* Receive Data */ 241 | return (uint8_t)(CEC->RXD); 242 | } 243 | 244 | /** 245 | * @brief Starts a new message. 246 | * @param None 247 | * @retval None 248 | */ 249 | void CEC_StartOfMessage(void) 250 | { 251 | /* Starts of new message */ 252 | *(__IO uint32_t *) CSR_TSOM_BB = (uint32_t)0x1; 253 | } 254 | 255 | /** 256 | * @brief Transmits message with or without an EOM bit. 257 | * @param NewState: new state of the CEC Tx End Of Message. 258 | * This parameter can be: ENABLE or DISABLE. 259 | * @retval None 260 | */ 261 | void CEC_EndOfMessageCmd(FunctionalState NewState) 262 | { 263 | /* Check the parameters */ 264 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 265 | 266 | /* The data byte will be transmitted with or without an EOM bit*/ 267 | *(__IO uint32_t *) CSR_TEOM_BB = (uint32_t)NewState; 268 | } 269 | 270 | /** 271 | * @brief Gets the CEC flag status 272 | * @param CEC_FLAG: specifies the CEC flag to check. 273 | * This parameter can be one of the following values: 274 | * @arg CEC_FLAG_BTE: Bit Timing Error 275 | * @arg CEC_FLAG_BPE: Bit Period Error 276 | * @arg CEC_FLAG_RBTFE: Rx Block Transfer Finished Error 277 | * @arg CEC_FLAG_SBE: Start Bit Error 278 | * @arg CEC_FLAG_ACKE: Block Acknowledge Error 279 | * @arg CEC_FLAG_LINE: Line Error 280 | * @arg CEC_FLAG_TBTFE: Tx Block Transfer Finsihed Error 281 | * @arg CEC_FLAG_TEOM: Tx End Of Message 282 | * @arg CEC_FLAG_TERR: Tx Error 283 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 284 | * @arg CEC_FLAG_RSOM: Rx Start Of Message 285 | * @arg CEC_FLAG_REOM: Rx End Of Message 286 | * @arg CEC_FLAG_RERR: Rx Error 287 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 288 | * @retval The new state of CEC_FLAG (SET or RESET) 289 | */ 290 | FlagStatus CEC_GetFlagStatus(uint32_t CEC_FLAG) 291 | { 292 | FlagStatus bitstatus = RESET; 293 | uint32_t cecreg = 0, cecbase = 0; 294 | 295 | /* Check the parameters */ 296 | assert_param(IS_CEC_GET_FLAG(CEC_FLAG)); 297 | 298 | /* Get the CEC peripheral base address */ 299 | cecbase = (uint32_t)(CEC_BASE); 300 | 301 | /* Read flag register index */ 302 | cecreg = CEC_FLAG >> 28; 303 | 304 | /* Get bit[23:0] of the flag */ 305 | CEC_FLAG &= FLAG_Mask; 306 | 307 | if(cecreg != 0) 308 | { 309 | /* Flag in CEC ESR Register */ 310 | CEC_FLAG = (uint32_t)(CEC_FLAG >> 16); 311 | 312 | /* Get the CEC ESR register address */ 313 | cecbase += 0xC; 314 | } 315 | else 316 | { 317 | /* Get the CEC CSR register address */ 318 | cecbase += 0x10; 319 | } 320 | 321 | if(((*(__IO uint32_t *)cecbase) & CEC_FLAG) != (uint32_t)RESET) 322 | { 323 | /* CEC_FLAG is set */ 324 | bitstatus = SET; 325 | } 326 | else 327 | { 328 | /* CEC_FLAG is reset */ 329 | bitstatus = RESET; 330 | } 331 | 332 | /* Return the CEC_FLAG status */ 333 | return bitstatus; 334 | } 335 | 336 | /** 337 | * @brief Clears the CEC's pending flags. 338 | * @param CEC_FLAG: specifies the flag to clear. 339 | * This parameter can be any combination of the following values: 340 | * @arg CEC_FLAG_TERR: Tx Error 341 | * @arg CEC_FLAG_TBTRF: Tx Byte Transfer Request or Block Transfer Finished 342 | * @arg CEC_FLAG_RSOM: Rx Start Of Message 343 | * @arg CEC_FLAG_REOM: Rx End Of Message 344 | * @arg CEC_FLAG_RERR: Rx Error 345 | * @arg CEC_FLAG_RBTF: Rx Byte/Block Transfer Finished 346 | * @retval None 347 | */ 348 | void CEC_ClearFlag(uint32_t CEC_FLAG) 349 | { 350 | uint32_t tmp = 0x0; 351 | 352 | /* Check the parameters */ 353 | assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG)); 354 | 355 | tmp = CEC->CSR & 0x2; 356 | 357 | /* Clear the selected CEC flags */ 358 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_FLAG) & 0xFFFFFFFC) | tmp); 359 | } 360 | 361 | /** 362 | * @brief Checks whether the specified CEC interrupt has occurred or not. 363 | * @param CEC_IT: specifies the CEC interrupt source to check. 364 | * This parameter can be one of the following values: 365 | * @arg CEC_IT_TERR: Tx Error 366 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished 367 | * @arg CEC_IT_RERR: Rx Error 368 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished 369 | * @retval The new state of CEC_IT (SET or RESET). 370 | */ 371 | ITStatus CEC_GetITStatus(uint8_t CEC_IT) 372 | { 373 | ITStatus bitstatus = RESET; 374 | uint32_t enablestatus = 0; 375 | 376 | /* Check the parameters */ 377 | assert_param(IS_CEC_GET_IT(CEC_IT)); 378 | 379 | /* Get the CEC IT enable bit status */ 380 | enablestatus = (CEC->CFGR & (uint8_t)CEC_CFGR_IE) ; 381 | 382 | /* Check the status of the specified CEC interrupt */ 383 | if (((CEC->CSR & CEC_IT) != (uint32_t)RESET) && enablestatus) 384 | { 385 | /* CEC_IT is set */ 386 | bitstatus = SET; 387 | } 388 | else 389 | { 390 | /* CEC_IT is reset */ 391 | bitstatus = RESET; 392 | } 393 | /* Return the CEC_IT status */ 394 | return bitstatus; 395 | } 396 | 397 | /** 398 | * @brief Clears the CEC's interrupt pending bits. 399 | * @param CEC_IT: specifies the CEC interrupt pending bit to clear. 400 | * This parameter can be any combination of the following values: 401 | * @arg CEC_IT_TERR: Tx Error 402 | * @arg CEC_IT_TBTF: Tx Block Transfer Finished 403 | * @arg CEC_IT_RERR: Rx Error 404 | * @arg CEC_IT_RBTF: Rx Block Transfer Finished 405 | * @retval None 406 | */ 407 | void CEC_ClearITPendingBit(uint16_t CEC_IT) 408 | { 409 | uint32_t tmp = 0x0; 410 | 411 | /* Check the parameters */ 412 | assert_param(IS_CEC_GET_IT(CEC_IT)); 413 | 414 | tmp = CEC->CSR & 0x2; 415 | 416 | /* Clear the selected CEC interrupt pending bits */ 417 | CEC->CSR &= (uint32_t)(((~(uint32_t)CEC_IT) & 0xFFFFFFFC) | tmp); 418 | } 419 | 420 | /** 421 | * @} 422 | */ 423 | 424 | /** 425 | * @} 426 | */ 427 | 428 | /** 429 | * @} 430 | */ 431 | 432 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 433 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_dac.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_dac.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the DAC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_DAC_H 24 | #define __STM32F10x_DAC_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup DAC 38 | * @{ 39 | */ 40 | 41 | /** @defgroup DAC_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief DAC Init structure definition 47 | */ 48 | 49 | typedef struct 50 | { 51 | uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel. 52 | This parameter can be a value of @ref DAC_trigger_selection */ 53 | 54 | uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves 55 | are generated, or whether no wave is generated. 56 | This parameter can be a value of @ref DAC_wave_generation */ 57 | 58 | uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or 59 | the maximum amplitude triangle generation for the DAC channel. 60 | This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ 61 | 62 | uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled. 63 | This parameter can be a value of @ref DAC_output_buffer */ 64 | }DAC_InitTypeDef; 65 | 66 | /** 67 | * @} 68 | */ 69 | 70 | /** @defgroup DAC_Exported_Constants 71 | * @{ 72 | */ 73 | 74 | /** @defgroup DAC_trigger_selection 75 | * @{ 76 | */ 77 | 78 | #define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 79 | has been loaded, and not by external trigger */ 80 | #define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */ 81 | #define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel 82 | only in High-density devices*/ 83 | #define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel 84 | only in Connectivity line, Medium-density and Low-density Value Line devices */ 85 | #define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */ 86 | #define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */ 87 | #define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel 88 | only in Medium-density and Low-density Value Line devices*/ 89 | #define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */ 90 | #define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */ 91 | #define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */ 92 | #define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */ 93 | 94 | #define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \ 95 | ((TRIGGER) == DAC_Trigger_T6_TRGO) || \ 96 | ((TRIGGER) == DAC_Trigger_T8_TRGO) || \ 97 | ((TRIGGER) == DAC_Trigger_T7_TRGO) || \ 98 | ((TRIGGER) == DAC_Trigger_T5_TRGO) || \ 99 | ((TRIGGER) == DAC_Trigger_T2_TRGO) || \ 100 | ((TRIGGER) == DAC_Trigger_T4_TRGO) || \ 101 | ((TRIGGER) == DAC_Trigger_Ext_IT9) || \ 102 | ((TRIGGER) == DAC_Trigger_Software)) 103 | 104 | /** 105 | * @} 106 | */ 107 | 108 | /** @defgroup DAC_wave_generation 109 | * @{ 110 | */ 111 | 112 | #define DAC_WaveGeneration_None ((uint32_t)0x00000000) 113 | #define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) 114 | #define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) 115 | #define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \ 116 | ((WAVE) == DAC_WaveGeneration_Noise) || \ 117 | ((WAVE) == DAC_WaveGeneration_Triangle)) 118 | /** 119 | * @} 120 | */ 121 | 122 | /** @defgroup DAC_lfsrunmask_triangleamplitude 123 | * @{ 124 | */ 125 | 126 | #define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */ 127 | #define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */ 128 | #define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */ 129 | #define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */ 130 | #define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */ 131 | #define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */ 132 | #define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */ 133 | #define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */ 134 | #define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */ 135 | #define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */ 136 | #define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */ 137 | #define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */ 138 | #define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */ 139 | #define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */ 140 | #define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */ 141 | #define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */ 142 | #define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */ 143 | #define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */ 144 | #define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */ 145 | #define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */ 146 | #define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */ 147 | #define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */ 148 | #define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */ 149 | #define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */ 150 | 151 | #define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \ 152 | ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \ 153 | ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \ 154 | ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \ 155 | ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \ 156 | ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \ 157 | ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \ 158 | ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \ 159 | ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \ 160 | ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \ 161 | ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \ 162 | ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \ 163 | ((VALUE) == DAC_TriangleAmplitude_1) || \ 164 | ((VALUE) == DAC_TriangleAmplitude_3) || \ 165 | ((VALUE) == DAC_TriangleAmplitude_7) || \ 166 | ((VALUE) == DAC_TriangleAmplitude_15) || \ 167 | ((VALUE) == DAC_TriangleAmplitude_31) || \ 168 | ((VALUE) == DAC_TriangleAmplitude_63) || \ 169 | ((VALUE) == DAC_TriangleAmplitude_127) || \ 170 | ((VALUE) == DAC_TriangleAmplitude_255) || \ 171 | ((VALUE) == DAC_TriangleAmplitude_511) || \ 172 | ((VALUE) == DAC_TriangleAmplitude_1023) || \ 173 | ((VALUE) == DAC_TriangleAmplitude_2047) || \ 174 | ((VALUE) == DAC_TriangleAmplitude_4095)) 175 | /** 176 | * @} 177 | */ 178 | 179 | /** @defgroup DAC_output_buffer 180 | * @{ 181 | */ 182 | 183 | #define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) 184 | #define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) 185 | #define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \ 186 | ((STATE) == DAC_OutputBuffer_Disable)) 187 | /** 188 | * @} 189 | */ 190 | 191 | /** @defgroup DAC_Channel_selection 192 | * @{ 193 | */ 194 | 195 | #define DAC_Channel_1 ((uint32_t)0x00000000) 196 | #define DAC_Channel_2 ((uint32_t)0x00000010) 197 | #define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \ 198 | ((CHANNEL) == DAC_Channel_2)) 199 | /** 200 | * @} 201 | */ 202 | 203 | /** @defgroup DAC_data_alignement 204 | * @{ 205 | */ 206 | 207 | #define DAC_Align_12b_R ((uint32_t)0x00000000) 208 | #define DAC_Align_12b_L ((uint32_t)0x00000004) 209 | #define DAC_Align_8b_R ((uint32_t)0x00000008) 210 | #define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \ 211 | ((ALIGN) == DAC_Align_12b_L) || \ 212 | ((ALIGN) == DAC_Align_8b_R)) 213 | /** 214 | * @} 215 | */ 216 | 217 | /** @defgroup DAC_wave_generation 218 | * @{ 219 | */ 220 | 221 | #define DAC_Wave_Noise ((uint32_t)0x00000040) 222 | #define DAC_Wave_Triangle ((uint32_t)0x00000080) 223 | #define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \ 224 | ((WAVE) == DAC_Wave_Triangle)) 225 | /** 226 | * @} 227 | */ 228 | 229 | /** @defgroup DAC_data 230 | * @{ 231 | */ 232 | 233 | #define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 234 | /** 235 | * @} 236 | */ 237 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 238 | /** @defgroup DAC_interrupts_definition 239 | * @{ 240 | */ 241 | 242 | #define DAC_IT_DMAUDR ((uint32_t)0x00002000) 243 | #define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 244 | 245 | /** 246 | * @} 247 | */ 248 | 249 | /** @defgroup DAC_flags_definition 250 | * @{ 251 | */ 252 | 253 | #define DAC_FLAG_DMAUDR ((uint32_t)0x00002000) 254 | #define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR)) 255 | 256 | /** 257 | * @} 258 | */ 259 | #endif 260 | 261 | /** 262 | * @} 263 | */ 264 | 265 | /** @defgroup DAC_Exported_Macros 266 | * @{ 267 | */ 268 | 269 | /** 270 | * @} 271 | */ 272 | 273 | /** @defgroup DAC_Exported_Functions 274 | * @{ 275 | */ 276 | 277 | void DAC_DeInit(void); 278 | void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); 279 | void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); 280 | void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); 281 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 282 | void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState); 283 | #endif 284 | void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); 285 | void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); 286 | void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); 287 | void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); 288 | void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); 289 | void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); 290 | void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); 291 | uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); 292 | #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 293 | FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG); 294 | void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG); 295 | ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT); 296 | void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT); 297 | #endif 298 | 299 | #ifdef __cplusplus 300 | } 301 | #endif 302 | 303 | #endif /*__STM32F10x_DAC_H */ 304 | /** 305 | * @} 306 | */ 307 | 308 | /** 309 | * @} 310 | */ 311 | 312 | /** 313 | * @} 314 | */ 315 | 316 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 317 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_usart.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_usart.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the USART 8 | * firmware library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_USART_H 24 | #define __STM32F10x_USART_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup USART 38 | * @{ 39 | */ 40 | 41 | /** @defgroup USART_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief USART Init Structure definition 47 | */ 48 | 49 | typedef struct 50 | { 51 | uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate. 52 | The baud rate is computed using the following formula: 53 | - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) 54 | - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ 55 | 56 | uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. 57 | This parameter can be a value of @ref USART_Word_Length */ 58 | 59 | uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted. 60 | This parameter can be a value of @ref USART_Stop_Bits */ 61 | 62 | uint16_t USART_Parity; /*!< Specifies the parity mode. 63 | This parameter can be a value of @ref USART_Parity 64 | @note When parity is enabled, the computed parity is inserted 65 | at the MSB position of the transmitted data (9th bit when 66 | the word length is set to 9 data bits; 8th bit when the 67 | word length is set to 8 data bits). */ 68 | 69 | uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled. 70 | This parameter can be a value of @ref USART_Mode */ 71 | 72 | uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled 73 | or disabled. 74 | This parameter can be a value of @ref USART_Hardware_Flow_Control */ 75 | } USART_InitTypeDef; 76 | 77 | /** 78 | * @brief USART Clock Init Structure definition 79 | */ 80 | 81 | typedef struct 82 | { 83 | 84 | uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled. 85 | This parameter can be a value of @ref USART_Clock */ 86 | 87 | uint16_t USART_CPOL; /*!< Specifies the steady state value of the serial clock. 88 | This parameter can be a value of @ref USART_Clock_Polarity */ 89 | 90 | uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made. 91 | This parameter can be a value of @ref USART_Clock_Phase */ 92 | 93 | uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted 94 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. 95 | This parameter can be a value of @ref USART_Last_Bit */ 96 | } USART_ClockInitTypeDef; 97 | 98 | /** 99 | * @} 100 | */ 101 | 102 | /** @defgroup USART_Exported_Constants 103 | * @{ 104 | */ 105 | 106 | #define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \ 107 | ((PERIPH) == USART2) || \ 108 | ((PERIPH) == USART3) || \ 109 | ((PERIPH) == UART4) || \ 110 | ((PERIPH) == UART5)) 111 | 112 | #define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \ 113 | ((PERIPH) == USART2) || \ 114 | ((PERIPH) == USART3)) 115 | 116 | #define IS_USART_1234_PERIPH(PERIPH) (((PERIPH) == USART1) || \ 117 | ((PERIPH) == USART2) || \ 118 | ((PERIPH) == USART3) || \ 119 | ((PERIPH) == UART4)) 120 | /** @defgroup USART_Word_Length 121 | * @{ 122 | */ 123 | 124 | #define USART_WordLength_8b ((uint16_t)0x0000) 125 | #define USART_WordLength_9b ((uint16_t)0x1000) 126 | 127 | #define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \ 128 | ((LENGTH) == USART_WordLength_9b)) 129 | /** 130 | * @} 131 | */ 132 | 133 | /** @defgroup USART_Stop_Bits 134 | * @{ 135 | */ 136 | 137 | #define USART_StopBits_1 ((uint16_t)0x0000) 138 | #define USART_StopBits_0_5 ((uint16_t)0x1000) 139 | #define USART_StopBits_2 ((uint16_t)0x2000) 140 | #define USART_StopBits_1_5 ((uint16_t)0x3000) 141 | #define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \ 142 | ((STOPBITS) == USART_StopBits_0_5) || \ 143 | ((STOPBITS) == USART_StopBits_2) || \ 144 | ((STOPBITS) == USART_StopBits_1_5)) 145 | /** 146 | * @} 147 | */ 148 | 149 | /** @defgroup USART_Parity 150 | * @{ 151 | */ 152 | 153 | #define USART_Parity_No ((uint16_t)0x0000) 154 | #define USART_Parity_Even ((uint16_t)0x0400) 155 | #define USART_Parity_Odd ((uint16_t)0x0600) 156 | #define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \ 157 | ((PARITY) == USART_Parity_Even) || \ 158 | ((PARITY) == USART_Parity_Odd)) 159 | /** 160 | * @} 161 | */ 162 | 163 | /** @defgroup USART_Mode 164 | * @{ 165 | */ 166 | 167 | #define USART_Mode_Rx ((uint16_t)0x0004) 168 | #define USART_Mode_Tx ((uint16_t)0x0008) 169 | #define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00)) 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @defgroup USART_Hardware_Flow_Control 175 | * @{ 176 | */ 177 | #define USART_HardwareFlowControl_None ((uint16_t)0x0000) 178 | #define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) 179 | #define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) 180 | #define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) 181 | #define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\ 182 | (((CONTROL) == USART_HardwareFlowControl_None) || \ 183 | ((CONTROL) == USART_HardwareFlowControl_RTS) || \ 184 | ((CONTROL) == USART_HardwareFlowControl_CTS) || \ 185 | ((CONTROL) == USART_HardwareFlowControl_RTS_CTS)) 186 | /** 187 | * @} 188 | */ 189 | 190 | /** @defgroup USART_Clock 191 | * @{ 192 | */ 193 | #define USART_Clock_Disable ((uint16_t)0x0000) 194 | #define USART_Clock_Enable ((uint16_t)0x0800) 195 | #define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \ 196 | ((CLOCK) == USART_Clock_Enable)) 197 | /** 198 | * @} 199 | */ 200 | 201 | /** @defgroup USART_Clock_Polarity 202 | * @{ 203 | */ 204 | 205 | #define USART_CPOL_Low ((uint16_t)0x0000) 206 | #define USART_CPOL_High ((uint16_t)0x0400) 207 | #define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High)) 208 | 209 | /** 210 | * @} 211 | */ 212 | 213 | /** @defgroup USART_Clock_Phase 214 | * @{ 215 | */ 216 | 217 | #define USART_CPHA_1Edge ((uint16_t)0x0000) 218 | #define USART_CPHA_2Edge ((uint16_t)0x0200) 219 | #define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge)) 220 | 221 | /** 222 | * @} 223 | */ 224 | 225 | /** @defgroup USART_Last_Bit 226 | * @{ 227 | */ 228 | 229 | #define USART_LastBit_Disable ((uint16_t)0x0000) 230 | #define USART_LastBit_Enable ((uint16_t)0x0100) 231 | #define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \ 232 | ((LASTBIT) == USART_LastBit_Enable)) 233 | /** 234 | * @} 235 | */ 236 | 237 | /** @defgroup USART_Interrupt_definition 238 | * @{ 239 | */ 240 | 241 | #define USART_IT_PE ((uint16_t)0x0028) 242 | #define USART_IT_TXE ((uint16_t)0x0727) 243 | #define USART_IT_TC ((uint16_t)0x0626) 244 | #define USART_IT_RXNE ((uint16_t)0x0525) 245 | #define USART_IT_IDLE ((uint16_t)0x0424) 246 | #define USART_IT_LBD ((uint16_t)0x0846) 247 | #define USART_IT_CTS ((uint16_t)0x096A) 248 | #define USART_IT_ERR ((uint16_t)0x0060) 249 | #define USART_IT_ORE ((uint16_t)0x0360) 250 | #define USART_IT_NE ((uint16_t)0x0260) 251 | #define USART_IT_FE ((uint16_t)0x0160) 252 | #define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ 253 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 254 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ 255 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR)) 256 | #define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \ 257 | ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 258 | ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \ 259 | ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \ 260 | ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE)) 261 | #define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \ 262 | ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS)) 263 | /** 264 | * @} 265 | */ 266 | 267 | /** @defgroup USART_DMA_Requests 268 | * @{ 269 | */ 270 | 271 | #define USART_DMAReq_Tx ((uint16_t)0x0080) 272 | #define USART_DMAReq_Rx ((uint16_t)0x0040) 273 | #define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00)) 274 | 275 | /** 276 | * @} 277 | */ 278 | 279 | /** @defgroup USART_WakeUp_methods 280 | * @{ 281 | */ 282 | 283 | #define USART_WakeUp_IdleLine ((uint16_t)0x0000) 284 | #define USART_WakeUp_AddressMark ((uint16_t)0x0800) 285 | #define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \ 286 | ((WAKEUP) == USART_WakeUp_AddressMark)) 287 | /** 288 | * @} 289 | */ 290 | 291 | /** @defgroup USART_LIN_Break_Detection_Length 292 | * @{ 293 | */ 294 | 295 | #define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) 296 | #define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) 297 | #define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \ 298 | (((LENGTH) == USART_LINBreakDetectLength_10b) || \ 299 | ((LENGTH) == USART_LINBreakDetectLength_11b)) 300 | /** 301 | * @} 302 | */ 303 | 304 | /** @defgroup USART_IrDA_Low_Power 305 | * @{ 306 | */ 307 | 308 | #define USART_IrDAMode_LowPower ((uint16_t)0x0004) 309 | #define USART_IrDAMode_Normal ((uint16_t)0x0000) 310 | #define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \ 311 | ((MODE) == USART_IrDAMode_Normal)) 312 | /** 313 | * @} 314 | */ 315 | 316 | /** @defgroup USART_Flags 317 | * @{ 318 | */ 319 | 320 | #define USART_FLAG_CTS ((uint16_t)0x0200) 321 | #define USART_FLAG_LBD ((uint16_t)0x0100) 322 | #define USART_FLAG_TXE ((uint16_t)0x0080) 323 | #define USART_FLAG_TC ((uint16_t)0x0040) 324 | #define USART_FLAG_RXNE ((uint16_t)0x0020) 325 | #define USART_FLAG_IDLE ((uint16_t)0x0010) 326 | #define USART_FLAG_ORE ((uint16_t)0x0008) 327 | #define USART_FLAG_NE ((uint16_t)0x0004) 328 | #define USART_FLAG_FE ((uint16_t)0x0002) 329 | #define USART_FLAG_PE ((uint16_t)0x0001) 330 | #define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \ 331 | ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \ 332 | ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \ 333 | ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \ 334 | ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE)) 335 | 336 | #define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00)) 337 | #define IS_USART_PERIPH_FLAG(PERIPH, USART_FLAG) ((((*(uint32_t*)&(PERIPH)) != UART4_BASE) &&\ 338 | ((*(uint32_t*)&(PERIPH)) != UART5_BASE)) \ 339 | || ((USART_FLAG) != USART_FLAG_CTS)) 340 | #define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x0044AA21)) 341 | #define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF) 342 | #define IS_USART_DATA(DATA) ((DATA) <= 0x1FF) 343 | 344 | /** 345 | * @} 346 | */ 347 | 348 | /** 349 | * @} 350 | */ 351 | 352 | /** @defgroup USART_Exported_Macros 353 | * @{ 354 | */ 355 | 356 | /** 357 | * @} 358 | */ 359 | 360 | /** @defgroup USART_Exported_Functions 361 | * @{ 362 | */ 363 | 364 | void USART_DeInit(USART_TypeDef* USARTx); 365 | void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); 366 | void USART_StructInit(USART_InitTypeDef* USART_InitStruct); 367 | void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); 368 | void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); 369 | void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 370 | void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); 371 | void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); 372 | void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); 373 | void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); 374 | void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); 375 | void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); 376 | void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); 377 | void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); 378 | uint16_t USART_ReceiveData(USART_TypeDef* USARTx); 379 | void USART_SendBreak(USART_TypeDef* USARTx); 380 | void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); 381 | void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); 382 | void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); 383 | void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); 384 | void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); 385 | void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState); 386 | void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState); 387 | void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); 388 | void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); 389 | FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); 390 | void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); 391 | ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); 392 | void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); 393 | 394 | #ifdef __cplusplus 395 | } 396 | #endif 397 | 398 | #endif /* __STM32F10x_USART_H */ 399 | /** 400 | * @} 401 | */ 402 | 403 | /** 404 | * @} 405 | */ 406 | 407 | /** 408 | * @} 409 | */ 410 | 411 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 412 | -------------------------------------------------------------------------------- /stdperiph/inc/stm32f10x_spi.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f10x_spi.h 4 | * @author MCD Application Team 5 | * @version V3.4.0 6 | * @date 10/15/2010 7 | * @brief This file contains all the functions prototypes for the SPI firmware 8 | * library. 9 | ****************************************************************************** 10 | * @copy 11 | * 12 | * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 13 | * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 14 | * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 15 | * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 16 | * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 17 | * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 18 | * 19 | *

© COPYRIGHT 2010 STMicroelectronics

20 | */ 21 | 22 | /* Define to prevent recursive inclusion -------------------------------------*/ 23 | #ifndef __STM32F10x_SPI_H 24 | #define __STM32F10x_SPI_H 25 | 26 | #ifdef __cplusplus 27 | extern "C" { 28 | #endif 29 | 30 | /* Includes ------------------------------------------------------------------*/ 31 | #include "stm32f10x.h" 32 | 33 | /** @addtogroup STM32F10x_StdPeriph_Driver 34 | * @{ 35 | */ 36 | 37 | /** @addtogroup SPI 38 | * @{ 39 | */ 40 | 41 | /** @defgroup SPI_Exported_Types 42 | * @{ 43 | */ 44 | 45 | /** 46 | * @brief SPI Init structure definition 47 | */ 48 | 49 | typedef struct 50 | { 51 | uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode. 52 | This parameter can be a value of @ref SPI_data_direction */ 53 | 54 | uint16_t SPI_Mode; /*!< Specifies the SPI operating mode. 55 | This parameter can be a value of @ref SPI_mode */ 56 | 57 | uint16_t SPI_DataSize; /*!< Specifies the SPI data size. 58 | This parameter can be a value of @ref SPI_data_size */ 59 | 60 | uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state. 61 | This parameter can be a value of @ref SPI_Clock_Polarity */ 62 | 63 | uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture. 64 | This parameter can be a value of @ref SPI_Clock_Phase */ 65 | 66 | uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by 67 | hardware (NSS pin) or by software using the SSI bit. 68 | This parameter can be a value of @ref SPI_Slave_Select_management */ 69 | 70 | uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 71 | used to configure the transmit and receive SCK clock. 72 | This parameter can be a value of @ref SPI_BaudRate_Prescaler. 73 | @note The communication clock is derived from the master 74 | clock. The slave clock does not need to be set. */ 75 | 76 | uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 77 | This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 78 | 79 | uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */ 80 | }SPI_InitTypeDef; 81 | 82 | /** 83 | * @brief I2S Init structure definition 84 | */ 85 | 86 | typedef struct 87 | { 88 | 89 | uint16_t I2S_Mode; /*!< Specifies the I2S operating mode. 90 | This parameter can be a value of @ref I2S_Mode */ 91 | 92 | uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication. 93 | This parameter can be a value of @ref I2S_Standard */ 94 | 95 | uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication. 96 | This parameter can be a value of @ref I2S_Data_Format */ 97 | 98 | uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 99 | This parameter can be a value of @ref I2S_MCLK_Output */ 100 | 101 | uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 102 | This parameter can be a value of @ref I2S_Audio_Frequency */ 103 | 104 | uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock. 105 | This parameter can be a value of @ref I2S_Clock_Polarity */ 106 | }I2S_InitTypeDef; 107 | 108 | /** 109 | * @} 110 | */ 111 | 112 | /** @defgroup SPI_Exported_Constants 113 | * @{ 114 | */ 115 | 116 | #define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \ 117 | ((PERIPH) == SPI2) || \ 118 | ((PERIPH) == SPI3)) 119 | 120 | #define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \ 121 | ((PERIPH) == SPI3)) 122 | 123 | /** @defgroup SPI_data_direction 124 | * @{ 125 | */ 126 | 127 | #define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) 128 | #define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) 129 | #define SPI_Direction_1Line_Rx ((uint16_t)0x8000) 130 | #define SPI_Direction_1Line_Tx ((uint16_t)0xC000) 131 | #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \ 132 | ((MODE) == SPI_Direction_2Lines_RxOnly) || \ 133 | ((MODE) == SPI_Direction_1Line_Rx) || \ 134 | ((MODE) == SPI_Direction_1Line_Tx)) 135 | /** 136 | * @} 137 | */ 138 | 139 | /** @defgroup SPI_mode 140 | * @{ 141 | */ 142 | 143 | #define SPI_Mode_Master ((uint16_t)0x0104) 144 | #define SPI_Mode_Slave ((uint16_t)0x0000) 145 | #define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \ 146 | ((MODE) == SPI_Mode_Slave)) 147 | /** 148 | * @} 149 | */ 150 | 151 | /** @defgroup SPI_data_size 152 | * @{ 153 | */ 154 | 155 | #define SPI_DataSize_16b ((uint16_t)0x0800) 156 | #define SPI_DataSize_8b ((uint16_t)0x0000) 157 | #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \ 158 | ((DATASIZE) == SPI_DataSize_8b)) 159 | /** 160 | * @} 161 | */ 162 | 163 | /** @defgroup SPI_Clock_Polarity 164 | * @{ 165 | */ 166 | 167 | #define SPI_CPOL_Low ((uint16_t)0x0000) 168 | #define SPI_CPOL_High ((uint16_t)0x0002) 169 | #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \ 170 | ((CPOL) == SPI_CPOL_High)) 171 | /** 172 | * @} 173 | */ 174 | 175 | /** @defgroup SPI_Clock_Phase 176 | * @{ 177 | */ 178 | 179 | #define SPI_CPHA_1Edge ((uint16_t)0x0000) 180 | #define SPI_CPHA_2Edge ((uint16_t)0x0001) 181 | #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \ 182 | ((CPHA) == SPI_CPHA_2Edge)) 183 | /** 184 | * @} 185 | */ 186 | 187 | /** @defgroup SPI_Slave_Select_management 188 | * @{ 189 | */ 190 | 191 | #define SPI_NSS_Soft ((uint16_t)0x0200) 192 | #define SPI_NSS_Hard ((uint16_t)0x0000) 193 | #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \ 194 | ((NSS) == SPI_NSS_Hard)) 195 | /** 196 | * @} 197 | */ 198 | 199 | /** @defgroup SPI_BaudRate_Prescaler 200 | * @{ 201 | */ 202 | 203 | #define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) 204 | #define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) 205 | #define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) 206 | #define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) 207 | #define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) 208 | #define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) 209 | #define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) 210 | #define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) 211 | #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \ 212 | ((PRESCALER) == SPI_BaudRatePrescaler_4) || \ 213 | ((PRESCALER) == SPI_BaudRatePrescaler_8) || \ 214 | ((PRESCALER) == SPI_BaudRatePrescaler_16) || \ 215 | ((PRESCALER) == SPI_BaudRatePrescaler_32) || \ 216 | ((PRESCALER) == SPI_BaudRatePrescaler_64) || \ 217 | ((PRESCALER) == SPI_BaudRatePrescaler_128) || \ 218 | ((PRESCALER) == SPI_BaudRatePrescaler_256)) 219 | /** 220 | * @} 221 | */ 222 | 223 | /** @defgroup SPI_MSB_LSB_transmission 224 | * @{ 225 | */ 226 | 227 | #define SPI_FirstBit_MSB ((uint16_t)0x0000) 228 | #define SPI_FirstBit_LSB ((uint16_t)0x0080) 229 | #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \ 230 | ((BIT) == SPI_FirstBit_LSB)) 231 | /** 232 | * @} 233 | */ 234 | 235 | /** @defgroup I2S_Mode 236 | * @{ 237 | */ 238 | 239 | #define I2S_Mode_SlaveTx ((uint16_t)0x0000) 240 | #define I2S_Mode_SlaveRx ((uint16_t)0x0100) 241 | #define I2S_Mode_MasterTx ((uint16_t)0x0200) 242 | #define I2S_Mode_MasterRx ((uint16_t)0x0300) 243 | #define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \ 244 | ((MODE) == I2S_Mode_SlaveRx) || \ 245 | ((MODE) == I2S_Mode_MasterTx) || \ 246 | ((MODE) == I2S_Mode_MasterRx) ) 247 | /** 248 | * @} 249 | */ 250 | 251 | /** @defgroup I2S_Standard 252 | * @{ 253 | */ 254 | 255 | #define I2S_Standard_Phillips ((uint16_t)0x0000) 256 | #define I2S_Standard_MSB ((uint16_t)0x0010) 257 | #define I2S_Standard_LSB ((uint16_t)0x0020) 258 | #define I2S_Standard_PCMShort ((uint16_t)0x0030) 259 | #define I2S_Standard_PCMLong ((uint16_t)0x00B0) 260 | #define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \ 261 | ((STANDARD) == I2S_Standard_MSB) || \ 262 | ((STANDARD) == I2S_Standard_LSB) || \ 263 | ((STANDARD) == I2S_Standard_PCMShort) || \ 264 | ((STANDARD) == I2S_Standard_PCMLong)) 265 | /** 266 | * @} 267 | */ 268 | 269 | /** @defgroup I2S_Data_Format 270 | * @{ 271 | */ 272 | 273 | #define I2S_DataFormat_16b ((uint16_t)0x0000) 274 | #define I2S_DataFormat_16bextended ((uint16_t)0x0001) 275 | #define I2S_DataFormat_24b ((uint16_t)0x0003) 276 | #define I2S_DataFormat_32b ((uint16_t)0x0005) 277 | #define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \ 278 | ((FORMAT) == I2S_DataFormat_16bextended) || \ 279 | ((FORMAT) == I2S_DataFormat_24b) || \ 280 | ((FORMAT) == I2S_DataFormat_32b)) 281 | /** 282 | * @} 283 | */ 284 | 285 | /** @defgroup I2S_MCLK_Output 286 | * @{ 287 | */ 288 | 289 | #define I2S_MCLKOutput_Enable ((uint16_t)0x0200) 290 | #define I2S_MCLKOutput_Disable ((uint16_t)0x0000) 291 | #define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \ 292 | ((OUTPUT) == I2S_MCLKOutput_Disable)) 293 | /** 294 | * @} 295 | */ 296 | 297 | /** @defgroup I2S_Audio_Frequency 298 | * @{ 299 | */ 300 | 301 | #define I2S_AudioFreq_192k ((uint32_t)192000) 302 | #define I2S_AudioFreq_96k ((uint32_t)96000) 303 | #define I2S_AudioFreq_48k ((uint32_t)48000) 304 | #define I2S_AudioFreq_44k ((uint32_t)44100) 305 | #define I2S_AudioFreq_32k ((uint32_t)32000) 306 | #define I2S_AudioFreq_22k ((uint32_t)22050) 307 | #define I2S_AudioFreq_16k ((uint32_t)16000) 308 | #define I2S_AudioFreq_11k ((uint32_t)11025) 309 | #define I2S_AudioFreq_8k ((uint32_t)8000) 310 | #define I2S_AudioFreq_Default ((uint32_t)2) 311 | 312 | #define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \ 313 | ((FREQ) <= I2S_AudioFreq_192k)) || \ 314 | ((FREQ) == I2S_AudioFreq_Default)) 315 | /** 316 | * @} 317 | */ 318 | 319 | /** @defgroup I2S_Clock_Polarity 320 | * @{ 321 | */ 322 | 323 | #define I2S_CPOL_Low ((uint16_t)0x0000) 324 | #define I2S_CPOL_High ((uint16_t)0x0008) 325 | #define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \ 326 | ((CPOL) == I2S_CPOL_High)) 327 | /** 328 | * @} 329 | */ 330 | 331 | /** @defgroup SPI_I2S_DMA_transfer_requests 332 | * @{ 333 | */ 334 | 335 | #define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) 336 | #define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) 337 | #define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00)) 338 | /** 339 | * @} 340 | */ 341 | 342 | /** @defgroup SPI_NSS_internal_software_mangement 343 | * @{ 344 | */ 345 | 346 | #define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) 347 | #define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) 348 | #define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \ 349 | ((INTERNAL) == SPI_NSSInternalSoft_Reset)) 350 | /** 351 | * @} 352 | */ 353 | 354 | /** @defgroup SPI_CRC_Transmit_Receive 355 | * @{ 356 | */ 357 | 358 | #define SPI_CRC_Tx ((uint8_t)0x00) 359 | #define SPI_CRC_Rx ((uint8_t)0x01) 360 | #define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx)) 361 | /** 362 | * @} 363 | */ 364 | 365 | /** @defgroup SPI_direction_transmit_receive 366 | * @{ 367 | */ 368 | 369 | #define SPI_Direction_Rx ((uint16_t)0xBFFF) 370 | #define SPI_Direction_Tx ((uint16_t)0x4000) 371 | #define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \ 372 | ((DIRECTION) == SPI_Direction_Tx)) 373 | /** 374 | * @} 375 | */ 376 | 377 | /** @defgroup SPI_I2S_interrupts_definition 378 | * @{ 379 | */ 380 | 381 | #define SPI_I2S_IT_TXE ((uint8_t)0x71) 382 | #define SPI_I2S_IT_RXNE ((uint8_t)0x60) 383 | #define SPI_I2S_IT_ERR ((uint8_t)0x50) 384 | #define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \ 385 | ((IT) == SPI_I2S_IT_RXNE) || \ 386 | ((IT) == SPI_I2S_IT_ERR)) 387 | #define SPI_I2S_IT_OVR ((uint8_t)0x56) 388 | #define SPI_IT_MODF ((uint8_t)0x55) 389 | #define SPI_IT_CRCERR ((uint8_t)0x54) 390 | #define I2S_IT_UDR ((uint8_t)0x53) 391 | #define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR)) 392 | #define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \ 393 | ((IT) == I2S_IT_UDR) || ((IT) == SPI_IT_CRCERR) || \ 394 | ((IT) == SPI_IT_MODF) || ((IT) == SPI_I2S_IT_OVR)) 395 | /** 396 | * @} 397 | */ 398 | 399 | /** @defgroup SPI_I2S_flags_definition 400 | * @{ 401 | */ 402 | 403 | #define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) 404 | #define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) 405 | #define I2S_FLAG_CHSIDE ((uint16_t)0x0004) 406 | #define I2S_FLAG_UDR ((uint16_t)0x0008) 407 | #define SPI_FLAG_CRCERR ((uint16_t)0x0010) 408 | #define SPI_FLAG_MODF ((uint16_t)0x0020) 409 | #define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) 410 | #define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) 411 | #define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR)) 412 | #define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \ 413 | ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \ 414 | ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \ 415 | ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)) 416 | /** 417 | * @} 418 | */ 419 | 420 | /** @defgroup SPI_CRC_polynomial 421 | * @{ 422 | */ 423 | 424 | #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1) 425 | /** 426 | * @} 427 | */ 428 | 429 | /** 430 | * @} 431 | */ 432 | 433 | /** @defgroup SPI_Exported_Macros 434 | * @{ 435 | */ 436 | 437 | /** 438 | * @} 439 | */ 440 | 441 | /** @defgroup SPI_Exported_Functions 442 | * @{ 443 | */ 444 | 445 | void SPI_I2S_DeInit(SPI_TypeDef* SPIx); 446 | void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); 447 | void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); 448 | void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); 449 | void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); 450 | void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 451 | void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); 452 | void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); 453 | void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); 454 | void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); 455 | uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); 456 | void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); 457 | void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); 458 | void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); 459 | void SPI_TransmitCRC(SPI_TypeDef* SPIx); 460 | void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); 461 | uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); 462 | uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); 463 | void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); 464 | FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 465 | void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); 466 | ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 467 | void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); 468 | 469 | #ifdef __cplusplus 470 | } 471 | #endif 472 | 473 | #endif /*__STM32F10x_SPI_H */ 474 | /** 475 | * @} 476 | */ 477 | 478 | /** 479 | * @} 480 | */ 481 | 482 | /** 483 | * @} 484 | */ 485 | 486 | /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/ 487 | --------------------------------------------------------------------------------