├── gowin_flash_sim ├── .gitignore ├── README.md ├── Makefile ├── sim_flash.py └── prim_sim.v.patch ├── poetry.toml ├── .gitignore ├── src ├── settings.py ├── firmware │ ├── main.h │ ├── isr.c │ ├── main.c │ ├── linker.ld │ └── Makefile ├── platform_sim.py ├── soc_base.py ├── main.py ├── platform_xilinx.py └── soc_pcie.py ├── scripts ├── s3_jlink_swd.cfg ├── ps7_boot.tcl ├── ps7_flash.tcl └── psu_boot.tcl ├── digilent_zedboard ├── boot_sd.cmd ├── boot_qspi.cmd ├── boot.bif └── README.md ├── pyproject.toml ├── .github └── workflows │ └── main.yml ├── LICENSE ├── Makefile.quickfeather ├── .gitmodules ├── Makefile.kv260 ├── Makefile.zcu216 ├── Makefile.zedboard ├── README.md └── poetry.lock /gowin_flash_sim/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | -------------------------------------------------------------------------------- /poetry.toml: -------------------------------------------------------------------------------- 1 | [virtualenvs] 2 | in-project = true 3 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | /build/ 2 | /zynq_fsbl.elf 3 | /libeos.zip 4 | -------------------------------------------------------------------------------- /src/settings.py: -------------------------------------------------------------------------------- 1 | device_model = "xc7a200tfbg484" 2 | speed_grade = -1 3 | -------------------------------------------------------------------------------- /src/firmware/main.h: -------------------------------------------------------------------------------- 1 | #ifndef FIRMWARE_MAIN_H 2 | #define FIRMWARE_MAIN_H 3 | 4 | #endif //FIRMWARE_MAIN_H 5 | -------------------------------------------------------------------------------- /scripts/s3_jlink_swd.cfg: -------------------------------------------------------------------------------- 1 | adapter driver jlink 2 | adapter speed 1000 3 | transport select swd 4 | source [find target/eos_s3.cfg] 5 | reset_config srst_only 6 | -------------------------------------------------------------------------------- /digilent_zedboard/boot_sd.cmd: -------------------------------------------------------------------------------- 1 | dcache off 2 | 3 | fatload mmc 0 0x100000 fpga.bit 4 | fpga loadb 0 0x100000 0x100000 5 | 6 | fatload mmc 0 0x100000 bios.bin 7 | go 0x100000 8 | -------------------------------------------------------------------------------- /digilent_zedboard/boot_qspi.cmd: -------------------------------------------------------------------------------- 1 | dcache off 2 | sf probe 3 | sf read 0x100000 0x300000 0x100000 4 | fpga load 0 0x100000 0x1000000 5 | sf read 0x100000 0x400000 0x100000 6 | go 0x100000 7 | -------------------------------------------------------------------------------- /scripts/ps7_boot.tcl: -------------------------------------------------------------------------------- 1 | connect 2 | targets -set -filter {name =~ "ARM*#0"} 3 | rst 4 | stop 5 | source [lindex $argv 0] 6 | ps7_init 7 | ps7_post_config 8 | 9 | dow [lindex $argv 1] 10 | fpga [lindex $argv 2] 11 | con 12 | -------------------------------------------------------------------------------- /scripts/ps7_flash.tcl: -------------------------------------------------------------------------------- 1 | source [lindex $argv 0] 2 | source lib/zynq_flash/flash_writer.tcl 3 | set flash_writer_elf lib/zynq_flash/zed_bin/flash_writer.elf 4 | connect 5 | targets -set -filter {name =~ "ARM*#0"} 6 | flash_image [lindex $argv 1] -------------------------------------------------------------------------------- /src/firmware/isr.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | 5 | void isr(void); 6 | void isr(void) 7 | { 8 | unsigned int irqs; 9 | 10 | irqs = irq_pending() & irq_getmask(); 11 | 12 | if(irqs & (1 << UART_INTERRUPT)) 13 | uart_isr(); 14 | } 15 | -------------------------------------------------------------------------------- /gowin_flash_sim/README.md: -------------------------------------------------------------------------------- 1 | ### LiteX / Verilator simulation of AHB Flash access by Gowin EMCU Arm core 2 | 3 | Uses `GW1N verilog functional simulation library` included in Gowin IDE, patched for compatibility with Verilator. 4 | 5 | Run `GOWIN_SDK=/path/to/gowin/ide make` to run a simulation, then `make gtkwave` to inspect the simulated waveforms. 6 | -------------------------------------------------------------------------------- /gowin_flash_sim/Makefile: -------------------------------------------------------------------------------- 1 | .DEFAULT_GOAL := sim 2 | .PHONY: sim gtkwave clean 3 | 4 | build: 5 | mkdir -p $@ 6 | 7 | build/prim_sim.v: build 8 | patch -o $@ $(GOWIN_SDK)/IDE/simlib/gw1n/prim_sim.v prim_sim.v.patch 9 | 10 | sim: build/prim_sim.v 11 | poetry run python sim_flash.py 12 | 13 | gtkwave: 14 | gtkwave build/sim/gateware/sim.vcd & 15 | 16 | clean: 17 | rm -rf build 18 | -------------------------------------------------------------------------------- /digilent_zedboard/boot.bif: -------------------------------------------------------------------------------- 1 | img: { 2 | [bootloader] build/digilent_zedboard/software/u-boot/spl/u-boot-spl.bin 3 | [offset=0x100000] build/digilent_zedboard/software/u-boot/u-boot.img 4 | [offset=0x300000] build/digilent_zedboard/gateware/digilent_zedboard.bit 5 | [offset=0x400000] build/digilent_zedboard/software/bios/bios.bin 6 | [offset=0xfc0000] build/digilent_zedboard/boot_qspi.scr 7 | } 8 | -------------------------------------------------------------------------------- /src/firmware/main.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | #include 4 | #include 5 | #include 6 | #include 7 | #include 8 | #include "main.h" 9 | 10 | 11 | int main(void) { 12 | int i = 0; 13 | 14 | irq_setmask(0); 15 | irq_setie(1); 16 | uart_init(); 17 | 18 | while (1) { 19 | puts("firmware running"); 20 | gpio_led_out_write(i ++); 21 | busy_wait_us(1000 * 1000); 22 | } 23 | 24 | return 0; 25 | } 26 | -------------------------------------------------------------------------------- /scripts/psu_boot.tcl: -------------------------------------------------------------------------------- 1 | connect 2 | 3 | targets -set -nocase -filter {name =~ "PSU"} 4 | stop 5 | mwr 0xffca0010 0x0 6 | mwr 0xff5e0200 0x0100 7 | rst -system 8 | 9 | targets -set -nocase -filter {name =~ "PSU"} 10 | mwr 0xFFCA0038 0x1FF 11 | 12 | target -set -filter {name =~ "MicroBlaze PMU"} 13 | dow [lindex $argv 0] 14 | con 15 | 16 | source [lindex $argv 1] 17 | targets -set -nocase -filter {name =~ "PSU"} 18 | psu_init 19 | after 500 20 | psu_post_config 21 | after 500 22 | psu_ps_pl_reset_config 23 | after 500 24 | psu_ps_pl_isolation_removal 25 | after 500 26 | mwr 0xffff0000 0x14000000 27 | mwr 0xFD1A0104 0x380E 28 | 29 | targets -set -filter {name =~ "Cortex-A53 #0"} 30 | dow [lindex $argv 2] 31 | fpga [lindex $argv 3] 32 | con 33 | -------------------------------------------------------------------------------- /pyproject.toml: -------------------------------------------------------------------------------- 1 | [tool.poetry] 2 | name = "litex-template" 3 | version = "0.1.0" 4 | description = "" 5 | authors = ["Ilia Sergachev "] 6 | 7 | [tool.poetry.dependencies] 8 | python = "^3.9" 9 | meson = "*" 10 | pythondata-cpu-vexriscv = "*" 11 | pythondata-misc-tapcfg = "*" 12 | pythondata-software-picolibc = "*" 13 | litex = {path = "lib/litex", develop = true} 14 | litespi = {path = "lib/litespi", develop = true} 15 | litehyperbus = {path = "lib/litehyperbus", develop = true} 16 | litepcie = {path = "lib/litepcie", develop = true} 17 | litex-boards = {path = "lib/litex-boards", develop = true} 18 | simplejson = "*" 19 | lxml = "*" 20 | tinyfpgab = "*" 21 | 22 | [build-system] 23 | requires = ["poetry>=1.1.5"] 24 | build-backend = "poetry.masonry.api" 25 | -------------------------------------------------------------------------------- /.github/workflows/main.yml: -------------------------------------------------------------------------------- 1 | name: CI 2 | 3 | on: 4 | push: 5 | branches: [ main ] 6 | pull_request: 7 | branches: [ main ] 8 | workflow_dispatch: 9 | 10 | jobs: 11 | build: 12 | runs-on: self-hosted 13 | steps: 14 | - uses: actions/checkout@v2 15 | with: 16 | submodules: 'recursive' 17 | - name: Build LiteX BIOS for QuickFeather 18 | run: make -f Makefile.quickfeather 19 | - name: Build LiteX BIOS for Tang Nano 4K 20 | run: poetry run python lib/litex-boards/litex_boards/targets/sipeed_tang_nano_4k.py --cpu-type=gowin_emcu 21 | - name: Build LiteX BIOS for Zedboard 22 | run: make -f Makefile.zedboard build/digilent_zedboard/software/bios/bios.bin 23 | - name: Build LiteX BIOS for KV260 24 | run: make -f Makefile.kv260 25 | - name: Build LiteX BIOS for ZCU216 26 | run: make -f Makefile.zcu216 27 | -------------------------------------------------------------------------------- /src/platform_sim.py: -------------------------------------------------------------------------------- 1 | from litex.build.sim import SimPlatform 2 | from litex.build.generic_platform import Pins, Subsignal 3 | 4 | 5 | class SimPins(Pins): 6 | def __init__(self, n=1): 7 | Pins.__init__(self, "s "*n) 8 | 9 | 10 | _io = [ 11 | ("sys_clk", 0, SimPins(1)), 12 | ("sys_rst", 0, SimPins(1)), 13 | ("serial", 0, 14 | Subsignal("source_valid", SimPins()), 15 | Subsignal("source_ready", SimPins()), 16 | Subsignal("source_data", SimPins(8)), 17 | 18 | Subsignal("sink_valid", SimPins()), 19 | Subsignal("sink_ready", SimPins()), 20 | Subsignal("sink_data", SimPins(8)), 21 | ), 22 | ("user_led", 0, SimPins(1)), 23 | ] 24 | 25 | 26 | class Platform(SimPlatform): 27 | default_clk_name = "sys_clk" 28 | default_clk_period = 1000 # ~ 1MHz 29 | 30 | def __init__(self): 31 | SimPlatform.__init__(self, "SIM", _io) 32 | 33 | def do_finalize(self, fragment, *args, **kwargs): 34 | pass 35 | -------------------------------------------------------------------------------- /src/firmware/linker.ld: -------------------------------------------------------------------------------- 1 | INCLUDE generated/output_format.ld 2 | ENTRY(_start) 3 | 4 | __DYNAMIC = 0; 5 | 6 | INCLUDE generated/regions.ld 7 | 8 | SECTIONS 9 | { 10 | .text : 11 | { 12 | _ftext = .; 13 | *(.text .stub .text.* .gnu.linkonce.t.*) 14 | _etext = .; 15 | } > main_ram 16 | 17 | .rodata : 18 | { 19 | . = ALIGN(4); 20 | _frodata = .; 21 | *(.rodata .rodata.* .gnu.linkonce.r.*) 22 | *(.rodata1) 23 | _erodata = .; 24 | } > main_ram 25 | 26 | .data : 27 | { 28 | . = ALIGN(4); 29 | _fdata = .; 30 | *(.data .data.* .gnu.linkonce.d.*) 31 | *(.data1) 32 | _gp = ALIGN(16); 33 | *(.sdata .sdata.* .gnu.linkonce.s.*) 34 | _edata = .; 35 | } > main_ram 36 | 37 | .bss : 38 | { 39 | . = ALIGN(4); 40 | _fbss = .; 41 | *(.dynsbss) 42 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 43 | *(.scommon) 44 | *(.dynbss) 45 | *(.bss .bss.* .gnu.linkonce.b.*) 46 | *(COMMON) 47 | . = ALIGN(4); 48 | _ebss = .; 49 | _end = .; 50 | } > sram 51 | } 52 | 53 | PROVIDE(_fstack = ORIGIN(sram) + LENGTH(sram) - 4); 54 | PROVIDE(_fdata_rom = LOADADDR(.data)); 55 | PROVIDE(_edata_rom = LOADADDR(.data) + SIZEOF(.data)); 56 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2019 Ilia Sergachev 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /src/firmware/Makefile: -------------------------------------------------------------------------------- 1 | include ../include/generated/variables.mak 2 | include $(SOC_DIRECTORY)/software/common.mak 3 | 4 | TARGET = firmware 5 | OBJECTS = isr.o main.o 6 | CFLAGS += -Wall -Wextra -Wno-strict-prototypes 7 | 8 | all: $(TARGET).bin 9 | 10 | # pull in dependency info for *existing* .o files 11 | -include $(OBJECTS:.o=.d) 12 | 13 | $(TARGET).elf: $(OBJECTS) crt0.o 14 | $(CC) $(LDFLAGS) \ 15 | -T $(FIRMWARE_DIRECTORY)/linker.ld \ 16 | -N -o $@ \ 17 | crt0.o \ 18 | $(OBJECTS) \ 19 | -Wl,--whole-archive \ 20 | -Wl,--gc-sections \ 21 | -Wl,-Map,$@.map \ 22 | -L ../libbase -L ../libc -lbase -lc 23 | chmod -x $@ 24 | 25 | %.bin: %.elf 26 | $(OBJCOPY) -O binary $< $@ 27 | chmod -x $@ 28 | ifeq ($(CPUENDIANNESS),little) 29 | $(PYTHON) -m litex.soc.software.mkmscimg $@ -o $(TARGET).fbi --little -f 30 | else 31 | $(PYTHON) -m litex.soc.software.mkmscimg $@ -o $(TARGET).fbi -f 32 | endif 33 | 34 | VPATH = $(FIRMWARE_DIRECTORY):$(CPU_DIRECTORY) 35 | 36 | %.o: $(FIRMWARE_DIRECTORY)/%.c 37 | $(compile) 38 | 39 | %.o: %.S 40 | $(assemble) 41 | 42 | clean: 43 | $(RM) $(OBJECTS) $(OBJECTS:.o=.d) $(TARGET).elf $(TARGET).bin $(TARGET).lst .*~ *~ 44 | 45 | .PHONY: all clean 46 | -------------------------------------------------------------------------------- /src/soc_base.py: -------------------------------------------------------------------------------- 1 | from migen.genlib.io import CRG 2 | from litex.soc.integration.soc_core import SoCCore 3 | from litex.soc.cores import gpio, uart 4 | 5 | 6 | class BaseSoC(SoCCore): 7 | csr_map = { 8 | "gpio_led": 14, 9 | } 10 | csr_map.update(SoCCore.csr_map) 11 | 12 | def __init__(self, platform, cpu, sim: bool, **kwargs): 13 | sys_clk_freq = int(1e9 / platform.default_clk_period) 14 | kwargs['with_uart'] = not sim 15 | kwargs['cpu_type'] = cpu.name 16 | SoCCore.__init__(self, platform, 17 | clk_freq=sys_clk_freq, 18 | **kwargs) 19 | self.submodules.crg = CRG(platform.request(platform.default_clk_name)) 20 | self.submodules.gpio_led = gpio.GPIOOut(platform.request("user_led")) 21 | self.add_constant("ROM_BOOT_ADDRESS", self.mem_map['main_ram']) 22 | 23 | if sim: 24 | self.submodules.uart_phy = uart.RS232PHYModel(platform.request("serial")) 25 | self.submodules.uart = uart.UART(self.uart_phy, 26 | tx_fifo_depth=kwargs["uart_fifo_depth"], 27 | rx_fifo_depth=kwargs["uart_fifo_depth"]) 28 | self.add_csr("uart") 29 | self.add_interrupt("uart") 30 | -------------------------------------------------------------------------------- /Makefile.quickfeather: -------------------------------------------------------------------------------- 1 | litex_platform = quicklogic_quickfeather 2 | 3 | export QORC_SDK = $(realpath ./lib/qorc-sdk) 4 | 5 | soc_dir = build/$(litex_platform) 6 | soc = poetry run python lib/litex-boards/litex_boards/targets/$(litex_platform).py 7 | bitstream_bin = $(soc_dir)/gateware/$(litex_platform).bin 8 | firmware_bin = $(soc_dir)/software/bios/bios.bin 9 | firmware_elf = $(soc_dir)/software/bios/bios.elf 10 | 11 | .DEFAULT_GOAL := $(firmware_bin) 12 | .PHONY: prepare clean gateware flash 13 | 14 | .venv: 15 | poetry install 16 | 17 | clean: 18 | rm -rf build 19 | 20 | prepare: 21 | poetry install 22 | # note: this is only to download/install tools, we don't need these environment modifications 23 | cd lib/qorc-sdk && bash -c "source envsetup.sh" 24 | 25 | $(firmware_bin): .venv 26 | $(soc) 27 | 28 | $(firmware_elf): $(firmware_bin) 29 | 30 | $(bitstream_bin): .venv 31 | PATH=$(QORC_SDK)/fpga_toolchain_install/v1.3.1/quicklogic-arch-defs/bin:$(QORC_SDK)/fpga_toolchain_install/v1.3.1/conda/bin:$(PATH) $(soc) --build 32 | 33 | gateware: $(bitstream_bin) 34 | 35 | firmware: $(firmware_bin) 36 | 37 | flash: | $(bitstream_bin) $(firmware_bin) 38 | poetry run python $(QORC_SDK)/TinyFPGA-Programmer-Application/tinyfpga-programmer-gui.py \ 39 | --mode fpga-m4 --m4app $(firmware_bin) --appfpga $(bitstream_bin) 40 | 41 | openocd: 42 | openocd -f scripts/s3_jlink_swd.cfg 43 | 44 | gdb: $(firmware_elf) 45 | arm-none-eabi-gdb -ex 'target extended-remote :3333' $^ 46 | -------------------------------------------------------------------------------- /.gitmodules: -------------------------------------------------------------------------------- 1 | [submodule "lib/litex"] 2 | path = lib/litex 3 | url = https://github.com/enjoy-digital/litex 4 | [submodule "lib/litex-boards"] 5 | path = lib/litex-boards 6 | url = https://github.com/litex-hub/litex-boards.git 7 | [submodule "lib/litepcie"] 8 | path = lib/litepcie 9 | url = https://github.com/enjoy-digital/litepcie 10 | [submodule "lib/liteiclink"] 11 | path = lib/liteiclink 12 | url = https://github.com/enjoy-digital/liteiclink 13 | [submodule "lib/litespi"] 14 | path = lib/litespi 15 | url = https://github.com/litex-hub/litespi.git 16 | [submodule "lib/litehyperbus"] 17 | path = lib/litehyperbus 18 | url = https://github.com/litex-hub/litehyperbus.git 19 | [submodule "lib/embeddedsw"] 20 | path = lib/embeddedsw 21 | url = https://github.com/Xilinx/embeddedsw.git 22 | [submodule "lib/qorc-sdk"] 23 | path = lib/qorc-sdk 24 | url = https://github.com/QuickLogic-Corp/qorc-sdk.git 25 | shallow = true 26 | [submodule "lib/u-boot"] 27 | path = lib/u-boot 28 | url = https://github.com/u-boot/u-boot 29 | [submodule "lib/armbin2elf"] 30 | path = lib/armbin2elf 31 | url = https://github.com/majbthrd/armbin2elf 32 | [submodule "lib/zynq-mkbootimage"] 33 | path = lib/zynq-mkbootimage 34 | url = https://github.com/antmicro/zynq-mkbootimage.git 35 | [submodule "lib/zynq_flash"] 36 | path = lib/zynq_flash 37 | url = https://github.com/raczben/zynq_flash.git 38 | [submodule "lib/zynqmp-pmufw-builder"] 39 | path = lib/zynqmp-pmufw-builder 40 | url = https://github.com/lucaceresoli/zynqmp-pmufw-builder.git 41 | -------------------------------------------------------------------------------- /Makefile.kv260: -------------------------------------------------------------------------------- 1 | litex_platform = xilinx_kv260 2 | uboot_device_tree = zynqmp-smk-k26-revA 3 | uboot_defconfig = xilinx_zynqmp_virt_defconfig 4 | 5 | vivado = vivado -nojournal -nolog -mode batch 6 | soc_dir = build/$(litex_platform) 7 | uboot_build_dir = $(soc_dir)/software/u-boot 8 | uboot_src_dir = lib/u-boot 9 | soc = poetry run python lib/litex-boards/litex_boards/targets/$(litex_platform).py 10 | bitstream_file = $(soc_dir)/gateware/$(litex_platform).bit 11 | firmware_elf = $(soc_dir)/software/bios/bios.elf 12 | pmu_fw_elf = lib/zynqmp-pmufw-builder/pmufw.elf 13 | 14 | .DEFAULT_GOAL := all 15 | .PHONY: all clean $(firmware_elf) 16 | 17 | all: $(firmware_elf) 18 | 19 | .venv: 20 | poetry install 21 | 22 | clean: 23 | rm -rf $(soc_dir) 24 | 25 | $(firmware_elf): .venv 26 | $(soc) 27 | 28 | $(bitstream_file): .venv 29 | $(soc) --no-compile-software --build && \ 30 | grep -i "All user specified timing constraints are met" $(soc_dir)/gateware/vivado.log 31 | test -f $@ 32 | 33 | $(uboot_build_dir)/.config: 34 | make -C $(uboot_src_dir) O=${CURDIR}/$(uboot_build_dir) ARCH=arm DEVICE_TREE=$(uboot_device_tree) CROSS_COMPILE=aarch64-none-linux-gnu- $(uboot_defconfig) 35 | 36 | $(uboot_build_dir)/u-boot.img: $(uboot_build_dir)/.config 37 | make -C $(uboot_src_dir) O=${CURDIR}/$(uboot_build_dir) ARCH=arm DEVICE_TREE=$(uboot_device_tree) CROSS_COMPILE=aarch64-none-linux-gnu- -j 38 | 39 | gateware: $(bitstream_file) 40 | 41 | $(pmu_fw_elf): 42 | cd $(@D) && \ 43 | ./build.sh toolchain && \ 44 | ./build.sh pmufw-build 45 | 46 | load: $(pmu_fw_elf) $(firmware_elf) $(bitstream_file) 47 | xsct scripts/psu_boot.tcl \ 48 | $(pmu_fw_elf) \ 49 | build/$(litex_platform)/gateware/$(litex_platform).gen/sources_1/ip/ps/psu_init.tcl \ 50 | $(firmware_elf) \ 51 | $(bitstream_file) 52 | -------------------------------------------------------------------------------- /Makefile.zcu216: -------------------------------------------------------------------------------- 1 | litex_platform = xilinx_zcu216 2 | uboot_device_tree = zynqmp-zcu216-revA 3 | uboot_defconfig = xilinx_zynqmp_virt_defconfig 4 | 5 | vivado = vivado -nojournal -nolog -mode batch 6 | soc_dir = build/$(litex_platform) 7 | uboot_build_dir = $(soc_dir)/software/u-boot 8 | uboot_src_dir = lib/u-boot 9 | soc = poetry run python lib/litex-boards/litex_boards/targets/$(litex_platform).py 10 | bitstream_file = $(soc_dir)/gateware/$(litex_platform).bit 11 | firmware_elf = $(soc_dir)/software/bios/bios.elf 12 | pmu_fw_elf = lib/zynqmp-pmufw-builder/pmufw.elf 13 | 14 | .DEFAULT_GOAL := all 15 | .PHONY: all clean $(firmware_elf) 16 | 17 | all: $(firmware_elf) 18 | 19 | .venv: 20 | poetry install 21 | 22 | clean: 23 | rm -rf $(soc_dir) 24 | 25 | $(firmware_elf): .venv 26 | $(soc) 27 | 28 | $(bitstream_file): .venv 29 | $(soc) --no-compile-software --build && \ 30 | grep -i "All user specified timing constraints are met" $(soc_dir)/gateware/vivado.log 31 | test -f $@ 32 | 33 | $(uboot_build_dir)/.config: 34 | make -C $(uboot_src_dir) O=${CURDIR}/$(uboot_build_dir) ARCH=arm DEVICE_TREE=$(uboot_device_tree) CROSS_COMPILE=aarch64-none-linux-gnu- $(uboot_defconfig) 35 | 36 | $(uboot_build_dir)/u-boot.img: $(uboot_build_dir)/.config 37 | make -C $(uboot_src_dir) O=${CURDIR}/$(uboot_build_dir) ARCH=arm DEVICE_TREE=$(uboot_device_tree) CROSS_COMPILE=aarch64-none-linux-gnu- -j 38 | 39 | gateware: $(bitstream_file) 40 | 41 | $(pmu_fw_elf): 42 | cd $(@D) && \ 43 | ./build.sh toolchain && \ 44 | ./build.sh pmufw-build 45 | 46 | load: $(pmu_fw_elf) $(firmware_elf) $(bitstream_file) 47 | xsct scripts/psu_boot.tcl \ 48 | $(pmu_fw_elf) \ 49 | build/$(litex_platform)/gateware/$(litex_platform).gen/sources_1/ip/ps/psu_init.tcl \ 50 | $(firmware_elf) \ 51 | $(bitstream_file) 52 | -------------------------------------------------------------------------------- /digilent_zedboard/README.md: -------------------------------------------------------------------------------- 1 | ### A complete LiteX implementation workflow for Zynq-7000 2 | 3 | Features: 4 | - LiteX BIOS running on Cortex-A9 Arm core, talking to LiteX gateware over AXI/Wishbone 5 | - U-Boot with SPL enabling boot from QSPI flash or SD card 6 | 7 | Howto: 8 | - look at the [top-level readme](../README.md), provide the required tools 9 | - build all binaries: `make -f Makefile.zedboard` from the top level 10 | - choose one of the boot options below and configure your board accordingly 11 | - option 1 - boot from SD card: format 1st partition as FAT32, copy these files to its root: 12 | - lib/u-boot/spl/boot.bin 13 | - lib/u-boot/u-boot.img 14 | - build/digilent_zedboard/boot.scr 15 | - build/digilent_zedboard/gateware/digilent_zedboard.bit **as fpga.bit** 16 | - build/digilent_zedboard/software/bios/bios.bin 17 | - option 2 - boot from QSPI flash: flash build/digilent_zedboard/qspi.bin into board's memory one of these ways: 18 | - with `make -f Makefile.zedboard flash` via [zynq_flash](https://github.com/raczben/zynq_flash) (uses `xsct` from Vitis) 19 | - with `make -f Makefile.zedboard flash2` - uses `program_flash` from Vitis, needs FSBL binary, one can be taken [here](https://digilent.com/reference/_media/zedboard/zedboard_oob_design.zip) (boot_image/zynq_fsbl.elf) 20 | - with U-Boot `sf` command (to be described) [link](https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842223/U-boot#U-boot-ProgrammingQSPIFlash) 21 | - option 3 - boot from JTAG: `make -f Makefile.zedboard load` (uses `xsct` from Vitis) 22 | - access the booted system via USB-Serial terminal 23 | 24 | Notes: 25 | - there is nearly nothing specific to Zedboard in the current implementation, 26 | will work as is or with minimal changes on other Zynq boards 27 | - there are options for debugging over JTAG with either `xsct` or `openocd`+`gdb` (to be described) -------------------------------------------------------------------------------- /src/main.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | import os 3 | 4 | from litex.soc.integration.common import get_mem_data 5 | from litex.soc.integration.soc_core import soc_core_args, soc_core_argdict 6 | from litex.soc.integration.builder import builder_args, builder_argdict, Builder 7 | from litex.soc.cores.cpu.vexriscv.core import VexRiscv 8 | from litex.build.sim.config import SimConfig 9 | 10 | import platform_xilinx 11 | import platform_sim 12 | from soc_base import BaseSoC 13 | from soc_pcie import PCIeDMASoC 14 | 15 | 16 | def main(): 17 | soc_cls = BaseSoC 18 | cpu = VexRiscv 19 | 20 | parser = argparse.ArgumentParser(description="LiteX SoC") 21 | builder_args(parser) 22 | soc_core_args(parser) 23 | parser.add_argument("--build_gateware", action='store_true') 24 | parser.add_argument("--yosys", action="store_true") 25 | parser.add_argument("--sim", action="store_true") 26 | parser.add_argument("--run", action="store_true") 27 | args = parser.parse_args() 28 | builder_kwargs = builder_argdict(args) 29 | soc_kwargs = soc_core_argdict(args) 30 | platform = platform_sim.Platform() if args.sim else platform_xilinx.Platform() 31 | output_dir = builder_kwargs['output_dir'] = 'build' 32 | fw_file = os.path.join(output_dir, "software", "firmware", "firmware.bin") 33 | soc_kwargs['integrated_rom_size'] = 32 * 1024 34 | soc_kwargs["integrated_main_ram_size"] = 16 * 1024 35 | try: 36 | soc_kwargs['integrated_main_ram_init'] = get_mem_data(fw_file, cpu.endianness) 37 | except OSError: 38 | pass 39 | soc = soc_cls(platform, cpu=cpu, sim=args.sim, output_dir=output_dir, **soc_kwargs) 40 | builder = Builder(soc, **builder_kwargs) 41 | builder.add_software_package("firmware", src_dir=os.path.join(os.getcwd(), 'src', 'firmware')) 42 | if args.sim: 43 | sim_config = SimConfig(default_clk="sys_clk") 44 | sim_config.add_module("serial2console", "serial") 45 | builder.build(run=False, sim_config=sim_config, opt_level='O3') 46 | if args.run: 47 | builder.build(build=False, sim_config=sim_config) 48 | else: 49 | builder.build(run=args.build_gateware, synth_mode="yosys" if args.yosys else "vivado") 50 | 51 | 52 | if __name__ == "__main__": 53 | main() 54 | -------------------------------------------------------------------------------- /src/platform_xilinx.py: -------------------------------------------------------------------------------- 1 | from litex.build.generic_platform import * 2 | from litex.build.xilinx import XilinxPlatform, VivadoProgrammer 3 | 4 | from settings import device_model, speed_grade 5 | 6 | io_std = IOStandard("LVCMOS33") 7 | 8 | _io = [ 9 | ("user_led", 0, Pins("D1 B1"), io_std), 10 | 11 | ("clk100", 0, Pins("V13"), io_std), 12 | 13 | ("serial", 0, 14 | Subsignal("tx", Pins("AB7")), 15 | Subsignal("rx", Pins("AB8")), 16 | io_std, 17 | ), 18 | 19 | ("spiflash", 0, # clock needs to be accessed through STARTUPE2 20 | Subsignal("mosi", Pins("P22")), 21 | Subsignal("miso", Pins("R22")), 22 | Subsignal("vpp", Pins("P21")), 23 | Subsignal("hold", Pins("R21")), 24 | io_std, 25 | ), 26 | 27 | ("spi_cs_n", 0, Pins("T19"), io_std), 28 | 29 | ("pcie_x1", 0, 30 | Subsignal("rst_n", Pins("E1"), IOStandard("LVCMOS25")), 31 | Subsignal("clk_p", Pins("F6")), 32 | Subsignal("clk_n", Pins("E6")), 33 | Subsignal("rx_p", Pins("B10")), 34 | Subsignal("rx_n", Pins("A10")), 35 | Subsignal("tx_p", Pins("B6")), 36 | Subsignal("tx_n", Pins("A6")) 37 | ), 38 | ] 39 | 40 | _connectors = [] 41 | 42 | 43 | class Platform(XilinxPlatform): 44 | default_clk_name = "clk100" 45 | default_clk_period = 10.0 46 | 47 | def __init__(self): 48 | XilinxPlatform.__init__(self, "{}{}".format(device_model, speed_grade), 49 | _io, _connectors, toolchain="vivado") 50 | self.add_platform_command(""" 51 | set_property CFGBVS VCCO [current_design] 52 | set_property CONFIG_VOLTAGE 3.3 [current_design] 53 | """) 54 | self.toolchain.bitstream_commands = \ 55 | ["set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]", 56 | "set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]", 57 | "set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]",] 58 | self.toolchain.additional_commands = \ 59 | ["write_cfgmem -force -format mcs -interface SPIx4 -size 16 " 60 | "-loadbit \"up 0x0 {build_name}.bit\" -file {build_name}.mcs"] 61 | self.speed_grade = speed_grade 62 | 63 | def create_programmer(self): 64 | return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") 65 | 66 | def do_finalize(self, fragment, *args, **kwargs): 67 | XilinxPlatform.do_finalize(self, fragment, *args, **kwargs) 68 | self.add_period_constraint(self.lookup_request(self.default_clk_name, loose=True), self.default_clk_period) 69 | -------------------------------------------------------------------------------- /gowin_flash_sim/sim_flash.py: -------------------------------------------------------------------------------- 1 | import argparse 2 | from migen import * 3 | from migen.genlib.misc import WaitTimer 4 | from litex.soc.integration.builder import builder_args, builder_argdict, Builder 5 | from litex.build.sim.config import SimConfig 6 | from litex.soc.integration.soc_core import SoCMini 7 | from litex.soc.interconnect import ahb 8 | from litex.build.sim import SimPlatform 9 | from litex.build.generic_platform import Pins 10 | from litex.soc.cores.cpu.gowin_emcu.core import AHBFlash 11 | 12 | 13 | _io = [ 14 | ("sys_clk", 0, Pins(1)), 15 | ("sys_rst", 0, Pins(1)), 16 | ] 17 | 18 | 19 | class Platform(SimPlatform): 20 | default_clk_name = "sys_clk" 21 | default_clk_period = 1000 # ~ 1MHz 22 | 23 | def __init__(self): 24 | SimPlatform.__init__(self, "SIM", _io) 25 | 26 | def do_finalize(self, fragment, *args, **kwargs): 27 | pass 28 | 29 | 30 | class SimSoC(SoCMini): 31 | def __init__(self, platform, sys_clk_freq): 32 | super().__init__(platform, sys_clk_freq) 33 | self.comb += platform.trace.eq(1) 34 | 35 | bus = ahb.Interface() 36 | self.submodules += AHBFlash(bus) 37 | 38 | platform.add_sources('build', "prim_sim.v") 39 | 40 | wt = self.submodules.wt = WaitTimer(8) 41 | 42 | loop_counter = Signal(10) 43 | self.sync += If(loop_counter == 100, Finish()) 44 | 45 | fsm = self.submodules.fsm = FSM() 46 | fsm.act('INIT', 47 | NextValue(bus.sel, 1), 48 | NextValue(bus.trans, ahb.TransferType.NONSEQUENTIAL), 49 | NextValue(bus.addr, 0b1111111100001111001101), 50 | NextValue(loop_counter, loop_counter + 1), 51 | NextState('WAIT0') 52 | ) 53 | fsm.act('WAIT0', NextState('WAIT')) 54 | fsm.act('WAIT', 55 | NextValue(bus.trans, ahb.TransferType.IDLE), 56 | If(bus.readyout, 57 | NextState('DONE'))) 58 | fsm.act('DONE', 59 | wt.wait.eq(1), 60 | If(wt.done, NextState('INIT'))) 61 | 62 | 63 | def main(): 64 | parser = argparse.ArgumentParser() 65 | builder_args(parser) 66 | args = parser.parse_args() 67 | builder_kwargs = builder_argdict(args) 68 | platform = Platform() 69 | soc = SimSoC(platform, 1e9 / platform.default_clk_period) 70 | builder = Builder(soc, **builder_kwargs) 71 | sim_config = SimConfig(default_clk=platform.default_clk_name) 72 | builder.build(sim_config=sim_config, opt_level='O3', trace=True, trace_fst=False) 73 | 74 | 75 | if __name__ == "__main__": 76 | main() 77 | -------------------------------------------------------------------------------- /Makefile.zedboard: -------------------------------------------------------------------------------- 1 | litex_platform = digilent_zedboard 2 | uboot_device_tree = zynq-zed 3 | uboot_defconfig = xilinx_zynq_virt_defconfig 4 | 5 | vivado = vivado -nojournal -nolog -mode batch 6 | soc_dir = build/$(litex_platform) 7 | uboot_build_dir = $(soc_dir)/software/u-boot 8 | uboot_src_dir = lib/u-boot 9 | soc = poetry run python lib/litex-boards/litex_boards/targets/$(litex_platform).py 10 | bitstream_file = $(soc_dir)/gateware/$(litex_platform).bit 11 | firmware_elf = $(soc_dir)/software/bios/bios.elf 12 | firmware_bin = $(soc_dir)/software/bios/bios.bin 13 | 14 | .DEFAULT_GOAL := all 15 | .PHONY: all clean $(firmware_elf) 16 | 17 | all: $(soc_dir)/qspi.bin build/$(litex_platform)/boot.scr 18 | 19 | .venv: 20 | poetry install 21 | 22 | clean: 23 | rm -rf $(soc_dir) 24 | 25 | $(firmware_elf): .venv 26 | $(soc) 27 | 28 | $(firmware_bin): $(firmware_elf) 29 | 30 | $(bitstream_file): .venv 31 | $(soc) --build && \ 32 | grep -i "All user specified timing constraints are met" $(soc_dir)/gateware/vivado.log 33 | test -f $@ 34 | 35 | $(uboot_build_dir)/.config: 36 | make -C $(uboot_src_dir) O=${CURDIR}/$(uboot_build_dir) ARCH=arm DEVICE_TREE=$(uboot_device_tree) CROSS_COMPILE=arm-none-linux-gnueabihf- $(uboot_defconfig) 37 | 38 | $(uboot_build_dir)/u-boot.img: $(uboot_build_dir)/.config 39 | make -C $(uboot_src_dir) O=${CURDIR}/$(uboot_build_dir) ARCH=arm DEVICE_TREE=$(uboot_device_tree) CROSS_COMPILE=arm-none-linux-gnueabihf- -j 40 | 41 | $(uboot_build_dir)/spl/u-boot-spl.bin: $(uboot_build_dir)/u-boot.img 42 | 43 | build/$(litex_platform)/boot_qspi.scr: $(litex_platform)/boot_qspi.cmd 44 | $(uboot_build_dir)/tools/mkimage -C none -A arm -T script -d $< $@ 45 | 46 | build/$(litex_platform)/boot.scr: $(litex_platform)/boot_sd.cmd 47 | $(uboot_build_dir)/tools/mkimage -C none -A arm -T script -d $< $@ 48 | 49 | lib/zynq-mkbootimage/mkbootimage: 50 | cd $(@D) && make 51 | 52 | $(soc_dir)/qspi.bin: $(litex_platform)/boot.bif $(bitstream_file) $(uboot_build_dir)/u-boot.img build/$(litex_platform)/boot_qspi.scr build/digilent_zedboard/software/bios/bios.bin $(uboot_build_dir)/spl/u-boot-spl.bin lib/zynq-mkbootimage/mkbootimage 53 | ./lib/zynq-mkbootimage/mkbootimage $< $@ 54 | 55 | gateware: $(bitstream_file) 56 | 57 | load: $(firmware_elf) $(bitstream_file) 58 | xsct scripts/ps7_boot.tcl \ 59 | build/$(litex_platform)/gateware/$(litex_platform).gen/sources_1/ip/Zynq/ps7_init.tcl \ 60 | $(firmware_elf) \ 61 | $(bitstream_file) 62 | 63 | openocd: 64 | openocd -f board/digilent_zedboard.cfg 65 | 66 | gdb: $(firmware_elf) 67 | arm-none-eabi-gdb -ex 'target extended-remote :3333' $^ 68 | 69 | flash: $(soc_dir)/qspi.bin 70 | xsct scripts/ps7_flash.tcl \ 71 | build/$(litex_platform)/gateware/$(litex_platform).gen/sources_1/ip/Zynq/ps7_init.tcl \ 72 | $< 73 | 74 | flash2: $(soc_dir)/qspi.bin 75 | program_flash -f $< -flash_type qspi-x4-single -fsbl ./zynq_fsbl.elf 76 | -------------------------------------------------------------------------------- /gowin_flash_sim/prim_sim.v.patch: -------------------------------------------------------------------------------- 1 | 18a19,25 2 | > module GSR (GSRI); 3 | > input GSRI; 4 | > wire GSRO; 5 | > assign GSRO = GSRI; 6 | > endmodule //GSR (global set/reset control) 7 | > 8 | > 9 | 23,37c30 10 | < table 11 | < // I0 I1 S O 12 | < 0 ? 0 : 0 ; 13 | < 1 ? 0 : 1 ; 14 | < x ? 0 : x ; 15 | < ? 0 1 : 0 ; 16 | < ? 1 1 : 1 ; 17 | < ? x 1 : x ; 18 | < 0 0 x : 0 ; 19 | < 0 1 x : x ; 20 | < 1 0 x : x ; 21 | < 1 1 x : 1 ; 22 | < ? x x : x ; 23 | < x ? x : x ; 24 | < endtable 25 | --- 26 | > assign O = S ? I1 : I0; 27 | 400,401d392 28 | < else 29 | < deassign Q_reg; 30 | 428,429d418 31 | < else 32 | < deassign Q_reg; 33 | 456,457d444 34 | < else 35 | < deassign Q_reg; 36 | 486,487d472 37 | < else 38 | < deassign Q_reg; 39 | 516,517d500 40 | < else 41 | < deassign Q_reg; 42 | 546,547d528 43 | < else 44 | < deassign Q_reg; 45 | 578,579d558 46 | < else 47 | < deassign Q_reg; 48 | 597a577 49 | > GSR GSR(.GSRI(1)); 50 | 607,608d586 51 | < else 52 | < deassign Q_reg; 53 | 627a606 54 | > GSR GSR(.GSRI(1)); 55 | 637,638d615 56 | < else 57 | < deassign Q_reg; 58 | 666,667d642 59 | < else 60 | < deassign Q_reg; 61 | 694,695d668 62 | < else 63 | < deassign Q_reg; 64 | 722,723d694 65 | < else 66 | < deassign Q_reg; 67 | 750,751d720 68 | < else 69 | < deassign Q_reg; 70 | 780,781d748 71 | < else 72 | < deassign Q_reg; 73 | 810,811d776 74 | < else 75 | < deassign Q_reg; 76 | 840,841d804 77 | < else 78 | < deassign Q_reg; 79 | 872,873d834 80 | < else 81 | < deassign Q_reg; 82 | 901,902d861 83 | < else 84 | < deassign Q_reg; 85 | 931,932d889 86 | < else 87 | < deassign Q_reg; 88 | 950a908 89 | > GSR GSR(.GSRI(1)); 90 | 960,961d917 91 | < else 92 | < deassign Q_reg; 93 | 1349,1354d1304 94 | < else begin 95 | < deassign Q0_reg; 96 | < deassign Q1_reg; 97 | < deassign Q0_oreg; 98 | < deassign Q1_oreg; 99 | < end 100 | 1408,1413d1357 101 | < else begin 102 | < deassign Q0_reg; 103 | < deassign Q1_reg; 104 | < deassign Q0_oreg; 105 | < deassign Q1_oreg; 106 | < end 107 | 1471,1482d1414 108 | < else begin 109 | < deassign Dd1_2; 110 | < deassign Dd0_2; 111 | < deassign Dd1_1; 112 | < deassign Dd0_1; 113 | < deassign Dd1_0; 114 | < deassign Dd0_0; 115 | < deassign Ttx0; 116 | < deassign Ttx1; 117 | < deassign DT0; 118 | < deassign DT1; 119 | < end 120 | 1561,1572d1492 121 | < else begin 122 | < deassign Dd1_2; 123 | < deassign Dd0_2; 124 | < deassign Dd1_1; 125 | < deassign Dd0_1; 126 | < deassign Dd1_0; 127 | < deassign Dd0_0; 128 | < deassign Ttx0; 129 | < deassign Ttx1; 130 | < deassign DT0; 131 | < deassign DT1; 132 | < end 133 | 12228,12236d12147 134 | < module GSR (GSRI); 135 | < 136 | < input GSRI; 137 | < 138 | < wire GSRO; 139 | < 140 | < assign GSRO = GSRI; 141 | < 142 | < endmodule //GSR (global set/reset control) 143 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ### Template project for [LiteX](https://github.com/enjoy-digital/litex) - based SoCs 2 | 3 | Various pieces and examples that are not in LiteX yet and a reproducible environment to build and use them. 4 | 5 | #### Features: 6 | - `LiteX`-related repositories are registered as git submodules so that their 7 | exact versions are tracked 8 | - a `poetry` environment is used to keep your system and user Python environments clean, 9 | therefore you can have multiple such projects using different versions of `LiteX` 10 | repositories etc. 11 | - `LiteX`-related packages are installed in the development mode so that they can be worked on easily 12 | - simple and compact 13 | 14 | #### How to use: 15 | - clone this repository **recursively** 16 | - check the dependencies below 17 | - use one of the following: 18 | - A complete (gateware + Cortex-A9 firmware) workflow for Zynq-7000 [demonstrated on Digilent Zedboard](./digilent_zedboard) 19 | - Xilinx KV260 / ZCU216: build all required binaries and run LiteX gateware and BIOS on Zynq Ultrascale+ / Cortex-A53 via JTAG: 20 | `make -f Makefile.kv260 load` (or Makefile.zcu216); use USB-serial terminal on the board (more detailed description coming) 21 | - Quicklogic Quickfeather - build and flash complete (gateware + BIOS on Cortex-M4) boot images: 22 | `make -f Makefile.quickfeather flash`; serial terminal is on pins J3.2/J3.3 23 | - [Gowin AHB Flash access simulation](./gowin_flash_sim) with LiteX and Verilator 24 | - other SoC/software/simulation examples in src: new description coming soon 25 | 26 | #### External dependencies - have to be in `PATH`: 27 | - GNU Make, [Ninja](https://ninja-build.org/), Python 3.9+, [poetry](https://python-poetry.org/) (Ubuntu 20.04 and similar: `apt install make ninja-build python3.9 python3-pip; pip install poetry`) 28 | - For RISC-V cores: [RISC-V GNU toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain/releases) (riscv64-elf variant is usually fine) 29 | - For all 32-bit ARM cores: [GNU Arm Embedded Toolchain](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads) (arm-none-eabi) - 10.3-2021.10 tested 30 | - For 64-bit ZynqMP: [GNU Toolchain for the A-profile Architecture](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads) (aarch64-none-elf) - 10.3-2021.07 tested 31 | - For Xilinx Zynq(MP) to build U-Boot: [GNU Toolchain for the A-profile Architecture](https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-a/downloads) 32 | (aarch64-none-linux for ZynqMP, arm-none-linux-gnueabihf for Zynq7000) - 10.3-2021.07 tested 33 | - For ZynqMP PMU firmware build: makeinfo, help2man, libtool (`apt install texinfo help2man libtool-bin`) 34 | - For implementation on Xilinx devices: [Xilinx Vivado](https://www.xilinx.com/support/download.html) (2021.2 tested; for some Zynq-related tasks it is convenient to install it as Vitis configuration) 35 | - For implementation on Gowin devices: [Gowin EDA](https://www.gowinsemi.com/en/support/download_eda/) 36 | - optional: [OSS CAD Suite](https://github.com/YosysHQ/oss-cad-suite-build/releases) - yosys for synthesis, OpenOCD and openFPGALoader for programming, verilator and gtkwave for simulations 37 | - see [LiteX readme](https://github.com/enjoy-digital/litex/#quick-start-guide) for potential additional requirements like `json-c` and `libevent` 38 | -------------------------------------------------------------------------------- /src/soc_pcie.py: -------------------------------------------------------------------------------- 1 | import os 2 | from migen.genlib.misc import WaitTimer 3 | from litex.build.generic_platform import tools 4 | from litex.soc.interconnect.csr import * 5 | from litex.soc.integration.soc_core import SoCMini 6 | from litex.soc.cores.clock import S7MMCM 7 | from litex.soc.integration.export import get_csr_header, get_soc_header, get_mem_header 8 | from litepcie.phy.s7pciephy import S7PCIEPHY 9 | from litepcie.core import LitePCIeEndpoint, LitePCIeMSI 10 | from litepcie.frontend.dma import LitePCIeDMA 11 | from litepcie.frontend.wishbone import LitePCIeWishboneBridge 12 | 13 | 14 | class _CRG(Module, AutoCSR): 15 | def __init__(self, platform, sys_clk_freq): 16 | self.rst = CSR() 17 | self.clock_domains.cd_sys = ClockDomain() 18 | 19 | # Delay software reset by 10us to ensure write has been acked on PCIe. 20 | rst_delay = WaitTimer(int(10e-6*sys_clk_freq)) 21 | self.submodules += rst_delay 22 | self.sync += If(self.rst.re, rst_delay.wait.eq(1)) 23 | 24 | self.submodules.pll = pll = S7MMCM(speedgrade=platform.speed_grade) 25 | self.comb += pll.reset.eq(rst_delay.done) 26 | pll.register_clkin(platform.request(platform.default_clk_name), 1e9 / platform.default_clk_period) 27 | pll.create_clkout(self.cd_sys, sys_clk_freq) 28 | 29 | 30 | class PCIeDMASoC(SoCMini): 31 | def __init__(self, platform, **kwargs): 32 | sys_clk_freq = int(100e6) 33 | SoCMini.__init__(self, platform, sys_clk_freq, 34 | csr_data_width=32, 35 | ident="LitePCIe example design", 36 | ident_version=True, 37 | with_uart=True, 38 | uart_name="bridge") 39 | self.submodules.crg = _CRG(platform, sys_clk_freq) 40 | self.add_csr("crg") 41 | self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x1")) 42 | self.pcie_phy.add_timing_constraints(platform) 43 | # platform.add_false_path_constraints(self.crg.cd_sys.clk, self.pcie_phy.cd_pcie.clk) 44 | self.add_csr("pcie_phy") 45 | self.submodules.pcie_endpoint = LitePCIeEndpoint(self.pcie_phy) 46 | 47 | self.submodules.pcie_bridge = LitePCIeWishboneBridge(self.pcie_endpoint, 48 | base_address=self.mem_map["csr"]) 49 | self.add_wb_master(self.pcie_bridge.wishbone) 50 | 51 | self.submodules.pcie_dma0 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, 52 | with_loopback=True) 53 | self.add_csr("pcie_dma0") 54 | self.submodules.pcie_dma1 = LitePCIeDMA(self.pcie_phy, self.pcie_endpoint, 55 | with_loopback=True) 56 | self.add_csr("pcie_dma1") 57 | self.add_constant("DMA_CHANNELS", 2) 58 | 59 | self.submodules.pcie_msi = LitePCIeMSI() 60 | self.add_csr("pcie_msi") 61 | self.comb += self.pcie_msi.source.connect(self.pcie_phy.msi) 62 | self.interrupts = { 63 | "PCIE_DMA0_WRITER": self.pcie_dma0.writer.irq, 64 | "PCIE_DMA0_READER": self.pcie_dma0.reader.irq, 65 | "PCIE_DMA1_WRITER": self.pcie_dma1.writer.irq, 66 | "PCIE_DMA1_READER": self.pcie_dma1.reader.irq, 67 | } 68 | for i, (k, v) in enumerate(sorted(self.interrupts.items())): 69 | self.comb += self.pcie_msi.irqs[i].eq(v) 70 | self.add_constant(k + "_INTERRUPT", i) 71 | 72 | def generate_software_headers(self, output_dir): 73 | csr_header = get_csr_header(self.csr_regions, self.constants, with_access_functions=False) 74 | tools.write_to_file(os.path.join(output_dir, "csr.h"), csr_header) 75 | soc_header = get_soc_header(self.constants, with_access_functions=False) 76 | tools.write_to_file(os.path.join(output_dir, "soc.h"), soc_header) 77 | mem_header = get_mem_header(self.mem_regions) 78 | tools.write_to_file(os.path.join(output_dir, "mem.h"), mem_header) 79 | 80 | 81 | default_subtarget = PCIeDMASoC 82 | -------------------------------------------------------------------------------- /poetry.lock: -------------------------------------------------------------------------------- 1 | # This file is automatically @generated by Poetry 2.2.1 and should not be changed by hand. 2 | 3 | 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