├── .gitignore ├── docs └── autochip-tree.png ├── verilogeval_prompts_tbs ├── validation_set │ ├── 7420 │ │ ├── canonical_solution.txt │ │ └── 7420.sv │ ├── circuit4 │ │ └── canonical_solution.txt │ ├── ece241_2014_q1c │ │ ├── canonical_solution.txt │ │ └── ece241_2014_q1c.sv │ ├── thermostat │ │ └── canonical_solution.txt │ ├── rule90 │ │ └── canonical_solution.txt │ ├── lfsr32 │ │ ├── canonical_solution.txt │ │ └── lfsr32.sv │ ├── review2015_fsmseq │ │ ├── review2015_fsmseq.sv │ │ └── canonical_solution.txt │ ├── countbcd │ │ ├── canonical_solution.txt │ │ └── countbcd.sv │ └── fsm_ps2 │ │ └── canonical_solution.txt ├── ve_testbenches_human │ ├── 7420 │ │ ├── canonical_solution.txt │ │ └── 7420.sv │ ├── 7458 │ │ └── canonical_solution.txt │ ├── circuit1 │ │ └── canonical_solution.txt │ ├── m2014_q4j │ │ ├── canonical_solution.txt │ │ └── m2014_q4j.sv │ ├── wire │ │ ├── canonical_solution.txt │ │ └── wire.sv │ ├── zero │ │ ├── canonical_solution.txt │ │ └── zero.sv │ ├── andgate │ │ ├── canonical_solution.txt │ │ └── andgate.sv │ ├── circuit2 │ │ └── canonical_solution.txt │ ├── circuit4 │ │ └── canonical_solution.txt │ ├── hadd │ │ ├── canonical_solution.txt │ │ └── hadd.sv │ ├── m2014_q4e │ │ ├── canonical_solution.txt │ │ └── m2014_q4e.sv │ ├── m2014_q4f │ │ ├── canonical_solution.txt │ │ └── m2014_q4f.sv │ ├── m2014_q4h │ │ ├── canonical_solution.txt │ │ └── m2014_q4h.sv │ ├── m2014_q4i │ │ ├── canonical_solution.txt │ │ └── m2014_q4i.sv │ ├── mt2015_q4 │ │ └── canonical_solution.txt │ ├── mt2015_q4b │ │ └── canonical_solution.txt │ ├── notgate │ │ ├── canonical_solution.txt │ │ └── notgate.sv │ ├── reduction │ │ ├── canonical_solution.txt │ │ └── reduction.sv │ ├── step_one │ │ ├── canonical_solution.txt │ │ └── step_one.sv │ ├── xnorgate │ │ ├── canonical_solution.txt │ │ └── xnorgate.sv │ ├── circuit3 │ │ └── canonical_solution.txt │ ├── fadd │ │ ├── canonical_solution.txt │ │ └── fadd.sv │ ├── kmap1 │ │ ├── canonical_solution.txt │ │ └── kmap1.sv │ ├── mt2015_q4a │ │ ├── canonical_solution.txt │ │ └── mt2015_q4a.sv │ ├── mux256to1 │ │ ├── canonical_solution.txt │ │ └── mux256to1.sv │ ├── mux2to1 │ │ ├── canonical_solution.txt │ │ └── mux2to1.sv │ ├── mux2to1v │ │ ├── canonical_solution.txt │ │ └── mux2to1v.sv │ ├── norgate │ │ ├── canonical_solution.txt │ │ └── norgate.sv │ ├── m2014_q4g │ │ ├── canonical_solution.txt │ │ └── m2014_q4g.sv │ ├── mt2015_eq2 │ │ ├── canonical_solution.txt │ │ └── mt2015_eq2.sv │ ├── vector1 │ │ ├── canonical_solution.txt │ │ └── vector1.sv │ ├── wire4 │ │ ├── canonical_solution.txt │ │ └── wire4.sv │ ├── popcount3 │ │ ├── canonical_solution.txt │ │ └── popcount3.sv │ ├── vector4 │ │ ├── canonical_solution.txt │ │ └── vector4.sv │ ├── circuit7 │ │ └── canonical_solution.txt │ ├── vector3 │ │ ├── canonical_solution.txt │ │ └── vector3.sv │ ├── ece241_2013_q7 │ │ ├── canonical_solution.txt │ │ └── ece241_2013_q7.sv │ ├── kmap2 │ │ ├── canonical_solution.txt │ │ └── kmap2.sv │ ├── vector0 │ │ ├── canonical_solution.txt │ │ └── vector0.sv │ ├── m2014_q4a │ │ ├── canonical_solution.txt │ │ └── m2014_q4a.sv │ ├── vector2 │ │ ├── canonical_solution.txt │ │ └── vector2.sv │ ├── 2012_q2b │ │ └── canonical_solution.txt │ ├── m2014_q6c │ │ └── canonical_solution.txt │ ├── dff │ │ ├── dff.sv │ │ └── canonical_solution.txt │ ├── dff8 │ │ ├── canonical_solution.txt │ │ └── dff8.sv │ ├── mux256to1v │ │ ├── canonical_solution.txt │ │ └── mux256to1v.sv │ ├── vectorr │ │ ├── canonical_solution.txt │ │ └── vectorr.sv │ ├── alwaysblock1 │ │ ├── canonical_solution.txt │ │ └── alwaysblock1.sv │ ├── bugs_mux2 │ │ ├── canonical_solution.txt │ │ └── bugs_mux2.sv │ ├── gates100 │ │ ├── canonical_solution.txt │ │ └── gates100.sv │ ├── gates4 │ │ ├── canonical_solution.txt │ │ └── gates4.sv │ ├── mt2015_muxdff │ │ └── canonical_solution.txt │ ├── vector5 │ │ ├── canonical_solution.txt │ │ └── vector5.sv │ ├── count15 │ │ ├── canonical_solution.txt │ │ └── count15.sv │ ├── dff8p │ │ ├── canonical_solution.txt │ │ └── dff8p.sv │ ├── dff8r │ │ ├── canonical_solution.txt │ │ └── dff8r.sv │ ├── ringer │ │ ├── canonical_solution.txt │ │ └── ringer.sv │ ├── 2014_q4a │ │ ├── canonical_solution.txt │ │ └── 2014_q4a.sv │ ├── circuit8 │ │ └── canonical_solution.txt │ ├── count10 │ │ ├── canonical_solution.txt │ │ └── count10.sv │ ├── vector100r │ │ ├── canonical_solution.txt │ │ └── vector100r.sv │ ├── count1to10 │ │ ├── canonical_solution.txt │ │ └── count1to10.sv │ ├── dff8ar │ │ ├── canonical_solution.txt │ │ └── dff8ar.sv │ ├── m2014_q4c │ │ ├── canonical_solution.txt │ │ └── m2014_q4c.sv │ ├── popcount255 │ │ ├── canonical_solution.txt │ │ └── popcount255.sv │ ├── always_if │ │ ├── canonical_solution.txt │ │ └── always_if.sv │ ├── m2014_q4d │ │ ├── canonical_solution.txt │ │ └── m2014_q4d.sv │ ├── review2015_count1k │ │ ├── canonical_solution.txt │ │ └── review2015_count1k.sv │ ├── vectorgates │ │ ├── canonical_solution.txt │ │ └── vectorgates.sv │ ├── ece241_2014_q1c │ │ ├── canonical_solution.txt │ │ └── ece241_2014_q1c.sv │ ├── wire_decl │ │ └── canonical_solution.txt │ ├── m2014_q4b │ │ ├── canonical_solution.txt │ │ └── m2014_q4b.sv │ ├── ece241_2014_q3 │ │ └── canonical_solution.txt │ ├── gatesv100 │ │ └── canonical_solution.txt │ ├── truthtable1 │ │ ├── canonical_solution.txt │ │ └── truthtable1.sv │ ├── alwaysblock2 │ │ ├── canonical_solution.txt │ │ └── alwaysblock2.sv │ ├── circuit10 │ │ └── canonical_solution.txt │ ├── gatesv │ │ └── canonical_solution.txt │ ├── edgedetect │ │ ├── canonical_solution.txt │ │ └── edgedetect.sv │ ├── circuit9 │ │ └── canonical_solution.txt │ ├── edgedetect2 │ │ ├── canonical_solution.txt │ │ └── edgedetect2.sv │ ├── thermostat │ │ └── canonical_solution.txt │ ├── conditional │ │ ├── canonical_solution.txt │ │ └── conditional.sv │ ├── circuit5 │ │ └── canonical_solution.txt │ ├── bugs_addsubz │ │ └── canonical_solution.txt │ ├── ece241_2013_q12 │ │ └── canonical_solution.txt │ ├── rule90 │ │ └── canonical_solution.txt │ ├── ece241_2014_q4 │ │ └── canonical_solution.txt │ ├── m2014_q4k │ │ ├── m2014_q4k.sv │ │ └── canonical_solution.txt │ ├── review2015_shiftcount │ │ ├── canonical_solution.txt │ │ └── review2015_shiftcount.sv │ ├── countslow │ │ ├── canonical_solution.txt │ │ └── countslow.sv │ ├── shift4 │ │ ├── canonical_solution.txt │ │ └── shift4.sv │ ├── ece241_2013_q2 │ │ ├── canonical_solution.txt │ │ └── ece241_2013_q2.sv │ ├── edgecapture │ │ ├── canonical_solution.txt │ │ └── edgecapture.sv │ ├── rotate100 │ │ └── canonical_solution.txt │ ├── timer │ │ └── canonical_solution.txt │ ├── gates │ │ ├── canonical_solution.txt │ │ └── gates.sv │ ├── dff16e │ │ ├── canonical_solution.txt │ │ └── dff16e.sv │ ├── always_nolatches │ │ └── canonical_solution.txt │ ├── circuit6 │ │ └── canonical_solution.txt │ ├── lfsr5 │ │ ├── canonical_solution.txt │ │ └── lfsr5.sv │ ├── always_case │ │ ├── canonical_solution.txt │ │ └── always_case.sv │ ├── always_if2 │ │ └── canonical_solution.txt │ ├── mux9to1v │ │ ├── canonical_solution.txt │ │ └── mux9to1v.sv │ ├── fsm3comb │ │ ├── canonical_solution.txt │ │ └── fsm3comb.sv │ ├── review2015_fsmseq │ │ ├── review2015_fsmseq.sv │ │ └── canonical_solution.txt │ ├── 2012_q1g │ │ ├── 2012_q1g.sv │ │ └── canonical_solution.txt │ ├── lfsr32 │ │ ├── canonical_solution.txt │ │ └── lfsr32.sv │ ├── kmap4 │ │ ├── kmap4.sv │ │ └── canonical_solution.txt │ ├── history_shift │ │ └── canonical_solution.txt │ ├── shift18 │ │ └── canonical_solution.txt │ ├── fsm3onehot │ │ ├── canonical_solution.txt │ │ └── fsm3onehot.sv │ ├── countbcd │ │ ├── canonical_solution.txt │ │ └── countbcd.sv │ ├── dualedge │ │ ├── dualedge.sv │ │ └── canonical_solution.txt │ ├── ece241_2014_q5b │ │ ├── canonical_solution.txt │ │ └── ece241_2014_q5b.sv │ ├── counter_2bc │ │ ├── canonical_solution.txt │ │ └── counter_2bc.sv │ ├── rule110 │ │ └── canonical_solution.txt │ ├── ece241_2014_q5a │ │ ├── canonical_solution.txt │ │ └── ece241_2014_q5a.sv │ ├── fsm2s │ │ ├── canonical_solution.txt │ │ └── fsm2s.sv │ ├── fsm1 │ │ ├── fsm1.sv │ │ └── canonical_solution.txt │ ├── fsm1s │ │ ├── canonical_solution.txt │ │ └── fsm1s.sv │ ├── always_casez │ │ ├── always_casez.sv │ │ └── canonical_solution.txt │ ├── fsm2 │ │ ├── canonical_solution.txt │ │ └── fsm2.sv │ ├── m2014_q3 │ │ ├── m2014_q3.sv │ │ └── canonical_solution.txt │ ├── kmap3 │ │ ├── kmap3.sv │ │ └── canonical_solution.txt │ ├── review2015_fsmshift │ │ ├── review2015_fsmshift.sv │ │ └── canonical_solution.txt │ ├── m2014_q6b │ │ ├── canonical_solution.txt │ │ └── m2014_q6b.sv │ ├── 2014_q3c │ │ ├── 2014_q3c.sv │ │ └── canonical_solution.txt │ ├── fsm3s │ │ ├── fsm3s.sv │ │ └── canonical_solution.txt │ ├── fsm3 │ │ ├── canonical_solution.txt │ │ └── fsm3.sv │ ├── lemmings1 │ │ └── canonical_solution.txt │ ├── m2014_q6 │ │ ├── m2014_q6.sv │ │ └── canonical_solution.txt │ ├── 2014_q3bfsm │ │ ├── 2014_q3bfsm.sv │ │ └── canonical_solution.txt │ ├── ece241_2013_q8 │ │ ├── ece241_2013_q8.sv │ │ └── canonical_solution.txt │ ├── 2012_q2fsm │ │ └── canonical_solution.txt │ ├── always_case2 │ │ ├── always_case2.sv │ │ └── canonical_solution.txt │ ├── review2015_fsmonehot │ │ └── canonical_solution.txt │ ├── fsm_ps2 │ │ └── canonical_solution.txt │ ├── bugs_case │ │ ├── canonical_solution.txt │ │ └── bugs_case.sv │ ├── 2014_q3fsm │ │ └── canonical_solution.txt │ ├── 2013_q2afsm │ │ └── canonical_solution.txt │ ├── fsm_onehot │ │ └── canonical_solution.txt │ ├── lemmings2 │ │ └── canonical_solution.txt │ └── 2013_q2bfsm │ │ └── canonical_solution.txt └── ve_testbenches_machine │ ├── 7420 │ ├── canonical_solution.txt │ └── 7420.sv │ ├── 7458 │ └── canonical_solution.txt │ ├── m2014_q4j │ └── canonical_solution.txt │ ├── wire │ └── canonical_solution.txt │ ├── andgate │ ├── canonical_solution.txt │ └── andgate.sv │ ├── circuit1 │ ├── canonical_solution.txt │ └── circuit1.sv │ ├── circuit4 │ ├── canonical_solution.txt │ └── circuit4.sv │ ├── m2014_q4f │ ├── canonical_solution.txt │ └── m2014_q4f.sv │ ├── m2014_q4h │ ├── canonical_solution.txt │ └── m2014_q4h.sv │ ├── mt2015_q4 │ ├── canonical_solution.txt │ └── mt2015_q4.sv │ ├── notgate │ ├── canonical_solution.txt │ └── notgate.sv │ ├── step_one │ ├── canonical_solution.txt │ └── step_one.sv │ ├── zero │ ├── canonical_solution.txt │ └── zero.sv │ ├── circuit2 │ ├── canonical_solution.txt │ └── circuit2.sv │ ├── hadd │ └── canonical_solution.txt │ ├── kmap1 │ ├── canonical_solution.txt │ └── kmap1.sv │ ├── m2014_q4e │ ├── canonical_solution.txt │ └── m2014_q4e.sv │ ├── m2014_q4i │ ├── canonical_solution.txt │ └── m2014_q4i.sv │ ├── mt2015_q4a │ ├── canonical_solution.txt │ └── mt2015_q4a.sv │ ├── mt2015_q4b │ ├── canonical_solution.txt │ └── mt2015_q4b.sv │ ├── mux256to1 │ ├── canonical_solution.txt │ └── mux256to1.sv │ ├── mux2to1 │ ├── canonical_solution.txt │ └── mux2to1.sv │ ├── norgate │ ├── canonical_solution.txt │ └── norgate.sv │ ├── reduction │ ├── canonical_solution.txt │ └── reduction.sv │ ├── xnorgate │ ├── canonical_solution.txt │ └── xnorgate.sv │ ├── circuit3 │ ├── canonical_solution.txt │ └── circuit3.sv │ ├── fadd │ └── canonical_solution.txt │ ├── m2014_q4g │ ├── canonical_solution.txt │ └── m2014_q4g.sv │ ├── mt2015_eq2 │ ├── canonical_solution.txt │ └── mt2015_eq2.sv │ ├── mux2to1v │ ├── canonical_solution.txt │ └── mux2to1v.sv │ ├── vector1 │ ├── canonical_solution.txt │ └── vector1.sv │ ├── wire4 │ ├── canonical_solution.txt │ └── wire4.sv │ ├── popcount3 │ ├── canonical_solution.txt │ └── popcount3.sv │ ├── vector4 │ ├── canonical_solution.txt │ └── vector4.sv │ ├── circuit7 │ ├── canonical_solution.txt │ └── circuit7.sv │ ├── vector3 │ └── canonical_solution.txt │ ├── ece241_2013_q7 │ └── canonical_solution.txt │ ├── kmap2 │ ├── canonical_solution.txt │ └── kmap2.sv │ ├── m2014_q4a │ ├── canonical_solution.txt │ └── m2014_q4a.sv │ ├── vector0 │ └── canonical_solution.txt │ ├── 2012_q2b │ └── canonical_solution.txt │ ├── m2014_q6c │ ├── canonical_solution.txt │ └── m2014_q6c.sv │ ├── vector2 │ ├── canonical_solution.txt │ └── vector2.sv │ ├── dff │ ├── canonical_solution.txt │ └── dff.sv │ ├── dff8 │ └── canonical_solution.txt │ ├── mux256to1v │ ├── canonical_solution.txt │ └── mux256to1v.sv │ ├── alwaysblock1 │ └── canonical_solution.txt │ ├── bugs_mux2 │ ├── canonical_solution.txt │ └── bugs_mux2.sv │ ├── gates100 │ └── canonical_solution.txt │ ├── gates4 │ └── canonical_solution.txt │ ├── mt2015_muxdff │ └── canonical_solution.txt │ ├── vector5 │ ├── canonical_solution.txt │ └── vector5.sv │ ├── vectorr │ ├── canonical_solution.txt │ └── vectorr.sv │ ├── dff8r │ └── canonical_solution.txt │ ├── ringer │ └── canonical_solution.txt │ ├── 2014_q4a │ └── canonical_solution.txt │ ├── count15 │ └── canonical_solution.txt │ ├── dff8p │ └── canonical_solution.txt │ ├── circuit8 │ ├── canonical_solution.txt │ └── circuit8.sv │ ├── vector100r │ └── canonical_solution.txt │ ├── count10 │ ├── canonical_solution.txt │ └── count10.sv │ ├── count1to10 │ ├── canonical_solution.txt │ └── count1to10.sv │ ├── dff8ar │ └── canonical_solution.txt │ ├── m2014_q4c │ ├── canonical_solution.txt │ └── m2014_q4c.sv │ ├── always_if │ └── canonical_solution.txt │ ├── m2014_q4d │ ├── canonical_solution.txt │ └── m2014_q4d.sv │ ├── popcount255 │ └── canonical_solution.txt │ ├── review2015_count1k │ ├── canonical_solution.txt │ └── review2015_count1k.sv │ ├── vectorgates │ └── canonical_solution.txt │ ├── wire_decl │ └── canonical_solution.txt │ ├── ece241_2014_q1c │ └── canonical_solution.txt │ ├── m2014_q4b │ └── canonical_solution.txt │ ├── ece241_2014_q3 │ ├── canonical_solution.txt │ └── ece241_2014_q3.sv │ ├── truthtable1 │ ├── canonical_solution.txt │ └── truthtable1.sv │ ├── alwaysblock2 │ └── canonical_solution.txt │ ├── gatesv │ └── canonical_solution.txt │ ├── gatesv100 │ └── canonical_solution.txt │ ├── circuit10 │ └── canonical_solution.txt │ ├── circuit9 │ ├── canonical_solution.txt │ └── circuit9.sv │ ├── edgedetect │ └── canonical_solution.txt │ ├── edgedetect2 │ └── canonical_solution.txt │ ├── thermostat │ └── canonical_solution.txt │ ├── conditional │ └── canonical_solution.txt │ ├── circuit5 │ └── canonical_solution.txt │ ├── ece241_2013_q12 │ ├── canonical_solution.txt │ └── ece241_2013_q12.sv │ ├── bugs_addsubz │ └── canonical_solution.txt │ ├── ece241_2014_q4 │ └── canonical_solution.txt │ ├── rule90 │ └── canonical_solution.txt │ ├── review2015_shiftcount │ └── canonical_solution.txt │ ├── countslow │ └── canonical_solution.txt │ ├── shift4 │ └── canonical_solution.txt │ ├── m2014_q4k │ └── canonical_solution.txt │ ├── ece241_2013_q2 │ └── canonical_solution.txt │ ├── edgecapture │ └── canonical_solution.txt │ ├── rotate100 │ └── canonical_solution.txt │ ├── timer │ └── canonical_solution.txt │ ├── gates │ └── canonical_solution.txt │ ├── dff16e │ └── canonical_solution.txt │ ├── circuit6 │ └── canonical_solution.txt │ ├── always_nolatches │ └── canonical_solution.txt │ ├── lfsr5 │ └── canonical_solution.txt │ ├── always_case │ └── canonical_solution.txt │ ├── always_if2 │ └── canonical_solution.txt │ ├── mux9to1v │ └── canonical_solution.txt │ ├── fsm3comb │ └── canonical_solution.txt │ ├── lfsr32 │ └── canonical_solution.txt │ ├── history_shift │ └── canonical_solution.txt │ ├── shift18 │ └── canonical_solution.txt │ ├── fsm3onehot │ └── canonical_solution.txt │ ├── ece241_2014_q5b │ └── canonical_solution.txt │ ├── counter_2bc │ └── canonical_solution.txt │ ├── rule110 │ └── canonical_solution.txt │ ├── ece241_2014_q5a │ └── canonical_solution.txt │ ├── fsm1s │ └── canonical_solution.txt │ ├── fsm2s │ └── canonical_solution.txt │ ├── always_casez │ └── canonical_solution.txt │ ├── dualedge │ └── canonical_solution.txt │ ├── fsm1 │ ├── canonical_solution.txt │ └── fsm1.sv │ ├── fsm2 │ └── canonical_solution.txt │ ├── 2012_q1g │ └── canonical_solution.txt │ ├── m2014_q6b │ └── canonical_solution.txt │ ├── m2014_q3 │ └── canonical_solution.txt │ ├── fsm3s │ └── canonical_solution.txt │ ├── lemmings1 │ └── canonical_solution.txt │ ├── fsm3 │ └── canonical_solution.txt │ ├── 2014_q3bfsm │ └── canonical_solution.txt │ ├── review2015_fsmshift │ ├── canonical_solution.txt │ └── review2015_fsmshift.sv │ ├── review2015_fsmseq │ └── canonical_solution.txt │ ├── 2012_q2fsm │ └── canonical_solution.txt │ ├── 2014_q3c │ └── canonical_solution.txt │ ├── always_case2 │ └── canonical_solution.txt │ ├── review2015_fsmonehot │ └── canonical_solution.txt │ ├── fsm_ps2 │ └── canonical_solution.txt │ ├── m2014_q6 │ └── canonical_solution.txt │ ├── bugs_case │ └── canonical_solution.txt │ ├── ece241_2013_q8 │ ├── canonical_solution.txt │ └── ece241_2013_q8.sv │ ├── 2014_q3fsm │ ├── canonical_solution.txt │ └── 2014_q3fsm.sv │ ├── kmap4 │ └── canonical_solution.txt │ ├── kmap3 │ └── canonical_solution.txt │ ├── 2013_q2afsm │ └── canonical_solution.txt │ ├── fsm_onehot │ └── canonical_solution.txt │ └── 2013_q2bfsm │ └── canonical_solution.txt ├── requirements.txt └── autochip_scripts ├── tools.py └── utils.py /.gitignore: -------------------------------------------------------------------------------- 1 | venv/ 2 | __pycache__/ 3 | *.vcd 4 | -------------------------------------------------------------------------------- /docs/autochip-tree.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shailja-thakur/AutoChip/HEAD/docs/autochip-tree.png -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/circuit4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = c | b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /requirements.txt: -------------------------------------------------------------------------------- 1 | openai 2 | anthropic 3 | google-generativeai 4 | transformers 5 | torch 6 | mistralai 7 | tiktoken 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = a&b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4j/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign sum = x+y; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/wire/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/zero/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign zero = 1'b0; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4j/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign sum = x+y; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/wire/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/andgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = a & b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = ~a^b^c^d; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = c | b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/hadd/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {cout, sum} = a+b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4e/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~(in1 | in2); 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4f/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in1 & ~in2; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4h/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4i/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = 1'b0; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_q4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = x|~y; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_q4b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = ~(x^y); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/notgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/reduction/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign parity = ^in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/step_one/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign one = 1'b1; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/xnorgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~(a^b); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/andgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = a & b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = a&b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = c | b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4f/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in1 & ~in2; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4h/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_q4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = x|~y; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/notgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/step_one/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign one = 1'b1; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/zero/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign zero = 1'b0; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = (a|b) & (c|d); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fadd/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {cout, sum} = a+b+cin; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = (a | b | c); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_q4a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = (x^y) & x; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux256to1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in[sel]; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux2to1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = sel ? b : a; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux2to1v/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = sel ? b : a; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/norgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~(a | b); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = ~a^b^c^d; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/hadd/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {cout, sum} = a+b; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/kmap1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = (a | b | c); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4e/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~(in1 | in2); 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4i/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = 1'b0; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_q4a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = (x^y) & x; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_q4b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = ~(x^y); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux256to1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in[sel]; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux2to1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = sel ? b : a; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/norgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~(a | b); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/reduction/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign parity = ^in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/xnorgate/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~(a^b); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4g/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = (~(in1 ^ in2)) ^ in3; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_eq2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = A[1:0]==B[1:0]; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {out_hi, out_lo} = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/wire4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {w,x,y,z} = {a,b,b,c}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign q = (a|b) & (c|d); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fadd/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {cout, sum} = a+b+cin; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4g/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = (~(in1 ^ in2)) ^ in3; 3 | endmodule 4 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_eq2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign z = A[1:0]==B[1:0]; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux2to1v/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = sel ? b : a; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {out_hi, out_lo} = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/wire4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {w,x,y,z} = {a,b,b,c}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/popcount3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in[0]+in[1]+in[2]; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = { {24{in[7]}}, in }; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/popcount3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = in[0]+in[1]+in[2]; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = { {24{in[7]}}, in }; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit7/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | q <= ~a; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign { w,x,y,z} = {a,b,c,d,e,f,2'b11}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit7/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | q <= ~a; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign { w,x,y,z} = {a,b,c,d,e,f,2'b11}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q7/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | Q <= j&~Q | ~k&Q; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector0/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign outv = vec; 3 | assign {o2, o1, o0} = vec; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/zero/zero.sv: -------------------------------------------------------------------------------- 1 | // Build a circuit that always outputs a LOW. 2 | 3 | module top_module( 4 | output zero); 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always@(*) begin 3 | if (ena) 4 | q = d; 5 | end 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = {in[7:0], in[15:8], in[23:16], in[31:24]}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2013_q7/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | Q <= j&~Q | ~k&Q; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/kmap2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = (~c & ~b) | (~d&~a) | (a&c&d) | (b&c&d); 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always@(*) begin 3 | if (ena) 4 | q = d; 5 | end 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector0/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign outv = vec; 3 | assign {o2, o1, o0} = vec; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2012_q2b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | assign Y1 = y[0]&w; 2 | assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q6c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | assign Y2 = y[1]&~w; 2 | assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2012_q2b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | assign Y1 = y[0]&w; 2 | assign Y3 = (y[1]|y[2]|y[4]|y[5]) & ~w; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q6c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | assign Y2 = y[1]&~w; 2 | assign Y4 = (y[2]|y[3]|y[5]|y[6]) & w; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = {in[7:0], in[15:8], in[23:16], in[31:24]}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff/dff.sv: -------------------------------------------------------------------------------- 1 | // Create a single D flip-flop. 2 | 3 | module top_module( 4 | input clk, 5 | input d, 6 | output reg q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial 3 | q = 1'hx; 4 | 5 | always @(posedge clk) 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial 3 | q = 8'h0; 4 | 5 | always @(posedge clk) 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux256to1v/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vectorr/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial 3 | q = 1'hx; 4 | 5 | always @(posedge clk) 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff8/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial 3 | q = 8'h0; 4 | 5 | always @(posedge clk) 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux256to1v/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/alwaysblock1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_assign = a & b; 3 | always @(*) out_alwaysblock = a & b; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/bugs_mux2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | // assign out = (~sel & a) | (sel & b); 3 | assign out = sel ? a : b; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gates100/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_and = ∈ 3 | assign out_or = |in; 4 | assign out_xor = ^in; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gates4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_and = ∈ 3 | assign out_or = |in; 4 | assign out_xor = ^in; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_muxdff/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial Q=0; 3 | always @(posedge clk) 4 | Q <= L ? r_in : q_in; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/notgate/notgate.sv: -------------------------------------------------------------------------------- 1 | // Create a module that implements a NOT gate. 2 | 3 | module top_module( 4 | input in, 5 | output out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector5/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/alwaysblock1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_assign = a & b; 3 | always @(*) out_alwaysblock = a & b; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/bugs_mux2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | // assign out = (~sel & a) | (sel & b); 3 | assign out = sel ? a : b; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/gates100/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_and = ∈ 3 | assign out_or = |in; 4 | assign out_xor = ^in; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/gates4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_and = ∈ 3 | assign out_or = |in; 4 | assign out_xor = ^in; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_muxdff/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial Q=0; 3 | always @(posedge clk) 4 | Q <= L ? r_in : q_in; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector5/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out = ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } ^ {5{a,b,c,d,e}}; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vectorr/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign {out[0],out[1],out[2],out[3],out[4],out[5],out[6],out[7]} = in; 3 | 4 | endmodule 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/7420/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign p1y = ~&( {p1a, p1b, p1c, p1d} ); 3 | assign p2y = ~&( {p2a, p2b, p2c, p2d} ); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/count15/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset) 4 | q <= 0; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8p/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(negedge clk) 3 | if (reset) 4 | q <= 8'h34; 5 | else 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8r/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset) 4 | q <= 0; 5 | else 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ringer/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign ringer = ring & ~vibrate_mode; 3 | assign motor = ring & vibrate_mode; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff8r/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset) 4 | q <= 0; 5 | else 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ringer/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign ringer = ring & ~vibrate_mode; 3 | assign motor = ring & vibrate_mode; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q4a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (L) 4 | Q <= R; 5 | else if (E) 6 | Q <= w; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/7420/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign p1y = ~&( {p1a, p1b, p1c, p1d} ); 3 | assign p2y = ~&( {p2a, p2b, p2c, p2d} ); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit8/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(negedge clock) 3 | q <= a; 4 | 5 | always @(*) 6 | if (clock) 7 | p = a; 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2014_q4a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (L) 4 | Q <= R; 5 | else if (E) 6 | Q <= w; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/7420/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign p1y = ~&( {p1a, p1b, p1c, p1d} ); 3 | assign p2y = ~&( {p2a, p2b, p2c, p2d} ); 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/count15/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset) 4 | q <= 0; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff8p/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(negedge clk) 3 | if (reset) 4 | q <= 8'h34; 5 | else 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/7458/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f}; 3 | assign p2y = &{p2a, p2b} | &{p2c, p2d}; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/andgate/andgate.sv: -------------------------------------------------------------------------------- 1 | // Create a module that implements an AND gate. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/count10/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset || q == 9) 4 | q <= 0; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4e/m2014_q4e.sv: -------------------------------------------------------------------------------- 1 | // Implement a 2-input NOR gate. 2 | 3 | module top_module ( 4 | input in1, 5 | input in2, 6 | output logic out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_q4a/mt2015_q4a.sv: -------------------------------------------------------------------------------- 1 | // Implement the boolean function z = (x^y) & x. 2 | 3 | module top_module( 4 | input x, 5 | input y, 6 | output z); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/norgate/norgate.sv: -------------------------------------------------------------------------------- 1 | // Create a module that implements a NOR gate. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector100r/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb 3 | for (int i=0;i<$bits(out);i++) 4 | out[i] = in[$bits(out)-i-1]; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/wire/wire.sv: -------------------------------------------------------------------------------- 1 | // Create a module with one input and one output that behaves like a wire. 2 | 3 | module top_module( 4 | input in, 5 | output out); 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/xnorgate/xnorgate.sv: -------------------------------------------------------------------------------- 1 | // Create a module that implements an XNOR gate. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit8/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(negedge clock) 3 | q <= a; 4 | 5 | always @(*) 6 | if (clock) 7 | p = a; 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector100r/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb 3 | for (int i=0;i<$bits(out);i++) 4 | out[i] = in[$bits(out)-i-1]; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/count1to10/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset || q == 10) 4 | q <= 1; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8ar/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk, posedge areset) 3 | if (areset) 4 | q <= 0; 5 | else 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/7458/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign p1y = &{p1a, p1b, p1c} | &{p1d, p1e, p1f}; 3 | assign p2y = &{p2a, p2b} | &{p2c, p2d}; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/count10/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset || q == 9) 4 | q <= 0; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4a/m2014_q4a.sv: -------------------------------------------------------------------------------- 1 | // Implement a D latch using an always block. 2 | 3 | 4 | module top_module ( 5 | input d, 6 | input ena, 7 | output logic q 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always@(posedge clk) begin 3 | if (r) 4 | q <= 0; 5 | else 6 | q <= d; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/popcount255/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | out = 0; 4 | for (int i=0;i<255;i++) 5 | out = out + in[i]; 6 | end 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/count1to10/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset || q == 10) 4 | q <= 1; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff8ar/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk, posedge areset) 3 | if (areset) 4 | q <= 0; 5 | else 6 | q <= d; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always@(posedge clk) begin 3 | if (r) 4 | q <= 0; 5 | else 6 | q <= d; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/ece241_2014_q1c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire [8:0] sum = a+b; 3 | assign s = sum[7:0]; 4 | assign overflow = !(a[7]^b[7]) && (a[7] != s[7]); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_if/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_assign = (sel_b1 & sel_b2) ? b : a; 3 | always @(*) out_always = (sel_b1 & sel_b2) ? b : a; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4d/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial 3 | out = 0; 4 | 5 | always@(posedge clk) begin 6 | out <= in ^ out; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_count1k/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset || q == 999) 4 | q <= 0; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vectorgates/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_or_bitwise = a | b; 3 | assign out_or_logical = a || b; 4 | assign out_not = {~b,~a}; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vectorr/vectorr.sv: -------------------------------------------------------------------------------- 1 | // Given an 8-bit input vector [7:0], reverse its bit ordering. 2 | 3 | module top_module ( 4 | input [7:0] in, 5 | output [7:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/always_if/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_assign = (sel_b1 & sel_b2) ? b : a; 3 | always @(*) out_always = (sel_b1 & sel_b2) ? b : a; 4 | 5 | endmodule 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4d/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | initial 3 | out = 0; 4 | 5 | always@(posedge clk) begin 6 | out <= in ^ out; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/popcount255/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | out = 0; 4 | for (int i=0;i<255;i++) 5 | out = out + in[i]; 6 | end 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_count1k/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset || q == 999) 4 | q <= 0; 5 | else 6 | q <= q+1; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vectorgates/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_or_bitwise = a | b; 3 | assign out_or_logical = a || b; 4 | assign out_not = {~b,~a}; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q1c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire [8:0] sum = a+b; 3 | assign s = sum[7:0]; 4 | assign overflow = !(a[7]^b[7]) && (a[7] != s[7]); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4i/m2014_q4i.sv: -------------------------------------------------------------------------------- 1 | // Build a circuit with no inputs and one output. That output should always drive 0 (or logic low). 2 | 3 | module top_module( 4 | output out); 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/step_one/step_one.sv: -------------------------------------------------------------------------------- 1 | // Build a circuit with no inputs and one output. That output should always drive 1 (or logic high). 2 | 3 | module top_module( 4 | output one); 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector2/vector2.sv: -------------------------------------------------------------------------------- 1 | // Build a circuit that reverses the byte order of a 32-bit vector. 2 | 3 | module top_module ( 4 | input [31:0] in, 5 | output [31:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/wire_decl/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire w1, w2; 3 | assign w1 = a&b; 4 | assign w2 = c&d; 5 | assign out = w1|w2; 6 | assign out_n = ~out; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/wire_decl/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire w1, w2; 3 | assign w1 = a&b; 4 | assign w2 = c&d; 5 | assign out = w1|w2; 6 | assign out_n = ~out; 7 | 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always@(posedge clk or posedge ar) begin 3 | if (ar) 4 | q <= 0; 5 | else 6 | q <= d; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4h/m2014_q4h.sv: -------------------------------------------------------------------------------- 1 | // The module assigns the output port to the same value as the input port combinationally. 2 | 3 | module top_module( 4 | input in, 5 | output out); 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2014_q1c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire [8:0] sum = a+b; 3 | assign s = sum[7:0]; 4 | assign overflow = !(a[7]^b[7]) && (a[7] != s[7]); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always@(posedge clk or posedge ar) begin 3 | if (ar) 4 | q <= 0; 5 | else 6 | q <= d; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign mux_in[0] = c | d; 3 | assign mux_in[1] = 0; 4 | assign mux_in[2] = ~d; 5 | assign mux_in[3] = c&d; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gatesv100/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_both = in & in[99:1]; 3 | assign out_any = in | in[99:1]; 4 | assign out_different = in^{in[0], in[99:1]}; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/truthtable1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign f = ( ~x3 & x2 & ~x1 ) | 3 | ( ~x3 & x2 & x1 ) | 4 | ( x3 & ~x2 & x1 ) | 5 | ( x3 & x2 & x1 ) ; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector100r/vector100r.sv: -------------------------------------------------------------------------------- 1 | // Given a 100-bit input vector [99:0], reverse its bit ordering. 2 | 3 | module top_module ( 4 | input [99:0] in, 5 | output reg [99:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2014_q3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign mux_in[0] = c | d; 3 | assign mux_in[1] = 0; 4 | assign mux_in[2] = ~d; 5 | assign mux_in[3] = c&d; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/truthtable1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign f = ( ~x3 & x2 & ~x1 ) | 3 | ( ~x3 & x2 & x1 ) | 4 | ( x3 & ~x2 & x1 ) | 5 | ( x3 & x2 & x1 ) ; 6 | 7 | endmodule 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/alwaysblock2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_assign = a ^ b; 3 | always @(*) out_always_comb = a ^ b; 4 | always @(posedge clk) out_always_ff <= a ^ b; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit10/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg c; 3 | always @(posedge clk) 4 | c <= a&b | a&c | b&c; 5 | 6 | assign q = a^b^c; 7 | assign state = c; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gatesv/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_both = in[2:0] & in[3:1]; 3 | assign out_any = in[2:0] | in[3:1]; 4 | assign out_different = in^{in[0], in[3:1]}; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/alwaysblock2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_assign = a ^ b; 3 | always @(*) out_always_comb = a ^ b; 4 | always @(posedge clk) out_always_ff <= a ^ b; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/gatesv/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_both = in[2:0] & in[3:1]; 3 | assign out_any = in[2:0] | in[3:1]; 4 | assign out_different = in^{in[0], in[3:1]}; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/gatesv100/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_both = in & in[99:1]; 3 | assign out_any = in | in[99:1]; 4 | assign out_different = in^{in[0], in[99:1]}; 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/thermostat/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign fan = (mode ? too_cold : too_hot) | fan_on; 3 | assign heater = (mode & too_cold); 4 | assign aircon = (~mode & too_hot); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8/dff8.sv: -------------------------------------------------------------------------------- 1 | // Create 8 D flip-flops. All DFFs should be triggered by the positive edge of clk. 2 | 3 | module top_module( 4 | input clk, 5 | input [7:0] d, 6 | output reg [7:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/edgedetect/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [7:0] d_last; 3 | 4 | always @(posedge clk) begin 5 | d_last <= in; 6 | pedge <= in & ~d_last; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit10/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg c; 3 | always @(posedge clk) 4 | c <= a&b | a&c | b&c; 5 | 6 | assign q = a^b^c; 7 | assign state = c; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit9/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (a) 4 | q <= 4; 5 | else if (q == 6) 6 | q <= 0; 7 | else 8 | q <= q + 1'b1; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/edgedetect2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [7:0] d_last; 3 | 4 | always @(posedge clk) begin 5 | d_last <= in; 6 | anyedge <= in ^ d_last; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/thermostat/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign fan = (mode ? too_cold : too_hot) | fan_on; 3 | assign heater = (mode & too_cold); 4 | assign aircon = (~mode & too_hot); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit9/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (a) 4 | q <= 4; 5 | else if (q == 6) 6 | q <= 0; 7 | else 8 | q <= q + 1'b1; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/edgedetect/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [7:0] d_last; 3 | 4 | always @(posedge clk) begin 5 | d_last <= in; 6 | pedge <= in & ~d_last; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/edgedetect2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [7:0] d_last; 3 | 4 | always @(posedge clk) begin 5 | d_last <= in; 6 | anyedge <= in ^ d_last; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/thermostat/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign fan = (mode ? too_cold : too_hot) | fan_on; 3 | assign heater = (mode & too_cold); 4 | assign aircon = (~mode & too_hot); 5 | 6 | endmodule 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/conditional/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | min = a; 4 | if (min > b) min = b; 5 | if (min > c) min = c; 6 | if (min > d) min = d; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/conditional/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | min = a; 4 | if (min > b) min = b; 5 | if (min > c) min = c; 6 | if (min > d) min = d; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux2to1/mux2to1.sv: -------------------------------------------------------------------------------- 1 | // Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input sel, 7 | output out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/rule90/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (load) 4 | q <= data; 5 | else begin 6 | q <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ; 7 | end 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit5/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) 3 | case (c) 4 | 0: q = b; 5 | 1: q = e; 6 | 2: q = a; 7 | 3: q = d; 8 | default: q = 4'hf; 9 | endcase 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4b/m2014_q4b.sv: -------------------------------------------------------------------------------- 1 | // Implement a D flip flop, positive edge triggered, with an asynchronous reset "ar". 2 | 3 | module top_module ( 4 | input clk, 5 | input d, 6 | input ar, 7 | output logic q 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit5/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) 3 | case (c) 4 | 0: q = b; 5 | 1: q = e; 6 | 2: q = a; 7 | 3: q = d; 8 | default: q = 4'hf; 9 | endcase 10 | 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/bugs_addsubz/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case (do_sub) 4 | 0: out = a + b; 5 | 1: out = a - b; 6 | endcase 7 | result_is_zero = (out == 0); 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q12/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [7:0] q; 3 | always @(posedge clk) begin 4 | if (enable) 5 | q <= {q[6:0], S}; 6 | end 7 | 8 | assign Z = q[ {A, B, C} ]; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/hadd/hadd.sv: -------------------------------------------------------------------------------- 1 | // Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | output sum, 7 | output cout 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4c/m2014_q4c.sv: -------------------------------------------------------------------------------- 1 | // Implement a simple D flip flop with active high synchronous reset (reset output to 0). 2 | 3 | module top_module ( 4 | input clk, 5 | input d, 6 | input r, 7 | output logic q 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4j/m2014_q4j.sv: -------------------------------------------------------------------------------- 1 | // Implement a 4-bit adder with full adders. The output sum should include the overflow bit. 2 | 3 | module top_module ( 4 | input [3:0] x, 5 | input [3:0] y, 6 | output [4:0] sum 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux2to1v/mux2to1v.sv: -------------------------------------------------------------------------------- 1 | // Create a 2-1 multiplexer. When sel=0, choose a. When sel=1, choose b. 2 | 3 | module top_module ( 4 | input [99:0] a, 5 | input [99:0] b, 6 | input sel, 7 | output [99:0] out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/rule90/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (load) 4 | q <= data; 5 | else begin 6 | q <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ; 7 | end 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2013_q12/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [7:0] q; 3 | always @(posedge clk) begin 4 | if (enable) 5 | q <= {q[6:0], S}; 6 | end 7 | 8 | assign Z = q[ {A, B, C} ]; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [2:0] s = 0; 3 | 4 | always @(posedge clk) begin 5 | s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x }; 6 | end 7 | 8 | assign z = ~|s; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4k/m2014_q4k.sv: -------------------------------------------------------------------------------- 1 | // Implement a shift register with four D flops. Reset is active-low synchronous resettable. 2 | 3 | module top_module ( 4 | input clk, 5 | input resetn, 6 | input in, 7 | output out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_shiftcount/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (shift_ena) 4 | q <= { q[2:0], data }; 5 | else if (count_ena) 6 | q <= q - 1'b1; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/bugs_addsubz/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case (do_sub) 4 | 0: out = a + b; 5 | 1: out = a - b; 6 | endcase 7 | result_is_zero = (out == 0); 8 | end 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2014_q4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [2:0] s = 0; 3 | 4 | always @(posedge clk) begin 5 | s <= { s[2] ^ x, ~s[1] & x, ~s[0] | x }; 6 | end 7 | 8 | assign z = ~|s; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/rule90/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (load) 4 | q <= data; 5 | else begin 6 | q <= q[$bits(q)-1:1] ^ {q[$bits(q)-2:0], 1'b0} ; 7 | end 8 | end 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_shiftcount/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (shift_ena) 4 | q <= { q[2:0], data }; 5 | else if (count_ena) 6 | q <= q - 1'b1; 7 | end 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/countslow/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset) 4 | q <= 0; 5 | else if (slowena) begin 6 | if (q == 9) 7 | q <= 0; 8 | else 9 | q <= q+1; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/shift4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | always @(posedge clk, posedge areset) begin 4 | if (areset) 5 | q <= 0; 6 | else if (load) 7 | q <= data; 8 | else if (ena) 9 | q <= q[3:1]; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/countslow/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) 3 | if (reset) 4 | q <= 0; 5 | else if (slowena) begin 6 | if (q == 9) 7 | q <= 0; 8 | else 9 | q <= q+1; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/alwaysblock1/alwaysblock1.sv: -------------------------------------------------------------------------------- 1 | // Build an AND gate using both an assign statement and a combinational always block. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out_assign, 7 | output reg out_alwaysblock 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/popcount3/popcount3.sv: -------------------------------------------------------------------------------- 1 | // A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector. 2 | 3 | module top_module ( 4 | input [2:0] in, 5 | output [1:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/shift4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | always @(posedge clk, posedge areset) begin 4 | if (areset) 5 | q <= 0; 6 | else if (load) 7 | q <= data; 8 | else if (ena) 9 | q <= q[3:1]; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fadd/fadd.sv: -------------------------------------------------------------------------------- 1 | // Create a full adder. A full adder adds three bits (including carry-in) and produces a sum and carry-out. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input cin, 7 | output cout, 8 | output sum 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4k/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [3:0] sr; 3 | always @(posedge clk) begin 4 | if (~resetn) 5 | sr <= '0; 6 | else 7 | sr <= {sr[2:0], in}; 8 | end 9 | 10 | assign out = sr[3]; 11 | 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4k/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [3:0] sr; 3 | always @(posedge clk) begin 4 | if (~resetn) 5 | sr <= '0; 6 | else 7 | sr <= {sr[2:0], in}; 8 | end 9 | 10 | assign out = sr[3]; 11 | 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire pos0, pos1; 3 | assign out_sop = c&d | ~a&~b&c; 4 | assign pos0 = c & (~b|d)&(~a|b); 5 | assign pos1 = c & (~b|d)&(~a|d); 6 | 7 | assign out_pos = (pos0 == pos1) ? pos0 : 1'bx; 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/edgecapture/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [31:0] d_last; 3 | 4 | always @(posedge clk) begin 5 | d_last <= in; 6 | if (reset) 7 | out <= '0; 8 | else 9 | out <= out | (~in & d_last); 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2013_q2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire pos0, pos1; 3 | assign out_sop = c&d | ~a&~b&c; 4 | assign pos0 = c & (~b|d)&(~a|b); 5 | assign pos1 = c & (~b|d)&(~a|d); 6 | 7 | assign out_pos = (pos0 == pos1) ? pos0 : 1'bx; 8 | endmodule 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/edgecapture/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | reg [31:0] d_last; 3 | 4 | always @(posedge clk) begin 5 | d_last <= in; 6 | if (reset) 7 | out <= '0; 8 | else 9 | out <= out | (~in & d_last); 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/count1to10/count1to10.sv: -------------------------------------------------------------------------------- 1 | // Make a decade counter that counts 1 through 10, inclusive. The reset input is active high synchronous, and should reset the counter to 1. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [3:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/popcount255/popcount255.sv: -------------------------------------------------------------------------------- 1 | // A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector. 2 | 3 | module top_module ( 4 | input [254:0] in, 5 | output reg [7:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector1/vector1.sv: -------------------------------------------------------------------------------- 1 | // Build a combinational circuit that splits an input half-word (16 bits, [15:0] ) into lower [7:0] and upper [15:8] bytes. 2 | 3 | module top_module ( 4 | input [15:0] in, 5 | output [7:0] out_hi, 6 | output [7:0] out_lo 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/rotate100/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | always @(posedge clk) begin 4 | if (load) 5 | q <= data; 6 | else if (ena == 2'h1) 7 | q <= {q[0], q[99:1]}; 8 | else if (ena == 2'h2) 9 | q <= {q[98:0], q[99]}; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/timer/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | logic [9:0] count_value; 2 | 3 | always @(posedge clk) 4 | if(load) count_value <= data; 5 | else if(count_value != 0) count_value <= count_value - 1; 6 | 7 | assign tc = count_value == 0; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/rotate100/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | always @(posedge clk) begin 4 | if (load) 5 | q <= data; 6 | else if (ena == 2'h1) 7 | q <= {q[0], q[99:1]}; 8 | else if (ena == 2'h2) 9 | q <= {q[98:0], q[99]}; 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/timer/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | logic [9:0] count_value; 2 | 3 | always @(posedge clk) 4 | if(load) count_value <= data; 5 | else if(count_value != 0) count_value <= count_value - 1; 6 | 7 | assign tc = count_value == 0; 8 | 9 | endmodule 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gates/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_and = a&b; 3 | assign out_or = a|b; 4 | assign out_xor = a^b; 5 | assign out_nand = ~(a&b); 6 | assign out_nor = ~(a|b); 7 | assign out_xnor = a^~b; 8 | assign out_anotb = a & ~b; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mt2015_eq2/mt2015_eq2.sv: -------------------------------------------------------------------------------- 1 | // Create a circuit that has two 2-bit inputs A[1:0] and B[1:0], and produces an output z. The value of z should be 1 if A = B, otherwise z should be 0. 2 | 3 | module top_module( 4 | input [1:0] A, 5 | input [1:0] B, 6 | output z); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/gates/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out_and = a&b; 3 | assign out_or = a|b; 4 | assign out_xor = a^b; 5 | assign out_nand = ~(a&b); 6 | assign out_nor = ~(a|b); 7 | assign out_xnor = a^~b; 8 | assign out_anotb = a & ~b; 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff16e/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (!resetn) 4 | q <= 0; 5 | else begin 6 | if (byteena[0]) 7 | q[7:0] <= d[7:0]; 8 | if (byteena[1]) 9 | q[15:8] <= d[15:8]; 10 | end 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8r/dff8r.sv: -------------------------------------------------------------------------------- 1 | // Create 8 D flip-flops with active high synchronous reset setting the output to zero. All DFFs should be triggered by the positive edge of clk. 2 | 3 | module top_module( 4 | input clk, 5 | input [7:0] d, 6 | input reset, 7 | output reg [7:0] q); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/count10/count10.sv: -------------------------------------------------------------------------------- 1 | // Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [3:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff16e/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (!resetn) 4 | q <= 0; 5 | else begin 6 | if (byteena[0]) 7 | q[7:0] <= d[7:0]; 8 | if (byteena[1]) 9 | q[15:8] <= d[15:8]; 10 | end 11 | end 12 | 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8ar/dff8ar.sv: -------------------------------------------------------------------------------- 1 | // Create 8 D flip-flops with active high asynchronous reset. The output should be reset to 0. All DFFs should be triggered by the positive edge of clk. 2 | 3 | module top_module( 4 | input clk, 5 | input [7:0] d, 6 | input areset, 7 | output reg [7:0] q); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_nolatches/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | {up, left, down, right} = 0; 4 | case (scancode) 5 | 16'he06b: left = 1; 6 | 16'he072: down = 1; 7 | 16'he074: right = 1; 8 | 16'he075: up = 1; 9 | endcase 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/circuit6/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) 3 | case (a) 4 | 0: q = 4658; 5 | 1: q = 44768; 6 | 2: q = 10196; 7 | 3: q = 23054; 8 | 4: q = 8294; 9 | 5: q = 25806; 10 | 6: q = 50470; 11 | 7: q = 12057; 12 | endcase 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/count15/count15.sv: -------------------------------------------------------------------------------- 1 | // Build a 4-bit binary counter that counts from 0 through 15, inclusive, with a period of 16. The reset input is active high synchronous, and should reset the counter to 0. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [3:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit6/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) 3 | case (a) 4 | 0: q = 4658; 5 | 1: q = 44768; 6 | 2: q = 10196; 7 | 3: q = 23054; 8 | 4: q = 8294; 9 | 5: q = 25806; 10 | 6: q = 50470; 11 | 7: q = 12057; 12 | endcase 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/always_nolatches/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | {up, left, down, right} = 0; 4 | case (scancode) 5 | 16'he06b: left = 1; 6 | 16'he072: down = 1; 7 | 16'he074: right = 1; 8 | 16'he075: up = 1; 9 | endcase 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_count1k/review2015_count1k.sv: -------------------------------------------------------------------------------- 1 | // Build a counter that counts from 0 to 999, inclusive, with a period of 1000 cycles. The reset input is active high synchronous, and should reset the counter to 0. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [9:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff8p/dff8p.sv: -------------------------------------------------------------------------------- 1 | // Create 8 D flip-flops with active high synchronous reset. The flip-flops must be reset to 0x34 rather than zero. All DFFs should be triggered by the negative edge of clk. 2 | 3 | module top_module( 4 | input clk, 5 | input [7:0] d, 6 | input reset, 7 | output reg [7:0] q); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/lfsr5/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | logic [4:0] q_next; 3 | always @(q) begin 4 | q_next = q[4:1]; 5 | q_next[4] = q[0]; 6 | q_next[2] ^= q[0]; 7 | end 8 | 9 | always @(posedge clk) begin 10 | if (reset) 11 | q <= 5'h1; 12 | else 13 | q <= q_next; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4f/m2014_q4f.sv: -------------------------------------------------------------------------------- 1 | // Implement the following circuit in Verilog. Two inputs (in1 and in2) go to an AND gate, but the in2 input to the AND gate has a bubble. The output of the AND gate is connected to 'out'. 2 | 3 | module top_module ( 4 | input in1, 5 | input in2, 6 | output logic out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/wire4/wire4.sv: -------------------------------------------------------------------------------- 1 | // Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections: a -> w 2 | // ; b -> x; b -> y; c -> z. 3 | 4 | module top_module ( 5 | input a, 6 | input b, 7 | input c, 8 | output w, 9 | output x, 10 | output y, 11 | output z ); 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/conditional/conditional.sv: -------------------------------------------------------------------------------- 1 | // Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). 2 | 3 | module top_module ( 4 | input [7:0] a, 5 | input [7:0] b, 6 | input [7:0] c, 7 | input [7:0] d, 8 | output reg [7:0] min 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/lfsr5/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | logic [4:0] q_next; 3 | always @(q) begin 4 | q_next = q[4:1]; 5 | q_next[4] = q[0]; 6 | q_next[2] ^= q[0]; 7 | end 8 | 9 | always @(posedge clk) begin 10 | if (reset) 11 | q <= 5'h1; 12 | else 13 | q <= q_next; 14 | end 15 | endmodule 16 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap1/kmap1.sv: -------------------------------------------------------------------------------- 1 | // Implement the circuit described by the Karnaugh map below. 2 | // a 3 | // bc 0 1 4 | // 00 | 0 | 1 | 5 | // 01 | 1 | 1 | 6 | // 11 | 1 | 1 | 7 | // 10 | 1 | 1 | 8 | 9 | 10 | module top_module( 11 | input a, 12 | input b, 13 | input c, 14 | output out 15 | ); 16 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_case/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case (sel) 4 | 3'h0: out = data0; 5 | 3'h1: out = data1; 6 | 3'h2: out = data2; 7 | 3'h3: out = data3; 8 | 3'h4: out = data4; 9 | 3'h5: out = data5; 10 | default: out = 4'b0; 11 | endcase 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux256to1/mux256to1.sv: -------------------------------------------------------------------------------- 1 | // Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc. 2 | 3 | module top_module ( 4 | input [255:0] in, 5 | input [7:0] sel, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/always_case/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case (sel) 4 | 3'h0: out = data0; 5 | 3'h1: out = data1; 6 | 3'h2: out = data2; 7 | 3'h3: out = data3; 8 | 3'h4: out = data4; 9 | 3'h5: out = data5; 10 | default: out = 4'b0; 11 | endcase 12 | end 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/ece241_2014_q1c/ece241_2014_q1c.sv: -------------------------------------------------------------------------------- 1 | // Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred. 2 | 3 | module top_module ( 4 | input [7:0] a, 5 | input [7:0] b, 6 | output [7:0] s, 7 | output overflow 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/edgedetect2/edgedetect2.sv: -------------------------------------------------------------------------------- 1 | // For each bit in an 8-bit vector, detect when the input signal changes from one clock cycle to the next (detect any edge). The output bit should be set the cycle after a 0 to 1 transition occurs. 2 | 3 | module top_module( 4 | input clk, 5 | input [7:0] in, 6 | output reg [7:0] anyedge); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q1c/ece241_2014_q1c.sv: -------------------------------------------------------------------------------- 1 | // Assume that you have two 8-bit 2's complement numbers, a[7:0] and b[7:0]. These numbers are added to produce s[7:0]. Also compute whether a (signed) overflow has occurred. 2 | 3 | module top_module ( 4 | input [7:0] a, 5 | input [7:0] b, 6 | output [7:0] s, 7 | output overflow 8 | ); 9 | -------------------------------------------------------------------------------- /autochip_scripts/tools.py: -------------------------------------------------------------------------------- 1 | from abc import ABC, abstractmethod 2 | import sys 3 | 4 | class AbstractCompilationTool(ABC): 5 | """Abstract Compilation Tool.""" 6 | 7 | def __init__(self): 8 | pass 9 | 10 | @abstractmethod 11 | def compile(self, file: str): 12 | """Compile the given file.""" 13 | pass 14 | 15 | class 16 | 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_if2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | if (cpu_overheated) 4 | shut_off_computer = 1; 5 | else 6 | shut_off_computer = 0; 7 | end 8 | 9 | always @(*) begin 10 | if (~arrived) 11 | keep_driving = !gas_tank_empty; 12 | else 13 | keep_driving = 1'b0; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/always_if2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | if (cpu_overheated) 4 | shut_off_computer = 1; 5 | else 6 | shut_off_computer = 0; 7 | end 8 | 9 | always @(*) begin 10 | if (~arrived) 11 | keep_driving = !gas_tank_empty; 12 | else 13 | keep_driving = 1'b0; 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/edgedetect/edgedetect.sv: -------------------------------------------------------------------------------- 1 | // For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs. 2 | 3 | module top_module( 4 | input clk, 5 | input [7:0] in, 6 | output reg [7:0] pedge); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux256to1v/mux256to1v.sv: -------------------------------------------------------------------------------- 1 | // Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc. 2 | 3 | module top_module ( 4 | input [1023:0] in, 5 | input [7:0] sel, 6 | output [3:0] out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4g/m2014_q4g.sv: -------------------------------------------------------------------------------- 1 | // Implement in Verilog the following circuit: A two-input XNOR (connected to 'in1' and 'in2) has an output connected to the input of a two-input XOR. The second input of the XOR is 'in3.' The output of the XOR is 'out'. 2 | 3 | module top_module ( 4 | input in1, 5 | input in2, 6 | input in3, 7 | output logic out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux9to1v/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | out = '1; 4 | case (sel) 5 | 4'h0: out = a; 6 | 4'h1: out = b; 7 | 4'h2: out = c; 8 | 4'h3: out = d; 9 | 4'h4: out = e; 10 | 4'h5: out = f; 11 | 4'h6: out = g; 12 | 4'h7: out = h; 13 | 4'h8: out = i; 14 | endcase 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux9to1v/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | out = '1; 4 | case (sel) 5 | 4'h0: out = a; 6 | 4'h1: out = b; 7 | 4'h2: out = c; 8 | 4'h3: out = d; 9 | 4'h4: out = e; 10 | 4'h5: out = f; 11 | 4'h6: out = g; 12 | 4'h7: out = h; 13 | 4'h8: out = i; 14 | endcase 15 | end 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/lfsr32/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | logic [31:0] q_next; 3 | always@(q) begin 4 | q_next = q[31:1]; 5 | q_next[31] = q[0]; 6 | q_next[21] ^= q[0]; 7 | q_next[1] ^= q[0]; 8 | q_next[0] ^= q[0]; 9 | end 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | q <= 32'h1; 14 | else 15 | q <= q_next; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/review2015_fsmseq/review2015_fsmseq.sv: -------------------------------------------------------------------------------- 1 | // Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Reset is active high synchronous. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | input data, 7 | output start_shifting); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q7/ece241_2013_q7.sv: -------------------------------------------------------------------------------- 1 | // A JK flip-flop has the below truth table. Note: Qold is the output of the flip-flop before the positive clock edge. 2 | // J | K | Q 3 | // 0 | 0 | Qold 4 | // 0 | 1 | 0 5 | // 1 | 0 | 1 6 | // 1 | 1 | ~Qold 7 | 8 | module top_module ( 9 | input clk, 10 | input j, 11 | input k, 12 | output reg Q 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3comb/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | 3 | always_comb begin 4 | case (state) 5 | A: next_state = in ? B : A; 6 | B: next_state = in ? B : C; 7 | C: next_state = in ? D : A; 8 | D: next_state = in ? B : C; 9 | endcase 10 | end 11 | 12 | assign out = (state==D); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_fsmseq/review2015_fsmseq.sv: -------------------------------------------------------------------------------- 1 | // Build a finite-state machine that searches for the sequence 1101 in an input bit stream. When the sequence is found, it should set start_shifting to 1, forever, until reset. Reset is active high synchronous. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | input data, 7 | output start_shifting); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm3comb/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | 3 | always_comb begin 4 | case (state) 5 | A: next_state = in ? B : A; 6 | B: next_state = in ? B : C; 7 | C: next_state = in ? D : A; 8 | D: next_state = in ? B : C; 9 | endcase 10 | end 11 | 12 | assign out = (state==D); 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2012_q1g/2012_q1g.sv: -------------------------------------------------------------------------------- 1 | // Consider the function f shown in the Karnaugh map below. Implement this function. 2 | // x[1]x[2] 3 | // x[3]x[4] 00 01 11 10 4 | // 00 | 1 | 0 | 0 | 1 | 5 | // 01 | 0 | 0 | 0 | 0 | 6 | // 11 | 1 | 1 | 1 | 0 | 7 | // 10 | 1 | 1 | 0 | 1 | 8 | 9 | module top_module ( 10 | input [4:1] x, 11 | output logic f 12 | ); 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/edgecapture/edgecapture.sv: -------------------------------------------------------------------------------- 1 | // For each bit in a 32-bit vector, capture when the input signal changes from 1 in one clock cycle to 0 the next. "Capture" means that the output will remain 1 until the register is reset (active high synchronous reset). 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | input [31:0] in, 7 | output reg [31:0] out); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap2/kmap2.sv: -------------------------------------------------------------------------------- 1 | // Implement the circuit described by the Karnaugh map below. 2 | 3 | // ab 4 | // cd 00 01 11 10 5 | // 00 | 1 | 1 | 0 | 1 | 6 | // 01 | 1 | 0 | 0 | 1 | 7 | // 11 | 0 | 1 | 1 | 1 | 8 | // 10 | 1 | 1 | 0 | 0 | 9 | 10 | module top_module ( 11 | input a, 12 | input b, 13 | input c, 14 | input d, 15 | output out 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/lfsr32/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | logic [31:0] q_next; 3 | always@(q) begin 4 | q_next = q[31:1]; 5 | q_next[31] = q[0]; 6 | q_next[21] ^= q[0]; 7 | q_next[1] ^= q[0]; 8 | q_next[0] ^= q[0]; 9 | end 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | q <= 32'h1; 14 | else 15 | q <= q_next; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q4d/m2014_q4d.sv: -------------------------------------------------------------------------------- 1 | // Implement in Verilog the following circuit: A D flip-flop takes as input the output of a two-input XOR. The flip-flop is positive edge triggered by clk, but there is no reset. The XOR takes as input 'in' along with the output 'out' of the flip-flop. 2 | 3 | module top_module ( 4 | input clk, 5 | input in, 6 | output logic out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector0/vector0.sv: -------------------------------------------------------------------------------- 1 | // Build a circuit that has one 3-bit input, then outputs the same vector, and also splits it into three separate 1-bit outputs. Connect output o0 to the input vector's position 0, o1 to position 1, etc. 2 | 3 | module top_module( 4 | input [2:0] vec, 5 | output [2:0] outv, 6 | output o2, 7 | output o1, 8 | output o0 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/lfsr32/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | logic [31:0] q_next; 3 | always@(q) begin 4 | q_next = q[31:1]; 5 | q_next[31] = q[0]; 6 | q_next[21] ^= q[0]; 7 | q_next[1] ^= q[0]; 8 | q_next[0] ^= q[0]; 9 | end 10 | 11 | always @(posedge clk) begin 12 | if (reset) 13 | q <= 32'h1; 14 | else 15 | q <= q_next; 16 | end 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap4/kmap4.sv: -------------------------------------------------------------------------------- 1 | // Implement the circuit described by the Karnaugh map below. 2 | 3 | // ab 4 | // cd 00 01 11 10 5 | // 00 | 0 | 1 | 0 | 1 | 6 | // 01 | 1 | 0 | 1 | 0 | 7 | // 11 | 0 | 1 | 0 | 1 | 8 | // 10 | 1 | 0 | 1 | 0 | 9 | 10 | module top_module ( 11 | input a, 12 | input b, 13 | input c, 14 | input d, 15 | output reg out 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/history_shift/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | always@(posedge clk, posedge areset) 2 | if (areset) begin 3 | predict_history = 0; 4 | end else begin 5 | if (train_mispredicted) 6 | predict_history <= {train_history, train_taken}; 7 | else if (predict_valid) 8 | predict_history <= {predict_history, predict_taken}; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/shift18/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | always @(posedge clk) begin 4 | if (load) 5 | q <= data; 6 | else if (ena) case (amount) 7 | 2'b00: q <= {q[62:0], 1'b0}; 8 | 2'b01: q <= {q[55:0], 8'b0}; 9 | 2'b10: q <= {q[63], q[63:1]}; 10 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; 11 | default: q <= 64'hx; 12 | endcase 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/history_shift/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | always@(posedge clk, posedge areset) 2 | if (areset) begin 3 | predict_history = 0; 4 | end else begin 5 | if (train_mispredicted) 6 | predict_history <= {train_history, train_taken}; 7 | else if (predict_valid) 8 | predict_history <= {predict_history, predict_taken}; 9 | end 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/shift18/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | 3 | always @(posedge clk) begin 4 | if (load) 5 | q <= data; 6 | else if (ena) case (amount) 7 | 2'b00: q <= {q[62:0], 1'b0}; 8 | 2'b01: q <= {q[55:0], 8'b0}; 9 | 2'b10: q <= {q[63], q[63:1]}; 10 | 2'b11: q <= {{8{q[63]}}, q[63:8]}; 11 | default: q <= 64'hx; 12 | endcase 13 | end 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3onehot/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | 3 | assign next_state[A] = (state[A] | state[C]) & ~in; 4 | assign next_state[B] = (state[A] | state[B] | state[D]) & in; 5 | assign next_state[C] = (state[B] | state[D]) & ~in; 6 | assign next_state[D] = state[C] & in; 7 | 8 | assign out = (state[D]); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vectorr/vectorr.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a 8-bit unidirectional data port. It takes an 8-bit input in, and outputs an 8-bit signal out. The output of the module is assigned to out based on the value of in. If in = {a,b,c,d,e,f,g,h}, then out = {h,g,f,e,d,c,b,a}. 2 | 3 | 4 | 5 | 6 | module top_module ( 7 | input [7:0] in, 8 | output [7:0] out 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gates4/gates4.sv: -------------------------------------------------------------------------------- 1 | // Build a combinational circuit with four inputs, in[3:0]. There are 3 outputs: 2 | // (1) out_and: output of a 4-input AND gate. 3 | // (2) out_or: output of a 4-input OR gate. 4 | // (3) out_xor: output of a 4-input XOR gate. 5 | 6 | 7 | module top_module ( 8 | input [3:0] in, 9 | output out_and, 10 | output out_or, 11 | output out_xor 12 | ); 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm3onehot/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | 3 | assign next_state[A] = (state[A] | state[C]) & ~in; 4 | assign next_state[B] = (state[A] | state[B] | state[D]) & in; 5 | assign next_state[C] = (state[B] | state[D]) & ~in; 6 | assign next_state[D] = state[C] & in; 7 | 8 | assign out = (state[D]); 9 | 10 | endmodule 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/countbcd/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1}; 3 | assign ena = enable[3:1]; 4 | always @(posedge clk) 5 | for (int i=0;i<4;i++) begin 6 | if (reset || (q[i*4 +:4] == 9 && enable[i])) 7 | q[i*4 +:4] <= 0; 8 | else if (enable[i]) 9 | q[i*4 +:4] <= q[i*4 +:4]+1; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_if/always_if.sv: -------------------------------------------------------------------------------- 1 | // Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input sel_b1, 7 | input sel_b2, 8 | output out_assign, 9 | output reg out_always 10 | ); 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/countbcd/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | wire [3:0] enable = { q[11:0]==12'h999, q[7:0]==8'h99, q[3:0] == 4'h9, 1'b1}; 3 | assign ena = enable[3:1]; 4 | always @(posedge clk) 5 | for (int i=0;i<4;i++) begin 6 | if (reset || (q[i*4 +:4] == 9 && enable[i])) 7 | q[i*4 +:4] <= 0; 8 | else if (enable[i]) 9 | q[i*4 +:4] <= q[i*4 +:4]+1; 10 | end 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dualedge/dualedge.sv: -------------------------------------------------------------------------------- 1 | // A dual-edge triggered flip-flop is triggered on both edges of the clock. However, FPGAs don't have dual-edge triggered flip-flops, and always @(posedge clk or negedge clk) is not accepted as a legal sensitivity list. Build a circuit that functionally behaves like a dual-edge triggered flip-flop. 2 | 3 | module top_module( 4 | input clk, 5 | input d, 6 | output reg q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q5b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter A=0,B=1; 3 | reg state; 4 | always @(posedge clk, posedge areset) begin 5 | if (areset) 6 | state <= A; 7 | else begin 8 | case (state) 9 | A: state <= x ? B : A; 10 | B: state <= B; 11 | endcase 12 | end 13 | end 14 | 15 | assign z = (state == A && x==1) | (state == B && x==0); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2014_q5b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter A=0,B=1; 3 | reg state; 4 | always @(posedge clk, posedge areset) begin 5 | if (areset) 6 | state <= A; 7 | else begin 8 | case (state) 9 | A: state <= x ? B : A; 10 | B: state <= B; 11 | endcase 12 | end 13 | end 14 | 15 | assign z = (state == A && x==1) | (state == B && x==0); 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/counter_2bc/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | always @(posedge clk, posedge areset) begin 2 | if (areset) 3 | state <= 1; 4 | else if (train_valid) begin 5 | if(state < 3 && train_taken) 6 | state <= state + 1; 7 | else if(state > 0 && !train_taken) 8 | state <= state - 1; 9 | end 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gates100/gates100.sv: -------------------------------------------------------------------------------- 1 | // Build a combinational circuit with 100 inputs, in[99:0]. There are 3 outputs: 2 | // (1) out_and: output of a 100-input AND gate. 3 | // (2) out_or: output of a 100-input OR gate. 4 | // (3) out_xor: output of a 100-input XOR gate. 5 | 6 | 7 | 8 | module top_module ( 9 | input [99:0] in, 10 | output out_and, 11 | output out_or, 12 | output out_xor 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/truthtable1/truthtable1.sv: -------------------------------------------------------------------------------- 1 | // Create a combinational circuit that implements the truth table. 2 | 3 | // x3 | x2 | x1 | f 4 | // 0 | 0 | 0 | 0 5 | // 0 | 0 | 1 | 0 6 | // 0 | 1 | 0 | 1 7 | // 0 | 1 | 1 | 1 8 | // 1 | 0 | 0 | 0 9 | // 1 | 0 | 1 | 1 10 | // 1 | 1 | 0 | 0 11 | // 1 | 1 | 1 | 1 12 | 13 | module top_module ( 14 | input x3, 15 | input x2, 16 | input x1, 17 | output f 18 | ); 19 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/rule110/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (load) 4 | q <= data; 5 | else begin 6 | q <= 7 | ~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) | 8 | (~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) | 9 | (q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) ) 10 | ; 11 | end 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/counter_2bc/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | always @(posedge clk, posedge areset) begin 2 | if (areset) 3 | state <= 1; 4 | else if (train_valid) begin 5 | if(state < 3 && train_taken) 6 | state <= state + 1; 7 | else if(state > 0 && !train_taken) 8 | state <= state - 1; 9 | end 10 | end 11 | endmodule 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/rule110/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(posedge clk) begin 3 | if (load) 4 | q <= data; 5 | else begin 6 | q <= 7 | ~((q[$bits(q)-1:1] & q[$bits(q)-1:0] & {q[$bits(q)-2:0], 1'b0}) | 8 | (~q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) | 9 | (q[$bits(q)-1:1] & ~q[$bits(q)-1:0] & ~{q[$bits(q)-2:0], 1'b0}) ) 10 | ; 11 | end 12 | end 13 | endmodule 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q5a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter A=0,B=1,C=2; 3 | reg [1:0] state; 4 | always @(posedge clk, posedge areset) begin 5 | if (areset) 6 | state <= A; 7 | else begin 8 | case (state) 9 | A: state <= x ? C : A; 10 | B: state <= x ? B : C; 11 | C: state <= x ? B : C; 12 | endcase 13 | end 14 | end 15 | 16 | assign z = (state == C); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm2s/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = j ? B : A; 8 | B: next = k ? A : B; 9 | endcase 10 | end 11 | 12 | always @(posedge clk) begin 13 | if (reset) state <= A; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/reduction/reduction.sv: -------------------------------------------------------------------------------- 1 | // Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits. 2 | 3 | module top_module ( 4 | input [7:0] in, 5 | output parity 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/bugs_mux2/bugs_mux2.sv: -------------------------------------------------------------------------------- 1 | // Find the bug and fix this 8-bit wide 2-to-1 mux. 2 | 3 | // module top_module ( 4 | // input sel, 5 | // input [7:0] a, 6 | // input [7:0] b, 7 | // output out ); 8 | 9 | // assign out = (~sel & a) | (sel & b); 10 | 11 | // endmodule 12 | 13 | module top_module ( 14 | input sel, 15 | input [7:0] a, 16 | input [7:0] b, 17 | output reg [7:0] out 18 | ); 19 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm1/fsm1.sv: -------------------------------------------------------------------------------- 1 | // Consider the follow Moore machine with the diagram described below: 2 | 3 | // B (1) --0--> A 4 | // B (1) --1--> B 5 | // A (0) --0--> B 6 | // A (0) --1--> A 7 | 8 | // Write Verilog implementing this state machine. It should asynchronously reset into state B if reset if high. 9 | 10 | module top_module ( 11 | input clk, 12 | input in, 13 | input areset, 14 | output out 15 | ); 16 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm1s/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? A : B; 8 | B: next = in ? B : A; 9 | endcase 10 | end 11 | 12 | always @(posedge clk) begin 13 | if (reset) state <= B; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2014_q5a/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter A=0,B=1,C=2; 3 | reg [1:0] state; 4 | always @(posedge clk, posedge areset) begin 5 | if (areset) 6 | state <= A; 7 | else begin 8 | case (state) 9 | A: state <= x ? C : A; 10 | B: state <= x ? B : C; 11 | C: state <= x ? B : C; 12 | endcase 13 | end 14 | end 15 | 16 | assign z = (state == C); 17 | 18 | endmodule 19 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm1s/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? A : B; 8 | B: next = in ? B : A; 9 | endcase 10 | end 11 | 12 | always @(posedge clk) begin 13 | if (reset) state <= B; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm2s/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = j ? B : A; 8 | B: next = k ? A : B; 9 | endcase 10 | end 11 | 12 | always @(posedge clk) begin 13 | if (reset) state <= A; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_casez/always_casez.sv: -------------------------------------------------------------------------------- 1 | // Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first (least significant) bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high. 2 | 3 | module top_module ( 4 | input [7:0] in, 5 | output reg [2:0] pos 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_casez/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | casez (in) 4 | default : pos = 2'h0; 5 | 8'bzzzzzzz1: pos = 3'h0; 6 | 8'bzzzzzz1z: pos = 3'h1; 7 | 8'bzzzzz1zz: pos = 3'h2; 8 | 8'bzzzz1zzz: pos = 3'h3; 9 | 8'bzzz1zzzz: pos = 3'h4; 10 | 8'bzz1zzzzz: pos = 3'h5; 11 | 8'bz1zzzzzz: pos = 3'h6; 12 | 8'b1zzzzzzz: pos = 3'h7; 13 | endcase 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/always_casez/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | casez (in) 4 | default : pos = 2'h0; 5 | 8'bzzzzzzz1: pos = 3'h0; 6 | 8'bzzzzzz1z: pos = 3'h1; 7 | 8'bzzzzz1zz: pos = 3'h2; 8 | 8'bzzzz1zzz: pos = 3'h3; 9 | 8'bzzz1zzzz: pos = 3'h4; 10 | 8'bzz1zzzzz: pos = 3'h5; 11 | 8'bz1zzzzzz: pos = 3'h6; 12 | 8'b1zzzzzzz: pos = 3'h7; 13 | endcase 14 | end 15 | 16 | endmodule 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm1s/fsm1s.sv: -------------------------------------------------------------------------------- 1 | // This is a Moore state machine with two states, one input, and one output. Implement this state machine in Verilog. The reset state is B and reset is active-high synchronous. 2 | 3 | // B (out=1) --in=0--> A 4 | // B (out=1) --in=1--> B 5 | // A (out=0) --in=0--> B 6 | // A (out=0) --in=1--> A 7 | 8 | module top_module ( 9 | input clk, 10 | input in, 11 | input reset, 12 | output out 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit9/circuit9.sv: -------------------------------------------------------------------------------- 1 | // The top Verilog module is a Mealy machine with two inputs (clk and a) and one output (q). 2 | The output q is a 3-bit value. 3 | The input a is an activity signal. 4 | When a is 1, q is set to 4. 5 | When a is 0 and q is 6, q is set to 0. 6 | When a is 0 and q is not 6, q is increased by 1. 7 | 8 | 9 | module top_module ( 10 | input clk, 11 | input a, 12 | output reg [2:0] q 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dualedge/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | /*always @(posedge clk, negedge clk) begin 3 | q <= d; 4 | end*/ 5 | 6 | reg qp, qn; 7 | always @(posedge clk) 8 | qp <= d; 9 | always @(negedge clk) 10 | qn <= d; 11 | // assign q = clk ? qp : qn; // This causes q to change too early when clk changes. Need delay by delta cycle 12 | always @(*) 13 | q <= clk ? qp : qn; 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? A : B; 8 | B: next = in ? B : A; 9 | endcase 10 | end 11 | 12 | always @(posedge clk, posedge areset) begin 13 | if (areset) state <= B; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = j ? B : A; 8 | B: next = k ? A : B; 9 | endcase 10 | end 11 | 12 | always @(posedge clk, posedge areset) begin 13 | if (areset) state <= A; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dualedge/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | /*always @(posedge clk, negedge clk) begin 3 | q <= d; 4 | end*/ 5 | 6 | reg qp, qn; 7 | always @(posedge clk) 8 | qp <= d; 9 | always @(negedge clk) 10 | qn <= d; 11 | // assign q = clk ? qp : qn; // This causes q to change too early when clk changes. Need delay by delta cycle 12 | always @(*) 13 | q <= clk ? qp : qn; 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? A : B; 8 | B: next = in ? B : A; 9 | endcase 10 | end 11 | 12 | always @(posedge clk, posedge areset) begin 13 | if (areset) state <= B; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = j ? B : A; 8 | B: next = k ? A : B; 9 | endcase 10 | end 11 | 12 | always @(posedge clk, posedge areset) begin 13 | if (areset) state <= A; 14 | else state <= next; 15 | end 16 | 17 | assign out = (state==B); 18 | 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_case/always_case.sv: -------------------------------------------------------------------------------- 1 | // Create a 6-to-1 multiplexer. When sel is between 0 and 5, choose the corresponding data input. Otherwise, output 0. The data inputs and outputs are all 4 bits wide. 2 | 3 | module top_module ( 4 | input [2:0] sel, 5 | input [3:0] data0, 6 | input [3:0] data1, 7 | input [3:0] data2, 8 | input [3:0] data3, 9 | input [3:0] data4, 10 | input [3:0] data5, 11 | output reg [3:0] out 12 | ); 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/countbcd/countbcd.sv: -------------------------------------------------------------------------------- 1 | // Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented. Include a synchronous active-high reset. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output [3:1] ena, 7 | output reg [15:0] q); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q5b/ece241_2014_q5b.sv: -------------------------------------------------------------------------------- 1 | // The following diagram is a Mealy machine implementation of the 2's complementer. Implement in Verilog using one-hot encoding. Resets into state A and reset is asynchronous active-high. 2 | 3 | // A --x=0 (z=0)--> A 4 | // A --x=1 (z=1)--> B 5 | // B --x=0 (z=1)--> B 6 | // B --x=1 (z=0)--> B 7 | 8 | module top_module ( 9 | input clk, 10 | input areset, 11 | input x, 12 | output z 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q6c/m2014_q6c.sv: -------------------------------------------------------------------------------- 1 | // This module is used to generate two outputs, Y2 and Y4, based on the inputs y and w. Y2 is generated by taking the logical AND of the first bit of the input y and the logical NOT of the input w. Y4 is generated by taking the logical AND of the second, third, fifth and sixth bits of the input y and the input w. 2 | 3 | module top_module ( 4 | input [6:1] y, 5 | input w, 6 | output Y2, 7 | output Y4 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/countbcd/countbcd.sv: -------------------------------------------------------------------------------- 1 | // Build a 4-digit BCD (binary-coded decimal) counter. Each decimal digit is encoded using 4 bits: q[3:0] is the ones digit, q[7:4] is the tens digit, etc. For digits [3:1], also output an enable signal indicating when each of the upper three digits should be incremented. Include a synchronous active-high reset. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output [3:1] ena, 7 | output reg [15:0] q); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm2/fsm2.sv: -------------------------------------------------------------------------------- 1 | // This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-high asynchronous reset to state OFF. 2 | 3 | // OFF (out=0) --j=0--> OFF 4 | // OFF (out=0) --j=1--> ON 5 | // ON (out=1) --k=0--> ON 6 | // ON (out=1) --k=1--> OFF 7 | 8 | module top_module ( 9 | input clk, 10 | input j, 11 | input k, 12 | input areset, 13 | output out 14 | ); 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm2s/fsm2s.sv: -------------------------------------------------------------------------------- 1 | // This is a Moore state machine with two states, two inputs, and one output. Implement this state machine in Verilog. Reset is an active-high synchronous reset to state OFF. 2 | 3 | // OFF (out=0) --j=0--> OFF 4 | // OFF (out=0) --j=1--> ON 5 | // ON (out=1) --k=0--> ON 6 | // ON (out=1) --k=1--> OFF 7 | 8 | module top_module ( 9 | input clk, 10 | input j, 11 | input k, 12 | input reset, 13 | output out 14 | ); 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q3/m2014_q3.sv: -------------------------------------------------------------------------------- 1 | // Consider the function f shown in the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient. Implement this function. 2 | // x[1]x[2] 3 | // x[3]x[4] 00 01 11 10 4 | // 00 | d | 0 | d | d | 5 | // 01 | 0 | d | 1 | 0 | 6 | // 11 | 1 | 1 | d | d | 7 | // 10 | 1 | 1 | 0 | d | 8 | 9 | module top_module ( 10 | input [4:1] x, 11 | output logic f 12 | ); 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector5/vector5.sv: -------------------------------------------------------------------------------- 1 | // Given five 1-bit signals (a, b, c, d, and e), compute all 25 pairwise one-bit comparisons in the 25-bit output vector. The output should be 1 if the two bits being compared are equal. Example: out[24] = ~a ^ a; out[23] = ~a ^ b; out[22] = ~a ^ c; ... out[ 1] = ~e ^ d; out[ 0] = ~e ^ e. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input c, 7 | input d, 8 | input e, 9 | output [24:0] out 10 | ); 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap3/kmap3.sv: -------------------------------------------------------------------------------- 1 | // Implement the circuit described by the Karnaugh map below. d is don't-care, which means you may choose to output whatever value is convenient. 2 | 3 | // ab 4 | // cd 01 00 10 11 5 | // 00 | d | 0 | 1 | 1 | 6 | // 01 | 0 | 0 | d | d | 7 | // 11 | 0 | 1 | 1 | 1 | 8 | // 10 | 0 | 1 | 1 | 1 | 9 | 10 | module top_module ( 11 | input a, 12 | input b, 13 | input c, 14 | input d, 15 | output reg out 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_fsmshift/review2015_fsmshift.sv: -------------------------------------------------------------------------------- 1 | // This module is a part of the FSM for controlling the shift register, we want the ability to enable the shift register for exactly 4 clock cycles whenever the proper bit pattern is detected. Whenever the FSM is reset, assert shift_ena for 4 cycles, then 0 forever (until reset). Reset should be active high synchronous. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output shift_ena); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2012_q1g/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case (x) 4 | 4'h0: f = 1; 5 | 4'h1: f = 1; 6 | 4'h2: f = 0; 7 | 4'h3: f = 0; 8 | 4'h4: f = 1; 9 | 4'h5: f = 1; 10 | 4'h6: f = 1; 11 | 4'h7: f = 0; 12 | 4'h8: f = 0; 13 | 4'h9: f = 0; 14 | 4'ha: f = 0; 15 | 4'hb: f = 0; 16 | 4'hc: f = 1; 17 | 4'hd: f = 0; 18 | 4'he: f = 1; 19 | 4'hf: f = 1; 20 | endcase 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q6b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case ({y, w}) 4 | 4'h0: Y2 = 1'b0; 5 | 4'h1: Y2 = 1'b0; 6 | 4'h2: Y2 = 1'b1; 7 | 4'h3: Y2 = 1'b1; 8 | 4'h4: Y2 = 1'b0; 9 | 4'h5: Y2 = 1'b1; 10 | 4'h6: Y2 = 1'b0; 11 | 4'h7: Y2 = 1'b0; 12 | 4'h8: Y2 = 1'b0; 13 | 4'h9: Y2 = 1'b1; 14 | 4'ha: Y2 = 1'b1; 15 | 4'hb: Y2 = 1'b1; 16 | default: Y2 = 1'bx; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2012_q1g/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case (x) 4 | 4'h0: f = 1; 5 | 4'h1: f = 1; 6 | 4'h2: f = 0; 7 | 4'h3: f = 0; 8 | 4'h4: f = 1; 9 | 4'h5: f = 1; 10 | 4'h6: f = 1; 11 | 4'h7: f = 0; 12 | 4'h8: f = 0; 13 | 4'h9: f = 0; 14 | 4'ha: f = 0; 15 | 4'hb: f = 0; 16 | 4'hc: f = 1; 17 | 4'hd: f = 0; 18 | 4'he: f = 1; 19 | 4'hf: f = 1; 20 | endcase 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q6b/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case ({y, w}) 4 | 4'h0: Y2 = 1'b0; 5 | 4'h1: Y2 = 1'b0; 6 | 4'h2: Y2 = 1'b1; 7 | 4'h3: Y2 = 1'b1; 8 | 4'h4: Y2 = 1'b0; 9 | 4'h5: Y2 = 1'b1; 10 | 4'h6: Y2 = 1'b0; 11 | 4'h7: Y2 = 1'b0; 12 | 4'h8: Y2 = 1'b0; 13 | 4'h9: Y2 = 1'b1; 14 | 4'ha: Y2 = 1'b1; 15 | 4'hb: Y2 = 1'b1; 16 | default: Y2 = 1'bx; 17 | endcase 18 | end 19 | 20 | endmodule 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/mux9to1v/mux9to1v.sv: -------------------------------------------------------------------------------- 1 | // Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'. 2 | 3 | module top_module ( 4 | input [15:0] a, 5 | input [15:0] b, 6 | input [15:0] c, 7 | input [15:0] d, 8 | input [15:0] e, 9 | input [15:0] f, 10 | input [15:0] g, 11 | input [15:0] h, 12 | input [15:0] i, 13 | input [3:0] sel, 14 | output logic [15:0] out 15 | ); 16 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/countslow/countslow.sv: -------------------------------------------------------------------------------- 1 | // Build a decade counter that counts from 0 through 9, inclusive, with a period of 10. The reset input is active high synchronous, and should reset the counter to 0. We want to be able to pause the counter rather than always incrementing every clock cycle, so the "slowena" input if high indicates when the counter should increment. 2 | 3 | module top_module( 4 | input clk, 5 | input slowena, 6 | input reset, 7 | output reg [3:0] q); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit2/circuit2.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module implements a logic function that takes four inputs (a, b, c, and d) and produces one output (q). It performs a bitwise XOR operation on the inputs, and then inverts the result. This means that the output will be high when an odd number of inputs are high, and low when an even number of inputs are high. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input c, 7 | input d, 8 | output q 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/7420/7420.sv: -------------------------------------------------------------------------------- 1 | // The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates. 2 | 3 | // Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs. 4 | 5 | module top_module( 6 | input p1a, 7 | input p1b, 8 | input p1c, 9 | input p1d, 10 | output p1y, 11 | input p2a, 12 | input p2b, 13 | input p2c, 14 | input p2d, 15 | output p2y 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q3c/2014_q3c.sv: -------------------------------------------------------------------------------- 1 | // Given the state-assigned table shown below, implement the logic functions Y[0] and z. 2 | // Present state y[2:0] | Next state Y[2:0] x=0, Next state Y[2:0] x=1 | Output z 3 | // 000 | 000, 001 | 0 4 | // 001 | 001, 100 | 0 5 | // 010 | 010, 001 | 0 6 | // 011 | 001, 010 | 1 7 | // 100 | 011, 100 | 1 8 | 9 | 10 | module top_module ( 11 | input clk, 12 | input x, 13 | input [2:0] y, 14 | output reg Y0, 15 | output reg z 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q4a/2014_q4a.sv: -------------------------------------------------------------------------------- 1 | // Consider an n-bit shift register circuit. Inputs E are for enabling shift, R for value to load, L is asserted when it should load, and w is the input to the first stage of the shift register. Write a Verilog module named top_module for one stage of this circuit, including both the flip-flop and multiplexers. 2 | 3 | module top_module ( 4 | input clk, 5 | input w, 6 | input R, 7 | input E, 8 | input L, 9 | output reg Q 10 | ); 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4i/m2014_q4i.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a simple module that has one output port, out. The output port is assigned a value of 0, which is a binary value. This module does not have any other ports or logic, so it simply assigns the output port to a constant value of 0. This module is useful for testing, as it can be used to set the output to a known value in order to test the functionality of other modules. 2 | 3 | module top_module( 4 | output out); 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/7420/7420.sv: -------------------------------------------------------------------------------- 1 | // The 7400-series integrated circuits are a series of digital chips with a few gates each. The 7420 is a chip with two 4-input NAND gates. 2 | 3 | // Create a module with the same functionality as the 7420 chip. It has 8 inputs and 2 outputs. 4 | 5 | module top_module( 6 | input p1a, 7 | input p1b, 8 | input p1c, 9 | input p1d, 10 | output p1y, 11 | input p2a, 12 | input p2b, 13 | input p2c, 14 | input p2d, 15 | output p2y 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case (x) 4 | 4'h0: f = 1'bx; 5 | 4'h1: f = 1'bx; 6 | 4'h2: f = 0; 7 | 4'h3: f = 1'bx; 8 | 4'h4: f = 1; 9 | 4'h5: f = 1'bx; 10 | 4'h6: f = 1; 11 | 4'h7: f = 0; 12 | 4'h8: f = 0; 13 | 4'h9: f = 0; 14 | 4'ha: f = 1'bx; 15 | 4'hb: f = 1; 16 | 4'hc: f = 1; 17 | 4'hd: f = 1'bx; 18 | 4'he: f = 1; 19 | 4'hf: f = 1'bx; 20 | endcase 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vectorgates/vectorgates.sv: -------------------------------------------------------------------------------- 1 | // Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half. 2 | 3 | module top_module( 4 | input [2:0] a, 5 | input [2:0] b, 6 | output [2:0] out_or_bitwise, 7 | output out_or_logical, 8 | output [5:0] out_not 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case (x) 4 | 4'h0: f = 1'bx; 5 | 4'h1: f = 1'bx; 6 | 4'h2: f = 0; 7 | 4'h3: f = 1'bx; 8 | 4'h4: f = 1; 9 | 4'h5: f = 1'bx; 10 | 4'h6: f = 1; 11 | 4'h7: f = 0; 12 | 4'h8: f = 0; 13 | 4'h9: f = 0; 14 | 4'ha: f = 1'bx; 15 | 4'hb: f = 1; 16 | 4'hc: f = 1; 17 | 4'hd: f = 1'bx; 18 | 4'he: f = 1; 19 | 4'hf: f = 1'bx; 20 | endcase 21 | end 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux2to1/mux2to1.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple multiplexer. It takes two inputs, a and b, as well as a selector input, sel. It then outputs the value of either a or b, depending on the value of sel. If sel is 1, the output will be b, and if sel is 0, the output will be a. This module is useful for selecting between two different values, depending on the value of the selector. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input sel, 7 | output out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3s/fsm3s.sv: -------------------------------------------------------------------------------- 1 | // The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous active high reset that resets the FSM to state A. 2 | // State | Next state in=0, Next state in=1 | Output 3 | // A | A, B | 0 4 | // B | C, B | 0 5 | // C | A, D | 0 6 | // D | C, B | 1 7 | 8 | module top_module ( 9 | input clk, 10 | input in, 11 | input reset, 12 | output out 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4g/m2014_q4g.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module takes three inputs, in1, in2, and in3, and produces a single output, out. The output is calculated by performing a bitwise XOR operation on in1 and in2, and then performing a bitwise NOT operation on the result, followed by another bitwise XOR operation with in3. In other words, the output is equal to (NOT (in1 XOR in2)) XOR in3. 2 | 3 | module top_module ( 4 | input in1, 5 | input in2, 6 | input in3, 7 | output logic out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3s/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? B : A; 8 | B: next = in ? B : C; 9 | C: next = in ? D : A; 10 | D: next = in ? B : C; 11 | endcase 12 | end 13 | 14 | always @(posedge clk) begin 15 | if (reset) state <= A; 16 | else state <= next; 17 | end 18 | 19 | assign out = (state==D); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm3s/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? B : A; 8 | B: next = in ? B : C; 9 | C: next = in ? D : A; 10 | D: next = in ? B : C; 11 | endcase 12 | end 13 | 14 | always @(posedge clk) begin 15 | if (reset) state <= A; 16 | else state <= next; 17 | end 18 | 19 | assign out = (state==D); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_q4b/mt2015_q4b.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple logic gate that takes two inputs, x and y, and produces an output, z. The output is the logical negation of the exclusive-or (XOR) of the two inputs. In other words, the output is true if either x or y is true, but not both. If both x and y are true, then the output is false. This module is a basic building block for more complex digital logic circuits. 2 | 3 | module top_module( 4 | input x, 5 | input y, 6 | output z); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux2to1v/mux2to1v.sv: -------------------------------------------------------------------------------- 1 | // This module is a simple multiplexer that takes two inputs a and b, and a select signal sel. Depending on the value of sel, the output out will be either a or b. If sel is 0, then out will be equal to a, and if sel is 1, then out will be equal to b. This module is useful for selecting between two different inputs depending on the value of the select signal. 2 | 3 | module top_module ( 4 | input [99:0] a, 5 | input [99:0] b, 6 | input sel, 7 | output [99:0] out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? B : A; 8 | B: next = in ? B : C; 9 | C: next = in ? D : A; 10 | D: next = in ? B : C; 11 | endcase 12 | end 13 | 14 | always @(posedge clk, posedge areset) begin 15 | if (areset) state <= A; 16 | else state <= next; 17 | end 18 | 19 | assign out = (state==D); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3/fsm3.sv: -------------------------------------------------------------------------------- 1 | // The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a positive edge triggered asynchronous reset that resets the FSM to state A. 2 | 3 | // state | next state in=0, next state in=1 | output 4 | // A | A, B | 0 5 | // B | C, B | 0 6 | // C | A, D | 0 7 | // D | C, B | 1 8 | 9 | module top_module ( 10 | input clk, 11 | input in, 12 | input areset, 13 | output out 14 | ); 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/lemmings1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter WL=0, WR=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | WL: next = bump_left ? WR : WL; 8 | WR: next = bump_right ? WL: WR; 9 | endcase 10 | end 11 | 12 | always @(posedge clk, posedge areset) begin 13 | if (areset) state <= WL; 14 | else state <= next; 15 | end 16 | 17 | assign walk_left = (state==WL); 18 | assign walk_right = (state==WR); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q6/m2014_q6.sv: -------------------------------------------------------------------------------- 1 | // Consider the state machine shown below: 2 | 3 | // A (0) --0--> B 4 | // A (0) --1--> A 5 | // B (0) --0--> C 6 | // B (0) --1--> D 7 | // C (0) --0--> E 8 | // C (0) --1--> D 9 | // D (0) --0--> F 10 | // D (0) --1--> A 11 | // E (1) --0--> E 12 | // E (1) --1--> D 13 | // F (1) --0--> C 14 | // F (1) --1--> D 15 | 16 | // Implement this state machine in Verilog. 17 | 18 | module top_module ( 19 | input clk, 20 | input reset, 21 | input w, 22 | output z 23 | ); 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/lemmings1/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter WL=0, WR=1; 2 | reg state; 3 | reg next; 4 | 5 | always_comb begin 6 | case (state) 7 | WL: next = bump_left ? WR : WL; 8 | WR: next = bump_right ? WL: WR; 9 | endcase 10 | end 11 | 12 | always @(posedge clk, posedge areset) begin 13 | if (areset) state <= WL; 14 | else state <= next; 15 | end 16 | 17 | assign walk_left = (state==WL); 18 | assign walk_right = (state==WR); 19 | 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/reduction/reduction.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple parity checker. It has one 8-bit input port, "in", and one output port, "parity". The output port is assigned to the bitwise XOR of the 8-bit input port. This means that the output will be a single bit that is 1 if the number of 1s in the 8-bit input is odd, and 0 if the number of 1s in the 8-bit input is even. This module can be used to detect errors in 8-bit data. 2 | 3 | module top_module ( 4 | input [7:0] in, 5 | output parity 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ringer/ringer.sv: -------------------------------------------------------------------------------- 1 | // Suppose you are designing a circuit to control a cellphone's ringer and vibration motor. Whenever the phone needs to ring from an incoming call (input ring), your circuit must either turn on the ringer (output ringer = 1) or the motor (output motor = 1), but not both. If the phone is in vibrate mode (input vibrate_mode = 1), turn on the motor. Otherwise, turn on the ringer. 2 | 3 | module top_module( 4 | input ring, 5 | input vibrate_mode, 6 | output ringer, 7 | output motor 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit4/circuit4.sv: -------------------------------------------------------------------------------- 1 | // This top module is a simple logic gate that takes four inputs (a, b, c, and d) and produces one output (q). The output q is the result of a logical OR operation between the inputs b and c. This means that the output q will be high if either input b or input c is high, and it will be low if both inputs b and c are low. The inputs a and d are not used in this module. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input c, 7 | input d, 8 | output q 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | always_comb begin 6 | case (state) 7 | A: next = in ? B : A; 8 | B: next = in ? B : C; 9 | C: next = in ? D : A; 10 | D: next = in ? B : C; 11 | endcase 12 | end 13 | 14 | always @(posedge clk, posedge areset) begin 15 | if (areset) state <= A; 16 | else state <= next; 17 | end 18 | 19 | assign out = (state==D); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q3bfsm/2014_q3bfsm.sv: -------------------------------------------------------------------------------- 1 | // Given the state-assigned table shown below, implement the finite-state machine. Reset should synchronous active high reset the FSM to state 000. 2 | 3 | // Present state y[2:0] | Next state y[2:0] x=0, Next state y[2:0] x=1, Output z 4 | // 000 | 000, 001 | 0 5 | // 001 | 001, 100 | 0 6 | // 010 | 010, 001 | 0 7 | // 011 | 001, 010 | 1 8 | // 100 | 011, 100 | 1 9 | 10 | 11 | module top_module ( 12 | input clk, 13 | input reset, 14 | input x, 15 | output reg z 16 | ); 17 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/alwaysblock2/alwaysblock2.sv: -------------------------------------------------------------------------------- 1 | // Build an XOR gate three ways, using an assign statement (output out_assign), a combinational always block (output out_always_comb), and a clocked always block (output out_always_ff). Note that the clocked always block produces a different circuit from the other two: There is a flip-flop so the output is delayed. 2 | 3 | module top_module( 4 | input clk, 5 | input a, 6 | input b, 7 | output out_assign, 8 | output reg out_always_comb, 9 | output reg out_always_ff 10 | ); 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q8/ece241_2013_q8.sv: -------------------------------------------------------------------------------- 1 | // Implement a Mealy-type finite state machine that recognizes the sequence "101" on an input signal named x. Your FSM should have an output signal, z, that is asserted to logic-1 when the "101" sequence is detected. Your FSM should also have a negative edge triggered asynchronous reset. You may only have 3 states in your state machine. Your FSM should recognize overlapping sequences. 2 | 3 | module top_module ( 4 | input clk, 5 | input aresetn, 6 | input x, 7 | output reg z 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/notgate/notgate.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple combinational circuit that takes an input and produces an inverted output. The input port is named "in" and the output port is named "out". The output is assigned to the inverse of the input, meaning that if the input is 0, the output will be 1, and if the input is 1, the output will be 0. This module does not have any internal logic or state transitions, it simply takes the input and inverts it. 2 | 3 | module top_module( 4 | input in, 5 | output out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q3bfsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3, E=4; 2 | reg [2:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (reset) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = x ? B : A; 12 | B: next = x ? E : B; 13 | C: next = x ? B : C; 14 | D: next = x ? C : B; 15 | E: next = x ? E : D; 16 | default: next = 'x; 17 | endcase 18 | end 19 | 20 | assign z = (state == D) || (state == E); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit3/circuit3.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module implements a logic gate that takes four inputs (a, b, c, and d) and outputs a single bit (q). The logic gate is a bitwise OR of the inputs a and b, and a bitwise OR of the inputs c and d. The output q is a bitwise AND of the two ORs. This means that the output q will be 1 only if at least one of the inputs a and b is 1, and at least one of the inputs c and d is 1. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input c, 7 | input d, 8 | output q 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/review2015_fsmseq/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter S=0, S1=1, S11=2, S110=3, Done=4; 3 | 4 | reg [2:0] state, next; 5 | 6 | always_comb begin 7 | case (state) 8 | S: next = data ? S1: S; 9 | S1: next = data ? S11: S; 10 | S11: next = data ? S11 : S110; 11 | S110: next = data ? Done : S; 12 | Done: next = Done; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) 17 | if (reset) state <= S; 18 | else state <= next; 19 | 20 | assign start_shifting = state == Done; 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_fsmshift/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter B0=0, B1=1, B2=2, B3=3, Done=4; 3 | 4 | reg [2:0] state, next; 5 | 6 | always_comb begin 7 | case (state) 8 | B0: next = B1; 9 | B1: next = B2; 10 | B2: next = B3; 11 | B3: next = Done; 12 | Done: next = Done; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) 17 | if (reset) state <= B0; 18 | else state <= next; 19 | 20 | assign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3); 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2014_q3bfsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3, E=4; 2 | reg [2:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (reset) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = x ? B : A; 12 | B: next = x ? E : B; 13 | C: next = x ? B : C; 14 | D: next = x ? C : B; 15 | E: next = x ? E : D; 16 | default: next = 'x; 17 | endcase 18 | end 19 | 20 | assign z = (state == D) || (state == E); 21 | 22 | endmodule 23 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_fsmshift/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter B0=0, B1=1, B2=2, B3=3, Done=4; 3 | 4 | reg [2:0] state, next; 5 | 6 | always_comb begin 7 | case (state) 8 | B0: next = B1; 9 | B1: next = B2; 10 | B2: next = B3; 11 | B3: next = Done; 12 | Done: next = Done; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) 17 | if (reset) state <= B0; 18 | else state <= next; 19 | 20 | assign shift_ena = (state == B0 || state == B1 || state == B2 || state == B3); 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/zero/zero.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a simple module that assigns the output zero to a value of 0. This module does not have any inputs and is used to assign a constant value to the output. This module is useful when a constant value is needed for a design. For example, if a design requires a signal to be always 0, this module can be used to assign the output zero to 0. This module can also be used to assign a constant value to a signal that is used as an input to another module. 2 | 3 | module top_module( 4 | output zero); 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/dff16e/dff16e.sv: -------------------------------------------------------------------------------- 1 | // Create 16 D flip-flops. It's sometimes useful to only modify parts of a group of flip-flops. The byte-enable inputs control whether each byte of the 16 registers should be written to on that cycle. byteena[1] controls the upper byte d[15:8], while byteena[0] controls the lower byte d[7:0]. resetn is a synchronous, active-low reset. All DFFs should be triggered by the positive edge of clk. 2 | 3 | module top_module( 4 | input clk, 5 | input resetn, 6 | input [1:0] byteena, 7 | input [15:0] d, 8 | output reg [15:0] q); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_fsmseq/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter S=0, S1=1, S11=2, S110=3, Done=4; 3 | 4 | reg [2:0] state, next; 5 | 6 | always_comb begin 7 | case (state) 8 | S: next = data ? S1: S; 9 | S1: next = data ? S11: S; 10 | S11: next = data ? S11 : S110; 11 | S110: next = data ? Done : S; 12 | Done: next = Done; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) 17 | if (reset) state <= S; 18 | else state <= next; 19 | 20 | assign start_shifting = state == Done; 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2012_q2fsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0,B=1,C=2,D=3,E=4,F=5; 2 | reg[2:0] state, next; 3 | 4 | always @(posedge clk) 5 | if (reset) state <= A; 6 | else state <= next; 7 | 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = w ? B : A; 12 | B: next = w ? C : D; 13 | C: next = w ? E : D; 14 | D: next = w ? F : A; 15 | E: next = w ? E : D; 16 | F: next = w ? C : D; 17 | default: next = 'x; 18 | endcase 19 | end 20 | 21 | assign z = (state == E) || (state == F); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4f/m2014_q4f.sv: -------------------------------------------------------------------------------- 1 | // This module takes two input signals, in1 and in2, and produces a single output signal, out. The output signal is the logical AND of in1 and the logical NOT of in2. This means that the output signal will be high (1) only when in1 is high (1) and in2 is low (0). If either in1 or in2 is low (0), the output signal will be low (0). This module is used to perform logical operations on two input signals to produce a single output signal. 2 | 3 | module top_module ( 4 | input in1, 5 | input in2, 6 | output logic out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_fsmseq/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter S=0, S1=1, S11=2, S110=3, Done=4; 3 | 4 | reg [2:0] state, next; 5 | 6 | always_comb begin 7 | case (state) 8 | S: next = data ? S1: S; 9 | S1: next = data ? S11: S; 10 | S11: next = data ? S11 : S110; 11 | S110: next = data ? Done : S; 12 | Done: next = Done; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) 17 | if (reset) state <= S; 18 | else state <= next; 19 | 20 | assign start_shifting = state == Done; 21 | 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector2/vector2.sv: -------------------------------------------------------------------------------- 1 | // This top module is a simple Verilog module that takes an input of 32 bits and outputs the same 32 bits in a different order. The module assigns the output to be the input bits rearranged in 8-bit chunks. The first 8 bits of the input are assigned to the first 8 bits of the output, the second 8 bits of the input are assigned to the second 8 bits of the output, and so on. This module is useful for rearranging the order of bits in a data stream. 2 | 3 | module top_module ( 4 | input [31:0] in, 5 | output [31:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q3c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case ({y[2:0], x}) 4 | 4'h0: Y0 = 0; 5 | 4'h1: Y0 = 1; 6 | 4'h2: Y0 = 1; 7 | 4'h3: Y0 = 0; 8 | 4'h4: Y0 = 0; 9 | 4'h5: Y0 = 1; 10 | 4'h6: Y0 = 1; 11 | 4'h7: Y0 = 0; 12 | 4'h8: Y0 = 1; 13 | 4'h9: Y0 = 0; 14 | default: Y0 = 1'bx; 15 | endcase 16 | 17 | case (y[2:0]) 18 | 3'h0: z = 0; 19 | 3'h1: z = 0; 20 | 3'h2: z = 0; 21 | 3'h3: z = 1; 22 | 3'h4: z = 1; 23 | default: z = 1'bx; 24 | endcase 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_case2/always_case2.sv: -------------------------------------------------------------------------------- 1 | // A priority encoder is a combinational circuit that, when given an input bit vector, outputs the position of the first 1 bit in the vector. For example, a 8-bit priority encoder given the input 8'b10010000 would output 3'd4, because bit[4] is first bit that is high. Build a 4-bit priority encoder. For this problem, if none of the input bits are high (i.e., input is zero), output zero. Note that a 4-bit number has 16 possible combinations. 2 | 3 | module top_module ( 4 | input [3:0] in, 5 | output reg [1:0] pos 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2012_q2fsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0,B=1,C=2,D=3,E=4,F=5; 2 | reg[2:0] state, next; 3 | 4 | always @(posedge clk) 5 | if (reset) state <= A; 6 | else state <= next; 7 | 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = w ? B : A; 12 | B: next = w ? C : D; 13 | C: next = w ? E : D; 14 | D: next = w ? F : A; 15 | E: next = w ? E : D; 16 | F: next = w ? C : D; 17 | default: next = 'x; 18 | endcase 19 | end 20 | 21 | assign z = (state == E) || (state == F); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2014_q3c/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always_comb begin 3 | case ({y[2:0], x}) 4 | 4'h0: Y0 = 0; 5 | 4'h1: Y0 = 1; 6 | 4'h2: Y0 = 1; 7 | 4'h3: Y0 = 0; 8 | 4'h4: Y0 = 0; 9 | 4'h5: Y0 = 1; 10 | 4'h6: Y0 = 1; 11 | 4'h7: Y0 = 0; 12 | 4'h8: Y0 = 1; 13 | 4'h9: Y0 = 0; 14 | default: Y0 = 1'bx; 15 | endcase 16 | 17 | case (y[2:0]) 18 | 3'h0: z = 0; 19 | 3'h1: z = 0; 20 | 3'h2: z = 0; 21 | 3'h3: z = 1; 22 | 3'h4: z = 1; 23 | default: z = 1'bx; 24 | endcase 25 | end 26 | 27 | endmodule 28 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/bugs_mux2/bugs_mux2.sv: -------------------------------------------------------------------------------- 1 | // 2 | The top Verilog module determines the value of output 'out' based on the value of input 'sel' and the data on 'a' and 'b'. 3 | When 'sel' is 0, the value of 'out' is equal to the value of 'b'. 4 | When 'sel' is 1, the value of 'out' is equal to the value of 'a'. 5 | 6 | The port connections of instantiated modules: 7 | sel --> sel 8 | a --> a 9 | b --> b 10 | out <-- out 11 | 12 | 13 | 14 | module top_module ( 15 | input sel, 16 | input [7:0] a, 17 | input [7:0] b, 18 | output reg [7:0] out 19 | ); 20 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/xnorgate/xnorgate.sv: -------------------------------------------------------------------------------- 1 | // This module is a simple two-input, one-output logic circuit. It takes two inputs, a and b, and produces an output, out. The output is the logical negation of the exclusive-or (XOR) of the two inputs. This means that the output will be true (1) when the inputs are not equal and false (0) when the inputs are equal. The module is implemented using a single assign statement, which assigns the output to the logical negation of the XOR of the two inputs. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/lfsr32/lfsr32.sv: -------------------------------------------------------------------------------- 1 | // A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce each bit's next value, while bit positions without a tap shift. Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1. Reset should be active high synchronous, and should reset the output q to 32'h1. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [31:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_fsmonehot/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9; 3 | 4 | assign B3_next = state[B2]; 5 | assign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack; 6 | assign S1_next = state[S]&d; 7 | assign Count_next = state[B3] | state[Count]&~done_counting; 8 | assign Wait_next = state[Count]&done_counting | state[Wait]&~ack; 9 | 10 | assign done = state[Wait]; 11 | assign counting = state[Count]; 12 | assign shift_ena = |state[B3:B0]; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_q4a/mt2015_q4a.sv: -------------------------------------------------------------------------------- 1 | // This top module is a simple combinational logic circuit that takes two inputs, x and y, and produces one output, z. The output z is the result of a logical AND operation between the exclusive OR (XOR) of the two inputs and the first input x. In other words, the output z will be high (1) if either x or y is high (1) but not both, and will be low (0) if both x and y are either high (1) or low (0). This is a useful circuit for implementing a 2-input multiplexer. 2 | 3 | module top_module( 4 | input x, 5 | input y, 6 | output z); 7 | -------------------------------------------------------------------------------- /autochip_scripts/utils.py: -------------------------------------------------------------------------------- 1 | import sys 2 | 3 | # Allows us to log the output of the model to a file if logging is enabled 4 | class LogStdoutToFile: 5 | def __init__(self, filename): 6 | self._filename = filename 7 | self._original_stdout = sys.stdout 8 | 9 | def __enter__(self): 10 | if self._filename: 11 | sys.stdout = open(self._filename, 'w') 12 | return self 13 | 14 | def __exit__(self, exc_type, exc_value, traceback): 15 | if self._filename: 16 | sys.stdout.close() 17 | sys.stdout = self._original_stdout 18 | 19 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/validation_set/fsm_ps2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | wire in3 = in[3]; 6 | 7 | always_comb begin 8 | case (state) 9 | BYTE1: next = in3 ? BYTE2 : BYTE1; 10 | BYTE2: next = BYTE3; 11 | BYTE3: next = DONE; 12 | DONE: next = in3 ? BYTE2 : BYTE1; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) begin 17 | if (reset) state <= BYTE1; 18 | else state <= next; 19 | end 20 | 21 | assign done = (state==DONE); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/always_case2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case (in) 4 | 4'h0: pos = 2'h0; 5 | 4'h1: pos = 2'h0; 6 | 4'h2: pos = 2'h1; 7 | 4'h3: pos = 2'h0; 8 | 4'h4: pos = 2'h2; 9 | 4'h5: pos = 2'h0; 10 | 4'h6: pos = 2'h1; 11 | 4'h7: pos = 2'h0; 12 | 4'h8: pos = 2'h3; 13 | 4'h9: pos = 2'h0; 14 | 4'ha: pos = 2'h1; 15 | 4'hb: pos = 2'h0; 16 | 4'hc: pos = 2'h2; 17 | 4'hd: pos = 2'h0; 18 | 4'he: pos = 2'h1; 19 | 4'hf: pos = 2'h0; 20 | default: pos = 2'b0; 21 | endcase 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/gates/gates.sv: -------------------------------------------------------------------------------- 1 | // Build a combinational circuit with two inputs, a and b. There are 7 outputs, each with a logic gate driving it: 2 | // (1) out_and: a and b 3 | // (2) out_or: a or b 4 | // (3) out_xor: a xor b 5 | // (4) out_nand: a nand b 6 | // (5) out_nor: a nor b 7 | // (6) out_xnor: a xnor b 8 | // (7) out_anotb: a and-not b 9 | 10 | module top_module ( 11 | input a, 12 | input b, 13 | output out_and, 14 | output out_or, 15 | output out_xor, 16 | output out_nand, 17 | output out_nor, 18 | output out_xnor, 19 | output out_anotb 20 | ); 21 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/lfsr32/lfsr32.sv: -------------------------------------------------------------------------------- 1 | // A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce each bit's next value, while bit positions without a tap shift. Build a 32-bit Galois LFSR with taps at bit positions 32, 22, 2, and 1. Reset should be active high synchronous, and should reset the output q to 32'h1. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [31:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q6/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3, E=4, F=5; 2 | reg [2:0] state, next; 3 | 4 | always @(posedge clk) 5 | if (reset) 6 | state <= A; 7 | else 8 | state <= next; 9 | 10 | 11 | always_comb begin 12 | case(state) 13 | A: next = w ? A : B; 14 | B: next = w ? D : C; 15 | C: next = w ? D : E; 16 | D: next = w ? A : F; 17 | E: next = w ? D : E; 18 | F: next = w ? D : C; 19 | default: next = 'x; 20 | endcase 21 | end 22 | 23 | assign z = (state == E || state == F); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/always_case2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case (in) 4 | 4'h0: pos = 2'h0; 5 | 4'h1: pos = 2'h0; 6 | 4'h2: pos = 2'h1; 7 | 4'h3: pos = 2'h0; 8 | 4'h4: pos = 2'h2; 9 | 4'h5: pos = 2'h0; 10 | 4'h6: pos = 2'h1; 11 | 4'h7: pos = 2'h0; 12 | 4'h8: pos = 2'h3; 13 | 4'h9: pos = 2'h0; 14 | 4'ha: pos = 2'h1; 15 | 4'hb: pos = 2'h0; 16 | 4'hc: pos = 2'h2; 17 | 4'hd: pos = 2'h0; 18 | 4'he: pos = 2'h1; 19 | 4'hf: pos = 2'h0; 20 | default: pos = 2'b0; 21 | endcase 22 | end 23 | 24 | endmodule 25 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4h/m2014_q4h.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple pass-through module. It has two ports, an input port and an output port. The input port is named "in" and the output port is named "out". The module assigns the output port to the same value as the input port. This means that whatever value is applied to the input port will be passed through to the output port. This module is useful for connecting two parts of a circuit together, allowing the same signal to be passed from one part to the other. 2 | 3 | module top_module( 4 | input in, 5 | output out); 6 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_eq2/mt2015_eq2.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple comparison module. It takes two 2-bit inputs, A and B, and compares them bit-by-bit. If all the bits of A are equal to the corresponding bits of B, then the output z is set to 1. Otherwise, z is set to 0. The module does not have any internal logic or state transitions, as it is simply a comparison of two inputs. The port connections of the module are as follows: A and B are both 2-bit inputs, and z is a single-bit output. 2 | 3 | module top_module( 4 | input [1:0] A, 5 | input [1:0] B, 6 | output z); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_fsmonehot/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | parameter S=0, S1=1, S11=2, S110=3, B0=4, B1=5, B2=6, B3=7, Count=8, Wait=9; 3 | 4 | assign B3_next = state[B2]; 5 | assign S_next = state[S]&~d | state[S1]&~d | state[S110]&~d | state[Wait]&ack; 6 | assign S1_next = state[S]&d; 7 | assign Count_next = state[B3] | state[Count]&~done_counting; 8 | assign Wait_next = state[Count]&done_counting | state[Wait]&~ack; 9 | 10 | assign done = state[Wait]; 11 | assign counting = state[Count]; 12 | assign shift_ena = |state[B3:B0]; 13 | 14 | endmodule 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm_ps2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | wire in3 = in[3]; 6 | 7 | always_comb begin 8 | case (state) 9 | BYTE1: next = in3 ? BYTE2 : BYTE1; 10 | BYTE2: next = BYTE3; 11 | BYTE3: next = DONE; 12 | DONE: next = in3 ? BYTE2 : BYTE1; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) begin 17 | if (reset) state <= BYTE1; 18 | else state <= next; 19 | end 20 | 21 | assign done = (state==DONE); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm_ps2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter BYTE1=0, BYTE2=1, BYTE3=2, DONE=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | wire in3 = in[3]; 6 | 7 | always_comb begin 8 | case (state) 9 | BYTE1: next = in3 ? BYTE2 : BYTE1; 10 | BYTE2: next = BYTE3; 11 | BYTE3: next = DONE; 12 | DONE: next = in3 ? BYTE2 : BYTE1; 13 | endcase 14 | end 15 | 16 | always @(posedge clk) begin 17 | if (reset) state <= BYTE1; 18 | else state <= next; 19 | end 20 | 21 | assign done = (state==DONE); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4e/m2014_q4e.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a combinational logic module that takes two input signals, in1 and in2, and produces one output signal, out. The output signal is the logical negation of the logical OR of the two input signals. This means that the output signal will be high (1) if both input signals are low (0), and will be low (0) if either of the input signals is high (1). This module is useful for implementing logic functions such as a NAND gate or a NOR gate. 2 | 3 | module top_module ( 4 | input in1, 5 | input in2, 6 | output logic out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q6/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3, E=4, F=5; 2 | reg [2:0] state, next; 3 | 4 | always @(posedge clk) 5 | if (reset) 6 | state <= A; 7 | else 8 | state <= next; 9 | 10 | 11 | always_comb begin 12 | case(state) 13 | A: next = w ? A : B; 14 | B: next = w ? D : C; 15 | C: next = w ? D : E; 16 | D: next = w ? A : F; 17 | E: next = w ? D : E; 18 | F: next = w ? D : C; 19 | default: next = 'x; 20 | endcase 21 | end 22 | 23 | assign z = (state == E || state == F); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit1/circuit1.sv: -------------------------------------------------------------------------------- 1 | // This module implements a logic AND gate between two inputs a and b, and the output q is the result of the AND operation. The module has three ports, two inputs (a and b) and one output (q). The inputs a and b are connected to the AND gate, and the output q is the result of the AND operation between a and b. The AND gate performs a logical AND operation between the two inputs and produces a single output. The output q will be 1 if both inputs a and b are 1, and 0 otherwise. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | output q 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/step_one/step_one.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a simple module that assigns the output one to a value of 1'b1. This means that the output one will always be set to a logic high value. This is a useful module for testing purposes, as it can be used to ensure that the logic in the rest of the circuit is functioning correctly. The output one is connected to the output of the module, and no other ports are connected. This module does not have any logic or state transitions, as it is simply assigning the output one to a constant value. 2 | 3 | module top_module( 4 | output one); 5 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector1/vector1.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple 16-bit to 8-bit splitter. It takes a 16-bit input signal, "in", and splits it into two 8-bit signals, "out_hi" and "out_lo". The two 8-bit signals are the upper and lower 8 bits of the original 16-bit signal, respectively. The module does not contain any logic, it simply assigns the two 8-bit signals to the 16-bit input signal. This module is useful when splitting a 16-bit signal into two 8-bit signals is necessary. 2 | 3 | module top_module ( 4 | input [15:0] in, 5 | output [7:0] out_hi, 6 | output [7:0] out_lo 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2014_q5a/ece241_2014_q5a.sv: -------------------------------------------------------------------------------- 1 | // You are to design a one-input one-output serial 2's complementer Moore state machine. The input (x) is a series of bits (one per clock cycle) beginning with the least-significant bit of the number, and the output (Z) is the 2's complement of the input. The machine will accept input numbers of arbitrary length. The circuit requires a positive edge triggered asynchronous reset. The conversion begins when Reset is released and stops when Reset is asserted. 2 | 3 | module top_module ( 4 | input clk, 5 | input areset, 6 | input x, 7 | output z 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mt2015_q4/mt2015_q4.sv: -------------------------------------------------------------------------------- 1 | // The top module is a logic gate that receives x and y inputs and returns the z output. 2 | The x input is the a input for the first gate and the b input for the second gate. 3 | The y input is the b input for the first gate and the a input for the second gate. 4 | The output of the first gate is the a input for the third gate. 5 | The output of the second gate is the b input for the third gate. 6 | The output of the third gate is the z output. 7 | 8 | 9 | module top_module( 10 | input x, 11 | input y, 12 | output z); 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/truthtable1/truthtable1.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module takes three input signals, x3, x2, and x1, and produces an output signal f. The output signal f is determined by the combination of the three input signals using a logical OR operation. The output signal f will be high if any of the following four combinations of the three input signals is true: (not x3 and x2 and not x1), (not x3 and x2 and x1), (x3 and not x2 and x1), or (x3 and x2 and x1). Otherwise, the output signal f will be low. 2 | 3 | module top_module ( 4 | input x3, 5 | input x2, 6 | input x1, 7 | output f 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4c/m2014_q4c.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple register that is used to store data. It has three inputs: a clock (clk), a data input (d), and a reset (r). It also has one output, q, which is the output of the register. The module is triggered on the rising edge of the clock. When the reset is active, the output of the register is set to 0. Otherwise, the output is set to the value of the data input. This allows the register to store the data input until the reset is activated. 2 | 3 | module top_module ( 4 | input clk, 5 | input d, 6 | input r, 7 | output logic q 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/bugs_case/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | // uhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch? 2 | // and have one of the entries be wrong? (duplicate case, using different base!) 3 | always @(*) begin 4 | out = 0; 5 | valid = 1; 6 | case (code) 7 | 8'h45: out = 0; 8 | 8'h16: out = 1; 9 | 8'h1e: out = 2; 10 | 8'h26: out = 3; 11 | 8'h25: out = 4; 12 | 8'h2e: out = 5; 13 | 8'h36: out = 6; 14 | 8'h3d: out = 7; 15 | 8'h3e: out = 8; 16 | 8'h46: out = 9; 17 | default: valid = 0; 18 | endcase 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q8/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter S=0, S1=1, S10=2; 2 | reg[1:0] state, next; 3 | 4 | always@(posedge clk, negedge aresetn) 5 | if (!aresetn) 6 | state <= S; 7 | else 8 | state <= next; 9 | 10 | always_comb begin 11 | case (state) 12 | S: next = x ? S1 : S; 13 | S1: next = x ? S1 : S10; 14 | S10: next = x ? S1 : S; 15 | default: next = 'x; 16 | endcase 17 | end 18 | 19 | always_comb begin 20 | case (state) 21 | S: z = 0; 22 | S1: z = 0; 23 | S10: z = x; 24 | default: z = 'x; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/bugs_case/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | // uhh.. make a case statement: maps scancode to 0-9, but accidentally infer a latch? 2 | // and have one of the entries be wrong? (duplicate case, using different base!) 3 | always @(*) begin 4 | out = 0; 5 | valid = 1; 6 | case (code) 7 | 8'h45: out = 0; 8 | 8'h16: out = 1; 9 | 8'h1e: out = 2; 10 | 8'h26: out = 3; 11 | 8'h25: out = 4; 12 | 8'h2e: out = 5; 13 | 8'h36: out = 6; 14 | 8'h3d: out = 7; 15 | 8'h3e: out = 8; 16 | 8'h46: out = 9; 17 | default: valid = 0; 18 | endcase 19 | end 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2013_q8/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter S=0, S1=1, S10=2; 2 | reg[1:0] state, next; 3 | 4 | always@(posedge clk, negedge aresetn) 5 | if (!aresetn) 6 | state <= S; 7 | else 8 | state <= next; 9 | 10 | always_comb begin 11 | case (state) 12 | S: next = x ? S1 : S; 13 | S1: next = x ? S1 : S10; 14 | S10: next = x ? S1 : S; 15 | default: next = 'x; 16 | endcase 17 | end 18 | 19 | always_comb begin 20 | case (state) 21 | S: z = 0; 22 | S1: z = 0; 23 | S10: z = x; 24 | default: z = 'x; 25 | endcase 26 | end 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/review2015_shiftcount/review2015_shiftcount.sv: -------------------------------------------------------------------------------- 1 | // Build a four-bit shift register that also acts as a down counter. Data is shifted in most-significant-bit first when shift_ena is 1. The number currently in the shift register is decremented when count_ena is 1. Since the full system doesn't ever use shift_ena and count_ena together, it does not matter what your circuit does if both control inputs are 1 (This mainly means that it doesn't matter which case gets higher priority). 2 | 3 | module top_module( 4 | input clk, 5 | input shift_ena, 6 | input count_ena, 7 | input data, 8 | output reg [3:0] q); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux256to1/mux256to1.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a top-level module that takes in an input vector of 256 bits (in) and an 8-bit selection vector (sel) and outputs a single bit (out). The output bit is determined by the selection vector, which is used to select one of the 256 bits from the input vector. The output bit is the bit from the input vector that corresponds to the selection vector. For example, if the selection vector is '10101010' (binary), the output bit will be the 8th bit of the input vector. 2 | 3 | module top_module ( 4 | input [255:0] in, 5 | input [7:0] sel, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4d/m2014_q4d.sv: -------------------------------------------------------------------------------- 1 | // This module is a simple toggle flip-flop. It takes an input signal (in) and a clock signal (clk) and produces an output signal (out). The output signal is initially set to 0. When the clock signal (clk) transitions from low to high (posedge), the output signal (out) is set to the logical XOR of the input signal (in) and the previous output signal (out). This means that the output signal (out) will toggle (change from 0 to 1 or from 1 to 0) every time the clock signal (clk) transitions from low to high. 2 | 3 | module top_module ( 4 | input clk, 5 | input in, 6 | output logic out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/bugs_case/bugs_case.sv: -------------------------------------------------------------------------------- 1 | // This combinational circuit is supposed to recognize 8-bit keyboard scancodes for keys 0 through 9. It should indicate whether one of the 10 cases were recognized (valid), and if so, which key was detected. If the 8-bit input is 8'h45, 8'h16, 8'h1e, 8'h26, 8'h25, 8'h2e, 8'h36, 8'h3d, 8'h3e, or 8'h46, the 4-bit output will be set to 0, 1, 2, 3, 4, 5, 6, 7, 8, or 9 respectively, the 1-bit valid would be set to 1. If the input does not match any of the cases, both output signals would be set to 0. 2 | 3 | module top_module ( 4 | input [7:0] code, 5 | output reg [3:0] out, 6 | output reg valid 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm1/fsm1.sv: -------------------------------------------------------------------------------- 1 | // The top module is a simple state machine that has two states, A and B. The state transitions are determined by the input signal 'in'. When the state is A, if 'in' is high, the next state is A, otherwise the next state is B. When the state is B, if 'in' is high, the next state is B, otherwise the next state is A. The state is updated on the rising edge of the clock signal 'clk' and reset to state B on the rising edge of the reset signal 'areset'. The output 'out' is high when the state is B and low otherwise. 2 | 3 | module top_module ( 4 | input clk, 5 | input in, 6 | input areset, 7 | output out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/wire4/wire4.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple combinational logic module that assigns the values of the inputs a, b, and c to the outputs w, x, y, and z. Specifically, the output w is assigned the value of input a, the output x is assigned the value of input b, the output y is assigned the value of input b, and the output z is assigned the value of input c. This module does not contain any state transitions or logic descriptions, as it is a simple combinational logic module. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input c, 7 | output w, 8 | output x, 9 | output y, 10 | output z ); 11 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/counter_2bc/counter_2bc.sv: -------------------------------------------------------------------------------- 1 | // Build a two-bit saturating counter. The counter increments (up to a maximum of 3) when train_valid = 1 and train_taken = 1. It decrements (down to a minimum of 0) when train_valid = 1 and train_taken = 0. When not training (train_valid = 0), the counter keeps its value unchanged. areset is a positive edge triggered asynchronous reset that resets the counter to weakly not-taken (2'b01). Output state[1:0] is the two-bit counter value. 2 | 3 | module top_module( 4 | input clk, 5 | input areset, 6 | input train_valid, 7 | input train_taken, 8 | output logic [1:0] state 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_count1k/review2015_count1k.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple counter that counts from 0 to 999. It has three ports, an input clock (clk), an input reset, and an output register (q). The output register is 10 bits wide, allowing it to count up to 999. The module is always triggered on the positive edge of the clock. When the reset input is active, the output register is reset to 0. Otherwise, the output register is incremented by 1. When the output register reaches 999, it is reset to 0 and the counting cycle begins again. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [9:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/ece241_2013_q2/ece241_2013_q2.sv: -------------------------------------------------------------------------------- 1 | // A single-output digital system with four inputs (a,b,c,d) generates a logic-1 when 2, 7, or 15 appears on the inputs, and a logic-0 when 0, 1, 4, 5, 6, 9, 10, 13, or 14 appears. The input conditions for the numbers 3, 8, 11, and 12 never occur in this system. For example, 7 corresponds to a,b,c,d being set to 0,1,1,1, respectively. Determine the output out_sop in minimum sum-of-products form, and the output out_pos in minimum product-of-sums form. 2 | 3 | 4 | 5 | module top_module ( 6 | input a, 7 | input b, 8 | input c, 9 | input d, 10 | output out_sop, 11 | output out_pos 12 | ); 13 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case({a,b,c,d}) 4 | 4'h0: out = 0; 5 | 4'h1: out = 1; 6 | 4'h3: out = 0; 7 | 4'h2: out = 1; 8 | 4'h4: out = 1; 9 | 4'h5: out = 0; 10 | 4'h7: out = 1; 11 | 4'h6: out = 0; 12 | 4'hc: out = 0; 13 | 4'hd: out = 1; 14 | 4'hf: out = 0; 15 | 4'he: out = 1; 16 | 4'h8: out = 1; 17 | 4'h9: out = 0; 18 | 4'hb: out = 1; 19 | 4'ha: out = 0; 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2014_q3fsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7; 2 | reg [2:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (reset) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = s ? B : A; 12 | B: next = w ? S11 : S10; 13 | C: next = w ? S11 : S10; 14 | S10: next = w ? S21 : S20; 15 | S11: next = w ? S22 : S21; 16 | S20: next = B; 17 | S21: next = w ? C : B; 18 | S22: next = w ? B : C; 19 | default: next = 'x; 20 | endcase 21 | end 22 | 23 | assign z = (state == C); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2014_q3fsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, S10=3, S11=4, S20=5, S21=6, S22=7; 2 | reg [2:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (reset) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = s ? B : A; 12 | B: next = w ? S11 : S10; 13 | C: next = w ? S11 : S10; 14 | S10: next = w ? S21 : S20; 15 | S11: next = w ? S22 : S21; 16 | S20: next = B; 17 | S21: next = w ? C : B; 18 | S22: next = w ? B : C; 19 | default: next = 'x; 20 | endcase 21 | end 22 | 23 | assign z = (state == C); 24 | 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/kmap4/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case({a,b,c,d}) 4 | 4'h0: out = 0; 5 | 4'h1: out = 1; 6 | 4'h3: out = 0; 7 | 4'h2: out = 1; 8 | 4'h4: out = 1; 9 | 4'h5: out = 0; 10 | 4'h7: out = 1; 11 | 4'h6: out = 0; 12 | 4'hc: out = 0; 13 | 4'hd: out = 1; 14 | 4'hf: out = 0; 15 | 4'he: out = 1; 16 | 4'h8: out = 1; 17 | 4'h9: out = 0; 18 | 4'hb: out = 1; 19 | 4'ha: out = 0; 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/kmap3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case({a,b,c,d}) 4 | 4'h0: out = 0; 5 | 4'h1: out = 0; 6 | 4'h3: out = 1; 7 | 4'h2: out = 1; 8 | 4'h4: out = 1'bx; 9 | 4'h5: out = 0; 10 | 4'h7: out = 0; 11 | 4'h6: out = 0; 12 | 4'hc: out = 1; 13 | 4'hd: out = 1'bx; 14 | 4'hf: out = 1; 15 | 4'he: out = 1; 16 | 4'h8: out = 1; 17 | 4'h9: out = 1'bx; 18 | 4'hb: out = 1; 19 | 4'ha: out = 1; 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/kmap1/kmap1.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple logic gate that performs a logical OR operation on the three inputs a, b, and c and assigns the result to the output out. The OR operation is a binary operation that returns a true value if one or more of its inputs are true. In this module, the output out will be true if any of the inputs a, b, or c are true. If all of the inputs are false, then the output out will be false. The module is composed of a single assign statement that performs the OR operation on the inputs and assigns the result to the output out. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | input c, 7 | output out 8 | ); 9 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/kmap3/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | always @(*) begin 3 | case({a,b,c,d}) 4 | 4'h0: out = 0; 5 | 4'h1: out = 0; 6 | 4'h3: out = 1; 7 | 4'h2: out = 1; 8 | 4'h4: out = 1'bx; 9 | 4'h5: out = 0; 10 | 4'h7: out = 0; 11 | 4'h6: out = 0; 12 | 4'hc: out = 1; 13 | 4'hd: out = 1'bx; 14 | 4'hf: out = 1; 15 | 4'he: out = 1; 16 | 4'h8: out = 1; 17 | 4'h9: out = 1'bx; 18 | 4'hb: out = 1; 19 | 4'ha: out = 1; 20 | endcase 21 | end 22 | endmodule 23 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/m2014_q4a/m2014_q4a.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple combinational logic circuit. It has three ports: an input port 'd', an enable port 'ena', and an output port 'q'. The enable port is used to control the output port. When the enable port is active (high), the output port will be equal to the value of the input port. When the enable port is inactive (low), the output port will remain unchanged. This module is useful for controlling the flow of data in a circuit, as it allows the user to enable or disable the flow of data from the input port to the output port. 2 | 3 | module top_module ( 4 | input d, 5 | input ena, 6 | output logic q 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/popcount3/popcount3.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple combinational logic module that takes three input bits and produces two output bits. The module is named top and it has three inputs, in[2:0], and two outputs, out[1:0]. The output of the module is calculated by adding the three input bits together. The result of the addition is stored in the two output bits, out[1:0]. The most significant bit of the result is stored in out[1] and the least significant bit is stored in out[0]. The module does not have any internal state and it does not use any instantiated modules. 2 | 3 | module top_module ( 4 | input [2:0] in, 5 | output [1:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit7/circuit7.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple combinational logic circuit that has one input (a) and one output (q). It is triggered by a clock signal (clk) and has a register (q) that stores the output value. The module uses a positive edge triggered always block to implement the logic. When the clock signal goes from low to high, the output q is set to the inverse of the input a. This means that when the input a is high, the output q will be low and vice versa. The module will continuously update the output q whenever the clock signal changes from low to high. 2 | 3 | module top_module ( 4 | input clk, 5 | input a, 6 | output reg q 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2014_q3/ece241_2014_q3.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a 4-to-1 multiplexer. It takes two inputs, c and d, and outputs a 4-bit signal mux_in. The output of the multiplexer is determined by the values of the two inputs. The output of the multiplexer is assigned to the 4-bit signal mux_in. The first bit of mux_in is assigned to the logical OR of the two inputs, c and d. The second bit of mux_in is assigned to 0. The third bit of mux_in is assigned to the logical NOT of the input d. The fourth bit of mux_in is assigned to the logical AND of the two inputs, c and d. 2 | 3 | module top_module ( 4 | input c, 5 | input d, 6 | output [3:0] mux_in 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/norgate/norgate.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module takes two input signals, a and b, and produces an output signal, out. The output signal is the logical negation of the logical OR of the two inputs. This means that the output will be high when both inputs are low, and low when either of the inputs is high. This module is a simple logic gate, specifically an OR gate with an inverter. The OR gate takes the two inputs and produces a high output when either of the inputs is high, and the inverter inverts the output of the OR gate, producing a low output when either of the inputs is high. 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector4/vector4.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple combinational circuit that takes an 8-bit input and produces a 32-bit output. The output is formed by replicating the 8-bit input 24 times and then concatenating it with the original 8-bit input. This module does not contain any instantiated modules or state transitions, so the functionality is straightforward. The input is connected directly to the output, with the 8-bit input being replicated 24 times. The output is 32 bits wide, with the first 24 bits being the replicated input and the last 8 bits being the original input. 2 | 3 | module top_module ( 4 | input [7:0] in, 5 | output [31:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2013_q2afsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | reg [1:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (~resetn) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always@(state,r) begin 10 | case (state) 11 | A: if (r[1]) next = B; 12 | else if (r[2]) next = C; 13 | else if (r[3]) next = D; 14 | else next = A; 15 | B: next = r[1] ? B : A; 16 | C: next = r[2] ? C : A; 17 | D: next = r[3] ? D : A; 18 | default: next = 'x; 19 | endcase 20 | end 21 | 22 | assign g[1] = (state == B); 23 | assign g[2] = (state == C); 24 | assign g[3] = (state == D); 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector3/vector3.sv: -------------------------------------------------------------------------------- 1 | // Given several input vectors, concatenate them together then split them up into several output vectors. There are six 5-bit input vectors: a, b, c, d, e, and f, for a total of 30 bits of input. There are four 8-bit output vectors: w, x, y, and z, for 32 bits of output. The output should be a concatenation of the input vectors followed by two 1 bits (the two 1 bits should be in the LSB positions). 2 | 3 | module top_module ( 4 | input [4:0] a, 5 | input [4:0] b, 6 | input [4:0] c, 7 | input [4:0] d, 8 | input [4:0] e, 9 | input [4:0] f, 10 | output [7:0] w, 11 | output [7:0] x, 12 | output [7:0] y, 13 | output [7:0] z 14 | ); 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2013_q2afsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, C=2, D=3; 2 | reg [1:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (~resetn) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always@(state,r) begin 10 | case (state) 11 | A: if (r[1]) next = B; 12 | else if (r[2]) next = C; 13 | else if (r[3]) next = D; 14 | else next = A; 15 | B: next = r[1] ? B : A; 16 | C: next = r[2] ? C : A; 17 | D: next = r[3] ? D : A; 18 | default: next = 'x; 19 | endcase 20 | end 21 | 22 | assign g[1] = (state == B); 23 | assign g[2] = (state == C); 24 | assign g[3] = (state == D); 25 | endmodule 26 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/andgate/andgate.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a simple logic gate that performs a logical AND operation on two input signals, a and b, and outputs the result on the out signal. The module has three ports, two inputs (a and b) and one output (out). The two inputs are connected to the logical AND gate, which produces the output signal out. The output signal out is the result of the logical AND operation between the two input signals a and b. The output signal out will be high (1) if both input signals a and b are high (1) and low (0) if either of the input signals a or b is low (0). 2 | 3 | module top_module( 4 | input a, 5 | input b, 6 | output out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/m2014_q6b/m2014_q6b.sv: -------------------------------------------------------------------------------- 1 | // Consider the state machine shown below: 2 | 3 | // A (0) --0--> B 4 | // A (0) --1--> A 5 | // B (0) --0--> C 6 | // B (0) --1--> D 7 | // C (0) --0--> E 8 | // C (0) --1--> D 9 | // D (0) --0--> F 10 | // D (0) --1--> A 11 | // E (1) --0--> E 12 | // E (1) --1--> D 13 | // F (1) --0--> C 14 | // F (1) --1--> D 15 | 16 | // Assume that you want to Implement the FSM using three flip-flops and state codes y[3:1] = 000, 001, ..., 101 for states A, B, ..., F, respectively. Implement just the next-state logic for y[2] in Verilog. The output Y2 is y[2]. 17 | 18 | module top_module( 19 | input [3:1] y, 20 | input w, 21 | output reg Y2); 22 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/shift4/shift4.sv: -------------------------------------------------------------------------------- 1 | // Build a 4-bit shift register (right shift), with asynchronous positive edge triggered areset, synchronous active high signals load, and enable. 2 | // (1) areset: Resets shift register to zero. 3 | // (2) load: Loads shift register with data[3:0] instead of shifting. 4 | // (3) ena: Shift right (q[3] becomes zero, q[0] is shifted out and disappears). 5 | // (4) q: The contents of the shift register. If both the load and ena inputs are asserted (1), the load input has higher priority. 6 | 7 | 8 | module top_module( 9 | input clk, 10 | input areset, 11 | input load, 12 | input ena, 13 | input [3:0] data, 14 | output reg [3:0] q); 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm_onehot/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out1 = state[8] | state[9]; 3 | assign out2 = state[7] | state[9]; 4 | 5 | assign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]); 6 | assign next_state[1] = in && (state[0] | state[8] | state[9]); 7 | assign next_state[2] = in && state[1]; 8 | assign next_state[3] = in && state[2]; 9 | assign next_state[4] = in && state[3]; 10 | assign next_state[5] = in && state[4]; 11 | assign next_state[6] = in && state[5]; 12 | assign next_state[7] = in && (state[6] | state[7]); 13 | assign next_state[8] = !in && state[5]; 14 | assign next_state[9] = !in && state[6]; 15 | 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/fsm_onehot/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | 2 | assign out1 = state[8] | state[9]; 3 | assign out2 = state[7] | state[9]; 4 | 5 | assign next_state[0] = !in && (|state[4:0] | state[7] | state[8] | state[9]); 6 | assign next_state[1] = in && (state[0] | state[8] | state[9]); 7 | assign next_state[2] = in && state[1]; 8 | assign next_state[3] = in && state[2]; 9 | assign next_state[4] = in && state[3]; 10 | assign next_state[5] = in && state[4]; 11 | assign next_state[6] = in && state[5]; 12 | assign next_state[7] = in && (state[6] | state[7]); 13 | assign next_state[8] = !in && state[5]; 14 | assign next_state[9] = !in && state[6]; 15 | 16 | 17 | endmodule 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/vector4/vector4.sv: -------------------------------------------------------------------------------- 1 | // One common place to see a replication operator is when sign-extending a smaller number to a larger one, while preserving its signed value. This is done by replicating the sign bit (the most significant bit) of the smaller number to the left. For example, sign-extending 4'b0101 (5) to 8 bits results in 8'b00000101 (5), while sign-extending 4'b1101 (-3) to 8 bits results in 8'b11111101 (-3). Build a circuit that sign-extends an 8-bit number to 32 bits. This requires a concatenation of 24 copies of the sign bit (i.e., replicate bit[7] 24 times) followed by the 8-bit number itself. 2 | 3 | module top_module ( 4 | input [7:0] in, 5 | output [31:0] out 6 | ); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/count10/count10.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple counter. It has one input, clk, one output, q, and one reset input. The clk input is used to trigger the counter. The reset input is used to reset the counter to 0. The output q is a 4-bit register that stores the current count value. The module has an always block that is triggered on the positive edge of the clk signal. Inside the always block, an if-else statement is used to determine the next value of q. If the reset input is asserted or the current value of q is equal to 9, then q is reset to 0. Otherwise, q is incremented by 1. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [3:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/circuit8/circuit8.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module has 2 inputs and 2 outputs. The inputs are a clock (clock) and a signal (a). The outputs are two registers, p and q. The clock signal is used to trigger the two always blocks. The first always block is triggered on the negative edge of the clock signal. This always block assigns the current value of the signal a to the register q. The second always block is triggered on any change of the input signal a. This always block assigns the current value of the signal a to the register p if the clock signal is high. 2 | 3 | 4 | 5 | 6 | module top_module ( 7 | input clock, 8 | input a, 9 | output reg p, 10 | output reg q 11 | ); 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3comb/fsm3comb.sv: -------------------------------------------------------------------------------- 1 | // The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2'b00, B=2'b01, C=2'b10, D=2'b11.Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state), compute the next_state and output (out) based on the state transition table. 2 | // State | Next state in=0, Next state in=1 | Output 3 | // A | A, B | 0 4 | // B | C, B | 0 5 | // C | A, D | 0 6 | // D | C, B | 1 7 | 8 | module top_module ( 9 | input in, 10 | input [1:0] state, 11 | output reg [1:0] next_state, 12 | output out 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/lemmings2/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter WL=0, WR=1, FALLL=2, FALLR=3; 2 | reg [1:0] state; 3 | reg [1:0] next; 4 | 5 | always_comb begin 6 | case (state) 7 | WL: next = ground ? (bump_left ? WR : WL) : FALLL; 8 | WR: next = ground ? (bump_right ? WL: WR) : FALLR; 9 | FALLL: next = ground ? WL : FALLL; 10 | FALLR: next = ground ? WR : FALLR; 11 | endcase 12 | end 13 | 14 | always @(posedge clk, posedge areset) begin 15 | if (areset) state <= WL; 16 | else state <= next; 17 | end 18 | 19 | assign walk_left = (state==WL); 20 | assign walk_right = (state==WR); 21 | assign aaah = (state == FALLL) || (state == FALLR); 22 | 23 | endmodule 24 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2014_q3fsm/2014_q3fsm.sv: -------------------------------------------------------------------------------- 1 | // state A: If s is asserted, next state is B 2 | state B: If w is asserted, next state is S11, otherwise next state is S10 3 | state C: If w is asserted, next state is S11, otherwise next state is S10 4 | state S10: If w is asserted, next state is S21, otherwise next state is S20 5 | state S11: If w is asserted, next state is S22, otherwise next state is S21 6 | state S20: next state is B 7 | state S21: If w is asserted, next state is C, otherwise next state is B 8 | state S22: If w is asserted, next state is B, otherwise next state is C 9 | 10 | 11 | module top_module ( 12 | input clk, 13 | input reset, 14 | input s, 15 | input w, 16 | output reg z 17 | ); 18 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/count1to10/count1to10.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a simple counter that increments its output q by one every clock cycle. It has 3 inputs, a clock (clk), a reset signal (reset), and an output register (q). The output register is a 4-bit register, meaning it can store values from 0 to 15. The module is triggered on the rising edge of the clock signal. When the reset signal is active, the output register is set to 1. If the reset signal is not active, the output register is incremented by one. When the output register reaches 10 (1010 in binary), it is reset to 1. This process is repeated every clock cycle. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [3:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/2013_q2bfsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8; 2 | reg [3:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (~resetn) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = B; 12 | B: next = S0; 13 | S0: next = x ? S1 : S0; 14 | S1: next = x ? S1 : S10; 15 | S10: next = x? G1 : S0; 16 | G1: next = y ? P1 : G2; 17 | G2: next = y ? P1 : P0; 18 | P0: next = P0; 19 | P1: next = P1; 20 | default: next = 'x; 21 | endcase 22 | end 23 | 24 | assign f = (state == B); 25 | assign g = (state == G1) || (state == G2) || (state == P1); 26 | endmodule 27 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/fsm3onehot/fsm3onehot.sv: -------------------------------------------------------------------------------- 1 | // The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4'b0001, B=4'b0010, C=4'b0100, D=4'b1000. Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. 2 | // State | Next state in=0, Next state in=1 | Output 3 | // A | A, B | 0 4 | // B | C, B | 0 5 | // C | A, D | 0 6 | // D | C, B | 1 7 | 8 | module top_module ( 9 | input in, 10 | input [3:0] state, 11 | output reg [3:0] next_state, 12 | output out 13 | ); 14 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/2013_q2bfsm/canonical_solution.txt: -------------------------------------------------------------------------------- 1 | parameter A=0, B=1, S0=2, S1=3, S10=4, G1=5, G2=6, P0=7, P1=8; 2 | reg [3:0] state, next; 3 | 4 | always @(posedge clk) begin 5 | if (~resetn) state <= A; 6 | else state <= next; 7 | end 8 | 9 | always_comb begin 10 | case (state) 11 | A: next = B; 12 | B: next = S0; 13 | S0: next = x ? S1 : S0; 14 | S1: next = x ? S1 : S10; 15 | S10: next = x? G1 : S0; 16 | G1: next = y ? P1 : G2; 17 | G2: next = y ? P1 : P0; 18 | P0: next = P0; 19 | P1: next = P1; 20 | default: next = 'x; 21 | endcase 22 | end 23 | 24 | assign f = (state == B); 25 | assign g = (state == G1) || (state == G2) || (state == P1); 26 | endmodule 27 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/dff/dff.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a simple top-level module that takes in two inputs, a clock signal (clk) and a data signal (d), and outputs a register signal (q). The module has an initial block that sets the initial value of the register signal q to 1'hx, which is a hexadecimal representation of a one-bit value that is unknown or undefined. The always block is triggered by the rising edge of the clock signal and sets the register signal q to the value of the data signal d. This module is used to synchronize the data signal d with the clock signal clk, so that the data signal is sampled at the rising edge of the clock signal. 2 | 3 | module top_module( 4 | input clk, 5 | input d, 6 | output reg q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2013_q12/ece241_2013_q12.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module is a shift register with a multiplexer at the output. The module has an 8-bit register, q, and a 3-bit multiplexer. The clock, enable, and S inputs are used to control the register. When the enable signal is high, the register is enabled and the S input is shifted into the register. The A, B, and C inputs are used to select which bit of the register is output on the Z output. The A, B, and C inputs are combined to form a 3-bit address that is used to select which bit of the register is output on the Z output. 2 | 3 | module top_module ( 4 | input clk, 5 | input enable, 6 | input S, 7 | input A, 8 | input B, 9 | input C, 10 | output reg Z 11 | ); 12 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/7420/7420.sv: -------------------------------------------------------------------------------- 1 | // This module is a simple logic gate that implements a 4-input AND gate with an inverted output. It has two sets of four inputs, p1a, p1b, p1c, and p1d, and p2a, p2b, p2c, and p2d. It also has two outputs, p1y and p2y. The p1y output is the result of the AND operation on the four inputs p1a, p1b, p1c, and p1d. The p2y output is the result of the AND operation on the four inputs p2a, p2b, p2c, and p2d. The outputs are inverted, so the output will be 0 if all the inputs are 1, and 1 if any of the inputs are 0. 2 | 3 | module top_module( 4 | input p1a, 5 | input p1b, 6 | input p1c, 7 | input p1d, 8 | output p1y, 9 | input p2a, 10 | input p2b, 11 | input p2c, 12 | input p2d, 13 | output p2y 14 | ); 15 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/kmap2/kmap2.sv: -------------------------------------------------------------------------------- 1 | // This Verilog module implements a logic function which takes four input signals (a, b, c, and d) and produces one output signal (out). The output signal is calculated by combining the four input signals using a logical OR operation. Specifically, the output signal is true (1) if any of the following conditions are met: 1. c and b are both false (0) 2. d and a are both false (0) 3. a, c, and d are all true (1) 4. b, c, and d are all true (1) Otherwise, the output signal is false (0). This module does not contain any instantiated modules, so all of the logic is implemented directly in the assign statement. 2 | 3 | module top_module ( 4 | input a, 5 | input b, 6 | input c, 7 | input d, 8 | output out 9 | ); 10 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/mux256to1v/mux256to1v.sv: -------------------------------------------------------------------------------- 1 | // This top Verilog module is a 4-bit selector module. It takes in a 1024-bit input vector (in) and an 8-bit selection vector (sel) and outputs a 4-bit vector (out). The selection vector (sel) is used to select a 4-bit block from the input vector (in). The output vector (out) is the 4-bit block selected from the input vector (in) based on the selection vector (sel). The selection vector (sel) is used to calculate the starting index of the 4-bit block in the input vector (in). The 4-bit block is then extracted from the input vector (in) starting from the calculated index and is assigned to the output vector (out). 2 | 3 | module top_module ( 4 | input [1023:0] in, 5 | input [7:0] sel, 6 | output [3:0] out 7 | ); 8 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/vector5/vector5.sv: -------------------------------------------------------------------------------- 1 | // The input a, b, c, d, e are boolean signals. 2 | The output out is a 25-bit vector. 3 | 4 | The module computes the bitwise exclusive-or of the 25-bit vector ~{ {5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}} } and the 25-bit vector {5{a,b,c,d,e}}. The first vector consists of 25 bits with value 1 if the corresponding input signal is 0, and consists of 25 bits with value 0 if the corresponding input signal is 1. The second vector consists of 25 bits with value 1 if the corresponding input signal is 1, and consists of 25 bits with value 0 if the corresponding input signal is 0. 5 | 6 | 7 | 8 | module top_module ( 9 | input a, 10 | input b, 11 | input c, 12 | input d, 13 | input e, 14 | output [24:0] out 15 | ); 16 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_human/lfsr5/lfsr5.sv: -------------------------------------------------------------------------------- 1 | // A linear feedback shift register is a shift register usually with a few XOR gates to produce the next state of the shift register. A Galois LFSR is one particular arrangement where bit positions with a "tap" are XORed with the output bit to produce its next value, while bit positions without a tap shift. If the taps positions are carefully chosen, the LFSR can be made to be "maximum-length". A maximum-length LFSR of n bits cycles through 2**n-1 states before repeating (the all-zero state is never reached). Build a 5-bit maximal-length Galois LFSR with taps at bit positions 5 and 3. The active-high synchronous reset should reset the LFSR output to 1. 2 | 3 | module top_module( 4 | input clk, 5 | input reset, 6 | output reg [4:0] q); 7 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/ece241_2013_q8/ece241_2013_q8.sv: -------------------------------------------------------------------------------- 1 | // when the input x is 0, and the state is S, the state next is S. 2 | when the input x is 1, and the state is S, the state next is S1. 3 | when the input x is 0, and the state is S1, the state next is S10. 4 | when the input x is 1, and the state is S1, the state next is S1. 5 | when the input x is 0, and the state is S10, the state next is S. 6 | when the input x is 1, and the state is S10, the state next is S1. 7 | 8 | when the input state is S, the output z is 0. 9 | when the input state is S1, the output z is 0. 10 | when the input state is S10, the output z is the input x. 11 | 12 | 13 | module top_module ( 14 | input clk, 15 | input aresetn, 16 | input x, 17 | output reg z 18 | ); 19 | -------------------------------------------------------------------------------- /verilogeval_prompts_tbs/ve_testbenches_machine/review2015_fsmshift/review2015_fsmshift.sv: -------------------------------------------------------------------------------- 1 | // The top module contains a 3 bit state register with the following state transition: 2 | 3 | B0 -> B1 -> B2 -> B3 -> Done 4 | 5 | B0 indicates that it is the first shift cycle. 6 | B1 indicates that it is the second shift cycle. 7 | B2 indicates that it is the third shift cycle. 8 | B3 indicates that it is the fourth shift cycle. 9 | Done indicates that it has completed the fourth shift cycle. 10 | 11 | When the reset is 1, it will always go to state B0. 12 | When the reset is 0, and state is not B0, B1, B2, or B3, it is in state Done. 13 | shift_ena will be 1 if state is B0, B1, B2, or B3. 14 | 15 | 16 | 17 | module top_module( 18 | input clk, 19 | input reset, 20 | output shift_ena); 21 | --------------------------------------------------------------------------------