├── .gitignore
├── README.md
└── single-layer-perceptron
    ├── activation_function.v
    ├── ff_lib.v
    ├── fifo.v
    ├── perceptron_top.v
    ├── single-layer-perceptron.gise
    ├── single-layer-perceptron.xise
    ├── uart_rx6.v
    ├── uart_tx6.v
    ├── weighted_sum_top.v
    └── weighted_sum_top_tb.v


/.gitignore:
--------------------------------------------------------------------------------
  1 | # vim .gitignore
  2 | [._]*.s[a-w][a-z]
  3 | [._]s[a-w][a-z]
  4 | *.un~
  5 | Session.vim
  6 | .netrwhist
  7 | *~
  8 | 
  9 | # OSX .gitignore
 10 | .DS_Store
 11 | .AppleDouble
 12 | .LSOverride
 13 | 
 14 | # Icon must ends with two \r.
 15 | Icon
 16 | 
 17 | 
 18 | # Thumbnails
 19 | ._*
 20 | 
 21 | # Files that might appear on external disk
 22 | .Spotlight-V100
 23 | .Trashes
 24 | # ignore ModelSim generated files and directories (temp files and so on)
 25 | [_@]*
 26 | 
 27 | # Linux KDE directory preferences
 28 | .directory
 29 | 
 30 | # ModelSim .gitignore
 31 | # ignore compilation output of ModelSim
 32 | *.mti
 33 | *.dat
 34 | *.dbs
 35 | *.psm
 36 | *.bak
 37 | *.cmp
 38 | *.jpg
 39 | *.html
 40 | *.bsf
 41 | 
 42 | # ignore simulation output of ModelSim
 43 | wlf*
 44 | *.wlf
 45 | *.vstf
 46 | *.ucdb
 47 | cov*/
 48 | transcript*
 49 | sc_dpiheader.h
 50 | vsim.dbg
 51 | 
 52 | # XILINX ISE .gitignore
 53 | # intermediate build files
 54 | *.bgn
 55 | *.bit
 56 | *.bld
 57 | *.cmd_log
 58 | *.drc
 59 | *.ll
 60 | *.lso
 61 | *.msd
 62 | *.msk
 63 | *.ncd
 64 | *.ngc
 65 | *.ngd
 66 | *.ngr
 67 | *.pad
 68 | *.par
 69 | *.pcf
 70 | *.prj
 71 | *.ptwx
 72 | *.rbb
 73 | *.rbd
 74 | *.stx
 75 | *.syr
 76 | *.twr
 77 | *.twx
 78 | *.unroutes
 79 | *.ut
 80 | *.xpi
 81 | *.xst
 82 | *_bitgen.xwbt
 83 | *_envsettings.html
 84 | *_map.map
 85 | *_map.mrp
 86 | *_map.ngm
 87 | *_map.xrpt
 88 | *_ngdbuild.xrpt
 89 | *_pad.csv
 90 | *_pad.txt
 91 | *_par.xrpt
 92 | *_summary.html
 93 | *_summary.xml
 94 | *_usage.xml
 95 | *_xst.xrpt
 96 | 
 97 | # project-wide generated files
 98 | par_usage_statistics.html
 99 | usage_statistics_webtalk.html
100 | webtalk.log
101 | webtalk_pn.xml
102 | *.log
103 | *.cmd
104 | *.wdb
105 | *.exe
106 | *.xmsgs
107 | *.ini
108 | *.xsl
109 | *.xml
110 | *.xwbt
111 | 
112 | # generated folders
113 | iseconfig/
114 | xlnx_auto_0_xdb/
115 | xst/
116 | _ngo/
117 | _xmsgs/
118 | ipcore_dir/
119 | isim/
120 | 


--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | ## Project Description
2 | This is a Verilog library intended for fast, modular hardware implementation of neural networks.
3 | 
4 | ## Current Status
5 | The project is currently under private development. The first release version will appear here at this repo. 
6 | 


--------------------------------------------------------------------------------
/single-layer-perceptron/activation_function.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: 
 5 | // 
 6 | // Create Date:    00:54:37 04/03/2014 
 7 | // Design Name: 
 8 | // Module Name:    activation_function 
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool versions: 
12 | // Description: 
13 | //
14 | // Dependencies: 
15 | //
16 | // Revision: 
17 | // Revision 0.01 - File Created
18 | // Additional Comments: 
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module activation_function(
22 |     input      signed [47 : 0] x,
23 |     output reg signed [47 : 0] y
24 | );
25 | // [TODO] determine whether it is useful or necessary to use 48 bits for y, since
26 | // y will always be <= `ONE
27 | 
28 | // [TODO] refine this representation
29 | `define ONE 48'h000001000000 /* 24.24 fixed point representation of 1.0 */
30 | 
31 | // Approximates a sigmoid function
32 | //         / 0, x < 0
33 | // f(x) = {  x, 0 <= x <= 1
34 | //         \ 1, x > 1
35 | always @(*) begin
36 | 	if (x[47]) // x < 0
37 | 		y = 47'b0;
38 | 	else if (x > `ONE)
39 | 		y = `ONE;
40 | 	else 
41 | 		y = x;
42 | end
43 | 
44 | endmodule


--------------------------------------------------------------------------------
/single-layer-perceptron/ff_lib.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company:
 4 | // Engineer:
 5 | //
 6 | // Create Date:    20:23:12 04/02/2014
 7 | // Design Name:
 8 | // Module Name:    ff_lib
 9 | // Project Name:
10 | // Target Devices:
11 | // Tool versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | 
22 | // dff: D flip-flop
23 | // Parametrized width; default of 1
24 | module dff #(parameter WIDTH = 1) (
25 |     input clk,
26 |     input [WIDTH-1:0] d,
27 |     output reg [WIDTH-1:0] q
28 | );
29 | 
30 | always @(posedge clk) 
31 |     q <= d;
32 | 
33 | endmodule
34 | 
35 | // dffr: D flip-flop with active high synchronous reset
36 | // Parametrized width; default of 1
37 | module dffr #(parameter WIDTH = 1) (
38 |     input clk,
39 |     input r,
40 |     input [WIDTH-1:0] d,
41 |     output reg [WIDTH-1:0] q
42 | );
43 | 
44 | always @(posedge clk)
45 |     if (r)
46 |         q <= {WIDTH{1'b0}};
47 |     else
48 |         q <= d;
49 | endmodule
50 | 
51 | 
52 |     // dffre: D flip-flop with active high enable and reset
53 |     // Parametrized width; default of 1
54 | module dffre #(parameter WIDTH = 1) (
55 |     input clk,
56 |     input r,
57 |     input en,
58 |     input [WIDTH-1:0] d,
59 |     output reg [WIDTH-1:0] q
60 | );
61 | 
62 | always @(posedge clk)
63 |     if (r)
64 |         q <= {WIDTH{1'b0}};
65 |     else if (en)
66 |         q <= d;
67 |     else
68 |         q <= q;
69 | endmodule
70 | 


--------------------------------------------------------------------------------
/single-layer-perceptron/fifo.v:
--------------------------------------------------------------------------------
 1 | `timescale 1ns / 1ps
 2 | //////////////////////////////////////////////////////////////////////////////////
 3 | // Company: 
 4 | // Engineer: Shane Leonard
 5 | // 
 6 | // Create Date:    19:52:03 04/27/2014 
 7 | // Design Name: 
 8 | // Module Name:    fifo 
 9 | // Project Name: 
10 | // Target Devices: 
11 | // Tool versions: 
12 | // Description: 
13 | //
14 | // Dependencies: 
15 | //
16 | // Revision: 
17 | // Revision 0.01 - File Created
18 | // Additional Comments: 
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 | module fifo(
22 | 	input clk,
23 | 	input [WIDTH - 1:0] in,
24 | 	output [WIDTH - 1:0] out
25 | );
26 | 
27 | parameter WIDTH  = 18;
28 | parameter DEPTH = 2;
29 | 
30 | wire [WIDTH - 1 : 0] pipe [DEPTH - 1 : 0];
31 | 
32 | dff #(WIDTH) start(
33 | 	.d   ( in      ),
34 | 	.q   ( pipe[0] ),
35 | 	.clk ( clk     )
36 | );
37 | 
38 | generate
39 | 	genvar i;
40 | 	for (i = 0; i < DEPTH - 1; i = i + 1)
41 | 	begin:pipeline_stage
42 | 		
43 | 		dff #(WIDTH) stage(
44 | 			.d   ( pipe[i]   ),
45 | 			.q   ( pipe[i+1] ),
46 | 			.clk ( clk       )
47 | 		);
48 | 
49 | 	end
50 | endgenerate
51 | 
52 | assign out = pipe[DEPTH - 1];
53 | 
54 | endmodule


--------------------------------------------------------------------------------
/single-layer-perceptron/perceptron_top.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | `include "uart_tx6.v"
  3 | //////////////////////////////////////////////////////////////////////////////////
  4 | // Company: 
  5 | // Engineer: 
  6 | // 
  7 | // Create Date:    15:25:20 04/28/2014 
  8 | // Design Name: 
  9 | // Module Name:    perceptron_top 
 10 | // Project Name: 
 11 | // Target Devices: 
 12 | // Tool versions: 
 13 | // Description: 
 14 | //
 15 | // Dependencies: 
 16 | //
 17 | // Revision: 
 18 | // Revision 0.01 - File Created
 19 | // Additional Comments: 
 20 | //
 21 | //////////////////////////////////////////////////////////////////////////////////
 22 | module perceptron_top(
 23 | 	input CLK,
 24 | 	input RX,
 25 | 	output TX
 26 | );
 27 | 
 28 | parameter N = 8; // number of input pairs to the weighted sum module
 29 | 
 30 | ////////////////////////
 31 | // Configure the UART //
 32 | ////////////////////////
 33 | wire [7:0] din, dout;
 34 | reg en_16_x_baud = 0;
 35 | wire rx_data_present, tx_data_present;
 36 | wire baud_clk;
 37 | 
 38 | dcm32to96mhz baud_clk_generator
 39 | (    // Clock in ports
 40 |     .CLK_IN1(CLK),      // IN
 41 |     // Clock out ports
 42 |     .CLK_OUT1(baud_clk)
 43 | );  // OUT
 44 | 
 45 | reg baud_count = 0;
 46 | 
 47 | always @(posedge baud_clk) begin
 48 | 	if (~baud_count) begin
 49 | 		en_16_x_baud <= 1;
 50 | 	end else begin
 51 | 		en_16_x_baud <= 0;
 52 | 	end
 53 | 	baud_count <= baud_count + 1;
 54 | end
 55 | 
 56 | uart_rx6 uart_rx6 (
 57 | 	.serial_in(RX),
 58 | 	.en_16_x_baud(en_16_x_baud),
 59 | 	.data_out(din),
 60 | 	.buffer_read(1),
 61 | 	.buffer_data_present(rx_data_present),
 62 |     //.buffer_half_full(),
 63 |     //.buffer_full(),
 64 |     .buffer_reset(0),
 65 |     .clk(baud_clk)
 66 | );
 67 | 
 68 | uart_tx6 uart_tx6 (
 69 |     .data_in(dout),
 70 |     .buffer_write(tx_data_present),
 71 |     .buffer_reset(0),
 72 |     .en_16_x_baud(en_16_x_baud),
 73 |     .serial_out(TX),
 74 |     //.buffer_data_present(),
 75 |     //.buffer_half_full(),
 76 |     //.buffer_full(),
 77 |     .clk(baud_clk) 
 78 | );
 79 | 
 80 | parameter M = 8;
 81 | 
 82 | wire [M-1:0] sum = {M{1'b1}};
 83 | 
 84 | send_binary_as_ascii #(M) bin_to_char(
 85 |     .en_16_x_baud(en_16_x_baud),
 86 |     .send(rx_data_present),
 87 |     .binary_in(sum),
 88 |     .ascii_out(dout),
 89 |     .data_present(tx_data_present)
 90 | );
 91 | 
 92 | // wire [17:0] x_val = 18'd10;
 93 | // wire [17:0] w_val = 18'd2;
 94 | 
 95 | // wire [18*N-1:0] x = {N*{x_val}};
 96 | // wire [18*N-1:0] w = {N*{w_val}};
 97 | 
 98 | // weighted_sum_top #(N) weighted_sum(
 99 | // 	.clk(baud_clk),
100 | // 	.x(x), 
101 | // 	.w(w),
102 | // 	.sum(sum)
103 | // );
104 | 
105 | endmodule
106 | 


--------------------------------------------------------------------------------
/single-layer-perceptron/single-layer-perceptron.gise:
--------------------------------------------------------------------------------
  1 | <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
  2 | <generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
  3 | 
  4 |   <!--                                                          -->
  5 | 
  6 |   <!--             For tool use only. Do not edit.              -->
  7 | 
  8 |   <!--                                                          -->
  9 | 
 10 |   <!-- ProjectNavigator created generated project file.         -->
 11 | 
 12 |   <!-- For use in tracking generated file and other information -->
 13 | 
 14 |   <!-- allowing preservation of process status.                 -->
 15 | 
 16 |   <!--                                                          -->
 17 | 
 18 |   <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
 19 | 
 20 |   <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
 21 | 
 22 |   <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="single-layer-perceptron.xise"/>
 23 | 
 24 |   <files xmlns="http://www.xilinx.com/XMLSchema">
 25 |     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
 26 |     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
 27 |     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
 28 |     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
 29 |     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
 30 |     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
 31 |     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
 32 |     <file xil_pn:fileType="FILE_LOG" xil_pn:name="fuse.log"/>
 33 |     <file xil_pn:fileType="FILE_LOG" xil_pn:name="ipcore_dir/coregen.log"/>
 34 |     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="isim"/>
 35 |     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_CMD" xil_pn:name="isim.cmd"/>
 36 |     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_LOG" xil_pn:name="isim.log"/>
 37 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="perceptron_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
 38 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="perceptron_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
 39 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="perceptron_top.bld"/>
 40 |     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="perceptron_top.cmd_log"/>
 41 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="perceptron_top.drc" xil_pn:subbranch="FPGAConfiguration"/>
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 44 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="perceptron_top.ngc"/>
 45 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="perceptron_top.ngd"/>
 46 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="perceptron_top.ngr"/>
 47 |     <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="perceptron_top.pad"/>
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 51 |     <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="perceptron_top.ptwx"/>
 52 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="perceptron_top.stx"/>
 53 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="perceptron_top.syr"/>
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 60 |     <file xil_pn:fileType="FILE_HTML" xil_pn:name="perceptron_top_envsettings.html"/>
 61 |     <file xil_pn:fileType="FILE_NCD" xil_pn:name="perceptron_top_guide.ncd" xil_pn:origination="imported"/>
 62 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="perceptron_top_map.map" xil_pn:subbranch="Map"/>
 63 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="perceptron_top_map.mrp" xil_pn:subbranch="Map"/>
 64 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="perceptron_top_map.ncd" xil_pn:subbranch="Map"/>
 65 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="perceptron_top_map.ngm" xil_pn:subbranch="Map"/>
 66 |     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="perceptron_top_map.xrpt"/>
 67 |     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="perceptron_top_ngdbuild.xrpt"/>
 68 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="perceptron_top_pad.csv" xil_pn:subbranch="Par"/>
 69 |     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="perceptron_top_pad.txt" xil_pn:subbranch="Par"/>
 70 |     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="perceptron_top_par.xrpt"/>
 71 |     <file xil_pn:fileType="FILE_HTML" xil_pn:name="perceptron_top_summary.html"/>
 72 |     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="perceptron_top_summary.xml"/>
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 75 |     <file xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="send_binary_as_ascii_tb_beh.prj"/>
 76 |     <file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_ISIM_EXE" xil_pn:name="send_binary_as_ascii_tb_isim_beh.exe"/>
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 78 |     <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
 79 |     <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
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 85 |   </files>
 86 | 
 87 |   <transforms xmlns="http://www.xilinx.com/XMLSchema">
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154 |       <status xil_pn:value="ReadyToRun"/>
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156 |     <transform xil_pn:end_ts="1398813842" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="5973403865220974793" xil_pn:start_ts="1398813842">
157 |       <status xil_pn:value="SuccessfullyRun"/>
158 |       <status xil_pn:value="ReadyToRun"/>
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160 |     <transform xil_pn:end_ts="1399776951" xil_pn:in_ck="-7167022312510122820" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="-642367692445411911" xil_pn:start_ts="1399776951">
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174 |     <transform xil_pn:end_ts="1398813842" xil_pn:in_ck="8381831743836209402" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="250970745955965653" xil_pn:start_ts="1398813842">
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211 |     <transform xil_pn:end_ts="1399776986" xil_pn:in_ck="-2048707257243962743" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="6093601622908603872" xil_pn:start_ts="1399776972">
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218 |       <status xil_pn:value="OutputRemoved"/>
219 |     </transform>
220 |     <transform xil_pn:end_ts="1399776999" xil_pn:in_ck="-2744011719412916702" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="93661965788626211" xil_pn:start_ts="1399776986">
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229 |     <transform xil_pn:end_ts="1399777008" xil_pn:in_ck="2620131758334199799" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1399776999">
230 |       <status xil_pn:value="SuccessfullyRun"/>
231 |       <status xil_pn:value="WarningsGenerated"/>
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234 |       <status xil_pn:value="OutOfDateForPredecessor"/>
235 |       <status xil_pn:value="OutOfDateForOutputs"/>
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237 |       <status xil_pn:value="OutputRemoved"/>
238 |     </transform>
239 |     <transform xil_pn:end_ts="1399776999" xil_pn:in_ck="-2048707257243962875" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1399776994">
240 |       <status xil_pn:value="SuccessfullyRun"/>
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246 |       <status xil_pn:value="OutputRemoved"/>
247 |     </transform>
248 |   </transforms>
249 | 
250 | </generated_project>
251 | 


--------------------------------------------------------------------------------
/single-layer-perceptron/single-layer-perceptron.xise:
--------------------------------------------------------------------------------
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145 |     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
146 |     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
147 |     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
148 |     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
149 |     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
150 |     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
151 |     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
152 |     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
153 |     <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
154 |     <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
155 |     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
156 |     <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
157 |     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
158 |     <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
159 |     <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
160 |     <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
161 |     <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
162 |     <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
163 |     <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
164 |     <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
165 |     <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
166 |     <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
167 |     <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
168 |     <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
169 |     <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
170 |     <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
171 |     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
172 |     <property xil_pn:name="Generate Verbose Library Compilation Messages" xil_pn:value="true" xil_pn:valueState="default"/>
173 |     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
174 |     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
175 |     <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
176 |     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
177 |     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
178 |     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
179 |     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
180 |     <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
181 |     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
182 |     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
183 |     <property xil_pn:name="Ignore Version Check" xil_pn:value="false" xil_pn:valueState="default"/>
184 |     <property xil_pn:name="Implementation Top" xil_pn:value="Module|perceptron_top" xil_pn:valueState="non-default"/>
185 |     <property xil_pn:name="Implementation Top File" xil_pn:value="perceptron_top.v" xil_pn:valueState="non-default"/>
186 |     <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/perceptron_top" xil_pn:valueState="non-default"/>
187 |     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
188 |     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
189 |     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
190 |     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
191 |     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
192 |     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
193 |     <property xil_pn:name="Instance Name for Simulation in Hardware" xil_pn:value="" xil_pn:valueState="default"/>
194 |     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
195 |     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
196 |     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
197 |     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
198 |     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
199 |     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
200 |     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
201 |     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
202 |     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
203 |     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
204 |     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
205 |     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
206 |     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
207 |     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
208 |     <property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
209 |     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
210 |     <property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
211 |     <property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
212 |     <property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
213 |     <property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
214 |     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
215 |     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
216 |     <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
217 |     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
218 |     <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
219 |     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
220 |     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
221 |     <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
222 |     <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
223 |     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
224 |     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
225 |     <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
226 |     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
227 |     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
228 |     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
229 |     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
230 |     <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
231 |     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
232 |     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
233 |     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
234 |     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
235 |     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
236 |     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
237 |     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
238 |     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
239 |     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
240 |     <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
241 |     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
242 |     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
243 |     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
244 |     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
245 |     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
246 |     <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
247 |     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
248 |     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
249 |     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
250 |     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
251 |     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
252 |     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
253 |     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
254 |     <property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
255 |     <property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
256 |     <property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
257 |     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
258 |     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
259 |     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
260 |     <property xil_pn:name="Output File Name" xil_pn:value="perceptron_top" xil_pn:valueState="default"/>
261 |     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
262 |     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
263 |     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
264 |     <property xil_pn:name="Package" xil_pn:value="tqg144" xil_pn:valueState="default"/>
265 |     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
266 |     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
267 |     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
268 |     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
269 |     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
270 |     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
271 |     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
272 |     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
273 |     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
274 |     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="perceptron_top_map.v" xil_pn:valueState="default"/>
275 |     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="perceptron_top_timesim.v" xil_pn:valueState="default"/>
276 |     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="perceptron_top_synthesis.v" xil_pn:valueState="default"/>
277 |     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="perceptron_top_translate.v" xil_pn:valueState="default"/>
278 |     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
279 |     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
280 |     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
281 |     <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
282 |     <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
283 |     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
284 |     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
285 |     <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
286 |     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
287 |     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
288 |     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
289 |     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
290 |     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
291 |     <property xil_pn:name="Re-Use Last Bitstream File" xil_pn:value="false" xil_pn:valueState="default"/>
292 |     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
293 |     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
294 |     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
295 |     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
296 |     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
297 |     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
298 |     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
299 |     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
300 |     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
301 |     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
302 |     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
303 |     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
304 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
305 |     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
306 |     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
307 |     <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
308 |     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
309 |     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
310 |     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
311 |     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
312 |     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
313 |     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
314 |     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
315 |     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
316 |     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
317 |     <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
318 |     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
319 |     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
320 |     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
321 |     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
322 |     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
323 |     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
324 |     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
325 |     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/perceptron" xil_pn:valueState="non-default"/>
326 |     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.perceptron" xil_pn:valueState="non-default"/>
327 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
328 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
329 |     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
330 |     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
331 |     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
332 |     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
333 |     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
334 |     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
335 |     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
336 |     <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
337 |     <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
338 |     <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
339 |     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
340 |     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
341 |     <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
342 |     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
343 |     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
344 |     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
345 |     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
346 |     <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
347 |     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
348 |     <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
349 |     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.perceptron" xil_pn:valueState="default"/>
350 |     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
351 |     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
352 |     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
353 |     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
354 |     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
355 |     <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
356 |     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
357 |     <property xil_pn:name="Target Board for Hardware Co-Simulation" xil_pn:value="SP601 (JTAG)" xil_pn:valueState="default"/>
358 |     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
359 |     <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
360 |     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
361 |     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
362 |     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
363 |     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
364 |     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
365 |     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
366 |     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
367 |     <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/>
368 |     <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
369 |     <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/>
370 |     <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
371 |     <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
372 |     <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
373 |     <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
374 |     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
375 |     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
376 |     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
377 |     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
378 |     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
379 |     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
380 |     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
381 |     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
382 |     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
383 |     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
384 |     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
385 |     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
386 |     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
387 |     <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
388 |     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
389 |     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
390 |     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
391 |     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
392 |     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
393 |     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
394 |     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
395 |     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
396 |     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
397 |     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
398 |     <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
399 |     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
400 |     <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
401 |     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
402 |     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
403 |     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
404 |     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
405 |     <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
406 |     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
407 |     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
408 |     <!--                                                                                  -->
409 |     <!-- The following properties are for internal use only. These should not be modified.-->
410 |     <!--                                                                                  -->
411 |     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|send_binary_as_ascii_tb" xil_pn:valueState="non-default"/>
412 |     <property xil_pn:name="PROP_DesignName" xil_pn:value="single-layer-perceptron" xil_pn:valueState="non-default"/>
413 |     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
414 |     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
415 |     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
416 |     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
417 |     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
418 |     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
419 |     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
420 |     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2014-04-02T19:10:44" xil_pn:valueState="non-default"/>
421 |     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7E4E5BB7CB6C01477B737E3993DCCE8F" xil_pn:valueState="non-default"/>
422 |     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
423 |     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
424 |   </properties>
425 | 
426 |   <bindings>
427 |     <binding xil_pn:location="/perceptron_top" xil_pn:name="../../../Documents/Papilio Pro/BPM7003-Papilio-Pro-LogicStart-MegaWing-general.ucf"/>
428 |   </bindings>
429 | 
430 |   <libraries/>
431 | 
432 |   <autoManagedFiles>
433 |     <!-- The following files are identified by `include statements in verilog -->
434 |     <!-- source files and are automatically managed by Project Navigator.     -->
435 |     <!--                                                                      -->
436 |     <!-- Do not hand-edit this section, as it will be overwritten when the    -->
437 |     <!-- project is analyzed based on files automatically identified as       -->
438 |     <!-- include files.                                                       -->
439 |     <file xil_pn:name="uart_tx6.v" xil_pn:type="FILE_VERILOG"/>
440 |   </autoManagedFiles>
441 | 
442 | </project>
443 | 


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/single-layer-perceptron/uart_rx6.v:
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https://raw.githubusercontent.com/shaneleonard/neural-hardware/a8d187db3504d263f885f7696ff15c074186e8ec/single-layer-perceptron/uart_rx6.v


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/single-layer-perceptron/uart_tx6.v:
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https://raw.githubusercontent.com/shaneleonard/neural-hardware/a8d187db3504d263f885f7696ff15c074186e8ec/single-layer-perceptron/uart_tx6.v


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/single-layer-perceptron/weighted_sum_top.v:
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 1 | `timescale 1ns / 1ps
 2 | `define SPARTAN6_XC6SLX9_DSP_SLICES 16 // number of DSP48 slices on the SPARTAN 6 X9
 3 | //////////////////////////////////////////////////////////////////////////////////
 4 | // Company: 
 5 | // Engineer: Shane Leonard
 6 | // 
 7 | // Create Date:    13:17:32 04/22/2014 
 8 | // Design Name: 
 9 | // Module Name:    weighted_sum_top 
10 | // Project Name: 
11 | // Target Devices: 
12 | // Tool versions: 
13 | // Description: 
14 | //
15 | // Dependencies: 
16 | //
17 | // Revision: 
18 | // Revision 0.01 - File Created
19 | // Additional Comments: 
20 | //
21 | //////////////////////////////////////////////////////////////////////////////////
22 | module weighted_sum_top(
23 | 	input  clk,
24 | 	input  [ 18*N-1 : 0 ] x, w,
25 | 	output [ 47:0 ] sum
26 | );
27 | 
28 | parameter N = 8; // number of 18-bit inputs
29 | 
30 | // M = MIN(N, `SPARTAN6_XC6SLX9_DSP_SLICES)
31 | localparam M = `SPARTAN6_XC6SLX9_DSP_SLICES < N ? `SPARTAN6_XC6SLX9_DSP_SLICES : N;
32 | 
33 | wire [47:0] carry   [N - 1:0];
34 | wire [47:0] int_sum [N - 1:0];
35 | 
36 | weighted_sum_slice start(
37 | 	.clk  ( clk        ),
38 | 	.a    ( x[17:0]    ),
39 | 	.b    ( w[17:0]    ),
40 | 	.pcin ( 48'b0      ),
41 | 	.pcout( carry[0]   ),
42 | 	.p    ( int_sum[0] )
43 | );
44 | 
45 | generate
46 | 	genvar i;
47 | 	for (i = 1; i < M; i = i + 1)
48 | 	begin:dsp_slice
49 | 		
50 | 		wire [17:0] x_delayed, w_delayed;
51 | 
52 | 		fifo #(.WIDTH(18), .DEPTH(i)) input_fifo(
53 | 			.clk( clk                ),
54 | 			.in ( x[18*i-1:18*(i-1)] ),
55 | 			.out( x_delayed          )
56 | 		);
57 | 
58 | 		fifo #(.WIDTH(18), .DEPTH(i)) weight_fifo(
59 | 			.clk( clk               ),
60 | 			.in ( w[18*i-1:18*(i-1)]),
61 | 			.out( w_delayed         )
62 | 		);
63 | 
64 | 		weighted_sum_slice slice(
65 | 			.clk  ( clk        ),
66 | 			.a    ( x_delayed  ),
67 | 			.b    ( w_delayed  ),
68 | 			.pcin ( carry[i-1] ),
69 | 			.pcout( carry[i]   ),
70 | 			.p    ( int_sum[i] )
71 | 		);
72 | 
73 | 	end
74 | endgenerate
75 | 
76 | assign sum = int_sum[N - 1];
77 | 
78 | endmodule


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/single-layer-perceptron/weighted_sum_top_tb.v:
--------------------------------------------------------------------------------
  1 | `timescale 1ns / 1ps
  2 | 
  3 | ////////////////////////////////////////////////////////////////////////////////
  4 | // Company: 
  5 | // Engineer:
  6 | //
  7 | // Create Date:   14:03:07 04/22/2014
  8 | // Design Name:   weighted_sum_top
  9 | // Module Name:   /home/shanel/research/neural-hardware/single-layer-perceptron/weighted_sum_top_tb.v
 10 | // Project Name:  single-layer-perceptron
 11 | // Target Device:  
 12 | // Tool versions:  
 13 | // Description: 
 14 | //
 15 | // Verilog Test Fixture created by ISE for module: weighted_sum_top
 16 | //
 17 | // Dependencies:
 18 | // 
 19 | // Revision:
 20 | // Revision 0.01 - File Created
 21 | // Additional Comments:
 22 | // 
 23 | ////////////////////////////////////////////////////////////////////////////////
 24 | 
 25 | module weighted_sum_top_tb;
 26 | 
 27 | 	parameter N = 16;
 28 | 
 29 | 	// Inputs
 30 | 	reg clk;
 31 | 	reg [18*N-1:0] x, w;
 32 | 
 33 | 	reg [17:0] x_val;
 34 | 	reg [17:0] w_val;
 35 | 
 36 | 	// Outputs
 37 | 	wire [47:0] sum;
 38 | 	wire [17:0] x_delayed, w_delayed;
 39 | 
 40 | 	// Instantiate the Unit Under Test (UUT)
 41 | 	weighted_sum_top #(N) uut (
 42 | 		.clk(clk), 
 43 | 		.x(x), 
 44 | 		.w(w), 
 45 | 		.sum(sum) 
 46 | 	);
 47 | 
 48 | 	fifo #(.WIDTH(18*N*2), .DEPTH(3 + N)) input_output_sync(
 49 | 		.clk(clk),
 50 | 		.in({x_val, w_val}),
 51 | 		.out({x_delayed, w_delayed})
 52 | 	);
 53 | 
 54 | 	initial begin
 55 | 		clk = 0;
 56 | 		forever #5 clk = ~clk;
 57 | 	end
 58 | 
 59 | 	initial begin
 60 | 		// Initialize Inputs
 61 | 		x = 0;
 62 | 		w = 0;
 63 | 
 64 | 		// Wait 100 ns for global reset to finish
 65 | 		#100;
 66 | 
 67 | 		// Slight offset for clk
 68 | 		#2;
 69 |         
 70 | 		x_val = 18'd10;
 71 | 		w_val = 18'd2;
 72 | 
 73 | 		x = {N{x_val}};
 74 | 		w = {N{w_val}};
 75 | 		#10;
 76 | 
 77 |         ////////////////////////////
 78 | 		//    Add stimulus here   //
 79 |         ////////////////////////////
 80 | 		forever begin 
 81 | 			x_val = x_val + 1;
 82 | 			w_val = w_val + 1;
 83 | 			
 84 | 			x = {N{x_val}};
 85 | 			w = {N{w_val}};
 86 | 			#10;
 87 | 		end
 88 | 		////////////////////////////
 89 | 	end
 90 | 
 91 | 	always @(posedge clk) begin
 92 | 		if (N * x_delayed * w_delayed != sum) begin
 93 | 			$display("Expected %d... Got %d instead", N * x_delayed * w_delayed, sum);
 94 | 		end
 95 | 	end
 96 |       
 97 | 
 98 |     initial begin
 99 |     	
100 |     	#1000;
101 |     	$finish;
102 | 
103 |     end
104 | endmodule


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