├── asm ├── cmptest.3 ├── guess.3 ├── label.3 ├── lwitest.3 ├── lwitest.t ├── guess.t ├── label.t ├── cmptest.t ├── ahead.t ├── guess.sp ├── lwitest.sp ├── cmptest.sp └── ssays.py ├── bb ├── testcases │ ├── .gitignore │ ├── 00flat.exp │ ├── 00flat.in │ ├── 01lowest.exp │ ├── 02low.exp │ ├── 05medium.exp │ ├── 06higher.exp │ ├── 07highest.exp │ ├── 08down.exp │ ├── 10top.exp │ ├── 01lowest.in │ ├── 04simple.exp │ ├── 04simple.in │ ├── 03low.exp │ ├── 02low.in │ ├── 09down.exp │ ├── 11top.exp │ ├── 05medium.in │ ├── 03low.in │ ├── 06higher.in │ ├── README │ ├── 07highest.in │ ├── 08down.in │ ├── 10top.in │ ├── 09down.in │ └── 11top.in ├── .gitignore ├── Boards.graffle ├── Breadboard.pcb ├── trit_test.net ├── CAM-MUX │ └── CAM-MUX.zip ├── half_adder_test.fpc ├── half_adder_test.net ├── CAM-sign │ ├── CAM-sign.zip │ ├── top_paste_mask.grb │ ├── bottom_paste_mask.grb │ └── board_outline.grb ├── CAM-Logic │ ├── CAM-logic3.zip │ ├── Loading “Sunstone Circuits - Order Details”.pdf │ ├── top_paste_mask.grb │ ├── bottom_paste_mask.grb │ ├── bottom_silk.grb │ └── board_outline.grb ├── CAM-adder │ ├── CAM-adder.zip │ ├── top_paste_mask.grb │ ├── bottom_paste_mask.grb │ └── board_outline.grb ├── user_created_header.pdf ├── half_adder_test_routed.fpc ├── CAM-dtflop-msmo │ └── CAM-dtflop.zip ├── CAM-dtflop-ms2 │ └── CAM-dtflop-ms2.zip ├── CAM-swrom-blank │ ├── trinary-swrom.zip │ └── README ├── CAM-swrom-fixed │ ├── CAM-swrom-fixed.zip │ └── Loading “Sunstone Circuits - Order Details”.pdf ├── bug2.net ├── rtest.net ├── clock_gen.net ├── Inverter.net ├── bug.net ├── tnor_test.net ├── tnand_test.net ├── wikify_pads.pl ├── tg_test.net ├── tg.py ├── sti_test.net ├── Tand.net ├── NKK-SP3T-SS14MDP2.fpl ├── tinv_test.net ├── Cycle_Up.net ├── Decoder.net ├── tnand.py ├── tnor.py ├── dtflop-msmo_test.net ├── tinv.py ├── dtflop-ms2_test.net ├── mux9-3.net └── mux3-1_test.net ├── .gitignore ├── circuits ├── .gitignore ├── main.plt ├── alu_test.plt ├── clock_gen.asc ├── tnor_test.plt ├── main_cmptest.plt ├── main_jmptest.plt ├── main_lwitest.plt ├── pznflop_test.plt ├── tnor3_test.plt ├── tsign_test.plt ├── ttlatch_test.plt ├── clock_gen_test.plt ├── full_adder_test.plt ├── min_instance.asc ├── ring_oscillator.plt ├── clock_gen-fast_test.plt ├── input_p.txt ├── input_z.txt ├── input_n.txt ├── cycle_up_instance.asc ├── tpower_test.asc ├── decoder_instance.asc ├── sti.asc ├── INPUT_A.txt ├── INPUT_B.txt ├── nti.asc ├── pti.asc ├── clock_gen_test.asc ├── sp3t_test.asc ├── trit-0.asc ├── trit-1.asc ├── trit-i.asc ├── inverter_instance.asc ├── clock_gen-fast_test.asc ├── tbuf.asc ├── tsign3.asy ├── tpower.asy ├── clock_gen-fast.asc ├── fd.asc ├── rd.asc ├── decoder1-3.asy ├── clock_gen.asy ├── max.asc ├── clock_gen-fast.asy ├── shift_up.asy ├── tsign4.asy ├── shift_down.asy ├── half_subtractor.asc ├── min.asc ├── swrom.asy ├── swrom-guess.asy ├── trit_test.asc ├── swrom-cmptest.asy ├── swrom-jmptest.asy ├── swrom-lwitest.asy ├── tbuf.asy ├── sti.asy ├── dtlatch.asy ├── shift_test.plt ├── swrom-fast.asy ├── tcycle_up.asy ├── tpower.asc ├── trit-1.asy ├── tcycle_down.asy ├── trit-i.asy ├── nti.asy ├── shift_up.asc ├── swrom.asc ├── tg.asy ├── diode_test.plt ├── shift_down.asc ├── swrom_test.asc ├── dtflop.asy ├── half_adder.asy ├── half_subtractor.asy ├── pti.asy ├── tcycle_test.plt ├── trit-0.asy ├── swrom-lwitest.asc ├── dtlatch_test.asc ├── sp3t-3.asy ├── swrom-guess.asc ├── sp3t-1.asy ├── swrom-cmptest.asc ├── tsign3.asc ├── pznlatch.asy ├── ttlatch.asy ├── dtflop-msmo.asy ├── swrom-fast_test.asc ├── dtflop-et.asy ├── sp3t-2.asy ├── full_adder.asy ├── decoder1-3_test.asc ├── shift_test.asc ├── pznlatch.asc ├── mux3-1.asy ├── diode_test.asc ├── dtlatch.asc ├── pznflop.asy ├── dtflop-ms2.asc ├── swrom-jmptest.asc ├── tcycle_test.asc ├── fd.asy ├── rd.asy ├── tsign4.asc ├── dtflop2.asy ├── max.asy ├── min.asy ├── dtlatch_test.plt ├── tnand_test.plt ├── trit_reg3.asy ├── dtflop-ms2.asy ├── tnand.asy ├── tnor.asy ├── sp3t-1.asc ├── sp3t-2.asc ├── sp3t-3.asc ├── tnand_test.asc ├── tnand3.asy ├── alu.asy ├── tg_test.asc ├── tnor3.asy ├── tinv_test.plt ├── alu-fast.asy ├── tinv.asy ├── tg_test.plt ├── dtflop_test.asc ├── half_adder_test.asc ├── tnor_test.asc ├── decoder1-3_test.plt ├── tcycle_up.asc ├── tinv.asc ├── tcycle_down.asc ├── trit_reg3.asc ├── half_subtractor_test.asc ├── dtflop-et_test.asc ├── dtflop-ms2_test.asc ├── mux3-1.asc ├── decoder1-3.asc ├── dtflop.asc ├── dtflop-et_test.plt ├── swrom_test.plt ├── half_subtractor_test.plt ├── swrom-fast_test.plt ├── half_adder.asc ├── dtflop-ms2_test.plt ├── dtflop_test.plt ├── pznlatch_test.asc ├── dtflop2_test.plt ├── mux3-1_test.plt ├── control_parts.asc ├── pznlatch_test.plt ├── trit_reg3_test.asc ├── dtflop2.asc ├── tnand.asc ├── swrom-fast.asc ├── alu-fast.asc ├── tnor.asc ├── dtflop-msmo_test.plt ├── trit_reg3_test.plt ├── mux3-1_test.asc ├── dtflop-et.asc ├── swrom-blank.asc ├── tinv_test.asc ├── dtflop2_test.asc ├── pznflop.asc ├── mux9-3.asy ├── mux9-3.asc ├── pznflop_test.asc ├── alu-fast_test.plt ├── tnand3.asc └── logic_board.asc ├── digital_simulator ├── testTokenizer ├── testParser ├── Architecture.py ├── Literal.py ├── Token.py ├── Keyword.py ├── Port.py ├── Symbols.py └── Identifier.py ├── 2008 Spring-Summer Schedule.mpp ├── extended ├── Hashtable.py ├── Register.py ├── Inst_Node.py ├── Node.py └── Iloc_cnst.py └── tools └── Symbols.py /asm/cmptest.3: -------------------------------------------------------------------------------- 1 | i1i0i0ii1 -------------------------------------------------------------------------------- /asm/guess.3: -------------------------------------------------------------------------------- 1 | 1010i0ii1 -------------------------------------------------------------------------------- /asm/label.3: -------------------------------------------------------------------------------- 1 | 0000ii011 -------------------------------------------------------------------------------- /asm/lwitest.3: -------------------------------------------------------------------------------- 1 | 0000i001i -------------------------------------------------------------------------------- /bb/testcases/.gitignore: -------------------------------------------------------------------------------- 1 | *.act 2 | -------------------------------------------------------------------------------- /bb/testcases/00flat.exp: -------------------------------------------------------------------------------- 1 | R1 1 0 12k 2 | -------------------------------------------------------------------------------- /bb/testcases/00flat.in: -------------------------------------------------------------------------------- 1 | R1 1 0 12k 2 | -------------------------------------------------------------------------------- /bb/testcases/01lowest.exp: -------------------------------------------------------------------------------- 1 | R$X1$RLL 1 1 12k 2 | -------------------------------------------------------------------------------- /bb/testcases/02low.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X1$RLL 7 7 12k 2 | -------------------------------------------------------------------------------- /bb/testcases/05medium.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X2$X1$RLL 7 7 12k 2 | -------------------------------------------------------------------------------- /bb/testcases/06higher.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X3$X2$X1$RLL 7 7 12k 2 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | *.pyc 3 | *.swp 4 | *.bak 5 | CAM 6 | -------------------------------------------------------------------------------- /bb/testcases/07highest.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X4$X3$X2$X1$RLL 7 7 12k 2 | -------------------------------------------------------------------------------- /circuits/.gitignore: -------------------------------------------------------------------------------- 1 | *.raw 2 | *.log 3 | *.fft 4 | *.net 5 | -------------------------------------------------------------------------------- /bb/.gitignore: -------------------------------------------------------------------------------- 1 | *.net2 2 | *.pads 3 | ~temp$$$* 4 | *.dsn 5 | *.ses 6 | -------------------------------------------------------------------------------- /digital_simulator/testTokenizer: -------------------------------------------------------------------------------- 1 | ( hi { port "01i0001" ^ "i01010i2" 2 | -------------------------------------------------------------------------------- /bb/testcases/08down.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X4$X3$X2$X1$RLL 7 7 12k 2 | R$Xtop$RD 7 7 12k 3 | -------------------------------------------------------------------------------- /bb/Boards.graffle: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/Boards.graffle -------------------------------------------------------------------------------- /bb/Breadboard.pcb: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/Breadboard.pcb -------------------------------------------------------------------------------- /bb/trit_test.net: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/trit_test.net -------------------------------------------------------------------------------- /circuits/main.plt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/circuits/main.plt -------------------------------------------------------------------------------- /asm/lwitest.t: -------------------------------------------------------------------------------- 1 | ; Test lwi (load word immediate) instruction 2 | lwi -3 3 | lwi 2 4 | lwi 0 5 | -------------------------------------------------------------------------------- /bb/CAM-MUX/CAM-MUX.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/CAM-MUX/CAM-MUX.zip -------------------------------------------------------------------------------- /bb/half_adder_test.fpc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/half_adder_test.fpc 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-------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/CAM-adder/CAM-adder.zip -------------------------------------------------------------------------------- /bb/testcases/01lowest.in: -------------------------------------------------------------------------------- 1 | X1 1 lowest 2 | 3 | .subckt lowest LL 4 | RLL LL LL 12k 5 | .ends 6 | 7 | -------------------------------------------------------------------------------- /bb/testcases/04simple.exp: -------------------------------------------------------------------------------- 1 | R$X1$R1 1 2 12k 2 | R$X2$R1 3 4 12k 3 | R$X3$R1 5 6 12k 4 | R$X4$R1 7 8 12k 5 | -------------------------------------------------------------------------------- /bb/user_created_header.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/user_created_header.pdf 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-------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | SYMBOL min 144 176 R0 4 | SYMATTR InstName X1 5 | -------------------------------------------------------------------------------- /circuits/ring_oscillator.plt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/circuits/ring_oscillator.plt -------------------------------------------------------------------------------- /2008 Spring-Summer Schedule.mpp: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/2008 Spring-Summer Schedule.mpp -------------------------------------------------------------------------------- /circuits/clock_gen-fast_test.plt: -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /bb/CAM-swrom-fixed/CAM-swrom-fixed.zip: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/CAM-swrom-fixed/CAM-swrom-fixed.zip -------------------------------------------------------------------------------- /bb/testcases/04simple.in: -------------------------------------------------------------------------------- 1 | X1 1 2 s 2 | X2 3 4 s 3 | X3 5 6 s 4 | X4 7 8 s 5 | 6 | .subckt s A B 7 | R1 A B 12k 8 | .ends s 9 | -------------------------------------------------------------------------------- /circuits/input_p.txt: -------------------------------------------------------------------------------- 1 | 0 -5 2 | 10e-9 -5 3 | 11e-9 5 4 | 12e-9 5 5 | 13e-9 -5 6 | 40e-9 -5 7 | 41e-9 0 8 | 42e-9 0 9 | 43e-9 -5 10 | -------------------------------------------------------------------------------- /circuits/input_z.txt: -------------------------------------------------------------------------------- 1 | 0 -5 2 | 20e-9 -5 3 | 21e-9 0 4 | 22e-9 0 5 | 23e-9 -5 6 | 60e-9 -5 7 | 61e-9 5 8 | 62e-9 5 9 | 63e-9 -5 10 | -------------------------------------------------------------------------------- /bb/testcases/03low.exp: -------------------------------------------------------------------------------- 1 | R$Xtop7$X1$RLL 7 7 12k 2 | R$Xtop6$X1$RLL 6 6 12k 3 | R$Xtop5$X1$RLL 5 5 12k 4 | R$Xtop4$X1$RLL 4 4 12k 5 | R$Xtop3$X1$RLL 3 3 12k 6 | -------------------------------------------------------------------------------- /circuits/input_n.txt: -------------------------------------------------------------------------------- 1 | 0 -5 2 | 30e-9 -5 3 | 31e-9 5 4 | 32e-9 5 5 | 33e-9 -5 6 | 45e-9 -5 7 | 51e-9 -5 8 | 52e-9 0 9 | 53e-9 0 10 | 54e-9 -5 11 | -------------------------------------------------------------------------------- /bb/testcases/02low.in: -------------------------------------------------------------------------------- 1 | Xtop 7 low 2 | 3 | .subckt low L 4 | X1 L lowest 5 | .ends 6 | 7 | .subckt lowest LL 8 | RLL LL LL 12k 9 | .ends 10 | 11 | -------------------------------------------------------------------------------- /bb/testcases/09down.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X4$X3$X2$X1$RLL 7 7 12k 2 | R$Xtop$X4$X3$X2$RL 7 7 12k 3 | R$Xtop$X4$X3$RM 7 7 12k 4 | R$Xtop$X4$RH 7 7 12k 5 | R$Xtop$RD 7 7 12k 6 | -------------------------------------------------------------------------------- /circuits/cycle_up_instance.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG 16 96 CU_IN 4 | FLAG 48 96 CU_OUT 5 | SYMBOL tcycle_up 32 96 R0 6 | SYMATTR InstName X1 7 | -------------------------------------------------------------------------------- /bb/CAM-Logic/Loading “Sunstone Circuits - Order Details”.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/CAM-Logic/Loading “Sunstone Circuits - Order Details”.pdf -------------------------------------------------------------------------------- /digital_simulator/testParser: -------------------------------------------------------------------------------- 1 | 2 | entity add is 3 | port ( a, b : in trit; 4 | c : out trit ); 5 | end add ; 6 | 7 | "i1i01i0i10i10i1i01i10iiiii" 8 | 9 | -------------------------------------------------------------------------------- /asm/guess.t: -------------------------------------------------------------------------------- 1 | init: lwi -3 ; random number to guess (0i0) 2 | check: cmp in, a ; did they guess right? (ii1) 3 | be init, check ; reinit if correct, loop (1i0) 4 | -------------------------------------------------------------------------------- /bb/CAM-swrom-fixed/Loading “Sunstone Circuits - Order Details”.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shellreef/trinary/HEAD/bb/CAM-swrom-fixed/Loading “Sunstone Circuits - Order Details”.pdf -------------------------------------------------------------------------------- /asm/label.t: -------------------------------------------------------------------------------- 1 | ; Demonstrate labels 2 | foo!@#$!@#: lwi -4 3 | lwi 4 4 | ; Address is 1 trit, lwi requires 2 trits 5 | ; so specify two trits for the operand. 6 | lwi foo!@#$!@#, foo!@#$!@# 7 | -------------------------------------------------------------------------------- /circuits/tpower_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG 160 144 $G_Vdd 4 | FLAG 160 208 $G_Vss 5 | SYMBOL tpower 160 176 R0 6 | SYMATTR InstName X1 7 | TEXT 80 368 Left 0 !.op 8 | -------------------------------------------------------------------------------- /bb/testcases/11top.exp: -------------------------------------------------------------------------------- 1 | R$Xtop$X4$X3$X2$X1$RLL Xtop$7 Xtop$7 12k 2 | R$Xtop$X4$X3$X2$RL Xtop$7 Xtop$7 12k 3 | R$Xtop$X4$X3$RM Xtop$7 Xtop$7 12k 4 | R$Xtop$X4$RH Xtop$7 Xtop$7 12k 5 | R$Xtop$RD Xtop$7 Xtop$7 12k 6 | -------------------------------------------------------------------------------- /asm/cmptest.t: -------------------------------------------------------------------------------- 1 | ; Test cmp (compare) instruction and lwi (load word immediate) 2 | lwi -3 ; load A with 0i0 3 | cmp in, a ; compare A to IN (probably 10i) 4 | cmp a, in ; now S should be opposite 5 | -------------------------------------------------------------------------------- /circuits/decoder_instance.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG 48 144 DEC_IN 4 | FLAG 240 96 OUT_i 5 | FLAG 240 144 OUT_0 6 | FLAG 240 192 OUT_1 7 | SYMBOL decoder1-3 144 96 R0 8 | SYMATTR InstName X1 9 | -------------------------------------------------------------------------------- /bb/testcases/05medium.in: -------------------------------------------------------------------------------- 1 | Xtop 7 medium 2 | 3 | .subckt medium m 4 | X2 m low 5 | .ends 6 | 7 | .subckt low L 8 | X1 L lowest 9 | .ends 10 | 11 | .subckt lowest LL 12 | RLL LL LL 12k 13 | .ends 14 | 15 | -------------------------------------------------------------------------------- /bb/testcases/03low.in: -------------------------------------------------------------------------------- 1 | Xtop7 7 low 2 | Xtop6 6 low 3 | Xtop5 5 low 4 | Xtop4 4 low 5 | Xtop3 3 low 6 | 7 | .subckt low L 8 | X1 L lowest 9 | .ends 10 | 11 | .subckt lowest LL 12 | RLL LL LL 12k 13 | .ends 14 | 15 | -------------------------------------------------------------------------------- /circuits/sti.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 160 128 112 128 4 | WIRE 240 128 208 128 5 | FLAG 112 128 IN 6 | IOPIN 112 128 In 7 | FLAG 240 128 OUT 8 | IOPIN 240 128 Out 9 | SYMBOL tinv 176 128 R0 10 | SYMATTR InstName Xinv 11 | -------------------------------------------------------------------------------- /circuits/INPUT_A.txt: -------------------------------------------------------------------------------- 1 | 0 -5 2 | 50E-9 -5 3 | 60E-9 -5 4 | 110E-9 -5 5 | 120E-9 -5 6 | 170E-9 -5 7 | 180E-9 0 8 | 230E-9 0 9 | 240E-9 0 10 | 290E-9 0 11 | 300E-9 0 12 | 350E-9 0 13 | 360E-9 5 14 | 410E-9 5 15 | 420E-9 5 16 | 470E-9 5 17 | 480E-9 5 18 | 530E-9 5 -------------------------------------------------------------------------------- /circuits/INPUT_B.txt: -------------------------------------------------------------------------------- 1 | 0 -5 2 | 50E-9 -5 3 | 60E-9 0 4 | 110E-9 0 5 | 120E-9 5 6 | 170E-9 5 7 | 180E-9 -5 8 | 230E-9 -5 9 | 240E-9 0 10 | 290E-9 0 11 | 300E-9 5 12 | 350E-9 5 13 | 360E-9 -5 14 | 410E-9 -5 15 | 420E-9 0 16 | 470E-9 0 17 | 480E-9 5 18 | 530E-9 5 -------------------------------------------------------------------------------- /circuits/nti.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 176 160 144 160 4 | WIRE 208 176 192 176 5 | WIRE 224 176 208 176 6 | FLAG 144 160 IN 7 | IOPIN 144 160 In 8 | FLAG 224 176 OUT 9 | IOPIN 224 176 Out 10 | SYMBOL tinv 192 160 R0 11 | SYMATTR InstName inv 12 | -------------------------------------------------------------------------------- /circuits/pti.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 224 112 208 112 4 | WIRE 256 112 224 112 5 | WIRE 192 128 160 128 6 | FLAG 256 112 OUT 7 | IOPIN 256 112 Out 8 | FLAG 160 128 IN 9 | IOPIN 160 128 In 10 | SYMBOL tinv 208 128 R0 11 | SYMATTR InstName inv 12 | -------------------------------------------------------------------------------- /bb/testcases/06higher.in: -------------------------------------------------------------------------------- 1 | Xtop 7 higher 2 | 3 | .subckt higher h 4 | X3 h medium 5 | .ends 6 | 7 | .subckt medium m 8 | X2 m low 9 | .ends 10 | 11 | .subckt low L 12 | X1 L lowest 13 | .ends 14 | 15 | .subckt lowest LL 16 | RLL LL LL 12k 17 | .ends 18 | 19 | -------------------------------------------------------------------------------- /asm/ahead.t: -------------------------------------------------------------------------------- 1 | ; This will fail to assemble because the labels refer to future instructions. 2 | ; TCA2's asm.py doesn't currently allow this, but it is possible by using 3 | ; a two-pass assembler to first resolve the labels, then assemble. 4 | be below, below2 5 | below: lwi -3 6 | below2: cmp in, a 7 | -------------------------------------------------------------------------------- /bb/CAM-swrom-blank/README: -------------------------------------------------------------------------------- 1 | Included is the Gerber and drill files for "Trinary Computer - SWROM". 2 | 3 | Board thickness: 0.062 inches 4 | Copper weight: 1 oz 5 | Surface Finish: Hot Air Solder Leveling (HASL) if available, otherwise White Tin 6 | 7 | Please contact Jeff at (951) 235-1285 for any questions. 8 | 9 | -------------------------------------------------------------------------------- /circuits/clock_gen_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 304 160 208 160 4 | FLAG 304 160 CLK 5 | FLAG -64 112 $G_Vdd 6 | FLAG -64 176 $G_Vss 7 | SYMBOL tpower -64 144 R0 8 | SYMATTR InstName X1 9 | SYMBOL clock_gen 128 80 R0 10 | SYMATTR InstName X2 11 | TEXT 168 304 Left 0 !.tran 200u 12 | -------------------------------------------------------------------------------- /bb/testcases/README: -------------------------------------------------------------------------------- 1 | 00flat to 11top test subcircuit flattening. 2 | 3 | Run with: 4 | 5 | python ../bb.py -t 6 | 7 | Files: 8 | *.in - SPICE input deck, likely hierarchical 9 | *.exp - expected flatten SPICE deck 10 | *.act - actual SPICE deck, should match *.exp 11 | 12 | Jeff Connelly 13 | 2008-04-20 14 | -------------------------------------------------------------------------------- /circuits/sp3t_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG 416 176 $G_Vss 4 | FLAG 416 112 $G_Vdd 5 | SYMBOL sp3t-1 160 96 R0 6 | SYMATTR InstName X1 7 | SYMBOL sp3t-2 160 160 R0 8 | SYMATTR InstName X2 9 | SYMBOL sp3t-3 160 224 R0 10 | SYMATTR InstName X3 11 | SYMBOL tpower 416 144 R0 12 | SYMATTR InstName X4 13 | -------------------------------------------------------------------------------- /bb/testcases/07highest.in: -------------------------------------------------------------------------------- 1 | Xtop 7 highest 2 | 3 | .subckt highest HH 4 | X4 HH higher 5 | .ends 6 | 7 | .subckt higher h 8 | X3 h medium 9 | .ends 10 | 11 | .subckt medium m 12 | X2 m low 13 | .ends 14 | 15 | .subckt low L 16 | X1 L lowest 17 | .ends 18 | 19 | .subckt lowest LL 20 | RLL LL LL 12k 21 | .ends 22 | 23 | -------------------------------------------------------------------------------- /circuits/trit-0.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 224 96 176 96 4 | WIRE 176 128 176 96 5 | WIRE 224 144 176 144 6 | WIRE 176 192 176 160 7 | WIRE 224 192 176 192 8 | FLAG 112 144 COM 9 | IOPIN 112 144 In 10 | FLAG 224 96 $G_Vss 11 | FLAG 224 144 0 12 | FLAG 224 192 $G_Vdd 13 | SYMBOL sp3t-2 176 144 R0 14 | SYMATTR InstName sw_0 15 | -------------------------------------------------------------------------------- /circuits/trit-1.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 224 96 176 96 4 | WIRE 176 128 176 96 5 | WIRE 224 144 176 144 6 | WIRE 176 192 176 160 7 | WIRE 224 192 176 192 8 | FLAG 112 144 COM 9 | IOPIN 112 144 In 10 | FLAG 224 96 $G_Vss 11 | FLAG 224 144 0 12 | FLAG 224 192 $G_Vdd 13 | SYMBOL sp3t-3 176 144 R0 14 | SYMATTR InstName sw_1 15 | -------------------------------------------------------------------------------- /circuits/trit-i.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 224 96 176 96 4 | WIRE 176 128 176 96 5 | WIRE 224 144 176 144 6 | WIRE 176 192 176 160 7 | WIRE 224 192 176 192 8 | FLAG 112 144 COM 9 | IOPIN 112 144 In 10 | FLAG 224 96 $G_Vss 11 | FLAG 224 144 0 12 | FLAG 224 192 $G_Vdd 13 | SYMBOL sp3t-1 176 144 R0 14 | SYMATTR InstName sw_i 15 | -------------------------------------------------------------------------------- /bb/testcases/08down.in: -------------------------------------------------------------------------------- 1 | Xtop 7 highest 2 | 3 | .subckt highest HH 4 | X4 HH higher 5 | RD HH HH 12k 6 | .ends 7 | 8 | .subckt higher h 9 | X3 h medium 10 | .ends 11 | 12 | .subckt medium m 13 | X2 m low 14 | .ends 15 | 16 | .subckt low L 17 | X1 L lowest 18 | .ends 19 | 20 | .subckt lowest LL 21 | RLL LL LL 12k 22 | .ends 23 | 24 | -------------------------------------------------------------------------------- /bb/bug2.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\dtflop-ms_test.asc 2 | X0 top higher 3 | 4 | .subckt higher h 5 | X1 h medium 6 | .ends 7 | 8 | .subckt medium m 9 | X2 m low 10 | RM low2 low2 12k 11 | .ends 12 | 13 | .subckt low L L2 14 | X3 L lowest 15 | X4 L2 lowest 16 | .ends 17 | 18 | .subckt lowest LL 19 | RLL LL LL 12k 20 | .ends 21 | 22 | -------------------------------------------------------------------------------- /circuits/inverter_instance.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG 176 160 INV_IN1 4 | FLAG 208 144 PTI1 5 | FLAG 224 160 STI1 6 | FLAG 208 176 NTI1 7 | FLAG 208 240 PTI2 8 | FLAG 224 256 STI2 9 | FLAG 208 272 NTI2 10 | FLAG 176 256 INV_IN2 11 | SYMBOL tinv 192 160 R0 12 | SYMATTR InstName X1 13 | SYMBOL tinv 192 256 R0 14 | SYMATTR InstName X2 15 | -------------------------------------------------------------------------------- /circuits/clock_gen-fast_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 304 160 256 160 4 | WIRE 304 224 256 224 5 | FLAG 304 160 FETCH 6 | FLAG 304 224 EXECUTE 7 | FLAG -48 176 $G_Vdd 8 | FLAG -48 240 $G_Vss 9 | SYMBOL clock_gen 176 112 R0 10 | SYMATTR InstName cg 11 | SYMBOL tpower -48 208 R0 12 | SYMATTR InstName X1 13 | TEXT 168 304 Left 0 !.tran 100u 14 | -------------------------------------------------------------------------------- /bb/testcases/10top.in: -------------------------------------------------------------------------------- 1 | Xtop highest 2 | 3 | .subckt highest 4 | * Node 7 ends here 5 | X4 7 higher 6 | RD 7 7 12k 7 | .ends 8 | 9 | .subckt higher h h2 10 | X3 h medium 11 | .ends 12 | 13 | .subckt medium m 14 | X2 m low 15 | .ends 16 | 17 | .subckt low L 18 | X1 L lowest 19 | .ends 20 | 21 | .subckt lowest LL 22 | RLL LL LL 12k 23 | .ends 24 | 25 | -------------------------------------------------------------------------------- /circuits/tbuf.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 128 160 96 160 4 | WIRE 192 160 176 160 5 | WIRE 240 160 192 160 6 | WIRE 320 160 288 160 7 | FLAG 96 160 IN 8 | IOPIN 96 160 In 9 | FLAG 192 160 _IN 10 | FLAG 320 160 OUT 11 | IOPIN 320 160 Out 12 | SYMBOL sti 144 160 R0 13 | SYMATTR InstName Xinv1 14 | SYMBOL sti 256 160 R0 15 | SYMATTR InstName Xinv2 16 | -------------------------------------------------------------------------------- /circuits/tsign3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 96 116 -96 -17 4 | PIN -96 96 LEFT 8 5 | PINATTR PinName I0 6 | PINATTR SpiceOrder 1 7 | PIN -96 64 LEFT 8 8 | PINATTR PinName I1 9 | PINATTR SpiceOrder 2 10 | PIN -96 32 LEFT 8 11 | PINATTR PinName I2 12 | PINATTR SpiceOrder 3 13 | PIN 96 48 RIGHT 8 14 | PINATTR PinName SIGN 15 | PINATTR SpiceOrder 4 16 | -------------------------------------------------------------------------------- /bb/testcases/09down.in: -------------------------------------------------------------------------------- 1 | Xtop 7 highest 2 | 3 | .subckt highest HH 4 | X4 HH higher 5 | RD HH HH 12k 6 | .ends 7 | 8 | .subckt higher h 9 | X3 h medium 10 | RH h h 12k 11 | .ends 12 | 13 | .subckt medium m 14 | X2 m low 15 | RM m m 12k 16 | .ends 17 | 18 | .subckt low L 19 | X1 L lowest 20 | RL L L 12k 21 | .ends 22 | 23 | .subckt lowest LL 24 | RLL LL LL 12k 25 | .ends 26 | 27 | -------------------------------------------------------------------------------- /circuits/tpower.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 85 32 -79 -32 4 | TEXT -74 0 Left 0 Power Supply 5 | TEXT -7 -24 Left 0 + 6 | TEXT -3 25 Left 0 - 7 | SYMATTR Description Dual-rail +/- power supply. Connect + to $G_Vdd, and - to $G_Vss. 8 | PIN 0 -32 NONE 8 9 | PINATTR PinName Vdd 10 | PINATTR SpiceOrder 1 11 | PIN 0 32 NONE 8 12 | PINATTR PinName Vss 13 | PINATTR SpiceOrder 2 14 | -------------------------------------------------------------------------------- /circuits/clock_gen-fast.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 112 -48 80 -48 4 | FLAG 192 -48 0 5 | FLAG 80 -48 CLK 6 | SYMBOL voltage 96 -48 M90 7 | WINDOW 123 0 0 Left 0 8 | WINDOW 39 0 0 Left 0 9 | WINDOW 3 -78 187 VLeft 0 10 | SYMATTR Value PULSE(-5 5 30u 1n 1n 30u 60u) 11 | SYMATTR InstName VCLK 12 | TEXT -64 -240 Left 0 ;Clock generator, behavioral model\nFor model with 555 timer, see clock_gen.asc 13 | -------------------------------------------------------------------------------- /bb/testcases/11top.in: -------------------------------------------------------------------------------- 1 | Xtop highest 2 | 3 | .subckt highest 4 | * Node 7 ends here 5 | X4 7 higher 6 | RD 7 7 12k 7 | .ends 8 | 9 | .subckt higher h h2 10 | X3 h medium 11 | RH h h 12k 12 | .ends 13 | 14 | .subckt medium m 15 | X2 m low 16 | RM m m 12k 17 | .ends 18 | 19 | .subckt low L 20 | X1 L lowest 21 | RL L L 12k 22 | .ends 23 | 24 | .subckt lowest LL 25 | RLL LL LL 12k 26 | .ends 27 | 28 | -------------------------------------------------------------------------------- /circuits/fd.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 160 144 96 144 4 | WIRE 240 144 160 144 5 | WIRE 160 240 160 224 6 | FLAG 160 240 0 7 | FLAG 32 144 IN 8 | IOPIN 32 144 In 9 | FLAG 240 144 OUT 10 | IOPIN 240 144 Out 11 | SYMBOL diode 32 160 R270 12 | WINDOW 0 32 32 VTop 0 13 | WINDOW 3 0 32 VBottom 0 14 | SYMATTR InstName Dfd 15 | SYMBOL res 144 128 R0 16 | SYMATTR InstName Rfd 17 | SYMATTR Value 10Meg 18 | -------------------------------------------------------------------------------- /circuits/rd.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 160 144 96 144 4 | WIRE 240 144 160 144 5 | WIRE 160 240 160 224 6 | FLAG 160 240 0 7 | FLAG 32 144 IN 8 | IOPIN 32 144 In 9 | FLAG 240 144 OUT 10 | IOPIN 240 144 Out 11 | SYMBOL diode 96 160 M270 12 | WINDOW 0 32 32 VTop 0 13 | WINDOW 3 0 32 VBottom 0 14 | SYMATTR InstName Drd 15 | SYMBOL res 144 128 R0 16 | SYMATTR InstName Rrd 17 | SYMATTR Value 10Meg 18 | -------------------------------------------------------------------------------- /circuits/decoder1-3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 96 116 -96 -17 4 | TEXT -66 24 Left 0 1:3 Decoder 5 | PIN -96 48 LEFT 8 6 | PINATTR PinName IN 7 | PINATTR SpiceOrder 1 8 | PIN 96 0 RIGHT 8 9 | PINATTR PinName OUT_i 10 | PINATTR SpiceOrder 2 11 | PIN 96 48 RIGHT 8 12 | PINATTR PinName OUT_0 13 | PINATTR SpiceOrder 3 14 | PIN 96 96 RIGHT 8 15 | PINATTR PinName OUT_1 16 | PINATTR SpiceOrder 4 17 | -------------------------------------------------------------------------------- /bb/rtest.net: -------------------------------------------------------------------------------- 1 | * Based on Z:\trinary\code\circuits\tinv_test.asc 2 | V1 N001 0 -5V 3 | Xsti N001 STI_Out1 sti 4 | 5 | * block symbol definitions 6 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 7 | RP PTI_Out STI_Out 12k 8 | RN STI_Out NTI_Out 12k 9 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 10 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 11 | .ends tinv 12 | 13 | .subckt sti IN OUT 14 | XX1 IN NC_01 OUT NC_02 tinv 15 | .ends sti 16 | 17 | -------------------------------------------------------------------------------- /bb/clock_gen.net: -------------------------------------------------------------------------------- 1 | *PADS2000* 2 | *Z:\trinary\code\circuits\clock_gen.asc Fri Jul 04 13:08:26 2008* 3 | *PART* 4 | U1 8DIP300 5 | C1 CK06 6 | C2 CK06 7 | R2 RC07 8 | R1 RC07 9 | 10 | *NET* 11 | *SIGNAL* $G_Vss 12 | U1.1 C1.2 C2.2 13 | *SIGNAL* N002 14 | U1.2 U1.6 C2.1 R2.2 15 | *SIGNAL* CLK 16 | U1.3 17 | *SIGNAL* $G_Vdd 18 | U1.4 U1.8 R1.1 19 | *SIGNAL* N003 20 | U1.5 C1.1 21 | *SIGNAL* N001 22 | U1.7 R2.1 R1.2 23 | *END* 24 | -------------------------------------------------------------------------------- /circuits/clock_gen.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | TEXT -18 125 Left 0 555 8 | WINDOW 0 3 -15 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary D-type master-slave flip-flop built using transmission gates and inverters 11 | PIN 80 80 RIGHT 4 12 | PINATTR PinName CLK 13 | PINATTR SpiceOrder 1 14 | -------------------------------------------------------------------------------- /circuits/max.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -32 112 -48 112 4 | WIRE 64 128 48 128 5 | WIRE 128 128 112 128 6 | WIRE -32 144 -48 144 7 | FLAG -48 112 A 8 | IOPIN -48 112 In 9 | FLAG -48 144 B 10 | IOPIN -48 144 In 11 | FLAG 128 128 MAX_OUT 12 | IOPIN 128 128 Out 13 | FLAG 48 128 AtnorB 14 | SYMBOL tnor 0 128 R0 15 | WINDOW 0 -8 -46 Center 0 16 | SYMATTR InstName Xtnor 17 | SYMBOL sti 80 128 R0 18 | SYMATTR InstName Xsti_tor 19 | -------------------------------------------------------------------------------- /circuits/clock_gen-fast.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | TEXT -58 119 Left 0 Behavioral 8 | WINDOW 0 3 -15 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary D-type master-slave flip-flop built using transmission gates and inverters 11 | PIN 80 80 RIGHT 4 12 | PINATTR PinName CLK 13 | PINATTR SpiceOrder 1 14 | -------------------------------------------------------------------------------- /circuits/shift_up.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 0 -3 -12 11 7 | LINE Normal -6 -2 0 -3 8 | LINE Normal 2 2 0 -3 9 | WINDOW 0 1 -34 Center 0 10 | SYMATTR Description Unary trinary gate: shift up 11 | PIN -16 0 NONE 8 12 | PINATTR PinName IN 13 | PINATTR SpiceOrder 1 14 | PIN 16 0 NONE 8 15 | PINATTR PinName OUT 16 | PINATTR SpiceOrder 2 17 | -------------------------------------------------------------------------------- /circuits/tsign4.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 96 116 -96 -17 4 | PIN -96 96 LEFT 8 5 | PINATTR PinName I0 6 | PINATTR SpiceOrder 1 7 | PIN -96 64 LEFT 8 8 | PINATTR PinName I1 9 | PINATTR SpiceOrder 2 10 | PIN -96 32 LEFT 8 11 | PINATTR PinName I2 12 | PINATTR SpiceOrder 3 13 | PIN 96 48 RIGHT 8 14 | PINATTR PinName SIGN 15 | PINATTR SpiceOrder 4 16 | PIN -96 0 LEFT 8 17 | PINATTR PinName I3 18 | PINATTR SpiceOrder 5 19 | -------------------------------------------------------------------------------- /circuits/shift_down.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 3 -3 -11 9 7 | LINE Normal -11 9 -5 8 8 | LINE Normal -9 4 -11 9 9 | WINDOW 0 1 -34 Center 0 10 | SYMATTR Description Unary trinary gate: shift down 11 | PIN -16 0 NONE 8 12 | PINATTR PinName IN 13 | PINATTR SpiceOrder 1 14 | PIN 16 0 NONE 8 15 | PINATTR PinName OUT 16 | PINATTR SpiceOrder 2 17 | -------------------------------------------------------------------------------- /digital_simulator/Architecture.py: -------------------------------------------------------------------------------- 1 | # vim: set fileencoding=utf8 2 | # Architecture.py 3 | # 4 | # Architecture object. 5 | # 6 | 7 | class Architecture(object): 8 | def __init__(self, name): 9 | '''Initialize Architecture object. ''' 10 | 11 | self.name = name 12 | 13 | def __str__(self): 14 | return "" % (self.name,) 15 | 16 | if __name__ == "__main__": 17 | a = Architecture("architecture") 18 | 19 | print a -------------------------------------------------------------------------------- /circuits/half_subtractor.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 160 144 -32 144 4 | WIRE 400 144 320 144 5 | WIRE 48 192 -32 192 6 | WIRE 160 192 96 192 7 | WIRE 400 192 320 192 8 | FLAG -32 144 A 9 | IOPIN -32 144 In 10 | FLAG -32 192 B 11 | IOPIN -32 192 In 12 | FLAG 400 192 D 13 | IOPIN 400 192 Out 14 | FLAG 400 144 C 15 | IOPIN 400 144 Out 16 | SYMBOL sti 64 192 R0 17 | SYMATTR InstName negate 18 | SYMBOL half_adder 240 96 R0 19 | SYMATTR InstName X2 20 | -------------------------------------------------------------------------------- /circuits/min.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -32 112 -48 112 4 | WIRE 64 128 48 128 5 | WIRE 128 128 112 128 6 | WIRE -32 144 -48 144 7 | FLAG -48 112 A 8 | IOPIN -48 112 In 9 | FLAG -48 144 B 10 | IOPIN -48 144 In 11 | FLAG 128 128 MIN_OUT 12 | IOPIN 128 128 Out 13 | FLAG 48 128 AtnandB 14 | SYMBOL sti 80 128 R0 15 | WINDOW 0 9 -34 Center 0 16 | SYMATTR InstName Xsti_tand 17 | SYMBOL tnand 0 128 R0 18 | WINDOW 0 -9 -47 Center 0 19 | SYMATTR InstName Xtnand 20 | -------------------------------------------------------------------------------- /circuits/swrom.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 208 144 -48 -33 4 | TEXT 6 39 Left 0 3x3 SWROM 5 | SYMATTR Description 3x3 trinary SWROM loaded with guess.t 6 | PIN -48 96 LEFT 8 7 | PINATTR PinName ADDRESS 8 | PINATTR SpiceOrder 1 9 | PIN 208 0 RIGHT 8 10 | PINATTR PinName D0 11 | PINATTR SpiceOrder 2 12 | PIN 208 48 RIGHT 8 13 | PINATTR PinName D1 14 | PINATTR SpiceOrder 3 15 | PIN 208 96 RIGHT 8 16 | PINATTR PinName D2 17 | PINATTR SpiceOrder 4 18 | -------------------------------------------------------------------------------- /asm/guess.sp: -------------------------------------------------------------------------------- 1 | ; swrom-fast include file, generated to by asm/asm.py, for tritstream: 2 | ; 101 3 | ; 0i0 4 | ; ii1 5 | 6 | ; Select a voltage value based on the logic input at A 7 | .func choose(A,for_n,for_z,for_p) {if(A<={V_N_max},for_n,if(A>={V_P_min},for_p,for_z))} 8 | 9 | ; Threshold voltages 10 | .param V_N_max=-2 11 | .param V_P_min=2 12 | 13 | .func program_i(A) {choose(A,V(1),V(0),V(_1))} 14 | .func program_0(A) {choose(A,V(0),V(_1),V(_1))} 15 | .func program_1(A) {choose(A,V(1),V(0),V(1))} 16 | -------------------------------------------------------------------------------- /asm/lwitest.sp: -------------------------------------------------------------------------------- 1 | ; swrom-fast include file, generated to by asm/asm.py, for tritstream: 2 | ; 000 3 | ; 0i0 4 | ; 01i 5 | 6 | ; Select a voltage value based on the logic input at A 7 | .func choose(A,for_n,for_z,for_p) {if(A<={V_N_max},for_n,if(A>={V_P_min},for_p,for_z))} 8 | 9 | ; Threshold voltages 10 | .param V_N_max=-2 11 | .param V_P_min=2 12 | 13 | .func program_i(A) {choose(A,V(0),V(0),V(0))} 14 | .func program_0(A) {choose(A,V(0),V(_1),V(1))} 15 | .func program_1(A) {choose(A,V(0),V(0),V(_1))} 16 | -------------------------------------------------------------------------------- /asm/cmptest.sp: -------------------------------------------------------------------------------- 1 | ; swrom-fast include file, generated to by asm/asm.py, for tritstream: 2 | ; i1i 3 | ; 0i0 4 | ; ii1 5 | 6 | ; Select a voltage value based on the logic input at A 7 | .func choose(A,for_n,for_z,for_p) {if(A<={V_N_max},for_n,if(A>={V_P_min},for_p,for_z))} 8 | 9 | ; Threshold voltages 10 | .param V_N_max=-2 11 | .param V_P_min=2 12 | 13 | .func program_i(A) {choose(A,V(_1),V(0),V(_1))} 14 | .func program_0(A) {choose(A,V(1),V(_1),V(_1))} 15 | .func program_1(A) {choose(A,V(_1),V(0),V(1))} 16 | -------------------------------------------------------------------------------- /circuits/swrom-guess.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 208 144 -48 -33 4 | TEXT 6 39 Left 0 3x3 SWROM 5 | TEXT 46 130 Left 0 guess 6 | SYMATTR Description 3x3 trinary SWROM loaded with cmptest 7 | PIN -48 96 LEFT 8 8 | PINATTR PinName ADDRESS 9 | PINATTR SpiceOrder 1 10 | PIN 208 0 RIGHT 8 11 | PINATTR PinName D0 12 | PINATTR SpiceOrder 2 13 | PIN 208 48 RIGHT 8 14 | PINATTR PinName D1 15 | PINATTR SpiceOrder 3 16 | PIN 208 96 RIGHT 8 17 | PINATTR PinName D2 18 | PINATTR SpiceOrder 4 19 | -------------------------------------------------------------------------------- /circuits/trit_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 224 96 192 96 4 | WIRE 224 176 192 176 5 | WIRE 224 256 192 256 6 | FLAG -16 144 $G_Vdd 7 | FLAG -16 208 $G_Vss 8 | FLAG 224 96 TRIT_i 9 | FLAG 224 176 TRIT_0 10 | FLAG 224 256 TRIT_1 11 | SYMBOL trit-i 128 96 M0 12 | SYMATTR InstName trit_i 13 | SYMBOL tpower -16 176 R0 14 | SYMATTR InstName power 15 | SYMBOL trit-0 128 176 M0 16 | SYMATTR InstName trit_0 17 | SYMBOL trit-1 128 256 M0 18 | SYMATTR InstName trit_1 19 | TEXT 184 320 Left 0 !.op 20 | -------------------------------------------------------------------------------- /circuits/swrom-cmptest.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 208 144 -48 -33 4 | TEXT 6 39 Left 0 3x3 SWROM 5 | TEXT 46 130 Left 0 cmptest 6 | SYMATTR Description 3x3 trinary SWROM loaded with cmptest 7 | PIN -48 96 LEFT 8 8 | PINATTR PinName ADDRESS 9 | PINATTR SpiceOrder 1 10 | PIN 208 0 RIGHT 8 11 | PINATTR PinName D0 12 | PINATTR SpiceOrder 2 13 | PIN 208 48 RIGHT 8 14 | PINATTR PinName D1 15 | PINATTR SpiceOrder 3 16 | PIN 208 96 RIGHT 8 17 | PINATTR PinName D2 18 | PINATTR SpiceOrder 4 19 | -------------------------------------------------------------------------------- /circuits/swrom-jmptest.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 208 144 -48 -33 4 | TEXT 6 39 Left 0 3x3 SWROM 5 | TEXT 37 125 Left 0 jmptest 6 | SYMATTR Description 3x3 trinary SWROM loaded with jmptest 7 | PIN -48 96 LEFT 8 8 | PINATTR PinName ADDRESS 9 | PINATTR SpiceOrder 1 10 | PIN 208 0 RIGHT 8 11 | PINATTR PinName D0 12 | PINATTR SpiceOrder 2 13 | PIN 208 48 RIGHT 8 14 | PINATTR PinName D1 15 | PINATTR SpiceOrder 3 16 | PIN 208 96 RIGHT 8 17 | PINATTR PinName D2 18 | PINATTR SpiceOrder 4 19 | -------------------------------------------------------------------------------- /circuits/swrom-lwitest.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 208 144 -48 -33 4 | TEXT 6 39 Left 0 3x3 SWROM 5 | TEXT 46 130 Left 0 lwitest 6 | SYMATTR Description 3x3 trinary SWROM loaded with lwitest 7 | PIN -48 96 LEFT 8 8 | PINATTR PinName ADDRESS 9 | PINATTR SpiceOrder 1 10 | PIN 208 0 RIGHT 8 11 | PINATTR PinName D0 12 | PINATTR SpiceOrder 2 13 | PIN 208 48 RIGHT 8 14 | PINATTR PinName D1 15 | PINATTR SpiceOrder 3 16 | PIN 208 96 RIGHT 8 17 | PINATTR PinName D2 18 | PINATTR SpiceOrder 4 19 | -------------------------------------------------------------------------------- /circuits/tbuf.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 11 0 -14 -12 7 | LINE Normal -14 14 11 0 8 | LINE Normal -14 -12 -14 14 9 | LINE Normal 32 0 24 0 10 | LINE Normal 16 0 24 0 11 | WINDOW 0 -5 -33 Center 0 12 | SYMATTR Description Unary trinary gate: simple ternary inverter 13 | PIN -16 0 NONE 8 14 | PINATTR PinName IN 15 | PINATTR SpiceOrder 1 16 | PIN 32 0 NONE 8 17 | PINATTR PinName OUT 18 | PINATTR SpiceOrder 2 19 | -------------------------------------------------------------------------------- /circuits/sti.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 11 0 -14 -12 7 | LINE Normal -14 14 11 0 8 | LINE Normal -14 -12 -14 14 9 | LINE Normal 32 0 24 0 10 | CIRCLE Normal 24 4 16 -4 11 | WINDOW 0 -5 -33 Center 0 12 | SYMATTR Description Unary trinary gate: simple ternary inverter 13 | PIN -16 0 NONE 8 14 | PINATTR PinName IN 15 | PINATTR SpiceOrder 1 16 | PIN 32 0 NONE 8 17 | PINATTR PinName OUT 18 | PINATTR SpiceOrder 2 19 | -------------------------------------------------------------------------------- /bb/Inverter.net: -------------------------------------------------------------------------------- 1 | * Z:\College\Senior Year\Trinary Research Project\trinary\circuits\Inverter.asc 2 | XX1 INV_IN1 PTI1 STI1 NTI1 tinv 3 | XX2 INV_IN2 PTI2 STI2 NTI2 tinv 4 | 5 | * block symbol definitions 6 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 7 | RP PTI_Out STI_Out 12k 8 | RN STI_Out NTI_Out 12k 9 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 10 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 11 | .ends tinv 12 | 13 | .model NMOS NMOS 14 | .model PMOS PMOS 15 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 16 | .backanno 17 | .end 18 | -------------------------------------------------------------------------------- /circuits/dtlatch.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | CIRCLE Normal 96 104 80 88 8 | WINDOW 0 -1 -17 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary D-type transparent latch 11 | PIN -80 64 LEFT 8 12 | PINATTR PinName D 13 | PINATTR SpiceOrder 1 14 | PIN 80 48 RIGHT 4 15 | PINATTR PinName Q 16 | PINATTR SpiceOrder 2 17 | PIN 96 96 RIGHT 20 18 | PINATTR PinName _Q 19 | PINATTR SpiceOrder 3 20 | -------------------------------------------------------------------------------- /circuits/shift_test.plt: -------------------------------------------------------------------------------- 1 | [DC transfer characteristic] 2 | { 3 | Npanes: 2 4 | { 5 | traces: 1 {524290,0,"V(shift_up)"} 6 | X: (' ',0,-5,1,5) 7 | Y[0]: (' ',0,-6,1,6) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,1,-6,1,6) 10 | Log: 0 0 0 11 | }, 12 | { 13 | traces: 1 {524291,0,"V(shift_down)"} 14 | X: (' ',0,-5,1,5) 15 | Y[0]: (' ',0,-6,1,6) 16 | Y[1]: ('_',0,1e+308,0,-1e+308) 17 | Volts: (' ',0,0,1,-6,1,6) 18 | Log: 0 0 0 19 | } 20 | } 21 | -------------------------------------------------------------------------------- /circuits/swrom-fast.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 208 144 -48 -33 4 | TEXT 6 39 Left 0 3x3 SWROM 5 | TEXT -41 131 Left 0 BEHAVORIAL MODEL 6 | SYMATTR Description Behavorial model of 3x3 trinary SWROM loaded with guess.t 7 | PIN -48 96 LEFT 8 8 | PINATTR PinName ADDRESS 9 | PINATTR SpiceOrder 1 10 | PIN 208 0 RIGHT 8 11 | PINATTR PinName D0 12 | PINATTR SpiceOrder 2 13 | PIN 208 48 RIGHT 8 14 | PINATTR PinName D1 15 | PINATTR SpiceOrder 3 16 | PIN 208 96 RIGHT 8 17 | PINATTR PinName D2 18 | PINATTR SpiceOrder 4 19 | -------------------------------------------------------------------------------- /bb/bug.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\dtflop-ms_test.asc 2 | X0 higher DATA1 DATA2 DATA3 higher 3 | 4 | .subckt higher D1 D2 D3 5 | Xflipflop D1 CLK1 QQQ1 dtflop-ms 6 | Xflipflop D2 CLK2 QQQ2 dtflop-ms 7 | Xflipflop D3 CLK3 QQQ3 dtflop-ms 8 | .ends 9 | 10 | .subckt dtflop-ms D C Q 11 | X1 D Q sti 12 | X2 C _C sti 13 | .ends dtflop-ms 14 | 15 | .subckt sti IN OUT 16 | Xinv IN NC_01 OUT NC_02 tinv 17 | .ends sti 18 | 19 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 20 | RP PTI_Out STI_Out 12k 21 | RN STI_Out NTI_Out 12k 22 | .ends tinv 23 | 24 | -------------------------------------------------------------------------------- /circuits/tcycle_up.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 4 1 -12 -8 7 | LINE Normal -12 10 4 1 8 | LINE Normal -12 3 -12 10 9 | LINE Normal -3 5 -9 5 10 | LINE Normal -6 10 -3 5 11 | LINE Normal -8 -6 -2 -6 12 | LINE Normal -6 -1 -8 -6 13 | WINDOW 0 2 -34 Center 0 14 | SYMATTR Description Unary trinary gate: cycle up 15 | PIN -16 0 NONE 8 16 | PINATTR PinName IN 17 | PINATTR SpiceOrder 1 18 | PIN 16 0 NONE 8 19 | PINATTR PinName OUT 20 | PINATTR SpiceOrder 2 21 | -------------------------------------------------------------------------------- /circuits/tpower.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -112 32 -320 32 4 | WIRE -112 112 -224 112 5 | WIRE -112 128 -112 112 6 | WIRE -224 144 -224 112 7 | WIRE -112 208 -320 208 8 | FLAG -224 144 0 9 | FLAG -320 32 Vdd 10 | IOPIN -320 32 Out 11 | FLAG -320 208 Vss 12 | IOPIN -320 208 Out 13 | SYMBOL voltage -112 16 R0 14 | WINDOW 0 26 26 Left 0 15 | WINDOW 3 34 68 Left 0 16 | SYMATTR InstName Vdd 17 | SYMATTR Value 5V 18 | SYMBOL voltage -112 112 R0 19 | WINDOW 0 26 34 Left 0 20 | WINDOW 3 31 80 Left 0 21 | SYMATTR InstName Vss 22 | SYMATTR Value 5V 23 | -------------------------------------------------------------------------------- /circuits/trit-1.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 0 -64 0 4 | LINE Normal -16 0 0 0 5 | LINE Normal -25 -16 0 -16 6 | LINE Normal -25 16 0 16 7 | LINE Normal -31 14 -48 0 8 | LINE Normal -31 8 -31 14 9 | LINE Normal -36 14 -31 14 10 | CIRCLE Normal -25 -13 -31 -19 11 | CIRCLE Normal -16 3 -22 -3 12 | CIRCLE Normal -25 19 -31 13 13 | TEXT -1 -19 Left 0 _1 14 | TEXT 0 0 Left 0 0 15 | TEXT -1 19 Left 0 1 16 | SYMATTR Description User input switch defaulting to trit 1. 17 | PIN -64 0 NONE 8 18 | PINATTR PinName COM 19 | PINATTR SpiceOrder 1 20 | -------------------------------------------------------------------------------- /circuits/tcycle_down.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 4 1 -12 -8 7 | LINE Normal -12 10 4 1 8 | LINE Normal -12 3 -12 10 9 | LINE Normal -3 -3 -8 -3 10 | LINE Normal -3 -8 -3 -3 11 | LINE Normal -7 7 -5 2 12 | LINE Normal -2 7 -7 7 13 | WINDOW 0 1 -34 Center 0 14 | SYMATTR Description Unary trinary gate: cycle down 15 | PIN -16 0 NONE 8 16 | PINATTR PinName IN 17 | PINATTR SpiceOrder 1 18 | PIN 16 0 NONE 8 19 | PINATTR PinName OUT 20 | PINATTR SpiceOrder 2 21 | -------------------------------------------------------------------------------- /circuits/trit-i.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 0 -64 0 4 | LINE Normal -16 0 0 0 5 | LINE Normal -25 -16 0 -16 6 | LINE Normal -25 16 0 16 7 | LINE Normal -37 -13 -30 -14 8 | LINE Normal -30 -14 -29 -7 9 | LINE Normal -30 -14 -48 0 10 | CIRCLE Normal -25 -13 -31 -19 11 | CIRCLE Normal -16 3 -22 -3 12 | CIRCLE Normal -25 19 -31 13 13 | TEXT -1 -19 Left 0 _1 14 | TEXT 0 0 Left 0 0 15 | TEXT -1 19 Left 0 1 16 | SYMATTR Description User input switch defaulting to trit i. 17 | PIN -64 0 NONE 8 18 | PINATTR PinName COM 19 | PINATTR SpiceOrder 1 20 | -------------------------------------------------------------------------------- /circuits/nti.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 11 0 -14 -12 7 | LINE Normal -14 14 11 0 8 | LINE Normal -14 -12 -14 14 9 | LINE Normal -1 1 -11 1 10 | LINE Normal -1 1 -2 1 11 | LINE Normal 32 0 24 0 12 | CIRCLE Normal 24 4 16 -4 13 | WINDOW 0 1 -32 Center 0 14 | SYMATTR Description Unary trinary gate: negative ternary inverter 15 | PIN -16 0 NONE 8 16 | PINATTR PinName IN 17 | PINATTR SpiceOrder 1 18 | PIN 32 0 NONE 8 19 | PINATTR PinName OUT 20 | PINATTR SpiceOrder 2 21 | -------------------------------------------------------------------------------- /asm/ssays.py: -------------------------------------------------------------------------------- 1 | # Created:200803010 2 | # By Jeff Connelly 3 | # 4 | # Trinary Simon Says (very high level, prototype for asm) 5 | 6 | import sys 7 | import random 8 | 9 | print "(Enter what Simon Says as [0,-1,1], for example)\n" 10 | 11 | while True: 12 | said = [ 13 | random.randint(-1,1), 14 | random.randint(-1,1), 15 | random.randint(-1,1)] 16 | print "Simon Says:",said 17 | user = None 18 | while user != said: 19 | try: 20 | user = input() 21 | except: 22 | continue 23 | print "Correct!\n" 24 | 25 | -------------------------------------------------------------------------------- /circuits/shift_up.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 144 192 112 192 4 | WIRE 208 192 192 192 5 | WIRE 304 192 272 192 6 | WIRE 336 192 304 192 7 | FLAG 112 192 IN 8 | IOPIN 112 192 In 9 | FLAG 384 192 OUT 10 | IOPIN 384 192 Out 11 | FLAG 304 272 0 12 | SYMBOL diode 272 176 R90 13 | WINDOW 0 0 32 VBottom 0 14 | WINDOW 3 32 32 VTop 0 15 | SYMATTR InstName Xrd 16 | SYMATTR Value 1N4148 17 | SYMBOL sti 352 192 R0 18 | SYMATTR InstName Xsti 19 | SYMBOL nti 160 192 R0 20 | SYMATTR InstName Xnti 21 | SYMBOL res 288 176 R0 22 | SYMATTR InstName Rrd 23 | SYMATTR Value 10Meg 24 | -------------------------------------------------------------------------------- /circuits/swrom.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 192 128 160 128 4 | WIRE 192 160 160 160 5 | WIRE 192 192 160 192 6 | WIRE 96 400 96 368 7 | FLAG 96 400 ADDRESS 8 | IOPIN 96 400 In 9 | FLAG 192 128 D0 10 | IOPIN 192 128 Out 11 | FLAG 192 160 D1 12 | IOPIN 192 160 Out 13 | FLAG 192 192 D2 14 | IOPIN 192 192 Out 15 | FLAG 48 32 0 16 | FLAG 48 64 $G_Vss 17 | FLAG 48 96 $G_Vss 18 | FLAG 48 144 $G_Vdd 19 | FLAG 48 176 $G_Vss 20 | FLAG 48 208 $G_Vss 21 | FLAG 48 256 0 22 | FLAG 48 288 $G_Vdd 23 | FLAG 48 320 $G_Vdd 24 | SYMBOL mux9-3 112 32 R0 25 | SYMATTR InstName X1 26 | -------------------------------------------------------------------------------- /circuits/tg.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 16 18 16 -16 7 | LINE Normal 16 18 -16 0 8 | LINE Normal -16 0 16 -16 9 | LINE Normal 0 9 0 16 10 | WINDOW 0 1 -34 Center 0 11 | SYMATTR Description Bidirectional transmission gate with integrated inverters 12 | PIN -16 0 NONE 8 13 | PINATTR PinName IN_OUT 14 | PINATTR SpiceOrder 1 15 | PIN 16 0 NONE 8 16 | PINATTR PinName OUT_IN 17 | PINATTR SpiceOrder 2 18 | PIN 0 16 NONE 8 19 | PINATTR PinName CONTROL 20 | PINATTR SpiceOrder 3 21 | -------------------------------------------------------------------------------- /circuits/diode_test.plt: -------------------------------------------------------------------------------- 1 | [DC transfer characteristic] 2 | { 3 | Npanes: 2 4 | { 5 | traces: 1 {524291,0,"V(rd)"} 6 | X: (' ',0,-5,1,5) 7 | Y[0]: (' ',1,-5,0.5,0.5) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,0,-5,0.5,0.5) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 1 {524290,0,"V(fd)"} 15 | X: (' ',0,-5,1,5) 16 | Y[0]: (' ',1,-0.5,0.5,5) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,-0.5,0.5,5) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | } 22 | } 23 | -------------------------------------------------------------------------------- /circuits/shift_down.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 144 192 112 192 4 | WIRE 208 192 192 192 5 | WIRE 304 192 272 192 6 | WIRE 336 192 304 192 7 | FLAG 112 192 IN 8 | IOPIN 112 192 In 9 | FLAG 384 192 OUT 10 | IOPIN 384 192 Out 11 | FLAG 304 272 0 12 | SYMBOL diode 208 176 M90 13 | WINDOW 0 0 32 VBottom 0 14 | WINDOW 3 32 32 VTop 0 15 | SYMATTR InstName Xfd 16 | SYMATTR Value 1N4148 17 | SYMBOL sti 352 192 R0 18 | SYMATTR InstName Xsti 19 | SYMBOL res 288 176 R0 20 | SYMATTR InstName Rfd 21 | SYMATTR Value 10Meg 22 | SYMBOL pti 160 192 R0 23 | SYMATTR InstName Xpti 24 | -------------------------------------------------------------------------------- /circuits/swrom_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 416 80 320 80 4 | WIRE 416 128 320 128 5 | WIRE 64 176 -32 176 6 | WIRE 416 176 320 176 7 | WIRE -32 224 -32 176 8 | FLAG 416 80 D0 9 | FLAG 416 128 D1 10 | FLAG 416 176 D2 11 | FLAG -32 304 0 12 | FLAG -192 32 $G_Vdd 13 | FLAG -192 96 $G_Vss 14 | FLAG -32 176 ADDRESS 15 | SYMBOL voltage -32 208 R0 16 | SYMATTR InstName A 17 | SYMATTR Value PWL(0 -5 14n -5 15n 0 29n 0 30n 5) 18 | SYMBOL tpower -192 64 R0 19 | SYMATTR InstName X2 20 | SYMBOL swrom 112 80 R0 21 | SYMATTR InstName X1 22 | TEXT -64 336 Left 0 !.tran 40n 23 | -------------------------------------------------------------------------------- /circuits/dtflop.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | CIRCLE Normal 96 104 80 88 8 | WINDOW 0 3 -15 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary D-type flip-flop 11 | PIN -80 48 LEFT 8 12 | PINATTR PinName D 13 | PINATTR SpiceOrder 1 14 | PIN -80 96 LEFT 8 15 | PINATTR PinName CLK 16 | PINATTR SpiceOrder 2 17 | PIN 80 48 RIGHT 4 18 | PINATTR PinName Q 19 | PINATTR SpiceOrder 3 20 | PIN 96 96 RIGHT 20 21 | PINATTR PinName _Q 22 | PINATTR SpiceOrder 4 23 | -------------------------------------------------------------------------------- /circuits/half_adder.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | TEXT -70 70 Left 0 + 8 | WINDOW 0 -1 -17 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary half-adder (2 trits) 11 | PIN -80 48 LEFT 8 12 | PINATTR PinName A 13 | PINATTR SpiceOrder 1 14 | PIN 80 48 RIGHT 4 15 | PINATTR PinName C 16 | PINATTR SpiceOrder 2 17 | PIN 80 96 RIGHT 4 18 | PINATTR PinName S 19 | PINATTR SpiceOrder 3 20 | PIN -80 96 LEFT 8 21 | PINATTR PinName B 22 | PINATTR SpiceOrder 4 23 | -------------------------------------------------------------------------------- /circuits/half_subtractor.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | TEXT -68 68 Left 0 - 8 | WINDOW 0 -1 -17 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary half-adder (2 trits) 11 | PIN -80 48 LEFT 8 12 | PINATTR PinName A 13 | PINATTR SpiceOrder 1 14 | PIN 80 48 RIGHT 4 15 | PINATTR PinName C 16 | PINATTR SpiceOrder 2 17 | PIN 80 96 RIGHT 4 18 | PINATTR PinName D 19 | PINATTR SpiceOrder 3 20 | PIN -80 96 LEFT 8 21 | PINATTR PinName B 22 | PINATTR SpiceOrder 4 23 | -------------------------------------------------------------------------------- /circuits/pti.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 11 0 -14 -12 7 | LINE Normal -14 14 11 0 8 | LINE Normal -14 -12 -14 14 9 | LINE Normal -6 7 -6 -4 10 | LINE Normal -1 1 -11 1 11 | LINE Normal -1 1 -2 1 12 | LINE Normal 32 0 24 0 13 | CIRCLE Normal 24 4 16 -4 14 | WINDOW 0 1 -32 Center 0 15 | SYMATTR Description Unary trinary gate: positive ternary inverter 16 | PIN -16 0 NONE 8 17 | PINATTR PinName IN 18 | PINATTR SpiceOrder 1 19 | PIN 32 0 NONE 8 20 | PINATTR PinName OUT 21 | PINATTR SpiceOrder 2 22 | -------------------------------------------------------------------------------- /circuits/tcycle_test.plt: -------------------------------------------------------------------------------- 1 | [DC transfer characteristic] 2 | { 3 | Npanes: 2 4 | Active Pane: 1 5 | { 6 | traces: 1 {268959746,0,"V(cycle_down)"} 7 | X: (' ',0,-5,1,5) 8 | Y[0]: (' ',0,-5,1,5) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-5,1,5) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524291,0,"V(cycle_up)"} 16 | X: (' ',0,-5,1,5) 17 | Y[0]: (' ',0,-5,1,5) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,0,-5,1,5) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | } 23 | } 24 | -------------------------------------------------------------------------------- /circuits/trit-0.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 0 -64 0 4 | LINE Normal -16 0 0 0 5 | LINE Normal -25 -16 0 -16 6 | LINE Normal -25 16 0 16 7 | LINE Normal -23 0 -48 0 8 | LINE Normal -22 0 -24 0 9 | LINE Normal -27 -4 -22 0 10 | LINE Normal -26 3 -22 0 11 | LINE Normal -27 4 -26 3 12 | CIRCLE Normal -25 -13 -31 -19 13 | CIRCLE Normal -16 3 -22 -3 14 | CIRCLE Normal -25 19 -31 13 15 | TEXT -1 -19 Left 0 _1 16 | TEXT 0 0 Left 0 0 17 | TEXT -1 19 Left 0 1 18 | SYMATTR Description User input switch defaulting to trit 0. 19 | PIN -64 0 NONE 8 20 | PINATTR PinName COM 21 | PINATTR SpiceOrder 1 22 | -------------------------------------------------------------------------------- /digital_simulator/Literal.py: -------------------------------------------------------------------------------- 1 | # vim: set fileencoding=utf8 2 | # Integer.py 3 | # 4 | # A literal is an integer. 5 | # 6 | 7 | class Literal(object): 8 | def __init__(self, value = 0): 9 | '''Initialize Literal object. 10 | value: integer value given to object. ''' 11 | 12 | if not isinstance(value, int): 13 | raise "Invalid integer value detected: |%s|" % (value, ) 14 | self.value = value 15 | 16 | def __str__(self): 17 | return "" % (self.value,) 18 | 19 | if __name__ == "__main__": 20 | a = Literal(4) 21 | b = Literal(5) 22 | 23 | print a, b -------------------------------------------------------------------------------- /circuits/swrom-lwitest.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 192 128 160 128 4 | WIRE 192 160 160 160 5 | WIRE 192 192 160 192 6 | WIRE 96 400 96 368 7 | FLAG 96 400 ADDRESS 8 | IOPIN 96 400 In 9 | FLAG 192 128 D0 10 | IOPIN 192 128 Out 11 | FLAG 192 160 D1 12 | IOPIN 192 160 Out 13 | FLAG 192 192 D2 14 | IOPIN 192 192 Out 15 | FLAG 48 32 0 16 | FLAG 48 64 0 17 | FLAG 48 96 0 18 | FLAG 48 144 0 19 | FLAG 48 176 $G_Vss 20 | FLAG 48 208 0 21 | FLAG 48 256 0 22 | FLAG 48 288 $G_Vdd 23 | FLAG 48 320 $G_Vss 24 | SYMBOL mux9-3 112 32 R0 25 | SYMATTR InstName X1 26 | TEXT -288 112 Left 0 ;Assembled from lwitest.t 27 | -------------------------------------------------------------------------------- /circuits/dtlatch_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 320 96 256 96 4 | WIRE 96 112 16 112 5 | WIRE 320 144 272 144 6 | WIRE 16 160 16 112 7 | WIRE 16 288 16 240 8 | FLAG 16 288 0 9 | FLAG 320 96 Q 10 | FLAG 320 144 _Q 11 | FLAG 16 112 D 12 | FLAG -112 64 $G_Vdd 13 | FLAG -112 128 $G_Vss 14 | SYMBOL voltage 16 144 R0 15 | WINDOW 123 0 0 Left 0 16 | WINDOW 39 0 0 Left 0 17 | SYMATTR InstName V1 18 | SYMATTR Value PWL(0 -5 10n -5 11n 0 20n 0 21n 5 30n 5 31n -5 40n -5) 19 | SYMBOL dtlatch 176 48 R0 20 | SYMATTR InstName X1 21 | SYMBOL tpower -112 96 R0 22 | SYMATTR InstName X2 23 | TEXT 64 304 Left 0 !.tran 40n 24 | -------------------------------------------------------------------------------- /circuits/sp3t-3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 0 -64 0 4 | LINE Normal -16 0 0 0 5 | LINE Normal -25 -16 0 -16 6 | LINE Normal -25 16 0 16 7 | LINE Normal -31 14 -48 0 8 | LINE Normal -31 8 -31 14 9 | LINE Normal -36 14 -31 14 10 | CIRCLE Normal -25 -13 -31 -19 11 | CIRCLE Normal -16 3 -22 -3 12 | CIRCLE Normal -25 19 -31 13 13 | PIN 0 -16 NONE 8 14 | PINATTR PinName 1 15 | PINATTR SpiceOrder 1 16 | PIN 0 0 NONE 8 17 | PINATTR PinName 2 18 | PINATTR SpiceOrder 2 19 | PIN 0 16 NONE 8 20 | PINATTR PinName 3 21 | PINATTR SpiceOrder 4 22 | PIN -64 0 NONE 8 23 | PINATTR PinName COM 24 | PINATTR SpiceOrder 3 25 | -------------------------------------------------------------------------------- /circuits/swrom-guess.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 192 128 160 128 4 | WIRE 192 160 160 160 5 | WIRE 192 192 160 192 6 | WIRE 96 400 96 368 7 | FLAG 96 400 ADDRESS 8 | IOPIN 96 400 In 9 | FLAG 192 128 D0 10 | IOPIN 192 128 Out 11 | FLAG 192 160 D1 12 | IOPIN 192 160 Out 13 | FLAG 192 192 D2 14 | IOPIN 192 192 Out 15 | FLAG 48 32 $G_Vdd 16 | FLAG 48 64 0 17 | FLAG 48 96 $G_Vdd 18 | FLAG 48 144 0 19 | FLAG 48 176 $G_Vss 20 | FLAG 48 208 0 21 | FLAG 48 256 $G_Vss 22 | FLAG 48 288 $G_Vss 23 | FLAG 48 320 $G_Vdd 24 | SYMBOL mux9-3 112 32 R0 25 | SYMATTR InstName X1 26 | TEXT -376 152 Left 0 ;Assembled from guess.t 27 | -------------------------------------------------------------------------------- /circuits/sp3t-1.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 0 -64 0 4 | LINE Normal -16 0 0 0 5 | LINE Normal -25 -16 0 -16 6 | LINE Normal -25 16 0 16 7 | LINE Normal -37 -13 -30 -14 8 | LINE Normal -30 -14 -29 -7 9 | LINE Normal -30 -14 -48 0 10 | CIRCLE Normal -25 -13 -31 -19 11 | CIRCLE Normal -16 3 -22 -3 12 | CIRCLE Normal -25 19 -31 13 13 | PIN 0 -16 NONE 8 14 | PINATTR PinName 1 15 | PINATTR SpiceOrder 1 16 | PIN 0 0 NONE 8 17 | PINATTR PinName 2 18 | PINATTR SpiceOrder 2 19 | PIN 0 16 NONE 8 20 | PINATTR PinName 3 21 | PINATTR SpiceOrder 4 22 | PIN -64 0 NONE 8 23 | PINATTR PinName COM 24 | PINATTR SpiceOrder 3 25 | -------------------------------------------------------------------------------- /circuits/swrom-cmptest.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 192 128 160 128 4 | WIRE 192 160 160 160 5 | WIRE 192 192 160 192 6 | WIRE 96 400 96 368 7 | FLAG 96 400 ADDRESS 8 | IOPIN 96 400 In 9 | FLAG 192 128 D0 10 | IOPIN 192 128 Out 11 | FLAG 192 160 D1 12 | IOPIN 192 160 Out 13 | FLAG 192 192 D2 14 | IOPIN 192 192 Out 15 | FLAG 48 32 $G_Vss 16 | FLAG 48 64 $G_Vdd 17 | FLAG 48 96 $G_Vss 18 | FLAG 48 144 0 19 | FLAG 48 176 $G_Vss 20 | FLAG 48 208 0 21 | FLAG 48 256 $G_Vss 22 | FLAG 48 288 $G_Vss 23 | FLAG 48 320 $G_Vdd 24 | SYMBOL mux9-3 112 32 R0 25 | SYMATTR InstName X1 26 | TEXT -376 152 Left 0 ;Assembled from cmptest.t 27 | -------------------------------------------------------------------------------- /circuits/tsign3.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 240 112 208 112 4 | WIRE 144 224 144 192 5 | WIRE 144 224 96 224 6 | WIRE 240 352 240 112 7 | WIRE 368 352 240 352 8 | WIRE 512 352 480 352 9 | WIRE 416 480 416 432 10 | WIRE 416 480 368 480 11 | FLAG 368 320 $G_Vss 12 | FLAG 368 384 $G_Vdd 13 | FLAG 368 480 I2 14 | IOPIN 368 480 In 15 | FLAG 96 80 $G_Vss 16 | FLAG 96 144 $G_Vdd 17 | FLAG 96 112 I0 18 | IOPIN 96 112 In 19 | FLAG 96 224 I1 20 | IOPIN 96 224 In 21 | FLAG 512 352 SIGN 22 | IOPIN 512 352 Out 23 | SYMBOL mux3-1 160 80 R0 24 | SYMATTR InstName XcheckI1 25 | SYMBOL mux3-1 432 320 R0 26 | SYMATTR InstName XcheckI2 27 | -------------------------------------------------------------------------------- /circuits/pznlatch.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | RECTANGLE Normal 64 161 -47 18 4 | CIRCLE Normal 80 120 64 104 5 | WINDOW 0 10 -1 Center 0 6 | SYMATTR Value pznflop 7 | SYMATTR Description Trinary PZN tri-latch, with inputs to pulse to set the latch to positive, negative, or zero 8 | PIN -48 48 LEFT 4 9 | PINATTR PinName P 10 | PINATTR SpiceOrder 1 11 | PIN -48 96 LEFT 4 12 | PINATTR PinName Z 13 | PINATTR SpiceOrder 2 14 | PIN -48 144 LEFT 4 15 | PINATTR PinName N 16 | PINATTR SpiceOrder 3 17 | PIN 64 64 RIGHT 4 18 | PINATTR PinName Q 19 | PINATTR SpiceOrder 4 20 | PIN 80 112 RIGHT 20 21 | PINATTR PinName _Q 22 | PINATTR SpiceOrder 5 23 | -------------------------------------------------------------------------------- /circuits/ttlatch.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | WINDOW 0 -1 -17 Center 0 8 | WINDOW 3 -45 91 Left 0 9 | SYMATTR Description Trinary T-type latch with PZN inputs 10 | PIN -80 64 LEFT 8 11 | PINATTR PinName T 12 | PINATTR SpiceOrder 1 13 | PIN 80 64 RIGHT 4 14 | PINATTR PinName Q 15 | PINATTR SpiceOrder 2 16 | PIN -48 144 BOTTOM 8 17 | PINATTR PinName P 18 | PINATTR SpiceOrder 3 19 | PIN 0 144 BOTTOM 8 20 | PINATTR PinName Z 21 | PINATTR SpiceOrder 4 22 | PIN 48 144 BOTTOM 8 23 | PINATTR PinName N 24 | PINATTR SpiceOrder 5 25 | -------------------------------------------------------------------------------- /digital_simulator/Token.py: -------------------------------------------------------------------------------- 1 | # vim: set fileencoding=utf8 2 | # Token.py 3 | # 4 | # A generic token is a semicolon, comma, etc. 5 | # 6 | 7 | symbols = ("(", ")", ",", ";", ":", "'", "{", "}", "^") 8 | 9 | class Token(object): 10 | def __init__(self, name): 11 | '''Initialize Token object. ''' 12 | 13 | # TODO: validate that 'name' is a valid token 14 | self.name = name 15 | 16 | def __str__(self): 17 | return "" % (self.name,) 18 | 19 | if __name__ == "__main__": 20 | a = Token(";") 21 | b = Token(",") 22 | c = Token("(") 23 | d = Token(")") 24 | 25 | print a, b, c, d 26 | -------------------------------------------------------------------------------- /circuits/dtflop-msmo.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | LINE Normal -72 94 -80 85 8 | LINE Normal -80 104 -72 94 9 | LINE Normal 47 31 29 31 10 | LINE Normal 47 48 47 31 11 | WINDOW 0 3 -15 Center 0 12 | WINDOW 3 -38 161 Left 0 13 | SYMATTR Description Trinary D-type master-slave flip-flop built using transmission gates and inverters 14 | PIN -80 48 LEFT 8 15 | PINATTR PinName D 16 | PINATTR SpiceOrder 1 17 | PIN -80 96 LEFT 8 18 | PINATTR PinName C 19 | PINATTR SpiceOrder 2 20 | PIN 80 48 RIGHT 4 21 | PINATTR PinName Q 22 | PINATTR SpiceOrder 3 23 | -------------------------------------------------------------------------------- /circuits/swrom-fast_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 416 80 320 80 4 | WIRE 416 128 320 128 5 | WIRE 64 176 -32 176 6 | WIRE 416 176 320 176 7 | WIRE -32 224 -32 176 8 | FLAG 416 80 D0 9 | FLAG 416 128 D1 10 | FLAG 416 176 D2 11 | FLAG -32 304 0 12 | FLAG -192 32 $G_Vdd 13 | FLAG -192 96 $G_Vss 14 | FLAG -32 176 ADDRESS 15 | SYMBOL voltage -32 208 R0 16 | SYMATTR InstName A 17 | SYMATTR Value PWL(0 -5 14n -5 15n 0 29n 0 30n 5) 18 | SYMBOL tpower -192 64 R0 19 | SYMATTR InstName X2 20 | SYMBOL swrom-fast 112 80 R0 21 | WINDOW 39 0 0 Left 0 22 | SYMATTR InstName X1 23 | TEXT -64 336 Left 0 !.tran 40n 24 | TEXT 72 240 Left 0 !.include ../asm/guess.sp 25 | -------------------------------------------------------------------------------- /bb/tnor_test.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\tnor_test.asc 2 | VA A 0 PWL file=INPUT_A.txt 3 | VB B 0 PWL file=INPUT_B.txt 4 | XX1 A B TNOR_Out tnor 5 | XX2 $G_Vdd $G_Vss tpower 6 | 7 | * block symbol definitions 8 | .subckt tnor A B TNOR_Out 9 | RP NP TNOR_Out 12k 10 | RN TNOR_Out NN 12k 11 | MN1 NN A $G_Vss $G_Vss CD4007N 12 | MP2 NI A $G_Vdd $G_Vdd CD4007P 13 | MN2 NN B $G_Vss $G_Vss CD4007N 14 | MP1 NI B NP $G_Vdd CD4007P 15 | .ends tnor 16 | 17 | .subckt tpower Vdd Vss 18 | Vdd Vdd 0 5V 19 | Vss 0 Vss 5V 20 | .ends tpower 21 | 22 | .model NMOS NMOS 23 | .model PMOS PMOS 24 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 25 | .tran 500ns 26 | .backanno 27 | .end 28 | -------------------------------------------------------------------------------- /circuits/dtflop-et.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | LINE Normal -72 94 -80 85 8 | LINE Normal -80 104 -72 94 9 | CIRCLE Normal 96 104 80 88 10 | WINDOW 0 3 -15 Center 0 11 | WINDOW 3 -38 161 Left 0 12 | SYMATTR Description Edge-triggered D-type tri-flop ***UNTESTED** 13 | PIN -80 48 LEFT 8 14 | PINATTR PinName D 15 | PINATTR SpiceOrder 1 16 | PIN -80 96 LEFT 8 17 | PINATTR PinName CLK 18 | PINATTR SpiceOrder 2 19 | PIN 80 48 RIGHT 4 20 | PINATTR PinName Q 21 | PINATTR SpiceOrder 3 22 | PIN 96 96 RIGHT 20 23 | PINATTR PinName _Q 24 | PINATTR SpiceOrder 4 25 | -------------------------------------------------------------------------------- /circuits/sp3t-2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 0 -64 0 4 | LINE Normal -16 0 0 0 5 | LINE Normal -25 -16 0 -16 6 | LINE Normal -25 16 0 16 7 | LINE Normal -23 0 -48 0 8 | LINE Normal -22 0 -24 0 9 | LINE Normal -27 -4 -22 0 10 | LINE Normal -26 3 -22 0 11 | LINE Normal -27 4 -26 3 12 | CIRCLE Normal -25 -13 -31 -19 13 | CIRCLE Normal -16 3 -22 -3 14 | CIRCLE Normal -25 19 -31 13 15 | PIN 0 -16 NONE 8 16 | PINATTR PinName 1 17 | PINATTR SpiceOrder 1 18 | PIN 0 0 NONE 8 19 | PINATTR PinName 2 20 | PINATTR SpiceOrder 2 21 | PIN 0 16 NONE 8 22 | PINATTR PinName 3 23 | PINATTR SpiceOrder 4 24 | PIN -64 0 NONE 8 25 | PINATTR PinName COM 26 | PINATTR SpiceOrder 3 27 | -------------------------------------------------------------------------------- /bb/tnand_test.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\tnand_test.asc 2 | VA A 0 PWL file=INPUT_A.txt 3 | XX1 A B TNAND_Out tnand 4 | VB B 0 PWL file=INPUT_B.txt 5 | XU1 $G_Vdd $G_Vss tpower 6 | 7 | * block symbol definitions 8 | .subckt tnand A B TNAND_Out 9 | RP NP TNAND_Out 12k 10 | RN TNAND_Out NN 12k 11 | MP1 NP B $G_Vdd $G_Vdd CD4007P 12 | MP2 NP A $G_Vdd $G_Vdd CD4007P 13 | MN2 NI B $G_Vss $G_Vss CD4007N 14 | MN1 NN A NI $G_Vss CD4007N 15 | .ends tnand 16 | 17 | .subckt tpower Vdd Vss 18 | Vdd Vdd 0 5V 19 | Vss 0 Vss 5V 20 | .ends tpower 21 | 22 | .model NMOS NMOS 23 | .model PMOS PMOS 24 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 25 | .tran 500ns 26 | .backanno 27 | .end 28 | -------------------------------------------------------------------------------- /circuits/full_adder.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | TEXT -70 86 Left 0 + 8 | TEXT -70 40 Left 0 + 9 | WINDOW 0 -1 -17 Center 0 10 | WINDOW 3 -38 161 Left 0 11 | SYMATTR Description Trinary half-adder (2 trits) 12 | PIN -80 64 LEFT 8 13 | PINATTR PinName X 14 | PINATTR SpiceOrder 1 15 | PIN 80 48 RIGHT 4 16 | PINATTR PinName CO 17 | PINATTR SpiceOrder 2 18 | PIN 80 96 RIGHT 4 19 | PINATTR PinName S 20 | PINATTR SpiceOrder 3 21 | PIN -80 112 LEFT 8 22 | PINATTR PinName Y 23 | PINATTR SpiceOrder 4 24 | PIN -80 16 LEFT 8 25 | PINATTR PinName CI 26 | PINATTR SpiceOrder 5 27 | -------------------------------------------------------------------------------- /circuits/decoder1-3_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 240 32 160 32 4 | WIRE -32 80 -128 80 5 | WIRE 240 80 160 80 6 | WIRE 240 128 160 128 7 | WIRE -128 208 -128 80 8 | WIRE -128 336 -128 288 9 | FLAG -128 336 0 10 | FLAG -128 80 IN 11 | FLAG -352 0 $G_Vdd 12 | FLAG -352 64 $G_Vss 13 | FLAG 240 32 IS_i 14 | FLAG 240 80 IS_0 15 | FLAG 240 128 IS_1 16 | SYMBOL voltage -128 192 R0 17 | WINDOW 3 -92 177 Left 0 18 | WINDOW 123 0 0 Left 0 19 | WINDOW 39 0 0 Left 0 20 | SYMATTR Value PWL(0 0 9n 0 10n -5 19n -5 20n 5) 21 | SYMATTR InstName V1 22 | SYMBOL tpower -352 32 R0 23 | SYMATTR InstName X3 24 | SYMBOL decoder1-3 64 32 R0 25 | SYMATTR InstName X1 26 | TEXT -432 448 Left 0 !.tran 30n 27 | -------------------------------------------------------------------------------- /circuits/shift_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 160 96 96 96 4 | WIRE 288 96 192 96 5 | WIRE 96 176 96 96 6 | WIRE 96 176 64 176 7 | WIRE 160 176 96 176 8 | WIRE 288 176 192 176 9 | WIRE 64 192 64 176 10 | WIRE 64 304 64 272 11 | FLAG 64 304 0 12 | FLAG 64 176 IN 13 | FLAG -80 176 $G_Vdd 14 | FLAG -80 240 $G_Vss 15 | FLAG 288 96 Shift_Up 16 | FLAG 288 176 Shift_Down 17 | SYMBOL voltage 64 176 R0 18 | WINDOW 3 24 104 Invisible 0 19 | SYMATTR Value 0V 20 | SYMATTR InstName V1 21 | SYMBOL tpower -80 208 R0 22 | SYMATTR InstName X2 23 | SYMBOL shift_up 176 96 R0 24 | SYMATTR InstName Xsup 25 | SYMBOL shift_down 176 176 R0 26 | SYMATTR InstName X1 27 | TEXT 88 288 Left 0 !.dc v1 -5 5 0.1 28 | -------------------------------------------------------------------------------- /circuits/pznlatch.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 304 48 208 48 4 | WIRE 304 64 256 64 5 | WIRE 400 64 384 64 6 | WIRE 448 64 400 64 7 | WIRE 256 96 256 64 8 | WIRE 256 96 208 96 9 | WIRE 304 128 400 64 10 | WIRE 256 144 256 96 11 | WIRE 304 144 256 144 12 | WIRE 400 144 304 80 13 | WIRE 400 144 384 144 14 | WIRE 448 144 400 144 15 | WIRE 304 160 208 160 16 | FLAG 448 144 Q 17 | IOPIN 448 144 Out 18 | FLAG 448 64 _Q 19 | IOPIN 448 64 Out 20 | FLAG 208 48 P 21 | IOPIN 208 48 In 22 | FLAG 208 96 Z 23 | IOPIN 208 96 In 24 | FLAG 208 160 N 25 | IOPIN 208 160 In 26 | SYMBOL tnor3 336 64 R0 27 | SYMATTR InstName U1 28 | SYMBOL tnor3 336 144 R0 29 | WINDOW 0 2 48 Center 0 30 | SYMATTR InstName U2 31 | -------------------------------------------------------------------------------- /extended/Hashtable.py: -------------------------------------------------------------------------------- 1 | 2 | import sys 3 | 4 | class Hashtable(object): 5 | def __init__(self): 6 | self.table = {} 7 | 8 | # check if key already defined, if not insert it 9 | def check_and_insert(self, key, value): 10 | if key in self.table: 11 | print "id '" + key + "' already defined" 12 | raise SystemExit 13 | self.table[id] = value 14 | 15 | # used for checking for valid assignments 16 | def assign_value(self, key, value): 17 | if key in self.table: 18 | print "id '" + key + "' already defined" 19 | raise SystemExit 20 | if self.table[key].compare_types(value, "assignment"): 21 | self.table[key] = value 22 | -------------------------------------------------------------------------------- /circuits/mux3-1.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal 48 -33 -64 -52 4 | LINE Normal -64 113 48 94 5 | LINE Normal -64 113 -64 -52 6 | LINE Normal 48 94 48 -33 7 | LINE Normal -16 105 -16 112 8 | TEXT -55 0 Left 0 _1 9 | TEXT -55 32 Left 0 0 10 | TEXT -55 63 Left 0 1 11 | WINDOW 0 -7 -69 Center 0 12 | SYMATTR Description 3:1 trinary multiplexer 13 | PIN -64 0 NONE 8 14 | PINATTR PinName A 15 | PINATTR SpiceOrder 1 16 | PIN -64 32 NONE 8 17 | PINATTR PinName B 18 | PINATTR SpiceOrder 2 19 | PIN -64 64 NONE 8 20 | PINATTR PinName C 21 | PINATTR SpiceOrder 3 22 | PIN -16 112 BOTTOM 8 23 | PINATTR PinName S 24 | PINATTR SpiceOrder 4 25 | PIN 48 32 RIGHT 8 26 | PINATTR PinName Q 27 | PINATTR SpiceOrder 5 28 | -------------------------------------------------------------------------------- /circuits/diode_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 192 -16 144 -16 4 | WIRE 288 -16 256 -16 5 | WIRE 144 176 144 -16 6 | WIRE 144 176 80 176 7 | WIRE 192 176 144 176 8 | WIRE 288 176 256 176 9 | WIRE 80 208 80 176 10 | WIRE 80 320 80 288 11 | FLAG 80 320 0 12 | FLAG -272 256 $G_Vss 13 | FLAG -272 192 $G_Vdd 14 | FLAG 80 176 input 15 | FLAG 288 -16 RD 16 | FLAG 288 176 FD 17 | SYMBOL voltage 80 192 R0 18 | WINDOW 3 24 104 Invisible 0 19 | WINDOW 0 -76 7 Left 0 20 | SYMATTR Value -5V 21 | SYMATTR InstName V1 22 | SYMBOL tpower -272 224 R0 23 | SYMATTR InstName U3 24 | SYMBOL fd 208 160 R0 25 | SYMATTR InstName Xfd 26 | SYMBOL rd 208 -32 R0 27 | SYMATTR InstName Xrd 28 | TEXT -120 248 Left 0 !.dc V1 -5 5 0.1 29 | -------------------------------------------------------------------------------- /bb/wikify_pads.pl: -------------------------------------------------------------------------------- 1 | #!/usr/bin/perl 2 | # Created:20080708 3 | # By Jeff Connelly 4 | # 5 | # Parse a .pads file and make a wiki table of the pins 6 | while(<>) 7 | { 8 | chomp; 9 | last if $_ eq "*NET*"; 10 | } 11 | while(<>) 12 | { 13 | if (m/^[*]SIGNAL[*] (.*)/) 14 | { 15 | $signals{$signal} = [ @pins ]; 16 | $signal = $1; 17 | @pins = (); 18 | } else { 19 | push @pins, split /\s+/; 20 | } 21 | } 22 | 23 | print <" % (self.name,) 20 | 21 | if __name__ == "__main__": 22 | a = Keyword("entity") 23 | b = Keyword("port") 24 | c = Keyword("architecture") 25 | d = Keyword("inout") 26 | 27 | print a, b, c, d 28 | -------------------------------------------------------------------------------- /circuits/tsign4.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 96 112 -80 112 4 | WIRE 368 112 208 112 5 | WIRE 512 112 480 112 6 | WIRE -144 240 -144 192 7 | WIRE -144 240 -192 240 8 | WIRE 144 240 144 192 9 | WIRE 144 240 96 240 10 | WIRE 416 240 416 192 11 | WIRE 416 240 368 240 12 | FLAG 368 80 $G_Vss 13 | FLAG 368 144 $G_Vdd 14 | FLAG 368 240 I3 15 | IOPIN 368 240 In 16 | FLAG 96 80 $G_Vss 17 | FLAG 96 144 $G_Vdd 18 | FLAG 96 240 I2 19 | IOPIN 96 240 In 20 | FLAG 512 112 SIGN 21 | IOPIN 512 112 Out 22 | FLAG -192 240 I1 23 | IOPIN -192 240 In 24 | FLAG -192 112 I0 25 | IOPIN -192 112 In 26 | FLAG -192 80 $G_Vss 27 | FLAG -192 144 $G_Vdd 28 | SYMBOL mux3-1 160 80 R0 29 | SYMATTR InstName XcheckI2 30 | SYMBOL mux3-1 432 80 R0 31 | SYMATTR InstName XcheckI3 32 | SYMBOL mux3-1 -128 80 R0 33 | SYMATTR InstName XcheckI1 34 | -------------------------------------------------------------------------------- /circuits/dtflop2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | CIRCLE Normal 96 104 80 88 8 | WINDOW 0 0 -18 Center 0 9 | WINDOW 3 -38 161 Left 0 10 | SYMATTR Description Trinary D-type flip-flop, experimental. Keep X and Y high for normal operation, bring Y low to set flip-flop to high. 11 | PIN -80 48 LEFT 8 12 | PINATTR PinName D 13 | PINATTR SpiceOrder 1 14 | PIN -80 96 LEFT 8 15 | PINATTR PinName CLK 16 | PINATTR SpiceOrder 2 17 | PIN 80 48 RIGHT 4 18 | PINATTR PinName Q 19 | PINATTR SpiceOrder 3 20 | PIN 96 96 RIGHT 20 21 | PINATTR PinName _Q 22 | PINATTR SpiceOrder 4 23 | PIN -48 144 LEFT 8 24 | PINATTR PinName X 25 | PINATTR SpiceOrder 5 26 | PIN 32 144 LEFT 8 27 | PINATTR PinName Y 28 | PINATTR SpiceOrder 6 29 | -------------------------------------------------------------------------------- /circuits/max.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -13 -28 1 -28 4 | LINE Normal -13 30 1 30 5 | LINE Normal -13 26 4 26 6 | LINE Normal -13 -25 3 -25 7 | LINE Normal -17 30 -13 30 8 | LINE Normal -13 -28 -17 -28 9 | LINE Normal -12 16 -32 16 10 | LINE Normal -32 -16 -13 -16 11 | LINE Normal 31 0 48 0 12 | ARC Normal -30 -28 31 30 0 31 0 -28 13 | ARC Normal -34 -26 27 27 4 31 1 -21 14 | ARC Normal -28 -29 -11 31 -17 30 -14 -27 15 | ARC Normal -27 -28 -6 28 -13 26 -5 -22 16 | TEXT 2 0 Left 0 3 17 | WINDOW 0 2 -44 Center 0 18 | SYMATTR Description TNOR dyadic trinary 2-input gate, OR (MAX) function 19 | PIN -32 -16 NONE 8 20 | PINATTR PinName A 21 | PINATTR SpiceOrder 1 22 | PIN -32 16 NONE 8 23 | PINATTR PinName B 24 | PINATTR SpiceOrder 2 25 | PIN 48 0 NONE 8 26 | PINATTR PinName MAX_OUT 27 | PINATTR SpiceOrder 3 28 | -------------------------------------------------------------------------------- /circuits/min.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -13 -28 1 -28 4 | LINE Normal -13 30 1 30 5 | LINE Normal -13 26 4 26 6 | LINE Normal -13 -25 3 -25 7 | LINE Normal -13 26 -13 -25 8 | LINE Normal -17 30 -13 30 9 | LINE Normal -17 -28 -17 30 10 | LINE Normal -13 -28 -17 -28 11 | LINE Normal -17 16 -32 16 12 | LINE Normal -17 -16 -32 -16 13 | LINE Normal 31 0 39 0 14 | LINE Normal 48 0 39 0 15 | ARC Normal -30 -28 31 30 0 31 0 -28 16 | ARC Normal -34 -26 27 27 4 31 1 -21 17 | TEXT -4 0 Left 0 3 18 | WINDOW 0 0 -43 Center 0 19 | SYMATTR Description MIN dyadic trinary 2-input gate, inverted TNAND function 20 | PIN -32 -16 NONE 8 21 | PINATTR PinName A 22 | PINATTR SpiceOrder 1 23 | PIN -32 16 NONE 8 24 | PINATTR PinName B 25 | PINATTR SpiceOrder 2 26 | PIN 48 0 NONE 8 27 | PINATTR PinName MIN_OUT 28 | PINATTR SpiceOrder 3 29 | -------------------------------------------------------------------------------- /circuits/dtlatch_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 3 4 | { 5 | traces: 1 {524292,0,"V(_q)"} 6 | X: ('n',0,0,4e-009,4e-008) 7 | Y[0]: (' ',0,-5,1,5.1) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,0,-5,1,5.1) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 1 {524291,0,"V(q)"} 15 | X: ('n',0,0,4e-009,4e-008) 16 | Y[0]: (' ',0,-5,1,5.1) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,-5,1,5.1) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | }, 22 | { 23 | traces: 1 {524290,0,"V(d)"} 24 | X: ('n',0,0,4e-009,4e-008) 25 | Y[0]: (' ',0,-5,1,5.1) 26 | Y[1]: ('_',0,1e+308,0,-1e+308) 27 | Volts: (' ',0,0,1,-5,1,5.1) 28 | Log: 0 0 0 29 | GridStyle: 1 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /circuits/tnand_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 3 4 | { 5 | traces: 1 {524291,0,"V(tnand_out)"} 6 | X: ('n',0,0,5e-008,5e-007) 7 | Y[0]: (' ',0,-6,1,6) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,0,-6,1,6) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 1 {524292,0,"V(b)"} 15 | X: ('n',0,0,5e-008,5e-007) 16 | Y[0]: (' ',0,-5,1,5) 17 | Y[1]: ('n',0,1e+308,2e-008,-1e+308) 18 | Volts: (' ',0,0,0,-5,1,5) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | }, 22 | { 23 | traces: 1 {524290,0,"V(a)"} 24 | X: ('n',0,0,5e-008,5e-007) 25 | Y[0]: (' ',0,-5,1,5) 26 | Y[1]: ('_',0,1e+308,0,-1e+308) 27 | Volts: (' ',0,0,0,-5,1,5) 28 | Log: 0 0 0 29 | GridStyle: 1 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /circuits/trit_reg3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 274 5 | LINE Normal -80 274 80 274 6 | LINE Normal 80 274 80 0 7 | LINE Normal -71 225 -79 213 8 | LINE Normal -80 237 -71 225 9 | WINDOW 0 0 -17 Center 0 10 | WINDOW 3 -43 258 Left 0 11 | SYMATTR Description 3-trit register 12 | PIN -80 112 LEFT 8 13 | PINATTR PinName D2 14 | PINATTR SpiceOrder 1 15 | PIN -80 224 LEFT 8 16 | PINATTR PinName CLK 17 | PINATTR SpiceOrder 2 18 | PIN 80 112 RIGHT 4 19 | PINATTR PinName Q2 20 | PINATTR SpiceOrder 3 21 | PIN -80 80 LEFT 8 22 | PINATTR PinName D1 23 | PINATTR SpiceOrder 4 24 | PIN 80 80 RIGHT 4 25 | PINATTR PinName Q1 26 | PINATTR SpiceOrder 5 27 | PIN 80 48 RIGHT 4 28 | PINATTR PinName Q0 29 | PINATTR SpiceOrder 6 30 | PIN -80 48 LEFT 8 31 | PINATTR PinName D0 32 | PINATTR SpiceOrder 7 33 | -------------------------------------------------------------------------------- /circuits/dtflop-ms2.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -80 0 80 0 4 | LINE Normal -80 0 -80 144 5 | LINE Normal -80 144 80 144 6 | LINE Normal 80 144 80 0 7 | LINE Normal -72 94 -80 85 8 | LINE Normal -80 104 -72 94 9 | LINE Normal 47 31 29 31 10 | LINE Normal 47 48 47 31 11 | LINE Normal 48 80 31 80 12 | LINE Normal 48 98 48 80 13 | CIRCLE Normal 96 104 80 88 14 | WINDOW 0 3 -15 Center 0 15 | WINDOW 3 -38 161 Left 0 16 | SYMATTR Description Trinary D-type master-slave rising edge-triggered flip-flop, built using two TNAND-based tri-flops 17 | PIN -80 48 LEFT 8 18 | PINATTR PinName D 19 | PINATTR SpiceOrder 1 20 | PIN -80 96 LEFT 8 21 | PINATTR PinName CLK 22 | PINATTR SpiceOrder 2 23 | PIN 80 48 RIGHT 4 24 | PINATTR PinName Q 25 | PINATTR SpiceOrder 3 26 | PIN 96 96 RIGHT 20 27 | PINATTR PinName _Q 28 | PINATTR SpiceOrder 4 29 | -------------------------------------------------------------------------------- /circuits/tnand.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -13 -28 1 -28 4 | LINE Normal -13 30 1 30 5 | LINE Normal -13 26 4 26 6 | LINE Normal -13 -25 3 -25 7 | LINE Normal -13 26 -13 -25 8 | LINE Normal -17 30 -13 30 9 | LINE Normal -17 -28 -17 30 10 | LINE Normal -13 -28 -17 -28 11 | LINE Normal -17 16 -32 16 12 | LINE Normal -17 -16 -32 -16 13 | LINE Normal 40 0 48 0 14 | CIRCLE Normal 40 5 31 -4 15 | ARC Normal -30 -28 31 30 0 31 0 -28 16 | ARC Normal -34 -26 27 27 4 31 1 -21 17 | TEXT -4 -2 Left 0 3 18 | WINDOW 0 0 -43 Center 0 19 | SYMATTR Description TNAND dyadic trinary 2-input gate, inverted AND (MIN) function 20 | PIN -32 -16 NONE 8 21 | PINATTR PinName A 22 | PINATTR SpiceOrder 1 23 | PIN -32 16 NONE 8 24 | PINATTR PinName B 25 | PINATTR SpiceOrder 2 26 | PIN 48 0 NONE 8 27 | PINATTR PinName TNAND_Out 28 | PINATTR SpiceOrder 3 29 | -------------------------------------------------------------------------------- /digital_simulator/Port.py: -------------------------------------------------------------------------------- 1 | #!/usr/bin/python 2 | # vim: set fileencoding=utf8 3 | # Created:20080211 4 | # By Jeff Connelly 5 | 6 | IN = "in" 7 | OUT = "out" 8 | INOUT = "inout" 9 | 10 | 11 | class Port(object): 12 | def __init__(self, name, direction, type, length = 0): 13 | self.name = name 14 | assert direction in [IN, OUT, INOUT], \ 15 | "Port direction %s is invalid" % (direction,) 16 | 17 | self.direction = direction 18 | self.type = type 19 | self.value = [] 20 | self.length = length 21 | 22 | def __str__(self): 23 | return "" % (self.name, self.direction, self.type, self.length) 24 | 25 | if __name__ == "__main__": 26 | a = Port("a", IN, None) 27 | b = Port("b", IN, None) 28 | c = Port("c", OUT, None) 29 | 30 | print a 31 | print b 32 | print c 33 | -------------------------------------------------------------------------------- /circuits/tnor.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -13 -28 1 -28 4 | LINE Normal -13 30 1 30 5 | LINE Normal -13 26 4 26 6 | LINE Normal -13 -25 3 -25 7 | LINE Normal -17 30 -13 30 8 | LINE Normal -13 -28 -17 -28 9 | LINE Normal -12 16 -32 16 10 | LINE Normal -32 -16 -13 -16 11 | LINE Normal 48 0 40 0 12 | CIRCLE Normal 40 5 31 -4 13 | ARC Normal -30 -28 31 30 0 31 0 -28 14 | ARC Normal -34 -26 27 27 4 31 1 -21 15 | ARC Normal -28 -29 -11 31 -17 30 -14 -27 16 | ARC Normal -27 -28 -6 28 -13 26 -5 -22 17 | TEXT 2 0 Left 0 3 18 | WINDOW 0 2 -44 Center 0 19 | SYMATTR Description TNOR dyadic trinary 2-input gate, inverted OR (MAX) function 20 | PIN -32 -16 NONE 8 21 | PINATTR PinName A 22 | PINATTR SpiceOrder 1 23 | PIN -32 16 NONE 8 24 | PINATTR PinName B 25 | PINATTR SpiceOrder 2 26 | PIN 48 0 NONE 8 27 | PINATTR PinName TNOR_Out 28 | PINATTR SpiceOrder 3 29 | -------------------------------------------------------------------------------- /bb/sti_test.net: -------------------------------------------------------------------------------- 1 | * Based on Z:\trinary\code\circuits\tinv_test.asc 2 | V1 N001 0 -5V 3 | Xsti N001 STI_Out1 sti 4 | *Xnti N001 NTI_Out1 nti 5 | *Xpti N001 PTI_Out1 pti 6 | 7 | * block symbol definitions 8 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 9 | RP PTI_Out STI_Out 12k 10 | RN STI_Out NTI_Out 12k 11 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 12 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 13 | .ends tinv 14 | 15 | .subckt tpower Vdd Vss 16 | Vdd Vdd 0 5V 17 | Vss 0 Vss 5V 18 | .ends tpower 19 | 20 | .subckt sti IN OUT 21 | XX1 IN NC_01 OUT NC_02 tinv 22 | .ends sti 23 | 24 | .subckt nti IN OUT 25 | XX1 IN NC_01 NC_02 OUT tinv 26 | .ends nti 27 | 28 | .subckt pti IN OUT 29 | XX1 IN OUT NC_01 NC_02 tinv 30 | .ends pti 31 | 32 | .model NMOS NMOS 33 | .model PMOS PMOS 34 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 35 | .dc V1 -5 5 0.1 36 | .backanno 37 | .end 38 | -------------------------------------------------------------------------------- /circuits/sp3t-1.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 144 64 128 64 4 | WIRE 240 64 224 64 5 | WIRE 128 160 128 64 6 | WIRE 128 160 0 160 7 | WIRE 160 160 128 160 8 | WIRE 240 160 224 160 9 | WIRE 128 256 128 160 10 | WIRE 160 256 128 256 11 | WIRE 240 256 224 256 12 | FLAG 0 160 COM 13 | IOPIN 0 160 In 14 | FLAG 240 64 1 15 | IOPIN 240 64 Out 16 | FLAG 240 160 2 17 | IOPIN 240 160 Out 18 | FLAG 240 256 3 19 | IOPIN 240 256 Out 20 | SYMBOL res 128 48 M90 21 | WINDOW 0 0 56 VBottom 0 22 | WINDOW 3 32 56 VTop 0 23 | SYMATTR InstName short1 24 | SYMATTR Value 1 25 | SYMBOL cap 224 144 R90 26 | WINDOW 0 0 32 VBottom 0 27 | WINDOW 3 32 32 VTop 0 28 | SYMATTR InstName open2 29 | SYMATTR Value 1p 30 | SYMBOL cap 224 240 R90 31 | WINDOW 0 0 32 VBottom 0 32 | WINDOW 3 32 32 VTop 0 33 | SYMATTR InstName open3 34 | SYMATTR Value 1p 35 | TEXT -184 -40 Left 0 ;Placeholder for real SP3T switch, hardwired to input 1. 36 | -------------------------------------------------------------------------------- /circuits/sp3t-2.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 144 64 128 64 4 | WIRE 240 64 208 64 5 | WIRE 128 160 128 64 6 | WIRE 128 160 0 160 7 | WIRE 144 160 128 160 8 | WIRE 240 160 224 160 9 | WIRE 128 256 128 160 10 | WIRE 144 256 128 256 11 | WIRE 240 256 208 256 12 | FLAG 0 160 COM 13 | IOPIN 0 160 In 14 | FLAG 240 64 1 15 | IOPIN 240 64 Out 16 | FLAG 240 160 2 17 | IOPIN 240 160 Out 18 | FLAG 240 256 3 19 | IOPIN 240 256 Out 20 | SYMBOL cap 208 48 R90 21 | WINDOW 0 0 32 VBottom 0 22 | WINDOW 3 32 32 VTop 0 23 | SYMATTR InstName open1 24 | SYMATTR Value 1p 25 | SYMBOL cap 208 240 R90 26 | WINDOW 0 0 32 VBottom 0 27 | WINDOW 3 32 32 VTop 0 28 | SYMATTR InstName open3 29 | SYMATTR Value 1p 30 | SYMBOL res 240 144 R90 31 | WINDOW 0 0 56 VBottom 0 32 | WINDOW 3 32 56 VTop 0 33 | SYMATTR InstName short2 34 | SYMATTR Value 1 35 | TEXT -184 -40 Left 0 ;Placeholder for real SP3T switch, hardwired to input 2. 36 | -------------------------------------------------------------------------------- /circuits/sp3t-3.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 144 64 128 64 4 | WIRE 240 64 208 64 5 | WIRE 128 160 128 64 6 | WIRE 128 160 0 160 7 | WIRE 144 160 128 160 8 | WIRE 240 160 208 160 9 | WIRE 128 256 128 160 10 | WIRE 144 256 128 256 11 | WIRE 240 256 224 256 12 | FLAG 0 160 COM 13 | IOPIN 0 160 In 14 | FLAG 240 64 1 15 | IOPIN 240 64 Out 16 | FLAG 240 160 2 17 | IOPIN 240 160 Out 18 | FLAG 240 256 3 19 | IOPIN 240 256 Out 20 | SYMBOL cap 144 48 M90 21 | WINDOW 0 0 32 VBottom 0 22 | WINDOW 3 32 32 VTop 0 23 | SYMATTR InstName open1 24 | SYMATTR Value 1p 25 | SYMBOL cap 144 144 M90 26 | WINDOW 0 0 32 VBottom 0 27 | WINDOW 3 32 32 VTop 0 28 | SYMATTR InstName open2 29 | SYMATTR Value 1p 30 | SYMBOL res 240 240 R90 31 | WINDOW 0 0 56 VBottom 0 32 | WINDOW 3 32 56 VTop 0 33 | SYMATTR InstName short3 34 | SYMATTR Value 1 35 | TEXT -184 -40 Left 0 ;Placeholder for real SP3T switch, hardwired to input 3. 36 | -------------------------------------------------------------------------------- /circuits/tnand_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 1148 680 3 | WIRE 192 112 112 112 4 | WIRE 320 128 272 128 5 | WIRE 112 208 112 112 6 | WIRE 192 208 192 144 7 | WIRE 112 320 112 288 8 | WIRE 160 320 112 320 9 | WIRE 192 320 192 288 10 | WIRE 192 320 160 320 11 | WIRE 160 368 160 320 12 | FLAG 160 368 0 13 | FLAG 320 128 TNAND_Out 14 | FLAG 112 112 A 15 | FLAG 192 144 B 16 | FLAG -64 96 $G_Vdd 17 | FLAG -64 160 $G_Vss 18 | SYMBOL voltage 112 192 R0 19 | WINDOW 3 -269 112 Left 0 20 | WINDOW 123 0 0 Left 0 21 | WINDOW 39 0 0 Left 0 22 | SYMATTR Value PWL file=INPUT_A.txt 23 | SYMATTR InstName VA 24 | SYMBOL TNAND 224 128 R0 25 | SYMATTR InstName X1 26 | SYMBOL voltage 192 192 R0 27 | WINDOW 3 27 108 Left 0 28 | WINDOW 123 0 0 Left 0 29 | WINDOW 39 0 0 Left 0 30 | SYMATTR Value PWL file=INPUT_B.txt 31 | SYMATTR InstName VB 32 | SYMBOL tpower -64 128 R0 33 | SYMATTR InstName U1 34 | TEXT -120 416 Left 0 !.tran 500ns 35 | -------------------------------------------------------------------------------- /bb/Tand.net: -------------------------------------------------------------------------------- 1 | * Z:\College\Senior Year\Trinary Research Project\trinary\circuits\TAND.asc 2 | XX1 TAND_1A TAND_1B TAND_1Y min 3 | 4 | * block symbol definitions 5 | .subckt min A B MIN_OUT 6 | XXsti_tand AtnandB MIN_OUT sti 7 | XXtnand A B AtnandB tnand 8 | .ends min 9 | 10 | .subckt sti IN OUT 11 | XXinv IN NC_01 OUT NC_02 tinv 12 | .ends sti 13 | 14 | .subckt tnand A B TNAND_Out 15 | RP NP TNAND_Out 12k 16 | RN TNAND_Out NN 12k 17 | MP1 NP B $G_Vdd $G_Vdd CD4007P 18 | MP2 NP A $G_Vdd $G_Vdd CD4007P 19 | MN2 NI B $G_Vss $G_Vss CD4007N 20 | MN1 NN A NI $G_Vss CD4007N 21 | .ends tnand 22 | 23 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 24 | RP PTI_Out STI_Out 12k 25 | RN STI_Out NTI_Out 12k 26 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 27 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 28 | .ends tinv 29 | 30 | .model NMOS NMOS 31 | .model PMOS PMOS 32 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 33 | .backanno 34 | .end 35 | -------------------------------------------------------------------------------- /circuits/tnand3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -13 -28 1 -28 4 | LINE Normal -13 30 1 30 5 | LINE Normal -13 26 4 26 6 | LINE Normal -13 -25 3 -25 7 | LINE Normal -13 26 -13 -25 8 | LINE Normal -17 30 -13 30 9 | LINE Normal -17 -28 -17 30 10 | LINE Normal -13 -28 -17 -28 11 | LINE Normal -17 0 -32 0 12 | LINE Normal -17 -16 -32 -16 13 | LINE Normal 40 0 48 0 14 | LINE Normal -17 16 -32 16 15 | CIRCLE Normal 40 5 31 -4 16 | ARC Normal -30 -28 31 30 0 31 0 -28 17 | ARC Normal -34 -26 27 27 4 31 1 -21 18 | WINDOW 0 1 -44 Center 0 19 | SYMATTR Description TNAND dyadic trinary 3-input gate, inverted AND (MIN) function 20 | PIN -32 -16 NONE 8 21 | PINATTR PinName A 22 | PINATTR SpiceOrder 1 23 | PIN -32 0 NONE 8 24 | PINATTR PinName B 25 | PINATTR SpiceOrder 2 26 | PIN -32 16 NONE 8 27 | PINATTR PinName C 28 | PINATTR SpiceOrder 3 29 | PIN 48 0 NONE 8 30 | PINATTR PinName TNAND_Out 31 | PINATTR SpiceOrder 4 32 | -------------------------------------------------------------------------------- /circuits/alu.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 80 -48 -16 4 | LINE Normal 16 112 -48 80 5 | LINE Normal -48 144 16 112 6 | LINE Normal 32 -16 -48 -16 7 | LINE Normal 160 64 32 -16 8 | LINE Normal 32 241 160 161 9 | LINE Normal 32 241 -48 241 10 | LINE Normal -48 240 -48 144 11 | LINE Normal 160 161 160 64 12 | WINDOW 0 1 -43 Center 0 13 | SYMATTR Description Arithmetic logic unit - behavioral model 14 | PIN -48 0 LEFT 8 15 | PINATTR PinName A2 16 | PINATTR SpiceOrder 1 17 | PIN -48 32 LEFT 8 18 | PINATTR PinName A1 19 | PINATTR SpiceOrder 2 20 | PIN -48 64 LEFT 8 21 | PINATTR PinName A0 22 | PINATTR SpiceOrder 3 23 | PIN -48 160 LEFT 8 24 | PINATTR PinName B2 25 | PINATTR SpiceOrder 4 26 | PIN -48 192 LEFT 8 27 | PINATTR PinName B1 28 | PINATTR SpiceOrder 5 29 | PIN -48 224 LEFT 8 30 | PINATTR PinName B0 31 | PINATTR SpiceOrder 6 32 | PIN 160 112 RIGHT 8 33 | PINATTR PinName S 34 | PINATTR SpiceOrder 7 35 | -------------------------------------------------------------------------------- /circuits/tg_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 272 160 224 160 4 | WIRE 320 160 272 160 5 | WIRE 400 160 352 160 6 | WIRE 336 192 336 176 7 | WIRE 224 208 224 160 8 | WIRE 336 208 336 192 9 | WIRE 224 304 224 288 10 | WIRE 288 304 224 304 11 | WIRE 336 304 336 288 12 | WIRE 336 304 288 304 13 | WIRE 288 320 288 304 14 | FLAG 64 128 $G_Vdd 15 | FLAG 64 192 $G_Vss 16 | FLAG 272 160 IN 17 | FLAG 400 160 OUT 18 | FLAG 336 192 C 19 | FLAG 288 320 0 20 | SYMBOL tpower 64 160 R0 21 | SYMATTR InstName X1 22 | SYMBOL tg 336 160 R0 23 | SYMATTR InstName X2 24 | SYMBOL voltage 224 192 R0 25 | WINDOW 3 -404 115 Left 0 26 | WINDOW 123 0 0 Left 0 27 | WINDOW 39 0 0 Left 0 28 | SYMATTR Value SINE(0 5 200Meg 1n) 29 | SYMATTR InstName V1 30 | SYMBOL voltage 336 192 R0 31 | WINDOW 123 0 0 Left 0 32 | WINDOW 39 0 0 Left 0 33 | SYMATTR InstName V2 34 | SYMATTR Value PWL(0 -5 5n -5 6n 5 13n 5 14n -5) 35 | TEXT 80 8 Left 0 !.tran 20n 36 | -------------------------------------------------------------------------------- /extended/Register.py: -------------------------------------------------------------------------------- 1 | 2 | class Register(object): 3 | 4 | def __init__(self, virtual_ndx = False, datatype = False): 5 | if virtual_ndx == False: 6 | self.virtual_ndx = -1 7 | else: 8 | self.virtual_ndx = virtual_ndx 9 | 10 | if datatype != False: 11 | self.datatype = datatype 12 | 13 | self.mem_loc = 0 14 | 15 | def __str__(self): 16 | return str(self.virtual_ndx) 17 | 18 | def set_virtual_ndx(self, virtual_ndx): 19 | self.virtual_ndx = virtual_ndx 20 | 21 | def get_virtual_ndx(self): 22 | return self.virtual_ndx 23 | 24 | def set_datatype(self, datatype): 25 | self.data_type = datatype 26 | 27 | def get_datatype(self): 28 | return self.datatype 29 | 30 | def set_mem_loc(self, loc): 31 | self.mem_loc = loc 32 | 33 | def get_mem_loc(self): 34 | return self.mem_loc 35 | -------------------------------------------------------------------------------- /circuits/tnor3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -13 -28 1 -28 4 | LINE Normal -13 30 1 30 5 | LINE Normal -13 26 4 26 6 | LINE Normal -13 -25 3 -25 7 | LINE Normal -17 30 -13 30 8 | LINE Normal -13 -28 -17 -28 9 | LINE Normal -12 16 -32 16 10 | LINE Normal -32 -16 -13 -16 11 | LINE Normal 48 0 40 0 12 | LINE Normal -11 0 -32 0 13 | CIRCLE Normal 40 5 31 -4 14 | ARC Normal -30 -28 31 30 0 31 0 -28 15 | ARC Normal -34 -26 27 27 4 31 1 -21 16 | ARC Normal -28 -29 -11 31 -17 30 -14 -27 17 | ARC Normal -27 -28 -6 28 -13 26 -5 -22 18 | WINDOW 0 1 -43 Center 0 19 | SYMATTR Description TNOR dyadic trinary 3-input gate, inverted OR (MAX) function 20 | PIN -32 -16 NONE 8 21 | PINATTR PinName A 22 | PINATTR SpiceOrder 1 23 | PIN -32 0 NONE 8 24 | PINATTR PinName B 25 | PINATTR SpiceOrder 2 26 | PIN -32 16 NONE 8 27 | PINATTR PinName C 28 | PINATTR SpiceOrder 3 29 | PIN 48 0 NONE 8 30 | PINATTR PinName TNOR_Out 31 | PINATTR SpiceOrder 4 32 | -------------------------------------------------------------------------------- /circuits/tinv_test.plt: -------------------------------------------------------------------------------- 1 | [DC transfer characteristic] 2 | { 3 | Npanes: 3 4 | { 5 | traces: 2 {524296,0,"V(epti_out)"} {524297,0,"V(enti_out)"} 6 | X: (' ',0,-5,1,5) 7 | Y[0]: (' ',1,-5.4,0.9,4.5) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,1,-5.4,0.9,4.5) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 3 {524293,0,"V(pti_out)"} {524294,0,"V(sti_out)"} {524295,0,"V(nti_out)"} 15 | X: (' ',0,-5,1,5) 16 | Y[0]: (' ',0,-5,1,5) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,-5,1,5) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | }, 22 | { 23 | traces: 3 {524290,0,"V(pti_out1)"} {524291,0,"V(sti_out1)"} {524292,0,"V(nti_out1)"} 24 | X: (' ',0,-5,1,5) 25 | Y[0]: (' ',0,-5,1,5) 26 | Y[1]: ('_',0,1e+308,0,-1e+308) 27 | Volts: (' ',0,0,0,-5,1,5) 28 | Log: 0 0 0 29 | GridStyle: 1 30 | } 31 | } 32 | -------------------------------------------------------------------------------- /circuits/alu-fast.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -48 80 -48 -16 4 | LINE Normal 16 112 -48 80 5 | LINE Normal -48 144 16 112 6 | LINE Normal 32 -16 -48 -16 7 | LINE Normal 160 64 32 -16 8 | LINE Normal 32 241 160 161 9 | LINE Normal 32 241 -48 241 10 | LINE Normal -48 240 -48 144 11 | LINE Normal 160 161 160 64 12 | TEXT 0 84 Left 0 BEHAVIORAL 13 | WINDOW 0 1 -43 Center 0 14 | SYMATTR Description Arithmetic logic unit - behavioral model 15 | PIN -48 0 LEFT 8 16 | PINATTR PinName A0 17 | PINATTR SpiceOrder 1 18 | PIN -48 32 LEFT 8 19 | PINATTR PinName A1 20 | PINATTR SpiceOrder 2 21 | PIN -48 64 LEFT 8 22 | PINATTR PinName A2 23 | PINATTR SpiceOrder 3 24 | PIN -48 160 LEFT 8 25 | PINATTR PinName B0 26 | PINATTR SpiceOrder 4 27 | PIN -48 192 LEFT 8 28 | PINATTR PinName B1 29 | PINATTR SpiceOrder 5 30 | PIN -48 224 LEFT 8 31 | PINATTR PinName B2 32 | PINATTR SpiceOrder 6 33 | PIN 160 112 RIGHT 8 34 | PINATTR PinName S 35 | PINATTR SpiceOrder 7 36 | -------------------------------------------------------------------------------- /bb/NKK-SP3T-SS14MDP2.fpl: -------------------------------------------------------------------------------- 1 | name: "SS14MDP2" 2 | author: "Jeff Connelly" 3 | source: "http://www.nkkswitches.com/pdf/SSnonilluminated.pdf" 4 | description: "NKK SP3T Switch" 5 | units: MIL 6 | sel_rect: -15 -15 215 715 7 | ref_text: 100 0 800 0 10 8 | centroid: -842150451 -33155.529567 -33155.529567 9 | outline_polyline: 10 0 0 10 | next_corner: 200 0 0 11 | next_corner: 200 700 0 12 | next_corner: 0 700 0 13 | close_polyline: 0 14 | n_pins: 4 15 | pin: "1" 45 100 100 0 16 | top_pad: 1 75 0 0 0 17 | inner_pad: 0 75 0 0 0 18 | bottom_pad: 1 75 0 0 0 19 | pin: "2" 45 100 200 0 20 | top_pad: 1 75 0 0 0 21 | inner_pad: 0 75 0 0 0 22 | bottom_pad: 1 75 0 0 0 23 | pin: "3" 45 100 300 0 24 | top_pad: 1 75 0 0 0 25 | inner_pad: 0 75 0 0 0 26 | bottom_pad: 1 75 0 0 0 27 | pin: "4" 45 100 500 0 28 | top_pad: 1 75 0 0 0 29 | inner_pad: 0 75 0 0 0 30 | bottom_pad: 1 75 0 0 0 31 | 32 | -------------------------------------------------------------------------------- /circuits/tinv.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal -16 18 -16 -16 4 | LINE Normal -16 18 16 0 5 | LINE Normal 16 0 -16 -16 6 | LINE Normal 11 0 -14 -12 7 | LINE Normal -14 14 11 0 8 | LINE Normal -14 -12 -14 14 9 | LINE Normal -3 -11 -3 -17 10 | LINE Normal 0 -14 -6 -14 11 | LINE Normal 0 15 -6 15 12 | LINE Normal 24 0 32 0 13 | LINE Normal 1 -16 16 -16 14 | LINE Normal 1 16 16 16 15 | LINE Normal -8 -2 -8 -8 16 | LINE Normal -5 -5 -11 -5 17 | LINE Normal -5 7 -11 7 18 | CIRCLE Normal 24 4 16 -4 19 | CIRCLE Normal -7 -10 1 -18 20 | CIRCLE Normal 1 19 -7 11 21 | WINDOW 0 1 -34 Center 0 22 | SYMATTR Description Unary trinary gate: negative, simple, and positive inverter 23 | PIN -16 0 NONE 8 24 | PINATTR PinName Vin 25 | PINATTR SpiceOrder 1 26 | PIN 16 -16 NONE 8 27 | PINATTR PinName PTI_Out 28 | PINATTR SpiceOrder 2 29 | PIN 32 0 NONE 8 30 | PINATTR PinName STI_Out 31 | PINATTR SpiceOrder 3 32 | PIN 16 16 NONE 8 33 | PINATTR PinName NTI_Out 34 | PINATTR SpiceOrder 4 35 | -------------------------------------------------------------------------------- /bb/tinv_test.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\tinv_test.asc 2 | V1 input 0 -5V 3 | Xpti_sti_nti input PTI_Out STI_Out NTI_Out tinv 4 | Xeartheds input EPTI_Out 0 ENTI_Out tinv 5 | XU3 $G_Vdd $G_Vss tpower 6 | Xsti1 input STI_Out1 sti 7 | Xnti1 input NTI_Out1 nti 8 | Xpti1 input PTI_Out1 pti 9 | 10 | * block symbol definitions 11 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 12 | RP PTI_Out STI_Out 12k 13 | RN STI_Out NTI_Out 12k 14 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 15 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 16 | .ends tinv 17 | 18 | .subckt tpower Vdd Vss 19 | Vdd Vdd 0 5V 20 | Vss 0 Vss 5V 21 | .ends tpower 22 | 23 | .subckt sti IN OUT 24 | XX1 IN NC_01 OUT NC_02 tinv 25 | .ends sti 26 | 27 | .subckt nti IN OUT 28 | XX1 IN NC_01 NC_02 OUT tinv 29 | .ends nti 30 | 31 | .subckt pti IN OUT 32 | XX1 IN OUT NC_01 NC_02 tinv 33 | .ends pti 34 | 35 | .model NMOS NMOS 36 | .model PMOS PMOS 37 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 38 | .dc V1 -5 5 0.1 39 | .backanno 40 | .end 41 | -------------------------------------------------------------------------------- /circuits/tg_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 3 4 | Active Pane: 1 5 | { 6 | traces: 1 {268959748,0,"V(out)"} 7 | X: ('n',0,0,2e-009,2e-008) 8 | Y[0]: (' ',0,-5,1,5) 9 | Y[1]: ('p',1,1e+308,1e-013,-1e+308) 10 | Volts: (' ',0,0,0,-5,1,5) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | PltMag: 1 14 | PltPhi: 1 0 15 | }, 16 | { 17 | traces: 1 {268959747,0,"V(c)"} 18 | X: ('n',0,0,2e-009,2e-008) 19 | Y[0]: (' ',0,-5,1,5) 20 | Y[1]: ('p',1,1e+308,1e-013,-1e+308) 21 | Volts: (' ',0,0,1,-5,1,5) 22 | Log: 0 0 0 23 | GridStyle: 1 24 | PltMag: 1 25 | PltPhi: 1 0 26 | }, 27 | { 28 | traces: 1 {268959746,0,"V(in)"} 29 | X: ('n',0,0,2e-009,2e-008) 30 | Y[0]: (' ',0,-5,1,5) 31 | Y[1]: ('p',1,1e+308,1e-013,-1e+308) 32 | Volts: (' ',0,0,0,-5,1,5) 33 | Log: 0 0 0 34 | GridStyle: 1 35 | PltMag: 1 36 | PltPhi: 1 0 37 | } 38 | } 39 | -------------------------------------------------------------------------------- /circuits/dtflop_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 112 112 0 112 4 | WIRE 176 112 112 112 5 | WIRE 400 112 336 112 6 | WIRE 416 112 400 112 7 | WIRE 176 160 112 160 8 | WIRE 400 160 352 160 9 | WIRE 416 160 400 160 10 | WIRE 0 208 0 112 11 | WIRE 112 208 112 160 12 | WIRE 64 288 0 288 13 | WIRE 112 288 64 288 14 | WIRE 64 320 64 288 15 | FLAG 400 160 _Q 16 | FLAG 400 112 Q 17 | FLAG 64 320 0 18 | FLAG 112 112 D 19 | FLAG 112 160 CLK 20 | FLAG -320 224 $G_Vdd 21 | FLAG -320 288 $G_Vss 22 | SYMBOL dtflop 256 64 R0 23 | SYMATTR InstName U1 24 | SYMBOL voltage 112 192 R0 25 | WINDOW 123 0 0 Left 0 26 | WINDOW 39 0 0 Left 0 27 | SYMATTR InstName V1 28 | SYMATTR Value PULSE(-5 5 0 1p 1p 10n 20n) 29 | SYMBOL voltage 0 192 R0 30 | WINDOW 3 -45 164 Left 0 31 | WINDOW 123 0 0 Left 0 32 | WINDOW 39 0 0 Left 0 33 | SYMATTR InstName V2 34 | SYMATTR Value PWL(0 0 10n 0 11n 5 17n 5 18n 0 24n 0 25n -5 34n -5 35n 5) 35 | SYMBOL tpower -320 256 R0 36 | SYMATTR InstName X1 37 | TEXT 216 248 Left 0 !.tran 50n 38 | -------------------------------------------------------------------------------- /circuits/half_adder_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 708 3 | WIRE -48 16 -112 16 4 | WIRE 224 16 -48 16 5 | WIRE 496 16 384 16 6 | WIRE 224 64 48 64 7 | WIRE 496 64 384 64 8 | WIRE -112 288 -112 16 9 | WIRE 48 288 48 64 10 | WIRE -112 400 -112 368 11 | WIRE -16 400 -112 400 12 | WIRE 48 400 48 368 13 | WIRE 48 400 -16 400 14 | WIRE -16 432 -16 400 15 | FLAG -288 176 $G_Vss 16 | FLAG -288 112 $G_Vdd 17 | FLAG -16 432 0 18 | FLAG -48 16 A 19 | FLAG 48 64 B 20 | FLAG 496 16 C 21 | FLAG 496 64 S 22 | SYMBOL tpower -288 144 R0 23 | SYMATTR InstName X1 24 | SYMBOL voltage -112 272 R0 25 | WINDOW 3 -171 104 Left 0 26 | WINDOW 123 0 0 Left 0 27 | WINDOW 39 0 0 Left 0 28 | SYMATTR Value PWL file=INPUT_A.txt 29 | SYMATTR InstName VA 30 | SYMBOL voltage 48 272 R0 31 | WINDOW 3 -86 103 Left 0 32 | WINDOW 123 0 0 Left 0 33 | WINDOW 39 0 0 Left 0 34 | SYMATTR Value PWL file=INPUT_B.txt 35 | SYMATTR InstName VB 36 | SYMBOL half_adder 304 -32 R0 37 | SYMATTR InstName Xadder 38 | TEXT 32 472 Left 0 !.tran 540e-9 39 | -------------------------------------------------------------------------------- /circuits/tnor_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 972 680 3 | WIRE 208 112 112 112 4 | WIRE 224 112 208 112 5 | WIRE 336 128 288 128 6 | WIRE 208 144 192 144 7 | WIRE 224 144 208 144 8 | WIRE 112 160 112 112 9 | WIRE 192 160 192 144 10 | WIRE 112 272 112 240 11 | WIRE 160 272 112 272 12 | WIRE 192 272 192 240 13 | WIRE 192 272 160 272 14 | WIRE 160 288 160 272 15 | FLAG 160 288 0 16 | FLAG 112 112 A 17 | FLAG 192 144 B 18 | FLAG 336 128 TNOR_Out 19 | FLAG -208 64 $G_Vdd 20 | FLAG -208 128 $G_Vss 21 | SYMBOL voltage 112 144 R0 22 | WINDOW 0 -74 58 Left 0 23 | WINDOW 3 -255 98 Left 0 24 | WINDOW 123 0 0 Left 0 25 | WINDOW 39 0 0 Left 0 26 | SYMATTR InstName VA 27 | SYMATTR Value PWL file=INPUT_A.txt 28 | SYMBOL voltage 192 144 R0 29 | WINDOW 0 37 52 Left 0 30 | WINDOW 123 0 0 Left 0 31 | WINDOW 39 0 0 Left 0 32 | SYMATTR InstName VB 33 | SYMATTR Value PWL file=INPUT_B.txt 34 | SYMBOL tnor 240 128 R0 35 | SYMATTR InstName X1 36 | SYMBOL tpower -208 96 R0 37 | SYMATTR InstName X2 38 | TEXT 40 312 Left 0 !.tran 500ns 39 | -------------------------------------------------------------------------------- /circuits/decoder1-3_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 3 5 | { 6 | traces: 1 {524293,0,"V(is_1)"} 7 | X: ('n',0,0,3e-009,3e-008) 8 | Y[0]: (' ',0,-6,1,5) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-6,1,5) 11 | Log: 0 0 0 12 | }, 13 | { 14 | traces: 1 {524292,0,"V(is_0)"} 15 | X: ('n',0,0,3e-009,3e-008) 16 | Y[0]: (' ',0,-6,1,6) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,-6,1,6) 19 | Log: 0 0 0 20 | }, 21 | { 22 | traces: 1 {524291,0,"V(is_i)"} 23 | X: ('n',0,0,3e-009,3e-008) 24 | Y[0]: (' ',0,-6,1,6) 25 | Y[1]: ('_',0,1e+308,0,-1e+308) 26 | Volts: (' ',0,0,0,-6,1,6) 27 | Log: 0 0 0 28 | }, 29 | { 30 | traces: 1 {524290,0,"V(in)"} 31 | X: ('n',0,0,3e-009,3e-008) 32 | Y[0]: (' ',0,-5,1,5) 33 | Y[1]: ('_',0,1e+308,0,-1e+308) 34 | Volts: (' ',0,0,0,-5,1,5) 35 | Log: 0 0 0 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /circuits/tcycle_up.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 208 128 112 128 4 | WIRE 304 128 256 128 5 | WIRE 320 128 304 128 6 | WIRE 320 144 320 128 7 | WIRE 352 144 320 144 8 | WIRE 48 160 0 160 9 | WIRE 112 160 112 128 10 | WIRE 112 160 96 160 11 | WIRE 144 160 112 160 12 | WIRE 224 160 192 160 13 | WIRE 240 160 224 160 14 | WIRE 448 160 432 160 15 | WIRE 336 176 320 176 16 | WIRE 352 176 336 176 17 | WIRE 240 192 208 192 18 | WIRE 208 224 208 192 19 | FLAG 0 160 IN 20 | FLAG 448 160 OUT 21 | FLAG 208 224 0 22 | FLAG 112 160 _IN 23 | FLAG 304 128 _IN_NTI 24 | FLAG 224 160 _IN_PTI 25 | FLAG 336 176 INI 26 | SYMBOL nti 224 128 R0 27 | WINDOW 0 -10 -32 Left 0 28 | SYMATTR InstName Xnti 29 | SYMBOL pti 160 160 R0 30 | WINDOW 0 -6 25 Left 0 31 | SYMATTR InstName Xpti 32 | SYMBOL sti 64 160 R0 33 | WINDOW 0 -12 -36 Left 0 34 | SYMATTR InstName Xsti 35 | SYMBOL tnor 384 160 R0 36 | WINDOW 0 1 -47 Left 0 37 | SYMATTR InstName Xtnor1 38 | SYMBOL tnor 272 176 R0 39 | WINDOW 0 -7 50 Left 0 40 | SYMATTR InstName Xtnor0 41 | -------------------------------------------------------------------------------- /circuits/tinv.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 208 -160 -176 -160 4 | WIRE -224 -112 -256 -112 5 | WIRE -176 -48 -176 -64 6 | WIRE -80 -48 -176 -48 7 | WIRE -176 -32 -176 -48 8 | WIRE -336 64 -336 48 9 | WIRE -256 64 -256 -112 10 | WIRE -256 64 -336 64 11 | WIRE -176 80 -176 48 12 | WIRE -80 80 -176 80 13 | WIRE -176 96 -176 80 14 | WIRE -176 240 -176 176 15 | WIRE -80 240 -176 240 16 | WIRE -256 288 -256 64 17 | WIRE -224 288 -256 288 18 | WIRE 208 336 -176 336 19 | FLAG -336 48 Vin 20 | IOPIN -336 48 In 21 | FLAG -80 80 STI_Out 22 | IOPIN -80 80 Out 23 | FLAG -80 -48 PTI_Out 24 | IOPIN -80 -48 Out 25 | FLAG -80 240 NTI_Out 26 | IOPIN -80 240 Out 27 | FLAG 208 -160 $G_Vdd 28 | FLAG 208 336 $G_Vss 29 | SYMBOL res -192 -48 R0 30 | SYMATTR InstName RP 31 | SYMATTR Value 12k 32 | SYMBOL res -192 80 R0 33 | SYMATTR InstName RN 34 | SYMATTR Value 12k 35 | SYMBOL nmos2 -224 240 R0 36 | SYMATTR InstName MN 37 | SYMATTR Value CD4007N 38 | SYMBOL pmos2 -224 -64 M180 39 | SYMATTR InstName MP 40 | SYMATTR Value CD4007P 41 | -------------------------------------------------------------------------------- /extended/Inst_Node.py: -------------------------------------------------------------------------------- 1 | 2 | class Inst_Node(object): 3 | 4 | def __init__(self, op, rs = False, rt = False, rd = False, imd = False): 5 | 6 | self.op = op 7 | if rs != False: 8 | self.rs = rs 9 | 10 | if rt != False: 11 | self.rt = rt 12 | 13 | if rd != False: 14 | self.rd = rd 15 | 16 | if imd != False: 17 | self.imd = imd 18 | 19 | def set_imd(self, imd): 20 | self.imd = imd 21 | 22 | def get_imd(self): 23 | return self.imd 24 | 25 | def set_arg_num(self, arg_num): 26 | self.arg_num = arg_num 27 | 28 | def get_arg_num(self): 29 | return self.arg_num 30 | 31 | def set_val_name(self, name): 32 | self.val_name = name 33 | 34 | def get_val_name(self): 35 | return self.val_name 36 | 37 | def add_label(self, label): 38 | self.label.append(label) 39 | 40 | def get_label_by_ndx(self, ndx): 41 | return self.label[ndx] 42 | 43 | -------------------------------------------------------------------------------- /circuits/tcycle_down.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 208 128 112 128 4 | WIRE 304 128 256 128 5 | WIRE 320 128 304 128 6 | WIRE 320 144 320 128 7 | WIRE 352 144 320 144 8 | WIRE 48 160 0 160 9 | WIRE 112 160 112 128 10 | WIRE 112 160 96 160 11 | WIRE 144 160 112 160 12 | WIRE 224 160 192 160 13 | WIRE 240 160 224 160 14 | WIRE 448 160 432 160 15 | WIRE 336 176 320 176 16 | WIRE 352 176 336 176 17 | WIRE 240 192 224 192 18 | WIRE 224 224 224 192 19 | FLAG 0 160 IN 20 | FLAG 448 160 OUT 21 | FLAG 224 224 0 22 | FLAG 112 160 _IN 23 | FLAG 304 128 _IN_PTI 24 | FLAG 224 160 _IN_NTI 25 | FLAG 336 176 INI 26 | SYMBOL tnand 384 160 R0 27 | WINDOW 0 -28 50 Left 0 28 | SYMATTR InstName Xtnand1 29 | SYMBOL tnand 272 176 R0 30 | WINDOW 0 -27 44 Left 0 31 | SYMATTR InstName Xtnand0 32 | SYMBOL nti 160 160 R0 33 | WINDOW 0 -15 34 Left 0 34 | SYMATTR InstName Xnti 35 | SYMBOL pti 224 128 R0 36 | WINDOW 0 -16 -32 Left 0 37 | SYMATTR InstName Xpti 38 | SYMBOL sti 64 160 R0 39 | WINDOW 0 -12 -36 Left 0 40 | SYMATTR InstName Xsti 41 | -------------------------------------------------------------------------------- /circuits/trit_reg3.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 96 64 16 64 4 | WIRE 320 64 256 64 5 | WIRE 96 112 64 112 6 | WIRE 96 240 32 240 7 | WIRE 304 240 256 240 8 | WIRE 64 288 64 112 9 | WIRE 96 288 64 288 10 | WIRE 16 352 16 64 11 | WIRE 16 352 -272 352 12 | WIRE 320 352 320 64 13 | WIRE 528 352 320 352 14 | WIRE 32 384 32 240 15 | WIRE 32 384 -272 384 16 | WIRE 304 384 304 240 17 | WIRE 528 384 304 384 18 | WIRE 96 416 -272 416 19 | WIRE 528 416 256 416 20 | WIRE 64 464 64 288 21 | WIRE 64 464 -272 464 22 | WIRE 96 464 64 464 23 | FLAG -272 464 CLK 24 | IOPIN -272 464 In 25 | FLAG -272 416 D0 26 | IOPIN -272 416 In 27 | FLAG -272 384 D1 28 | IOPIN -272 384 In 29 | FLAG -272 352 D2 30 | IOPIN -272 352 In 31 | FLAG 528 416 Q0 32 | IOPIN 528 416 Out 33 | FLAG 528 384 Q1 34 | IOPIN 528 384 Out 35 | FLAG 528 352 Q2 36 | IOPIN 528 352 Out 37 | SYMBOL dtflop-ms2 176 368 R0 38 | SYMATTR InstName Xtrit0 39 | SYMBOL dtflop-ms2 176 192 R0 40 | SYMATTR InstName Xtrit1 41 | SYMBOL dtflop-ms2 176 16 R0 42 | SYMATTR InstName Xtrit2 43 | -------------------------------------------------------------------------------- /circuits/half_subtractor_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 708 3 | WIRE -48 16 -112 16 4 | WIRE 224 16 -48 16 5 | WIRE 496 16 384 16 6 | WIRE 224 64 48 64 7 | WIRE 496 64 384 64 8 | WIRE -112 288 -112 16 9 | WIRE 48 288 48 64 10 | WIRE -112 400 -112 368 11 | WIRE -16 400 -112 400 12 | WIRE 48 400 48 368 13 | WIRE 48 400 -16 400 14 | WIRE -16 432 -16 400 15 | FLAG -288 176 $G_Vss 16 | FLAG -288 112 $G_Vdd 17 | FLAG -16 432 0 18 | FLAG -48 16 A 19 | FLAG 48 64 B 20 | FLAG 496 16 C 21 | FLAG 496 64 D 22 | SYMBOL tpower -288 144 R0 23 | SYMATTR InstName X1 24 | SYMBOL voltage -112 272 R0 25 | WINDOW 3 -171 104 Left 0 26 | WINDOW 123 0 0 Left 0 27 | WINDOW 39 0 0 Left 0 28 | SYMATTR Value PWL file=INPUT_A.txt 29 | SYMATTR InstName VA 30 | SYMBOL voltage 48 272 R0 31 | WINDOW 3 -86 103 Left 0 32 | WINDOW 123 0 0 Left 0 33 | WINDOW 39 0 0 Left 0 34 | SYMATTR Value PWL file=INPUT_B.txt 35 | SYMATTR InstName VB 36 | SYMBOL half_subtractor 304 -32 R0 37 | SYMATTR InstName X3 38 | TEXT 32 472 Left 0 !.tran 540e-9 39 | TEXT -208 -88 Left 0 ;WARNING: thinks 1 - _1 is 4 (1 1) instead of 2 (1 _1) 40 | -------------------------------------------------------------------------------- /circuits/dtflop-et_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 1664 680 3 | WIRE 112 112 0 112 4 | WIRE 176 112 112 112 5 | WIRE 400 112 336 112 6 | WIRE 416 112 400 112 7 | WIRE 176 160 112 160 8 | WIRE 400 160 352 160 9 | WIRE 416 160 400 160 10 | WIRE 0 208 0 112 11 | WIRE 112 208 112 160 12 | WIRE 64 288 0 288 13 | WIRE 112 288 64 288 14 | WIRE 64 320 64 288 15 | FLAG 400 160 _Q 16 | FLAG 400 112 Q 17 | FLAG 64 320 0 18 | FLAG 112 112 D 19 | FLAG 112 160 CLK 20 | FLAG -320 224 $G_Vdd 21 | FLAG -320 288 $G_Vss 22 | SYMBOL voltage 112 192 R0 23 | WINDOW 123 0 0 Left 0 24 | WINDOW 39 0 0 Left 0 25 | SYMATTR InstName V1 26 | SYMATTR Value PULSE(-5 5 0 1p 1p 10n 20n) 27 | SYMBOL voltage 0 192 R0 28 | WINDOW 3 -45 164 Left 0 29 | WINDOW 123 0 0 Left 0 30 | WINDOW 39 0 0 Left 0 31 | SYMATTR Value PWL(0 0 1n 0 5n -5 8n -5 9n 0 10n 0 11n 5 21n 5 22n 0 24n 0 25n -5 34n -5 35n -5 40n -5 41n -5 42n 0 43n 5 44n 5 45n -5 46n 0 47n -5 48n 0) 32 | SYMATTR InstName V2 33 | SYMBOL tpower -320 256 R0 34 | SYMATTR InstName X1 35 | SYMBOL dtflop-et 256 64 R0 36 | SYMATTR InstName X2 37 | TEXT 216 248 Left 0 !.tran 50n 38 | -------------------------------------------------------------------------------- /circuits/dtflop-ms2_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 1664 680 3 | WIRE 112 112 0 112 4 | WIRE 176 112 112 112 5 | WIRE 400 112 336 112 6 | WIRE 416 112 400 112 7 | WIRE 176 160 112 160 8 | WIRE 400 160 352 160 9 | WIRE 416 160 400 160 10 | WIRE 0 208 0 112 11 | WIRE 112 208 112 160 12 | WIRE 64 288 0 288 13 | WIRE 112 288 64 288 14 | WIRE 64 320 64 288 15 | FLAG 400 160 _Q 16 | FLAG 400 112 Q 17 | FLAG 64 320 0 18 | FLAG 112 112 D 19 | FLAG 112 160 CLK 20 | FLAG -320 224 $G_Vdd 21 | FLAG -320 288 $G_Vss 22 | SYMBOL voltage 112 192 R0 23 | WINDOW 123 0 0 Left 0 24 | WINDOW 39 0 0 Left 0 25 | SYMATTR InstName Vclk 26 | SYMATTR Value PULSE(-5 5 0 1p 1p 10n 20n) 27 | SYMBOL voltage 0 192 R0 28 | WINDOW 3 -45 164 Left 0 29 | WINDOW 123 0 0 Left 0 30 | WINDOW 39 0 0 Left 0 31 | SYMATTR Value PWL(0 0 1n 0 5n -5 8n -5 9n 0 10n 0 11n 5 21n 5 22n 0 24n 0 25n -5 34n -5 35n -5 40n -5 41n -5 42n 0 43n 5 44n 5 45n -5 46n 0 47n -5 48n 0) 32 | SYMATTR InstName Vd 33 | SYMBOL tpower -320 256 R0 34 | SYMATTR InstName X1 35 | SYMBOL dtflop-ms2 256 64 R0 36 | SYMATTR InstName ff 37 | TEXT 216 248 Left 0 !.tran 50n 38 | -------------------------------------------------------------------------------- /circuits/mux3-1.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 744 3 | WIRE 144 32 96 32 4 | WIRE 480 32 176 32 5 | WIRE 256 96 96 96 6 | WIRE 480 96 480 32 7 | WIRE 480 96 288 96 8 | WIRE 368 176 96 176 9 | WIRE 480 176 480 96 10 | WIRE 480 176 400 176 11 | WIRE 272 224 272 112 12 | WIRE 160 240 160 48 13 | WIRE 384 240 384 192 14 | WIRE 480 256 480 176 15 | WIRE 160 272 160 240 16 | WIRE 224 272 160 272 17 | WIRE 384 272 384 240 18 | WIRE 384 272 320 272 19 | WIRE 224 304 224 272 20 | WIRE 272 304 272 224 21 | WIRE 320 304 320 272 22 | WIRE 272 544 272 496 23 | WIRE 272 544 -16 544 24 | FLAG 96 32 A 25 | IOPIN 96 32 In 26 | FLAG 96 96 B 27 | IOPIN 96 96 In 28 | FLAG 96 176 C 29 | IOPIN 96 176 In 30 | FLAG -16 544 S 31 | IOPIN -16 544 In 32 | FLAG 480 256 Q 33 | IOPIN 480 256 Out 34 | FLAG 160 240 CTRL_A 35 | FLAG 272 224 CTRL_B 36 | FLAG 384 240 CTRL_C 37 | SYMBOL tg 160 32 R0 38 | SYMATTR InstName XtgA 39 | SYMBOL tg 384 176 R0 40 | SYMATTR InstName XtgC 41 | SYMBOL tg 272 96 R0 42 | SYMATTR InstName XtgB 43 | SYMBOL decoder1-3 224 400 R270 44 | WINDOW 0 5 -32 Left 0 45 | SYMATTR InstName Xdecoder 46 | -------------------------------------------------------------------------------- /tools/Symbols.py: -------------------------------------------------------------------------------- 1 | #!env python 2 | # vim: set fileencoding=utf8 3 | # Created:20080216 4 | # By Jeff Connelly 5 | # 6 | # Trinary-related symbols 7 | # See http://jeff.tk/wiki/Trinary/Symbols 8 | # Note: to print, .encode('utf8') first 9 | # 10 | # MORE IMPORTANT NOTE: This isn't needed most of the time. 11 | # Instead, just use the Unicode symbols directly. You can 12 | # do this if the second line of the file is: 13 | # # vim: set fileencoding=utf8 14 | 15 | # TODO: Use literal values, actual characters, not escape 16 | 17 | # Trinary.cc-based unary 18 | ROTATE_UP = u"\u2229" 19 | ROTATE_DN = u"\u222a" 20 | SHIFT_UP = u"\u2197" 21 | SHIFT_DN = u"\2198" 22 | INVERT = u"/" 23 | 24 | # Mouftah-based unary 25 | FD = u"\u00ac" 26 | RD = u"\u2310" 27 | PTI = u"\u2518"; PTI2 = u"\u2518" 28 | NTI = u"\u2207"; NTI2 = u"\u2514" 29 | STI = u"/" 30 | 31 | # TODO: dyadic 32 | 33 | # Balanced base 9 34 | NONARY = { 35 | -1: u"\u2460", 36 | -2: u"\u2461", 37 | -3: u"\u2462", 38 | -4: u"\u2463", 39 | 0: u"0", 40 | 1: u"1", 41 | 2: u"2", 42 | 3: u"3", 43 | 4: u"4"} 44 | 45 | -------------------------------------------------------------------------------- /circuits/decoder1-3.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 240 112 80 112 4 | WIRE 272 112 240 112 5 | WIRE 352 112 320 112 6 | WIRE 384 112 352 112 7 | WIRE 464 112 432 112 8 | WIRE 592 112 464 112 9 | WIRE 464 192 464 112 10 | WIRE 592 208 544 208 11 | WIRE 240 304 240 112 12 | WIRE 272 304 240 304 13 | WIRE 416 304 320 304 14 | WIRE 464 304 464 224 15 | WIRE 464 304 416 304 16 | WIRE 592 304 464 304 17 | FLAG 80 112 IN 18 | IOPIN 80 112 In 19 | FLAG 592 112 OUT_1 20 | IOPIN 592 112 Out 21 | FLAG 592 304 OUT_i 22 | IOPIN 592 304 Out 23 | FLAG 592 208 OUT_0 24 | IOPIN 592 208 Out 25 | FLAG 352 112 IN_pti 26 | FLAG 416 304 IN_nti 27 | SYMBOL pti 288 112 R0 28 | SYMATTR InstName X1pti 29 | SYMBOL sti 400 112 R0 30 | SYMATTR InstName X1sti 31 | SYMBOL nti 288 304 R0 32 | SYMATTR InstName Xinti 33 | SYMBOL tnor 496 208 R0 34 | SYMATTR InstName X0nor 35 | TEXT 144 24 Left 0 ;Note: this is also called a "J_k circuit" 36 | TEXT -24 344 Left 0 ;Note: X1sti and X0nor can be binary gates! (that output _1 or 1)\nHere they are trinary, but for efficiency they should be binary\nsince OUT_1, OUT_0, and OUT_i are always either _1 or 1. 37 | -------------------------------------------------------------------------------- /digital_simulator/Symbols.py: -------------------------------------------------------------------------------- 1 | #!env python 2 | # vim: set fileencoding=utf8 3 | # Created:20080216 4 | # By Jeff Connelly 5 | # 6 | # Trinary-related symbols 7 | # See http://jeff.tk/wiki/Trinary/Symbols 8 | # Note: to print, .encode('utf8') first 9 | # 10 | # MORE IMPORTANT NOTE: This isn't needed most of the time. 11 | # Instead, just use the Unicode symbols directly. You can 12 | # do this if the second line of the file is: 13 | # # vim: set fileencoding=utf8 14 | 15 | # TODO: Use literal values, actual characters, not escape 16 | 17 | # Trinary.cc-based unary 18 | ROTATE_UP = u"\u2229" 19 | ROTATE_DN = u"\u222a" 20 | SHIFT_UP = u"\u2197" 21 | SHIFT_DN = u"\2198" 22 | INVERT = u"/" 23 | 24 | # Mouftah-based unary 25 | FD = u"\u00ac" 26 | RD = u"\u2310" 27 | PTI = u"\u2518"; PTI2 = u"\u2518" 28 | NTI = u"\u2207"; NTI2 = u"\u2514" 29 | STI = u"/" 30 | 31 | # TODO: dyadic 32 | 33 | # Balanced base 9 34 | NONARY = { 35 | -1: u"\u2460", 36 | -2: u"\u2461", 37 | -3: u"\u2462", 38 | -4: u"\u2463", 39 | 0: u"0", 40 | 1: u"1", 41 | 2: u"2", 42 | 3: u"3", 43 | 4: u"4"} 44 | 45 | -------------------------------------------------------------------------------- /circuits/dtflop.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 64 80 32 80 4 | WIRE 160 80 64 80 5 | WIRE 272 96 240 96 6 | WIRE 320 96 272 96 7 | WIRE 160 112 144 112 8 | WIRE 416 112 400 112 9 | WIRE 432 112 416 112 10 | WIRE 320 128 304 128 11 | WIRE 144 176 144 112 12 | WIRE 144 176 32 176 13 | WIRE 304 208 416 112 14 | WIRE 320 208 304 208 15 | WIRE 144 224 144 176 16 | WIRE 160 224 144 224 17 | WIRE 416 224 304 128 18 | WIRE 416 224 400 224 19 | WIRE 432 224 416 224 20 | WIRE 272 240 240 240 21 | WIRE 320 240 272 240 22 | WIRE 64 256 64 80 23 | WIRE 80 256 64 256 24 | WIRE 144 256 128 256 25 | WIRE 160 256 144 256 26 | FLAG 32 80 D 27 | IOPIN 32 80 In 28 | FLAG 32 176 CLK 29 | IOPIN 32 176 In 30 | FLAG 432 112 Q 31 | IOPIN 432 112 Out 32 | FLAG 432 224 _Q 33 | IOPIN 432 224 Out 34 | FLAG 272 96 Q_storage 35 | FLAG 272 240 _Q_storage 36 | FLAG 144 256 _D 37 | SYMBOL tnand 352 112 R0 38 | SYMATTR InstName Xlatch 39 | SYMBOL tnand 352 224 R0 40 | SYMATTR InstName _Xlatch 41 | SYMBOL tnand 192 96 R0 42 | SYMATTR InstName Xgatetop 43 | SYMBOL tnand 192 240 R0 44 | SYMATTR InstName Xgatebot 45 | SYMBOL sti 96 256 R0 46 | SYMATTR InstName XstiD 47 | -------------------------------------------------------------------------------- /circuits/dtflop-et_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 3 5 | { 6 | traces: 1 {524292,0,"V(q)"} 7 | X: ('n',0,0,5e-009,5e-008) 8 | Y[0]: ('m',0,-0.28,0.04,0.16) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: ('m',0,0,0,-0.28,0.04,0.16) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524291,0,"V(clk)"} 16 | X: ('n',0,0,5e-009,5e-008) 17 | Y[0]: (' ',0,-5,1,5) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,0,-5,1,5) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | }, 23 | { 24 | traces: 1 {524290,0,"V(d)"} 25 | X: ('n',0,0,5e-009,5e-008) 26 | Y[0]: (' ',0,-5,1,5) 27 | Y[1]: ('_',0,1e+308,0,-1e+308) 28 | Volts: (' ',0,0,0,-5,1,5) 29 | Log: 0 0 0 30 | GridStyle: 1 31 | }, 32 | { 33 | traces: 2 {268959747,0,"V(clk)"} {524293,0,"V(x2:n003)"} 34 | X: ('n',0,0,5e-009,5e-008) 35 | Y[0]: (' ',0,-6,1,7) 36 | Y[1]: ('m',0,1e+308,0.06,-1e+308) 37 | Volts: (' ',0,0,0,-6,1,7) 38 | Log: 0 0 0 39 | GridStyle: 1 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /bb/Cycle_Up.net: -------------------------------------------------------------------------------- 1 | * Z:\College\Senior Year\Trinary Research Project\trinary\circuits\Cycle_Up.asc 2 | XX1 CU_IN CU_OUT tcycle_up 3 | 4 | * block symbol definitions 5 | .subckt tcycle_up IN OUT 6 | XXnti _IN _IN_NTI nti 7 | XXpti _IN _IN_PTI pti 8 | XXsti IN _IN sti 9 | XXtnor1 _IN_NTI INI OUT tnor 10 | XXtnor0 _IN_PTI 0 INI tnor 11 | .ends tcycle_up 12 | 13 | .subckt nti IN OUT 14 | Xinv IN NC_01 NC_02 OUT tinv 15 | .ends nti 16 | 17 | .subckt pti IN OUT 18 | Xinv IN OUT NC_01 NC_02 tinv 19 | .ends pti 20 | 21 | .subckt sti IN OUT 22 | XXinv IN NC_01 OUT NC_02 tinv 23 | .ends sti 24 | 25 | .subckt tnor A B TNOR_Out 26 | RP NP TNOR_Out 12k 27 | RN TNOR_Out NN 12k 28 | MN1 NN A $G_Vss $G_Vss CD4007N 29 | MP2 NI A $G_Vdd $G_Vdd CD4007P 30 | MN2 NN B $G_Vss $G_Vss CD4007N 31 | MP1 NI B NP $G_Vdd CD4007P 32 | .ends tnor 33 | 34 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 35 | RP PTI_Out STI_Out 12k 36 | RN STI_Out NTI_Out 12k 37 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 38 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 39 | .ends tinv 40 | 41 | .model NMOS NMOS 42 | .model PMOS PMOS 43 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 44 | .backanno 45 | .end 46 | -------------------------------------------------------------------------------- /bb/Decoder.net: -------------------------------------------------------------------------------- 1 | * Z:\College\Senior Year\Trinary Research Project\trinary\circuits\Decoder.asc 2 | XX1 DEC_IN OUT_i OUT_0 OUT_1 decoder1-3 3 | 4 | * block symbol definitions 5 | .subckt decoder1-3 IN OUT_i OUT_0 OUT_1 6 | XX1pti IN IN_pti pti 7 | XX1sti IN_pti OUT_1 sti 8 | XXinti IN OUT_i nti 9 | XX0nor OUT_1 OUT_i OUT_0 tnor 10 | .ends decoder1-3 11 | 12 | .subckt pti IN OUT 13 | Xinv IN OUT NC_01 NC_02 tinv 14 | .ends pti 15 | 16 | .subckt sti IN OUT 17 | XXinv IN NC_01 OUT NC_02 tinv 18 | .ends sti 19 | 20 | .subckt nti IN OUT 21 | Xinv IN NC_01 NC_02 OUT tinv 22 | .ends nti 23 | 24 | .subckt tnor A B TNOR_Out 25 | RP NP TNOR_Out 12k 26 | RN TNOR_Out NN 12k 27 | MN1 NN A $G_Vss $G_Vss CD4007N 28 | MP2 NI A $G_Vdd $G_Vdd CD4007P 29 | MN2 NN B $G_Vss $G_Vss CD4007N 30 | MP1 NI B NP $G_Vdd CD4007P 31 | .ends tnor 32 | 33 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 34 | RP PTI_Out STI_Out 12k 35 | RN STI_Out NTI_Out 12k 36 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 37 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 38 | .ends tinv 39 | 40 | .model NMOS NMOS 41 | .model PMOS PMOS 42 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 43 | .backanno 44 | .end 45 | -------------------------------------------------------------------------------- /circuits/swrom_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 3 5 | { 6 | traces: 1 {524293,0,"V(d2)"} 7 | X: ('n',0,0,4e-009,3.99008088200116e-008) 8 | Y[0]: (' ',1,-4,0.8,5.6) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,1,-4,0.8,5.6) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524292,0,"V(d1)"} 16 | X: ('n',0,0,4e-009,3.99008088200116e-008) 17 | Y[0]: (' ',1,-5.8,0.2,-3.8) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,1,-5.8,0.2,-3.8) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | }, 23 | { 24 | traces: 1 {524290,0,"V(d0)"} 25 | X: ('n',0,0,4e-009,3.99008088200116e-008) 26 | Y[0]: (' ',0,-6,1,6) 27 | Y[1]: ('_',0,1e+308,0,-1e+308) 28 | Volts: (' ',0,0,0,-6,1,6) 29 | Log: 0 0 0 30 | GridStyle: 1 31 | }, 32 | { 33 | traces: 1 {524291,0,"V(address)"} 34 | X: ('n',0,0,4e-009,3.99008088200116e-008) 35 | Y[0]: (' ',0,-5,1,5) 36 | Y[1]: ('_',0,1e+308,0,-1e+308) 37 | Volts: (' ',0,0,0,-5,1,5) 38 | Log: 0 0 0 39 | GridStyle: 1 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /circuits/half_subtractor_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 1 5 | { 6 | traces: 1 {524293,0,"V(d)"} 7 | X: ('n',0,0,5e-008,5.4e-007) 8 | Y[0]: (' ',0,-6,1,6) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-6,1,6) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | Text: "V" 1 (3.89169381107492e-007,3.72307692307692) ;Should be i 14 | }, 15 | { 16 | traces: 1 {524292,0,"V(c)"} 17 | X: ('n',0,0,5e-008,5.4e-007) 18 | Y[0]: (' ',0,-6,1,6) 19 | Y[1]: ('_',0,1e+308,0,-1e+308) 20 | Volts: (' ',0,0,0,-6,1,6) 21 | Log: 0 0 0 22 | GridStyle: 1 23 | }, 24 | { 25 | traces: 1 {524291,0,"V(b)"} 26 | X: ('n',0,0,5e-008,5.4e-007) 27 | Y[0]: (' ',0,-6,1,6) 28 | Y[1]: ('_',0,1e+308,0,-1e+308) 29 | Volts: (' ',0,0,0,-6,1,6) 30 | Log: 0 0 0 31 | GridStyle: 1 32 | }, 33 | { 34 | traces: 1 {524290,0,"V(a)"} 35 | X: ('n',0,0,5e-008,5.4e-007) 36 | Y[0]: (' ',0,-6,1,6) 37 | Y[1]: ('_',0,1e+308,0,-1e+308) 38 | Volts: (' ',0,0,0,-6,1,6) 39 | Log: 0 0 0 40 | GridStyle: 1 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /circuits/swrom-fast_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 3 5 | { 6 | traces: 1 {524293,0,"V(d2)"} 7 | X: ('n',0,0,4e-009,3.99008088200116e-008) 8 | Y[0]: (' ',1,-4,0.8,5.6) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,1,-4,0.8,5.6) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524292,0,"V(d1)"} 16 | X: ('n',0,0,4e-009,3.99008088200116e-008) 17 | Y[0]: (' ',1,-5.8,0.2,-3.8) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,1,-5.8,0.2,-3.8) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | }, 23 | { 24 | traces: 1 {524290,0,"V(d0)"} 25 | X: ('n',0,0,4e-009,3.99008088200116e-008) 26 | Y[0]: (' ',0,-6,1,6) 27 | Y[1]: ('_',0,1e+308,0,-1e+308) 28 | Volts: (' ',0,0,0,-6,1,6) 29 | Log: 0 0 0 30 | GridStyle: 1 31 | }, 32 | { 33 | traces: 1 {524291,0,"V(address)"} 34 | X: ('n',0,0,4e-009,3.99008088200116e-008) 35 | Y[0]: (' ',0,-5,1,5) 36 | Y[1]: ('_',0,1e+308,0,-1e+308) 37 | Volts: (' ',0,0,0,-5,1,5) 38 | Log: 0 0 0 39 | GridStyle: 1 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /digital_simulator/Identifier.py: -------------------------------------------------------------------------------- 1 | # 2 | # vim: set fileencoding=utf8 3 | # Identifier.py 4 | # Creates identifier object. 5 | # 6 | # Created by Antonio on 2/16/08. 7 | # 8 | 9 | from Trits import Trits 10 | 11 | class Identifier(object): 12 | def __init__(self, name, value = ""): 13 | '''Initialize Identifier object. 14 | length field will be used to index vector from n to 0 15 | ''' 16 | 17 | self.name = name 18 | self.value = Trits(value) 19 | self.length = len(self.value) 20 | if self.length > 1: self.type = "vector" 21 | else: self.type = "trit" 22 | 23 | def __str__(self): 24 | return "" % (self.name, self.value) 25 | 26 | def setValue(self, value): 27 | self.value = Trits(value) 28 | self.length = len(self.value) 29 | if self.length > 1 : self.type = "vector" 30 | else: self.type = "trit" 31 | 32 | def getValue(self): 33 | return self.value 34 | 35 | 36 | if __name__ == "__main__": 37 | a = Identifier("one", "i") 38 | b = Identifier("two", "0") 39 | c = Identifier("three", "01i01") 40 | d = Identifier("four") 41 | 42 | print a, b, c, d 43 | -------------------------------------------------------------------------------- /bb/tnand.py: -------------------------------------------------------------------------------- 1 | # Ternary NAND, implemented with CD4007 2 | # 3 | 4 | nodes = ("A", "B", "TNAND_Out") 5 | 6 | # Dual MOSFET Complementary Pair + Binary Inverter 7 | parts_generated = ["CD4007"] 8 | parts_consumed = ["MP1", "MP2", "MN1", "MN2"] 9 | parts_kept = ["RP", "RN"] 10 | 11 | # Based on pinout from http://www.cedmagic.com/tech-info/data/cd4016.pdf 12 | pins = [ 13 | { 14 | "A": ("CD4007", 3), 15 | "B": ("CD4007", 6), 16 | "$G_Vdd": [("CD4007", 2), ("CD4007", 14)], 17 | "TNAND_Out": "TNAND_Out", 18 | "$G_Vss": ("CD4007", 7), 19 | 20 | # Internal nodes 21 | 22 | # Connect these two nodes together 23 | "NI": [("CD4007", 4), ("CD4007", 8)], 24 | # Connects to resistors 25 | "NP": [("CD4007", 1), ("CD4007", 13)], 26 | "NN": ("CD4007", 5), 27 | } 28 | ] 29 | 30 | # Always connected once if use once or more 31 | global_pins = { 32 | # TODO: always connect binary inverter, since we'll never be using it, 33 | # but to prevent MOSFETs from switching on and off, wasting power? 34 | # May need a change in this data structure to support multiple connections to $G_Vdd/Vss 35 | } 36 | 37 | 38 | -------------------------------------------------------------------------------- /bb/tnor.py: -------------------------------------------------------------------------------- 1 | # Ternary NOR, implemented with CD4007 2 | # 3 | 4 | nodes = ("A", "B", "TNOR_Out") 5 | 6 | # Dual MOSFET Complementary Pair + Binary Inverter 7 | parts_generated = ["CD4007"] 8 | parts_consumed = ["MP1", "MP2", "MN1", "MN2"] 9 | parts_kept = ["RP", "RN"] 10 | 11 | # Based on pinout from http://www.cedmagic.com/tech-info/data/cd4016.pdf 12 | pins = [ 13 | { 14 | "A": ("CD4007", 6), 15 | "B": ("CD4007", 3), 16 | "TNOR_Out": "TNOR_Out", 17 | "$G_Vss": [("CD4007", 4), ("CD4007", 7)], 18 | "$G_Vdd": ("CD4007", 14), 19 | 20 | 21 | # Internal nodes 22 | 23 | # Connect these two nodes together 24 | "NI": [("CD4007", 13), ("CD4007", 2)], 25 | # Connects to resistors 26 | "NP": ("CD4007", 1), 27 | "NN": [("CD4007", 8), ("CD4007", 5)], 28 | 29 | } 30 | ] 31 | 32 | # Always connected once if use once or more 33 | global_pins = { 34 | # TODO: always connect binary inverter, since we'll never be using it, 35 | # but to prevent MOSFETs from switching on and off, wasting power? 36 | # May need a change in this data structure to support multiple connections to $G_Vdd/Vss 37 | } 38 | 39 | -------------------------------------------------------------------------------- /extended/Node.py: -------------------------------------------------------------------------------- 1 | 2 | class Node(object): 3 | 4 | def __init__(self, label = False): 5 | self.iloc_inst = [] 6 | self.sparc_inst = [] 7 | self.entry_nodes = [] 8 | self.exit_nodes = [] 9 | self.labels = [] 10 | 11 | if label != False: 12 | self.labels.append(label) 13 | 14 | self.num_locals = 0 15 | self.num_args = 0 16 | 17 | def add_entry_node(self, node): 18 | self.entry_nodes.append(node) 19 | 20 | def add_exit_node(self, node): 21 | self.exit_node.append(node) 22 | 23 | def add_label(self, label): 24 | self.labels.append(label) 25 | 26 | def add_iloc_inst(self, inst): 27 | self.iloc_inst.append(inst) 28 | 29 | def extend_iloc(self, iloc_insts): 30 | self.iloc_inst.extend(iloc_insts) 31 | 32 | def add_sparc_inst(self, inst): 33 | self.sparc_inst.append(int) 34 | 35 | def set_num_locals(self, num): 36 | self.num_locals = num 37 | 38 | def get_num_locals(self): 39 | return self.num_locals 40 | 41 | def set_num_args(self, num): 42 | self.num_args = num 43 | 44 | def get_num_args(self): 45 | return self.num_args 46 | -------------------------------------------------------------------------------- /circuits/half_adder.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -32 -48 -96 -48 4 | WIRE 48 -48 32 -48 5 | WIRE 48 -16 48 -48 6 | WIRE 112 -16 48 -16 7 | WIRE 304 16 224 16 8 | WIRE 112 48 48 48 9 | WIRE -96 80 -96 -48 10 | WIRE -32 80 -96 80 11 | WIRE 48 80 48 48 12 | WIRE 48 80 32 80 13 | WIRE -96 160 -96 80 14 | WIRE -96 160 -208 160 15 | WIRE -96 256 -96 160 16 | WIRE 16 256 -96 256 17 | WIRE 96 256 48 256 18 | WIRE 96 288 96 256 19 | WIRE 112 288 96 288 20 | WIRE -96 320 -96 256 21 | WIRE 112 320 -96 320 22 | WIRE 304 320 224 320 23 | WIRE 112 352 96 352 24 | WIRE -96 400 -96 320 25 | WIRE 16 400 -96 400 26 | WIRE 96 400 96 352 27 | WIRE 96 400 48 400 28 | WIRE 160 400 160 96 29 | WIRE 160 448 160 400 30 | WIRE 160 448 -208 448 31 | FLAG 112 16 0 32 | FLAG 304 16 C 33 | FLAG 304 320 S 34 | FLAG -208 160 A 35 | FLAG -208 448 B 36 | SYMBOL mux3-1 176 -16 R0 37 | WINDOW 0 2 -68 Center 0 38 | SYMATTR InstName Xmux_carry1 39 | SYMBOL mux3-1 176 288 R0 40 | SYMATTR InstName Xmux_sum1 41 | SYMBOL tcycle_down 32 256 R0 42 | SYMATTR InstName Xcd 43 | SYMBOL shift_up 32 400 R0 44 | SYMATTR InstName Xsu 45 | SYMBOL rd -16 -32 M180 46 | WINDOW 0 2 -17 Left 0 47 | SYMATTR InstName Xrd 48 | SYMBOL fd -16 64 R0 49 | WINDOW 0 5 -14 Left 0 50 | SYMATTR InstName Xfd 51 | -------------------------------------------------------------------------------- /bb/CAM-sign/top_paste_mask.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-sign\top_paste_mask.grb* 3 | G04 layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X0Y0D02* 18 | G01X0Y37000D01* 19 | G04 end of side 1* 20 | G01X45500Y37000D01* 21 | G04 end of side 2* 22 | G01X45500Y0D01* 23 | G04 end of side 3* 24 | G01X0Y0D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4016_1* 29 | G04 Draw part IC_CD4007_2* 30 | G04 Draw part R_12K_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_CD4007_5* 33 | G04 Draw part R_12K_6* 34 | G04 Draw part IC_CD4016_7* 35 | G04 Draw part IC_CD4007_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part R_12K_10* 38 | G04 Draw part IC_CD4016_11* 39 | G04 Draw part IC_CD4007_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_15* 42 | G04 Draw part SD* 43 | G04 Draw part R1* 44 | G04 Draw part R2* 45 | G04 Draw part R3* 46 | 47 | G04 Draw traces* 48 | 49 | G04 Draw Text* 50 | M00* 51 | M02* 52 | -------------------------------------------------------------------------------- /bb/CAM-sign/bottom_paste_mask.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-sign\bottom_paste_mask.grb* 3 | G04 layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X0Y0D02* 18 | G01X0Y37000D01* 19 | G04 end of side 1* 20 | G01X45500Y37000D01* 21 | G04 end of side 2* 22 | G01X45500Y0D01* 23 | G04 end of side 3* 24 | G01X0Y0D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4016_1* 29 | G04 Draw part IC_CD4007_2* 30 | G04 Draw part R_12K_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_CD4007_5* 33 | G04 Draw part R_12K_6* 34 | G04 Draw part IC_CD4016_7* 35 | G04 Draw part IC_CD4007_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part R_12K_10* 38 | G04 Draw part IC_CD4016_11* 39 | G04 Draw part IC_CD4007_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_15* 42 | G04 Draw part SD* 43 | G04 Draw part R1* 44 | G04 Draw part R2* 45 | G04 Draw part R3* 46 | 47 | G04 Draw traces* 48 | 49 | G04 Draw Text* 50 | M00* 51 | M02* 52 | -------------------------------------------------------------------------------- /bb/CAM-sign/board_outline.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-sign\board_outline.grb* 3 | G04 board outline layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X0Y0D02* 18 | G01X0Y37000D01* 19 | G04 end of side 1* 20 | G01X45500Y37000D01* 21 | G04 end of side 2* 22 | G01X45500Y0D01* 23 | G04 end of side 3* 24 | G01X0Y0D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4016_1* 29 | G04 Draw part IC_CD4007_2* 30 | G04 Draw part R_12K_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_CD4007_5* 33 | G04 Draw part R_12K_6* 34 | G04 Draw part IC_CD4016_7* 35 | G04 Draw part IC_CD4007_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part R_12K_10* 38 | G04 Draw part IC_CD4016_11* 39 | G04 Draw part IC_CD4007_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_15* 42 | G04 Draw part SD* 43 | G04 Draw part R1* 44 | G04 Draw part R2* 45 | G04 Draw part R3* 46 | 47 | G04 Draw traces* 48 | 49 | G04 Draw Text* 50 | M00* 51 | M02* 52 | -------------------------------------------------------------------------------- /circuits/dtflop-ms2_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 3 4 | Active Pane: 2 5 | { 6 | traces: 1 {524292,0,"V(q)"} 7 | X: ('n',0,0,5e-009,5e-008) 8 | Y[0]: (' ',0,-5,1,6) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-5,1,6) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524290,0,"V(clk)"} 16 | X: ('n',0,0,5e-009,5e-008) 17 | Y[0]: (' ',0,-6,1,6) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,0,-6,1,6) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | Arrow: "V" 1 0 (2e-008,-4.74137931034483) (2e-008,5) 23 | Arrow: "V" 1 0 (0,-4.74137931034483) (0,4.91379310344828) 24 | Arrow: "V" 1 0 (4.00862068965517e-008,-4.82758620689655) (4.00862068965517e-008,4.91379310344828) 25 | }, 26 | { 27 | traces: 1 {589827,0,"V(d)"} 28 | X: ('n',0,0,5e-009,5e-008) 29 | Y[0]: (' ',0,-6,1,6) 30 | Y[1]: ('_',0,1e+308,0,-1e+308) 31 | Volts: (' ',0,0,0,-6,1,6) 32 | Log: 0 0 0 33 | GridStyle: 1 34 | Line: "V" 1 1 (2.00738916256158e-008,-9.02608695652174) (2.00738916256158e-008,4.74782608695652) 35 | Line: "V" 1 1 (4.01477832512315e-008,-6.82608695652174) (4.00862068965517e-008,4.73913043478261) 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /circuits/dtflop_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 3 4 | Active Pane: 1 5 | { 6 | traces: 1 {524292,0,"V(q)"} 7 | X: ('n',0,0,5e-009,5e-008) 8 | Y[0]: (' ',0,-6,1,5) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-6,1,5) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | Text: "V" 1 (1.42276422764228e-008,-4.70588235294118) ;0 14 | Text: "V" 1 (3.33333333333333e-008,-3.8) ;i 15 | Text: "V" 1 (4.52574525745257e-008,-4.5764705882353) ;1 16 | }, 17 | { 18 | traces: 1 {524291,0,"V(clk)"} 19 | X: ('n',0,0,5e-009,5e-008) 20 | Y[0]: (' ',0,-5,1,5.1) 21 | Y[1]: ('_',0,1e+308,0,-1e+308) 22 | Volts: (' ',0,0,0,-5,1,5.1) 23 | Log: 0 0 0 24 | GridStyle: 1 25 | }, 26 | { 27 | traces: 1 {524290,0,"V(d)"} 28 | X: ('n',0,0,5e-009,5e-008) 29 | Y[0]: (' ',0,-5,1,5.1) 30 | Y[1]: ('_',0,1e+308,0,-1e+308) 31 | Volts: (' ',0,0,0,-5,1,5.1) 32 | Log: 0 0 0 33 | GridStyle: 1 34 | Text: "V" 1 (4.74254742547425e-009,-3.75308641975309) ;0 35 | Text: "V" 1 (1.46341463414634e-008,-3.87777777777778) ;1 36 | Text: "V" 1 (2.84552845528455e-008,-4.00246913580247) ;i 37 | Text: "V" 1 (4.15989159891599e-008,-3.87777777777778) ;1 38 | } 39 | } 40 | -------------------------------------------------------------------------------- /circuits/pznlatch_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 176 64 -16 64 4 | WIRE 224 64 176 64 5 | WIRE 432 80 336 80 6 | WIRE 176 112 80 112 7 | WIRE 224 112 176 112 8 | WIRE 432 128 352 128 9 | WIRE 224 160 176 160 10 | WIRE -16 256 -16 64 11 | WIRE 80 256 80 112 12 | WIRE 176 256 176 160 13 | WIRE -16 352 -16 336 14 | WIRE 80 352 80 336 15 | WIRE 80 352 -16 352 16 | WIRE 176 352 176 336 17 | WIRE 176 352 80 352 18 | WIRE 80 384 80 352 19 | FLAG -144 112 $G_Vdd 20 | FLAG -144 176 $G_Vss 21 | FLAG 80 384 0 22 | FLAG 432 80 Q 23 | FLAG 432 128 _Q 24 | FLAG 176 64 P 25 | FLAG 176 112 Z 26 | FLAG 176 160 N 27 | SYMBOL voltage 176 240 R0 28 | WINDOW 3 25 113 Left 0 29 | WINDOW 123 0 0 Left 0 30 | WINDOW 39 0 0 Left 0 31 | SYMATTR Value PWL file=input_n.txt 32 | SYMATTR InstName VN 33 | SYMBOL voltage 80 240 R0 34 | WINDOW 3 -88 180 Left 0 35 | WINDOW 123 0 0 Left 0 36 | WINDOW 39 0 0 Left 0 37 | SYMATTR Value PWL file=input_z.txt 38 | SYMATTR InstName VZ 39 | SYMBOL voltage -16 240 R0 40 | WINDOW 3 -239 108 Left 0 41 | WINDOW 123 0 0 Left 0 42 | WINDOW 39 0 0 Left 0 43 | SYMATTR Value PWL file=input_p.txt 44 | SYMATTR InstName VP 45 | SYMBOL tpower -144 144 R0 46 | SYMATTR InstName U1 47 | SYMBOL pznlatch 272 16 R0 48 | SYMATTR InstName X2 49 | TEXT -256 440 Left 0 !.tran 0 65ns 35ns 50 | TEXT -256 408 Left 0 !.tran 40ns 51 | -------------------------------------------------------------------------------- /circuits/dtflop2_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 5 4 | Active Pane: 1 5 | { 6 | traces: 0 7 | X: ('n',0,0,5e-009,5e-008) 8 | Y[0]: (' ',0,1e+308,1,-1e+308) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 1 {524293,0,"V($g_vdd)"} 15 | X: ('n',0,0,5e-009,5e-008) 16 | Y[0]: (' ',3,4.994,0.001,5.005) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,4.994,0.001,5.005) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | }, 22 | { 23 | traces: 1 {524292,0,"V(q)"} 24 | X: ('n',0,0,5e-009,5e-008) 25 | Y[0]: (' ',0,-6,1,6) 26 | Y[1]: ('_',0,1e+308,0,-1e+308) 27 | Volts: (' ',0,0,0,-6,1,6) 28 | Log: 0 0 0 29 | GridStyle: 1 30 | }, 31 | { 32 | traces: 1 {524291,0,"V(clk)"} 33 | X: ('n',0,0,5e-009,5e-008) 34 | Y[0]: (' ',0,-5,1,5) 35 | Y[1]: ('_',0,1e+308,0,-1e+308) 36 | Volts: (' ',0,0,0,-5,1,5) 37 | Log: 0 0 0 38 | GridStyle: 1 39 | }, 40 | { 41 | traces: 1 {524290,0,"V(d)"} 42 | X: ('n',0,0,5e-009,5e-008) 43 | Y[0]: (' ',0,-5,1,5) 44 | Y[1]: ('_',0,1e+308,0,-1e+308) 45 | Volts: (' ',0,0,0,-5,1,5) 46 | Log: 0 0 0 47 | GridStyle: 1 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /circuits/mux3-1_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 5 4 | { 5 | traces: 1 {524294,0,"V(q)"} 6 | X: ('n',0,0,5e-009,5e-008) 7 | Y[0]: (' ',0,-6,1,6) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,0,-6,1,6) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 1 {268959749,0,"V(s)"} 15 | X: ('n',0,0,5e-009,5e-008) 16 | Y[0]: (' ',0,-5,1,5) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,-5,1,5) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | }, 22 | { 23 | traces: 1 {268959748,0,"V(c)"} 24 | X: ('n',0,0,5e-009,5e-008) 25 | Y[0]: (' ',0,-5,1,5) 26 | Y[1]: ('_',0,1e+308,0,-1e+308) 27 | Volts: (' ',0,0,0,-5,1,5) 28 | Log: 0 0 0 29 | GridStyle: 1 30 | }, 31 | { 32 | traces: 1 {268959747,0,"V(b)"} 33 | X: ('n',0,0,5e-009,5e-008) 34 | Y[0]: (' ',0,-5,1,5) 35 | Y[1]: ('_',0,1e+308,0,-1e+308) 36 | Volts: (' ',0,0,0,-5,1,5) 37 | Log: 0 0 0 38 | GridStyle: 1 39 | }, 40 | { 41 | traces: 1 {268959746,0,"V(a)"} 42 | X: ('n',0,0,5e-009,5e-008) 43 | Y[0]: (' ',0,-5,1,5) 44 | Y[1]: ('_',0,1e+308,0,-1e+308) 45 | Volts: (' ',0,0,0,-5,1,5) 46 | Log: 0 0 0 47 | GridStyle: 1 48 | } 49 | } 50 | -------------------------------------------------------------------------------- /circuits/control_parts.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG -320 -320 $G_Vdd 4 | FLAG -320 -256 $G_Vss 5 | FLAG -560 -112 M1i 6 | FLAG -560 -80 M10 7 | FLAG -560 -48 M11 8 | FLAG -560 144 M2i 9 | FLAG -560 176 M20 10 | FLAG -560 208 M21 11 | FLAG -560 432 M3i 12 | FLAG -560 464 M30 13 | FLAG -560 496 M31 14 | FLAG -448 -80 M1q 15 | FLAG -448 176 M2q 16 | FLAG -448 464 M3q 17 | FLAG -512 0 M1S 18 | FLAG -512 256 M2S 19 | FLAG -512 544 M3S 20 | FLAG -160 -128 CU_In 21 | FLAG -128 -128 CU_Out 22 | FLAG -144 -16 tand1A 23 | FLAG -144 16 tand1B 24 | FLAG -144 96 tand2A 25 | FLAG -144 128 tand2B 26 | FLAG -144 224 tand3A 27 | FLAG -144 256 tand3B 28 | FLAG -64 0 tand1Y 29 | FLAG -64 112 tand2Y 30 | FLAG -64 240 tand3Y 31 | FLAG -224 448 Din 32 | FLAG -32 400 Dout_i 33 | FLAG -32 448 Dout_0 34 | FLAG -32 496 Dout_1 35 | SYMBOL mux3-1 -496 -112 R0 36 | SYMATTR InstName Xmux1 37 | SYMBOL mux3-1 -496 144 R0 38 | SYMATTR InstName Xmux2 39 | SYMBOL mux3-1 -496 432 R0 40 | SYMATTR InstName Xmux3 41 | SYMBOL tcycle_up -144 -128 R0 42 | SYMATTR InstName XCycle_Up 43 | SYMBOL min -112 0 R0 44 | SYMATTR InstName tand1 45 | SYMBOL min -112 112 R0 46 | SYMATTR InstName tand2 47 | SYMBOL min -112 240 R0 48 | SYMATTR InstName tand3 49 | SYMBOL decoder1-3 -128 400 R0 50 | SYMATTR InstName Decoder 51 | SYMBOL tpower -320 -288 R0 52 | SYMATTR InstName Xpower 53 | -------------------------------------------------------------------------------- /circuits/pznlatch_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 5 4 | Active Pane: 2 5 | { 6 | traces: 1 {524294,0,"V(_q)"} 7 | X: ('n',0,0,4e-009,4e-008) 8 | Y[0]: (' ',0,-6,1,5) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-6,1,5) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {524293,0,"V(q)"} 16 | X: ('n',0,0,4e-009,4e-008) 17 | Y[0]: (' ',0,-5,1,6) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,0,-5,1,6) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | }, 23 | { 24 | traces: 1 {524292,0,"V(n)"} 25 | X: ('n',0,0,4e-009,4e-008) 26 | Y[0]: (' ',0,-5,1,5) 27 | Y[1]: ('_',0,1e+308,0,-1e+308) 28 | Volts: (' ',0,0,0,-5,1,5) 29 | Log: 0 0 0 30 | GridStyle: 1 31 | }, 32 | { 33 | traces: 1 {524291,0,"V(z)"} 34 | X: ('n',0,0,4e-009,4e-008) 35 | Y[0]: (' ',1,-5,0.5,0) 36 | Y[1]: ('_',0,1e+308,0,-1e+308) 37 | Volts: (' ',0,0,1,-5,0.5,0) 38 | Log: 0 0 0 39 | GridStyle: 1 40 | }, 41 | { 42 | traces: 1 {524290,0,"V(p)"} 43 | X: ('n',0,0,4e-009,4e-008) 44 | Y[0]: (' ',0,-5,1,5) 45 | Y[1]: ('_',0,1e+308,0,-1e+308) 46 | Volts: (' ',0,0,0,-5,1,5) 47 | Log: 0 0 0 48 | GridStyle: 1 49 | } 50 | } 51 | -------------------------------------------------------------------------------- /circuits/trit_reg3_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 176 -112 144 -112 4 | WIRE 192 -112 176 -112 5 | WIRE 384 -112 352 -112 6 | WIRE 48 -80 0 -80 7 | WIRE 96 -80 48 -80 8 | WIRE 144 -80 144 -112 9 | WIRE 144 -80 96 -80 10 | WIRE 192 -80 144 -80 11 | WIRE 384 -80 352 -80 12 | WIRE 48 -48 48 -80 13 | WIRE 80 -48 48 -48 14 | WIRE 160 -48 128 -48 15 | WIRE 192 -48 160 -48 16 | WIRE 384 -48 352 -48 17 | WIRE 192 64 112 64 18 | WIRE 0 208 0 -80 19 | WIRE 112 208 112 64 20 | WIRE 64 288 0 288 21 | WIRE 112 288 64 288 22 | WIRE 64 320 64 288 23 | FLAG 64 320 0 24 | FLAG -320 224 $G_Vdd 25 | FLAG -320 288 $G_Vss 26 | FLAG 112 64 CLK 27 | FLAG 384 -112 Q0 28 | FLAG 384 -80 Q1 29 | FLAG 384 -48 Q2 30 | FLAG 160 -48 D2 31 | FLAG 96 -80 D1 32 | FLAG 176 -112 D0 33 | SYMBOL voltage 112 192 R0 34 | WINDOW 123 0 0 Left 0 35 | WINDOW 39 0 0 Left 0 36 | SYMATTR InstName V1 37 | SYMATTR Value PULSE(5 -5 0 1p 1p 10n 20n) 38 | SYMBOL voltage 0 192 R0 39 | WINDOW 3 -45 164 Left 0 40 | WINDOW 123 0 0 Left 0 41 | WINDOW 39 0 0 Left 0 42 | SYMATTR Value PWL(0 0 7n 0 8n 5 17n 5 18n 0 24n 0 25n -5 34n -5 35n 5) 43 | SYMATTR InstName V2 44 | SYMBOL tpower -320 256 R0 45 | SYMATTR InstName X1 46 | SYMBOL trit_reg3 272 -160 R0 47 | SYMATTR InstName X2 48 | SYMBOL sti 96 -48 R0 49 | WINDOW 0 1 26 Center 0 50 | SYMATTR InstName Xinv 51 | TEXT 216 248 Left 0 !.tran 50n 52 | -------------------------------------------------------------------------------- /circuits/dtflop2.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 64 80 32 80 4 | WIRE 160 80 64 80 5 | WIRE 144 96 144 32 6 | WIRE 160 96 144 96 7 | WIRE 320 96 240 96 8 | WIRE 160 112 144 112 9 | WIRE 416 112 400 112 10 | WIRE 432 112 416 112 11 | WIRE 416 160 416 112 12 | WIRE 416 160 304 160 13 | WIRE 144 176 144 112 14 | WIRE 144 176 32 176 15 | WIRE 320 192 320 128 16 | WIRE 416 192 320 192 17 | WIRE 304 208 304 160 18 | WIRE 320 208 304 208 19 | WIRE 144 224 144 176 20 | WIRE 160 224 144 224 21 | WIRE 416 224 416 192 22 | WIRE 416 224 400 224 23 | WIRE 432 224 416 224 24 | WIRE 160 240 144 240 25 | WIRE 320 240 240 240 26 | WIRE 64 256 64 80 27 | WIRE 80 256 64 256 28 | WIRE 160 256 128 256 29 | WIRE 144 288 144 240 30 | FLAG 32 80 D 31 | IOPIN 32 80 In 32 | FLAG 32 176 CLK 33 | IOPIN 32 176 In 34 | FLAG 432 112 Q 35 | IOPIN 432 112 Out 36 | FLAG 432 224 _Q 37 | IOPIN 432 224 Out 38 | FLAG 144 32 X 39 | IOPIN 144 32 In 40 | FLAG 144 288 Y 41 | IOPIN 144 288 In 42 | SYMBOL sti 96 256 R0 43 | WINDOW 0 -13 -32 Left 0 44 | SYMATTR InstName X5 45 | SYMBOL tnand 352 112 R0 46 | SYMATTR InstName X1 47 | SYMBOL tnand 352 224 R0 48 | SYMATTR InstName X2 49 | SYMBOL tnand3 192 96 R0 50 | SYMATTR InstName X6 51 | SYMBOL tnand3 192 240 R0 52 | SYMATTR InstName X3 53 | TEXT -160 -32 Left 0 ;Experimental attempt at a D-flip flop with additional inputs. Not well-tested 54 | -------------------------------------------------------------------------------- /circuits/tnand.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -176 -160 -352 -160 4 | WIRE 208 -160 -176 -160 5 | WIRE -448 -112 -560 -112 6 | WIRE -400 -112 -448 -112 7 | WIRE -224 -112 -256 -112 8 | WIRE -176 -64 -352 -64 9 | WIRE -176 -48 -176 -64 10 | WIRE -176 -16 -176 -48 11 | WIRE -176 96 -176 64 12 | WIRE -112 96 -176 96 13 | WIRE -176 128 -176 96 14 | WIRE -176 224 -176 208 15 | WIRE -176 240 -176 224 16 | WIRE -448 288 -448 -112 17 | WIRE -224 288 -448 288 18 | WIRE -64 288 -176 288 19 | WIRE -176 352 -176 336 20 | WIRE -176 368 -176 352 21 | WIRE -256 416 -256 -112 22 | WIRE -256 416 -560 416 23 | WIRE -224 416 -256 416 24 | WIRE 208 464 -176 464 25 | FLAG -112 96 TNAND_Out 26 | IOPIN -112 96 Out 27 | FLAG -560 -112 A 28 | IOPIN -560 -112 In 29 | FLAG -560 416 B 30 | IOPIN -560 416 In 31 | FLAG 208 -160 $G_Vdd 32 | FLAG 208 464 $G_Vss 33 | FLAG -64 288 $G_Vss 34 | FLAG -176 -48 NP 35 | FLAG -176 224 NN 36 | FLAG -176 352 NI 37 | SYMBOL res -192 -32 R0 38 | SYMATTR InstName RP 39 | SYMATTR Value 12k 40 | SYMBOL res -192 112 R0 41 | SYMATTR InstName RN 42 | SYMATTR Value 12k 43 | SYMBOL pmos2 -224 -64 M180 44 | SYMATTR InstName MP1 45 | SYMATTR Value CD4007P 46 | SYMBOL pmos2 -400 -64 M180 47 | SYMATTR InstName MP2 48 | SYMATTR Value CD4007P 49 | SYMBOL nmos2 -224 368 R0 50 | SYMATTR InstName MN2 51 | SYMATTR Value CD4007N 52 | SYMBOL nmos5 -224 240 R0 53 | SYMATTR InstName MN1 54 | SYMATTR Value CD4007N 55 | -------------------------------------------------------------------------------- /bb/dtflop-msmo_test.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\dtflop-ms_test.asc 2 | Vclk CLK 0 PULSE(-5 5 0 1p 1p 10n 20n) 3 | Vd D 0 PWL(0 0 1n 0 5n -5 8n -5 9n 0 10n 0 11n 5 21n 5 22n 0 24n 0 25n -5 34n -5 35n -5 40n -5 41n -5 42n 0 43n 5 44n 5 45n -5 46n 0 47n -5 48n 0) 4 | XX1 $G_Vdd $G_Vss tpower 5 | Xflipflop D CLK Q dtflop-ms 6 | 7 | * block symbol definitions 8 | .subckt tpower Vdd Vss 9 | Vdd Vdd 0 5V 10 | Vss 0 Vss 5V 11 | .ends tpower 12 | 13 | .subckt dtflop-ms D C Q 14 | XX2 tg_master _Q_master sti 15 | XX4 tg_D tg_master sti 16 | XX3 tg_slave Q sti 17 | XX1 Q _Q_slave sti 18 | XXB _Q_master tg_D C tg 19 | XXC tg_slave tg_master C tg 20 | XXA D tg_D _C tg 21 | XXD _Q_slave tg_slave _C tg 22 | XX5 C _C sti 23 | .ends dtflop-ms 24 | 25 | .subckt sti IN OUT 26 | Xinv IN NC_01 OUT NC_02 tinv 27 | .ends sti 28 | 29 | .subckt tg IN_OUT OUT_IN CONTROL 30 | M1 OUT_IN _C IN_OUT $G_Vdd CD4007P 31 | M2 IN_OUT C OUT_IN $G_Vss CD4007N 32 | M3 $G_Vdd CONTROL _C $G_Vdd CD4007P 33 | M4 _C CONTROL $G_Vss $G_Vss CD4007N 34 | M5 $G_Vdd _C C $G_Vdd CD4007P 35 | M6 C _C $G_Vss $G_Vss CD4007N 36 | .ends tg 37 | 38 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 39 | RP PTI_Out STI_Out 12k 40 | RN STI_Out NTI_Out 12k 41 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 42 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 43 | .ends tinv 44 | 45 | .model NMOS NMOS 46 | .model PMOS PMOS 47 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 48 | .tran 50n 49 | .backanno 50 | .end 51 | -------------------------------------------------------------------------------- /circuits/swrom-fast.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 720 3 | WIRE 176 64 96 64 4 | WIRE 176 208 96 208 5 | WIRE -544 288 -624 288 6 | WIRE -336 288 -432 288 7 | WIRE -32 288 -32 224 8 | WIRE -624 320 -624 288 9 | WIRE -432 320 -432 288 10 | WIRE 176 336 96 336 11 | FLAG 176 64 D0 12 | IOPIN 176 64 Out 13 | FLAG 176 208 D1 14 | IOPIN 176 208 Out 15 | FLAG 176 336 D2 16 | IOPIN 176 336 Out 17 | FLAG -32 288 ADDRESS 18 | IOPIN -32 288 In 19 | FLAG 96 144 0 20 | FLAG 96 288 0 21 | FLAG 96 416 0 22 | FLAG -624 400 0 23 | FLAG -544 288 _1 24 | FLAG -432 400 0 25 | FLAG -336 288 1 26 | SYMBOL bv 96 48 R0 27 | SYMATTR InstName B1 28 | SYMATTR Value V=program_i(V(ADDRESS)) 29 | SYMBOL bv 96 192 R0 30 | SYMATTR InstName B2 31 | SYMATTR Value V=program_0(V(ADDRESS)) 32 | SYMBOL bv 96 320 R0 33 | SYMATTR InstName B3 34 | SYMATTR Value V=program_1(V(ADDRESS)) 35 | SYMBOL bv -624 304 R0 36 | SYMATTR InstName B4 37 | SYMATTR Value V=V($G_Vss) 38 | SYMBOL bv -432 304 R0 39 | SYMATTR InstName B5 40 | SYMATTR Value V=V($G_Vdd) 41 | TEXT -776 256 Left 0 ;Shortcuts so you can type V(_1) for logic -1 instead of V($G_Vss), etc. 42 | TEXT -48 -280 Left 0 ;; Note: there should be overbars over all these 1's\n; If not, go to Tools -> Sync Release, upgrade to at least 2.23y\nV=choose(V(_1),V(_1),V(_1))\nV=(V(_1),V(_1),V(_1))\nV(_1),V(_1),V(_1) 43 | TEXT -8 -8 Left 0 ;program_x should come from the top-level schematic,\nby an .include ../asm/guess.sp (for example) statement 44 | -------------------------------------------------------------------------------- /bb/tinv.py: -------------------------------------------------------------------------------- 1 | # Basic Ternary Inverter, implemented with CD4007 2 | # 3 | # TODO: embed with tinv.asc, netlist generated by 4 | 5 | nodes = ("Vin", "PTI_Out", "STI_Out", "NTI_Out") 6 | 7 | # Dual MOSFET Complementary Pair + Binary Inverter 8 | parts_generated = ["CD4007"] 9 | parts_consumed = ["MP", "MN"] 10 | parts_kept = ["RP", "RN"] 11 | 12 | # Based on pinout from http://www.cedmagic.com/tech-info/data/cd4016.pdf 13 | pins = [ 14 | { 15 | # First MOSFET pair has sources already connected to Vdd/Vss 16 | "Vin": ("CD4007", 6), 17 | "PTI_Out": ("CD4007", 13), 18 | "NTI_Out": ("CD4007", 8), 19 | "STI_Out": "STI_Out", 20 | }, 21 | { 22 | # Second MOSFET pair, need to connect sources 23 | "Vin": ("CD4007", 3), 24 | "PTI_Out": ("CD4007", 1), 25 | "NTI_Out": ("CD4007", 5), 26 | "STI_Out": "STI_Out", 27 | "$G_Vdd": ("CD4007", 2), 28 | "$G_Vss": ("CD4007", 4), 29 | }, 30 | ] 31 | 32 | # Always connected once if use once or more 33 | global_pins = { 34 | # Power connections 35 | "$G_Vdd": ("CD4007", 14), 36 | "$G_Vss": ("CD4007", 7), 37 | 38 | # TODO: always connect binary inverter, since we'll never be using it, 39 | # but to prevent MOSFETs from switching on and off, wasting power? 40 | # May need a change in this data structure to support multiple connections to $G_Vdd/Vss 41 | } 42 | 43 | -------------------------------------------------------------------------------- /bb/dtflop-ms2_test.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\dtflop-ms2_test.asc 2 | Vclk CLK 0 PULSE(-5 5 0 1p 1p 10n 20n) 3 | Vd D 0 PWL(0 0 1n 0 5n -5 8n -5 9n 0 10n 0 11n 5 21n 5 22n 0 24n 0 25n -5 34n -5 35n -5 40n -5 41n -5 42n 0 43n 5 44n 5 45n -5 46n 0 47n -5 48n 0) 4 | XX1 $G_Vdd $G_Vss tpower 5 | Xff D CLK Q _Q dtflop-ms2 6 | 7 | * block symbol definitions 8 | .subckt tpower Vdd Vss 9 | Vdd Vdd 0 5V 10 | Vss 0 Vss 5V 11 | .ends tpower 12 | 13 | .subckt dtflop-ms2 D CLK Q _Q 14 | XMaster D _CLK between NC_01 dtflop 15 | XSlave between CLK Q _Q dtflop 16 | XXstiCLK CLK _CLK sti 17 | .ends dtflop-ms2 18 | 19 | .subckt dtflop D CLK Q _Q 20 | XXlatch Q_storage _Q Q tnand 21 | X_Xlatch Q _Q_storage _Q tnand 22 | XXgatetop D CLK Q_storage tnand 23 | XXgatebot CLK _D _Q_storage tnand 24 | XXstiD D _D sti 25 | .ends dtflop 26 | 27 | .subckt sti IN OUT 28 | XXinv IN NC_01 OUT NC_02 tinv 29 | .ends sti 30 | 31 | .subckt tnand A B TNAND_Out 32 | RP NP TNAND_Out 12k 33 | RN TNAND_Out NN 12k 34 | MP1 NP B $G_Vdd $G_Vdd CD4007P 35 | MP2 NP A $G_Vdd $G_Vdd CD4007P 36 | MN2 NI B $G_Vss $G_Vss CD4007N 37 | MN1 NN A NI $G_Vss CD4007N 38 | .ends tnand 39 | 40 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 41 | RP PTI_Out STI_Out 12k 42 | RN STI_Out NTI_Out 12k 43 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 44 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 45 | .ends tinv 46 | 47 | .model NMOS NMOS 48 | .model PMOS PMOS 49 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 50 | .tran 50n 51 | .backanno 52 | .end 53 | -------------------------------------------------------------------------------- /bb/CAM-adder/top_paste_mask.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-adder\top_paste_mask.grb* 3 | G04 layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X0Y45000D02* 18 | G01X60000Y45000D01* 19 | G04 end of side 1* 20 | G01X60000Y0D01* 21 | G04 end of side 2* 22 | G01X0Y0D01* 23 | G04 end of side 3* 24 | G01X0Y45000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part R_12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part R_12K_5* 33 | G04 Draw part IC_CD4016_6* 34 | G04 Draw part IC_CD4016_7* 35 | G04 Draw part IC_CD4016_8* 36 | G04 Draw part IC_CD4016_9* 37 | G04 Draw part IC_CD4016_10* 38 | G04 Draw part IC_CD4016_11* 39 | G04 Draw part IC_CD4016_12* 40 | G04 Draw part IC_CD4016_13* 41 | G04 Draw part IC_CD4016_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_CD4007_16* 44 | G04 Draw part R_12K_17* 45 | G04 Draw part IC_CD4016_18* 46 | G04 Draw part IC_CD4016_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_CD4007_21* 49 | G04 Draw part R_12K_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part FULL_ADDER* 52 | 53 | G04 Draw traces* 54 | 55 | G04 Draw Text* 56 | M00* 57 | M02* 58 | -------------------------------------------------------------------------------- /bb/CAM-adder/bottom_paste_mask.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-adder\bottom_paste_mask.grb* 3 | G04 layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X0Y45000D02* 18 | G01X60000Y45000D01* 19 | G04 end of side 1* 20 | G01X60000Y0D01* 21 | G04 end of side 2* 22 | G01X0Y0D01* 23 | G04 end of side 3* 24 | G01X0Y45000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part R_12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part R_12K_5* 33 | G04 Draw part IC_CD4016_6* 34 | G04 Draw part IC_CD4016_7* 35 | G04 Draw part IC_CD4016_8* 36 | G04 Draw part IC_CD4016_9* 37 | G04 Draw part IC_CD4016_10* 38 | G04 Draw part IC_CD4016_11* 39 | G04 Draw part IC_CD4016_12* 40 | G04 Draw part IC_CD4016_13* 41 | G04 Draw part IC_CD4016_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_CD4007_16* 44 | G04 Draw part R_12K_17* 45 | G04 Draw part IC_CD4016_18* 46 | G04 Draw part IC_CD4016_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_CD4007_21* 49 | G04 Draw part R_12K_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part FULL_ADDER* 52 | 53 | G04 Draw traces* 54 | 55 | G04 Draw Text* 56 | M00* 57 | M02* 58 | -------------------------------------------------------------------------------- /bb/CAM-adder/board_outline.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-adder\board_outline.grb* 3 | G04 board outline layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X0Y45000D02* 18 | G01X60000Y45000D01* 19 | G04 end of side 1* 20 | G01X60000Y0D01* 21 | G04 end of side 2* 22 | G01X0Y0D01* 23 | G04 end of side 3* 24 | G01X0Y45000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part R_12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part R_12K_5* 33 | G04 Draw part IC_CD4016_6* 34 | G04 Draw part IC_CD4016_7* 35 | G04 Draw part IC_CD4016_8* 36 | G04 Draw part IC_CD4016_9* 37 | G04 Draw part IC_CD4016_10* 38 | G04 Draw part IC_CD4016_11* 39 | G04 Draw part IC_CD4016_12* 40 | G04 Draw part IC_CD4016_13* 41 | G04 Draw part IC_CD4016_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_CD4007_16* 44 | G04 Draw part R_12K_17* 45 | G04 Draw part IC_CD4016_18* 46 | G04 Draw part IC_CD4016_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_CD4007_21* 49 | G04 Draw part R_12K_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part FULL_ADDER* 52 | 53 | G04 Draw traces* 54 | 55 | G04 Draw Text* 56 | M00* 57 | M02* 58 | -------------------------------------------------------------------------------- /circuits/alu-fast.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 992 680 3 | WIRE -416 144 -464 144 4 | WIRE -416 192 -464 192 5 | WIRE 656 192 464 192 6 | WIRE 464 224 464 192 7 | WIRE -416 240 -464 240 8 | WIRE -416 304 -464 304 9 | WIRE -416 352 -464 352 10 | WIRE 464 368 464 304 11 | WIRE -416 400 -464 400 12 | FLAG -464 144 A0 13 | IOPIN -464 144 In 14 | FLAG -464 192 A1 15 | IOPIN -464 192 In 16 | FLAG -464 240 A2 17 | IOPIN -464 240 In 18 | FLAG -464 304 B0 19 | IOPIN -464 304 In 20 | FLAG -464 352 B1 21 | IOPIN -464 352 In 22 | FLAG -464 400 B2 23 | IOPIN -464 400 In 24 | FLAG 656 192 S 25 | IOPIN 656 192 Out 26 | FLAG 464 368 0 27 | SYMBOL bv 464 208 R0 28 | SYMATTR InstName B1 29 | SYMATTR Value V=compare() 30 | TEXT -176 -232 Left 0 !.param V_N_max=-2 ; TODO: put in a library file\n.param V_P_min=2\n.func is_i(A){if(A<={V_N_max},5,0)}\n.func is_1(A){if(A>={V_P_min},5,0)}\n.func is_0(A){if(is_i(A) | is_1(A),0,5)}\n.func isnt_0(A){if(is_i(A) | is_1(A),5,0)}\n.func choose(A,for_n,for_z,for_p) {if(is_i(A),for_n,if(is_1(A),for_p,for_z))}\n.func tdiscrete(A){choose(A,-1,0,1)} ; make -1, 0, or 1 31 | TEXT -232 312 Left 0 !.func compare(){if(numA()numB(),5,0))} 32 | TEXT -240 80 Left 0 !; Sign of balanced trinary number (most-significant non-zero trit)\n.func tsign(c,b,a){if(isnt_0(c),c,if(isnt_0(b),b,if(isnt_0(a),a,0)))} 33 | TEXT -360 208 Left 0 !.func num(c,b,a){a*(3**0) + b*(3**1) + c*(3**2)}\n.func numA(){num(tdiscrete(V(A2)),tdiscrete(V(A1)),tdiscrete(V(A0)))}\n.func numB(){num(tdiscrete(V(B2)),tdiscrete(V(B1)),tdiscrete(V(B0)))} 34 | -------------------------------------------------------------------------------- /circuits/tnor.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 208 -288 -176 -288 4 | WIRE -256 -240 -544 -240 5 | WIRE -224 -240 -256 -240 6 | WIRE -176 -176 -176 -192 7 | WIRE -176 -160 -176 -176 8 | WIRE -224 -112 -400 -112 9 | WIRE -48 -112 -176 -112 10 | WIRE -176 -48 -176 -64 11 | WIRE -176 -32 -176 -48 12 | WIRE -176 80 -176 48 13 | WIRE -112 80 -176 80 14 | WIRE -176 96 -176 80 15 | WIRE -176 208 -176 176 16 | WIRE -176 224 -176 208 17 | WIRE -176 224 -320 224 18 | WIRE -320 240 -320 224 19 | WIRE -176 240 -176 224 20 | WIRE -400 288 -400 -112 21 | WIRE -400 288 -544 288 22 | WIRE -368 288 -400 288 23 | WIRE -256 288 -256 -240 24 | WIRE -224 288 -256 288 25 | WIRE -320 368 -320 336 26 | WIRE -176 368 -176 336 27 | WIRE -176 368 -320 368 28 | WIRE 208 368 -176 368 29 | FLAG -112 80 TNOR_Out 30 | IOPIN -112 80 Out 31 | FLAG -544 -240 A 32 | IOPIN -544 -240 In 33 | FLAG -544 288 B 34 | IOPIN -544 288 In 35 | FLAG 208 -288 $G_Vdd 36 | FLAG 208 368 $G_Vss 37 | FLAG -48 -112 $G_Vdd 38 | FLAG -176 -48 NP 39 | FLAG -176 208 NN 40 | FLAG -176 -176 NI 41 | SYMBOL res -192 -48 R0 42 | SYMATTR InstName RP 43 | SYMATTR Value 12k 44 | SYMBOL res -192 80 R0 45 | SYMATTR InstName RN 46 | SYMATTR Value 12k 47 | SYMBOL nmos2 -224 240 R0 48 | SYMATTR InstName MN1 49 | SYMATTR Value CD4007N 50 | SYMBOL pmos2 -224 -192 M180 51 | SYMATTR InstName MP2 52 | SYMATTR Value CD4007P 53 | SYMBOL nmos2 -368 240 R0 54 | SYMATTR InstName MN2 55 | SYMATTR Value CD4007N 56 | SYMBOL pmos5 -224 -160 R0 57 | SYMATTR InstName MP1 58 | SYMATTR Value CD4007P 59 | -------------------------------------------------------------------------------- /circuits/dtflop-msmo_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 2 5 | { 6 | traces: 2 {268959751,0,"V(d0)"} {268959752,0,"V(q0)"} 7 | X: ('n',0,0,5e-009,5e-008) 8 | Y[0]: (' ',0,-6,1,6) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-6,1,6) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 1 {268959750,0,"V(q1)"} 16 | X: ('n',0,0,5e-009,5e-008) 17 | Y[0]: (' ',0,-6,1,6) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,0,-6,1,6) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | Line: "V" 1 1 (1.00243506493506e-008,33.1139240506329) (1.00243506493506e-008,-19.8987341772152) 23 | Line: "V" 1 1 (2.99918831168831e-008,33.0379746835443) (3.00324675324675e-008,-20.0506329113924) 24 | }, 25 | { 26 | traces: 2 {268959746,0,"V(d2)"} {268959748,0,"V(q2)"} 27 | X: ('n',0,0,5e-009,5e-008) 28 | Y[0]: (' ',0,-6,1,6) 29 | Y[1]: ('_',0,1e+308,0,-1e+308) 30 | Volts: (' ',0,0,0,-6,1,6) 31 | Log: 0 0 0 32 | GridStyle: 1 33 | }, 34 | { 35 | traces: 1 {268959747,0,"V(clk)"} 36 | X: ('n',0,0,5e-009,5e-008) 37 | Y[0]: (' ',0,-6,1,6) 38 | Y[1]: ('_',0,1e+308,0,-1e+308) 39 | Volts: (' ',0,0,0,-6,1,6) 40 | Log: 0 0 0 41 | GridStyle: 1 42 | Arrow: "V" 1 0 (1.00649350649351e-008,-4.93670886075949) (9.98376623376623e-009,5.08860759493671) 43 | Arrow: "V" 1 0 (3.00324675324675e-008,-4.78481012658228) (2.99918831168831e-008,5.31645569620253) 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /circuits/trit_reg3_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 4 4 | Active Pane: 2 5 | { 6 | traces: 2 {524295,0,"V(d0)"} {524296,0,"V(q0)"} 7 | X: ('n',0,0,5e-009,5e-008) 8 | Y[0]: (' ',0,-6,1,6) 9 | Y[1]: ('_',0,1e+308,0,-1e+308) 10 | Volts: (' ',0,0,0,-6,1,6) 11 | Log: 0 0 0 12 | GridStyle: 1 13 | }, 14 | { 15 | traces: 2 {524293,0,"V(d1)"} {524294,0,"V(q1)"} 16 | X: ('n',0,0,5e-009,5e-008) 17 | Y[0]: (' ',0,-6,1,6) 18 | Y[1]: ('_',0,1e+308,0,-1e+308) 19 | Volts: (' ',0,0,0,-6,1,6) 20 | Log: 0 0 0 21 | GridStyle: 1 22 | Line: "V" 1 1 (1.00243506493506e-008,33.1139240506329) (1.00243506493506e-008,-19.8987341772152) 23 | Line: "V" 1 1 (2.99918831168831e-008,33.0379746835443) (3.00324675324675e-008,-20.0506329113924) 24 | }, 25 | { 26 | traces: 2 {524290,0,"V(d2)"} {524292,0,"V(q2)"} 27 | X: ('n',0,0,5e-009,5e-008) 28 | Y[0]: (' ',0,-6,1,6) 29 | Y[1]: ('_',0,1e+308,0,-1e+308) 30 | Volts: (' ',0,0,0,-6,1,6) 31 | Log: 0 0 0 32 | GridStyle: 1 33 | }, 34 | { 35 | traces: 1 {524291,0,"V(clk)"} 36 | X: ('n',0,0,5e-009,5e-008) 37 | Y[0]: (' ',0,-6,1,6) 38 | Y[1]: ('_',0,1e+308,0,-1e+308) 39 | Volts: (' ',0,0,0,-6,1,6) 40 | Log: 0 0 0 41 | GridStyle: 1 42 | Arrow: "V" 1 0 (1.00649350649351e-008,-4.93670886075949) (9.98376623376623e-009,5.08860759493671) 43 | Arrow: "V" 1 0 (3.00324675324675e-008,-4.78481012658228) (2.99918831168831e-008,5.31645569620253) 44 | } 45 | } 46 | -------------------------------------------------------------------------------- /circuits/mux3-1_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 744 3 | WIRE 96 64 -416 64 4 | WIRE 96 96 -288 96 5 | WIRE 432 96 208 96 6 | WIRE 96 128 -144 128 7 | WIRE 144 240 144 176 8 | WIRE 144 240 -16 240 9 | WIRE -416 256 -416 64 10 | WIRE -288 256 -288 96 11 | WIRE -144 256 -144 128 12 | WIRE -16 256 -16 240 13 | WIRE 144 272 144 240 14 | WIRE -416 336 -416 320 15 | WIRE -416 368 -416 336 16 | WIRE -288 368 -288 336 17 | WIRE -288 368 -416 368 18 | WIRE -192 368 -288 368 19 | WIRE -144 368 -144 336 20 | WIRE -144 368 -192 368 21 | WIRE -16 368 -16 336 22 | WIRE -16 368 -144 368 23 | WIRE -192 384 -192 368 24 | FLAG -192 384 0 25 | FLAG -656 272 $G_Vss 26 | FLAG -656 208 $G_Vdd 27 | FLAG -416 64 A 28 | FLAG -288 96 B 29 | FLAG -144 128 C 30 | FLAG 144 272 S 31 | FLAG 432 96 Q 32 | SYMBOL voltage -416 240 R0 33 | WINDOW 3 -166 187 Left 0 34 | WINDOW 123 0 0 Left 0 35 | WINDOW 39 0 0 Left 0 36 | SYMATTR Value SINE(0 5 200Meg) 37 | SYMATTR InstName VA 38 | SYMBOL voltage -288 240 R0 39 | WINDOW 3 -101 194 Left 0 40 | WINDOW 123 0 0 Left 0 41 | WINDOW 39 0 0 Left 0 42 | SYMATTR Value SINE(0 5 1000Meg) 43 | SYMATTR InstName VB 44 | SYMBOL voltage -144 240 R0 45 | WINDOW 3 -24 199 Left 0 46 | WINDOW 123 0 0 Left 0 47 | WINDOW 39 0 0 Left 0 48 | SYMATTR Value PULSE(-5 5 0n 1p 1p 3n 6n) 49 | SYMATTR InstName VC 50 | SYMBOL voltage -16 240 R0 51 | WINDOW 123 0 0 Left 0 52 | WINDOW 39 0 0 Left 0 53 | SYMATTR InstName VS 54 | SYMATTR Value PWL(0 -5 14n -5 15n 0 29n 0 30n 5) 55 | SYMBOL tpower -656 240 R0 56 | SYMATTR InstName X11 57 | SYMBOL mux3-1 160 64 R0 58 | SYMATTR InstName X1 59 | TEXT -64 392 Left 0 !.tran 50n 60 | -------------------------------------------------------------------------------- /circuits/dtflop-et.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 1308 680 3 | WIRE 112 96 -144 96 4 | WIRE 112 144 112 96 5 | WIRE 144 144 112 144 6 | WIRE 368 144 304 144 7 | WIRE -160 160 -288 160 8 | WIRE -160 176 -160 160 9 | WIRE -144 176 -160 176 10 | WIRE -48 192 -64 192 11 | WIRE 16 192 -16 192 12 | WIRE 80 192 64 192 13 | WIRE 144 192 128 192 14 | WIRE 368 192 320 192 15 | WIRE -288 208 -288 160 16 | WIRE -288 208 -320 208 17 | WIRE -240 208 -288 208 18 | WIRE -144 208 -192 208 19 | FLAG -144 96 D 20 | IOPIN -144 96 In 21 | FLAG -320 208 CLK 22 | IOPIN -320 208 In 23 | FLAG 368 144 Q 24 | IOPIN 368 144 Out 25 | FLAG 368 192 _Q 26 | IOPIN 368 192 Out 27 | SYMBOL dtflop 224 96 R0 28 | SYMATTR InstName X1 29 | SYMBOL tnand -112 192 R0 30 | SYMATTR InstName X3 31 | SYMBOL sti -224 208 R0 32 | SYMATTR InstName X2 33 | SYMBOL tcycle_up -32 192 R0 34 | SYMATTR InstName X4 35 | SYMBOL pti 32 192 R0 36 | SYMATTR InstName X5 37 | SYMBOL pti 96 192 R0 38 | SYMATTR InstName X6 39 | TEXT -80 16 Left 0 ;UNTESTED -- a better approach may be to \nfeed a clocked PZN tri-flop 40 | TEXT -176 328 Left 0 ;5 V with pulses of ~0 V 41 | TEXT -64 288 Left 0 ;-5 V with 0 V pulses 42 | TEXT 168 272 Left 0 ;Signal is completely lost (ranges from -5.016 \nto -4.986 V) at this point due to low noise margins 43 | LINE Normal -320 288 -352 288 44 | LINE Normal -320 256 -320 288 45 | LINE Normal -288 256 -320 256 46 | LINE Normal 112 256 96 256 47 | LINE Normal 112 224 112 256 48 | LINE Normal 128 224 112 224 49 | LINE Normal 128 256 128 224 50 | LINE Normal 144 256 128 256 51 | LINE Normal -64 208 -96 320 52 | LINE Normal 0 208 -16 272 53 | LINE Normal 128 208 160 256 54 | -------------------------------------------------------------------------------- /circuits/swrom-blank.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 128 32 48 32 4 | WIRE 160 32 128 32 5 | WIRE 128 64 -32 64 6 | WIRE 160 64 128 64 7 | WIRE 128 96 -112 96 8 | WIRE 160 96 128 96 9 | WIRE 304 128 272 128 10 | WIRE 128 144 48 144 11 | WIRE 160 144 128 144 12 | WIRE 304 160 272 160 13 | WIRE 128 176 -32 176 14 | WIRE 160 176 128 176 15 | WIRE 304 192 272 192 16 | WIRE 128 208 -112 208 17 | WIRE 160 208 128 208 18 | WIRE 128 256 48 256 19 | WIRE 160 256 128 256 20 | WIRE 128 288 -32 288 21 | WIRE 160 288 128 288 22 | WIRE 128 320 -112 320 23 | WIRE 160 320 128 320 24 | WIRE 208 400 208 368 25 | FLAG 208 400 ADDRESS 26 | IOPIN 208 400 In 27 | FLAG 304 128 D0 28 | IOPIN 304 128 Out 29 | FLAG 304 160 D1 30 | IOPIN 304 160 Out 31 | FLAG 304 192 D2 32 | IOPIN 304 192 Out 33 | FLAG 128 32 NiA 34 | FLAG 128 64 NiB 35 | FLAG 128 96 NiC 36 | FLAG 128 144 N0A 37 | FLAG 128 176 N0B 38 | FLAG 128 208 N0C 39 | FLAG 128 256 N1A 40 | FLAG 128 288 N1B 41 | FLAG 128 320 N1C 42 | FLAG -336 144 $G_Vdd 43 | FLAG -336 208 $G_Vss 44 | SYMBOL mux9-3 224 32 R0 45 | SYMATTR InstName Xrom 46 | SYMBOL tpower -336 176 R0 47 | SYMATTR InstName X1 48 | SYMBOL trit-0 -16 32 M0 49 | SYMATTR InstName X2 50 | SYMBOL trit-0 -96 64 M0 51 | SYMATTR InstName X3 52 | SYMBOL trit-0 -176 96 M0 53 | SYMATTR InstName X4 54 | SYMBOL trit-0 -16 144 M0 55 | SYMATTR InstName X5 56 | SYMBOL trit-0 -96 176 M0 57 | SYMATTR InstName X6 58 | SYMBOL trit-0 -176 208 M0 59 | SYMATTR InstName X7 60 | SYMBOL trit-0 -16 256 M0 61 | SYMATTR InstName X8 62 | SYMBOL trit-0 -96 288 M0 63 | SYMATTR InstName X9 64 | SYMBOL trit-0 -176 320 M0 65 | SYMATTR InstName X10 66 | -------------------------------------------------------------------------------- /extended/Iloc_cnst.py: -------------------------------------------------------------------------------- 1 | 2 | class Iloc_cnst(object): 3 | 4 | ADD = "add" 5 | ADDI = "addi" 6 | AND = "and" 7 | CALL = "call" 8 | CBREQ = "cbreq" 9 | CBRGE = "cbrge" 10 | CBRGT = "cbrgt" 11 | CBRLE = "cbrle" 12 | CBRLT = "cbrlt" 13 | CBRNE = "cbrne" 14 | COMP = "comp" 15 | COMPI = "compi" 16 | DEL = "del" 17 | DIV = "div" 18 | EMPTY = "$" 19 | JUMPI = "jumpi" 20 | LABEL = "label" 21 | LDSW = "ldsw" 22 | LOADAI = "loadai" 23 | LOADGLOBAL = "loadglobal" 24 | LOADI = "loadi" 25 | LOADINARGUMENT = "loadinargument" 26 | LOADRET = "loadret" 27 | MOV = "mov" 28 | MULT = "mult" 29 | MULTI = "multi" 30 | NEW = "new" 31 | OR = "or" 32 | PRINT = "print" 33 | PRINTLN = "println" 34 | READ = "read" 35 | RET = "ret" 36 | STOREAI = "storeai" 37 | STOREGLOBAL = "storeglobal" 38 | STOREINARGUMENT = "storeinargument" 39 | STOREOUTARGUMENT = "storeoutargument" 40 | STORERET = "storeret" 41 | SUB = "sub" 42 | XORI = "xori" 43 | 44 | GLOBAL = "global" 45 | LOCAL = "local" 46 | STRUCT_MEMBER = "struct member" 47 | ARGUMENT = "argument" 48 | MEMORY = "memory" 49 | -------------------------------------------------------------------------------- /bb/CAM-Logic/top_paste_mask.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-logic\top_paste_mask.grb* 3 | G04 layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X-30000Y40000D02* 18 | G01X20000Y40000D01* 19 | G04 end of side 1* 20 | G01X20000Y-20000D01* 21 | G04 end of side 2* 22 | G01X-30000Y-20000D01* 23 | G04 end of side 3* 24 | G01X-30000Y40000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part IC_MDP1403-12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_MDP1403-12K_5* 33 | G04 Draw part IC_CD4007_6* 34 | G04 Draw part IC_CD4007_7* 35 | G04 Draw part IC_MDP1403-12K_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part IC_CD4007_10* 38 | G04 Draw part IC_CD4007_11* 39 | G04 Draw part IC_MDP1403-12K_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_MDP1403-12K_16* 44 | G04 Draw part IC_CD4007_17* 45 | G04 Draw part IC_MDP1403-12K_18* 46 | G04 Draw part IC_CD4007_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_MDP1403-12K_21* 49 | G04 Draw part IC_CD4007_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part IC_MDP1403-12K_24* 52 | G04 Draw part IC_CD4007_25* 53 | G04 Draw part LOGIC* 54 | 55 | G04 Draw traces* 56 | 57 | G04 Draw Text* 58 | M00* 59 | M02* 60 | -------------------------------------------------------------------------------- /circuits/tinv_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 192 -16 144 -16 4 | WIRE 272 -16 240 -16 5 | WIRE 144 32 144 -16 6 | WIRE 192 32 144 32 7 | WIRE 272 32 240 32 8 | WIRE 144 80 144 32 9 | WIRE 192 80 144 80 10 | WIRE 272 80 240 80 11 | WIRE 272 144 208 144 12 | WIRE 208 160 208 144 13 | WIRE 144 176 144 80 14 | WIRE 144 176 80 176 15 | WIRE 176 176 144 176 16 | WIRE 272 176 224 176 17 | WIRE 80 208 80 176 18 | WIRE 208 208 208 192 19 | WIRE 272 208 208 208 20 | WIRE 272 240 208 240 21 | WIRE 208 256 208 240 22 | WIRE 144 272 144 176 23 | WIRE 176 272 144 272 24 | WIRE 224 272 208 272 25 | WIRE 208 304 208 288 26 | WIRE 272 304 208 304 27 | WIRE 80 320 80 288 28 | FLAG 80 320 0 29 | FLAG 224 272 0 30 | FLAG 272 144 PTI_Out 31 | FLAG 272 176 STI_Out 32 | FLAG 272 208 NTI_Out 33 | FLAG 272 240 EPTI_Out 34 | FLAG 272 304 ENTI_Out 35 | FLAG -272 256 $G_Vss 36 | FLAG -272 192 $G_Vdd 37 | FLAG 272 -16 PTI_Out1 38 | FLAG 272 32 STI_Out1 39 | FLAG 272 80 NTI_Out1 40 | FLAG 80 176 input 41 | SYMBOL voltage 80 192 R0 42 | WINDOW 3 24 104 Invisible 0 43 | WINDOW 0 -76 7 Left 0 44 | SYMATTR Value -5V 45 | SYMATTR InstName V1 46 | SYMBOL tinv 192 176 R0 47 | WINDOW 0 -101 -44 Left 0 48 | SYMATTR InstName pti_sti_nti 49 | SYMBOL tinv 192 272 R0 50 | WINDOW 0 -69 -44 Left 0 51 | SYMATTR InstName eartheds 52 | SYMBOL tpower -272 224 R0 53 | SYMATTR InstName U3 54 | SYMBOL sti 208 32 R0 55 | WINDOW 0 -55 -32 Left 0 56 | SYMATTR InstName sti1 57 | SYMBOL nti 208 80 R0 58 | WINDOW 0 -39 -29 Center 0 59 | SYMATTR InstName nti1 60 | SYMBOL pti 208 -16 R0 61 | WINDOW 0 -42 -30 Center 0 62 | SYMATTR InstName pti1 63 | TEXT -120 248 Left 0 !.dc V1 -5 5 0.1 64 | -------------------------------------------------------------------------------- /bb/CAM-Logic/bottom_paste_mask.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-logic\bottom_paste_mask.grb* 3 | G04 layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X-30000Y40000D02* 18 | G01X20000Y40000D01* 19 | G04 end of side 1* 20 | G01X20000Y-20000D01* 21 | G04 end of side 2* 22 | G01X-30000Y-20000D01* 23 | G04 end of side 3* 24 | G01X-30000Y40000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part IC_MDP1403-12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_MDP1403-12K_5* 33 | G04 Draw part IC_CD4007_6* 34 | G04 Draw part IC_CD4007_7* 35 | G04 Draw part IC_MDP1403-12K_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part IC_CD4007_10* 38 | G04 Draw part IC_CD4007_11* 39 | G04 Draw part IC_MDP1403-12K_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_MDP1403-12K_16* 44 | G04 Draw part IC_CD4007_17* 45 | G04 Draw part IC_MDP1403-12K_18* 46 | G04 Draw part IC_CD4007_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_MDP1403-12K_21* 49 | G04 Draw part IC_CD4007_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part IC_MDP1403-12K_24* 52 | G04 Draw part IC_CD4007_25* 53 | G04 Draw part LOGIC* 54 | 55 | G04 Draw traces* 56 | 57 | G04 Draw Text* 58 | M00* 59 | M02* 60 | -------------------------------------------------------------------------------- /bb/CAM-Logic/bottom_silk.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-logic\bottom_silk.grb* 3 | G04 bottom silk layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X-30000Y40000D02* 18 | G01X20000Y40000D01* 19 | G04 end of side 1* 20 | G01X20000Y-20000D01* 21 | G04 end of side 2* 22 | G01X-30000Y-20000D01* 23 | G04 end of side 3* 24 | G01X-30000Y40000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part IC_MDP1403-12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_MDP1403-12K_5* 33 | G04 Draw part IC_CD4007_6* 34 | G04 Draw part IC_CD4007_7* 35 | G04 Draw part IC_MDP1403-12K_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part IC_CD4007_10* 38 | G04 Draw part IC_CD4007_11* 39 | G04 Draw part IC_MDP1403-12K_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_MDP1403-12K_16* 44 | G04 Draw part IC_CD4007_17* 45 | G04 Draw part IC_MDP1403-12K_18* 46 | G04 Draw part IC_CD4007_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_MDP1403-12K_21* 49 | G04 Draw part IC_CD4007_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part IC_MDP1403-12K_24* 52 | G04 Draw part IC_CD4007_25* 53 | G04 Draw part LOGIC* 54 | 55 | G04 Draw traces* 56 | 57 | G04 Draw Text* 58 | M00* 59 | M02* 60 | -------------------------------------------------------------------------------- /bb/CAM-Logic/board_outline.grb: -------------------------------------------------------------------------------- 1 | G04 FreePCB version 1.343* 2 | G04 Z:\trinary\code\bb\CAM-logic\board_outline.grb* 3 | G04 board outline layer * 4 | G04 Scale: 100 percent, Rotated: No, Reflected: No * 5 | %FSLAX24Y24*% 6 | %MOIN*% 7 | %LNTop*% 8 | %ADD10C,0.005000*% 9 | G90* 10 | G70D02* 11 | 12 | G04 Step and Repeat for panelization * 13 | 14 | G04 ----------------------- Draw board outline (positive)* 15 | %LPD*% 16 | G54D10* 17 | G01X-30000Y40000D02* 18 | G01X20000Y40000D01* 19 | G04 end of side 1* 20 | G01X20000Y-20000D01* 21 | G04 end of side 2* 22 | G01X-30000Y-20000D01* 23 | G04 end of side 3* 24 | G01X-30000Y40000D01* 25 | 26 | G04 -------------- Draw Parts, Pads, Traces, Vias and Text (positive)* 27 | %LPD*% 28 | G04 Draw part IC_CD4007_1* 29 | G04 Draw part IC_MDP1403-12K_2* 30 | G04 Draw part IC_CD4007_3* 31 | G04 Draw part IC_CD4007_4* 32 | G04 Draw part IC_MDP1403-12K_5* 33 | G04 Draw part IC_CD4007_6* 34 | G04 Draw part IC_CD4007_7* 35 | G04 Draw part IC_MDP1403-12K_8* 36 | G04 Draw part IC_CD4007_9* 37 | G04 Draw part IC_CD4007_10* 38 | G04 Draw part IC_CD4007_11* 39 | G04 Draw part IC_MDP1403-12K_12* 40 | G04 Draw part IC_CD4007_13* 41 | G04 Draw part IC_CD4007_14* 42 | G04 Draw part IC_CD4007_15* 43 | G04 Draw part IC_MDP1403-12K_16* 44 | G04 Draw part IC_CD4007_17* 45 | G04 Draw part IC_MDP1403-12K_18* 46 | G04 Draw part IC_CD4007_19* 47 | G04 Draw part IC_CD4007_20* 48 | G04 Draw part IC_MDP1403-12K_21* 49 | G04 Draw part IC_CD4007_22* 50 | G04 Draw part IC_CD4007_23* 51 | G04 Draw part IC_MDP1403-12K_24* 52 | G04 Draw part IC_CD4007_25* 53 | G04 Draw part LOGIC* 54 | 55 | G04 Draw traces* 56 | 57 | G04 Draw Text* 58 | M00* 59 | M02* 60 | -------------------------------------------------------------------------------- /circuits/dtflop2_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 1372 680 3 | WIRE 112 112 0 112 4 | WIRE 176 112 112 112 5 | WIRE 400 112 336 112 6 | WIRE 416 112 400 112 7 | WIRE 176 160 112 160 8 | WIRE 400 160 352 160 9 | WIRE 416 160 400 160 10 | WIRE 0 208 0 112 11 | WIRE 112 208 112 160 12 | WIRE 64 288 0 288 13 | WIRE 112 288 64 288 14 | WIRE 208 288 208 208 15 | WIRE 288 288 288 208 16 | WIRE 64 320 64 288 17 | WIRE 208 384 208 288 18 | WIRE 288 384 288 288 19 | WIRE 208 496 208 464 20 | WIRE 288 496 288 464 21 | FLAG 400 160 _Q 22 | FLAG 400 112 Q 23 | FLAG 64 320 0 24 | FLAG 112 112 D 25 | FLAG 112 160 CLK 26 | FLAG -320 224 $G_Vdd 27 | FLAG -320 288 $G_Vss 28 | FLAG 208 288 X 29 | FLAG 288 288 Y 30 | FLAG 208 496 0 31 | FLAG 288 496 0 32 | SYMBOL voltage 112 192 R0 33 | WINDOW 123 0 0 Left 0 34 | WINDOW 39 0 0 Left 0 35 | WINDOW 3 33 54 Left 0 36 | SYMATTR Value PULSE(-5 5 0 1p 1p 10n 20n) 37 | SYMATTR InstName V1 38 | SYMBOL voltage 0 192 R0 39 | WINDOW 3 -148 161 Left 0 40 | WINDOW 123 0 0 Left 0 41 | WINDOW 39 0 0 Left 0 42 | SYMATTR Value PWL(0 0 10n 0 11n 5 17n 5 18n 0 24n 0 25n -5 34n -5 35n 5 49n 5 50n 0 60n 0 61n 5 67n 5 68n 0 72n 0 75n -5 84n -5 85n -5) 43 | SYMATTR InstName V2 44 | SYMBOL tpower -320 256 R0 45 | SYMATTR InstName X1 46 | SYMBOL dtflop2 256 64 R0 47 | SYMATTR InstName X2 48 | SYMATTR Description Trinary D-type flip-flop, experimental. UNTESTED. 49 | SYMBOL voltage 208 368 R0 50 | WINDOW 3 -293 97 Left 0 51 | WINDOW 123 0 0 Left 0 52 | WINDOW 39 0 0 Left 0 53 | SYMATTR InstName V3 54 | SYMATTR Value PWL(0 5 50n 5 51n 5) 55 | SYMBOL voltage 288 368 R0 56 | SYMATTR InstName V4 57 | SYMATTR Value PWL(0 5 50n 5 51n -5) 58 | TEXT -152 320 Left 0 !.tran 100n 59 | -------------------------------------------------------------------------------- /circuits/pznflop.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE 128 -32 -16 -32 4 | WIRE 128 0 80 0 5 | WIRE 208 48 208 -16 6 | WIRE 240 48 208 48 7 | WIRE 304 48 240 48 8 | WIRE 304 64 256 64 9 | WIRE 416 64 384 64 10 | WIRE 448 64 416 64 11 | WIRE 128 80 -16 80 12 | WIRE 240 96 208 96 13 | WIRE 256 96 256 64 14 | WIRE 256 96 240 96 15 | WIRE 80 112 80 0 16 | WIRE 128 112 80 112 17 | WIRE 80 128 80 112 18 | WIRE 80 128 -96 128 19 | WIRE 304 128 416 64 20 | WIRE 256 144 256 96 21 | WIRE 304 144 256 144 22 | WIRE 416 144 304 80 23 | WIRE 416 144 384 144 24 | WIRE 448 144 416 144 25 | WIRE 240 160 208 160 26 | WIRE 304 160 240 160 27 | WIRE 80 208 80 128 28 | WIRE 128 208 80 208 29 | WIRE 208 224 208 160 30 | WIRE 128 240 -16 240 31 | FLAG 448 144 _Q 32 | IOPIN 448 144 Out 33 | FLAG 448 64 Q 34 | IOPIN 448 64 Out 35 | FLAG -16 -32 P 36 | IOPIN -16 -32 In 37 | FLAG -16 80 Z 38 | IOPIN -16 80 In 39 | FLAG -16 240 N 40 | IOPIN -16 240 In 41 | FLAG -96 128 CLK 42 | IOPIN -96 128 In 43 | FLAG 240 48 P_gated 44 | FLAG 240 96 Z_gated 45 | FLAG 240 160 N_gated 46 | SYMBOL tnand3 336 64 R0 47 | SYMATTR InstName Xlatch 48 | SYMBOL tnand3 336 144 R0 49 | WINDOW 0 2 44 Center 0 50 | SYMATTR InstName _Xlatch 51 | SYMBOL tnand 160 -16 R0 52 | WINDOW 0 -13 -43 Center 0 53 | SYMATTR InstName XtnandP 54 | SYMBOL tnand 160 96 R0 55 | WINDOW 0 -23 -44 Center 0 56 | SYMATTR InstName XtnandZ 57 | SYMBOL tnand 160 224 R0 58 | WINDOW 0 -17 -43 Center 0 59 | SYMATTR InstName XtnandN 60 | TEXT -96 192 Left 0 ;_1 61 | TEXT -48 144 Left 0 ;1 62 | LINE Normal -64 192 -80 192 63 | LINE Normal -64 144 -64 192 64 | LINE Normal -16 144 -64 144 65 | LINE Normal -16 192 -16 144 66 | LINE Normal 0 192 -16 192 67 | -------------------------------------------------------------------------------- /circuits/mux9-3.asy: -------------------------------------------------------------------------------- 1 | Version 4 2 | SymbolType BLOCK 3 | LINE Normal 48 -33 -64 -52 4 | LINE Normal -64 327 -64 -52 5 | LINE Normal 48 308 -64 327 6 | LINE Normal -16 319 -16 336 7 | LINE Normal 48 308 48 -33 8 | LINE Normal -33 66 -33 0 9 | LINE Normal -33 177 -33 112 10 | LINE Normal -33 290 -33 225 11 | TEXT -32 33 Left 0 _1 12 | TEXT -30 144 Left 0 0 13 | TEXT -32 256 Left 0 1 14 | TEXT -55 3 Left 0 A 15 | TEXT -55 33 Left 0 B 16 | TEXT -55 63 Left 0 C 17 | TEXT -54 117 Left 0 A 18 | TEXT -54 147 Left 0 B 19 | TEXT -54 177 Left 0 C 20 | TEXT -54 227 Left 0 A 21 | TEXT -54 257 Left 0 B 22 | TEXT -54 287 Left 0 C 23 | WINDOW 0 -7 -69 Center 0 24 | SYMATTR Description 9:3 trinary multiplexer, select from three groups of 3 trits 25 | PIN -64 0 NONE 8 26 | PINATTR PinName IiA 27 | PINATTR SpiceOrder 1 28 | PIN -64 32 NONE 8 29 | PINATTR PinName IiB 30 | PINATTR SpiceOrder 2 31 | PIN -64 112 NONE 8 32 | PINATTR PinName I0A 33 | PINATTR SpiceOrder 4 34 | PIN -64 144 NONE 8 35 | PINATTR PinName I0B 36 | PINATTR SpiceOrder 5 37 | PIN -64 176 NONE 8 38 | PINATTR PinName I0C 39 | PINATTR SpiceOrder 6 40 | PIN -64 224 NONE 8 41 | PINATTR PinName I1A 42 | PINATTR SpiceOrder 7 43 | PIN -64 256 NONE 8 44 | PINATTR PinName I1B 45 | PINATTR SpiceOrder 8 46 | PIN -64 288 NONE 8 47 | PINATTR PinName I1C 48 | PINATTR SpiceOrder 9 49 | PIN -16 336 LEFT 8 50 | PINATTR PinName S 51 | PINATTR SpiceOrder 10 52 | PIN 48 160 RIGHT 8 53 | PINATTR PinName QC 54 | PINATTR SpiceOrder 11 55 | PIN 48 128 RIGHT 8 56 | PINATTR PinName QB 57 | PINATTR SpiceOrder 12 58 | PIN 48 96 RIGHT 8 59 | PINATTR PinName QA 60 | PINATTR SpiceOrder 13 61 | PIN -64 64 NONE 8 62 | PINATTR PinName IiC 63 | PINATTR SpiceOrder 3 64 | -------------------------------------------------------------------------------- /circuits/mux9-3.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 692 3 | WIRE -32 -224 -528 -224 4 | WIRE -32 -192 -384 -192 5 | WIRE -32 -160 -256 -160 6 | WIRE 16 -112 -80 -112 7 | WIRE -32 16 -496 16 8 | WIRE -32 48 -352 48 9 | WIRE -32 80 -224 80 10 | WIRE -80 128 -80 -112 11 | WIRE 16 128 -80 128 12 | WIRE -32 272 -464 272 13 | WIRE -32 304 -320 304 14 | WIRE -32 336 -192 336 15 | WIRE -80 384 -80 128 16 | WIRE 16 384 -80 384 17 | WIRE -528 464 -528 -224 18 | WIRE -496 464 -496 16 19 | WIRE -464 464 -464 272 20 | WIRE -384 464 -384 -192 21 | WIRE -352 464 -352 48 22 | WIRE -320 464 -320 304 23 | WIRE -256 464 -256 -160 24 | WIRE -224 464 -224 80 25 | WIRE -192 464 -192 336 26 | WIRE -80 464 -80 384 27 | FLAG 80 -192 QA 28 | IOPIN 80 -192 Out 29 | FLAG 80 48 QB 30 | IOPIN 80 48 Out 31 | FLAG 80 304 QC 32 | IOPIN 80 304 Out 33 | FLAG -528 464 IiA 34 | IOPIN -528 464 In 35 | FLAG -496 464 IiB 36 | IOPIN -496 464 In 37 | FLAG -464 464 IiC 38 | IOPIN -464 464 In 39 | FLAG -384 464 I0A 40 | IOPIN -384 464 In 41 | FLAG -352 464 I0B 42 | IOPIN -352 464 In 43 | FLAG -320 464 I0C 44 | IOPIN -320 464 In 45 | FLAG -256 464 I1A 46 | IOPIN -256 464 In 47 | FLAG -224 464 I1B 48 | IOPIN -224 464 In 49 | FLAG -192 464 I1C 50 | IOPIN -192 464 In 51 | FLAG -80 464 S 52 | IOPIN -80 464 In 53 | SYMBOL mux3-1 32 -224 R0 54 | SYMATTR InstName Xmux1 55 | SYMBOL mux3-1 32 16 R0 56 | SYMATTR InstName Xmux2 57 | SYMBOL mux3-1 32 272 R0 58 | SYMATTR InstName Xmux3 59 | TEXT -520 -288 Left 0 ;9:3 multiplexer\nSelect from one of three groups of 3 trits 60 | TEXT -848 -104 Left 0 ;Note: this is inefficient; the 1:3 decoder circuitry is redundant in each\nof the 3:1 multiplexers. For efficiency, this circuit should be made from\na 1:3 decoder and 3 groups of 3 transmission gates. See alu.asc for\nan example of how to do this. 61 | -------------------------------------------------------------------------------- /circuits/pznflop_test.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 1196 680 3 | WIRE 176 64 -16 64 4 | WIRE 224 64 176 64 5 | WIRE 432 80 336 80 6 | WIRE 176 96 80 96 7 | WIRE 224 96 176 96 8 | WIRE 224 128 176 128 9 | WIRE 432 128 352 128 10 | WIRE 224 160 208 160 11 | WIRE 208 224 208 160 12 | WIRE 288 224 208 224 13 | WIRE -16 256 -16 64 14 | WIRE 80 256 80 96 15 | WIRE 176 256 176 128 16 | WIRE 288 256 288 224 17 | WIRE -16 352 -16 336 18 | WIRE 80 352 80 336 19 | WIRE 80 352 -16 352 20 | WIRE 176 352 176 336 21 | WIRE 176 352 80 352 22 | WIRE 288 352 288 336 23 | WIRE 288 352 176 352 24 | WIRE 80 384 80 352 25 | FLAG -144 112 $G_Vdd 26 | FLAG -144 176 $G_Vss 27 | FLAG 80 384 0 28 | FLAG 432 80 Q 29 | FLAG 432 128 _Q 30 | FLAG 176 64 P 31 | FLAG 176 96 Z 32 | FLAG 176 128 N 33 | FLAG 288 224 CLK 34 | SYMBOL voltage 176 240 R0 35 | WINDOW 3 -29 134 Left 0 36 | WINDOW 123 0 0 Left 0 37 | WINDOW 39 0 0 Left 0 38 | SYMATTR Value PWL(0 -5 27e-9 -5 28e-9 5 32e-9 5 33e-9 -5 45e-9 -5 51e-9 -5 52e-9 0 54e-9 -5 53e9 0) 39 | SYMATTR InstName VN 40 | SYMBOL voltage 80 240 R0 41 | WINDOW 3 -88 180 Left 0 42 | WINDOW 123 0 0 Left 0 43 | WINDOW 39 0 0 Left 0 44 | SYMATTR Value PWL(0 -5 17e-9 -5 18e-9 0 22e-9 0 23e-9 -5 60e-9 -5 61e-9 5 62e-9 5 63e-9 -5) 45 | SYMATTR InstName VZ 46 | SYMBOL voltage -16 240 R0 47 | WINDOW 3 -376 258 Left 0 48 | WINDOW 123 0 0 Left 0 49 | WINDOW 39 0 0 Left 0 50 | SYMATTR Value PWL(0 -5 8e-9 -5 9e-9 5 12e-9 5 13e-9 -5 40e-9 -5 41e-9 0 42e-9 0 43e-9 -5) 51 | SYMATTR InstName VP 52 | SYMBOL tpower -144 144 R0 53 | SYMATTR InstName U1 54 | SYMBOL pznflop 272 16 R0 55 | SYMATTR InstName X1 56 | SYMBOL voltage 288 240 R0 57 | WINDOW 123 0 0 Left 0 58 | WINDOW 39 0 0 Left 0 59 | SYMATTR InstName VCLK 60 | SYMATTR Value PULSE(-5 5 0 0.5n 0.5n 5n 10n) 61 | TEXT -256 440 Left 0 !;tran 0 65ns 35ns 62 | TEXT -256 408 Left 0 !.tran 40ns 63 | -------------------------------------------------------------------------------- /circuits/alu-fast_test.plt: -------------------------------------------------------------------------------- 1 | [Transient Analysis] 2 | { 3 | Npanes: 7 4 | { 5 | traces: 1 {524290,0,"V(s)"} 6 | X: ('n',0,0,8e-009,8e-008) 7 | Y[0]: (' ',0,-6,1,6) 8 | Y[1]: ('_',0,1e+308,0,-1e+308) 9 | Volts: (' ',0,0,0,-6,1,6) 10 | Log: 0 0 0 11 | GridStyle: 1 12 | }, 13 | { 14 | traces: 1 {524296,0,"V(b2)"} 15 | X: ('n',0,0,8e-009,8e-008) 16 | Y[0]: (' ',0,-6,1,6) 17 | Y[1]: ('_',0,1e+308,0,-1e+308) 18 | Volts: (' ',0,0,0,-6,1,6) 19 | Log: 0 0 0 20 | GridStyle: 1 21 | }, 22 | { 23 | traces: 1 {524295,0,"V(b1)"} 24 | X: ('n',0,0,8e-009,8e-008) 25 | Y[0]: (' ',0,-6,1,6) 26 | Y[1]: ('_',0,1e+308,0,-1e+308) 27 | Volts: (' ',0,0,1,-6,1,6) 28 | Log: 0 0 0 29 | GridStyle: 1 30 | }, 31 | { 32 | traces: 1 {524294,0,"V(b0)"} 33 | X: ('n',0,0,8e-009,8e-008) 34 | Y[0]: (' ',0,-6,1,6) 35 | Y[1]: ('_',0,1e+308,0,-1e+308) 36 | Volts: (' ',0,0,1,-6,1,6) 37 | Log: 0 0 0 38 | GridStyle: 1 39 | }, 40 | { 41 | traces: 1 {524293,0,"V(a2)"} 42 | X: ('n',0,0,8e-009,8e-008) 43 | Y[0]: (' ',0,-6,1,6) 44 | Y[1]: ('_',0,1e+308,0,-1e+308) 45 | Volts: (' ',0,0,0,-6,1,6) 46 | Log: 0 0 0 47 | GridStyle: 1 48 | }, 49 | { 50 | traces: 1 {524292,0,"V(a1)"} 51 | X: ('n',0,0,8e-009,8e-008) 52 | Y[0]: (' ',0,-6,1,6) 53 | Y[1]: ('_',0,1e+308,0,-1e+308) 54 | Volts: (' ',0,0,1,-6,1,6) 55 | Log: 0 0 0 56 | GridStyle: 1 57 | }, 58 | { 59 | traces: 1 {524291,0,"V(a0)"} 60 | X: ('n',0,0,8e-009,8e-008) 61 | Y[0]: (' ',0,-6,1,6) 62 | Y[1]: ('_',0,1e+308,0,-1e+308) 63 | Volts: (' ',0,0,0,-6,1,6) 64 | Log: 0 0 0 65 | GridStyle: 1 66 | } 67 | } 68 | -------------------------------------------------------------------------------- /bb/mux9-3.net: -------------------------------------------------------------------------------- 1 | * Z:\trinary\code\circuits\mux9-3.asc 2 | XX1 IiA I0A I1A S QA mux3-1 3 | XX2 IiB I0B I1B S QB mux3-1 4 | XX3 IiC I0C I1C S QC mux3-1 5 | 6 | * block symbol definitions 7 | .subckt mux3-1 A B C S Q 8 | XXtgA A Q CTRL_A tg 9 | XXtgC C Q CTRL_C tg 10 | XXtgB B Q CTRL_B tg 11 | XXdecoder S CTRL_A CTRL_B CTRL_C decoder3-1 12 | .ends mux3-1 13 | 14 | .subckt tg IN_OUT OUT_IN CONTROL 15 | M1 OUT_IN _C IN_OUT $G_Vdd CD4007P 16 | M2 IN_OUT C OUT_IN $G_Vss CD4007N 17 | M3 $G_Vdd CONTROL _C $G_Vdd CD4007P 18 | M4 _C CONTROL $G_Vss $G_Vss CD4007N 19 | M5 $G_Vdd _C C $G_Vdd CD4007P 20 | M6 C _C $G_Vss $G_Vss CD4007N 21 | .ends tg 22 | 23 | .subckt decoder3-1 IN OUT_i OUT_0 OUT_1 24 | XX1pti1 IN N1 pti 25 | XX1pti2 N1 OUT_1 pti 26 | XXinti IN OUT_i nti 27 | XX0pti N0tnand OUT_0 pti 28 | XX0sti IN N0sti sti 29 | XX0tnand IN N0sti N0tnand max 30 | .ends decoder3-1 31 | 32 | .subckt pti IN OUT 33 | Xinv IN OUT NC_01 NC_02 tinv 34 | .ends pti 35 | 36 | .subckt nti IN OUT 37 | Xinv IN NC_01 NC_02 OUT tinv 38 | .ends nti 39 | 40 | .subckt sti IN OUT 41 | Xinv IN NC_01 OUT NC_02 tinv 42 | .ends sti 43 | 44 | .subckt max A B MAX_OUT 45 | XX1 A B P001 tnor 46 | XX2 P001 MAX_OUT sti 47 | .ends max 48 | 49 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 50 | RP PTI_Out STI_Out 12k 51 | RN STI_Out NTI_Out 12k 52 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 53 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 54 | .ends tinv 55 | 56 | .subckt tnor A B TNOR_Out 57 | RP NP TNOR_Out 12k 58 | RN TNOR_Out NN 12k 59 | MN1 NN A $G_Vss $G_Vss CD4007N 60 | MP2 NI A $G_Vdd $G_Vdd CD4007P 61 | MN2 NN B $G_Vss $G_Vss CD4007N 62 | MP1 NI B NP $G_Vdd CD4007P 63 | .ends tnor 64 | 65 | .model NMOS NMOS 66 | .model PMOS PMOS 67 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 68 | * 9:3 multiplexer\nSelect from one of three groups of 3 trits 69 | .backanno 70 | .end 71 | -------------------------------------------------------------------------------- /circuits/tnand3.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | WIRE -352 -160 -544 -160 4 | WIRE -176 -160 -352 -160 5 | WIRE 208 -160 -176 -160 6 | WIRE -224 -112 -256 -112 7 | WIRE -352 -64 -544 -64 8 | WIRE -176 -64 -352 -64 9 | WIRE -176 -32 -176 -64 10 | WIRE -176 80 -176 48 11 | WIRE -112 80 -176 80 12 | WIRE -176 96 -176 80 13 | WIRE -176 208 -176 176 14 | WIRE -176 224 -176 208 15 | WIRE -176 240 -176 224 16 | WIRE -256 272 -256 -112 17 | WIRE -256 272 -672 272 18 | WIRE -224 272 -256 272 19 | WIRE -64 272 -176 272 20 | WIRE -176 336 -176 320 21 | WIRE -176 352 -176 336 22 | WIRE -400 400 -400 -112 23 | WIRE -400 400 -672 400 24 | WIRE -224 400 -400 400 25 | WIRE -64 400 -176 400 26 | WIRE -176 464 -176 448 27 | WIRE -176 480 -176 464 28 | WIRE -592 528 -592 -112 29 | WIRE -592 528 -672 528 30 | WIRE -224 528 -592 528 31 | WIRE 208 576 -176 576 32 | FLAG -112 80 TNAND_Out 33 | IOPIN -112 80 Out 34 | FLAG -672 272 A 35 | IOPIN -672 272 In 36 | FLAG -672 400 B 37 | IOPIN -672 400 In 38 | FLAG 208 -160 $G_Vdd 39 | FLAG 208 576 $G_Vss 40 | FLAG -64 400 $G_Vss 41 | FLAG -64 272 $G_Vss 42 | FLAG -672 528 C 43 | IOPIN -672 528 In 44 | FLAG -176 336 A_B 45 | FLAG -176 464 B_C 46 | FLAG -176 -32 NP 47 | FLAG -176 208 NN 48 | SYMBOL res -192 -48 R0 49 | SYMATTR InstName RP 50 | SYMATTR Value 12k 51 | SYMBOL res -192 80 R0 52 | SYMATTR InstName RN 53 | SYMATTR Value 12k 54 | SYMBOL pmos2 -224 -64 M180 55 | SYMATTR InstName MP1 56 | SYMATTR Value CD4007P 57 | SYMBOL pmos2 -400 -64 M180 58 | SYMATTR InstName MP2 59 | SYMATTR Value CD4007P 60 | SYMBOL nmos2 -224 480 R0 61 | SYMATTR InstName MN3 62 | SYMATTR Value CD4007N 63 | SYMBOL nmos5 -224 352 R0 64 | SYMATTR InstName MN2 65 | SYMATTR Value CD4007N 66 | SYMBOL pmos2 -592 -64 M180 67 | SYMATTR InstName MP3 68 | SYMATTR Value CD4007P 69 | SYMBOL nmos5 -224 224 R0 70 | SYMATTR InstName MN1 71 | SYMATTR Value CD4007N 72 | -------------------------------------------------------------------------------- /circuits/logic_board.asc: -------------------------------------------------------------------------------- 1 | Version 4 2 | SHEET 1 880 680 3 | FLAG 16 96 DEC_IN 4 | FLAG 208 48 OUT_i 5 | FLAG 208 96 OUT_0 6 | FLAG 208 144 OUT_1 7 | FLAG 16 288 CU_IN 8 | FLAG 48 288 CU_OUT 9 | FLAG 336 224 TAND_1A 10 | FLAG 336 256 TAND_1B 11 | FLAG 416 240 TAND_1Y 12 | FLAG 336 336 TAND_2A 13 | FLAG 336 368 TAND_2B 14 | FLAG 416 352 TAND_2Y 15 | FLAG 336 448 TAND_3A 16 | FLAG 336 480 TAND_3B 17 | FLAG 416 464 TAND_3Y 18 | FLAG 432 16 $G_Vdd 19 | FLAG 432 80 $G_Vss 20 | FLAG -256 32 PTI1 21 | FLAG -240 48 STI1 22 | FLAG -256 64 NTI1 23 | FLAG -288 48 INV1_IN 24 | FLAG -256 112 PTI2 25 | FLAG -240 128 STI2 26 | FLAG -256 144 NTI2 27 | FLAG -256 192 PTI3 28 | FLAG -240 208 STI3 29 | FLAG -256 224 NTI3 30 | FLAG -256 272 PTI4 31 | FLAG -240 288 STI4 32 | FLAG -256 304 NTI4 33 | FLAG -288 128 INV2_IN 34 | FLAG -288 208 INV3_IN 35 | FLAG -288 288 INV4_IN 36 | FLAG -672 48 BUF1_IN 37 | FLAG -624 48 BUF1_OUT 38 | FLAG -672 144 BUF2_IN 39 | FLAG -624 144 BUF2_OUT 40 | FLAG -672 240 BUF3_IN 41 | FLAG -624 240 BUF3_OUT 42 | FLAG -624 336 BUF4_OUT 43 | FLAG -672 336 BUF4_IN 44 | SYMBOL decoder1-3 112 48 R0 45 | WINDOW 0 -51 -37 Left 0 46 | SYMATTR InstName DECODER 47 | SYMBOL tpower 432 48 R0 48 | SYMATTR InstName X2 49 | SYMBOL tcycle_up 32 288 R0 50 | SYMATTR InstName CYCLE_UP 51 | SYMBOL min 368 240 R0 52 | SYMATTR InstName TAND_1 53 | SYMBOL min 368 352 R0 54 | SYMATTR InstName TAND_2 55 | SYMBOL min 368 464 R0 56 | SYMATTR InstName TAND_3 57 | SYMBOL tinv -272 48 R0 58 | SYMATTR InstName X7 59 | SYMBOL tinv -272 128 R0 60 | SYMATTR InstName X8 61 | SYMBOL tinv -272 208 R0 62 | SYMATTR InstName X9 63 | SYMBOL tinv -272 288 R0 64 | SYMATTR InstName X10 65 | SYMBOL tbuf -656 48 R0 66 | SYMATTR InstName BUF1 67 | SYMBOL tbuf -656 144 R0 68 | SYMATTR InstName BUF2 69 | SYMBOL tbuf -656 240 R0 70 | SYMATTR InstName BUF3 71 | SYMBOL tbuf -656 336 R0 72 | SYMATTR InstName BUF4 73 | -------------------------------------------------------------------------------- /bb/mux3-1_test.net: -------------------------------------------------------------------------------- 1 | * Z:\College\Senior Year\Trinary Research Project\trinary\circuits\mux3-1_test.asc 2 | VA A 0 SINE(0 5 200Meg) 3 | VB B 0 SINE(0 5 1000Meg) 4 | VC C 0 PULSE(-5 5 0n 1p 1p 3n 6n) 5 | VS S 0 PWL(0 -5 14n -5 15n 0 29n 0 30n 5) 6 | XX11 $G_Vdd $G_Vss tpower 7 | XX1 A B C S Q mux3-1 8 | 9 | * block symbol definitions 10 | .subckt tpower Vdd Vss 11 | Vdd Vdd 0 5V 12 | Vss 0 Vss 5V 13 | .ends tpower 14 | 15 | .subckt mux3-1 A B C S Q 16 | XXtgA A Q CTRL_A tg 17 | XXtgC C Q CTRL_C tg 18 | XXtgB B Q CTRL_B tg 19 | XXdecoder S CTRL_A CTRL_B CTRL_C decoder1-3 20 | .ends mux3-1 21 | 22 | .subckt tg IN_OUT OUT_IN CONTROL 23 | M1 OUT_IN _C IN_OUT $G_Vdd CD4007P 24 | M2 IN_OUT C OUT_IN $G_Vss CD4007N 25 | M3 $G_Vdd CONTROL _C $G_Vdd CD4007P 26 | M4 _C CONTROL $G_Vss $G_Vss CD4007N 27 | M5 $G_Vdd _C C $G_Vdd CD4007P 28 | M6 C _C $G_Vss $G_Vss CD4007N 29 | .ends tg 30 | 31 | .subckt decoder1-3 IN OUT_i OUT_0 OUT_1 32 | XX1pti IN IN_pti pti 33 | XX1sti IN_pti OUT_1 sti 34 | XXinti IN OUT_i nti 35 | XX0nor OUT_1 OUT_i OUT_0 tnor 36 | .ends decoder1-3 37 | 38 | .subckt pti IN OUT 39 | Xinv IN OUT NC_01 NC_02 tinv 40 | .ends pti 41 | 42 | .subckt sti IN OUT 43 | XXinv IN NC_01 OUT NC_02 tinv 44 | .ends sti 45 | 46 | .subckt nti IN OUT 47 | Xinv IN NC_01 NC_02 OUT tinv 48 | .ends nti 49 | 50 | .subckt tnor A B TNOR_Out 51 | RP NP TNOR_Out 12k 52 | RN TNOR_Out NN 12k 53 | MN1 NN A $G_Vss $G_Vss CD4007N 54 | MP2 NI A $G_Vdd $G_Vdd CD4007P 55 | MN2 NN B $G_Vss $G_Vss CD4007N 56 | MP1 NI B NP $G_Vdd CD4007P 57 | .ends tnor 58 | 59 | .subckt tinv Vin PTI_Out STI_Out NTI_Out 60 | RP PTI_Out STI_Out 12k 61 | RN STI_Out NTI_Out 12k 62 | MN NTI_Out Vin $G_Vss $G_Vss CD4007N 63 | MP PTI_Out Vin $G_Vdd $G_Vdd CD4007P 64 | .ends tinv 65 | 66 | .model NMOS NMOS 67 | .model PMOS PMOS 68 | .lib C:\PROGRA~1\LTC\SwCADIII\lib\cmp\standard.mos 69 | .tran 50n 70 | .backanno 71 | .end 72 | --------------------------------------------------------------------------------