├── tb ├── getchar.stdin ├── yourname.stdin ├── lisp.stdin ├── sram_test.good ├── cpu_test.bl.good ├── cpu_test.li.good ├── cpu_test.or.good ├── cpu_test.addi.good ├── cpu_test.rlwinm.good ├── cpu_test.stwlwz.good ├── cpu_test.stwu.good ├── cpu_test.getchar.good ├── cpu_test.bm_nqueen.good ├── cpu_test.putchar.good ├── cpu_test.gloval.good ├── cpu_test.hello.good ├── cpu_test.yourname.good ├── cpu_test.bm_tarai.good ├── rs232c_sim.v ├── sram_sim.v ├── sram_test.v ├── cpu_test.v └── cpu_test.fizzbuzz.good ├── psim ├── min-caml ├── ml ├── cls-bug.ml ├── cls-rec.ml ├── float.ml ├── join-reg.ml ├── join-reg2.ml ├── print.ml ├── join-stack.ml ├── join-stack2.ml ├── join-stack3.ml ├── sum.ml ├── fib.ml ├── adder.ml ├── sum-tail.ml ├── gcd.ml ├── non-tail-if2.ml ├── ack.ml ├── non-tail-if.ml ├── shuffle.ml ├── funcomp.ml ├── inprod-rec.ml ├── inprod-loop.ml ├── cls-bug2.ml ├── even-odd.ml ├── inprod.ml ├── spill2.ml ├── spill.ml ├── matmul.ml ├── matmul-flat.ml └── spill3.ml ├── min-caml.patch ├── c ├── hello.c ├── getchar.c ├── putchar.c ├── gloval.c ├── yourname.c ├── fizzbuzz.c ├── util.h ├── bm_tarai.c ├── mulhw.c ├── mullw.c ├── mulli.c ├── bm_nqueen.c └── lisp.c ├── trace_filter.rb ├── filter_stdout.rb ├── as ├── li.s ├── or.s ├── bl.s ├── addi.s ├── rlwinm.s ├── stwlwz.s └── stwu.s ├── rtl ├── ppc.qpf ├── const.v ├── ram.qip ├── pll.ppf ├── pll.qip ├── decode.v ├── clk_div.v ├── rs232c_rx.v ├── rs232c_tx.v ├── ppc.sdc ├── init.v ├── load.v ├── ram_bb.v ├── pll_bb.v ├── pll_ram_bb.v ├── ram.v ├── ppc.v ├── ppc.qsf ├── pll.v └── pll_ram.v ├── mincamlstub.c ├── diff_trace.rb ├── bin2hex.rb ├── libc.h ├── client.rb ├── psim.patch ├── Makefile ├── libc.c ├── libmincaml.S └── ppc.lds /tb/getchar.stdin: -------------------------------------------------------------------------------- 1 | x 2 | -------------------------------------------------------------------------------- /tb/yourname.stdin: -------------------------------------------------------------------------------- 1 | Alice 2 | -------------------------------------------------------------------------------- /psim: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/psim -------------------------------------------------------------------------------- /min-caml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/min-caml -------------------------------------------------------------------------------- /tb/lisp.stdin: -------------------------------------------------------------------------------- 1 | (- (+ 5 (* 3 13)) 2) 2 | (neg? (- 2 3)) 3 | 4 | -------------------------------------------------------------------------------- /ml/cls-bug.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/cls-bug.ml -------------------------------------------------------------------------------- /ml/cls-rec.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/cls-rec.ml -------------------------------------------------------------------------------- /ml/float.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/float.ml -------------------------------------------------------------------------------- /min-caml.patch: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/min-caml.patch -------------------------------------------------------------------------------- /ml/join-reg.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/join-reg.ml -------------------------------------------------------------------------------- /ml/join-reg2.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/join-reg2.ml -------------------------------------------------------------------------------- /ml/print.ml: -------------------------------------------------------------------------------- 1 | print_int 123; 2 | print_int (-456); 3 | print_int (789+0) 4 | -------------------------------------------------------------------------------- /ml/join-stack.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/join-stack.ml -------------------------------------------------------------------------------- /ml/join-stack2.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/join-stack2.ml -------------------------------------------------------------------------------- /ml/join-stack3.ml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/shinh/ppc/master/ml/join-stack3.ml -------------------------------------------------------------------------------- /c/hello.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | int main() { 4 | return puts("Hello, world!"); 5 | } 6 | -------------------------------------------------------------------------------- /c/getchar.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | int main() { 4 | putchar(getchar()); 5 | return 0; 6 | } 7 | -------------------------------------------------------------------------------- /ml/sum.ml: -------------------------------------------------------------------------------- 1 | let rec sum x = 2 | if x <= 0 then 0 else 3 | sum (x - 1) + x in 4 | print_int (sum 100) 5 | -------------------------------------------------------------------------------- /ml/fib.ml: -------------------------------------------------------------------------------- 1 | let rec fib n = 2 | if n <= 1 then n else 3 | fib (n - 1) + fib (n - 2) in 4 | print_int (fib 10) 5 | -------------------------------------------------------------------------------- /trace_filter.rb: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env ruby 2 | 3 | while gets !~ /PC: 01014/ 4 | end 5 | 6 | puts $_ 7 | puts [*$<] 8 | -------------------------------------------------------------------------------- /filter_stdout.rb: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env ruby 2 | 3 | o = '' 4 | $<.read.scan(/OUT: (.)/ms){ 5 | o += $1 6 | } 7 | print o 8 | -------------------------------------------------------------------------------- /ml/adder.ml: -------------------------------------------------------------------------------- 1 | let rec make_adder x = 2 | let rec adder y = x + y in 3 | adder in 4 | print_int ((make_adder 3) 7) 5 | -------------------------------------------------------------------------------- /ml/sum-tail.ml: -------------------------------------------------------------------------------- 1 | let rec sum acc x = 2 | if x <= 0 then acc else 3 | sum (acc + x) (x - 1) in 4 | print_int (sum 0 10000) 5 | -------------------------------------------------------------------------------- /as/li.s: -------------------------------------------------------------------------------- 1 | _start: 2 | li 0, 0x2000 3 | li 1, 0x1234 4 | li 5, 0x4444 5 | lis 31, 0x2345 6 | trap 7 | -------------------------------------------------------------------------------- /rtl/ppc.qpf: -------------------------------------------------------------------------------- 1 | DATE = "19:11:57 December 25, 2014" 2 | QUARTUS_VERSION = "12.0" 3 | 4 | # Revisions 5 | 6 | PROJECT_REVISION = "ppc" 7 | -------------------------------------------------------------------------------- /as/or.s: -------------------------------------------------------------------------------- 1 | _start: 2 | li r3, 0x1111 3 | li r4, 0x2345 4 | or r5, r3, r4 5 | mr r6, r3 6 | mr r7, r4 7 | trap 8 | -------------------------------------------------------------------------------- /ml/gcd.ml: -------------------------------------------------------------------------------- 1 | let rec gcd m n = 2 | if m = 0 then n else 3 | if m <= n then gcd m (n - m) else 4 | gcd n (m - n) in 5 | print_int (gcd 21600 337500) 6 | -------------------------------------------------------------------------------- /ml/non-tail-if2.ml: -------------------------------------------------------------------------------- 1 | let rec f _ = 12345 in 2 | let y = Array.create 10 3 in 3 | let x = 67890 in 4 | print_int (if y.(0) = 3 then f () + y.(1) + x else 7) 5 | -------------------------------------------------------------------------------- /tb/sram_test.good: -------------------------------------------------------------------------------- 1 | 12345678 2 | 12000000 3 | 00340000 4 | 00005600 5 | 00000078 6 | 12005600 7 | 98765678 8 | 98765432 9 | 12345678 10 | 12345678 11 | -------------------------------------------------------------------------------- /ml/ack.ml: -------------------------------------------------------------------------------- 1 | let rec ack x y = 2 | if x <= 0 then y + 1 else 3 | if y <= 0 then ack (x - 1) 1 else 4 | ack (x - 1) (ack x (y - 1)) in 5 | print_int (ack 2 5) 6 | -------------------------------------------------------------------------------- /mincamlstub.c: -------------------------------------------------------------------------------- 1 | #include "libc.h" 2 | 3 | int main() { 4 | char *hp, *sp; 5 | hp = malloc(40000); sp = malloc(10000); 6 | _min_caml_start(sp, hp); 7 | return 0; 8 | } 9 | -------------------------------------------------------------------------------- /as/bl.s: -------------------------------------------------------------------------------- 1 | _start: 2 | bl func 3 | li r4, 0x4567 4 | mtlr r4 5 | trap 6 | func: 7 | mflr r2 8 | li r3, 0x1234 9 | blr 10 | -------------------------------------------------------------------------------- /as/addi.s: -------------------------------------------------------------------------------- 1 | _start: 2 | li 2, 2 3 | addi 3, 2, 3 4 | li 0, 4 5 | addi 4, 0, 5 6 | 7 | lis 5, 0x2345 8 | addi 5, 5, 0x6789 9 | trap 10 | -------------------------------------------------------------------------------- /c/putchar.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | void func() {} 4 | 5 | int main() { 6 | putchar('y'); 7 | func(); 8 | putchar('a'); 9 | putchar('y'); 10 | putchar('\n'); 11 | return 0; 12 | } -------------------------------------------------------------------------------- /diff_trace.rb: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env ruby 2 | 3 | fn = ARGV[0] 4 | if !fn 5 | raise 6 | end 7 | 8 | b = File.basename(fn) 9 | a = %W(exe/#{b}.trace tb/cpu_trace.#{b}.trace) 10 | system("diff -U 40 #{a * ' '}") 11 | -------------------------------------------------------------------------------- /ml/non-tail-if.ml: -------------------------------------------------------------------------------- 1 | let x = truncate 1.23 in 2 | let y = truncate 4.56 in 3 | let z = truncate (-.7.89) in 4 | print_int 5 | ((if z < 0 then y else x) + 6 | (if x > 0 then z else y) + 7 | (if y < 0 then x else z)) 8 | -------------------------------------------------------------------------------- /ml/shuffle.ml: -------------------------------------------------------------------------------- 1 | let rec foo a b c d e f = 2 | print_int a; 3 | print_int b; 4 | print_int c; 5 | print_int d; 6 | print_int e; 7 | print_int f in 8 | let rec bar a b c d e f = 9 | foo b a d e f c in 10 | bar 1 2 3 4 5 6 11 | -------------------------------------------------------------------------------- /ml/funcomp.ml: -------------------------------------------------------------------------------- 1 | let rec compose f g = 2 | let rec composed x = g (f x) in 3 | composed in 4 | let rec dbl x = x + x in 5 | let rec inc x = x + 1 in 6 | let rec dec x = x - 1 in 7 | let h = compose inc (compose dbl dec) in 8 | print_int (h 123) 9 | -------------------------------------------------------------------------------- /ml/inprod-rec.ml: -------------------------------------------------------------------------------- 1 | let rec inprod v1 v2 i = 2 | if i < 0 then 0.0 else 3 | v1.(i) *. v2.(i) +. inprod v1 v2 (i - 1) in 4 | let v1 = Array.create 3 1.23 in 5 | let v2 = Array.create 3 4.56 in 6 | print_int (truncate (1000000. *. inprod v1 v2 2)) 7 | -------------------------------------------------------------------------------- /rtl/const.v: -------------------------------------------------------------------------------- 1 | `define PPC_INIT 2'd0 2 | `define PPC_LOAD 2'd1 3 | `define PPC_EXEC 2'd2 4 | `define PPC_FAIL 2'd3 5 | 6 | `define RAM_ADDR_BITS 14 7 | `define RAM_ADDR_MAX 14'd16383 8 | //`define RAM_ADDR_BITS 16 9 | //`define RAM_ADDR_MAX 16'd65535 10 | -------------------------------------------------------------------------------- /c/gloval.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | char buf[99]; 4 | 5 | int main() { 6 | buf[0] = 'f'; 7 | buf[1] = 'o'; 8 | buf[2] = 'o'; 9 | buf[3] = 'b'; 10 | buf[4] = 'a'; 11 | buf[5] = 'r'; 12 | buf[6] = '\0'; 13 | return puts(buf); 14 | } 15 | -------------------------------------------------------------------------------- /ml/inprod-loop.ml: -------------------------------------------------------------------------------- 1 | let rec inprod v1 v2 acc i = 2 | if i < 0 then acc else 3 | inprod v1 v2 (acc +. v1.(i) *. v2.(i)) (i - 1) in 4 | let v1 = Array.create 3 1.23 in 5 | let v2 = Array.create 3 4.56 in 6 | print_int (truncate (1000000. *. inprod v1 v2 0. 2)) 7 | -------------------------------------------------------------------------------- /as/rlwinm.s: -------------------------------------------------------------------------------- 1 | _start: 2 | lis r2, 0x1234 3 | ori r2, r2, 0x5678 4 | rlwinm r3, r2, 0, 0, 31 5 | rlwinm r4, r2, 5, 0, 31 6 | rlwinm r5, r2, 25, 7, 31 7 | rlwinm r6, r2, 0, 0, 20 8 | 9 | li r0, 1 10 | sc 11 | -------------------------------------------------------------------------------- /as/stwlwz.s: -------------------------------------------------------------------------------- 1 | _start: 2 | subi r6, r1, 16 3 | lis r2, 0x1234 4 | addi r2, r2, 0x5678 5 | stw r2, 0(r6) 6 | lwz r3, 0(r6) 7 | 8 | addi r4, r6, 4 9 | stw r2, 4(r6) 10 | lwz r5, 0(r4) 11 | 12 | trap 13 | -------------------------------------------------------------------------------- /ml/cls-bug2.ml: -------------------------------------------------------------------------------- 1 | (* thanks to http://ameblo.jp/nuevo-namasute/entry-10006785787.html 2 | and http://blog.livedoor.jp/azounoman/archives/50232574.html *) 3 | let rec f n = 4 | if n < 0 then () else 5 | (print_int n; 6 | let a = Array.create 1 f in 7 | a.(0) (n - 1)) in 8 | f 9 9 | -------------------------------------------------------------------------------- /c/yourname.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | char buf[256]; 4 | 5 | int main() { 6 | char c; 7 | int i; 8 | puts("your name?"); 9 | for (i = 0; (c = getchar()) != '\n'; i++) { 10 | buf[i] = c; 11 | } 12 | buf[i] = 0; 13 | puts("Hello"); 14 | puts(buf); 15 | return 0; 16 | } 17 | -------------------------------------------------------------------------------- /ml/even-odd.ml: -------------------------------------------------------------------------------- 1 | let t = 123 in 2 | let f = 456 in 3 | let rec even x = 4 | let rec odd x = 5 | if x > 0 then even (x - 1) else 6 | if x < 0 then even (x + 1) else 7 | f in 8 | if x > 0 then odd (x - 1) else 9 | if x < 0 then odd (x + 1) else 10 | t in 11 | print_int (even 789) 12 | -------------------------------------------------------------------------------- /as/stwu.s: -------------------------------------------------------------------------------- 1 | _start: 2 | subi r3, r1, 48 3 | li r2, 0x1234 4 | stwu r2, 4(r3) 5 | li r2, 0x2345 6 | stwu r2, 4(r3) 7 | li r2, 0x3456 8 | stwu r2, 4(r3) 9 | lwz r4, 0(r3) 10 | lwz r5, -4(r3) 11 | lwz r6, -8(r3) 12 | trap 13 | -------------------------------------------------------------------------------- /ml/inprod.ml: -------------------------------------------------------------------------------- 1 | let rec getx v = (let (x, y, z) = v in x) in 2 | let rec gety v = (let (x, y, z) = v in y) in 3 | let rec getz v = (let (x, y, z) = v in z) in 4 | let rec inprod v1 v2 = 5 | getx v1 *. getx v2 +. gety v1 *. gety v2 +. getz v1 *. getz v2 in 6 | print_int (truncate (1000000. *. inprod (1., 2., 3.) (4., 5., 6.))) 7 | -------------------------------------------------------------------------------- /rtl/ram.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "ram.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ram_bb.v"] 6 | -------------------------------------------------------------------------------- /c/fizzbuzz.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | #include "util.h" 3 | 4 | int main() { 5 | int i; 6 | for (i = 1; i <= 100; i++) { 7 | if (i % 3 == 0) { 8 | print_str("Fizz"); 9 | } 10 | if (i % 5 == 0) { 11 | print_str("Buzz"); 12 | } 13 | if (i % 3 && i % 5) { 14 | print_int(i); 15 | } 16 | puts(""); 17 | } 18 | } 19 | -------------------------------------------------------------------------------- /c/util.h: -------------------------------------------------------------------------------- 1 | void print_str(const char* p) { 2 | for (; *p; p++) 3 | putchar(*p); 4 | } 5 | 6 | void print_int(long v) { 7 | char buf[99]; 8 | char* p = buf + 98; 9 | if (v < 0) { 10 | v = -v; 11 | print_str("-"); 12 | } 13 | *p = '\0'; 14 | do { 15 | --p; 16 | *p = v % 10 + '0'; 17 | v /= 10; 18 | } while (v); 19 | print_str(p); 20 | } 21 | -------------------------------------------------------------------------------- /rtl/pll.ppf: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | -------------------------------------------------------------------------------- /c/bm_tarai.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | #include "util.h" 3 | 4 | int tarai(int x, int y, int z) { 5 | if (x <= y) 6 | return y; 7 | return tarai(tarai(x-1, y, z), tarai(y-1, z, x), tarai(z-1, x, y)); 8 | } 9 | 10 | int main() { 11 | puts("=== START ==="); 12 | print_int(tarai(6, 3, 0)); 13 | //print_int(tarai(12, 6, 0)); 14 | putchar('\n'); 15 | puts("=== END ==="); 16 | } 17 | -------------------------------------------------------------------------------- /rtl/pll.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name IP_TOOL_NAME "ALTPLL" 2 | set_global_assignment -name IP_TOOL_VERSION "14.0" 3 | set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}" 4 | set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] 5 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_bb.v"] 6 | set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] 7 | -------------------------------------------------------------------------------- /bin2hex.rb: -------------------------------------------------------------------------------- 1 | #!/usr/bin/ruby 2 | 3 | d = File.open(ARGV[0], 'r:binary', &:read) 4 | a = '' 5 | d.each_byte{|b| 6 | a += '%02x' % b 7 | if a.size == 8 8 | puts a.split("") * "_" 9 | a = '' 10 | end 11 | } 12 | 13 | if a.size > 0 14 | while a.size != 8 15 | a += '00' 16 | end 17 | puts a.split("") * "_" 18 | end 19 | 20 | __END__ 21 | 22 | d = `objdump -s -j .init -j .text #{ARGV[0]}` 23 | d.sub!(/.*?\.(init|text):\n/ms, '') 24 | d.gsub!(/ .*/, '') 25 | d.scan(/\s(\h{8})/) do 26 | puts $1.split("") * "_" 27 | end 28 | -------------------------------------------------------------------------------- /c/mulhw.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | int main() { 4 | int result; 5 | asm volatile("mulhw %0, %1, %2" 6 | :"=r"(result) 7 | :"r"(2999999), "r"(3000000)); 8 | printf("%d\n", result); 9 | asm volatile("mulhw %0, %1, %2" 10 | :"=r"(result) 11 | :"r"(2999999), "r"(-3000000)); 12 | printf("%d\n", result); 13 | asm volatile("mulhw %0, %1, %2" 14 | :"=r"(result) 15 | :"r"(-2999999), "r"(3000000)); 16 | printf("%d\n", result); 17 | asm volatile("mulhw %0, %1, %2" 18 | :"=r"(result) 19 | :"r"(-2999999), "r"(-3000000)); 20 | printf("%d\n", result); 21 | } 22 | -------------------------------------------------------------------------------- /c/mullw.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | int main() { 4 | int result; 5 | asm volatile("mullw %0, %1, %2" 6 | :"=r"(result) 7 | :"r"(2999999), "r"(3000000)); 8 | printf("%d\n", result); 9 | asm volatile("mullw %0, %1, %2" 10 | :"=r"(result) 11 | :"r"(2999999), "r"(-3000000)); 12 | printf("%d\n", result); 13 | asm volatile("mullw %0, %1, %2" 14 | :"=r"(result) 15 | :"r"(-2999999), "r"(3000000)); 16 | printf("%d\n", result); 17 | asm volatile("mullw %0, %1, %2" 18 | :"=r"(result) 19 | :"r"(-2999999), "r"(-3000000)); 20 | printf("%d\n", result); 21 | } 22 | -------------------------------------------------------------------------------- /rtl/decode.v: -------------------------------------------------------------------------------- 1 | module decode(input [31:0] op, 2 | output [5:0] opcode, 3 | output [9:0] sub_opcode, 4 | output [4:0] d, 5 | output [4:0] a, 6 | output [4:0] b, 7 | output [2:0] crfd, 8 | output [15:0] imm, 9 | output signed [31:0] simm); 10 | assign opcode = op[31:26]; 11 | assign sub_opcode = op[10:1]; 12 | assign d = op[25:21]; 13 | assign a = op[20:16]; 14 | assign b = op[15:11]; 15 | assign crfd = op[25:23]; 16 | assign imm = op[15:0]; 17 | assign simm = {{16{op[15]}}, op[15:0]}; 18 | endmodule // decode 19 | -------------------------------------------------------------------------------- /tb/cpu_test.bl.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 01010 3 | R00: 00000000 4 | R01: 00010000 5 | R02: 00001004 6 | R03: 00001234 7 | R04: 00004567 8 | R05: 00010010 9 | R06: 00010138 10 | R07: 00000000 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 00000000 35 | XER: 00000000 36 | LR: 00004567 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /tb/cpu_test.li.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 01014 3 | R00: 00002000 4 | R01: 00001234 5 | R02: 00000000 6 | R03: 00000001 7 | R04: 00010008 8 | R05: 00004444 9 | R06: 00010138 10 | R07: 00000000 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 23450000 35 | XER: 00000000 36 | LR: 00000000 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /tb/cpu_test.or.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 01018 3 | R00: 00000000 4 | R01: 00010000 5 | R02: 00000000 6 | R03: 00001111 7 | R04: 00002345 8 | R05: 00003355 9 | R06: 00001111 10 | R07: 00002345 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 00000000 35 | XER: 00000000 36 | LR: 00000000 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /tb/cpu_test.addi.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 0101c 3 | R00: 00000004 4 | R01: 00010000 5 | R02: 00000002 6 | R03: 00000005 7 | R04: 00000005 8 | R05: 23456789 9 | R06: 00010138 10 | R07: 00000000 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 00000000 35 | XER: 00000000 36 | LR: 00000000 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /tb/cpu_test.rlwinm.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 01020 3 | R00: 00000001 4 | R01: 00010000 5 | R02: 12345678 6 | R03: 12345678 7 | R04: 468acf02 8 | R05: 002468ac 9 | R06: 12345000 10 | R07: 00000000 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 00000000 35 | XER: 00000000 36 | LR: 00000000 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /tb/cpu_test.stwlwz.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 01024 3 | R00: 00000000 4 | R01: 00010000 5 | R02: 12345678 6 | R03: 12345678 7 | R04: 0000fff4 8 | R05: 12345678 9 | R06: 0000fff0 10 | R07: 00000000 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 00000000 35 | XER: 00000000 36 | LR: 00000000 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /tb/cpu_test.stwu.good: -------------------------------------------------------------------------------- 1 | CPU State: 7 2 | PC: 0102c 3 | R00: 00000000 4 | R01: 00010000 5 | R02: 00003456 6 | R03: 0000ffdc 7 | R04: 00003456 8 | R05: 00002345 9 | R06: 00001234 10 | R07: 00000000 11 | R08: 00000000 12 | R09: 00000000 13 | R10: 00000000 14 | R11: 00000000 15 | R12: 00000000 16 | R13: 00000000 17 | R14: 00000000 18 | R15: 00000000 19 | R16: 00000000 20 | R17: 00000000 21 | R18: 00000000 22 | R19: 00000000 23 | R20: 00000000 24 | R21: 00000000 25 | R22: 00000000 26 | R23: 00000000 27 | R24: 00000000 28 | R25: 00000000 29 | R26: 00000000 30 | R27: 00000000 31 | R28: 00000000 32 | R29: 00000000 33 | R30: 00000000 34 | R31: 00000000 35 | XER: 00000000 36 | LR: 00000000 37 | CTR: 00000000 38 | RAM: xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 39 | -------------------------------------------------------------------------------- /ml/spill2.ml: -------------------------------------------------------------------------------- 1 | (* http://smpl.seesaa.net/article/9342186.html#comment *) 2 | let rec f _ = 12345 in 3 | let rec g y = y + 1 in 4 | let z = Array.create 10 1 in 5 | let x = f () in 6 | let y = 67890 in 7 | let z0 = z.(0) in 8 | let z1 = z0 + z0 in 9 | let z2 = z1 + z1 in 10 | let z3 = z2 + z2 in 11 | let z4 = z3 + z3 in 12 | let z5 = z4 + z4 in 13 | let z6 = z5 + z5 in 14 | let z7 = z6 + z6 in 15 | let z8 = z7 + z7 in 16 | let z9 = z8 + z8 in 17 | let z10 = z9 + z9 in 18 | let z11 = z10 + z10 in 19 | let z12 = z11 + z11 in 20 | let z13 = z12 + z12 in 21 | let z14 = z13 + z13 in 22 | let z15 = z14 + z14 in 23 | print_int 24 | (if z.(1) = 0 then g y else 25 | z0 + z1 + z2 + z3 + z4 + z5 + z6 + z7 + 26 | z8 + z9 + z10 + z11 + z12 + z13 + z14 + z15 + x) 27 | -------------------------------------------------------------------------------- /rtl/clk_div.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module clk_div(clk, rst, div, clk_out); 4 | input wire clk; 5 | input wire rst; 6 | input wire [15:0] div; 7 | output wire clk_out; 8 | 9 | reg [15:0] counter; 10 | reg clk_out_reg; 11 | 12 | assign clk_out = clk_out_reg; 13 | 14 | always @(posedge clk) begin 15 | if (rst == 1'b1) begin 16 | counter <= 0; 17 | clk_out_reg <= 1; 18 | end else begin 19 | if (counter == div) begin 20 | counter <= 0; 21 | clk_out_reg <= 1; 22 | end else begin 23 | counter <= counter + 1; 24 | clk_out_reg <= 0; 25 | end 26 | end 27 | end 28 | 29 | endmodule // clk_div 30 | -------------------------------------------------------------------------------- /tb/cpu_test.getchar.good: -------------------------------------------------------------------------------- 1 | OUT: x 2 | CPU State: 7 3 | PC: 01028 4 | R00: 00000001 5 | R01: 0000fff0 6 | R02: 00000000 7 | R03: 00000000 8 | R04: 00000000 9 | R05: 00000001 10 | R06: 00000078 11 | R07: 00000001 12 | R08: 00000001 13 | R09: 00000001 14 | R10: 00000000 15 | R11: 00000000 16 | R12: 00000000 17 | R13: 00000000 18 | R14: 00000000 19 | R15: 00000000 20 | R16: 00000000 21 | R17: 00000000 22 | R18: 00000000 23 | R19: 00000000 24 | R20: 00000000 25 | R21: 00000000 26 | R22: 00000000 27 | R23: 00000000 28 | R24: 00000000 29 | R25: 00000000 30 | R26: 00000000 31 | R27: 00000000 32 | R28: 00000000 33 | R29: 00000000 34 | R30: 00000000 35 | R31: 0000fff0 36 | XER: 00000000 37 | LR: 00001018 38 | CTR: 00000000 39 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 40 | -------------------------------------------------------------------------------- /tb/cpu_test.bm_nqueen.good: -------------------------------------------------------------------------------- 1 | OUT: 4 2 | OUT: 0 3 | OUT: 4 | 5 | CPU State: 7 6 | PC: 01028 7 | R00: 00000001 8 | R01: 0000fff0 9 | R02: 00000000 10 | R03: 00000000 11 | R04: 00000000 12 | R05: 00000001 13 | R06: 0000000a 14 | R07: 00000001 15 | R08: 00000001 16 | R09: 00000000 17 | R10: 00000000 18 | R11: 00000000 19 | R12: 00000007 20 | R13: 00000000 21 | R14: 00000000 22 | R15: 00000000 23 | R16: 00000000 24 | R17: 00000000 25 | R18: 00000000 26 | R19: 00000000 27 | R20: 00000000 28 | R21: 00000000 29 | R22: 00000000 30 | R23: 00000000 31 | R24: 00000000 32 | R25: 00000000 33 | R26: 00000000 34 | R27: 00000000 35 | R28: 00000000 36 | R29: 00000000 37 | R30: 00000000 38 | R31: 0000fff0 39 | XER: 00000000 40 | LR: 00001018 41 | CTR: 00000000 42 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 43 | -------------------------------------------------------------------------------- /tb/cpu_test.putchar.good: -------------------------------------------------------------------------------- 1 | OUT: y 2 | OUT: a 3 | OUT: y 4 | OUT: 5 | 6 | CPU State: 7 7 | PC: 01028 8 | R00: 00000001 9 | R01: 0000fff0 10 | R02: 00000000 11 | R03: 00000000 12 | R04: 00000000 13 | R05: 00000001 14 | R06: 0000000a 15 | R07: 00000001 16 | R08: 00000001 17 | R09: 00000000 18 | R10: 00000000 19 | R11: 00000000 20 | R12: 00000000 21 | R13: 00000000 22 | R14: 00000000 23 | R15: 00000000 24 | R16: 00000000 25 | R17: 00000000 26 | R18: 00000000 27 | R19: 00000000 28 | R20: 00000000 29 | R21: 00000000 30 | R22: 00000000 31 | R23: 00000000 32 | R24: 00000000 33 | R25: 00000000 34 | R26: 00000000 35 | R27: 00000000 36 | R28: 00000000 37 | R29: 00000000 38 | R30: 00000000 39 | R31: 0000fff0 40 | XER: 00000000 41 | LR: 00001018 42 | CTR: 00000000 43 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 44 | -------------------------------------------------------------------------------- /tb/cpu_test.gloval.good: -------------------------------------------------------------------------------- 1 | OUT: f 2 | OUT: o 3 | OUT: o 4 | OUT: b 5 | OUT: a 6 | OUT: r 7 | OUT: 8 | 9 | CPU State: 7 10 | PC: 01028 11 | R00: 00000001 12 | R01: 0000fff0 13 | R02: 00000000 14 | R03: 00000001 15 | R04: 00000001 16 | R05: 00000001 17 | R06: 00000001 18 | R07: 00000001 19 | R08: 00000001 20 | R09: 00000001 21 | R10: 00000000 22 | R11: 00000000 23 | R12: 00000000 24 | R13: 00000000 25 | R14: 00000000 26 | R15: 00000000 27 | R16: 00000000 28 | R17: 00000000 29 | R18: 00000000 30 | R19: 00000000 31 | R20: 00000000 32 | R21: 00000000 33 | R22: 00000000 34 | R23: 00000000 35 | R24: 00000000 36 | R25: 00000000 37 | R26: 00000000 38 | R27: 00000000 39 | R28: 00000000 40 | R29: 00000000 41 | R30: 00000000 42 | R31: 0000fff0 43 | XER: 00000000 44 | LR: 00001018 45 | CTR: 00000000 46 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 47 | -------------------------------------------------------------------------------- /c/mulli.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | int main() { 4 | int result; 5 | asm volatile("mulli %0, %1, 30000" 6 | :"=r"(result) 7 | :"r"(29999)); 8 | printf("%d\n", result); 9 | asm volatile("mulli %0, %1, -30000" 10 | :"=r"(result) 11 | :"r"(29999)); 12 | printf("%d\n", result); 13 | asm volatile("mulli %0, %1, 30000" 14 | :"=r"(result) 15 | :"r"(-29999)); 16 | printf("%d\n", result); 17 | asm volatile("mulli %0, %1, -30000" 18 | :"=r"(result) 19 | :"r"(-29999)); 20 | printf("%d\n", result); 21 | asm volatile("mulli %0, %1, 30000" 22 | :"=r"(result) 23 | :"r"(-2999999)); 24 | printf("%d\n", result); 25 | asm volatile("mulli %0, %1, -30000" 26 | :"=r"(result) 27 | :"r"(-2999999)); 28 | printf("%d\n", result); 29 | } 30 | -------------------------------------------------------------------------------- /tb/cpu_test.hello.good: -------------------------------------------------------------------------------- 1 | OUT: H 2 | OUT: e 3 | OUT: l 4 | OUT: l 5 | OUT: o 6 | OUT: , 7 | OUT: 8 | OUT: w 9 | OUT: o 10 | OUT: r 11 | OUT: l 12 | OUT: d 13 | OUT: ! 14 | OUT: 15 | 16 | CPU State: 7 17 | PC: 01028 18 | R00: 00000001 19 | R01: 0000fff0 20 | R02: 00000000 21 | R03: 00000001 22 | R04: 00000001 23 | R05: 00000001 24 | R06: 00000001 25 | R07: 00000001 26 | R08: 00000001 27 | R09: 00000001 28 | R10: 00000000 29 | R11: 00000000 30 | R12: 00000000 31 | R13: 00000000 32 | R14: 00000000 33 | R15: 00000000 34 | R16: 00000000 35 | R17: 00000000 36 | R18: 00000000 37 | R19: 00000000 38 | R20: 00000000 39 | R21: 00000000 40 | R22: 00000000 41 | R23: 00000000 42 | R24: 00000000 43 | R25: 00000000 44 | R26: 00000000 45 | R27: 00000000 46 | R28: 00000000 47 | R29: 00000000 48 | R30: 00000000 49 | R31: 0000fff0 50 | XER: 00000000 51 | LR: 00001018 52 | CTR: 00000000 53 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 54 | -------------------------------------------------------------------------------- /libc.h: -------------------------------------------------------------------------------- 1 | int main(); 2 | 3 | // stddef.h 4 | typedef unsigned long size_t; 5 | 6 | // stdio.h - output 7 | int write(int fd, const void* buf, int cnt); 8 | int putchar(int c); 9 | int puts(const char* s); 10 | int printf(const char* fmt, ...); 11 | int fprintf(void* fp, const char* fmt, ...); 12 | int fputc(int c, void* fp); 13 | 14 | // stdio.h - input 15 | int read(int fd, void* buf, int cnt); 16 | int getchar(void); 17 | int scanf(const char* fmt, ...); 18 | 19 | // stdlib.h - alloc 20 | void* malloc(size_t s); 21 | void* calloc(size_t n, size_t s); 22 | void free(void* p); 23 | 24 | // stdlib.h 25 | void exit(int s); 26 | 27 | // string.h 28 | void* memcpy(void* d, const void* s, size_t n); 29 | void* memset(void* s, int c, size_t n); 30 | size_t strlen(const char* s); 31 | char* strcat(char* d, const char* s); 32 | 33 | // math.h 34 | double sqrt(double x); 35 | double sin(double x); 36 | double cos(double x); 37 | double atan(double x); 38 | double floor(double x); 39 | 40 | #define NULL 0 41 | -------------------------------------------------------------------------------- /tb/cpu_test.yourname.good: -------------------------------------------------------------------------------- 1 | OUT: y 2 | OUT: o 3 | OUT: u 4 | OUT: r 5 | OUT: 6 | OUT: n 7 | OUT: a 8 | OUT: m 9 | OUT: e 10 | OUT: ? 11 | OUT: 12 | 13 | OUT: H 14 | OUT: e 15 | OUT: l 16 | OUT: l 17 | OUT: o 18 | OUT: 19 | 20 | OUT: A 21 | OUT: l 22 | OUT: i 23 | OUT: c 24 | OUT: e 25 | OUT: 26 | 27 | CPU State: 7 28 | PC: 01028 29 | R00: 00000001 30 | R01: 0000fff0 31 | R02: 00000000 32 | R03: 00000000 33 | R04: 00000000 34 | R05: 00000001 35 | R06: 00000001 36 | R07: 00000001 37 | R08: 00000001 38 | R09: 00000001 39 | R10: 00000000 40 | R11: 00000000 41 | R12: 00000000 42 | R13: 00000000 43 | R14: 00000000 44 | R15: 00000000 45 | R16: 00000000 46 | R17: 00000000 47 | R18: 00000000 48 | R19: 00000000 49 | R20: 00000000 50 | R21: 00000000 51 | R22: 00000000 52 | R23: 00000000 53 | R24: 00000000 54 | R25: 00000000 55 | R26: 00000000 56 | R27: 00000000 57 | R28: 00000000 58 | R29: 00000000 59 | R30: 00000000 60 | R31: 0000fff0 61 | XER: 00000000 62 | LR: 00001018 63 | CTR: 00000000 64 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 65 | -------------------------------------------------------------------------------- /tb/cpu_test.bm_tarai.good: -------------------------------------------------------------------------------- 1 | OUT: = 2 | OUT: = 3 | OUT: = 4 | OUT: 5 | OUT: S 6 | OUT: T 7 | OUT: A 8 | OUT: R 9 | OUT: T 10 | OUT: 11 | OUT: = 12 | OUT: = 13 | OUT: = 14 | OUT: 15 | 16 | OUT: 6 17 | OUT: 18 | 19 | OUT: = 20 | OUT: = 21 | OUT: = 22 | OUT: 23 | OUT: E 24 | OUT: N 25 | OUT: D 26 | OUT: 27 | OUT: = 28 | OUT: = 29 | OUT: = 30 | OUT: 31 | 32 | CPU State: 7 33 | PC: 01028 34 | R00: 00000001 35 | R01: 0000fff0 36 | R02: 00000000 37 | R03: 00000000 38 | R04: 00000000 39 | R05: 00000001 40 | R06: 00000001 41 | R07: 00000001 42 | R08: 00000001 43 | R09: 00000001 44 | R10: 00000000 45 | R11: 00000000 46 | R12: 00000000 47 | R13: 00000000 48 | R14: 00000000 49 | R15: 00000000 50 | R16: 00000000 51 | R17: 00000000 52 | R18: 00000000 53 | R19: 00000000 54 | R20: 00000000 55 | R21: 00000000 56 | R22: 00000000 57 | R23: 00000000 58 | R24: 00000000 59 | R25: 00000000 60 | R26: 00000000 61 | R27: 00000000 62 | R28: 00000000 63 | R29: 00000000 64 | R30: 00000000 65 | R31: 0000fff0 66 | XER: 00000000 67 | LR: 00001018 68 | CTR: 00000000 69 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 70 | -------------------------------------------------------------------------------- /ml/spill.ml: -------------------------------------------------------------------------------- 1 | let rec f a b c d = 2 | let e = a + b in 3 | let f = a + c in 4 | let g = a + d in 5 | let h = b + c in 6 | let i = b + d in 7 | let j = c + d in 8 | 9 | let k = e + f in 10 | let l = e + g in 11 | let m = e + h in 12 | let n = e + i in 13 | let o = e + j in 14 | let p = f + g in 15 | let q = f + h in 16 | let r = f + i in 17 | let s = f + j in 18 | let t = g + h in 19 | let u = g + i in 20 | let v = g + j in 21 | let w = h + i in 22 | let x = h + j in 23 | let y = i + j in 24 | 25 | let aa = k + l in 26 | let ab = k + m in 27 | let ac = k + n in 28 | let ad = k + o in 29 | let ae = k + p in 30 | let af = k + q in 31 | let ag = k + r in 32 | let ah = k + s in 33 | let ai = k + t in 34 | let aj = k + u in 35 | let ak = k + v in 36 | let al = k + w in 37 | let am = k + x in 38 | let an = k + y in 39 | 40 | let z = a + b + c + d + 41 | e + f + g + h + i + j + 42 | k + l + m + n + o + p + q + r + s + t + u + v + w + x + y + 43 | aa + ab + ac + ad + ae + af + ag + ah + ai + aj + ak + al + am + an in 44 | -z in 45 | print_int (f 1 2 3 4) 46 | -------------------------------------------------------------------------------- /ml/matmul.ml: -------------------------------------------------------------------------------- 1 | let rec mul l m n a b c = 2 | let rec loop1 i = 3 | if i < 0 then () else 4 | let rec loop2 j = 5 | if j < 0 then () else 6 | let rec loop3 k = 7 | if k < 0 then () else 8 | (c.(i).(j) <- c.(i).(j) +. a.(i).(k) *. b.(k).(j); 9 | loop3 (k - 1)) in 10 | loop3 (m - 1); 11 | loop2 (j - 1) in 12 | loop2 (n - 1); 13 | loop1 (i - 1) in 14 | loop1 (l - 1) in 15 | let dummy = Array.create 0 0. in 16 | let rec make m n = 17 | let mat = Array.create m dummy in 18 | let rec init i = 19 | if i < 0 then () else 20 | (mat.(i) <- Array.create n 0.; 21 | init (i - 1)) in 22 | init (m - 1); 23 | mat in 24 | let a = make 2 3 in 25 | let b = make 3 2 in 26 | let c = make 2 2 in 27 | a.(0).(0) <- 1.; a.(0).(1) <- 2.; a.(0).(2) <- 3.; 28 | a.(1).(0) <- 4.; a.(1).(1) <- 5.; a.(1).(2) <- 6.; 29 | b.(0).(0) <- 7.; b.(0).(1) <- 8.; 30 | b.(1).(0) <- 9.; b.(1).(1) <- 10.; 31 | b.(2).(0) <- 11.; b.(2).(1) <- 12.; 32 | mul 2 3 2 a b c; 33 | print_int (truncate (c.(0).(0))); 34 | print_newline (); 35 | print_int (truncate (c.(0).(1))); 36 | print_newline (); 37 | print_int (truncate (c.(1).(0))); 38 | print_newline (); 39 | print_int (truncate (c.(1).(1))); 40 | print_newline () 41 | -------------------------------------------------------------------------------- /ml/matmul-flat.ml: -------------------------------------------------------------------------------- 1 | let rec loop3 i k j a b c = 2 | if k < 0 then () else 3 | (c.(i).(j) <- c.(i).(j) +. a.(i).(k) *. b.(k).(j); 4 | loop3 i (k - 1) j a b c) in 5 | let rec loop2 i m j a b c = 6 | if j < 0 then () else 7 | (loop3 i (m - 1) j a b c; 8 | loop2 i m (j - 1) a b c) in 9 | let rec loop1 i m n a b c = 10 | if i < 0 then () else 11 | (loop2 i m (n - 1) a b c; 12 | loop1 (i - 1) m n a b c) in 13 | let rec mul l m n a b c = 14 | loop1 (l - 1) m n a b c in 15 | let dummy = Array.create 0 0. in 16 | let rec init i n mat = 17 | if i < 0 then () else 18 | (mat.(i) <- Array.create n 0.; 19 | init (i - 1) n mat) in 20 | let rec make m n dummy = 21 | let mat = Array.create m dummy in 22 | init (m - 1) n mat; 23 | mat in 24 | let a = make 2 3 dummy in 25 | let b = make 3 2 dummy in 26 | let c = make 2 2 dummy in 27 | a.(0).(0) <- 1.; a.(0).(1) <- 2.; a.(0).(2) <- 3.; 28 | a.(1).(0) <- 4.; a.(1).(1) <- 5.; a.(1).(2) <- 6.; 29 | b.(0).(0) <- 7.; b.(0).(1) <- 8.; 30 | b.(1).(0) <- 9.; b.(1).(1) <- 10.; 31 | b.(2).(0) <- 11.; b.(2).(1) <- 12.; 32 | mul 2 3 2 a b c; 33 | print_int (truncate (c.(0).(0))); 34 | print_newline (); 35 | print_int (truncate (c.(0).(1))); 36 | print_newline (); 37 | print_int (truncate (c.(1).(0))); 38 | print_newline (); 39 | print_int (truncate (c.(1).(1))); 40 | print_newline () 41 | -------------------------------------------------------------------------------- /tb/rs232c_sim.v: -------------------------------------------------------------------------------- 1 | module rs232_sim(input clk, 2 | input tx_req, 3 | output tx_ready, 4 | input [7:0] tx_data, 5 | output rx_ready, 6 | output [7:0] rx_data); 7 | reg [7:0] tx_wait = 0; 8 | 9 | assign tx_ready = tx_wait == 0; 10 | 11 | reg [31:0] rx_buf[65535:0]; 12 | reg [31:0] rx_ptr; 13 | reg [15:0] rx_wait = 500; 14 | assign rx_data = (rx_buf[rx_ptr >> 2] >> (3 - (rx_ptr & 3)) * 8) & 255; 15 | assign rx_ready = rx_wait == 0; 16 | 17 | initial begin 18 | $readmemh(`STDIN, rx_buf); 19 | rx_wait <= 4000; 20 | rx_ptr <= -1; 21 | end 22 | 23 | always @(posedge clk) begin 24 | if (tx_wait) begin 25 | tx_wait <= tx_wait - 1; 26 | end else if (tx_req) begin 27 | tx_wait <= 50; 28 | `ifdef TRACE 29 | $write("%c", tx_data); 30 | `else 31 | $display("OUT: %c", tx_data); 32 | `endif 33 | end 34 | 35 | if (rx_wait == 1) begin 36 | rx_ptr <= rx_ptr + 1; 37 | rx_wait <= rx_wait - 1; 38 | end else if (rx_wait == 0) begin 39 | rx_wait <= 4000; 40 | end else begin 41 | rx_wait <= rx_wait - 1; 42 | end 43 | end 44 | 45 | endmodule // rs232_sim 46 | -------------------------------------------------------------------------------- /ml/spill3.ml: -------------------------------------------------------------------------------- 1 | (* http://blog.livedoor.jp/azounoman/archives/50392600.html *) 2 | let rec f x0 = 3 | let x1 = x0 + 1 in 4 | let x2 = x1 + 1 in 5 | let x3 = x2 + 1 in 6 | let x4 = x3 + 1 in 7 | let x5 = x4 + 1 in 8 | let x6 = x5 + 1 in 9 | let x7 = x6 + 1 in 10 | let x8 = x7 + 1 in 11 | let x9 = x8 + 1 in 12 | let x10 = x9 + 1 in 13 | let x11 = x10 + 1 in 14 | let x12 = x11 + 1 in 15 | let x13 = x12 + 1 in 16 | let x14 = x13 + 1 in 17 | let x15 = x14 + 1 in 18 | let x16 = x15 + 1 in 19 | let x17 = x16 + 1 in 20 | let x18 = x17 + 1 in 21 | let x19 = x18 + x1 in 22 | let x20 = x19 + x2 in 23 | let x21 = x20 + x3 in 24 | let x22 = x21 + x4 in 25 | let x23 = x22 + x5 in 26 | let x24 = x23 + x6 in 27 | let x25 = x24 + x7 in 28 | let x26 = x25 + x8 in 29 | let x27 = x26 + x9 in 30 | let x28 = x27 + x10 in 31 | let x29 = x28 + x11 in 32 | let x30 = x29 + x12 in 33 | let x31 = x30 + x13 in 34 | let x32 = x31 + x14 in 35 | let x33 = x32 + x15 in 36 | let x34 = x33 + x16 in 37 | let x35 = x34 + x17 in 38 | let x36 = x35 + x0 in 39 | x1 + x2 + x3 + x4 + x5 + x6 + x7 + x8 + x9 + 40 | x10 + x11 + x12 + x13 + x14 + x15 + x16 + x17 + x18 + x19 + 41 | x20 + x21 + x22 + x23 + x24 + x25 + x26 + x27 + x28 + x29 + 42 | x30 + x31 + x32 + x33 + x34 + x35 + x36 + x0 in 43 | print_int (f 0) 44 | -------------------------------------------------------------------------------- /client.rb: -------------------------------------------------------------------------------- 1 | #!/usr/bin/env ruby 2 | # -*- coding: binary -*- 3 | 4 | require 'serialport' 5 | 6 | def File.read(filename) 7 | File.open(filename, 'r:binary') do |f| 8 | f.read 9 | end 10 | end 11 | 12 | sp = SerialPort.new(Dir.glob('/dev/ttyUSB?')[0], 19200, 8, 1, 0) 13 | 14 | wrbuf = '' 15 | code = File.read(ARGV[0]) 16 | while code[-1] == "\0" 17 | code.chomp!("\0") 18 | end 19 | size = code.size 20 | checksum = 0 21 | code.each_byte{|b| 22 | checksum ^= b 23 | } 24 | STDERR.puts "code size=#{size} checksum=%x" % checksum 25 | 26 | wrbuf << ((size >> 16) & 255) 27 | wrbuf << ((size >> 8) & 255) 28 | wrbuf << (size & 255) 29 | wrbuf << code 30 | wrbuf << checksum 31 | 32 | while true 33 | rs, ws = IO::select([sp], [], [], 0.01) 34 | if rs && rs[0] == sp 35 | sp.getc 36 | else 37 | break 38 | end 39 | end 40 | 41 | inbuf = ''.b 42 | start_time = nil 43 | while true 44 | ws = [] 45 | if !wrbuf.empty? 46 | ws = [sp] 47 | end 48 | 49 | rs, ws = IO::select([STDIN, sp], ws, [], 0.2) 50 | if rs && rs[0] == STDIN 51 | c = STDIN.getc 52 | wrbuf << c 53 | elsif rs && rs[0] == sp 54 | c = sp.getc 55 | STDOUT.write(c) 56 | STDOUT.flush 57 | if c == "\n" 58 | if inbuf =~ /\=== START ===/ 59 | start_time = Time.new 60 | elsif inbuf =~ /\=== END ===/ 61 | STDERR.puts Time.new - start_time 62 | end 63 | inbuf = '' 64 | else 65 | inbuf += c.b 66 | end 67 | end 68 | 69 | if ws && ws[0] == sp 70 | sp.write(wrbuf[0]) 71 | wrbuf = wrbuf[1..-1] 72 | #if wrbuf.size % 1000 == 0 73 | # STDERR.puts "#{wrbuf.size} left" 74 | #end 75 | end 76 | end 77 | -------------------------------------------------------------------------------- /tb/sram_sim.v: -------------------------------------------------------------------------------- 1 | `include "const.v" 2 | 3 | module sram(input [`RAM_ADDR_BITS-1:0] addr, 4 | input [`RAM_ADDR_BITS-1:0] addr2, 5 | input [3:0] byteen, 6 | input clk, 7 | input [31:0] data, 8 | input [31:0] data2, 9 | input wren, 10 | input wren2, 11 | output [31:0] q, 12 | output [31:0] q2); 13 | reg [31:0] mem [`RAM_ADDR_MAX:0]; 14 | reg [`RAM_ADDR_BITS-1:0] addr_buf; 15 | reg [`RAM_ADDR_BITS-1:0] addr2_buf; 16 | reg [31:0] data_buf; 17 | reg [3:0] byteen_buf; 18 | reg wren_buf; 19 | 20 | assign q = { byteen_buf[3] ? mem[addr_buf][31:24] : 8'h00, 21 | byteen_buf[2] ? mem[addr_buf][23:16] : 8'h00, 22 | byteen_buf[1] ? mem[addr_buf][15:8] : 8'h00, 23 | byteen_buf[0] ? mem[addr_buf][7:0] : 8'h00 }; 24 | assign q2 = mem[addr2_buf]; 25 | 26 | always @(posedge clk) begin 27 | addr_buf <= addr; 28 | addr2_buf <= addr2; 29 | data_buf <= data; 30 | byteen_buf <= byteen; 31 | wren_buf <= wren; 32 | 33 | if (wren_buf) begin 34 | if (byteen_buf[3]) begin 35 | mem[addr_buf][3*8+7:3*8] <= data_buf[3*8+7:3*8]; 36 | end 37 | if (byteen_buf[2]) begin 38 | mem[addr_buf][2*8+7:2*8] <= data_buf[2*8+7:2*8]; 39 | end 40 | if (byteen_buf[1]) begin 41 | mem[addr_buf][1*8+7:1*8] <= data_buf[1*8+7:1*8]; 42 | end 43 | if (byteen_buf[0]) begin 44 | mem[addr_buf][0*8+7:0*8] <= data_buf[0*8+7:0*8]; 45 | end 46 | end 47 | end 48 | endmodule // sram 49 | -------------------------------------------------------------------------------- /rtl/rs232c_rx.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module rs232c_rx(clk, rst, din, rd, dout); 4 | parameter sys_clk = 50000000; 5 | parameter rate = 19200; 6 | 7 | input wire clk; 8 | input wire rst; 9 | input wire din; 10 | output wire rd; 11 | output reg [7:0] dout; 12 | reg [7:0] parallel; 13 | reg serial; 14 | reg start; 15 | reg rdi; 16 | reg [7:0] cbit; 17 | 18 | wire rx_en; 19 | wire [15:0] rx_div; 20 | 21 | assign rx_div = (((sys_clk / rate) / 16) - 1); 22 | clk_div div(.clk(clk), .rst(rst), .div(rx_div), .clk_out(rx_en)); 23 | 24 | assign rd = rdi & rx_en; 25 | 26 | always @(posedge rx_en or posedge rst) begin 27 | if (rst) begin 28 | start <= 0; 29 | cbit <= 0; 30 | parallel <= 0; 31 | dout <= 0; 32 | end else begin 33 | rdi <= 0; 34 | if (start == 0) begin 35 | if (din == 0) begin 36 | start <= 1; 37 | end 38 | end else begin 39 | serial <= din; 40 | case (cbit) 41 | 6: begin 42 | if (serial == 1) begin 43 | start <= 0; 44 | cbit <= 0; 45 | end else begin 46 | cbit <= cbit + 1; 47 | end 48 | end 49 | 22, 38, 54, 70, 86, 102, 118, 134: begin 50 | cbit <= cbit + 1; 51 | parallel <= {serial, parallel[7:1]}; 52 | end 53 | 150: begin 54 | cbit <= 0; 55 | dout <= parallel; 56 | start <= 0; 57 | rdi <= 1; 58 | end 59 | default: begin 60 | cbit <= cbit + 1; 61 | end 62 | endcase // case (cbit) 63 | end // else: !if(start == 0) 64 | end 65 | end 66 | 67 | endmodule // rs232c_rx 68 | -------------------------------------------------------------------------------- /tb/sram_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/100ps 2 | 3 | module sram_test; 4 | reg [12:0] addr; 5 | reg [12:0] addr2; 6 | reg [3:0] byteen; 7 | reg clk; 8 | reg [31:0] data; 9 | reg wren; 10 | wire [31:0] out; 11 | wire [31:0] out2; 12 | 13 | sram sram(.addr(addr), 14 | .addr2(addr2), 15 | .byteen(byteen), 16 | .clk(clk), 17 | .data(data), 18 | .wren(wren), 19 | .q(out), 20 | .q2(out2)); 21 | 22 | always #1 clk = !clk; 23 | 24 | task write(input [12:0] a, 25 | input [3:0] b, 26 | input [31:0] d); 27 | begin 28 | addr <= a; 29 | byteen <= b; 30 | data <= d; 31 | wren <= 1'b1; 32 | #2; 33 | end 34 | endtask // write 35 | 36 | task read(input [12:0] a, 37 | input [3:0] b); 38 | begin 39 | addr <= a; 40 | byteen <= b; 41 | wren <= 1'b0; 42 | #2; 43 | end 44 | endtask // read 45 | 46 | task read2(input [12:0] a); 47 | begin 48 | addr2 <= a; 49 | wren <= 1'b0; 50 | #2; 51 | end 52 | endtask // read2 53 | 54 | task read_and_display(input [12:0] a, 55 | input [3:0] b); 56 | begin 57 | read(a, b); 58 | $display("%x", out); 59 | end 60 | endtask // read_and_display 61 | 62 | initial begin 63 | $dumpfile("sram_test.vcd"); 64 | clk <= 1'b0; 65 | wren <= 1'b0; 66 | 67 | write(12'h0, 4'b1111, 32'h12345678); 68 | write(12'h1, 4'b1111, 32'h12345678); 69 | read_and_display(12'h0, 4'b1111); 70 | read_and_display(12'h0, 4'b1000); 71 | read_and_display(12'h0, 4'b0100); 72 | read_and_display(12'h0, 4'b0010); 73 | read_and_display(12'h0, 4'b0001); 74 | read_and_display(12'h0, 4'b1010); 75 | 76 | write(12'h0, 4'b1100, 32'h9876dead); 77 | read_and_display(12'h0, 4'b1111); 78 | write(12'h0, 4'b0011, 32'hdead5432); 79 | read_and_display(12'h0, 4'b1111); 80 | 81 | read_and_display(12'h1, 4'b1111); 82 | 83 | read2(12'h1); 84 | $display("%x", out2); 85 | 86 | $finish; 87 | end 88 | 89 | endmodule // sram_test 90 | -------------------------------------------------------------------------------- /rtl/rs232c_tx.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | module rs232c_tx(clk, rst, wr, din, dout, ready); 4 | parameter sys_clk = 50000000; 5 | parameter rate = 19200; 6 | 7 | input wire clk; 8 | input wire rst; 9 | input wire wr; 10 | input wire [7:0] din; 11 | output reg dout; 12 | output wire ready; 13 | 14 | reg [7:0] in_din; 15 | reg load; 16 | reg [2:0] cbit; 17 | reg run; 18 | 19 | wire tx_en; 20 | wire [15:0] tx_div; 21 | 22 | reg [3:0] status; 23 | 24 | assign ready = (run == 0 && load == 0) ? 1 : 0; 25 | 26 | assign tx_div = ((sys_clk / rate) - 1); 27 | clk_div div(.clk(clk), .rst(rst), .div(tx_div), .clk_out(tx_en)); 28 | 29 | always @(posedge clk or posedge rst) begin 30 | if (rst == 1) begin 31 | load <= 0; 32 | end else begin 33 | if (wr == 1 && run == 0) begin 34 | load <= 1; 35 | in_din <= din; 36 | end 37 | if (load == 1 && run == 1) begin 38 | load <= 0; 39 | end 40 | end // else: !if(rst == 1) 41 | end // always @ (posedge clk or posedge rst) 42 | 43 | always @(posedge tx_en or posedge rst) begin 44 | if (rst == 1) begin 45 | dout <= 1; 46 | cbit <= 0; 47 | run <= 0; 48 | status <= 0; 49 | end else begin 50 | if (status == 0) begin 51 | if (load == 1) begin 52 | // The start bit. 53 | dout <= 0; 54 | cbit <= 0; 55 | run <= 1; 56 | status <= 1; 57 | end else begin 58 | dout <= 1; 59 | run <= 0; 60 | end 61 | end else if (status == 1) begin // if (status == 0) 62 | if (cbit == 7) begin 63 | status <= 2; 64 | end 65 | cbit <= cbit + 1; 66 | dout <= in_din[cbit]; 67 | end else if (status == 2) begin 68 | status <= 0; 69 | dout <= 1; 70 | end else begin 71 | status <= 0; 72 | dout <= 1; 73 | end 74 | end // else: !if(rst == 1) 75 | end 76 | 77 | // reg [23:0] counter = 24'h000000; 78 | // always @(posedge clk) begin 79 | // counter <= counter + 1; 80 | // if (counter == 0) begin 81 | // dout <= !dout; 82 | // end 83 | // end 84 | 85 | endmodule // rs232c_tx 86 | -------------------------------------------------------------------------------- /rtl/ppc.sdc: -------------------------------------------------------------------------------- 1 | #************************************************************** 2 | # This .sdc file is created by Terasic Tool. 3 | # Users are recommended to modify this file to match users logic. 4 | #************************************************************** 5 | 6 | #************************************************************** 7 | # Create Clock 8 | #************************************************************** 9 | create_clock -period 20 [get_ports CLOCK_50] 10 | 11 | #************************************************************** 12 | # Create Generated Clock 13 | #************************************************************** 14 | derive_pll_clocks 15 | 16 | 17 | 18 | #************************************************************** 19 | # Set Clock Latency 20 | #************************************************************** 21 | 22 | 23 | 24 | #************************************************************** 25 | # Set Clock Uncertainty 26 | #************************************************************** 27 | derive_clock_uncertainty 28 | 29 | 30 | 31 | #************************************************************** 32 | # Set Input Delay 33 | #************************************************************** 34 | 35 | 36 | 37 | #************************************************************** 38 | # Set Output Delay 39 | #************************************************************** 40 | 41 | 42 | 43 | #************************************************************** 44 | # Set Clock Groups 45 | #************************************************************** 46 | 47 | 48 | 49 | #************************************************************** 50 | # Set False Path 51 | #************************************************************** 52 | 53 | 54 | 55 | #************************************************************** 56 | # Set Multicycle Path 57 | #************************************************************** 58 | 59 | 60 | 61 | #************************************************************** 62 | # Set Maximum Delay 63 | #************************************************************** 64 | 65 | 66 | 67 | #************************************************************** 68 | # Set Minimum Delay 69 | #************************************************************** 70 | 71 | 72 | 73 | #************************************************************** 74 | # Set Input Transition 75 | #************************************************************** 76 | 77 | 78 | 79 | #************************************************************** 80 | # Set Load 81 | #************************************************************** 82 | 83 | 84 | 85 | -------------------------------------------------------------------------------- /c/bm_nqueen.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | #include "util.h" 3 | 4 | int *board; 5 | int **stack; 6 | char **reaches; 7 | int dir[3]; 8 | int num; 9 | int size; 10 | static const int size3 = 64; 11 | 12 | void show_board() { 13 | int i, j; 14 | for (i = 0; i < size; i++) { 15 | for (j = 0; j < size; j++) { 16 | print_int(board[i*size+j]); 17 | print_str(" "); 18 | //printf("%d ", board[i*size+j]); 19 | } 20 | puts(""); 21 | } 22 | } 23 | 24 | int search4(int d, int *p){ 25 | int s = 0; 26 | int *n = p + num; 27 | int *q = p + num/2; 28 | int even = num&1 == 0; 29 | int *first = q; 30 | while (1) { 31 | if(!*q){ 32 | if(d==1){ 33 | s++; 34 | if (even || !*first) s++; 35 | } 36 | else{ 37 | char **rp = reaches + ((q-board)<<6); 38 | while (*rp) ++**rp++; 39 | *stack++=q; 40 | d--; 41 | q=n+1; 42 | n+=size; 43 | } 44 | } 45 | q++; 46 | while (q == n) { 47 | char **rp; 48 | if(d==num) { 49 | return s; 50 | } 51 | n-=size; 52 | d++; 53 | q=*--stack; 54 | rp = reaches + ((q-board)<<6); 55 | while (*rp) --**rp++; 56 | q++; 57 | } 58 | } 59 | } 60 | 61 | int main(int argc, char* argv[]){ 62 | int i,j,k; 63 | //if(argc==1)return 1; 64 | //num = atoi(argv[1]); 65 | num = 7; 66 | size = num+2; 67 | board = (int*)malloc(sizeof(int)*size*size); 68 | stack = (int**)malloc(sizeof(int*)*size); 69 | reaches = (char**)malloc(size*size*size3); 70 | dir[0]=size-1; 71 | dir[1]=size; 72 | dir[2]=size+1; 73 | for(i=0; iprogram_counter); 14 | + } 15 | + if (ppc_trace[trace_reg]) { 16 | + int i; 17 | + for (i = 0; i < 32; i++) { 18 | + printf("R%02d: %08x\n", i, p->regs.gpr[i]); 19 | + } 20 | + printf("CR:"); 21 | + for (i = 0; i < 32; i++) { 22 | + if (i % 4 == 0) 23 | + putchar(' '); 24 | + printf("%d", (p->regs.cr >> (31 - i)) & 1); 25 | + } 26 | + puts(""); 27 | + printf("XER: %08x\n", p->regs.spr[spr_xer]); 28 | + printf("LR: %08x\n", p->regs.spr[spr_lr]); 29 | + printf("CTR: %08x\n", p->regs.spr[spr_ctr]); 30 | + } 31 | + if (ppc_trace[trace_pc] || ppc_trace[trace_reg] || ppc_trace[trace_mem]) { 32 | + fflush(stdout); 33 | + } 34 | +} 35 | + 36 | #endif /* _CPU_C_ */ 37 | diff --git a/sim/ppc/cpu.h b/sim/ppc/cpu.h 38 | index cb141f2..83512a4 100644 39 | --- a/sim/ppc/cpu.h 40 | +++ b/sim/ppc/cpu.h 41 | @@ -250,4 +250,6 @@ INLINE_CPU\ 42 | # include "cpu.c" 43 | #endif 44 | 45 | +void show_trace(cpu* p); 46 | + 47 | #endif 48 | diff --git a/sim/ppc/debug.c b/sim/ppc/debug.c 49 | index 1ec279b..3de0e12 100644 50 | --- a/sim/ppc/debug.c 51 | +++ b/sim/ppc/debug.c 52 | @@ -84,7 +84,10 @@ static trace_option_descriptor trace_description[] = { 53 | /*{ trace_tbd, "tbd", "Trace any missing features" },*/ 54 | { trace_print_device_tree, "print-device-tree", "Output the contents of the device tree" }, 55 | { trace_dump_device_tree, "dump-device-tree", "Output the contents of the device tree then exit" }, 56 | - /* sentinal */ 57 | + { trace_pc, "pc" }, 58 | + { trace_reg, "regs" }, 59 | + { trace_mem, "mem" }, 60 | + /* sentinal */ 61 | { nr_trace_options, NULL }, 62 | }; 63 | 64 | diff --git a/sim/ppc/debug.h b/sim/ppc/debug.h 65 | index fdf2e3c..1440cd7 100644 66 | --- a/sim/ppc/debug.h 67 | +++ b/sim/ppc/debug.h 68 | @@ -75,6 +75,9 @@ typedef enum { 69 | trace_print_info, 70 | trace_print_device_tree, 71 | trace_dump_device_tree, 72 | + trace_pc, 73 | + trace_reg, 74 | + trace_mem, 75 | nr_trace_options 76 | } trace_options; 77 | 78 | diff --git a/sim/ppc/emul_unix.c b/sim/ppc/emul_unix.c 79 | index d72525d..97a5e15 100644 80 | --- a/sim/ppc/emul_unix.c 81 | +++ b/sim/ppc/emul_unix.c 82 | @@ -957,8 +957,9 @@ emul_unix_create(device *root, 83 | /* establish a few defaults */ 84 | if (image->xvec->flavour == bfd_target_elf_flavour) { 85 | elf_binary = 1; 86 | - top_of_stack = 0xe0000000; 87 | - stack_size = 0x00100000; 88 | + //top_of_stack = 0xe0000000; 89 | + top_of_stack = 0x00009100; 90 | + stack_size = 0x00002000; 91 | } 92 | else { 93 | elf_binary = 0; 94 | diff --git a/sim/ppc/gen-idecode.c b/sim/ppc/gen-idecode.c 95 | index 256ba75..4daa527 100644 96 | --- a/sim/ppc/gen-idecode.c 97 | +++ b/sim/ppc/gen-idecode.c 98 | @@ -914,6 +914,8 @@ print_run_until_stop_body(lf *file, 99 | lf_putstr(file, "unsigned_word cia =\n"); 100 | lf_putstr(file, " cpu_get_program_counter(processor);\n"); 101 | 102 | + lf_putstr(file, "show_trace(processor);\n"); 103 | + 104 | if (!(code & generate_with_icache)) { 105 | lf_putstr(file, "instruction_word instruction =\n"); 106 | lf_putstr(file, " vm_instruction_map_read(cpu_instruction_map(processor), processor, cia);\n"); 107 | -------------------------------------------------------------------------------- /tb/cpu_test.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns/100ps 2 | 3 | `include "const.v" 4 | 5 | module cpu_test; 6 | reg rst; 7 | reg clk; 8 | reg ram_clk; 9 | 10 | wire [`RAM_ADDR_BITS-1:0] ram_addr; 11 | wire [`RAM_ADDR_BITS-1:0] ram_addr2; 12 | wire [3:0] ram_byteen; 13 | wire [31:0] ram_wrdata; 14 | wire [31:0] ram_wrdata2; 15 | wire ram_wren; 16 | wire ram_wren2; 17 | wire [31:0] ram_rddata; 18 | wire [31:0] ram_rddata2; 19 | assign ram_addr = cpu_ram_addr; 20 | assign ram_byteen = cpu_ram_byteen; 21 | assign ram_wrdata = cpu_ram_wrdata; 22 | assign ram_wren = cpu_ram_wren; 23 | assign ram_addr2 = cpu_ram_addr2; 24 | assign ram_wrdata2 = 0; 25 | assign ram_wren2 = 0; 26 | 27 | sram sram(.addr(ram_addr), 28 | .addr2(ram_addr2), 29 | .byteen(ram_byteen), 30 | .clk(ram_clk), 31 | .data(ram_wrdata), 32 | .data2(ram_wrdata2), 33 | .wren(ram_wren), 34 | .wren2(ram_wren2), 35 | .q(ram_rddata), 36 | .q2(ram_rddata2)); 37 | 38 | reg tx_req = 0; 39 | wire tx_ready; 40 | reg [7:0] tx_data; 41 | wire rx_ready; 42 | wire [7:0] rx_data; 43 | rs232_sim rs232(.clk(clk), 44 | .tx_req(tx_req), 45 | .tx_ready(tx_ready), 46 | .tx_data(tx_data), 47 | .rx_ready(rx_ready), 48 | .rx_data(rx_data)); 49 | 50 | wire [1:0] cpu_next_state; 51 | wire [5:0] cpu_leds; 52 | wire [`RAM_ADDR_BITS-1:0] cpu_ram_addr; 53 | wire [`RAM_ADDR_BITS-1:0] cpu_ram_addr2; 54 | wire [3:0] cpu_ram_byteen; 55 | wire [31:0] cpu_ram_wrdata; 56 | wire cpu_ram_wren; 57 | wire cpu_tx_req; 58 | wire [7:0] cpu_tx_data; 59 | wire [32*36-1:0] cpu_debug_out; 60 | 61 | cpu cpu(.clk(clk), 62 | .rst(rst), 63 | .next_state(cpu_next_state), 64 | .leds(cpu_leds), 65 | .ram_addr(cpu_ram_addr), 66 | .ram_addr2(cpu_ram_addr2), 67 | .ram_byteen(cpu_ram_byteen), 68 | .ram_wrdata(cpu_ram_wrdata), 69 | .ram_wren(cpu_ram_wren), 70 | .ram_rddata(ram_rddata), 71 | .ram_rddata2(ram_rddata2), 72 | 73 | .tx_req(cpu_tx_req), 74 | .tx_ready(tx_ready), 75 | .tx_data(cpu_tx_data), 76 | .rx_ready(rx_ready), 77 | .rx_data(rx_data), 78 | 79 | .debug_out(cpu_debug_out)); 80 | 81 | always #2 clk = !clk; 82 | always #1 ram_clk = !ram_clk; 83 | 84 | integer i; 85 | 86 | always @(posedge clk) begin 87 | tx_req <= cpu_tx_req; 88 | tx_data <= cpu_tx_data; 89 | end 90 | 91 | initial begin 92 | $readmemh(`RAM, sram.mem, 4096 / 4); 93 | 94 | clk <= 1'b0; 95 | ram_clk <= 1'b0; 96 | rst <= 1'b1; 97 | #2; 98 | 99 | rst <= 1'b0; 100 | #2; 101 | 102 | for (i = 0; i < 1000 && cpu.state != 7; i = i + 1) begin 103 | #1000; 104 | end 105 | 106 | `ifndef TRACE 107 | $display("CPU State: %01d", cpu.state); 108 | $display("PC: %x", cpu.pc * 4); 109 | for (i = 0; i < 32; i = i + 1) begin 110 | $display("R%02d: %x", i, cpu.gprs[i]); 111 | end 112 | $display("XER: %x", cpu.sprs[0]); 113 | $display("LR: %x", cpu.sprs[1]); 114 | $display("CTR: %x", cpu.sprs[2]); 115 | $display("RAM: %x %x %x %x", 116 | sram.mem[0], sram.mem[1], sram.mem[2], sram.mem[3]); 117 | `endif 118 | 119 | $finish; 120 | end 121 | 122 | endmodule // cpu_test 123 | -------------------------------------------------------------------------------- /rtl/load.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | `include "const.v" 4 | 5 | module load(input clk, 6 | input rst, 7 | output [1:0] next_state, 8 | output [5:0] leds, 9 | output [`RAM_ADDR_BITS-1:0] ram_addr, 10 | output [3:0] ram_byteen, 11 | output [31:0] ram_wrdata, 12 | output ram_rden, 13 | output ram_wren, 14 | input [31:0] ram_rddata, 15 | input rx_ready, 16 | input [7:0] rx_data); 17 | 18 | localparam LOAD_READ_SIZE = 3'd0; 19 | localparam LOAD_LOAD_PROG = 3'd1; 20 | localparam LOAD_READ_CHECKSUM = 3'd2; 21 | localparam LOAD_VERIFY_PROG = 3'd3; 22 | localparam LOAD_DONE = 3'd4; 23 | 24 | localparam LOAD_OFFSET = 32'h1000; 25 | 26 | localparam PTR_BITS = `RAM_ADDR_BITS + 5 - 3; 27 | 28 | reg [2:0] state = LOAD_READ_SIZE; 29 | reg [PTR_BITS-1:0] ptr = 0; 30 | reg failed = 0; 31 | 32 | assign next_state = (failed ? `PPC_FAIL : 33 | state == LOAD_DONE ? `PPC_EXEC : `PPC_LOAD); 34 | assign leds[2:0] = state; 35 | assign leds[5:3] = ram_checksum[2:0]; 36 | 37 | reg [31:0] wrdata; 38 | //assign ram_addr = ptr[PTR_BITS-1:2] + 4096 / 4; 39 | assign ram_addr = ptr[PTR_BITS-1:2]; 40 | assign ram_byteen = 4'd8 >> ptr[1:0]; 41 | assign ram_wrdata = wrdata; 42 | reg rden = 0; 43 | assign ram_rden = rden; 44 | reg wren = 0; 45 | assign ram_wren = wren; 46 | 47 | reg [23:0] code_size; 48 | reg [7:0] rx_checksum; 49 | reg [7:0] ram_checksum; 50 | 51 | always @(posedge clk or posedge rst) begin 52 | if (rst) begin 53 | state <= LOAD_READ_SIZE; 54 | ptr <= 0; 55 | failed <= 0; 56 | rden <= 0; 57 | wren <= 0; 58 | rx_checksum <= 0; 59 | ram_checksum <= 0; 60 | end else if (state == LOAD_READ_SIZE) begin 61 | if (rx_ready) begin 62 | if (ptr == 0) begin 63 | code_size[23:16] <= rx_data; 64 | ptr <= ptr + 1; 65 | end else if (ptr == 1) begin 66 | code_size[15:8] <= rx_data; 67 | ptr <= ptr + 1; 68 | end else if (ptr == 2) begin 69 | code_size[7:0] <= rx_data; 70 | ptr <= LOAD_OFFSET; 71 | state <= LOAD_LOAD_PROG; 72 | end 73 | end 74 | end else if (state == LOAD_LOAD_PROG) begin 75 | if (wren) begin 76 | if (ptr + 1 == code_size + LOAD_OFFSET) begin 77 | state <= LOAD_READ_CHECKSUM; 78 | ptr <= 0; 79 | end else begin 80 | ptr <= ptr + 1; 81 | end 82 | wren <= 0; 83 | end 84 | if (rx_ready) begin 85 | wrdata <= 0; 86 | if (ptr[1:0] == 3) 87 | wrdata[7:0] <= rx_data; 88 | else if (ptr[1:0] == 2) 89 | wrdata[15:8] <= rx_data; 90 | else if (ptr[1:0] == 1) 91 | wrdata[23:16] <= rx_data; 92 | else if (ptr[1:0] == 0) 93 | wrdata[31:24] <= rx_data; 94 | rx_checksum <= rx_checksum ^ rx_data; 95 | wren <= 1; 96 | end 97 | end else if (state == LOAD_READ_CHECKSUM) begin 98 | if (rx_ready) begin 99 | if (rx_data != rx_checksum) begin 100 | failed <= 1; 101 | end else begin 102 | ptr <= LOAD_OFFSET; 103 | state <= LOAD_VERIFY_PROG; 104 | end 105 | end 106 | end else if (state == LOAD_VERIFY_PROG) begin 107 | if (rden) begin 108 | if (ptr[1:0] == 3) 109 | ram_checksum <= ram_checksum ^ ram_rddata[7:0]; 110 | else if (ptr[1:0] == 2) 111 | ram_checksum <= ram_checksum ^ ram_rddata[15:8]; 112 | else if (ptr[1:0] == 1) 113 | ram_checksum <= ram_checksum ^ ram_rddata[23:16]; 114 | else if (ptr[1:0] == 0) 115 | ram_checksum <= ram_checksum ^ ram_rddata[31:24]; 116 | 117 | if (ptr == code_size + LOAD_OFFSET) begin 118 | if (ram_checksum != rx_checksum) begin 119 | failed <= 1; 120 | end else begin 121 | state <= LOAD_DONE; 122 | end 123 | ptr <= 0; 124 | end else begin 125 | ptr <= ptr + 1; 126 | end 127 | rden <= 0; 128 | end else begin 129 | rden <= 1; 130 | end 131 | end 132 | end 133 | 134 | endmodule // load 135 | -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | AS := powerpc-linux-gnu-as 2 | LD := powerpc-linux-gnu-ld 3 | 4 | AS_SRCS := $(wildcard as/*.s) 5 | AS_OBJS := $(AS_SRCS:.s=.o) 6 | AS_EXES := $(AS_OBJS:as/%.o=exe/%) 7 | 8 | C_SRCS := $(wildcard c/*.c) 9 | C_ASMS := $(C_SRCS:.c=.s) 10 | C_OBJS := $(C_ASMS:.s=.o) 11 | C_EXES := $(C_OBJS:c/%.o=exe/%) 12 | 13 | ML_SRCS := $(wildcard ml/*.ml) 14 | ML_ASMS := $(ML_SRCS:.ml=.s) 15 | ML_OBJS := $(ML_ASMS:.s=.o) 16 | ML_EXES := $(ML_OBJS:ml/%.o=exe/%) 17 | # TODO: float 18 | ML_EXES := $(filter-out exe/float exe/inprod-loop exe/matmul exe/inprod exe/inprod-rec exe/matmul-flat exe/non-tail-if, $(ML_EXES)) 19 | 20 | RTL_SRCS := $(wildcard rtl/*.v) 21 | RTL_SRCS := $(filter-out rtl/ram.v rtl/pll.v rtl/pll_ram.v, $(RTL_SRCS)) 22 | 23 | TB_SRCS := $(filter-out tb/cpu_test.v, $(wildcard tb/*_test.v)) 24 | TB_SIM_SRCS := $(wildcard tb/*_sim.v) 25 | TB_EXES := $(TB_SRCS:.v=) 26 | 27 | EXES := $(AS_EXES) $(C_EXES) $(ML_EXES) 28 | BINS := $(EXES:=.bin) 29 | EXE_STDOUTS := $(EXES:=.stdout) 30 | EXE_TRACES := $(EXES:=.trace) 31 | STDINS := $(wildcard $(EXES:exe/%=tb/%.stdin)) 32 | 33 | TB_CPU_SRCS := tb/cpu_test.v $(TB_SIM_SRCS) 34 | TB_CPU_RAMS := $(BINS:exe/%.bin=tb/cpu_test.%.ram) 35 | TB_CPU_EXES := $(TB_CPU_RAMS:.ram=) 36 | TB_CPU_TRACE_EXES := $(TB_CPU_RAMS:tb/cpu_test.%.ram=tb/cpu_trace.%) 37 | TB_CPU_TRACES := $(TB_CPU_TRACE_EXES:=.trace) 38 | TB_CPU_STDOUTS := $(TB_CPU_EXES:=.stdout) 39 | TB_CPU_OKS := $(TB_CPU_EXES:=.ok) 40 | TB_CPU_OKS := $(filter-out $(AS_EXES:exe/%=tb/cpu_test.%.ok), $(TB_CPU_OKS)) 41 | TB_CPU_TRACE_OKS := $(TB_CPU_TRACES:.trace=.ok) 42 | TB_CPU_TRACE_OKS := $(filter-out $(AS_EXES:exe/%=tb/cpu_trace.%.ok), $(TB_CPU_TRACE_OKS)) 43 | TB_CPU_STDINS := $(STDINS:tb/%.stdin=tb/cpu_test.%.stdin.hex) 44 | 45 | TB_ALL_EXES := $(TB_EXES) $(TB_CPU_EXES) 46 | TB_ALL_OUTS := $(TB_ALL_EXES:=.out) 47 | TB_ALL_RESULTS := $(TB_ALL_OUTS:.out=.res) 48 | 49 | ALL := $(ML_EXES) $(C_EXES) $(AS_EXES) 50 | ALL += libc.s libc.o 51 | ALL += $(TB_ALL_RESULTS) 52 | ALL += $(TB_RAMS) 53 | ALL += $(TB_CPU_OKS) 54 | ALL += $(TB_CPU_TRACE_OKS) 55 | 56 | IVERILOG := iverilog -g2005 -Wall -Wno-timescale -Irtl 57 | 58 | all: $(ALL) 59 | 60 | %.s: %.ml min-caml 61 | ./min-caml $(basename $<) 62 | 63 | %.s: %.c 64 | clang -MMD -O2 -Wno-builtin-requires-header -target powerpc -S -o $@ $< 65 | 66 | %.s: %.S 67 | cpp $< > $@ 68 | 69 | %.o: %.s 70 | $(AS) -mregnames -o $@ $< 71 | 72 | exe: 73 | mkdir -p $@ 74 | 75 | $(AS_EXES): exe/%: as/%.o ppc.lds | exe 76 | $(LD) -o $@ $< -Tppc.lds 77 | 78 | $(C_EXES): exe/%: c/%.o libc.o ppc.lds | exe 79 | $(LD) -o $@ $< libc.o -Tppc.lds 80 | 81 | $(ML_EXES): exe/%: ml/%.o libmincaml.o mincamlstub.o libc.o ppc.lds | exe 82 | $(LD) -o $@ $< libmincaml.o mincamlstub.o libc.o -Tppc.lds 83 | 84 | $(BINS): %.bin: % 85 | objcopy -I elf32-big -O binary $< $@ 86 | 87 | $(TB_EXES): %: %.v $(RTL_SRCS) $(TB_SIM_SRCS) 88 | $(IVERILOG) $(RTL_SRCS) $(TB_SIM_SRCS) $< -o $@ 89 | 90 | define stdin-impl 91 | $(if $1,$2$1$3) 92 | endef 93 | 94 | define stdin 95 | $(call stdin-impl,$(wildcard $1),$2,$3) 96 | endef 97 | 98 | define run-iverilog 99 | $(IVERILOG) -DTEST -DRAM=\"$<\" -DSTDIN=\"tb/cpu_test.$*.stdin.hex\" $1 $(TB_CPU_SRCS) $(RTL_SRCS) -o $@ 100 | endef 101 | 102 | $(TB_CPU_STDINS): tb/cpu_test.%.stdin.hex: tb/%.stdin ./bin2hex.rb 103 | ./bin2hex.rb $< > $@ 104 | 105 | %.stdin.hex: 106 | ./bin2hex.rb /dev/null > $@ 107 | 108 | $(TB_CPU_EXES): tb/cpu_test.%: tb/cpu_test.%.ram tb/cpu_test.%.stdin.hex $(TB_CPU_SRCS) $(RTL_SRCS) $(TB_RAMS) 109 | $(call run-iverilog) 110 | 111 | $(TB_CPU_TRACE_EXES): tb/cpu_trace.%: tb/cpu_test.%.ram tb/cpu_test.%.stdin.hex $(TB_CPU_SRCS) $(RTL_SRCS) $(TB_RAMS) 112 | $(call run-iverilog, -DTRACE=1) 113 | 114 | define run-verilog-sim 115 | $< | grep -v ': \$$readmemh' 116 | endef 117 | 118 | $(TB_ALL_OUTS): %.out: % 119 | $(run-verilog-sim) > $@.tmp && mv $@.tmp $@ 120 | 121 | $(TB_CPU_TRACES): %.trace: % trace_filter.rb 122 | $(run-verilog-sim) | ./trace_filter.rb > $@.tmp && mv $@.tmp $@ 123 | 124 | define run-diff 125 | @if diff -uN $1 $2 > $@.tmp; then \ 126 | echo PASS: "$*($3)"; \ 127 | mv $@.tmp $@; \ 128 | else \ 129 | echo FAIL: "$*($3)"; \ 130 | cat $@.tmp; \ 131 | fi 132 | endef 133 | 134 | $(TB_ALL_RESULTS): %.res: %.out 135 | # $(call run-diff,$*.good,$<,test) 136 | 137 | $(TB_CPU_RAMS): tb/cpu_test.%.ram: exe/%.bin ./bin2hex.rb 138 | ./bin2hex.rb $< > $@ 139 | 140 | $(TB_CPU_STDOUTS): %.stdout: %.out filter_stdout.rb 141 | ./filter_stdout.rb $< > $@.tmp && mv $@.tmp $@ 142 | 143 | $(TB_CPU_OKS): tb/cpu_test.%.ok: exe/%.stdout tb/cpu_test.%.stdout 144 | $(call run-diff,exe/$*.stdout,tb/cpu_test.$*.stdout,stdout) 145 | 146 | $(TB_CPU_TRACE_OKS): tb/cpu_trace.%.ok: exe/%.trace tb/cpu_trace.%.trace 147 | $(call run-diff,exe/$*.trace,tb/cpu_trace.$*.trace,trace) 148 | 149 | $(EXE_STDOUTS): exe/%.stdout: exe/% $(STDINS) psim 150 | ./psim -e linux $< $(call stdin,tb/$*.stdin,<) > $@ || true 151 | 152 | $(EXE_TRACES): exe/%.trace: exe/% $(STDINS) psim trace_filter.rb 153 | ./psim -e linux -t pc -t regs $< $(call stdin,tb/$*.stdin,<) | ./trace_filter.rb > $@ || true 154 | 155 | -include c/*.d 156 | 157 | .SUFFIXES: 158 | -------------------------------------------------------------------------------- /tb/cpu_test.fizzbuzz.good: -------------------------------------------------------------------------------- 1 | OUT: 1 2 | OUT: 3 | 4 | OUT: 2 5 | OUT: 6 | 7 | OUT: F 8 | OUT: i 9 | OUT: z 10 | OUT: z 11 | OUT: 12 | 13 | OUT: 4 14 | OUT: 15 | 16 | OUT: B 17 | OUT: u 18 | OUT: z 19 | OUT: z 20 | OUT: 21 | 22 | OUT: F 23 | OUT: i 24 | OUT: z 25 | OUT: z 26 | OUT: 27 | 28 | OUT: 7 29 | OUT: 30 | 31 | OUT: 8 32 | OUT: 33 | 34 | OUT: F 35 | OUT: i 36 | OUT: z 37 | OUT: z 38 | OUT: 39 | 40 | OUT: B 41 | OUT: u 42 | OUT: z 43 | OUT: z 44 | OUT: 45 | 46 | OUT: 1 47 | OUT: 1 48 | OUT: 49 | 50 | OUT: F 51 | OUT: i 52 | OUT: z 53 | OUT: z 54 | OUT: 55 | 56 | OUT: 1 57 | OUT: 3 58 | OUT: 59 | 60 | OUT: 1 61 | OUT: 4 62 | OUT: 63 | 64 | OUT: F 65 | OUT: i 66 | OUT: z 67 | OUT: z 68 | OUT: B 69 | OUT: u 70 | OUT: z 71 | OUT: z 72 | OUT: 73 | 74 | OUT: 1 75 | OUT: 6 76 | OUT: 77 | 78 | OUT: 1 79 | OUT: 7 80 | OUT: 81 | 82 | OUT: F 83 | OUT: i 84 | OUT: z 85 | OUT: z 86 | OUT: 87 | 88 | OUT: 1 89 | OUT: 9 90 | OUT: 91 | 92 | OUT: B 93 | OUT: u 94 | OUT: z 95 | OUT: z 96 | OUT: 97 | 98 | OUT: F 99 | OUT: i 100 | OUT: z 101 | OUT: z 102 | OUT: 103 | 104 | OUT: 2 105 | OUT: 2 106 | OUT: 107 | 108 | OUT: 2 109 | OUT: 3 110 | OUT: 111 | 112 | OUT: F 113 | OUT: i 114 | OUT: z 115 | OUT: z 116 | OUT: 117 | 118 | OUT: B 119 | OUT: u 120 | OUT: z 121 | OUT: z 122 | OUT: 123 | 124 | OUT: 2 125 | OUT: 6 126 | OUT: 127 | 128 | OUT: F 129 | OUT: i 130 | OUT: z 131 | OUT: z 132 | OUT: 133 | 134 | OUT: 2 135 | OUT: 8 136 | OUT: 137 | 138 | OUT: 2 139 | OUT: 9 140 | OUT: 141 | 142 | OUT: F 143 | OUT: i 144 | OUT: z 145 | OUT: z 146 | OUT: B 147 | OUT: u 148 | OUT: z 149 | OUT: z 150 | OUT: 151 | 152 | OUT: 3 153 | OUT: 1 154 | OUT: 155 | 156 | OUT: 3 157 | OUT: 2 158 | OUT: 159 | 160 | OUT: F 161 | OUT: i 162 | OUT: z 163 | OUT: z 164 | OUT: 165 | 166 | OUT: 3 167 | OUT: 4 168 | OUT: 169 | 170 | OUT: B 171 | OUT: u 172 | OUT: z 173 | OUT: z 174 | OUT: 175 | 176 | OUT: F 177 | OUT: i 178 | OUT: z 179 | OUT: z 180 | OUT: 181 | 182 | OUT: 3 183 | OUT: 7 184 | OUT: 185 | 186 | OUT: 3 187 | OUT: 8 188 | OUT: 189 | 190 | OUT: F 191 | OUT: i 192 | OUT: z 193 | OUT: z 194 | OUT: 195 | 196 | OUT: B 197 | OUT: u 198 | OUT: z 199 | OUT: z 200 | OUT: 201 | 202 | OUT: 4 203 | OUT: 1 204 | OUT: 205 | 206 | OUT: F 207 | OUT: i 208 | OUT: z 209 | OUT: z 210 | OUT: 211 | 212 | OUT: 4 213 | OUT: 3 214 | OUT: 215 | 216 | OUT: 4 217 | OUT: 4 218 | OUT: 219 | 220 | OUT: F 221 | OUT: i 222 | OUT: z 223 | OUT: z 224 | OUT: B 225 | OUT: u 226 | OUT: z 227 | OUT: z 228 | OUT: 229 | 230 | OUT: 4 231 | OUT: 6 232 | OUT: 233 | 234 | OUT: 4 235 | OUT: 7 236 | OUT: 237 | 238 | OUT: F 239 | OUT: i 240 | OUT: z 241 | OUT: z 242 | OUT: 243 | 244 | OUT: 4 245 | OUT: 9 246 | OUT: 247 | 248 | OUT: B 249 | OUT: u 250 | OUT: z 251 | OUT: z 252 | OUT: 253 | 254 | OUT: F 255 | OUT: i 256 | OUT: z 257 | OUT: z 258 | OUT: 259 | 260 | OUT: 5 261 | OUT: 2 262 | OUT: 263 | 264 | OUT: 5 265 | OUT: 3 266 | OUT: 267 | 268 | OUT: F 269 | OUT: i 270 | OUT: z 271 | OUT: z 272 | OUT: 273 | 274 | OUT: B 275 | OUT: u 276 | OUT: z 277 | OUT: z 278 | OUT: 279 | 280 | OUT: 5 281 | OUT: 6 282 | OUT: 283 | 284 | OUT: F 285 | OUT: i 286 | OUT: z 287 | OUT: z 288 | OUT: 289 | 290 | OUT: 5 291 | OUT: 8 292 | OUT: 293 | 294 | OUT: 5 295 | OUT: 9 296 | OUT: 297 | 298 | OUT: F 299 | OUT: i 300 | OUT: z 301 | OUT: z 302 | OUT: B 303 | OUT: u 304 | OUT: z 305 | OUT: z 306 | OUT: 307 | 308 | OUT: 6 309 | OUT: 1 310 | OUT: 311 | 312 | OUT: 6 313 | OUT: 2 314 | OUT: 315 | 316 | OUT: F 317 | OUT: i 318 | OUT: z 319 | OUT: z 320 | OUT: 321 | 322 | OUT: 6 323 | OUT: 4 324 | OUT: 325 | 326 | OUT: B 327 | OUT: u 328 | OUT: z 329 | OUT: z 330 | OUT: 331 | 332 | OUT: F 333 | OUT: i 334 | OUT: z 335 | OUT: z 336 | OUT: 337 | 338 | OUT: 6 339 | OUT: 7 340 | OUT: 341 | 342 | OUT: 6 343 | OUT: 8 344 | OUT: 345 | 346 | OUT: F 347 | OUT: i 348 | OUT: z 349 | OUT: z 350 | OUT: 351 | 352 | OUT: B 353 | OUT: u 354 | OUT: z 355 | OUT: z 356 | OUT: 357 | 358 | OUT: 7 359 | OUT: 1 360 | OUT: 361 | 362 | OUT: F 363 | OUT: i 364 | OUT: z 365 | OUT: z 366 | OUT: 367 | 368 | OUT: 7 369 | OUT: 3 370 | OUT: 371 | 372 | OUT: 7 373 | OUT: 4 374 | OUT: 375 | 376 | OUT: F 377 | OUT: i 378 | OUT: z 379 | OUT: z 380 | OUT: B 381 | OUT: u 382 | OUT: z 383 | OUT: z 384 | OUT: 385 | 386 | OUT: 7 387 | OUT: 6 388 | OUT: 389 | 390 | OUT: 7 391 | OUT: 7 392 | OUT: 393 | 394 | OUT: F 395 | OUT: i 396 | OUT: z 397 | OUT: z 398 | OUT: 399 | 400 | OUT: 7 401 | OUT: 9 402 | OUT: 403 | 404 | OUT: B 405 | OUT: u 406 | OUT: z 407 | OUT: z 408 | OUT: 409 | 410 | OUT: F 411 | OUT: i 412 | OUT: z 413 | OUT: z 414 | OUT: 415 | 416 | OUT: 8 417 | OUT: 2 418 | OUT: 419 | 420 | OUT: 8 421 | OUT: 3 422 | OUT: 423 | 424 | OUT: F 425 | OUT: i 426 | OUT: z 427 | OUT: z 428 | OUT: 429 | 430 | OUT: B 431 | OUT: u 432 | OUT: z 433 | OUT: z 434 | OUT: 435 | 436 | OUT: 8 437 | OUT: 6 438 | OUT: 439 | 440 | OUT: F 441 | OUT: i 442 | OUT: z 443 | OUT: z 444 | OUT: 445 | 446 | OUT: 8 447 | OUT: 8 448 | OUT: 449 | 450 | OUT: 8 451 | OUT: 9 452 | OUT: 453 | 454 | OUT: F 455 | OUT: i 456 | OUT: z 457 | OUT: z 458 | OUT: B 459 | OUT: u 460 | OUT: z 461 | OUT: z 462 | OUT: 463 | 464 | OUT: 9 465 | OUT: 1 466 | OUT: 467 | 468 | OUT: 9 469 | OUT: 2 470 | OUT: 471 | 472 | OUT: F 473 | OUT: i 474 | OUT: z 475 | OUT: z 476 | OUT: 477 | 478 | OUT: 9 479 | OUT: 4 480 | OUT: 481 | 482 | OUT: B 483 | OUT: u 484 | OUT: z 485 | OUT: z 486 | OUT: 487 | 488 | OUT: F 489 | OUT: i 490 | OUT: z 491 | OUT: z 492 | OUT: 493 | 494 | OUT: 9 495 | OUT: 7 496 | OUT: 497 | 498 | OUT: 9 499 | OUT: 8 500 | OUT: 501 | 502 | OUT: F 503 | OUT: i 504 | OUT: z 505 | OUT: z 506 | OUT: 507 | 508 | OUT: B 509 | OUT: u 510 | OUT: z 511 | OUT: z 512 | OUT: 513 | 514 | CPU State: 7 515 | PC: 01028 516 | R00: 00000001 517 | R01: 0000fff0 518 | R02: 00000000 519 | R03: 00000000 520 | R04: 00000000 521 | R05: 00000001 522 | R06: 0000000a 523 | R07: 00000001 524 | R08: 00000001 525 | R09: 00000000 526 | R10: 00000000 527 | R11: 55550000 528 | R12: 66660000 529 | R13: 00000000 530 | R14: 00000000 531 | R15: 00000000 532 | R16: 00000000 533 | R17: 00000000 534 | R18: 00000000 535 | R19: 00000000 536 | R20: 00000000 537 | R21: 00000000 538 | R22: 00000000 539 | R23: 00000000 540 | R24: 00000000 541 | R25: 00000000 542 | R26: 00000000 543 | R27: 00000000 544 | R28: 00000000 545 | R29: 00000000 546 | R30: 00000000 547 | R31: 0000fff0 548 | XER: 00000000 549 | LR: 00001018 550 | CTR: 00000000 551 | RAM: xxxxxxxx 00000000 xxxxxxxx xxxxxxxx 552 | -------------------------------------------------------------------------------- /libc.c: -------------------------------------------------------------------------------- 1 | #include "libc.h" 2 | 3 | #include 4 | #include 5 | 6 | static void print_str(const char* p) { 7 | for (; *p; p++) 8 | putchar(*p); 9 | } 10 | 11 | static char* stringify_int(long v, char* p) { 12 | int is_negative = 0; 13 | *p = '\0'; 14 | if (v < 0) { 15 | if (v == LONG_MIN) { 16 | --p; 17 | // The last digit is 8 for both 32bit and 64bit long. 18 | *p = '8'; 19 | // This heavily depends on C99's division. 20 | v /= 10; 21 | } 22 | v = -v; 23 | is_negative = 1; 24 | } 25 | do { 26 | --p; 27 | *p = v % 10 + '0'; 28 | v /= 10; 29 | } while (v); 30 | if (is_negative) 31 | *--p = '-'; 32 | return p; 33 | } 34 | 35 | static void print_int(long v) { 36 | char buf[32]; 37 | print_str(stringify_int(v, buf + sizeof(buf) - 1)); 38 | } 39 | 40 | static char* stringify_hex(long v, char* p) { 41 | int is_negative = 0; 42 | int c; 43 | *p = '\0'; 44 | if (v < 0) { 45 | if (v == LONG_MIN) { 46 | --p; 47 | *p = '0'; 48 | // This heavily depends on C99's division. 49 | v /= 16; 50 | } 51 | v = -v; 52 | is_negative = 1; 53 | } 54 | do { 55 | --p; 56 | c = v % 16; 57 | *p = c < 10 ? c + '0' : c - 10 + 'A'; 58 | v /= 16; 59 | } while (v); 60 | *--p = 'x'; 61 | *--p = '0'; 62 | if (is_negative) 63 | *--p = '-'; 64 | return p; 65 | } 66 | 67 | int write(int fd, const void* buf, int cnt) { 68 | int r = -1; 69 | asm volatile("mr r3, %1\n" 70 | "mr r4, %2\n" 71 | "mr r5, %3\n" 72 | "li r0, 4\n" 73 | "sc\n" 74 | "mr %0, r3\n" 75 | :"=r"(r): "r"(fd), "r"(buf), "r"(cnt) 76 | : "r0", "r3", "r4", "r5"); 77 | return r; 78 | } 79 | 80 | int putchar(int c) { 81 | char b = c; 82 | write(1, &b, 1); 83 | return c; 84 | } 85 | 86 | int puts(const char* s) { 87 | for (; *s; s++) { 88 | putchar(*s); 89 | } 90 | putchar('\n'); 91 | return 1; 92 | } 93 | 94 | int fputc(int c, void* fp) { 95 | puts("fputc!"); 96 | return 0; 97 | } 98 | 99 | int printf(const char* fmt, ...) { 100 | static const char kOverflowMsg[] = " *** OVERFLOW! ***\n"; 101 | char buf[300] = {0}; 102 | const size_t kMaxFormattedStringSize = sizeof(buf) - sizeof(kOverflowMsg); 103 | char* outp = buf; 104 | const char* inp; 105 | va_list ap; 106 | int is_overflow = 0; 107 | 108 | va_start(ap, fmt); 109 | for (inp = fmt; *inp && (outp - buf) < kMaxFormattedStringSize; inp++) { 110 | if (*inp != '%') { 111 | *outp++ = *inp; 112 | if (outp - buf >= kMaxFormattedStringSize) { 113 | is_overflow = 1; 114 | break; 115 | } 116 | continue; 117 | } 118 | 119 | char cur_buf[32]; 120 | char* cur_p; 121 | switch (*++inp) { 122 | case 'd': 123 | // This is unsafe if we pass more than 6 integer values to 124 | // this function on x86-64, because it starts using stack. 125 | // You need to cast to long in the call site for such cases. 126 | cur_p = stringify_int(va_arg(ap, long), cur_buf + sizeof(cur_buf) - 1); 127 | break; 128 | case 'x': 129 | cur_p = stringify_hex(va_arg(ap, long), cur_buf + sizeof(cur_buf) - 1); 130 | break; 131 | case 's': 132 | cur_p = va_arg(ap, char*); 133 | break; 134 | default: 135 | print_str("unknown format!\n"); 136 | exit(1); 137 | } 138 | 139 | size_t len = strlen(cur_p); 140 | if (outp + len - buf >= kMaxFormattedStringSize) { 141 | is_overflow = 1; 142 | break; 143 | } 144 | strcat(buf, cur_p); 145 | outp += len; 146 | } 147 | va_end(ap); 148 | 149 | if (strlen(buf) > kMaxFormattedStringSize) { 150 | print_str(buf); 151 | if (is_overflow) 152 | print_str(kOverflowMsg); 153 | // This should not happen. 154 | exit(1); 155 | } 156 | if (is_overflow) 157 | strcat(buf, kOverflowMsg); 158 | print_str(buf); 159 | return 0; 160 | } 161 | 162 | int fprintf(void* fp, const char* fmt, ...) { 163 | puts("fprintf!"); 164 | return 0; 165 | } 166 | 167 | int read(int fd, void* buf, int cnt) { 168 | int r = -1; 169 | asm volatile("mr r3, %1\n" 170 | "mr r4, %2\n" 171 | "mr r5, %3\n" 172 | "li r0, 3\n" 173 | "sc\n" 174 | "mr %0, r3\n" 175 | :"=r"(r): "r"(fd), "r"(buf), "r"(cnt) 176 | : "r0", "r3", "r4", "r5"); 177 | return r; 178 | } 179 | 180 | int getchar(void) { 181 | char c; 182 | if (read(0, &c, 1) <= 0) 183 | return -1; 184 | return c; 185 | } 186 | 187 | int scanf(const char* fmt, ...) { 188 | puts("scanf!"); 189 | return 0; 190 | } 191 | 192 | __attribute__((section(".heap"))) 193 | char heap[0x8000]; 194 | 195 | void* malloc(size_t s) { 196 | static char* p = heap; 197 | char* r = p; 198 | p += s; 199 | return r; 200 | } 201 | 202 | void* calloc(size_t n, size_t s) { 203 | return malloc(n * s); 204 | } 205 | 206 | void free(void* p) { 207 | } 208 | 209 | void exit(int s) { 210 | asm volatile("mr r3, %0\n" 211 | "li r0, 1\n" 212 | "sc\n" 213 | ::"r"(s): "r0", "r3"); 214 | } 215 | 216 | void* memset(void* d, int c, size_t n) { 217 | size_t i; 218 | for (i = 0; i < n; i++) { 219 | ((char*)d)[i] = c; 220 | } 221 | return d; 222 | } 223 | 224 | void* memcpy(void* d, const void* s, size_t n) { 225 | size_t i; 226 | for (i = 0; i < n; i++) { 227 | ((char*)d)[i] = ((char*)s)[i]; 228 | } 229 | return d; 230 | } 231 | 232 | size_t strlen(const char* s) { 233 | size_t r; 234 | for (r = 0; s[r]; r++) {} 235 | return r; 236 | } 237 | 238 | char* strcat(char* d, const char* s) { 239 | char* r = d; 240 | for (; *d; d++) {} 241 | for (; *s; s++, d++) 242 | *d = *s; 243 | return r; 244 | } 245 | 246 | double sqrt(double x) { 247 | puts(__func__); 248 | puts("called!"); 249 | return 0.0; 250 | } 251 | 252 | double sin(double x) { 253 | puts(__func__); 254 | puts("called!"); 255 | return 0.0; 256 | } 257 | 258 | double cos(double x) { 259 | puts(__func__); 260 | puts("called!"); 261 | return 0.0; 262 | } 263 | 264 | double atan(double x) { 265 | puts(__func__); 266 | puts("called!"); 267 | return 0.0; 268 | } 269 | 270 | double floor(double x) { 271 | puts(__func__); 272 | puts("called!"); 273 | return 0.0; 274 | } 275 | 276 | // Abuse .init section, to let the address of _start be 0x1000. 277 | asm(".section .init\n" 278 | ".globl _start\n" 279 | "_start:\n" 280 | "lis r1, 1\n" 281 | "li r3, 0\n" 282 | "li r4, 0\n" 283 | "li r5, 0\n" 284 | "li r6, 0\n" 285 | "bl main\n" 286 | "li r0, 1\n" 287 | "sc\n"); 288 | -------------------------------------------------------------------------------- /rtl/ram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: ram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module ram ( 36 | address_a, 37 | address_b, 38 | byteena_a, 39 | clock, 40 | data_a, 41 | data_b, 42 | wren_a, 43 | wren_b, 44 | q_a, 45 | q_b); 46 | 47 | input [13:0] address_a; 48 | input [13:0] address_b; 49 | input [3:0] byteena_a; 50 | input clock; 51 | input [31:0] data_a; 52 | input [31:0] data_b; 53 | input wren_a; 54 | input wren_b; 55 | output [31:0] q_a; 56 | output [31:0] q_b; 57 | `ifndef ALTERA_RESERVED_QIS 58 | // synopsys translate_off 59 | `endif 60 | tri1 [3:0] byteena_a; 61 | tri1 clock; 62 | tri0 wren_a; 63 | tri0 wren_b; 64 | `ifndef ALTERA_RESERVED_QIS 65 | // synopsys translate_on 66 | `endif 67 | 68 | endmodule 69 | 70 | // ============================================================ 71 | // CNX file retrieval info 72 | // ============================================================ 73 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 74 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 75 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 76 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 77 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1" 78 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 79 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 80 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 81 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 82 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 83 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 84 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 85 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 86 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 87 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 88 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 89 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 90 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 91 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 92 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 93 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 94 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 95 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 96 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 97 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 98 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 99 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 100 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 101 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 102 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 103 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "524288" 104 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 105 | // Retrieval info: PRIVATE: MIFfilename STRING "" 106 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 107 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 108 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 109 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 110 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 111 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 112 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 113 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 114 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 115 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 116 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 117 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 118 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 119 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 120 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 121 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 122 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 123 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 124 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 125 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 126 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 127 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 128 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 129 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 130 | // Retrieval info: PRIVATE: enable NUMERIC "0" 131 | // Retrieval info: PRIVATE: rden NUMERIC "0" 132 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 133 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 134 | // Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" 135 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 136 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 137 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 138 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 139 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 140 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 141 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 142 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" 143 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" 144 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 145 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 146 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 147 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 148 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 149 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 150 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 151 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 152 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 153 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" 154 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" 155 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 156 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 157 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" 158 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 159 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 160 | // Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" 161 | // Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" 162 | // Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]" 163 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 164 | // Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" 165 | // Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" 166 | // Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" 167 | // Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" 168 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 169 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 170 | // Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 171 | // Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 172 | // Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0 173 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 174 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 175 | // Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 176 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 177 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 178 | // Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 179 | // Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 180 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE 181 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE 182 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE 183 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE 184 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE 185 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v TRUE 186 | // Retrieval info: LIB_FILE: altera_mf 187 | -------------------------------------------------------------------------------- /libmincaml.S: -------------------------------------------------------------------------------- 1 | .align 2 2 | LC0: 3 | .ascii "%d\0" 4 | .align 2 5 | LC1: 6 | .ascii "%lf\0" 7 | .align 3 8 | LC2: 9 | .long 1127219200 10 | .long -2147483648 11 | .text 12 | .align 2 13 | .globl min_caml_print_newline 14 | min_caml_print_newline: 15 | mflr r0 16 | stw r30, -8(r1) 17 | stw r31, -4(r1) 18 | stw r0, 8(r1) 19 | stw r3, 12(r1) 20 | stw r4, 16(r1) 21 | stwu r1, -80(r1) 22 | mr r30, r1 23 | li r3, 10 24 | bl putchar 25 | lwz r1, 0(r1) 26 | lwz r0, 8(r1) 27 | lwz r3, 12(r1) 28 | lwz r4, 16(r1) 29 | mtlr r0 30 | lwz r30, -8(r1) 31 | lwz r31, -4(r1) 32 | blr 33 | .section .text 34 | .align 5 35 | .align 2 36 | .globl min_caml_print_int 37 | min_caml_print_int: 38 | mflr r0 39 | stw r30, -8(r1) 40 | stw r31, -4(r1) 41 | stw r0, 8(r1) 42 | stw r3, 12(r1) 43 | stw r4, 16(r1) 44 | stwu r1, -80(r1) 45 | mr r30, r1 46 | bcl 20, 31, L2pb 47 | L2pb: 48 | mflr r31 49 | mr r4, r2 50 | addis r2, r31, LC0 - L2pb@ha 51 | la r3, LC0 - L2pb@l(r2) 52 | bl printf 53 | lwz r1, 0(r1) 54 | lwz r0, 8(r1) 55 | lwz r3, 12(r1) 56 | lwz r4, 16(r1) 57 | mtlr r0 58 | lwz r30, -8(r1) 59 | lwz r31, -4(r1) 60 | blr 61 | .align 5 62 | .align 2 63 | .globl min_caml_print_byte 64 | min_caml_print_byte: 65 | mflr r0 66 | stw r30, -8(r1) 67 | stw r31, -4(r1) 68 | stw r0, 8(r1) 69 | stw r3, 12(r1) 70 | stw r4, 16(r1) 71 | stwu r1, -80(r1) 72 | mr r30, r1 73 | stw r3, 104(r30) 74 | mr r3, r2 75 | bl putchar 76 | lwz r1, 0(r1) 77 | lwz r0, 8(r1) 78 | lwz r3, 12(r1) 79 | lwz r4, 16(r1) 80 | mtlr r0 81 | lwz r30, -8(r1) 82 | lwz r31, -4(r1) 83 | blr 84 | # prerr_int 85 | .text 86 | .align 2 87 | .globl min_caml_prerr_int 88 | min_caml_prerr_int: 89 | mflr r0 90 | stw r30, -8(r1) 91 | stw r31, -4(r1) 92 | stw r0, 8(r1) 93 | stw r3, 12(r1) 94 | stw r4, 16(r1) 95 | stwu r1, -80(r1) 96 | mr r30, r1 97 | bcl 20, 31, L3pb 98 | L3pb: 99 | mflr r31 100 | mr r6, r2 101 | mr r2, r5 102 | mr r5, r6 103 | addis r2, r31, L - L3pb@ha 104 | lwz r2, L - L3pb@l(r2) 105 | addi r0, r2, 176 106 | mr r3, r0 107 | addis r2, r31, LC0 - L3pb@ha 108 | la r4, LC0 - L3pb@l(r2) 109 | bl fprintf 110 | lwz r1, 0(r1) 111 | lwz r0, 8(r1) 112 | lwz r3, 12(r1) 113 | lwz r4, 16(r1) 114 | mtlr r0 115 | lwz r30, -8(r1) 116 | lwz r31, -4(r1) 117 | blr 118 | L: 119 | .long 0 120 | .align 5 121 | .align 2 122 | .globl min_caml_prerr_byte 123 | min_caml_prerr_byte: 124 | mflr r0 125 | stmw r30, -8(r1) 126 | stw r0, 8(r1) 127 | stw r3, 12(r1) 128 | stw r4, 16(r1) 129 | stwu r1, -80(r1) 130 | mr r30, r1 131 | bcl 20, 31, L4pb 132 | L4pb: 133 | mflr r31 134 | mr r3, r2 135 | addis r2, r31, L - L4pb@ha 136 | lwz r2, L - L4pb@l(r2) 137 | addi r0, r2, 176 138 | mr r4, r0 139 | bl fputc 140 | lwz r1, 0(r1) 141 | lwz r0, 8(r1) 142 | lwz r3, 12(r1) 143 | lwz r4, 16(r1) 144 | mtlr r0 145 | lmw r30, -8(r1) 146 | blr 147 | .align 5 148 | .align 2 149 | .globl min_caml_prerr_float 150 | min_caml_prerr_float: 151 | mflr r0 152 | stmw r29, -12(r1) 153 | stw r0, 8(r1) 154 | stw r3, 12(r1) 155 | stw r4, 16(r1) 156 | stwu r1, -96(r1) 157 | mr r30, r1 158 | bcl 20, 31, L5pb 159 | L5pb: 160 | mflr r31 161 | addis r2, r31, L - L5pb@ha 162 | lwz r2, L - L5pb@l(r2) 163 | addi r29, r2, 176 164 | stfd f0, 64(r30) 165 | lwz r2, 64(r30) 166 | lwz r3, 68(r30) 167 | mr r10, r3 168 | mr r9, r2 169 | stw r2, 64(r30) 170 | stw r3, 68(r30) 171 | lfd f13, 64(r30) 172 | # fmr f0, f13 173 | mr r3, r29 174 | addis r2, r31, LC1 - L5pb@ha 175 | la r4, LC1 - L5pb@l(r2) 176 | mr r5, r9 177 | mr r6, r10 178 | fmr f1, f0 179 | bl fprintf 180 | lwz r1, 0(r1) 181 | lwz r0, 8(r1) 182 | lwz r3, 12(r1) 183 | lwz r4, 16(r1) 184 | mtlr r0 185 | lmw r29, -12(r1) 186 | blr 187 | # read_int 188 | .text 189 | .align 2 190 | .globl min_caml_read_int 191 | min_caml_read_int: 192 | mflr r0 193 | stw r30, -8(r1) 194 | stw r31, -4(r1) 195 | stw r0, 8(r1) 196 | stw r3, 12(r1) 197 | stw r4, 16(r1) 198 | stwu r1, -96(r1) 199 | mr r30, r1 200 | bcl 20, 31, L6pb 201 | L6pb: 202 | mflr r31 203 | addis r2, r31, LC0 - L6pb@ha 204 | la r3, LC0 - L6pb@l(r2) 205 | addi r4, r30, 56 206 | bl scanf 207 | lwz r2, 56(r30) 208 | lwz r1, 0(r1) 209 | lwz r0, 8(r1) 210 | lwz r3, 12(r1) 211 | lwz r4, 16(r1) 212 | mtlr r0 213 | lwz r30, -8(r1) 214 | lwz r31, -4(r1) 215 | blr 216 | .align 5 217 | .align 2 218 | .globl min_caml_read_float 219 | min_caml_read_float: 220 | mflr r0 221 | stw r30, -8(r1) 222 | stw r31, -4(r1) 223 | stw r0, 8(r1) 224 | stw r3, 12(r1) 225 | stw r4, 16(r1) 226 | stwu r1, -112(r1) 227 | mr r30, r1 228 | bcl 20, 31, L7pb 229 | L7pb: 230 | mflr r31 231 | addis r2, r31, LC1 - L7pb@ha 232 | la r3, LC1 - L7pb@l(r2) 233 | addi r4, r30, 56 234 | bl scanf 235 | lfd f0, 56(r30) 236 | lwz r1, 0(r1) 237 | lwz r0, 8(r1) 238 | lwz r3, 12(r1) 239 | lwz r4, 16(r1) 240 | mtlr r0 241 | lmw r30, -8(r1) 242 | blr 243 | # create_array 244 | .text 245 | .align 2 246 | .globl min_caml_create_array 247 | min_caml_create_array: 248 | mr r6, r2 249 | mr r2, r4 250 | create_array_loop: 251 | cmpwi cr7, r6, 0 252 | bne cr7, create_array_cont 253 | b create_array_exit 254 | create_array_exit: 255 | blr 256 | create_array_cont: 257 | stw r5, 0(r4) 258 | subi r6, r6, 1 259 | addi r4, r4, 4 260 | b create_array_loop 261 | # create_float_array 262 | .globl min_caml_create_float_array 263 | min_caml_create_float_array: 264 | mr r5, r2 265 | mr r2, r4 266 | create_float_array_loop: 267 | cmpwi cr7, r5, 0 268 | bne cr7, create_float_array_cont 269 | blr 270 | create_float_array_cont: 271 | stfd f0, 0(r4) 272 | subi r5, r5, 1 273 | addi r4, r4, 8 274 | b create_float_array_loop 275 | .globl min_caml_abs_float 276 | min_caml_abs_float: 277 | fabs f0, f0 278 | blr 279 | # sqrt 280 | .text 281 | .align 2 282 | .globl min_caml_sqrt 283 | min_caml_sqrt: 284 | mflr r0 285 | stw r30, -8(r1) 286 | stw r31, -4(r1) 287 | stw r0, 8(r1) 288 | stw r3, 12(r1) 289 | stw r4, 16(r1) 290 | stwu r1, -96(r1) 291 | mr r30, r1 292 | bcl 20, 31, L8pb 293 | L8pb: 294 | mflr r31 295 | fmr f1, f0 296 | bl sqrt 297 | fmr f0, f1 298 | lwz r1, 0(r1) 299 | lwz r0, 8(r1) 300 | lwz r3, 12(r1) 301 | lwz r4, 16(r1) 302 | mtlr r0 303 | lwz r30, -8(r1) 304 | lwz r31, -4(r1) 305 | blr 306 | .align 5 307 | .align 2 308 | .globl min_caml_floor 309 | min_caml_floor: 310 | mflr r0 311 | stw r30, -8(r1) 312 | stw r31, -4(r1) 313 | stw r0, 8(r1) 314 | stw r3, 12(r1) 315 | stw r4, 16(r1) 316 | stwu r1, -80(r1) 317 | mr r30, r1 318 | fmr f1, f0 319 | stfd f1, 56(r30) 320 | lfd f1, 56(r30) 321 | bl floor 322 | fmr f0, f1 323 | lwz r1, 0(r1) 324 | lwz r0, 8(r1) 325 | lwz r3, 12(r1) 326 | lwz r4, 16(r1) 327 | mtlr r0 328 | lmw r30, -8(r1) 329 | blr 330 | .align 5 331 | .align 2 332 | .globl min_caml_int_of_float 333 | min_caml_int_of_float: 334 | .globl min_caml_truncate 335 | min_caml_truncate: 336 | stw r30, -8(r1) 337 | stw r31, -4(r1) 338 | stwu r1, -64(r1) 339 | mr r30, r1 340 | stfd f0, 24(r30) 341 | lfd f1, 24(r30) 342 | fctiwz f1, f1 343 | stfd f1, 32(r30) 344 | lwz r31, 36(r30) 345 | mr r2, r31 346 | lwz r1, 0(r1) 347 | lwz r30, -8(r1) 348 | lwz r31, -4(r1) 349 | blr 350 | # float_of_int 351 | .globl min_caml_float_of_int 352 | min_caml_float_of_int: 353 | stw r30, -8(r1) 354 | stw r31, -4(r1) 355 | stw r3, 8(r1) 356 | stw r4, 12(r1) 357 | stwu r1, -48(r1) 358 | mr r30, r1 359 | mflr r0 360 | bcl 20, 31, Lapb 361 | Lapb: 362 | mflr r10 363 | mtlr r0 364 | stw r2, 72(r30) 365 | lwz r0, 72(r30) 366 | lis r2, 0x4330 367 | addis r9, r10, LC2 - Lapb@ha 368 | lfd f13, LC2 - Lapb@l(r9) 369 | xoris r0, r0, 0x8000 370 | stw r0, 28(r30) 371 | stw r2, 24(r30) 372 | lfd f0, 24(r30) 373 | fsub f0, f0, f13 374 | lwz r1, 0(r1) 375 | lwz r3, 8(r1) 376 | lwz r4, 12(r1) 377 | lwz r30, -8(r1) 378 | lwz r31, -4(r1) 379 | blr 380 | # cos 381 | .text 382 | .align 2 383 | .globl min_caml_cos 384 | min_caml_cos: 385 | mflr r0 386 | stw r30, -8(r1) 387 | stw r31, -4(r1) 388 | stw r0, 8(r1) 389 | stw r3, 12(r1) 390 | stw r4, 16(r1) 391 | stwu r1, -96(r1) 392 | mr r30, r1 393 | bcl 20, 31, Lbpb 394 | Lbpb: 395 | mflr r31 396 | fmr f1, f0 397 | bl cos 398 | fmr f0, f1 399 | lwz r1, 0(r1) 400 | lwz r0, 8(r1) 401 | lwz r3, 12(r1) 402 | lwz r4, 16(r1) 403 | mtlr r0 404 | lwz r30, -8(r1) 405 | lwz r31, -4(r1) 406 | blr 407 | .align 5 408 | .align 2 409 | .globl min_caml_sin 410 | min_caml_sin: 411 | mflr r0 412 | stw r30, -8(r1) 413 | stw r31, -4(r1) 414 | stw r0, 8(r1) 415 | stw r3, 12(r1) 416 | stw r4, 16(r1) 417 | stwu r1, -96(r1) 418 | mr r30, r1 419 | bcl 20, 31, Lcpb 420 | Lcpb: 421 | mflr r31 422 | fmr f1, f0 423 | bl sin 424 | fmr f0, f1 425 | lwz r1, 0(r1) 426 | lwz r0, 8(r1) 427 | lwz r3, 12(r1) 428 | lwz r4, 16(r1) 429 | mtlr r0 430 | lwz r30, -8(r1) 431 | lwz r31, -4(r1) 432 | blr 433 | .align 5 434 | .align 2 435 | .globl min_caml_atan 436 | min_caml_atan: 437 | mflr r0 438 | stw r30, -8(r1) 439 | stw r31, -4(r1) 440 | stw r0, 8(r1) 441 | stw r3, 12(r1) 442 | stw r4, 16(r1) 443 | stwu r1, -96(r1) 444 | mr r30, r1 445 | bcl 20, 31, Ldpb 446 | Ldpb: 447 | mflr r31 448 | fmr f1, f0 449 | bl atan 450 | fmr f0, f1 451 | lwz r1, 0(r1) 452 | lwz r0, 8(r1) 453 | lwz r3, 12(r1) 454 | lwz r4, 16(r1) 455 | mtlr r0 456 | lwz r30, -8(r1) 457 | lwz r31, -4(r1) 458 | blr 459 | .align 5 460 | .align 8 461 | float_0: 462 | .long 0x0 463 | .long 0x0 464 | float_1: 465 | .long 0x3ff00000 466 | .long 0x0 467 | 468 | 469 | -------------------------------------------------------------------------------- /ppc.lds: -------------------------------------------------------------------------------- 1 | /* Script for -z combreloc: combine and sort reloc sections */ 2 | /* Copyright (C) 2014 Free Software Foundation, Inc. 3 | Copying and distribution of this script, with or without modification, 4 | are permitted in any medium without royalty provided the copyright 5 | notice and this notice are preserved. */ 6 | OUTPUT_FORMAT("elf32-powerpc", "elf32-powerpc", 7 | "elf32-powerpc") 8 | OUTPUT_ARCH(powerpc:common) 9 | ENTRY(_start) 10 | SEARCH_DIR("=/usr/powerpc-linux-gnu/lib32"); SEARCH_DIR("=/usr/local/lib32"); SEARCH_DIR("=/lib32"); SEARCH_DIR("=/usr/lib32"); SEARCH_DIR("=/usr/powerpc-linux-gnu/lib"); SEARCH_DIR("=/usr/local/lib/powerpc-linux-gnu"); SEARCH_DIR("=/usr/local/lib"); SEARCH_DIR("=/lib/powerpc-linux-gnu"); SEARCH_DIR("=/lib"); SEARCH_DIR("=/usr/lib/powerpc-linux-gnu"); SEARCH_DIR("=/usr/lib"); SEARCH_DIR("/usr/powerpc-linux-gnu/lib"); SEARCH_DIR("/usr/powerpc-linux-gnu/lib32"); 11 | SECTIONS 12 | { 13 | . = 0x1000; 14 | /* Read-only sections, merged into text segment: */ 15 | /*PROVIDE (__executable_start = SEGMENT_START("text-segment", 0x1000)); . = SEGMENT_START("text-segment", 0x1000) + SIZEOF_HEADERS;*/ 16 | .interp : { *(.interp) } 17 | .note.gnu.build-id : { *(.note.gnu.build-id) } 18 | .hash : { *(.hash) } 19 | .gnu.hash : { *(.gnu.hash) } 20 | .dynsym : { *(.dynsym) } 21 | .dynstr : { *(.dynstr) } 22 | .gnu.version : { *(.gnu.version) } 23 | .gnu.version_d : { *(.gnu.version_d) } 24 | .gnu.version_r : { *(.gnu.version_r) } 25 | .rela.dyn : 26 | { 27 | *(.rela.init) 28 | *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*) 29 | *(.rela.fini) 30 | *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*) 31 | *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*) 32 | *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*) 33 | *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*) 34 | *(.rela.ctors) 35 | *(.rela.dtors) 36 | *(.rela.got) 37 | *(.rela.got1) 38 | *(.rela.got2) 39 | *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*) 40 | *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*) 41 | *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*) 42 | *(.rela.sbss2 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We want to adjust up to 90 | the same address within the page on the next page up. */ 91 | . = ALIGN(0x1000); 92 | /* Exception handling */ 93 | .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } 94 | .gcc_except_table : ONLY_IF_RW { *(.gcc_except_table .gcc_except_table.*) } 95 | .exception_ranges : ONLY_IF_RW { *(.exception_ranges .exception_ranges*) } 96 | /* Thread Local Storage sections */ 97 | .tdata : { *(.tdata .tdata.* .gnu.linkonce.td.*) } 98 | .tbss : { *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon) } 99 | .preinit_array : 100 | { 101 | PROVIDE_HIDDEN (__preinit_array_start = .); 102 | KEEP (*(.preinit_array)) 103 | PROVIDE_HIDDEN (__preinit_array_end = .); 104 | } 105 | .init_array : 106 | { 107 | PROVIDE_HIDDEN (__init_array_start = .); 108 | KEEP (*(SORT(.init_array.*))) 109 | KEEP (*(.init_array )) 110 | PROVIDE_HIDDEN (__init_array_end = .); 111 | } 112 | .fini_array : 113 | { 114 | PROVIDE_HIDDEN (__fini_array_start = .); 115 | KEEP (*(SORT(.fini_array.*))) 116 | KEEP (*(.fini_array )) 117 | PROVIDE_HIDDEN (__fini_array_end = .); 118 | } 119 | .ctors : 120 | { 121 | /* gcc uses crtbegin.o to find the start of 122 | the constructors, so we make sure it is 123 | first. Because this is a wildcard, it 124 | doesn't matter if the user does not 125 | actually link against crtbegin.o; the 126 | linker won't look for a file to match a 127 | wildcard. The wildcard also means that it 128 | doesn't matter which directory crtbegin.o 129 | is in. */ 130 | KEEP (*crtbegin.o(.ctors)) 131 | KEEP (*crtbegin?.o(.ctors)) 132 | /* We don't want to include the .ctor section from 133 | the crtend.o file until after the sorted ctors. 134 | The .ctor section from the crtend file contains the 135 | end of ctors marker and it must be last */ 136 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) 137 | KEEP (*(SORT(.ctors.*))) 138 | KEEP (*(.ctors)) 139 | } 140 | .dtors : 141 | { 142 | KEEP (*crtbegin.o(.dtors)) 143 | KEEP (*crtbegin?.o(.dtors)) 144 | KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) 145 | KEEP (*(SORT(.dtors.*))) 146 | KEEP (*(.dtors)) 147 | } 148 | .jcr : { KEEP (*(.jcr)) } 149 | .data.rel.ro : { *(.data.rel.ro.local* .gnu.linkonce.d.rel.ro.local.*) *(.data.rel.ro .data.rel.ro.* .gnu.linkonce.d.rel.ro.*) } 150 | .got1 : { *(.got1) } 151 | .got2 : { *(.got2) } 152 | .dynamic : { *(.dynamic) } 153 | .got : SPECIAL { *(.got) } 154 | /*. = DATA_SEGMENT_RELRO_END (0, .);*/ 155 | .plt : SPECIAL { *(.plt) } 156 | .data : 157 | { 158 | *(.data .data.* .gnu.linkonce.d.*) 159 | SORT(CONSTRUCTORS) 160 | } 161 | .data1 : { *(.data1) } 162 | .got : SPECIAL { *(.got) } 163 | /* We want the small data sections together, so single-instruction offsets 164 | can access them all, and initialized data all before uninitialized, so 165 | we can shorten the on-disk segment size. */ 166 | .sdata : 167 | { 168 | *(.sdata .sdata.* .gnu.linkonce.s.*) 169 | } 170 | _edata = .; PROVIDE (edata = .); 171 | . = .; 172 | __bss_start = .; 173 | .sbss : 174 | { 175 | PROVIDE (__sbss_start = .); PROVIDE (___sbss_start = .); 176 | *(.dynsbss) 177 | *(.sbss .sbss.* .gnu.linkonce.sb.*) 178 | *(.scommon) 179 | PROVIDE (__sbss_end = .); PROVIDE (___sbss_end = .); 180 | } 181 | .plt : SPECIAL { *(.plt) } 182 | .iplt : { *(.iplt) } 183 | .bss : 184 | { 185 | *(.dynbss) 186 | *(.bss .bss.* .gnu.linkonce.b.*) 187 | *(COMMON) 188 | /* Align here to ensure that the .bss section occupies space up to 189 | _end. Align after .bss to ensure correct alignment even if the 190 | .bss section disappears because there are no input sections. 191 | FIXME: Why do we need it? When there is no .bss section, we don't 192 | pad the .data section. */ 193 | . = ALIGN(. != 0 ? 32 / 8 : 1); 194 | } 195 | . = ALIGN(32 / 8); 196 | _end = .; PROVIDE (end = .); 197 | /* Stabs debugging sections. */ 198 | .stab 0 : { *(.stab) } 199 | .stabstr 0 : { *(.stabstr) } 200 | .stab.excl 0 : { *(.stab.excl) } 201 | .stab.exclstr 0 : { *(.stab.exclstr) } 202 | .stab.index 0 : { *(.stab.index) } 203 | .stab.indexstr 0 : { *(.stab.indexstr) } 204 | .comment 0 : { *(.comment) } 205 | /* DWARF debug sections. 206 | Symbols in the DWARF debugging sections are relative to the beginning 207 | of the section so we begin them at 0. */ 208 | /* DWARF 1 */ 209 | .debug 0 : { *(.debug) } 210 | .line 0 : { *(.line) } 211 | /* GNU DWARF 1 extensions */ 212 | .debug_srcinfo 0 : { *(.debug_srcinfo) } 213 | .debug_sfnames 0 : { *(.debug_sfnames) } 214 | /* DWARF 1.1 and DWARF 2 */ 215 | .debug_aranges 0 : { *(.debug_aranges) } 216 | .debug_pubnames 0 : { *(.debug_pubnames) } 217 | /* DWARF 2 */ 218 | .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } 219 | .debug_abbrev 0 : { *(.debug_abbrev) } 220 | .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end ) } 221 | .debug_frame 0 : { *(.debug_frame) } 222 | .debug_str 0 : { *(.debug_str) } 223 | .debug_loc 0 : { *(.debug_loc) } 224 | .debug_macinfo 0 : { *(.debug_macinfo) } 225 | /* SGI/MIPS DWARF 2 extensions */ 226 | .debug_weaknames 0 : { *(.debug_weaknames) } 227 | .debug_funcnames 0 : { *(.debug_funcnames) } 228 | .debug_typenames 0 : { *(.debug_typenames) } 229 | .debug_varnames 0 : { *(.debug_varnames) } 230 | /* DWARF 3 */ 231 | .debug_pubtypes 0 : { *(.debug_pubtypes) } 232 | .debug_ranges 0 : { *(.debug_ranges) } 233 | /* DWARF Extension. */ 234 | .debug_macro 0 : { *(.debug_macro) } 235 | .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } 236 | /DISCARD/ : { *(.fixup) } 237 | /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } 238 | . = 0x6000; 239 | .heap : { *(.heap) } 240 | } 241 | -------------------------------------------------------------------------------- /rtl/pll_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module pll ( 36 | inclk0, 37 | c0); 38 | 39 | input inclk0; 40 | output c0; 41 | 42 | endmodule 43 | 44 | // ============================================================ 45 | // CNX file retrieval info 46 | // ============================================================ 47 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 48 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 49 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 50 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 51 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 52 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 53 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 54 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 55 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 56 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 57 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 58 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 59 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 60 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 61 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 62 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 63 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 64 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 65 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" 66 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 67 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 68 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 69 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 70 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 71 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 72 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 73 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 74 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 75 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 76 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 77 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 78 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 79 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 80 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 81 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 82 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 83 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 84 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 85 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 86 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 87 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 88 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 89 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 90 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" 91 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" 92 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 93 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 94 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 95 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 96 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 97 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 98 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 99 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 100 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 101 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 102 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 103 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 104 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 105 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 106 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 107 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 108 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 109 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 110 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 111 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 112 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 113 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 114 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 115 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 116 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 117 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 118 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 119 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 120 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 121 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 122 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 123 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 124 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 125 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 126 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 127 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 128 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 129 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 130 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 131 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 132 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 133 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 134 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 135 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 136 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 137 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 138 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 139 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 140 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 141 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 142 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 143 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 144 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 145 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 146 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 147 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 148 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 149 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 150 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 151 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 152 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 153 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 154 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 155 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 156 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 157 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 158 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 159 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 160 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 161 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 162 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 163 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 164 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 165 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 166 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 167 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 168 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 169 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 170 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 171 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 172 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 173 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 174 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 175 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 176 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 177 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 178 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 179 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 180 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 181 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 182 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 183 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 184 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 185 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 186 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 187 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 188 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 189 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 190 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 191 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 192 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 193 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 194 | // Retrieval info: LIB_FILE: altera_mf 195 | // Retrieval info: CBX_MODULE_PREFIX: ON 196 | -------------------------------------------------------------------------------- /rtl/pll_ram_bb.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL%VBB% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll_ram.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 21 | //Your use of Altera Corporation's design tools, logic functions 22 | //and other software and tools, and its AMPP partner logic 23 | //functions, and any output files from any of the foregoing 24 | //(including device programming or simulation files), and any 25 | //associated documentation or information are expressly subject 26 | //to the terms and conditions of the Altera Program License 27 | //Subscription Agreement, the Altera Quartus II License Agreement, 28 | //the Altera MegaCore Function License Agreement, or other 29 | //applicable license agreement, including, without limitation, 30 | //that your use is for the sole purpose of programming logic 31 | //devices manufactured by Altera and sold by Altera or its 32 | //authorized distributors. Please refer to the applicable 33 | //agreement for further details. 34 | 35 | module pll_ram ( 36 | inclk0, 37 | c0); 38 | 39 | input inclk0; 40 | output c0; 41 | 42 | endmodule 43 | 44 | // ============================================================ 45 | // CNX file retrieval info 46 | // ============================================================ 47 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 48 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 49 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 50 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 51 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 52 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 53 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 54 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 55 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 56 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 57 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 58 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 59 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 60 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 61 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 62 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 63 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 64 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 65 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" 66 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 67 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 68 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 69 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 70 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 71 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 72 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 73 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 74 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 75 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 76 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 77 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 78 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 79 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 80 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 81 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 82 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 83 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 84 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 85 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 86 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 87 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 88 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" 89 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 90 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" 91 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" 92 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 93 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 94 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 95 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "330.00000000" 96 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 97 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 98 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 99 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 100 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 101 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 102 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 103 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 104 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 105 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 106 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 107 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 108 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ram.mif" 109 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 110 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 111 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 112 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 113 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 114 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 115 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 116 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 117 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 118 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 119 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 120 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 121 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 122 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 123 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 124 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 125 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 126 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 127 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 128 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 129 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 130 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 131 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" 132 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "4583" 133 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 134 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 135 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 136 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 137 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 138 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 139 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 140 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 141 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 142 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 143 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 144 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 145 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 146 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 147 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 148 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 149 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 150 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 151 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 152 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 153 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 154 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 155 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 156 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 157 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 158 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 159 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 160 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 161 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 162 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 163 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 164 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 165 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 166 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 167 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 168 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 169 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 170 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 171 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 172 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 173 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 174 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 175 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 176 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 177 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 178 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 179 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 180 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 181 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 182 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 183 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 184 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 185 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 186 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 187 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.v TRUE 188 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.ppf TRUE 189 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.inc FALSE 190 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.cmp FALSE 191 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.bsf FALSE 192 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram_inst.v FALSE 193 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram_bb.v TRUE 194 | // Retrieval info: LIB_FILE: altera_mf 195 | // Retrieval info: CBX_MODULE_PREFIX: ON 196 | -------------------------------------------------------------------------------- /rtl/ram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %RAM: 2-PORT% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altsyncram 5 | 6 | // ============================================================ 7 | // File Name: ram.v 8 | // Megafunction Name(s): 9 | // altsyncram 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module ram ( 41 | address_a, 42 | address_b, 43 | byteena_a, 44 | clock, 45 | data_a, 46 | data_b, 47 | wren_a, 48 | wren_b, 49 | q_a, 50 | q_b); 51 | 52 | input [13:0] address_a; 53 | input [13:0] address_b; 54 | input [3:0] byteena_a; 55 | input clock; 56 | input [31:0] data_a; 57 | input [31:0] data_b; 58 | input wren_a; 59 | input wren_b; 60 | output [31:0] q_a; 61 | output [31:0] q_b; 62 | `ifndef ALTERA_RESERVED_QIS 63 | // synopsys translate_off 64 | `endif 65 | tri1 [3:0] byteena_a; 66 | tri1 clock; 67 | tri0 wren_a; 68 | tri0 wren_b; 69 | `ifndef ALTERA_RESERVED_QIS 70 | // synopsys translate_on 71 | `endif 72 | 73 | wire [31:0] sub_wire0; 74 | wire [31:0] sub_wire1; 75 | wire [31:0] q_a = sub_wire0[31:0]; 76 | wire [31:0] q_b = sub_wire1[31:0]; 77 | 78 | altsyncram altsyncram_component ( 79 | .address_a (address_a), 80 | .address_b (address_b), 81 | .byteena_a (byteena_a), 82 | .clock0 (clock), 83 | .data_a (data_a), 84 | .data_b (data_b), 85 | .wren_a (wren_a), 86 | .wren_b (wren_b), 87 | .q_a (sub_wire0), 88 | .q_b (sub_wire1), 89 | .aclr0 (1'b0), 90 | .aclr1 (1'b0), 91 | .addressstall_a (1'b0), 92 | .addressstall_b (1'b0), 93 | .byteena_b (1'b1), 94 | .clock1 (1'b1), 95 | .clocken0 (1'b1), 96 | .clocken1 (1'b1), 97 | .clocken2 (1'b1), 98 | .clocken3 (1'b1), 99 | .eccstatus (), 100 | .rden_a (1'b1), 101 | .rden_b (1'b1)); 102 | defparam 103 | altsyncram_component.address_reg_b = "CLOCK0", 104 | altsyncram_component.byte_size = 8, 105 | altsyncram_component.clock_enable_input_a = "BYPASS", 106 | altsyncram_component.clock_enable_input_b = "BYPASS", 107 | altsyncram_component.clock_enable_output_a = "BYPASS", 108 | altsyncram_component.clock_enable_output_b = "BYPASS", 109 | altsyncram_component.indata_reg_b = "CLOCK0", 110 | altsyncram_component.intended_device_family = "Cyclone IV E", 111 | altsyncram_component.lpm_type = "altsyncram", 112 | altsyncram_component.numwords_a = 16384, 113 | altsyncram_component.numwords_b = 16384, 114 | altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", 115 | altsyncram_component.outdata_aclr_a = "NONE", 116 | altsyncram_component.outdata_aclr_b = "NONE", 117 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 118 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 119 | altsyncram_component.power_up_uninitialized = "FALSE", 120 | altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", 121 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 122 | altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", 123 | altsyncram_component.widthad_a = 14, 124 | altsyncram_component.widthad_b = 14, 125 | altsyncram_component.width_a = 32, 126 | altsyncram_component.width_b = 32, 127 | altsyncram_component.width_byteena_a = 4, 128 | altsyncram_component.width_byteena_b = 1, 129 | altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; 130 | 131 | 132 | endmodule 133 | 134 | // ============================================================ 135 | // CNX file retrieval info 136 | // ============================================================ 137 | // Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" 138 | // Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" 139 | // Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" 140 | // Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" 141 | // Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1" 142 | // Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" 143 | // Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" 144 | // Retrieval info: PRIVATE: BlankMemory NUMERIC "1" 145 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" 146 | // Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" 147 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" 148 | // Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" 149 | // Retrieval info: PRIVATE: CLRdata NUMERIC "0" 150 | // Retrieval info: PRIVATE: CLRq NUMERIC "0" 151 | // Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" 152 | // Retrieval info: PRIVATE: CLRrren NUMERIC "0" 153 | // Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" 154 | // Retrieval info: PRIVATE: CLRwren NUMERIC "0" 155 | // Retrieval info: PRIVATE: Clock NUMERIC "0" 156 | // Retrieval info: PRIVATE: Clock_A NUMERIC "0" 157 | // Retrieval info: PRIVATE: Clock_B NUMERIC "0" 158 | // Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" 159 | // Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" 160 | // Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" 161 | // Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" 162 | // Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" 163 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 164 | // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" 165 | // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" 166 | // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" 167 | // Retrieval info: PRIVATE: MEMSIZE NUMERIC "524288" 168 | // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" 169 | // Retrieval info: PRIVATE: MIFfilename STRING "" 170 | // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" 171 | // Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" 172 | // Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" 173 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" 174 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" 175 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3" 176 | // Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3" 177 | // Retrieval info: PRIVATE: REGdata NUMERIC "1" 178 | // Retrieval info: PRIVATE: REGq NUMERIC "0" 179 | // Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" 180 | // Retrieval info: PRIVATE: REGrren NUMERIC "0" 181 | // Retrieval info: PRIVATE: REGwraddress NUMERIC "1" 182 | // Retrieval info: PRIVATE: REGwren NUMERIC "1" 183 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 184 | // Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" 185 | // Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" 186 | // Retrieval info: PRIVATE: VarWidth NUMERIC "0" 187 | // Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "32" 188 | // Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32" 189 | // Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "32" 190 | // Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32" 191 | // Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" 192 | // Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" 193 | // Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" 194 | // Retrieval info: PRIVATE: enable NUMERIC "0" 195 | // Retrieval info: PRIVATE: rden NUMERIC "0" 196 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 197 | // Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0" 198 | // Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" 199 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" 200 | // Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" 201 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" 202 | // Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" 203 | // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK0" 204 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 205 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" 206 | // Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" 207 | // Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" 208 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" 209 | // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" 210 | // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" 211 | // Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" 212 | // Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" 213 | // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" 214 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE" 215 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" 216 | // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" 217 | // Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" 218 | // Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" 219 | // Retrieval info: CONSTANT: WIDTH_A NUMERIC "32" 220 | // Retrieval info: CONSTANT: WIDTH_B NUMERIC "32" 221 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "4" 222 | // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" 223 | // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK0" 224 | // Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" 225 | // Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" 226 | // Retrieval info: USED_PORT: byteena_a 0 0 4 0 INPUT VCC "byteena_a[3..0]" 227 | // Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock" 228 | // Retrieval info: USED_PORT: data_a 0 0 32 0 INPUT NODEFVAL "data_a[31..0]" 229 | // Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]" 230 | // Retrieval info: USED_PORT: q_a 0 0 32 0 OUTPUT NODEFVAL "q_a[31..0]" 231 | // Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]" 232 | // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" 233 | // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" 234 | // Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 235 | // Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 236 | // Retrieval info: CONNECT: @byteena_a 0 0 4 0 byteena_a 0 0 4 0 237 | // Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0 238 | // Retrieval info: CONNECT: @data_a 0 0 32 0 data_a 0 0 32 0 239 | // Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0 240 | // Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 241 | // Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 242 | // Retrieval info: CONNECT: q_a 0 0 32 0 @q_a 0 0 32 0 243 | // Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0 244 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.v TRUE 245 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.inc FALSE 246 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.cmp FALSE 247 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram.bsf FALSE 248 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_inst.v FALSE 249 | // Retrieval info: GEN_FILE: TYPE_NORMAL ram_bb.v TRUE 250 | // Retrieval info: LIB_FILE: altera_mf 251 | -------------------------------------------------------------------------------- /rtl/ppc.v: -------------------------------------------------------------------------------- 1 | `default_nettype none 2 | 3 | `include "const.v" 4 | 5 | module ppc( 6 | CLOCK_50, 7 | LED, 8 | KEY, 9 | DRAM_ADDR, 10 | DRAM_BA, 11 | DRAM_CAS_N, 12 | DRAM_CKE, 13 | DRAM_CLK, 14 | DRAM_CS_N, 15 | DRAM_DQ, 16 | DRAM_DQM, 17 | DRAM_RAS_N, 18 | DRAM_WE_N, 19 | GPIO, 20 | GPIO_IN 21 | ); 22 | input CLOCK_50; 23 | output [7:0] LED; 24 | input [1:0] KEY; 25 | 26 | output [12:0] DRAM_ADDR; 27 | output [1:0] DRAM_BA; 28 | output DRAM_CAS_N; 29 | output DRAM_CKE; 30 | output DRAM_CLK; 31 | output DRAM_CS_N; 32 | inout [15:0] DRAM_DQ; 33 | output [1:0] DRAM_DQM; 34 | output DRAM_RAS_N; 35 | output DRAM_WE_N; 36 | 37 | inout [33:0] GPIO; 38 | input [1:0] GPIO_IN; 39 | 40 | //wire clk = CLOCK_50; 41 | //parameter sys_clk = 50000000; 42 | wire clk; 43 | //parameter sys_clk = 25000000; 44 | //parameter sys_clk = 37500000; 45 | parameter sys_clk = 50000000; 46 | pll pll(.inclk0(CLOCK_50), .c0(clk)); 47 | 48 | wire ram_clk; 49 | pll_ram pll_ram(.inclk0(CLOCK_50), .c0(ram_clk)); 50 | 51 | wire rst; 52 | wire rx, tx; 53 | assign rst = !KEY[0]; 54 | assign rx = GPIO[32]; 55 | assign GPIO[33] = tx; 56 | 57 | reg [1:0] state; 58 | assign LED[1:0] = state; 59 | reg [5:0] leds; 60 | assign LED[7:2] = leds; 61 | 62 | reg tx_req = 0; 63 | wire tx_ready; 64 | reg [7:0] tx_data; 65 | wire rx_ready; 66 | wire [7:0] rx_data; 67 | rs232c_tx #(sys_clk) rs232c_tx(.clk(clk), .rst(rst), .wr(tx_req), 68 | .din(tx_data), .dout(tx), .ready(tx_ready)); 69 | rs232c_rx #(sys_clk) rs232c_rx(.clk(clk), .rst(rst), .din(rx), 70 | .rd(rx_ready), .dout(rx_data)); 71 | 72 | wire [`RAM_ADDR_BITS-1:0] ram_addr; 73 | wire [3:0] ram_byteen; 74 | wire [31:0] ram_wrdata; 75 | wire ram_wren; 76 | wire [31:0] ram_rddata; 77 | wire [`RAM_ADDR_BITS-1:0] ram_addr2; 78 | wire [31:0] ram_wrdata2; 79 | wire ram_wren2; 80 | wire [31:0] ram_rddata2; 81 | assign ram_wrdata2 = 0; 82 | assign ram_wren2 = 0; 83 | ram ram(.address_a(ram_addr), 84 | .address_b(ram_addr2), 85 | .byteena_a(ram_byteen), 86 | .clock(ram_clk), 87 | .data_a(ram_wrdata), 88 | .data_b(ram_wrdata2), 89 | .wren_a(ram_wren), 90 | .wren_b(ram_wren2), 91 | .q_a(ram_rddata), 92 | .q_b(ram_rddata2)); 93 | 94 | wire [1:0] init_next_state; 95 | wire [5:0] init_leds; 96 | wire [`RAM_ADDR_BITS-1:0] init_ram_addr; 97 | wire [3:0] init_ram_byteen; 98 | wire [31:0] init_ram_wrdata; 99 | wire init_ram_wren; 100 | init init(.clk(clk && state == `PPC_INIT), 101 | .rst(rst), 102 | .next_state(init_next_state), 103 | .leds(init_leds), 104 | .ram_addr(init_ram_addr), 105 | .ram_byteen(init_ram_byteen), 106 | .ram_wrdata(init_ram_wrdata), 107 | .ram_wren(init_ram_wren), 108 | .ram_rddata(ram_rddata)); 109 | 110 | wire [1:0] load_next_state; 111 | wire [5:0] load_leds; 112 | wire [`RAM_ADDR_BITS-1:0] load_ram_addr; 113 | wire [3:0] load_ram_byteen; 114 | wire [31:0] load_ram_wrdata; 115 | wire load_ram_wren; 116 | load load(.clk(clk && state == `PPC_LOAD), 117 | .rst(rst), 118 | .next_state(load_next_state), 119 | .leds(load_leds), 120 | .ram_addr(load_ram_addr), 121 | .ram_byteen(load_ram_byteen), 122 | .ram_wrdata(load_ram_wrdata), 123 | .ram_wren(load_ram_wren), 124 | .ram_rddata(ram_rddata), 125 | .rx_ready(rx_ready), 126 | .rx_data(rx_data)); 127 | 128 | wire [1:0] cpu_next_state; 129 | wire [5:0] cpu_leds; 130 | wire [`RAM_ADDR_BITS-1:0] cpu_ram_addr; 131 | wire [`RAM_ADDR_BITS-1:0] cpu_ram_addr2; 132 | wire [3:0] cpu_ram_byteen; 133 | wire [31:0] cpu_ram_wrdata; 134 | wire cpu_ram_wren; 135 | wire cpu_tx_req; 136 | wire [7:0] cpu_tx_data; 137 | wire [32*36-1:0] cpu_debug_out; 138 | cpu cpu(.clk(clk && state == `PPC_EXEC), 139 | .rst(rst), 140 | .next_state(cpu_next_state), 141 | .leds(cpu_leds), 142 | .ram_addr(cpu_ram_addr), 143 | .ram_addr2(cpu_ram_addr2), 144 | .ram_byteen(cpu_ram_byteen), 145 | .ram_wrdata(cpu_ram_wrdata), 146 | .ram_wren(cpu_ram_wren), 147 | .ram_rddata(ram_rddata), 148 | .ram_rddata2(ram_rddata2), 149 | 150 | .tx_req(cpu_tx_req), 151 | .tx_ready(tx_ready), 152 | .tx_data(cpu_tx_data), 153 | .rx_ready(rx_ready), 154 | .rx_data(rx_data), 155 | 156 | .debug_out(cpu_debug_out)); 157 | 158 | reg [`RAM_ADDR_BITS+5-3:0] ptr = 0; 159 | reg [6:0] wait_counter = 0; 160 | reg [11:0] dump_steps = 0; 161 | reg [7:0] dump_data; 162 | reg dump_ready = 0; 163 | reg [`RAM_ADDR_BITS-1:0] dump_ram_addr; 164 | reg [3:0] dump_ram_byteen; 165 | reg [31:0] dump_ram_wrdata; 166 | reg dump_ram_wren; 167 | 168 | assign ram_addr = (state == `PPC_INIT ? init_ram_addr : 169 | state == `PPC_LOAD ? load_ram_addr : 170 | state == `PPC_EXEC ? cpu_ram_addr : 171 | state == `PPC_FAIL ? dump_ram_addr : 0); 172 | assign ram_addr2 = (state == `PPC_EXEC ? cpu_ram_addr2 : 0); 173 | assign ram_byteen = (state == `PPC_INIT ? init_ram_byteen : 174 | state == `PPC_LOAD ? load_ram_byteen : 175 | state == `PPC_EXEC ? cpu_ram_byteen : 176 | state == `PPC_FAIL ? dump_ram_byteen : 0); 177 | assign ram_wrdata = (state == `PPC_INIT ? init_ram_wrdata : 178 | state == `PPC_LOAD ? load_ram_wrdata : 179 | state == `PPC_EXEC ? cpu_ram_wrdata : 180 | state == `PPC_FAIL ? dump_ram_wrdata : 0); 181 | assign ram_wren = (state == `PPC_INIT ? init_ram_wren : 182 | state == `PPC_LOAD ? load_ram_wren : 183 | state == `PPC_EXEC ? cpu_ram_wren : 184 | state == `PPC_FAIL ? dump_ram_wren : 0); 185 | 186 | always @(posedge clk) begin 187 | if (rst) begin 188 | state <= `PPC_INIT; 189 | leds <= 0; 190 | tx_req <= 0; 191 | dump_steps <= 0; 192 | end else if (!KEY[1]) begin 193 | state <= `PPC_FAIL; 194 | dump_steps <= 36 * 32 / 8 - 1; 195 | end else if (state == `PPC_INIT) begin 196 | state <= init_next_state; 197 | leds <= init_leds; 198 | tx_req <= 0; 199 | dump_steps <= 0; 200 | end else if (state == `PPC_LOAD) begin 201 | state <= load_next_state; 202 | leds <= load_leds; 203 | end else if (state == `PPC_EXEC) begin 204 | dump_steps <= 36 * 32 / 8 - 1; 205 | state <= cpu_next_state; 206 | leds <= cpu_leds; 207 | tx_req <= cpu_tx_req; 208 | tx_data <= cpu_tx_data; 209 | end else if (state == `PPC_FAIL) begin 210 | if (wait_counter) begin 211 | wait_counter <= wait_counter - 1; 212 | end else if (dump_steps <= 36 * 32 / 8) begin 213 | if (tx_ready) begin 214 | tx_req <= 1; 215 | //tx_data <= cpu_debug_out[dump_steps] + 48; 216 | tx_data <= { cpu_debug_out[dump_steps*8+7], 217 | cpu_debug_out[dump_steps*8+6], 218 | cpu_debug_out[dump_steps*8+5], 219 | cpu_debug_out[dump_steps*8+4], 220 | cpu_debug_out[dump_steps*8+3], 221 | cpu_debug_out[dump_steps*8+2], 222 | cpu_debug_out[dump_steps*8+1], 223 | cpu_debug_out[dump_steps*8+0] 224 | }; 225 | ptr <= 0; 226 | end else if (!tx_ready && ptr == 0) begin 227 | tx_req <= 0; 228 | ptr <= 1; 229 | wait_counter <= 20; 230 | dump_steps <= dump_steps - 1; 231 | dump_ram_addr <= ptr[`RAM_ADDR_BITS+5-3:2]; 232 | //dump_ram_byteen <= 4'd8 >> ptr[1:0]; 233 | dump_ram_byteen <= 4'd15; 234 | //dump_ready <= 0; 235 | end 236 | end else if (ptr == 4096*5) begin // if (dump_steps < 36 * 32 / 8) 237 | /* 238 | end if (wait_counter) begin 239 | wait_counter <= wait_counter - 1; 240 | */ 241 | /* 242 | end else if (!dump_ready) begin 243 | dump_ready <= 1; 244 | if (ptr[1:0] == 3) 245 | dump_data <= ram_rddata[31:24]; 246 | else if (ptr[1:0] == 2) 247 | dump_data <= ram_rddata[23:16]; 248 | else if (ptr[1:0] == 1) 249 | dump_data <= ram_rddata[15:8]; 250 | else if (ptr[1:0] == 0) 251 | dump_data <= ram_rddata[7:0]; 252 | */ 253 | //end else if (dump_ready && tx_ready) begin 254 | end else if (tx_ready && !tx_req) begin 255 | tx_req <= 1; 256 | //tx_data <= dump_data; 257 | if (ptr[1:0] == 0) 258 | tx_data <= ram_rddata[7:0]; 259 | else if (ptr[1:0] == 3) 260 | tx_data <= ram_rddata[15:8]; 261 | else if (ptr[1:0] == 2) 262 | tx_data <= ram_rddata[23:16]; 263 | else if (ptr[1:0] == 1) 264 | tx_data <= ram_rddata[31:24]; 265 | /* 266 | if (ptr[1:0] == 3) 267 | tx_data <= ram_rddata[31:24]; 268 | else if (ptr[1:0] == 2) 269 | tx_data <= ram_rddata[23:16]; 270 | else if (ptr[1:0] == 1) 271 | tx_data <= ram_rddata[15:8]; 272 | else if (ptr[1:0] == 0) 273 | tx_data <= ram_rddata[7:0]; 274 | if (ptr == 0) 275 | tx_data <= 8'h61; 276 | */ 277 | /* 278 | if (ptr == 1) 279 | tx_data <= 8'h62; 280 | if (ptr == 2) 281 | tx_data <= 8'h63; 282 | if (ptr == 3) 283 | tx_data <= 8'h64; 284 | */ 285 | 286 | ptr <= ptr + 1; 287 | wait_counter <= 20; 288 | dump_ram_addr <= ptr[`RAM_ADDR_BITS+5-3:2]; 289 | //dump_ram_byteen <= 4'd8 >> ptr[1:0]; 290 | dump_ready <= 1; 291 | end 292 | if (!tx_ready) begin 293 | tx_req <= 0; 294 | end 295 | end // if (state == `PPC_FAIL) 296 | end 297 | 298 | endmodule 299 | -------------------------------------------------------------------------------- /c/lisp.c: -------------------------------------------------------------------------------- 1 | #include "../libc.h" 2 | 3 | __attribute__((noinline)) static void print_int(int v) { 4 | if (v < 0) { 5 | putchar('-'); 6 | v = -v; 7 | } 8 | int buf[16]; 9 | int n = 0; 10 | do { 11 | buf[n] = v % 10; 12 | v /= 10; 13 | n++; 14 | } while (v); 15 | 16 | while (n--) { 17 | putchar(buf[n] + '0'); 18 | } 19 | } 20 | 21 | static void print_str(int* p) { 22 | while (*p) { 23 | putchar(*p); 24 | p++; 25 | } 26 | } 27 | 28 | int g_buf = -1; 29 | 30 | int getChar(void) { 31 | int r; 32 | if (g_buf >= 0) { 33 | r = g_buf; 34 | g_buf = -1; 35 | } else { 36 | r = getchar(); 37 | if (r == -1 || r == 0) 38 | exit(0); 39 | } 40 | return r; 41 | } 42 | 43 | int peekChar(void) { 44 | if (g_buf >= 0) 45 | return g_buf; 46 | int c = getchar(); 47 | g_buf = c; 48 | return c; 49 | } 50 | 51 | void ungetChar(int c) { 52 | g_buf = c; 53 | } 54 | 55 | const int g_close_char = ')'; 56 | 57 | #define ALLOC(s) calloc(s / 4, 4) 58 | 59 | #define ERROR(s) (puts(s), printExpr(a), putchar('\n'), exit(1)) 60 | 61 | typedef enum { 62 | NUM, 63 | STR, 64 | LIST, 65 | LAMBDA 66 | } Type; 67 | 68 | typedef struct List { 69 | struct Atom* head; 70 | struct List* tail; 71 | } List; 72 | 73 | typedef struct Atom { 74 | Type type; 75 | union { 76 | int num; 77 | int* str; 78 | List* list; 79 | }; 80 | } Atom; 81 | 82 | typedef struct Table { 83 | int* key; 84 | Atom* value; 85 | struct Table* next; 86 | } Table; 87 | 88 | void printExpr(Atom* expr) { 89 | if (!expr) { 90 | putchar('n'); 91 | putchar('i'); 92 | putchar('l'); 93 | return; 94 | } 95 | 96 | if (expr->type == NUM) { 97 | print_int(expr->num); 98 | return; 99 | } 100 | 101 | if (expr->type == STR) { 102 | print_str(expr->str); 103 | return; 104 | } 105 | 106 | putchar('('); 107 | if (expr->type == LAMBDA) { 108 | putchar('l'); 109 | putchar('a'); 110 | putchar('m'); 111 | putchar('b'); 112 | putchar('d'); 113 | putchar('a'); 114 | putchar(' '); 115 | } 116 | 117 | List* l = expr->list; 118 | while (l) { 119 | printExpr(l->head); 120 | l = l->tail; 121 | if (l) 122 | putchar(' '); 123 | } 124 | putchar(')'); 125 | } 126 | 127 | List* cons(Atom* h, List* t) { 128 | List* s = (List*)ALLOC(sizeof(List)); 129 | s->head = h; 130 | s->tail = t; 131 | return s; 132 | } 133 | 134 | Atom* createAtom(Type type) { 135 | Atom* a = (Atom*)ALLOC(sizeof(Atom)); 136 | a->type = type; 137 | return a; 138 | } 139 | 140 | Atom* createInt(int n) { 141 | Atom* a = createAtom(NUM); 142 | a->num = n; 143 | return a; 144 | } 145 | 146 | Atom* createStr(int* s) { 147 | Atom* a = createAtom(STR); 148 | a->str = s; 149 | return a; 150 | } 151 | 152 | Atom* createList(List* l) { 153 | if (l == NULL) 154 | return NULL; 155 | Atom* a = createAtom(LIST); 156 | a->list = l; 157 | return a; 158 | } 159 | 160 | Atom* createLambda(List* l) { 161 | Atom* a = createAtom(LAMBDA); 162 | a->list = l; 163 | return a; 164 | } 165 | 166 | int atom(Atom* a) { 167 | return a == NULL || a->type != LIST || a->list == NULL; 168 | } 169 | 170 | int isList(Atom* a) { 171 | return a == NULL || a->type == LIST; 172 | } 173 | 174 | Atom* g_t; 175 | 176 | Table* g_val; 177 | 178 | Atom* parse(void); 179 | 180 | void skipWS(void) { 181 | int c = getChar(); 182 | while (c == ' ' || c == '\n') 183 | c = getChar(); 184 | ungetChar(c); 185 | } 186 | 187 | Atom* parseList(void) { 188 | List* l = NULL; 189 | List* n = NULL; 190 | while (1) { 191 | skipWS(); 192 | if (peekChar() == g_close_char) { 193 | getChar(); 194 | break; 195 | } 196 | Atom* a = parse(); 197 | List* t = cons(a, NULL); 198 | if (n) { 199 | n->tail = t; 200 | } else { 201 | l = n = t; 202 | } 203 | n = t; 204 | } 205 | return createList(l); 206 | } 207 | 208 | Atom* parseStr(int c) { 209 | int buf[99]; 210 | int n = 0; 211 | while (c != ' ' && c != '\n' && c != '(' && c != ')') { 212 | buf[n] = c; 213 | c = getChar(); 214 | n++; 215 | } 216 | ungetChar(c); 217 | 218 | if (n == 3 && buf[0] == 'n' && buf[1] == 'i' && buf[2] == 'l') 219 | return NULL; 220 | 221 | int* str = calloc(n + 1, 4); 222 | int i; 223 | for (i = 0; i < n; i++) { 224 | str[i] = buf[i]; 225 | } 226 | str[i] = '\0'; 227 | return createStr(str); 228 | } 229 | 230 | Atom* parseInt(int c) { 231 | int n = 0; 232 | int m = 0; 233 | if (c == '-') { 234 | m = 1; 235 | } else { 236 | n += c - '0'; 237 | } 238 | 239 | while (1) { 240 | c = getChar(); 241 | if (c >= '0' && c <= '9') { 242 | n *= 10; 243 | n += c - '0'; 244 | } else { 245 | ungetChar(c); 246 | break; 247 | } 248 | } 249 | 250 | if (m) { 251 | if (n == 0) 252 | return parseStr('-'); 253 | n = -n; 254 | } 255 | return createInt(n); 256 | } 257 | 258 | int eqStr(int* l, int* r) { 259 | int i; 260 | for (i = 0; l[i] || r[i]; i++) { 261 | if (l[i] != r[i]) 262 | return 0; 263 | } 264 | return 1; 265 | } 266 | 267 | Table* lookupTable(Table* t, int* k) { 268 | while (t) { 269 | if (eqStr(t->key, k)) 270 | return t; 271 | t = t->next; 272 | } 273 | return NULL; 274 | } 275 | 276 | void addTable(Table** t, int* k, Atom* v) { 277 | Table* nt = lookupTable(*t, k); 278 | if (!nt) { 279 | nt = (Table*)ALLOC(sizeof(Table)); 280 | nt->next = *t; 281 | *t = nt; 282 | } 283 | nt->key = k; 284 | nt->value = v; 285 | } 286 | 287 | int eq(Atom* l, Atom* r); 288 | 289 | int eqList(List* l, List* r) { 290 | while (l && r) { 291 | if (!eq(l->head, r->head)) 292 | return 0; 293 | 294 | l = l->tail; 295 | r = r->tail; 296 | } 297 | 298 | return l == NULL && r == NULL; 299 | } 300 | 301 | int eq(Atom* l, Atom* r) { 302 | if (l == r) 303 | return 1; 304 | 305 | if (l == NULL || r == NULL) 306 | return 0; 307 | 308 | if (l->type != r->type) 309 | return 0; 310 | 311 | if (l->type == NUM) 312 | return l->num == r->num; 313 | 314 | if (l->type == STR) 315 | return eqStr(l->str, r->str); 316 | 317 | return eqList(l->list, r->list); 318 | } 319 | 320 | int getListSize(List* l) { 321 | int n = 0; 322 | while (l) { 323 | l = l->tail; 324 | n++; 325 | } 326 | return n; 327 | } 328 | 329 | Atom* eval(Atom* a, Table* val) { 330 | if (atom(a)) { 331 | if (a && a->type == STR) { 332 | Table* t = lookupTable(val, a->str); 333 | if (t) 334 | return t->value; 335 | t = lookupTable(g_val, a->str); 336 | if (t) 337 | return t->value; 338 | } 339 | return a; 340 | } 341 | 342 | List* s = a->list; 343 | 344 | if (s->head->type == STR) { 345 | int* fn = s->head->str; 346 | if (fn[0] == 'i' && fn[1] == 'f' && fn[2] == '\0') { 347 | if (getListSize(s) != 4) 348 | ERROR("invalid if"); 349 | 350 | Atom* c = eval(s->tail->head, val); 351 | if (c) { 352 | return eval(s->tail->tail->head, val); 353 | } else { 354 | return eval(s->tail->tail->tail->head, val); 355 | } 356 | } else if (fn[0] == 'q' && fn[1] == 'u' && fn[2] == 'o' && 357 | fn[3] == 't' && fn[4] == 'e' && fn[5] == '\0') { 358 | if (getListSize(s) != 2) 359 | ERROR("invalid quote"); 360 | 361 | return s->tail->head; 362 | } else if (fn[0] == 'd' && fn[1] == 'e' && fn[2] == 'f' && 363 | fn[3] == 'i' && fn[4] == 'n' && fn[5] == 'e' && 364 | fn[6] == '\0') { 365 | if (getListSize(s) != 3 || s->tail->head->type != STR) 366 | ERROR("invalid define"); 367 | 368 | Atom* e = eval(s->tail->tail->head, val); 369 | addTable(&g_val, s->tail->head->str, e); 370 | return e; 371 | } else if (fn[0] == 'l' && fn[1] == 'a' && fn[2] == 'm' && 372 | fn[3] == 'b' && fn[4] == 'd' && fn[5] == 'a' && 373 | fn[6] == '\0') { 374 | if (getListSize(s) != 3 || !isList(s->tail->head)) 375 | ERROR("invalid lambda"); 376 | 377 | return createLambda(s->tail); 378 | } else if (fn[0] == 'd' && fn[1] == 'e' && fn[2] == 'f' && 379 | fn[3] == 'u' && fn[4] == 'n' && fn[5] == '\0') { 380 | if (getListSize(s) != 4 || 381 | s->tail->head->type != STR || !isList(s->tail->tail->head)) 382 | ERROR("invalid defun"); 383 | 384 | Atom* e = createLambda(s->tail->tail); 385 | addTable(&g_val, s->tail->head->str, e); 386 | return e; 387 | } 388 | } 389 | 390 | Atom* hd = eval(s->head, val); 391 | 392 | if (hd->type == LAMBDA) { 393 | List* args = hd->list->head ? hd->list->head->list : NULL; 394 | 395 | if (getListSize(s) - 1 != getListSize(args)) 396 | ERROR("invalid lambda application"); 397 | 398 | Table* nval = NULL; 399 | List* params = s->tail; 400 | while (args) { 401 | addTable(&nval, args->head->str, eval(params->head, val)); 402 | args = args->tail; 403 | params = params->tail; 404 | } 405 | 406 | Atom* expr = hd->list->tail->head; 407 | return eval(expr, nval); 408 | } 409 | 410 | if (hd->type == STR) { 411 | int* fn = hd->str; 412 | int op = fn[0]; 413 | if (((op == '+' || op == '-' || op == '*' || op == '/') && 414 | fn[1] == '\0') || 415 | (op == 'm' && fn[1] == 'o' && fn[2] == 'd' && fn[3] == '\0')) { 416 | if (getListSize(s) != 3) 417 | ERROR("invalid arith"); 418 | Atom* l = eval(s->tail->head, val); 419 | Atom* r = eval(s->tail->tail->head, val); 420 | if (l->type != NUM || r->type != NUM) 421 | ERROR("invalid arith"); 422 | int result = 0; 423 | if (op == '+') result = l->num + r->num; 424 | else if (op == '-') result = l->num - r->num; 425 | else if (op == '*') result = l->num * r->num; 426 | else if (op == '/') result = l->num / r->num; 427 | else result = l->num % r->num; 428 | return createInt(result); 429 | } else if (op == 'e' && fn[1] == 'q' && fn[2] == '\0') { 430 | if (getListSize(s) != 3) 431 | ERROR("invalid eq"); 432 | 433 | Atom* l = eval(s->tail->head, val); 434 | Atom* r = eval(s->tail->tail->head, val); 435 | if (eq(l, r)) 436 | return g_t; 437 | else 438 | return NULL; 439 | } else if (op == 'c' && (fn[1] == 'a' || fn[1] == 'd') && 440 | fn[2] == 'r' && fn[3] == '\0') { 441 | Atom* e = eval(s->tail->head, val); 442 | 443 | if (e == NULL) 444 | return NULL; 445 | 446 | if (e->type != LIST || getListSize(s) != 2) 447 | ERROR("invalid car/cdr"); 448 | 449 | if (fn[1] == 'a') 450 | return e->list->head; 451 | else 452 | return createList(e->list->tail); 453 | } else if (op == 'c' && fn[1] == 'o' && fn[2] == 'n' && 454 | fn[3] == 's' && fn[4] == '\0') { 455 | if (getListSize(s) != 3) 456 | ERROR("invalid cons"); 457 | 458 | Atom* l = eval(s->tail->head, val); 459 | Atom* r = eval(s->tail->tail->head, val); 460 | 461 | if (r && r->type != LIST) 462 | ERROR("invalid cons"); 463 | 464 | return createList(cons(l, r ? r->list : NULL)); 465 | } else if (op == 'a' && fn[1] == 't' && fn[2] == 'o' && 466 | fn[3] == 'm' && fn[4] == '\0') { 467 | if (getListSize(s) != 2) 468 | ERROR("invalid atom"); 469 | 470 | Atom* e = eval(s->tail->head, val); 471 | 472 | if (atom(e)) 473 | return g_t; 474 | else 475 | return NULL; 476 | } else if (op == 'n' && fn[1] == 'e' && fn[2] == 'g' && 477 | fn[3] == '?' && fn[4] == '\0') { 478 | if (getListSize(s) != 2) 479 | ERROR("invalid neg?"); 480 | 481 | Atom* e = eval(s->tail->head, val); 482 | 483 | if (e->type == NUM && e->num < 0) 484 | return g_t; 485 | else 486 | return NULL; 487 | } else if (fn[0] == 'p' && fn[1] == 'r' && fn[2] == 'i' && 488 | fn[3] == 'n' && fn[4] == 't' && fn[5] == '\0') { 489 | if (getListSize(s) != 2) 490 | ERROR("invalid print"); 491 | 492 | Atom* e = eval(s->tail->head, val); 493 | printExpr(e); 494 | putchar('\n'); 495 | return e; 496 | } 497 | 498 | print_str(fn); 499 | putchar(':'); 500 | putchar(' '); 501 | ERROR("undefined function"); 502 | } 503 | 504 | ERROR("invalid function application"); 505 | return NULL; 506 | } 507 | 508 | Atom* parse(void) { 509 | skipWS(); 510 | int c = getChar(); 511 | if (c == '(') { 512 | return parseList(); 513 | } else if (c == '-' || (c >= '0' && c <= '9')) { 514 | return parseInt(c); 515 | } else if (c == ';') { 516 | while (c != '\n') { 517 | c = getChar(); 518 | } 519 | return parse(); 520 | } else { 521 | return parseStr(c); 522 | } 523 | } 524 | 525 | int main() { 526 | int buf[2]; 527 | buf[0] = 't'; 528 | buf[1] = '\0'; 529 | g_t = createStr(buf); 530 | 531 | while (1) { 532 | Atom* expr = parse(); 533 | Atom* result = eval(expr, NULL); 534 | printExpr(result); 535 | putchar('\n'); 536 | } 537 | } 538 | -------------------------------------------------------------------------------- /rtl/ppc.qsf: -------------------------------------------------------------------------------- 1 | #============================================================ 2 | # Build by Terasic System Builder 3 | #============================================================ 4 | 5 | set_global_assignment -name FAMILY "Cyclone IV E" 6 | set_global_assignment -name DEVICE EP4CE22F17C6 7 | set_global_assignment -name TOP_LEVEL_ENTITY "ppc" 8 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 12.0 9 | set_global_assignment -name LAST_QUARTUS_VERSION 14.0 10 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:11:57 DECEMBER 25,2014" 11 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA 12 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 256 13 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 14 | 15 | #============================================================ 16 | # CLOCK 17 | #============================================================ 18 | set_location_assignment PIN_R8 -to CLOCK_50 19 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to CLOCK_50 20 | 21 | #============================================================ 22 | # LED 23 | #============================================================ 24 | set_location_assignment PIN_A15 -to LED[0] 25 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0] 26 | set_location_assignment PIN_A13 -to LED[1] 27 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1] 28 | set_location_assignment PIN_B13 -to LED[2] 29 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2] 30 | set_location_assignment PIN_A11 -to LED[3] 31 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3] 32 | set_location_assignment PIN_D1 -to LED[4] 33 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4] 34 | set_location_assignment PIN_F3 -to LED[5] 35 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5] 36 | set_location_assignment PIN_B1 -to LED[6] 37 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6] 38 | set_location_assignment PIN_L3 -to LED[7] 39 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7] 40 | 41 | #============================================================ 42 | # KEY 43 | #============================================================ 44 | set_location_assignment PIN_J15 -to KEY[0] 45 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0] 46 | set_location_assignment PIN_E1 -to KEY[1] 47 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1] 48 | 49 | #============================================================ 50 | # SDRAM 51 | #============================================================ 52 | set_location_assignment PIN_M7 -to DRAM_BA[0] 53 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[0] 54 | set_location_assignment PIN_M6 -to DRAM_BA[1] 55 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_BA[1] 56 | set_location_assignment PIN_R6 -to DRAM_DQM[0] 57 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[0] 58 | set_location_assignment PIN_T5 -to DRAM_DQM[1] 59 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQM[1] 60 | set_location_assignment PIN_L2 -to DRAM_RAS_N 61 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_RAS_N 62 | set_location_assignment PIN_L1 -to DRAM_CAS_N 63 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CAS_N 64 | set_location_assignment PIN_L7 -to DRAM_CKE 65 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CKE 66 | set_location_assignment PIN_R4 -to DRAM_CLK 67 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CLK 68 | set_location_assignment PIN_C2 -to DRAM_WE_N 69 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_WE_N 70 | set_location_assignment PIN_P6 -to DRAM_CS_N 71 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_CS_N 72 | set_location_assignment PIN_G2 -to DRAM_DQ[0] 73 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[0] 74 | set_location_assignment PIN_G1 -to DRAM_DQ[1] 75 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[1] 76 | set_location_assignment PIN_L8 -to DRAM_DQ[2] 77 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[2] 78 | set_location_assignment PIN_K5 -to DRAM_DQ[3] 79 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[3] 80 | set_location_assignment PIN_K2 -to DRAM_DQ[4] 81 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[4] 82 | set_location_assignment PIN_J2 -to DRAM_DQ[5] 83 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[5] 84 | set_location_assignment PIN_J1 -to DRAM_DQ[6] 85 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[6] 86 | set_location_assignment PIN_R7 -to DRAM_DQ[7] 87 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[7] 88 | set_location_assignment PIN_T4 -to DRAM_DQ[8] 89 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[8] 90 | set_location_assignment PIN_T2 -to DRAM_DQ[9] 91 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[9] 92 | set_location_assignment PIN_T3 -to DRAM_DQ[10] 93 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[10] 94 | set_location_assignment PIN_R3 -to DRAM_DQ[11] 95 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[11] 96 | set_location_assignment PIN_R5 -to DRAM_DQ[12] 97 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[12] 98 | set_location_assignment PIN_P3 -to DRAM_DQ[13] 99 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[13] 100 | set_location_assignment PIN_N3 -to DRAM_DQ[14] 101 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[14] 102 | set_location_assignment PIN_K1 -to DRAM_DQ[15] 103 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_DQ[15] 104 | set_location_assignment PIN_P2 -to DRAM_ADDR[0] 105 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[0] 106 | set_location_assignment PIN_N5 -to DRAM_ADDR[1] 107 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[1] 108 | set_location_assignment PIN_N6 -to DRAM_ADDR[2] 109 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[2] 110 | set_location_assignment PIN_M8 -to DRAM_ADDR[3] 111 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[3] 112 | set_location_assignment PIN_P8 -to DRAM_ADDR[4] 113 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[4] 114 | set_location_assignment PIN_T7 -to DRAM_ADDR[5] 115 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[5] 116 | set_location_assignment PIN_N8 -to DRAM_ADDR[6] 117 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[6] 118 | set_location_assignment PIN_T6 -to DRAM_ADDR[7] 119 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[7] 120 | set_location_assignment PIN_R1 -to DRAM_ADDR[8] 121 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[8] 122 | set_location_assignment PIN_P1 -to DRAM_ADDR[9] 123 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[9] 124 | set_location_assignment PIN_N2 -to DRAM_ADDR[10] 125 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[10] 126 | set_location_assignment PIN_N1 -to DRAM_ADDR[11] 127 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[11] 128 | set_location_assignment PIN_L4 -to DRAM_ADDR[12] 129 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to DRAM_ADDR[12] 130 | 131 | #============================================================ 132 | # GPIO_0, GPIO_0 connect to GPIO Default 133 | #============================================================ 134 | set_location_assignment PIN_A8 -to GPIO_IN[0] 135 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_IN[0] 136 | set_location_assignment PIN_D3 -to GPIO[0] 137 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[0] 138 | set_location_assignment PIN_B8 -to GPIO_IN[1] 139 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_IN[1] 140 | set_location_assignment PIN_C3 -to GPIO[1] 141 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[1] 142 | set_location_assignment PIN_A2 -to GPIO[2] 143 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[2] 144 | set_location_assignment PIN_A3 -to GPIO[3] 145 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[3] 146 | set_location_assignment PIN_B3 -to GPIO[4] 147 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[4] 148 | set_location_assignment PIN_B4 -to GPIO[5] 149 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[5] 150 | set_location_assignment PIN_A4 -to GPIO[6] 151 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[6] 152 | set_location_assignment PIN_B5 -to GPIO[7] 153 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[7] 154 | set_location_assignment PIN_A5 -to GPIO[8] 155 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[8] 156 | set_location_assignment PIN_D5 -to GPIO[9] 157 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[9] 158 | set_location_assignment PIN_B6 -to GPIO[10] 159 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[10] 160 | set_location_assignment PIN_A6 -to GPIO[11] 161 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[11] 162 | set_location_assignment PIN_B7 -to GPIO[12] 163 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[12] 164 | set_location_assignment PIN_D6 -to GPIO[13] 165 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[13] 166 | set_location_assignment PIN_A7 -to GPIO[14] 167 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[14] 168 | set_location_assignment PIN_C6 -to GPIO[15] 169 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[15] 170 | set_location_assignment PIN_C8 -to GPIO[16] 171 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[16] 172 | set_location_assignment PIN_E6 -to GPIO[17] 173 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[17] 174 | set_location_assignment PIN_E7 -to GPIO[18] 175 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[18] 176 | set_location_assignment PIN_D8 -to GPIO[19] 177 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[19] 178 | set_location_assignment PIN_E8 -to GPIO[20] 179 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[20] 180 | set_location_assignment PIN_F8 -to GPIO[21] 181 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[21] 182 | set_location_assignment PIN_F9 -to GPIO[22] 183 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[22] 184 | set_location_assignment PIN_E9 -to GPIO[23] 185 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[23] 186 | set_location_assignment PIN_C9 -to GPIO[24] 187 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[24] 188 | set_location_assignment PIN_D9 -to GPIO[25] 189 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[25] 190 | set_location_assignment PIN_E11 -to GPIO[26] 191 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[26] 192 | set_location_assignment PIN_E10 -to GPIO[27] 193 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[27] 194 | set_location_assignment PIN_C11 -to GPIO[28] 195 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[28] 196 | set_location_assignment PIN_B11 -to GPIO[29] 197 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[29] 198 | set_location_assignment PIN_A12 -to GPIO[30] 199 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[30] 200 | set_location_assignment PIN_D11 -to GPIO[31] 201 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[31] 202 | set_location_assignment PIN_D12 -to GPIO[32] 203 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[32] 204 | set_location_assignment PIN_B12 -to GPIO[33] 205 | set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO[33] 206 | 207 | #============================================================ 208 | # End of pin assignments by Terasic System Builder 209 | #============================================================ 210 | 211 | 212 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 213 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 214 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 215 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 216 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 217 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 218 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 219 | set_global_assignment -name VERILOG_FILE cpu.v 220 | set_global_assignment -name VERILOG_FILE decode.v 221 | set_global_assignment -name VERILOG_FILE sram.v 222 | set_global_assignment -name VERILOG_FILE rs232c_tx.v 223 | set_global_assignment -name VERILOG_FILE rs232c_rx.v 224 | set_global_assignment -name VERILOG_FILE clk_div.v 225 | set_global_assignment -name VERILOG_FILE const.v 226 | set_global_assignment -name VERILOG_FILE ppc.v 227 | set_global_assignment -name VERILOG_FILE init.v 228 | set_global_assignment -name SDC_FILE ppc.SDC 229 | set_global_assignment -name QIP_FILE ram.qip 230 | set_global_assignment -name QIP_FILE pll.qip 231 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" 232 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation 233 | set_global_assignment -name QIP_FILE pll_ram.qip 234 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /rtl/pll.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pll ( 41 | inclk0, 42 | c0); 43 | 44 | input inclk0; 45 | output c0; 46 | 47 | wire [0:0] sub_wire2 = 1'h0; 48 | wire [4:0] sub_wire3; 49 | wire sub_wire0 = inclk0; 50 | wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; 51 | wire [0:0] sub_wire4 = sub_wire3[0:0]; 52 | wire c0 = sub_wire4; 53 | 54 | altpll altpll_component ( 55 | .inclk (sub_wire1), 56 | .clk (sub_wire3), 57 | .activeclock (), 58 | .areset (1'b0), 59 | .clkbad (), 60 | .clkena ({6{1'b1}}), 61 | .clkloss (), 62 | .clkswitch (1'b0), 63 | .configupdate (1'b0), 64 | .enable0 (), 65 | .enable1 (), 66 | .extclk (), 67 | .extclkena ({4{1'b1}}), 68 | .fbin (1'b1), 69 | .fbmimicbidir (), 70 | .fbout (), 71 | .fref (), 72 | .icdrclk (), 73 | .locked (), 74 | .pfdena (1'b1), 75 | .phasecounterselect ({4{1'b1}}), 76 | .phasedone (), 77 | .phasestep (1'b1), 78 | .phaseupdown (1'b1), 79 | .pllena (1'b1), 80 | .scanaclr (1'b0), 81 | .scanclk (1'b0), 82 | .scanclkena (1'b1), 83 | .scandata (1'b0), 84 | .scandataout (), 85 | .scandone (), 86 | .scanread (1'b0), 87 | .scanwrite (1'b0), 88 | .sclkout0 (), 89 | .sclkout1 (), 90 | .vcooverrange (), 91 | .vcounderrange ()); 92 | defparam 93 | altpll_component.bandwidth_type = "AUTO", 94 | altpll_component.clk0_divide_by = 1, 95 | altpll_component.clk0_duty_cycle = 50, 96 | altpll_component.clk0_multiply_by = 1, 97 | altpll_component.clk0_phase_shift = "0", 98 | altpll_component.compensate_clock = "CLK0", 99 | altpll_component.inclk0_input_frequency = 20000, 100 | altpll_component.intended_device_family = "Cyclone IV E", 101 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", 102 | altpll_component.lpm_type = "altpll", 103 | altpll_component.operation_mode = "NORMAL", 104 | altpll_component.pll_type = "AUTO", 105 | altpll_component.port_activeclock = "PORT_UNUSED", 106 | altpll_component.port_areset = "PORT_UNUSED", 107 | altpll_component.port_clkbad0 = "PORT_UNUSED", 108 | altpll_component.port_clkbad1 = "PORT_UNUSED", 109 | altpll_component.port_clkloss = "PORT_UNUSED", 110 | altpll_component.port_clkswitch = "PORT_UNUSED", 111 | altpll_component.port_configupdate = "PORT_UNUSED", 112 | altpll_component.port_fbin = "PORT_UNUSED", 113 | altpll_component.port_inclk0 = "PORT_USED", 114 | altpll_component.port_inclk1 = "PORT_UNUSED", 115 | altpll_component.port_locked = "PORT_UNUSED", 116 | altpll_component.port_pfdena = "PORT_UNUSED", 117 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 118 | altpll_component.port_phasedone = "PORT_UNUSED", 119 | altpll_component.port_phasestep = "PORT_UNUSED", 120 | altpll_component.port_phaseupdown = "PORT_UNUSED", 121 | altpll_component.port_pllena = "PORT_UNUSED", 122 | altpll_component.port_scanaclr = "PORT_UNUSED", 123 | altpll_component.port_scanclk = "PORT_UNUSED", 124 | altpll_component.port_scanclkena = "PORT_UNUSED", 125 | altpll_component.port_scandata = "PORT_UNUSED", 126 | altpll_component.port_scandataout = "PORT_UNUSED", 127 | altpll_component.port_scandone = "PORT_UNUSED", 128 | altpll_component.port_scanread = "PORT_UNUSED", 129 | altpll_component.port_scanwrite = "PORT_UNUSED", 130 | altpll_component.port_clk0 = "PORT_USED", 131 | altpll_component.port_clk1 = "PORT_UNUSED", 132 | altpll_component.port_clk2 = "PORT_UNUSED", 133 | altpll_component.port_clk3 = "PORT_UNUSED", 134 | altpll_component.port_clk4 = "PORT_UNUSED", 135 | altpll_component.port_clk5 = "PORT_UNUSED", 136 | altpll_component.port_clkena0 = "PORT_UNUSED", 137 | altpll_component.port_clkena1 = "PORT_UNUSED", 138 | altpll_component.port_clkena2 = "PORT_UNUSED", 139 | altpll_component.port_clkena3 = "PORT_UNUSED", 140 | altpll_component.port_clkena4 = "PORT_UNUSED", 141 | altpll_component.port_clkena5 = "PORT_UNUSED", 142 | altpll_component.port_extclk0 = "PORT_UNUSED", 143 | altpll_component.port_extclk1 = "PORT_UNUSED", 144 | altpll_component.port_extclk2 = "PORT_UNUSED", 145 | altpll_component.port_extclk3 = "PORT_UNUSED", 146 | altpll_component.width_clock = 5; 147 | 148 | 149 | endmodule 150 | 151 | // ============================================================ 152 | // CNX file retrieval info 153 | // ============================================================ 154 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 156 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 157 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 158 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 159 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 160 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 161 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 162 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 163 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 164 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 165 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 166 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 168 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 169 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 170 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 171 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 172 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "50.000000" 173 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 174 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 175 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 176 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 177 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 179 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 180 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 181 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 182 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 183 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 184 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 185 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 186 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 187 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 188 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 189 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 190 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 191 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 192 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 193 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 194 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 195 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" 196 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 197 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "10.00000000" 198 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" 199 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 200 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 201 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" 203 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 205 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 208 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 209 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 210 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 212 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 214 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 215 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" 216 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 218 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 219 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 220 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 221 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 222 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 223 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 224 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 225 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 226 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 227 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 228 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 229 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 230 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 231 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 232 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 233 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 234 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 235 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 236 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 237 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 238 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1" 239 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" 240 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 241 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 242 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 243 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 244 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 245 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 246 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 247 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 248 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 255 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 260 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 262 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 269 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 271 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 272 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 286 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 288 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 289 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 290 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 291 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 292 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 293 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 294 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE 295 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE 296 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE 297 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE 298 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE 299 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE 300 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v TRUE 301 | // Retrieval info: LIB_FILE: altera_mf 302 | // Retrieval info: CBX_MODULE_PREFIX: ON 303 | -------------------------------------------------------------------------------- /rtl/pll_ram.v: -------------------------------------------------------------------------------- 1 | // megafunction wizard: %ALTPLL% 2 | // GENERATION: STANDARD 3 | // VERSION: WM1.0 4 | // MODULE: altpll 5 | 6 | // ============================================================ 7 | // File Name: pll_ram.v 8 | // Megafunction Name(s): 9 | // altpll 10 | // 11 | // Simulation Library Files(s): 12 | // altera_mf 13 | // ============================================================ 14 | // ************************************************************ 15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! 16 | // 17 | // 14.0.0 Build 200 06/17/2014 SJ Web Edition 18 | // ************************************************************ 19 | 20 | 21 | //Copyright (C) 1991-2014 Altera Corporation. All rights reserved. 22 | //Your use of Altera Corporation's design tools, logic functions 23 | //and other software and tools, and its AMPP partner logic 24 | //functions, and any output files from any of the foregoing 25 | //(including device programming or simulation files), and any 26 | //associated documentation or information are expressly subject 27 | //to the terms and conditions of the Altera Program License 28 | //Subscription Agreement, the Altera Quartus II License Agreement, 29 | //the Altera MegaCore Function License Agreement, or other 30 | //applicable license agreement, including, without limitation, 31 | //that your use is for the sole purpose of programming logic 32 | //devices manufactured by Altera and sold by Altera or its 33 | //authorized distributors. Please refer to the applicable 34 | //agreement for further details. 35 | 36 | 37 | // synopsys translate_off 38 | `timescale 1 ps / 1 ps 39 | // synopsys translate_on 40 | module pll_ram ( 41 | inclk0, 42 | c0); 43 | 44 | input inclk0; 45 | output c0; 46 | 47 | wire [0:0] sub_wire2 = 1'h0; 48 | wire [4:0] sub_wire3; 49 | wire sub_wire0 = inclk0; 50 | wire [1:0] sub_wire1 = {sub_wire2, sub_wire0}; 51 | wire [0:0] sub_wire4 = sub_wire3[0:0]; 52 | wire c0 = sub_wire4; 53 | 54 | altpll altpll_component ( 55 | .inclk (sub_wire1), 56 | .clk (sub_wire3), 57 | .activeclock (), 58 | .areset (1'b0), 59 | .clkbad (), 60 | .clkena ({6{1'b1}}), 61 | .clkloss (), 62 | .clkswitch (1'b0), 63 | .configupdate (1'b0), 64 | .enable0 (), 65 | .enable1 (), 66 | .extclk (), 67 | .extclkena ({4{1'b1}}), 68 | .fbin (1'b1), 69 | .fbmimicbidir (), 70 | .fbout (), 71 | .fref (), 72 | .icdrclk (), 73 | .locked (), 74 | .pfdena (1'b1), 75 | .phasecounterselect ({4{1'b1}}), 76 | .phasedone (), 77 | .phasestep (1'b1), 78 | .phaseupdown (1'b1), 79 | .pllena (1'b1), 80 | .scanaclr (1'b0), 81 | .scanclk (1'b0), 82 | .scanclkena (1'b1), 83 | .scandata (1'b0), 84 | .scandataout (), 85 | .scandone (), 86 | .scanread (1'b0), 87 | .scanwrite (1'b0), 88 | .sclkout0 (), 89 | .sclkout1 (), 90 | .vcooverrange (), 91 | .vcounderrange ()); 92 | defparam 93 | altpll_component.bandwidth_type = "AUTO", 94 | altpll_component.clk0_divide_by = 1, 95 | altpll_component.clk0_duty_cycle = 50, 96 | altpll_component.clk0_multiply_by = 4, 97 | altpll_component.clk0_phase_shift = "4583", 98 | altpll_component.compensate_clock = "CLK0", 99 | altpll_component.inclk0_input_frequency = 20000, 100 | altpll_component.intended_device_family = "Cyclone IV E", 101 | altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ram", 102 | altpll_component.lpm_type = "altpll", 103 | altpll_component.operation_mode = "NORMAL", 104 | altpll_component.pll_type = "AUTO", 105 | altpll_component.port_activeclock = "PORT_UNUSED", 106 | altpll_component.port_areset = "PORT_UNUSED", 107 | altpll_component.port_clkbad0 = "PORT_UNUSED", 108 | altpll_component.port_clkbad1 = "PORT_UNUSED", 109 | altpll_component.port_clkloss = "PORT_UNUSED", 110 | altpll_component.port_clkswitch = "PORT_UNUSED", 111 | altpll_component.port_configupdate = "PORT_UNUSED", 112 | altpll_component.port_fbin = "PORT_UNUSED", 113 | altpll_component.port_inclk0 = "PORT_USED", 114 | altpll_component.port_inclk1 = "PORT_UNUSED", 115 | altpll_component.port_locked = "PORT_UNUSED", 116 | altpll_component.port_pfdena = "PORT_UNUSED", 117 | altpll_component.port_phasecounterselect = "PORT_UNUSED", 118 | altpll_component.port_phasedone = "PORT_UNUSED", 119 | altpll_component.port_phasestep = "PORT_UNUSED", 120 | altpll_component.port_phaseupdown = "PORT_UNUSED", 121 | altpll_component.port_pllena = "PORT_UNUSED", 122 | altpll_component.port_scanaclr = "PORT_UNUSED", 123 | altpll_component.port_scanclk = "PORT_UNUSED", 124 | altpll_component.port_scanclkena = "PORT_UNUSED", 125 | altpll_component.port_scandata = "PORT_UNUSED", 126 | altpll_component.port_scandataout = "PORT_UNUSED", 127 | altpll_component.port_scandone = "PORT_UNUSED", 128 | altpll_component.port_scanread = "PORT_UNUSED", 129 | altpll_component.port_scanwrite = "PORT_UNUSED", 130 | altpll_component.port_clk0 = "PORT_USED", 131 | altpll_component.port_clk1 = "PORT_UNUSED", 132 | altpll_component.port_clk2 = "PORT_UNUSED", 133 | altpll_component.port_clk3 = "PORT_UNUSED", 134 | altpll_component.port_clk4 = "PORT_UNUSED", 135 | altpll_component.port_clk5 = "PORT_UNUSED", 136 | altpll_component.port_clkena0 = "PORT_UNUSED", 137 | altpll_component.port_clkena1 = "PORT_UNUSED", 138 | altpll_component.port_clkena2 = "PORT_UNUSED", 139 | altpll_component.port_clkena3 = "PORT_UNUSED", 140 | altpll_component.port_clkena4 = "PORT_UNUSED", 141 | altpll_component.port_clkena5 = "PORT_UNUSED", 142 | altpll_component.port_extclk0 = "PORT_UNUSED", 143 | altpll_component.port_extclk1 = "PORT_UNUSED", 144 | altpll_component.port_extclk2 = "PORT_UNUSED", 145 | altpll_component.port_extclk3 = "PORT_UNUSED", 146 | altpll_component.width_clock = 5; 147 | 148 | 149 | endmodule 150 | 151 | // ============================================================ 152 | // CNX file retrieval info 153 | // ============================================================ 154 | // Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" 155 | // Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" 156 | // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" 157 | // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" 158 | // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" 159 | // Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" 160 | // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" 161 | // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" 162 | // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" 163 | // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" 164 | // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" 165 | // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" 166 | // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" 167 | // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" 168 | // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" 169 | // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" 170 | // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" 171 | // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" 172 | // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "200.000000" 173 | // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" 174 | // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" 175 | // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" 176 | // Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" 177 | // Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" 178 | // Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" 179 | // Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" 180 | // Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000" 181 | // Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" 182 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" 183 | // Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" 184 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" 185 | // Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" 186 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 187 | // Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" 188 | // Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" 189 | // Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" 190 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" 191 | // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" 192 | // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" 193 | // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" 194 | // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" 195 | // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "4" 196 | // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" 197 | // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" 198 | // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" 199 | // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" 200 | // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" 201 | // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" 202 | // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "330.00000000" 203 | // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" 204 | // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" 205 | // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" 206 | // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" 207 | // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" 208 | // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" 209 | // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" 210 | // Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" 211 | // Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" 212 | // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" 213 | // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" 214 | // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" 215 | // Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ram.mif" 216 | // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" 217 | // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" 218 | // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" 219 | // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" 220 | // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" 221 | // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" 222 | // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" 223 | // Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" 224 | // Retrieval info: PRIVATE: SPREAD_USE STRING "0" 225 | // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" 226 | // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" 227 | // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" 228 | // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" 229 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" 230 | // Retrieval info: PRIVATE: USE_CLK0 STRING "1" 231 | // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" 232 | // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" 233 | // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" 234 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all 235 | // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" 236 | // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1" 237 | // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" 238 | // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "4" 239 | // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "4583" 240 | // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" 241 | // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000" 242 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E" 243 | // Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" 244 | // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" 245 | // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" 246 | // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" 247 | // Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" 248 | // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" 249 | // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" 250 | // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" 251 | // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" 252 | // Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" 253 | // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" 254 | // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" 255 | // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" 256 | // Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" 257 | // Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" 258 | // Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" 259 | // Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" 260 | // Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" 261 | // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" 262 | // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" 263 | // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" 264 | // Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" 265 | // Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" 266 | // Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" 267 | // Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" 268 | // Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" 269 | // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" 270 | // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" 271 | // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" 272 | // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" 273 | // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" 274 | // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" 275 | // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" 276 | // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" 277 | // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" 278 | // Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" 279 | // Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" 280 | // Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" 281 | // Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" 282 | // Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" 283 | // Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" 284 | // Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" 285 | // Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" 286 | // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" 287 | // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" 288 | // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" 289 | // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" 290 | // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" 291 | // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 292 | // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 293 | // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 294 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.v TRUE 295 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.ppf TRUE 296 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.inc FALSE 297 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.cmp FALSE 298 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram.bsf FALSE 299 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram_inst.v FALSE 300 | // Retrieval info: GEN_FILE: TYPE_NORMAL pll_ram_bb.v TRUE 301 | // Retrieval info: LIB_FILE: altera_mf 302 | // Retrieval info: CBX_MODULE_PREFIX: ON 303 | --------------------------------------------------------------------------------