├── .gitignore ├── LICENSE ├── README.md ├── setup.py ├── src └── upp │ ├── __init__.py │ ├── atom_gen │ ├── README.md │ ├── __init__.py │ ├── atombios.py │ ├── pptable_v1_0.py │ ├── smu_v11_0_7_navi20.py │ ├── smu_v11_0_arcturus.py │ ├── smu_v11_0_navi10.py │ ├── smu_v13_0_7_navi30.py │ ├── smu_v14_0_2_navi40.py │ ├── vega10_pptable.py │ └── vega20_pptable.py │ ├── decode.py │ └── upp.py ├── test ├── AMD.RX480.8192.160603.rom.dump ├── AMD.RX480.8192.160603.rom.rawdump ├── AMD.RX5700XT.8192.190616.rom.check ├── AMD.RX5700XT.8192.190616.rom.conf ├── AMD.RX5700XT.8192.190616.rom.dump ├── AMD.RX5700XT.8192.190616.rom.rawdump ├── AMD.RX6900XT.16384.201104.rom.dump ├── AMD.RX6900XT.16384.201104.rom.rawdump ├── AMD.RX7900XTX.24576.230323.rom.dump ├── AMD.RX7900XTX.24576.230323.rom.rawdump ├── AMD.RXVega64.8176.170719.rom.dump ├── AMD.RXVega64.8176.170719.rom.rawdump ├── AMD.RXVegaFrontier.16384.170628.rom.dump ├── AMD.RXVegaFrontier.16384.170628.rom.rawdump ├── AMD.RadeonVII.16384.190116.rom.dump ├── AMD.RadeonVII.16384.190116.rom.rawdump ├── MI100_000.000.000.000.016113_113-D3431401-100.rom.dump ├── MI100_000.000.000.000.016113_113-D3431401-100.rom.rawdump ├── Powercolor.RX9070.16384.241204_1.rom.dump ├── Powercolor.RX9070.16384.241204_1.rom.rawdump ├── navi23.mpt └── test.sh └── upliftpowerplay@.service /.gitignore: -------------------------------------------------------------------------------- 1 | test/ROMs/ 2 | test/tmp/ 3 | 4 | # Byte-compiled / optimized / DLL files 5 | __pycache__/ 6 | *.py[cod] 7 | *$py.class 8 | 9 | # C extensions 10 | *.so 11 | 12 | # Distribution / packaging 13 | .Python 14 | build/ 15 | develop-eggs/ 16 | dist/ 17 | downloads/ 18 | eggs/ 19 | .eggs/ 20 | lib/ 21 | lib64/ 22 | parts/ 23 | sdist/ 24 | var/ 25 | wheels/ 26 | *.egg-info/ 27 | .installed.cfg 28 | *.egg 29 | MANIFEST 30 | 31 | # PyInstaller 32 | # Usually these files are written by a python script from a template 33 | # before PyInstaller builds the exe, so as to inject date/other infos into it. 34 | *.manifest 35 | *.spec 36 | 37 | # Installer logs 38 | pip-log.txt 39 | pip-delete-this-directory.txt 40 | 41 | # Unit test / coverage reports 42 | htmlcov/ 43 | .tox/ 44 | .coverage 45 | .coverage.* 46 | .cache 47 | nosetests.xml 48 | coverage.xml 49 | *.cover 50 | .hypothesis/ 51 | .pytest_cache/ 52 | 53 | # Translations 54 | *.mo 55 | *.pot 56 | 57 | # Django stuff: 58 | *.log 59 | local_settings.py 60 | db.sqlite3 61 | 62 | # Flask stuff: 63 | instance/ 64 | .webassets-cache 65 | 66 | # Scrapy stuff: 67 | .scrapy 68 | 69 | # Sphinx documentation 70 | docs/_build/ 71 | 72 | # PyBuilder 73 | target/ 74 | 75 | # Jupyter Notebook 76 | .ipynb_checkpoints 77 | 78 | # pyenv 79 | .python-version 80 | 81 | # celery beat schedule file 82 | celerybeat-schedule 83 | 84 | # SageMath parsed files 85 | *.sage.py 86 | 87 | # Environments 88 | .env 89 | .venv 90 | env/ 91 | venv/ 92 | ENV/ 93 | env.bak/ 94 | venv.bak/ 95 | 96 | # Spyder project settings 97 | .spyderproject 98 | .spyproject 99 | 100 | # Rope project settings 101 | .ropeproject 102 | 103 | # mkdocs documentation 104 | /site 105 | 106 | # mypy 107 | .mypy_cache/ 108 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | ## UPP 2 | 3 | UPP: Uplift Power Play 4 | 5 | A tool for parsing, dumping and modifying data in Radeon PowerPlay tables 6 | 7 | ### Introduction 8 | 9 | UPP is able to parse and modify binary data structures of PowerPlay tables 10 | commonly found on certain AMD Radeon GPUs. Drivers on recent AMD GPUs 11 | allow PowerPlay tables to be dynamically modified on runtime, which may be 12 | known as "soft" PowerPlay table. On Linux, the PowerPlay table is by default 13 | found at: `/sys/class/drm/card0/device/pp_table`. 14 | 15 | This tool does very minimal interpretation of actual PowerPlay table values. 16 | By design, it is mostly up to the user to do such thing. 17 | 18 | Alternatively, one can use this tool to get PowerPlay data by: 19 | 20 | * Extracting PowerPlay table from Video ROM image (see extract command) 21 | * Importing "Soft PowerPlay" table from Windows registry, directly from 22 | offline Windows/System32/config/SYSTEM file on disk, so it would work 23 | from Linux distro that has access to mounted Windows partition 24 | (path to SYSTEM registry file is specified with `--from-registry` option) 25 | * Importing "Soft PowerPlay" table from "More Powe Tool" MPT file 26 | (path to MPT file is specified with `--from-mpt option`) 27 | 28 | This tool currently supports parsing and modifying PowerPlay tables found 29 | on the following AMD GPU families: 30 | 31 | * Polaris 32 | * Vega 33 | * Radeon VII 34 | * Navi 10 35 | * Arcturus (MI100) 36 | * Navi 12 (PRO V520) 37 | * Navi 14 38 | * Navi 21 (Sienna Cichlid) 39 | * Navi 22 (Navy Flounder) 40 | * Navi 23 (Dimgrey Cavefish) 41 | * Navi 3x 42 | * Navi 4x 43 | 44 | Notes: 45 | * iGPUs found in many recent AMD APUs are using completely different 46 | PowerPlay control methods, this tool does not support them. 47 | * The amdgpu kernel driver does not fully implement modifying the PowerPlay 48 | tables on runtime for Navi 3x and Navi 4x cards. 49 | * The amdgpu kernel driver does the incomplete PowerPlay table data dump 50 | to the `/sys/class/drm/cardX/device/pp_table` file, for Navi 3x AND 4x. 51 | The pp_table file is truncated to first 4095 bytes. Likely a driver bug. 52 | 53 | **WARNING**: Authors of this tool are in no way responsible for any damage 54 | that may happen to your expansive graphics card if you choose to modify 55 | card voltages, power limits, or any other PowerPlay parameters. Always 56 | remember that you are doing it entirely on your own risk! 57 | 58 | If you have bugs to report or features to request please create an issue on: 59 | https://github.com/sibradzic/upp 60 | 61 | ### Requirements 62 | 63 | Python 3.7+, click library. Optionally, for reading "soft" PowerPlay table 64 | from Windows registry: python-registry. Should work on Windows as well 65 | (testers wanted). 66 | 67 | ### Installation 68 | 69 | Either get it with pip: 70 | 71 | pip install upp 72 | 73 | or use it as is directly from the source tree: 74 | 75 | cd src 76 | python3 -m upp.upp --help 77 | 78 | ### Usage 79 | 80 | At its current form this is a CLI only tool. Getting help: 81 | 82 | upp --help 83 | 84 | or 85 | 86 | upp --help 87 | 88 | Upp will only work by specifying a command which tells it what to do to one's 89 | Radeon PowerPlay table data. Currently available commands are: 90 | 91 | * **dump** - Dumps all PowerPlay data to console 92 | * **extract** - Extracts PowerPlay data from full VBIOS ROM image 93 | * **inject** - Injects PowerPlay data from file into VBIOS ROM image 94 | * **get** - Retrieves current value of one or multiple PowerPlay parameter(s) 95 | * **set** - Sets value to one or multiple PowerPlay parameters 96 | * **undump** - Sets all PowerPlay parameters to pp file or registry 97 | * **version** - Shows UPP version 98 | 99 | So, an usage pattern would be like this: 100 | 101 | upp [OPTIONS] COMMAND [ARGS]... 102 | 103 | Some generic options applicable to all commands may be used, but please note 104 | that they have to be specified *before* an actual command: 105 | 106 | -p, --pp-file Input/output PP table binary file. 107 | -f, --from-registry Import PP_PhmSoftPowerPlayTable from Windows 108 | registry (overrides -p / --pp-file option). 109 | -m, --from-mpt Import PowerPlay Table from More Power Tool 110 | (overrides --pp-file and --from-registry optios). 111 | -d, --debug / --no-debug Debug mode. 112 | -h, --help Show this message and exit. 113 | 114 | #### Dumping all data: 115 | 116 | The **dump** command de-serializes PowerPlay binary data into a human-readable 117 | text output. For example: 118 | 119 | upp dump 120 | 121 | In standard mode all data will be dumped to console, where data tree hierarchy 122 | is indicated by indentation. In raw mode a table showing all hex and binary 123 | data, as well as variable names and values, will be dumped. 124 | 125 | #### Extracting PowerPlay table from Video ROM image: 126 | 127 | Use **extract** command for this. The source video ROM binary must be specified 128 | with `-r/--video-rom` parameter, and extracted PowerPlay table will be saved 129 | into file specified with generic `-p/--pp-file` option. For example: 130 | 131 | upp --pp-file=extracted.pp_table extract -r VIDEO.rom 132 | 133 | Default output file name will be an original ROM file name with an 134 | additional .pp_table extension. 135 | 136 | #### Injecting PowerPlay data from file into VBIOS ROM image: 137 | 138 | Use **inject** command for this. The input video ROM binary must be specified 139 | with `-i/--input-rom` parameter, and the output ROM can be specified with an 140 | optional `-o/--output-rom parameter`. For example: 141 | 142 | upp -p modded.pp_table inject -i original.rom -o modded.rom 143 | 144 | **WARNING**: Modified vROM image is probably not going to work if flashed as is 145 | to your card, due to ROM signature checks on recent Radeon cards. Authors of 146 | this tool are in no way responsible for any damage that may happen to your 147 | expansive graphics card if you choose to flash the modified video ROM, you are 148 | doing it entirely on your own risk. 149 | 150 | #### Getting PowerPlay table parameter value(s): 151 | 152 | The **get** command retrieves current value of one or multiple PowerPlay table 153 | parameter value(s). The parameter variable path must be specified in `/` 154 | notation, for example: 155 | 156 | upp get smc_pptable/FreqTableGfx/1 smc_pptable/FreqTableGfx/2 157 | 1850 158 | 1400 159 | 160 | The order of the output values will match the order of the parameter variable 161 | paths specified. 162 | 163 | #### Setting PowerPlay table parameter value(s): 164 | 165 | The **set** command sets value to one or multiple PowerPlay table 166 | parameter(s). The parameter path and value must be specified in 167 | `/=` notation, for example: 168 | 169 | upp -p /tmp/custom-pp_table set --write \ 170 | smc_pptable/SocketPowerLimitAc/0=100 \ 171 | smc_pptable/SocketPowerLimitDc/0=100 \ 172 | smc_pptable/FanStartTemp=100 \ 173 | smc_pptable/FreqTableGfx/1=1550 174 | 175 | It is possible to set parameters from a configuration file with one 176 | "/=" per line using -c/--from-conf instead of directly 177 | passing parameters from command line 178 | 179 | upp set --from-conf=card0.conf 180 | 181 | Note the `--write` parameter, which has to be specified to actually commit 182 | changes to the PowerPlay table file. 183 | 184 | #### Undumps all PowerPlay parameters: 185 | 186 | The **undump** command sets all values from previously dumped PowerPlay table parameter(s) back to pp_table or registry. It allows you to make changes in dumped text file and write back all changes at once. Basically it's a convenient way to set multiple values. For example: 187 | 188 | # extract pp_table from vbios 189 | upp --pp-file=vbios.pp_table extract -r vbios.rom 190 | # dump powerplay table to text file 191 | upp --pp-file=vbios.pp_table dump > vbios.pp_table.dump 192 | # make changes in vbios.pp_table.dump 193 | # undump all changes back into pp_table 194 | upp --pp-file=vbios.pp_table undump -d vbios.pp_table.dump -w 195 | 196 | Note the `--write` parameter, which has to be specified to actually commit 197 | changes to the PowerPlay table file. 198 | 199 | #### Getting upp version 200 | 201 | upp version 202 | 203 | #### Running as sudo 204 | 205 | Note that if you need to run upp deployed with **pip** in `--user` mode with 206 | sudo, you'll need to add some parameters to sudo command to make user env 207 | available to super-user. For example: 208 | 209 | sudo -E env "PATH=$PATH" upp --help 210 | 211 | -------------------------------------------------------------------------------- /setup.py: -------------------------------------------------------------------------------- 1 | import setuptools 2 | 3 | with open('README.md', 'r') as fh: 4 | long_description = fh.read() 5 | 6 | setuptools.setup( 7 | name='upp', 8 | version='0.2.4', 9 | author='Samir Ibradžić', 10 | description='Uplift Power Play', 11 | long_description=long_description, 12 | long_description_content_type='text/markdown', 13 | url='https://github.com/sibradzic/upp', 14 | package_dir={'': 'src'}, 15 | packages=['upp', 'upp/atom_gen'], 16 | classifiers=[ 17 | 'Programming Language :: Python :: 3', 18 | 'Programming Language :: Python :: 3.7', 19 | 'Programming Language :: Python :: 3.8', 20 | 'Programming Language :: Python :: 3.9', 21 | 'Programming Language :: Python :: 3.10', 22 | 'Programming Language :: Python :: 3.11', 23 | 'Programming Language :: Python :: 3.12', 24 | 'License :: OSI Approved :: GNU General Public License v3 (GPLv3)', 25 | 'Operating System :: OS Independent', 26 | ], 27 | python_requires='>=3.7, <4', 28 | install_requires=[ 29 | 'click', 30 | 'setuptools' 31 | ], 32 | entry_points={ 33 | 'console_scripts': [ 34 | 'upp=upp.upp:main', 35 | ], 36 | }, 37 | ) 38 | -------------------------------------------------------------------------------- /src/upp/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sibradzic/upp/3db7f14910211a82f8e2fd2f85cfd9ebbfa7192d/src/upp/__init__.py -------------------------------------------------------------------------------- /src/upp/atom_gen/README.md: -------------------------------------------------------------------------------- 1 | 2 | # How to generate Python readable ATOM C structures from Linux kernel code 3 | 4 | ## Versions 5 | 6 | Generated against kernel commit 80e54e849 (v6.14-rc6) (Sun Mar 9 13:45:25 2025 -1000) 7 | Generated against drm-next kernel commit 5da39dce1 tag drm-xe-next-fixes-2025-03-12 8 | 9 | clang version 19.1.7 10 | ctypeslib2 2.4.0 11 | 12 | 13 | ## Python Requirements 14 | 15 | sudo apt install clang 16 | pip3 install --user clang==19.1.7 ctypeslib2==2.4.0 17 | 18 | or 19 | 20 | pacman -S clang 21 | pipx install --preinstall clang==19.1.7 ctypeslib2 22 | 23 | 24 | ## Get a particular Linux kernel release 25 | 26 | git clone --depth=1 git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 27 | pushd linux 28 | # git fetch origin v6.14-rc6 --tags 29 | # git checkout v6.14-rc6 30 | # git remote add linux-next https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git 31 | # git fetch --tags linux-next 32 | git remote add drm-next https://anongit.freedesktop.org/git/drm/drm.git 33 | git fetch --tags drm-next 34 | git checkout drm-next 35 | popd 36 | 37 | 38 | ## Some Linux header hacks, clang2py can't deal with __counted_by() 39 | 40 | sed -i 's| __counted_by(.*);|; //\0|' linux/drivers/gpu/drm/amd/include/pptable.h 41 | sed -i 's| __counted_by(.*);|; //\0|' linux/drivers/gpu/drm/amd/include/atomfirmware.h 42 | sed -i 's| __counted_by(.*);|; //\0|' linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h 43 | sed -i 's|#include "hwmgr.h"|//\0|' linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h 44 | 45 | 46 | ## atombios.py 47 | 48 | clang2py -k 's' --clang-args="\ 49 | --include stdint.h \ 50 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 51 | " \ 52 | -s struct__ATOM_COMMON_TABLE_HEADER -s struct__ATOM_MASTER_DATA_TABLE \ 53 | -s struct__ATOM_ROM_HEADER -s struct__ATOM_ROM_HEADER_V2_1 \ 54 | linux/drivers/gpu/drm/amd/include/atombios.h > atombios.py 55 | 56 | 57 | ## pptable_v1_0.py (Polaris/Tonga) 58 | 59 | 60 | clang2py -k 'mst' \ 61 | --clang-args="\ 62 | --include stdint.h \ 63 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 64 | --include linux/drivers/gpu/drm/amd/include/atombios.h 65 | " \ 66 | linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h > pptable_v1_0.py 67 | 68 | 69 | ## vega10_pptable.py (Vega10 aka Vega 56/64) 70 | 71 | clang2py -k 'mste' \ 72 | --clang-args="--include stdint.h \ 73 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 74 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 75 | --include linux/drivers/gpu/drm/amd/include/atombios.h" \ 76 | linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega10_pptable.h > vega10_pptable.py 77 | 78 | 79 | ## vega20_pptable.py (Vega20 aka Radeon7) 80 | 81 | clang2py -k 'mste' \ 82 | --clang-args="--include stdint.h \ 83 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 84 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 85 | --include linux/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h " \ 86 | linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega20_pptable.h > vega20_pptable.py 87 | 88 | 89 | ## smu_v11_0_navi10.py (Navi10/14) 90 | 91 | clang2py -k 'mste' \ 92 | --clang-args="--include stdint.h \ 93 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 94 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 95 | --include linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_navi10.h " \ 96 | linux/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h > smu_v11_0_navi10.py 97 | 98 | 99 | ## smu_v11_0_arcturus.py (MI100) 100 | 101 | clang2py -k 'mste' \ 102 | --clang-args="--include stdint.h \ 103 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 104 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 105 | --include linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_arcturus.h " \ 106 | linux/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_pptable.h > smu_v11_0_arcturus.py 107 | 108 | 109 | ## smu_v11_0_navi20.py (Navi2x) 110 | 111 | clang2py -k 'mste' \ 112 | --clang-args="--include stdint.h \ 113 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 114 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 115 | --include linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu11_driver_if_sienna_cichlid.h " \ 116 | linux/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v11_0_7_pptable.h > smu_v11_0_7_navi20.py 117 | 118 | 119 | ## smu_v13_0 (Navi 3x) 120 | 121 | clang2py -k 'mste' \ 122 | --clang-args="--include stdint.h \ 123 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 124 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 125 | --include linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu13_driver_if_v13_0_7.h " \ 126 | linux/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0_7_pptable.h > smu_v13_0_7_navi30.py 127 | 128 | 129 | ## smu_v14_0 (Navi 4x) 130 | 131 | clang2py -k 'mste' \ 132 | --clang-args="--include stdint.h \ 133 | --include linux/drivers/gpu/drm/amd/include/atom-types.h \ 134 | --include linux/drivers/gpu/drm/amd/include/atomfirmware.h \ 135 | --include linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h " \ 136 | linux/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0_2_pptable.h > smu_v14_0_2_navi40.py 137 | 138 | 139 | ## Linux source cleanup 140 | 141 | pushd linux 142 | git checkout \ 143 | drivers/gpu/drm/amd/include/pptable.h \ 144 | drivers/gpu/drm/amd/include/atomfirmware.h \ 145 | drivers/gpu/drm/amd/pm/powerplay/hwmgr/pptable_v1_0.h 146 | popd 147 | 148 | -------------------------------------------------------------------------------- /src/upp/atom_gen/__init__.py: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sibradzic/upp/3db7f14910211a82f8e2fd2f85cfd9ebbfa7192d/src/upp/atom_gen/__init__.py -------------------------------------------------------------------------------- /src/upp/atom_gen/atombios.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # 3 | # TARGET arch is: ['', '--include', 'stdint.h', '--include', 'linux/drivers/gpu/drm/amd/include/atom-types.h', ''] 4 | # WORD_SIZE is: 8 5 | # POINTER_SIZE is: 8 6 | # LONGDOUBLE_SIZE is: 16 7 | # 8 | import ctypes 9 | 10 | 11 | class AsDictMixin: 12 | @classmethod 13 | def as_dict(cls, self): 14 | result = {} 15 | if not isinstance(self, AsDictMixin): 16 | # not a structure, assume it's already a python object 17 | return self 18 | if not hasattr(cls, "_fields_"): 19 | return result 20 | # sys.version_info >= (3, 5) 21 | # for (field, *_) in cls._fields_: # noqa 22 | for field_tuple in cls._fields_: # noqa 23 | field = field_tuple[0] 24 | if field.startswith('PADDING_'): 25 | continue 26 | value = getattr(self, field) 27 | type_ = type(value) 28 | if hasattr(value, "_length_") and hasattr(value, "_type_"): 29 | # array 30 | type_ = type_._type_ 31 | if hasattr(type_, 'as_dict'): 32 | value = [type_.as_dict(v) for v in value] 33 | else: 34 | value = [i for i in value] 35 | elif hasattr(value, "contents") and hasattr(value, "_type_"): 36 | # pointer 37 | try: 38 | if not hasattr(type_, "as_dict"): 39 | value = value.contents 40 | else: 41 | type_ = type_._type_ 42 | value = type_.as_dict(value.contents) 43 | except ValueError: 44 | # nullptr 45 | value = None 46 | elif isinstance(value, AsDictMixin): 47 | # other structure 48 | value = type_.as_dict(value) 49 | result[field] = value 50 | return result 51 | 52 | 53 | class Structure(ctypes.Structure, AsDictMixin): 54 | 55 | def __init__(self, *args, **kwds): 56 | # We don't want to use positional arguments fill PADDING_* fields 57 | 58 | args = dict(zip(self.__class__._field_names_(), args)) 59 | args.update(kwds) 60 | super(Structure, self).__init__(**args) 61 | 62 | @classmethod 63 | def _field_names_(cls): 64 | if hasattr(cls, '_fields_'): 65 | return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) 66 | else: 67 | return () 68 | 69 | @classmethod 70 | def get_type(cls, field): 71 | for f in cls._fields_: 72 | if f[0] == field: 73 | return f[1] 74 | return None 75 | 76 | @classmethod 77 | def bind(cls, bound_fields): 78 | fields = {} 79 | for name, type_ in cls._fields_: 80 | if hasattr(type_, "restype"): 81 | if name in bound_fields: 82 | if bound_fields[name] is None: 83 | fields[name] = type_() 84 | else: 85 | # use a closure to capture the callback from the loop scope 86 | fields[name] = ( 87 | type_((lambda callback: lambda *args: callback(*args))( 88 | bound_fields[name])) 89 | ) 90 | del bound_fields[name] 91 | else: 92 | # default callback implementation (does nothing) 93 | try: 94 | default_ = type_(0).restype().value 95 | except TypeError: 96 | default_ = None 97 | fields[name] = type_(( 98 | lambda default_: lambda *args: default_)(default_)) 99 | else: 100 | # not a callback function, use default initialization 101 | if name in bound_fields: 102 | fields[name] = bound_fields[name] 103 | del bound_fields[name] 104 | else: 105 | fields[name] = type_() 106 | if len(bound_fields) != 0: 107 | raise ValueError( 108 | "Cannot bind the following unknown callback(s) {}.{}".format( 109 | cls.__name__, bound_fields.keys() 110 | )) 111 | return cls(**fields) 112 | 113 | 114 | class Union(ctypes.Union, AsDictMixin): 115 | pass 116 | 117 | 118 | 119 | 120 | 121 | class struct__ATOM_COMMON_TABLE_HEADER(Structure): 122 | pass 123 | 124 | struct__ATOM_COMMON_TABLE_HEADER._pack_ = 1 # source:False 125 | struct__ATOM_COMMON_TABLE_HEADER._fields_ = [ 126 | ('usStructureSize', ctypes.c_uint16), 127 | ('ucTableFormatRevision', ctypes.c_ubyte), 128 | ('ucTableContentRevision', ctypes.c_ubyte), 129 | ] 130 | 131 | class struct__ATOM_ROM_HEADER(Structure): 132 | pass 133 | 134 | ATOM_COMMON_TABLE_HEADER = struct__ATOM_COMMON_TABLE_HEADER 135 | struct__ATOM_ROM_HEADER._pack_ = 1 # source:False 136 | struct__ATOM_ROM_HEADER._fields_ = [ 137 | ('sHeader', ATOM_COMMON_TABLE_HEADER), 138 | ('uaFirmWareSignature', ctypes.c_ubyte * 4), 139 | ('usBiosRuntimeSegmentAddress', ctypes.c_uint16), 140 | ('usProtectedModeInfoOffset', ctypes.c_uint16), 141 | ('usConfigFilenameOffset', ctypes.c_uint16), 142 | ('usCRC_BlockOffset', ctypes.c_uint16), 143 | ('usBIOS_BootupMessageOffset', ctypes.c_uint16), 144 | ('usInt10Offset', ctypes.c_uint16), 145 | ('usPciBusDevInitCode', ctypes.c_uint16), 146 | ('usIoBaseAddress', ctypes.c_uint16), 147 | ('usSubsystemVendorID', ctypes.c_uint16), 148 | ('usSubsystemID', ctypes.c_uint16), 149 | ('usPCI_InfoOffset', ctypes.c_uint16), 150 | ('usMasterCommandTableOffset', ctypes.c_uint16), 151 | ('usMasterDataTableOffset', ctypes.c_uint16), 152 | ('ucExtendedFunctionCode', ctypes.c_ubyte), 153 | ('ucReserved', ctypes.c_ubyte), 154 | ] 155 | 156 | class struct__ATOM_ROM_HEADER_V2_1(Structure): 157 | pass 158 | 159 | struct__ATOM_ROM_HEADER_V2_1._pack_ = 1 # source:False 160 | struct__ATOM_ROM_HEADER_V2_1._fields_ = [ 161 | ('sHeader', ATOM_COMMON_TABLE_HEADER), 162 | ('uaFirmWareSignature', ctypes.c_ubyte * 4), 163 | ('usBiosRuntimeSegmentAddress', ctypes.c_uint16), 164 | ('usProtectedModeInfoOffset', ctypes.c_uint16), 165 | ('usConfigFilenameOffset', ctypes.c_uint16), 166 | ('usCRC_BlockOffset', ctypes.c_uint16), 167 | ('usBIOS_BootupMessageOffset', ctypes.c_uint16), 168 | ('usInt10Offset', ctypes.c_uint16), 169 | ('usPciBusDevInitCode', ctypes.c_uint16), 170 | ('usIoBaseAddress', ctypes.c_uint16), 171 | ('usSubsystemVendorID', ctypes.c_uint16), 172 | ('usSubsystemID', ctypes.c_uint16), 173 | ('usPCI_InfoOffset', ctypes.c_uint16), 174 | ('usMasterCommandTableOffset', ctypes.c_uint16), 175 | ('usMasterDataTableOffset', ctypes.c_uint16), 176 | ('ucExtendedFunctionCode', ctypes.c_ubyte), 177 | ('ucReserved', ctypes.c_ubyte), 178 | ('ulPSPDirTableOffset', ctypes.c_uint32), 179 | ] 180 | 181 | class struct__ATOM_MASTER_DATA_TABLE(Structure): 182 | pass 183 | 184 | class struct__ATOM_MASTER_LIST_OF_DATA_TABLES(Structure): 185 | pass 186 | 187 | struct__ATOM_MASTER_LIST_OF_DATA_TABLES._pack_ = 1 # source:False 188 | struct__ATOM_MASTER_LIST_OF_DATA_TABLES._fields_ = [ 189 | ('UtilityPipeLine', ctypes.c_uint16), 190 | ('MultimediaCapabilityInfo', ctypes.c_uint16), 191 | ('MultimediaConfigInfo', ctypes.c_uint16), 192 | ('StandardVESA_Timing', ctypes.c_uint16), 193 | ('FirmwareInfo', ctypes.c_uint16), 194 | ('PaletteData', ctypes.c_uint16), 195 | ('LCD_Info', ctypes.c_uint16), 196 | ('DIGTransmitterInfo', ctypes.c_uint16), 197 | ('SMU_Info', ctypes.c_uint16), 198 | ('SupportedDevicesInfo', ctypes.c_uint16), 199 | ('GPIO_I2C_Info', ctypes.c_uint16), 200 | ('VRAM_UsageByFirmware', ctypes.c_uint16), 201 | ('GPIO_Pin_LUT', ctypes.c_uint16), 202 | ('VESA_ToInternalModeLUT', ctypes.c_uint16), 203 | ('GFX_Info', ctypes.c_uint16), 204 | ('PowerPlayInfo', ctypes.c_uint16), 205 | ('GPUVirtualizationInfo', ctypes.c_uint16), 206 | ('SaveRestoreInfo', ctypes.c_uint16), 207 | ('PPLL_SS_Info', ctypes.c_uint16), 208 | ('OemInfo', ctypes.c_uint16), 209 | ('XTMDS_Info', ctypes.c_uint16), 210 | ('MclkSS_Info', ctypes.c_uint16), 211 | ('Object_Header', ctypes.c_uint16), 212 | ('IndirectIOAccess', ctypes.c_uint16), 213 | ('MC_InitParameter', ctypes.c_uint16), 214 | ('ASIC_VDDC_Info', ctypes.c_uint16), 215 | ('ASIC_InternalSS_Info', ctypes.c_uint16), 216 | ('TV_VideoMode', ctypes.c_uint16), 217 | ('VRAM_Info', ctypes.c_uint16), 218 | ('MemoryTrainingInfo', ctypes.c_uint16), 219 | ('IntegratedSystemInfo', ctypes.c_uint16), 220 | ('ASIC_ProfilingInfo', ctypes.c_uint16), 221 | ('VoltageObjectInfo', ctypes.c_uint16), 222 | ('PowerSourceInfo', ctypes.c_uint16), 223 | ('ServiceInfo', ctypes.c_uint16), 224 | ] 225 | 226 | ATOM_MASTER_LIST_OF_DATA_TABLES = struct__ATOM_MASTER_LIST_OF_DATA_TABLES 227 | struct__ATOM_MASTER_DATA_TABLE._pack_ = 1 # source:False 228 | struct__ATOM_MASTER_DATA_TABLE._fields_ = [ 229 | ('sHeader', ATOM_COMMON_TABLE_HEADER), 230 | ('ListOfDataTables', ATOM_MASTER_LIST_OF_DATA_TABLES), 231 | ] 232 | 233 | __all__ = \ 234 | ['ATOM_COMMON_TABLE_HEADER', 'ATOM_MASTER_LIST_OF_DATA_TABLES', 235 | 'struct__ATOM_COMMON_TABLE_HEADER', 236 | 'struct__ATOM_MASTER_DATA_TABLE', 237 | 'struct__ATOM_MASTER_LIST_OF_DATA_TABLES', 238 | 'struct__ATOM_ROM_HEADER', 'struct__ATOM_ROM_HEADER_V2_1'] 239 | -------------------------------------------------------------------------------- /src/upp/atom_gen/vega20_pptable.py: -------------------------------------------------------------------------------- 1 | # -*- coding: utf-8 -*- 2 | # 3 | # TARGET arch is: ['--include', 'stdint.h', '--include', 'linux/drivers/gpu/drm/amd/include/atom-types.h', '--include', 'linux/drivers/gpu/drm/amd/include/atomfirmware.h', '--include', 'linux/drivers/gpu/drm/amd/pm/powerplay/inc/smu11_driver_if.h', ''] 4 | # WORD_SIZE is: 8 5 | # POINTER_SIZE is: 8 6 | # LONGDOUBLE_SIZE is: 16 7 | # 8 | import ctypes 9 | 10 | 11 | class AsDictMixin: 12 | @classmethod 13 | def as_dict(cls, self): 14 | result = {} 15 | if not isinstance(self, AsDictMixin): 16 | # not a structure, assume it's already a python object 17 | return self 18 | if not hasattr(cls, "_fields_"): 19 | return result 20 | # sys.version_info >= (3, 5) 21 | # for (field, *_) in cls._fields_: # noqa 22 | for field_tuple in cls._fields_: # noqa 23 | field = field_tuple[0] 24 | if field.startswith('PADDING_'): 25 | continue 26 | value = getattr(self, field) 27 | type_ = type(value) 28 | if hasattr(value, "_length_") and hasattr(value, "_type_"): 29 | # array 30 | type_ = type_._type_ 31 | if hasattr(type_, 'as_dict'): 32 | value = [type_.as_dict(v) for v in value] 33 | else: 34 | value = [i for i in value] 35 | elif hasattr(value, "contents") and hasattr(value, "_type_"): 36 | # pointer 37 | try: 38 | if not hasattr(type_, "as_dict"): 39 | value = value.contents 40 | else: 41 | type_ = type_._type_ 42 | value = type_.as_dict(value.contents) 43 | except ValueError: 44 | # nullptr 45 | value = None 46 | elif isinstance(value, AsDictMixin): 47 | # other structure 48 | value = type_.as_dict(value) 49 | result[field] = value 50 | return result 51 | 52 | 53 | class Structure(ctypes.Structure, AsDictMixin): 54 | 55 | def __init__(self, *args, **kwds): 56 | # We don't want to use positional arguments fill PADDING_* fields 57 | 58 | args = dict(zip(self.__class__._field_names_(), args)) 59 | args.update(kwds) 60 | super(Structure, self).__init__(**args) 61 | 62 | @classmethod 63 | def _field_names_(cls): 64 | if hasattr(cls, '_fields_'): 65 | return (f[0] for f in cls._fields_ if not f[0].startswith('PADDING')) 66 | else: 67 | return () 68 | 69 | @classmethod 70 | def get_type(cls, field): 71 | for f in cls._fields_: 72 | if f[0] == field: 73 | return f[1] 74 | return None 75 | 76 | @classmethod 77 | def bind(cls, bound_fields): 78 | fields = {} 79 | for name, type_ in cls._fields_: 80 | if hasattr(type_, "restype"): 81 | if name in bound_fields: 82 | if bound_fields[name] is None: 83 | fields[name] = type_() 84 | else: 85 | # use a closure to capture the callback from the loop scope 86 | fields[name] = ( 87 | type_((lambda callback: lambda *args: callback(*args))( 88 | bound_fields[name])) 89 | ) 90 | del bound_fields[name] 91 | else: 92 | # default callback implementation (does nothing) 93 | try: 94 | default_ = type_(0).restype().value 95 | except TypeError: 96 | default_ = None 97 | fields[name] = type_(( 98 | lambda default_: lambda *args: default_)(default_)) 99 | else: 100 | # not a callback function, use default initialization 101 | if name in bound_fields: 102 | fields[name] = bound_fields[name] 103 | del bound_fields[name] 104 | else: 105 | fields[name] = type_() 106 | if len(bound_fields) != 0: 107 | raise ValueError( 108 | "Cannot bind the following unknown callback(s) {}.{}".format( 109 | cls.__name__, bound_fields.keys() 110 | )) 111 | return cls(**fields) 112 | 113 | 114 | class Union(ctypes.Union, AsDictMixin): 115 | pass 116 | 117 | 118 | 119 | 120 | 121 | _VEGA20_PPTABLE_H_ = True # macro 122 | ATOM_VEGA20_PP_THERMALCONTROLLER_NONE = 0 # macro 123 | ATOM_VEGA20_PP_THERMALCONTROLLER_VEGA20 = 26 # macro 124 | ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY = 0x1 # macro 125 | ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE = 0x2 # macro 126 | ATOM_VEGA20_PP_PLATFORM_CAP_HARDWAREDC = 0x4 # macro 127 | ATOM_VEGA20_PP_PLATFORM_CAP_BACO = 0x8 # macro 128 | ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO = 0x10 # macro 129 | ATOM_VEGA20_PP_PLATFORM_CAP_ENABLESHADOWPSTATE = 0x20 # macro 130 | ATOM_VEGA20_TABLE_REVISION_VEGA20 = 11 # macro 131 | ATOM_VEGA20_ODFEATURE_MAX_COUNT = 32 # macro 132 | ATOM_VEGA20_ODSETTING_MAX_COUNT = 32 # macro 133 | ATOM_VEGA20_PPCLOCK_MAX_COUNT = 16 # macro 134 | 135 | # values for enumeration 'ATOM_VEGA20_ODFEATURE_ID' 136 | ATOM_VEGA20_ODFEATURE_ID__enumvalues = { 137 | 0: 'ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS', 138 | 1: 'ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE', 139 | 2: 'ATOM_VEGA20_ODFEATURE_UCLK_MAX', 140 | 3: 'ATOM_VEGA20_ODFEATURE_POWER_LIMIT', 141 | 4: 'ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT', 142 | 5: 'ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN', 143 | 6: 'ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN', 144 | 7: 'ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM', 145 | 8: 'ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE', 146 | 9: 'ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL', 147 | 10: 'ATOM_VEGA20_ODFEATURE_COUNT', 148 | } 149 | ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS = 0 150 | ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE = 1 151 | ATOM_VEGA20_ODFEATURE_UCLK_MAX = 2 152 | ATOM_VEGA20_ODFEATURE_POWER_LIMIT = 3 153 | ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT = 4 154 | ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN = 5 155 | ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN = 6 156 | ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM = 7 157 | ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE = 8 158 | ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL = 9 159 | ATOM_VEGA20_ODFEATURE_COUNT = 10 160 | ATOM_VEGA20_ODFEATURE_ID = ctypes.c_uint32 # enum 161 | 162 | # values for enumeration 'ATOM_VEGA20_ODSETTING_ID' 163 | ATOM_VEGA20_ODSETTING_ID__enumvalues = { 164 | 0: 'ATOM_VEGA20_ODSETTING_GFXCLKFMAX', 165 | 1: 'ATOM_VEGA20_ODSETTING_GFXCLKFMIN', 166 | 2: 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1', 167 | 3: 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1', 168 | 4: 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2', 169 | 5: 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2', 170 | 6: 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3', 171 | 7: 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3', 172 | 8: 'ATOM_VEGA20_ODSETTING_UCLKFMAX', 173 | 9: 'ATOM_VEGA20_ODSETTING_POWERPERCENTAGE', 174 | 10: 'ATOM_VEGA20_ODSETTING_FANRPMMIN', 175 | 11: 'ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT', 176 | 12: 'ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE', 177 | 13: 'ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX', 178 | 14: 'ATOM_VEGA20_ODSETTING_COUNT', 179 | } 180 | ATOM_VEGA20_ODSETTING_GFXCLKFMAX = 0 181 | ATOM_VEGA20_ODSETTING_GFXCLKFMIN = 1 182 | ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1 = 2 183 | ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1 = 3 184 | ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2 = 4 185 | ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2 = 5 186 | ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3 = 6 187 | ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3 = 7 188 | ATOM_VEGA20_ODSETTING_UCLKFMAX = 8 189 | ATOM_VEGA20_ODSETTING_POWERPERCENTAGE = 9 190 | ATOM_VEGA20_ODSETTING_FANRPMMIN = 10 191 | ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT = 11 192 | ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE = 12 193 | ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX = 13 194 | ATOM_VEGA20_ODSETTING_COUNT = 14 195 | ATOM_VEGA20_ODSETTING_ID = ctypes.c_uint32 # enum 196 | class struct__ATOM_VEGA20_OVERDRIVE8_RECORD(Structure): 197 | pass 198 | 199 | struct__ATOM_VEGA20_OVERDRIVE8_RECORD._pack_ = 1 # source:False 200 | struct__ATOM_VEGA20_OVERDRIVE8_RECORD._fields_ = [ 201 | ('ucODTableRevision', ctypes.c_ubyte), 202 | ('ODFeatureCount', ctypes.c_uint32), 203 | ('ODFeatureCapabilities', ctypes.c_ubyte * 32), 204 | ('ODSettingCount', ctypes.c_uint32), 205 | ('ODSettingsMax', ctypes.c_uint32 * 32), 206 | ('ODSettingsMin', ctypes.c_uint32 * 32), 207 | ] 208 | 209 | ATOM_VEGA20_OVERDRIVE8_RECORD = struct__ATOM_VEGA20_OVERDRIVE8_RECORD 210 | 211 | # values for enumeration 'ATOM_VEGA20_PPCLOCK_ID' 212 | ATOM_VEGA20_PPCLOCK_ID__enumvalues = { 213 | 0: 'ATOM_VEGA20_PPCLOCK_GFXCLK', 214 | 1: 'ATOM_VEGA20_PPCLOCK_VCLK', 215 | 2: 'ATOM_VEGA20_PPCLOCK_DCLK', 216 | 3: 'ATOM_VEGA20_PPCLOCK_ECLK', 217 | 4: 'ATOM_VEGA20_PPCLOCK_SOCCLK', 218 | 5: 'ATOM_VEGA20_PPCLOCK_UCLK', 219 | 6: 'ATOM_VEGA20_PPCLOCK_FCLK', 220 | 7: 'ATOM_VEGA20_PPCLOCK_DCEFCLK', 221 | 8: 'ATOM_VEGA20_PPCLOCK_DISPCLK', 222 | 9: 'ATOM_VEGA20_PPCLOCK_PIXCLK', 223 | 10: 'ATOM_VEGA20_PPCLOCK_PHYCLK', 224 | 11: 'ATOM_VEGA20_PPCLOCK_COUNT', 225 | } 226 | ATOM_VEGA20_PPCLOCK_GFXCLK = 0 227 | ATOM_VEGA20_PPCLOCK_VCLK = 1 228 | ATOM_VEGA20_PPCLOCK_DCLK = 2 229 | ATOM_VEGA20_PPCLOCK_ECLK = 3 230 | ATOM_VEGA20_PPCLOCK_SOCCLK = 4 231 | ATOM_VEGA20_PPCLOCK_UCLK = 5 232 | ATOM_VEGA20_PPCLOCK_FCLK = 6 233 | ATOM_VEGA20_PPCLOCK_DCEFCLK = 7 234 | ATOM_VEGA20_PPCLOCK_DISPCLK = 8 235 | ATOM_VEGA20_PPCLOCK_PIXCLK = 9 236 | ATOM_VEGA20_PPCLOCK_PHYCLK = 10 237 | ATOM_VEGA20_PPCLOCK_COUNT = 11 238 | ATOM_VEGA20_PPCLOCK_ID = ctypes.c_uint32 # enum 239 | class struct__ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD(Structure): 240 | pass 241 | 242 | struct__ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD._pack_ = 1 # source:False 243 | struct__ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD._fields_ = [ 244 | ('ucTableRevision', ctypes.c_ubyte), 245 | ('PowerSavingClockCount', ctypes.c_uint32), 246 | ('PowerSavingClockMax', ctypes.c_uint32 * 16), 247 | ('PowerSavingClockMin', ctypes.c_uint32 * 16), 248 | ] 249 | 250 | ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD = struct__ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD 251 | class struct__ATOM_VEGA20_POWERPLAYTABLE(Structure): 252 | pass 253 | 254 | class struct_atom_common_table_header(Structure): 255 | pass 256 | 257 | struct_atom_common_table_header._pack_ = 1 # source:False 258 | struct_atom_common_table_header._fields_ = [ 259 | ('structuresize', ctypes.c_uint16), 260 | ('format_revision', ctypes.c_ubyte), 261 | ('content_revision', ctypes.c_ubyte), 262 | ] 263 | 264 | class struct_PPTable_t(Structure): 265 | pass 266 | 267 | class struct_DpmDescriptor_t(Structure): 268 | pass 269 | 270 | class struct_LinearInt_t(Structure): 271 | pass 272 | 273 | struct_LinearInt_t._pack_ = 1 # source:False 274 | struct_LinearInt_t._fields_ = [ 275 | ('m', ctypes.c_uint32), 276 | ('b', ctypes.c_uint32), 277 | ] 278 | 279 | class struct_QuadraticInt_t(Structure): 280 | pass 281 | 282 | struct_QuadraticInt_t._pack_ = 1 # source:False 283 | struct_QuadraticInt_t._fields_ = [ 284 | ('a', ctypes.c_uint32), 285 | ('b', ctypes.c_uint32), 286 | ('c', ctypes.c_uint32), 287 | ] 288 | 289 | struct_DpmDescriptor_t._pack_ = 1 # source:False 290 | struct_DpmDescriptor_t._fields_ = [ 291 | ('VoltageMode', ctypes.c_ubyte), 292 | ('SnapToDiscrete', ctypes.c_ubyte), 293 | ('NumDiscreteLevels', ctypes.c_ubyte), 294 | ('padding', ctypes.c_ubyte), 295 | ('ConversionToAvfsClk', struct_LinearInt_t), 296 | ('SsCurve', struct_QuadraticInt_t), 297 | ] 298 | 299 | class struct_DroopInt_t(Structure): 300 | pass 301 | 302 | struct_DroopInt_t._pack_ = 1 # source:False 303 | struct_DroopInt_t._fields_ = [ 304 | ('a', ctypes.c_uint32), 305 | ('b', ctypes.c_uint32), 306 | ('c', ctypes.c_uint32), 307 | ] 308 | 309 | class struct_I2cControllerConfig_t(Structure): 310 | pass 311 | 312 | struct_I2cControllerConfig_t._pack_ = 1 # source:False 313 | struct_I2cControllerConfig_t._fields_ = [ 314 | ('Enabled', ctypes.c_uint32), 315 | ('SlaveAddress', ctypes.c_uint32), 316 | ('ControllerPort', ctypes.c_uint32), 317 | ('ControllerName', ctypes.c_uint32), 318 | ('ThermalThrottler', ctypes.c_uint32), 319 | ('I2cProtocol', ctypes.c_uint32), 320 | ('I2cSpeed', ctypes.c_uint32), 321 | ] 322 | 323 | struct_PPTable_t._pack_ = 1 # source:False 324 | struct_PPTable_t._fields_ = [ 325 | ('Version', ctypes.c_uint32), 326 | ('FeaturesToRun', ctypes.c_uint32 * 2), 327 | ('SocketPowerLimitAc0', ctypes.c_uint16), 328 | ('SocketPowerLimitAc0Tau', ctypes.c_uint16), 329 | ('SocketPowerLimitAc1', ctypes.c_uint16), 330 | ('SocketPowerLimitAc1Tau', ctypes.c_uint16), 331 | ('SocketPowerLimitAc2', ctypes.c_uint16), 332 | ('SocketPowerLimitAc2Tau', ctypes.c_uint16), 333 | ('SocketPowerLimitAc3', ctypes.c_uint16), 334 | ('SocketPowerLimitAc3Tau', ctypes.c_uint16), 335 | ('SocketPowerLimitDc', ctypes.c_uint16), 336 | ('SocketPowerLimitDcTau', ctypes.c_uint16), 337 | ('TdcLimitSoc', ctypes.c_uint16), 338 | ('TdcLimitSocTau', ctypes.c_uint16), 339 | ('TdcLimitGfx', ctypes.c_uint16), 340 | ('TdcLimitGfxTau', ctypes.c_uint16), 341 | ('TedgeLimit', ctypes.c_uint16), 342 | ('ThotspotLimit', ctypes.c_uint16), 343 | ('ThbmLimit', ctypes.c_uint16), 344 | ('Tvr_gfxLimit', ctypes.c_uint16), 345 | ('Tvr_memLimit', ctypes.c_uint16), 346 | ('Tliquid1Limit', ctypes.c_uint16), 347 | ('Tliquid2Limit', ctypes.c_uint16), 348 | ('TplxLimit', ctypes.c_uint16), 349 | ('FitLimit', ctypes.c_uint32), 350 | ('PpmPowerLimit', ctypes.c_uint16), 351 | ('PpmTemperatureThreshold', ctypes.c_uint16), 352 | ('MemoryOnPackage', ctypes.c_ubyte), 353 | ('padding8_limits', ctypes.c_ubyte), 354 | ('Tvr_SocLimit', ctypes.c_uint16), 355 | ('UlvVoltageOffsetSoc', ctypes.c_uint16), 356 | ('UlvVoltageOffsetGfx', ctypes.c_uint16), 357 | ('UlvSmnclkDid', ctypes.c_ubyte), 358 | ('UlvMp1clkDid', ctypes.c_ubyte), 359 | ('UlvGfxclkBypass', ctypes.c_ubyte), 360 | ('Padding234', ctypes.c_ubyte), 361 | ('MinVoltageGfx', ctypes.c_uint16), 362 | ('MinVoltageSoc', ctypes.c_uint16), 363 | ('MaxVoltageGfx', ctypes.c_uint16), 364 | ('MaxVoltageSoc', ctypes.c_uint16), 365 | ('LoadLineResistanceGfx', ctypes.c_uint16), 366 | ('LoadLineResistanceSoc', ctypes.c_uint16), 367 | ('DpmDescriptor', struct_DpmDescriptor_t * 11), 368 | ('FreqTableGfx', ctypes.c_uint16 * 16), 369 | ('FreqTableVclk', ctypes.c_uint16 * 8), 370 | ('FreqTableDclk', ctypes.c_uint16 * 8), 371 | ('FreqTableEclk', ctypes.c_uint16 * 8), 372 | ('FreqTableSocclk', ctypes.c_uint16 * 8), 373 | ('FreqTableUclk', ctypes.c_uint16 * 4), 374 | ('FreqTableFclk', ctypes.c_uint16 * 8), 375 | ('FreqTableDcefclk', ctypes.c_uint16 * 8), 376 | ('FreqTableDispclk', ctypes.c_uint16 * 8), 377 | ('FreqTablePixclk', ctypes.c_uint16 * 8), 378 | ('FreqTablePhyclk', ctypes.c_uint16 * 8), 379 | ('DcModeMaxFreq', ctypes.c_uint16 * 11), 380 | ('Padding8_Clks', ctypes.c_uint16), 381 | ('Mp0clkFreq', ctypes.c_uint16 * 2), 382 | ('Mp0DpmVoltage', ctypes.c_uint16 * 2), 383 | ('GfxclkFidle', ctypes.c_uint16), 384 | ('GfxclkSlewRate', ctypes.c_uint16), 385 | ('CksEnableFreq', ctypes.c_uint16), 386 | ('Padding789', ctypes.c_uint16), 387 | ('CksVoltageOffset', struct_QuadraticInt_t), 388 | ('Padding567', ctypes.c_ubyte * 4), 389 | ('GfxclkDsMaxFreq', ctypes.c_uint16), 390 | ('GfxclkSource', ctypes.c_ubyte), 391 | ('Padding456', ctypes.c_ubyte), 392 | ('LowestUclkReservedForUlv', ctypes.c_ubyte), 393 | ('Padding8_Uclk', ctypes.c_ubyte * 3), 394 | ('PcieGenSpeed', ctypes.c_ubyte * 2), 395 | ('PcieLaneCount', ctypes.c_ubyte * 2), 396 | ('LclkFreq', ctypes.c_uint16 * 2), 397 | ('EnableTdpm', ctypes.c_uint16), 398 | ('TdpmHighHystTemperature', ctypes.c_uint16), 399 | ('TdpmLowHystTemperature', ctypes.c_uint16), 400 | ('GfxclkFreqHighTempLimit', ctypes.c_uint16), 401 | ('FanStopTemp', ctypes.c_uint16), 402 | ('FanStartTemp', ctypes.c_uint16), 403 | ('FanGainEdge', ctypes.c_uint16), 404 | ('FanGainHotspot', ctypes.c_uint16), 405 | ('FanGainLiquid', ctypes.c_uint16), 406 | ('FanGainVrGfx', ctypes.c_uint16), 407 | ('FanGainVrSoc', ctypes.c_uint16), 408 | ('FanGainPlx', ctypes.c_uint16), 409 | ('FanGainHbm', ctypes.c_uint16), 410 | ('FanPwmMin', ctypes.c_uint16), 411 | ('FanAcousticLimitRpm', ctypes.c_uint16), 412 | ('FanThrottlingRpm', ctypes.c_uint16), 413 | ('FanMaximumRpm', ctypes.c_uint16), 414 | ('FanTargetTemperature', ctypes.c_uint16), 415 | ('FanTargetGfxclk', ctypes.c_uint16), 416 | ('FanZeroRpmEnable', ctypes.c_ubyte), 417 | ('FanTachEdgePerRev', ctypes.c_ubyte), 418 | ('FuzzyFan_ErrorSetDelta', ctypes.c_int16), 419 | ('FuzzyFan_ErrorRateSetDelta', ctypes.c_int16), 420 | ('FuzzyFan_PwmSetDelta', ctypes.c_int16), 421 | ('FuzzyFan_Reserved', ctypes.c_uint16), 422 | ('OverrideAvfsGb', ctypes.c_ubyte * 2), 423 | ('Padding8_Avfs', ctypes.c_ubyte * 2), 424 | ('qAvfsGb', struct_QuadraticInt_t * 2), 425 | ('dBtcGbGfxCksOn', struct_DroopInt_t), 426 | ('dBtcGbGfxCksOff', struct_DroopInt_t), 427 | ('dBtcGbGfxAfll', struct_DroopInt_t), 428 | ('dBtcGbSoc', struct_DroopInt_t), 429 | ('qAgingGb', struct_LinearInt_t * 2), 430 | ('qStaticVoltageOffset', struct_QuadraticInt_t * 2), 431 | ('DcTol', ctypes.c_uint16 * 2), 432 | ('DcBtcEnabled', ctypes.c_ubyte * 2), 433 | ('Padding8_GfxBtc', ctypes.c_ubyte * 2), 434 | ('DcBtcMin', ctypes.c_int16 * 2), 435 | ('DcBtcMax', ctypes.c_uint16 * 2), 436 | ('XgmiLinkSpeed', ctypes.c_ubyte * 2), 437 | ('XgmiLinkWidth', ctypes.c_ubyte * 2), 438 | ('XgmiFclkFreq', ctypes.c_uint16 * 2), 439 | ('XgmiUclkFreq', ctypes.c_uint16 * 2), 440 | ('XgmiSocclkFreq', ctypes.c_uint16 * 2), 441 | ('XgmiSocVoltage', ctypes.c_uint16 * 2), 442 | ('DebugOverrides', ctypes.c_uint32), 443 | ('ReservedEquation0', struct_QuadraticInt_t), 444 | ('ReservedEquation1', struct_QuadraticInt_t), 445 | ('ReservedEquation2', struct_QuadraticInt_t), 446 | ('ReservedEquation3', struct_QuadraticInt_t), 447 | ('MinVoltageUlvGfx', ctypes.c_uint16), 448 | ('MinVoltageUlvSoc', ctypes.c_uint16), 449 | ('MGpuFanBoostLimitRpm', ctypes.c_uint16), 450 | ('padding16_Fan', ctypes.c_uint16), 451 | ('FanGainVrMem0', ctypes.c_uint16), 452 | ('FanGainVrMem1', ctypes.c_uint16), 453 | ('DcBtcGb', ctypes.c_uint16 * 2), 454 | ('Reserved', ctypes.c_uint32 * 11), 455 | ('Padding32', ctypes.c_uint32 * 3), 456 | ('MaxVoltageStepGfx', ctypes.c_uint16), 457 | ('MaxVoltageStepSoc', ctypes.c_uint16), 458 | ('VddGfxVrMapping', ctypes.c_ubyte), 459 | ('VddSocVrMapping', ctypes.c_ubyte), 460 | ('VddMem0VrMapping', ctypes.c_ubyte), 461 | ('VddMem1VrMapping', ctypes.c_ubyte), 462 | ('GfxUlvPhaseSheddingMask', ctypes.c_ubyte), 463 | ('SocUlvPhaseSheddingMask', ctypes.c_ubyte), 464 | ('ExternalSensorPresent', ctypes.c_ubyte), 465 | ('Padding8_V', ctypes.c_ubyte), 466 | ('GfxMaxCurrent', ctypes.c_uint16), 467 | ('GfxOffset', ctypes.c_byte), 468 | ('Padding_TelemetryGfx', ctypes.c_ubyte), 469 | ('SocMaxCurrent', ctypes.c_uint16), 470 | ('SocOffset', ctypes.c_byte), 471 | ('Padding_TelemetrySoc', ctypes.c_ubyte), 472 | ('Mem0MaxCurrent', ctypes.c_uint16), 473 | ('Mem0Offset', ctypes.c_byte), 474 | ('Padding_TelemetryMem0', ctypes.c_ubyte), 475 | ('Mem1MaxCurrent', ctypes.c_uint16), 476 | ('Mem1Offset', ctypes.c_byte), 477 | ('Padding_TelemetryMem1', ctypes.c_ubyte), 478 | ('AcDcGpio', ctypes.c_ubyte), 479 | ('AcDcPolarity', ctypes.c_ubyte), 480 | ('VR0HotGpio', ctypes.c_ubyte), 481 | ('VR0HotPolarity', ctypes.c_ubyte), 482 | ('VR1HotGpio', ctypes.c_ubyte), 483 | ('VR1HotPolarity', ctypes.c_ubyte), 484 | ('Padding1', ctypes.c_ubyte), 485 | ('Padding2', ctypes.c_ubyte), 486 | ('LedPin0', ctypes.c_ubyte), 487 | ('LedPin1', ctypes.c_ubyte), 488 | ('LedPin2', ctypes.c_ubyte), 489 | ('padding8_4', ctypes.c_ubyte), 490 | ('PllGfxclkSpreadEnabled', ctypes.c_ubyte), 491 | ('PllGfxclkSpreadPercent', ctypes.c_ubyte), 492 | ('PllGfxclkSpreadFreq', ctypes.c_uint16), 493 | ('UclkSpreadEnabled', ctypes.c_ubyte), 494 | ('UclkSpreadPercent', ctypes.c_ubyte), 495 | ('UclkSpreadFreq', ctypes.c_uint16), 496 | ('FclkSpreadEnabled', ctypes.c_ubyte), 497 | ('FclkSpreadPercent', ctypes.c_ubyte), 498 | ('FclkSpreadFreq', ctypes.c_uint16), 499 | ('FllGfxclkSpreadEnabled', ctypes.c_ubyte), 500 | ('FllGfxclkSpreadPercent', ctypes.c_ubyte), 501 | ('FllGfxclkSpreadFreq', ctypes.c_uint16), 502 | ('I2cControllers', struct_I2cControllerConfig_t * 7), 503 | ('BoardReserved', ctypes.c_uint32 * 10), 504 | ('MmHubPadding', ctypes.c_uint32 * 8), 505 | ] 506 | 507 | struct__ATOM_VEGA20_POWERPLAYTABLE._pack_ = 1 # source:False 508 | struct__ATOM_VEGA20_POWERPLAYTABLE._fields_ = [ 509 | ('sHeader', struct_atom_common_table_header), 510 | ('ucTableRevision', ctypes.c_ubyte), 511 | ('usTableSize', ctypes.c_uint16), 512 | ('ulGoldenPPID', ctypes.c_uint32), 513 | ('ulGoldenRevision', ctypes.c_uint32), 514 | ('usFormatID', ctypes.c_uint16), 515 | ('ulPlatformCaps', ctypes.c_uint32), 516 | ('ucThermalControllerType', ctypes.c_ubyte), 517 | ('usSmallPowerLimit1', ctypes.c_uint16), 518 | ('usSmallPowerLimit2', ctypes.c_uint16), 519 | ('usBoostPowerLimit', ctypes.c_uint16), 520 | ('usODTurboPowerLimit', ctypes.c_uint16), 521 | ('usODPowerSavePowerLimit', ctypes.c_uint16), 522 | ('usSoftwareShutdownTemp', ctypes.c_uint16), 523 | ('PowerSavingClockTable', ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD), 524 | ('OverDrive8Table', ATOM_VEGA20_OVERDRIVE8_RECORD), 525 | ('usReserve', ctypes.c_uint16 * 5), 526 | ('smcPPTable', struct_PPTable_t), 527 | ] 528 | 529 | ATOM_Vega20_POWERPLAYTABLE = struct__ATOM_VEGA20_POWERPLAYTABLE 530 | __all__ = \ 531 | ['ATOM_VEGA20_ODFEATURE_COUNT', 532 | 'ATOM_VEGA20_ODFEATURE_FAN_ACOUSTIC_LIMIT', 533 | 'ATOM_VEGA20_ODFEATURE_FAN_SPEED_MIN', 534 | 'ATOM_VEGA20_ODFEATURE_FAN_ZERO_RPM_CONTROL', 535 | 'ATOM_VEGA20_ODFEATURE_GFXCLK_CURVE', 536 | 'ATOM_VEGA20_ODFEATURE_GFXCLK_LIMITS', 'ATOM_VEGA20_ODFEATURE_ID', 537 | 'ATOM_VEGA20_ODFEATURE_MAX_COUNT', 538 | 'ATOM_VEGA20_ODFEATURE_MEMORY_TIMING_TUNE', 539 | 'ATOM_VEGA20_ODFEATURE_POWER_LIMIT', 540 | 'ATOM_VEGA20_ODFEATURE_TEMPERATURE_FAN', 541 | 'ATOM_VEGA20_ODFEATURE_TEMPERATURE_SYSTEM', 542 | 'ATOM_VEGA20_ODFEATURE_UCLK_MAX', 'ATOM_VEGA20_ODSETTING_COUNT', 543 | 'ATOM_VEGA20_ODSETTING_FANRPMACOUSTICLIMIT', 544 | 'ATOM_VEGA20_ODSETTING_FANRPMMIN', 545 | 'ATOM_VEGA20_ODSETTING_FANTARGETTEMPERATURE', 546 | 'ATOM_VEGA20_ODSETTING_GFXCLKFMAX', 547 | 'ATOM_VEGA20_ODSETTING_GFXCLKFMIN', 'ATOM_VEGA20_ODSETTING_ID', 548 | 'ATOM_VEGA20_ODSETTING_MAX_COUNT', 549 | 'ATOM_VEGA20_ODSETTING_OPERATINGTEMPMAX', 550 | 'ATOM_VEGA20_ODSETTING_POWERPERCENTAGE', 551 | 'ATOM_VEGA20_ODSETTING_UCLKFMAX', 552 | 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P1', 553 | 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P2', 554 | 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEFREQ_P3', 555 | 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P1', 556 | 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P2', 557 | 'ATOM_VEGA20_ODSETTING_VDDGFXCURVEVOLTAGEOFFSET_P3', 558 | 'ATOM_VEGA20_OVERDRIVE8_RECORD', 559 | 'ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD', 560 | 'ATOM_VEGA20_PPCLOCK_COUNT', 'ATOM_VEGA20_PPCLOCK_DCEFCLK', 561 | 'ATOM_VEGA20_PPCLOCK_DCLK', 'ATOM_VEGA20_PPCLOCK_DISPCLK', 562 | 'ATOM_VEGA20_PPCLOCK_ECLK', 'ATOM_VEGA20_PPCLOCK_FCLK', 563 | 'ATOM_VEGA20_PPCLOCK_GFXCLK', 'ATOM_VEGA20_PPCLOCK_ID', 564 | 'ATOM_VEGA20_PPCLOCK_MAX_COUNT', 'ATOM_VEGA20_PPCLOCK_PHYCLK', 565 | 'ATOM_VEGA20_PPCLOCK_PIXCLK', 'ATOM_VEGA20_PPCLOCK_SOCCLK', 566 | 'ATOM_VEGA20_PPCLOCK_UCLK', 'ATOM_VEGA20_PPCLOCK_VCLK', 567 | 'ATOM_VEGA20_PP_PLATFORM_CAP_BACO', 568 | 'ATOM_VEGA20_PP_PLATFORM_CAP_BAMACO', 569 | 'ATOM_VEGA20_PP_PLATFORM_CAP_ENABLESHADOWPSTATE', 570 | 'ATOM_VEGA20_PP_PLATFORM_CAP_HARDWAREDC', 571 | 'ATOM_VEGA20_PP_PLATFORM_CAP_POWERPLAY', 572 | 'ATOM_VEGA20_PP_PLATFORM_CAP_SBIOSPOWERSOURCE', 573 | 'ATOM_VEGA20_PP_THERMALCONTROLLER_NONE', 574 | 'ATOM_VEGA20_PP_THERMALCONTROLLER_VEGA20', 575 | 'ATOM_VEGA20_TABLE_REVISION_VEGA20', 'ATOM_Vega20_POWERPLAYTABLE', 576 | '_VEGA20_PPTABLE_H_', 'struct_DpmDescriptor_t', 577 | 'struct_DroopInt_t', 'struct_I2cControllerConfig_t', 578 | 'struct_LinearInt_t', 'struct_PPTable_t', 'struct_QuadraticInt_t', 579 | 'struct__ATOM_VEGA20_OVERDRIVE8_RECORD', 580 | 'struct__ATOM_VEGA20_POWERPLAYTABLE', 581 | 'struct__ATOM_VEGA20_POWER_SAVING_CLOCK_RECORD', 582 | 'struct_atom_common_table_header'] 583 | -------------------------------------------------------------------------------- /src/upp/upp.py: -------------------------------------------------------------------------------- 1 | # To run without installing, relative imports must match the module imports, 2 | # which is satisfied when in 'src' directory: python3 -m upp.upp --help 3 | 4 | import click 5 | import tempfile 6 | from upp import decode 7 | import importlib.metadata 8 | import os.path 9 | import sys 10 | 11 | CONTEXT_SETTINGS = dict(help_option_names=['-h', '--help']) 12 | REG_CTRL_CLASS = 'Control\\Class\\{4d36e968-e325-11ce-bfc1-08002be10318}' 13 | REG_KEY = 'ControlSet001\\' + REG_CTRL_CLASS 14 | REG_KEY_VAL = 'PP_PhmSoftPowerPlayTable' 15 | REG_HEADER = 'Windows Registry Editor Version 5.00' + 2 * '\r\n' + \ 16 | '[HKEY_LOCAL_MACHINE\\SYSTEM\\CurrentControlSet\\' + \ 17 | REG_CTRL_CLASS + '\\0000]\r\n' 18 | 19 | 20 | def _normalize_var_path(var_path_str): 21 | var_path_list = var_path_str.strip('/').split('/') 22 | normalized_var_path_list = [ 23 | int(item) if item.isdigit() else item for item in var_path_list] 24 | return normalized_var_path_list 25 | 26 | 27 | def _is_int_or_float(value): 28 | if value.isdigit(): 29 | return True 30 | try: 31 | float(value) 32 | return True 33 | except ValueError: 34 | pass 35 | return False 36 | 37 | 38 | def _validate_set_pair(set_pair): 39 | valid = False 40 | if '=' in set_pair and _is_int_or_float(set_pair.split('=')[-1]): 41 | return set_pair.split('=') 42 | else: 43 | print("ERROR: Invalid variable assignment '{}'. ".format(set_pair), 44 | "Assignment must be specified in = ", 45 | "format. For example: /PowerTuneTable/TDP=75") 46 | return None, None 47 | 48 | 49 | def _get_pp_data_from_registry(reg_file_path): 50 | reg_path = 'HKLM\\SYSTEM\\' + REG_KEY + ':' + REG_KEY_VAL 51 | try: 52 | from Registry import Registry 53 | except ImportError as e: 54 | print('ERROR: -f/--from-registry option requires python-registry', 55 | 'package, consider installing it with PIP.') 56 | sys.exit(-2) 57 | try: 58 | reg = Registry.Registry(reg_file_path) 59 | keys = reg.open(REG_KEY) 60 | except Exception as e: 61 | print('ERROR: Can not access', REG_KEY, 'in', reg_file_path) 62 | print(e) 63 | return None 64 | found_data = False 65 | for key in keys.subkeys(): 66 | index = key.name() 67 | key_path = REG_KEY + '\\' + index 68 | if index.startswith('0'): 69 | try: 70 | data_type = key.value(REG_KEY_VAL).value_type_str() 71 | registry_data = key.value(REG_KEY_VAL).raw_data() 72 | print('Found', data_type, 'type value', REG_KEY_VAL, 73 | 'in', key_path) 74 | if found_data: 75 | print('WARNING: Multiple PP tables found in the registry,', 76 | 'only using data from last table found!') 77 | found_data = True 78 | tmpf_prefix = 'registry_device_' + index + '_pp_table_' 79 | tmp_pp_file = tempfile.NamedTemporaryFile(prefix=tmpf_prefix, 80 | delete=False) 81 | decode._write_binary_file(tmp_pp_file.name, registry_data) 82 | print('Saved registry PP table', 'data to', tmp_pp_file.name) 83 | tmp_pp_file.close() 84 | except Registry.RegistryValueNotFoundException: 85 | print("Can't find needed value", REG_KEY_VAL, 'in', key_path) 86 | 87 | return tmp_pp_file.name 88 | 89 | 90 | def _get_pp_data_from_mpt(mpt_filename): 91 | 92 | try: 93 | mpt_bytes = decode._read_binary_file(mpt_filename) 94 | except Exception as e: 95 | print('ERROR: Can not access', mpt_filename) 96 | print(e) 97 | sys.exit(-2) 98 | mpt_table_filename = mpt_filename + '.pp_table' 99 | print('Saving MPT PP table data to', mpt_table_filename) 100 | decode._write_binary_file(mpt_table_filename, mpt_bytes[0x100:]) 101 | 102 | return mpt_table_filename 103 | 104 | 105 | def _check_file_writeable(filename): 106 | if os.path.exists(filename): 107 | if os.path.isfile(filename): 108 | return os.access(filename, os.W_OK) 109 | else: 110 | return False 111 | pdir = os.path.dirname(filename) 112 | if not pdir: 113 | pdir = '.' 114 | return os.access(pdir, os.W_OK) 115 | 116 | 117 | def _write_pp_to_reg_file(filename, data, debug=False): 118 | if _check_file_writeable(filename): 119 | reg_string = REG_KEY_VAL[3:] + '"=hex:' + data.hex(',') 120 | reg_lines = [reg_string[i:i+75] for i in range(0, len(reg_string), 75)] 121 | reg_lines[0] = '"' + REG_KEY_VAL[:3] + reg_lines[0] 122 | formatted_reg_string = '\\\r\n '.join(reg_lines) 123 | reg_pp_data = REG_HEADER + formatted_reg_string + 2 * '\r\n' 124 | if debug: 125 | print(reg_pp_data) 126 | decode._write_binary_file(filename, reg_pp_data.encode('utf-16')) 127 | print('Written {} Soft PowerPlay bytes to {}'.format(len(data), 128 | filename)) 129 | else: 130 | print('Can not write to {}'.format(filename)) 131 | return 0 132 | 133 | 134 | def _load_variable_set(dump_filename): 135 | variable_set = [] 136 | with open(dump_filename, 'r') as file: 137 | keys = [] 138 | indent = 0 139 | prev_indent = 0 140 | lines = file.readlines() 141 | for line in lines: 142 | prev_indent = indent 143 | indent = (len(line) - len(line.lstrip()))//2 144 | if line.strip() == '': 145 | continue 146 | if indent == 0: 147 | keys.clear() 148 | elif indent <= prev_indent: 149 | keys = keys[0:indent] 150 | 151 | key, value = line.split(':') 152 | key = key.strip() 153 | value = value.strip() 154 | if len(value) > 0: 155 | value = value.split()[0] 156 | if key.find('Unused') == 0 or value.find('UNUSED') == 0: 157 | continue 158 | if len(keys) > 0 and key.find(keys[-1]) == 0: 159 | key = key.split(' ')[1] 160 | keys.append(key) 161 | if value != '': 162 | variable_set.append('{}={}'.format('/'.join(keys), value)) 163 | return variable_set 164 | 165 | 166 | @click.group(context_settings=CONTEXT_SETTINGS) 167 | @click.option('-p', '--pp-file', help='Input/output PP table binary file.', 168 | metavar='', 169 | default='/sys/class/drm/card0/device/pp_table') 170 | @click.option('-f', '--from-registry', 171 | help='Import PP_PhmSoftPowerPlayTable from Windows registry ' + 172 | '(overrides -p / --pp-file option).', 173 | metavar='') 174 | @click.option('-m', '--from-mpt', 175 | help='Import PowerPlay Table from More Power Tool ' + 176 | '(overrides --pp-file and --from-registry optios).', 177 | metavar='') 178 | @click.option('--debug/--no-debug', '-d/ ', default='False', 179 | help='Debug mode.') 180 | @click.pass_context 181 | def cli(ctx, debug, pp_file, from_registry, from_mpt): 182 | """UPP: Uplift Power Play 183 | 184 | A tool for parsing, dumping and modifying data in Radeon PowerPlay tables. 185 | 186 | UPP is able to parse and modify binary data structures of PowerPlay 187 | tables commonly found on certain AMD Radeon GPUs. Drivers on recent 188 | AMD GPUs allow PowerPlay tables to be dynamically modified on runtime, 189 | which may be known as "soft PowerPlay tables". On Linux, the PowerPlay 190 | table is by default found at: 191 | 192 | \b 193 | /sys/class/drm/card0/device/pp_table 194 | 195 | There are also two alternative ways of getting PowerPlay data that this 196 | tool supports: 197 | 198 | \b 199 | - By extracting PowerPlay table from Video ROM image (see extract command) 200 | - Import "Soft PowerPlay" table from Windows registry, directly from 201 | offline Windows/System32/config/SYSTEM file on disk, so it would work 202 | from Linux distro that has acces to mounted Windows partition 203 | (path to SYSTEM registry file is specified with --from-registry option) 204 | - Import "Soft PowerPlay" table from "More Powe Tool" MPT file 205 | (path to MPT file is specified with --from-mpt option) 206 | 207 | This tool currently supports parsing and modifying PowerPlay tables 208 | found on the following AMD GPU families: 209 | 210 | \b 211 | - Polaris 212 | - Vega 213 | - Radeon VII 214 | - Navi 10, 12, 14 215 | - Navi 21, 22, 23 216 | - Navi 3x (experimental) 217 | 218 | Note: iGPUs found in many recent AMD APUs are using completely different 219 | PowerPlay control methods, this tool does not support them. 220 | 221 | If you have bugs to report or features to request please check: 222 | 223 | github.com/sibradzic/upp 224 | """ 225 | ctx.ensure_object(dict) 226 | ctx.obj['DEBUG'] = debug 227 | ctx.obj['PPBINARY'] = pp_file 228 | ctx.obj['FROMREGISTRY'] = from_registry 229 | ctx.obj['FROMMPT'] = from_mpt 230 | 231 | 232 | @click.command(short_help='Show UPP version.') 233 | def version(): 234 | """Shows UPP version.""" 235 | version = importlib.metadata.version('upp') 236 | click.echo(version) 237 | 238 | 239 | @click.command(short_help='Dumps all PowerPlay parameters to console.') 240 | @click.option('--raw/--no-raw', '-r/ ', help='Show raw binary data.', 241 | default='False') 242 | @click.pass_context 243 | def dump(ctx, raw): 244 | """Dumps all PowerPlay data to console 245 | 246 | De-serializes PowerPlay binary data into a human-readable text output. 247 | For example: 248 | 249 | \b 250 | upp --pp-file=radeon.pp_table dump 251 | 252 | In standard mode all data will be dumped to console, where 253 | data tree hierarchy is indicated by indentation. 254 | 255 | In raw mode a table showing all hex and binary data, as well 256 | as variable names and values, will be dumped. 257 | """ 258 | debug = ctx.obj['DEBUG'] 259 | pp_file = ctx.obj['PPBINARY'] 260 | from_registry = ctx.obj['FROMREGISTRY'] 261 | from_mpt = ctx.obj['FROMMPT'] 262 | if from_registry: 263 | pp_file = _get_pp_data_from_registry(from_registry) 264 | if from_mpt: 265 | pp_file = _get_pp_data_from_mpt(from_mpt) 266 | decode.dump_pp_table(pp_file, rawdump=raw, debug=debug) 267 | return 0 268 | 269 | 270 | @click.command(short_help='Undumps all PowerPlay parameters to a binary' + 271 | 'PP Table file or a Registry') 272 | @click.option('-d', '--dump-filename', 273 | help='File path of dumped powerplay parameters.') 274 | @click.option('-t', '--to-registry', metavar='', 275 | help='Output to Windows registry .reg file.') 276 | @click.option('-w', '--write', is_flag=True, 277 | help='Write changes to PP binary.', default=False) 278 | @click.pass_context 279 | def undump(ctx, dump_filename, to_registry, write): 280 | """Undumps all PowerPlay data to pp file or registry 281 | 282 | Serializes previously dumped PowerPlay text to pp file or registry. 283 | For example: 284 | 285 | \b 286 | upp --pp-file=radeon.pp_table undump -d pp.dump --write 287 | 288 | """ 289 | variable_set = _load_variable_set(dump_filename) 290 | ctx.invoke(set, variable_path_set=variable_set, 291 | to_registry=to_registry, write=write) 292 | return 0 293 | 294 | 295 | @click.command(short_help='Extract PowerPlay table from Video BIOS ROM image.') 296 | @click.option('-r', '--video-rom', required=True, metavar='', 297 | help='Input Video ROM binary image file.') 298 | @click.pass_context 299 | def extract(ctx, video_rom): 300 | """Extracts PowerPlay data from full VBIOS ROM image 301 | 302 | The source video ROM binary must be specified with -r/--video-rom 303 | parameter, and extracted PowerPlay table will be saved into file 304 | specified with -p/--pp-file. For example: 305 | 306 | \b 307 | upp --pp-file=extracted.pp_table extract -r VIDEO.rom 308 | 309 | Default output file name will be an original ROM file name with an 310 | additional .pp_table extension. 311 | """ 312 | pp_file = ctx.obj['PPBINARY'] 313 | ctx.obj['ROMBINARY'] = video_rom 314 | # Override default, we don't want to extract any random VBIOS into sysfs 315 | if pp_file.endswith('device/pp_table'): 316 | pp_file = video_rom + '.pp_table' 317 | msg = "Extracting PP table from '{}' ROM image..." 318 | print(msg.format(video_rom)) 319 | if decode.extract_rom(video_rom, pp_file): 320 | print('Done') 321 | 322 | return 0 323 | 324 | 325 | @click.command(short_help='Inject PowerPlay table into Video BIOS ROM image.') 326 | @click.option('-i', '--input-rom', required=True, metavar='', 327 | help='Input Video ROM binary image file.') 328 | @click.option('-o', '--output-rom', required=False, metavar='', 329 | help='Output Video ROM binary image file.') 330 | @click.pass_context 331 | def inject(ctx, input_rom, output_rom): 332 | """Injects PowerPlay data from file into VBIOS ROM image 333 | 334 | The input video ROM binary must be specified with -i/--input-rom 335 | parameter, and the output ROM can be specified with an optional 336 | -o/--output-rom parameter. 337 | 338 | \b 339 | upp -p modded.pp_table inject -i original.rom -o modded.rom 340 | 341 | The output filename defaults to .modded. 342 | 343 | WARNING: Modified vROM image is probalby not going to work if flashed as 344 | is to your card, due to ROM signature checks on recent Radeon cards. 345 | Authors of this tool are in no way responsible for any damage that may 346 | happen to your expansive graphics card if you choose to flash the modified 347 | video ROM, you are doing it entierly on your own risk. 348 | """ 349 | pp_file = ctx.obj['PPBINARY'] 350 | if not output_rom: 351 | output_rom = input_rom + '.modded' 352 | msg = "Injecting {} PP table into {} ROM image..." 353 | print(msg.format(pp_file, input_rom)) 354 | if decode.inject_pp_table(input_rom, output_rom, pp_file): 355 | print('Saved modified vROM image as {}.'.format(output_rom)) 356 | 357 | return 0 358 | 359 | 360 | @click.command(short_help='Get current value of a PowerPlay parameter(s).') 361 | @click.argument('variable-path-set', nargs=-1, required=True) 362 | @click.pass_context 363 | def get(ctx, variable_path_set): 364 | """Retrieves current value of one or multiple PP parameters 365 | 366 | The parameter variable path must be specified in 367 | "/ notation", for example: 368 | 369 | \b 370 | upp get /FanTable/TargetTemperature /VddgfxLookupTable/7/Vdd 371 | 372 | The raw value of the parameter will be retrieved, 373 | decoded and displayed on console. 374 | Multiple PP parameters can be specified at the same time. 375 | """ 376 | debug = ctx.obj['DEBUG'] 377 | pp_file = ctx.obj['PPBINARY'] 378 | from_registry = ctx.obj['FROMREGISTRY'] 379 | if from_registry: 380 | pp_file = _get_pp_data_from_registry(from_registry) 381 | pp_bytes = decode._read_binary_file(pp_file) 382 | data = decode.select_pp_struct(pp_bytes, debug=debug) 383 | 384 | for set_pair_str in variable_path_set: 385 | var_path = _normalize_var_path(set_pair_str) 386 | res = decode.get_value(pp_file, var_path, data, debug=debug) 387 | if res: 388 | print('{:n}'.format(res['value'])) 389 | else: 390 | print('ERROR: Incorrect variable path:', set_pair_str) 391 | exit(2) 392 | 393 | return 0 394 | 395 | 396 | @click.command(short_help='Set value to PowerPlay parameter(s).') 397 | @click.argument('variable-path-set', nargs=-1, required=False) 398 | @click.option('-w', '--write', is_flag=True, 399 | help='Write changes to PP binary.', default=False) 400 | @click.option('-t', '--to-registry', metavar='', 401 | help='Output to Windows registry .reg file.') 402 | @click.option('-c', '--from-conf', metavar='', 403 | help='Input VARIABLE_PATH_SET from file.') 404 | @click.pass_context 405 | def set(ctx, variable_path_set, to_registry, write, from_conf): 406 | """Sets value to one or multiple PP parameters 407 | 408 | The parameter path and value must be specified in 409 | "/= notation", for example: 410 | 411 | \b 412 | upp set /PowerTuneTable/TDP=75 /SclkDependencyTable/7/Sclk=107000 413 | 414 | Multiple PP parameters can be set at the same time. 415 | The PP tables will not be changed unless additional 416 | --write option is set. 417 | 418 | It is possible to set parameters from a configuration file with one 419 | "/=" per line using -c/--from-conf instead of directly 420 | passing parameters from command line 421 | 422 | \b 423 | upp set --from-conf=card0.conf 424 | 425 | Optionally, if -t/--to-registry output is specified, an additional Windows 426 | registry format file with '.reg' extension will be generated, for example: 427 | 428 | \b 429 | upp set /PowerTuneTable/TDP=75 --to-registry=test 430 | 431 | will produce the file test.reg in the current working directory. 432 | """ 433 | debug = ctx.obj['DEBUG'] 434 | pp_file = ctx.obj['PPBINARY'] 435 | 436 | if from_conf is not None: 437 | if (len(variable_path_set) > 0): 438 | print("ERROR: VARIABLE_PATH_SET found when using -c/--from-conf.") 439 | exit(2) 440 | if not os.path.isfile(from_conf): 441 | print("ERROR: file {} not found.".format(from_conf)) 442 | exit(2) 443 | with open(from_conf, 'r') as config: 444 | variable_path_set = list(filter(''.__ne__, 445 | config.read().splitlines())) 446 | elif (len(variable_path_set) == 0): 447 | print("ERROR: no parameters given to set to pp table.") 448 | exit(2) 449 | 450 | set_pairs = [] 451 | for set_pair_str in variable_path_set: 452 | var, val = _validate_set_pair(set_pair_str) 453 | if var and val: 454 | var_path = _normalize_var_path(var) 455 | res = decode.get_value(pp_file, var_path) 456 | if res: 457 | if res["type"] == 'f': 458 | set_pairs += [var_path + [float(val)]] 459 | else: 460 | set_pairs += [var_path + [int(val)]] 461 | else: 462 | print('ERROR: Incorrect variable path:', var) 463 | exit(2) 464 | else: 465 | exit(2) 466 | 467 | pp_bytes = decode._read_binary_file(pp_file) 468 | data = decode.select_pp_struct(pp_bytes) 469 | 470 | for set_list in set_pairs: 471 | decode.set_value(pp_file, pp_bytes, set_list[:-1], set_list[-1], 472 | data_dict=data, write=False, debug=debug) 473 | if write: 474 | print("Committing changes to '{}'.".format(pp_file)) 475 | decode._write_binary_file(pp_file, pp_bytes) 476 | else: 477 | print("WARNING: Nothing was written to '{}'.".format(pp_file), 478 | "Add --write option to commit the changes for real!") 479 | if to_registry: 480 | _write_pp_to_reg_file(to_registry + '.reg', pp_bytes, debug=debug) 481 | 482 | return 0 483 | 484 | 485 | cli.add_command(extract) 486 | cli.add_command(inject) 487 | cli.add_command(dump) 488 | cli.add_command(undump) 489 | cli.add_command(get) 490 | cli.add_command(set) 491 | cli.add_command(version) 492 | 493 | 494 | def main(): 495 | cli(obj={})() 496 | 497 | 498 | if __name__ == "__main__": 499 | main() 500 | -------------------------------------------------------------------------------- /test/AMD.RX480.8192.160603.rom.dump: -------------------------------------------------------------------------------- 1 | sHeader: 2 | StructureSize: 820 3 | TableFormatRevision: 7 4 | TableContentRevision: 1 5 | TableRevision: 0 6 | TableSize: 77 7 | GoldenPPID: 1546 8 | GoldenRevision: 9275 9 | FormatID: 25 10 | VoltageTime: 0 11 | PlatformCaps: 16941056 12 | MaxODEngineClock: 200000 13 | MaxODMemoryClock: 225000 14 | PowerControlLimit: 50 15 | UlvVoltageOffset: 50 16 | StateArray: 17 | RevId: 1 18 | NumEntries: 2 19 | entries: 20 | entries 0: 21 | EngineClockIndexHigh: 0 22 | EngineClockIndexLow: 0 23 | MemoryClockIndexHigh: 0 24 | MemoryClockIndexLow: 0 25 | PCIEGenLow: 0 26 | PCIEGenHigh: 0 27 | PCIELaneLow: 0 28 | PCIELaneHigh: 0 29 | Classification: 8 30 | CapsAndSettings: 0 31 | Classification2: 0 32 | Unused: 33 | Unused 0: 0 34 | Unused 1: 0 35 | Unused 2: 0 36 | Unused 3: 0 37 | entries 1: 38 | EngineClockIndexHigh: 7 39 | EngineClockIndexLow: 0 40 | MemoryClockIndexHigh: 1 41 | MemoryClockIndexLow: 0 42 | PCIEGenLow: 0 43 | PCIEGenHigh: 0 44 | PCIELaneLow: 0 45 | PCIELaneHigh: 0 46 | Classification: 5 47 | CapsAndSettings: 0 48 | Classification2: 0 49 | Unused: 50 | Unused 0: 0 51 | Unused 1: 0 52 | Unused 2: 0 53 | Unused 3: 0 54 | FanTable: 55 | RevId: 9 56 | THyst: 3 57 | TMin: 4000 58 | TMed: 6500 59 | THigh: 8500 60 | PWMMin: 2000 61 | PWMMed: 4000 62 | PWMHigh: 6000 63 | TMax: 10900 64 | FanControlMode: 1 65 | FanPWMMax: 100 66 | FanOutputSensitivity: 4836 67 | FanRPMMax: 2200 68 | MinFanSCLKAcousticLimit: 91000 69 | TargetTemperature: 80 70 | MinimumPWMLimit: 20 71 | FanGainEdge: 100 72 | FanGainHotspot: 100 73 | FanGainLiquid: 100 74 | FanGainVrVddc: 100 75 | FanGainVrMvdd: 100 76 | FanGainPlx: 100 77 | FanGainHbm: 100 78 | EnableZeroRPM: 0 79 | FanStopTemperature: 50 80 | FanStartTemperature: 60 81 | Reserved: 0 82 | ThermalController: 83 | RevId: 1 84 | Type: 23 85 | I2cLine: 0 86 | I2cAddress: 0 87 | FanParameters: 2 88 | FanMinRPM: 0 89 | FanMaxRPM: 52 90 | Reserved: 0 91 | Flags: 0 92 | Reserv: 0 93 | MclkDependencyTable: 94 | RevId: 0 95 | NumEntries: 2 96 | entries: 97 | entries 0: 98 | VddcInd: 0 99 | Vddci: 850 100 | VddgfxOffset: 0 101 | Mvdd: 1000 102 | Mclk: 30000 103 | Reserved: 0 104 | entries 1: 105 | VddcInd: 15 106 | Vddci: 950 107 | VddgfxOffset: 0 108 | Mvdd: 1000 109 | Mclk: 200000 110 | Reserved: 0 111 | SclkDependencyTable: 112 | RevId: 1 113 | NumEntries: 8 114 | entries: 115 | entries 0: 116 | VddInd: 0 117 | VddcOffset: 0 118 | Sclk: 30000 119 | EdcCurrent: 0 120 | ReliabilityTemperature: 0 121 | CKSVOffsetandDisable: 128 122 | SclkOffset: 0 123 | entries 1: 124 | VddInd: 1 125 | VddcOffset: 65510 126 | Sclk: 60800 127 | EdcCurrent: 0 128 | ReliabilityTemperature: 0 129 | CKSVOffsetandDisable: 0 130 | SclkOffset: 0 131 | entries 2: 132 | VddInd: 2 133 | VddcOffset: 65510 134 | Sclk: 91000 135 | EdcCurrent: 0 136 | ReliabilityTemperature: 0 137 | CKSVOffsetandDisable: 0 138 | SclkOffset: 5000 139 | entries 3: 140 | VddInd: 3 141 | VddcOffset: 65510 142 | Sclk: 107700 143 | EdcCurrent: 0 144 | ReliabilityTemperature: 0 145 | CKSVOffsetandDisable: 0 146 | SclkOffset: 0 147 | entries 4: 148 | VddInd: 4 149 | VddcOffset: 65510 150 | Sclk: 114500 151 | EdcCurrent: 0 152 | ReliabilityTemperature: 0 153 | CKSVOffsetandDisable: 0 154 | SclkOffset: 0 155 | entries 5: 156 | VddInd: 5 157 | VddcOffset: 65510 158 | Sclk: 119100 159 | EdcCurrent: 0 160 | ReliabilityTemperature: 0 161 | CKSVOffsetandDisable: 0 162 | SclkOffset: 0 163 | entries 6: 164 | VddInd: 6 165 | VddcOffset: 65510 166 | Sclk: 123600 167 | EdcCurrent: 0 168 | ReliabilityTemperature: 0 169 | CKSVOffsetandDisable: 0 170 | SclkOffset: 0 171 | entries 7: 172 | VddInd: 7 173 | VddcOffset: 0 174 | Sclk: 126600 175 | EdcCurrent: 0 176 | ReliabilityTemperature: 0 177 | CKSVOffsetandDisable: 0 178 | SclkOffset: 0 179 | VddcLookupTable: 180 | RevId: 0 181 | NumEntries: 16 182 | entries: 183 | entries 0: 184 | Vdd: 800 185 | CACLow: 0 186 | CACMid: 0 187 | CACHigh: 0 188 | entries 1: 189 | Vdd: 65282 190 | CACLow: 0 191 | CACMid: 0 192 | CACHigh: 0 193 | entries 2: 194 | Vdd: 65283 195 | CACLow: 0 196 | CACMid: 0 197 | CACHigh: 0 198 | entries 3: 199 | Vdd: 65284 200 | CACLow: 0 201 | CACMid: 0 202 | CACHigh: 0 203 | entries 4: 204 | Vdd: 65285 205 | CACLow: 0 206 | CACMid: 0 207 | CACHigh: 0 208 | entries 5: 209 | Vdd: 65286 210 | CACLow: 0 211 | CACMid: 0 212 | CACHigh: 0 213 | entries 6: 214 | Vdd: 65287 215 | CACLow: 0 216 | CACMid: 0 217 | CACHigh: 0 218 | entries 7: 219 | Vdd: 65288 220 | CACLow: 0 221 | CACMid: 0 222 | CACHigh: 0 223 | entries 8: 224 | Vdd: 850 225 | CACLow: 0 226 | CACMid: 0 227 | CACHigh: 0 228 | entries 9: 229 | Vdd: 900 230 | CACLow: 0 231 | CACMid: 0 232 | CACHigh: 0 233 | entries 10: 234 | Vdd: 950 235 | CACLow: 0 236 | CACMid: 0 237 | CACHigh: 0 238 | entries 11: 239 | Vdd: 1000 240 | CACLow: 0 241 | CACMid: 0 242 | CACHigh: 0 243 | entries 12: 244 | Vdd: 1050 245 | CACLow: 0 246 | CACMid: 0 247 | CACHigh: 0 248 | entries 13: 249 | Vdd: 1100 250 | CACLow: 0 251 | CACMid: 0 252 | CACHigh: 0 253 | entries 14: 254 | Vdd: 1150 255 | CACLow: 0 256 | CACMid: 0 257 | CACHigh: 0 258 | entries 15: 259 | Vdd: 975 260 | CACLow: 0 261 | CACMid: 0 262 | CACHigh: 0 263 | VddgfxLookupTable: 264 | RevId: 0 265 | NumEntries: 8 266 | entries: 267 | entries 0: 268 | Vdd: 900 269 | CACLow: 0 270 | CACMid: 0 271 | CACHigh: 0 272 | entries 1: 273 | Vdd: 65282 274 | CACLow: 0 275 | CACMid: 0 276 | CACHigh: 0 277 | entries 2: 278 | Vdd: 65283 279 | CACLow: 0 280 | CACMid: 0 281 | CACHigh: 0 282 | entries 3: 283 | Vdd: 65284 284 | CACLow: 0 285 | CACMid: 0 286 | CACHigh: 0 287 | entries 4: 288 | Vdd: 65285 289 | CACLow: 0 290 | CACMid: 0 291 | CACHigh: 0 292 | entries 5: 293 | Vdd: 65286 294 | CACLow: 0 295 | CACMid: 0 296 | CACHigh: 0 297 | entries 6: 298 | Vdd: 65287 299 | CACLow: 0 300 | CACMid: 0 301 | CACHigh: 0 302 | entries 7: 303 | Vdd: 65288 304 | CACLow: 0 305 | CACMid: 0 306 | CACHigh: 0 307 | MMDependencyTable: 308 | RevId: 0 309 | NumEntries: 8 310 | entries: 311 | entries 0: 312 | VddcInd: 0 313 | VddgfxOffset: 0 314 | DClk: 58000 315 | VClk: 75000 316 | EClk: 63000 317 | AClk: 0 318 | SAMUClk: 57000 319 | entries 1: 320 | VddcInd: 8 321 | VddgfxOffset: 65460 322 | DClk: 63000 323 | VClk: 80000 324 | EClk: 69000 325 | AClk: 0 326 | SAMUClk: 64000 327 | entries 2: 328 | VddcInd: 9 329 | VddgfxOffset: 65435 330 | DClk: 68000 331 | VClk: 85000 332 | EClk: 75000 333 | AClk: 0 334 | SAMUClk: 70000 335 | entries 3: 336 | VddcInd: 10 337 | VddgfxOffset: 65410 338 | DClk: 73000 339 | VClk: 89000 340 | EClk: 81000 341 | AClk: 0 342 | SAMUClk: 76000 343 | entries 4: 344 | VddcInd: 11 345 | VddgfxOffset: 65385 346 | DClk: 77000 347 | VClk: 92000 348 | EClk: 86000 349 | AClk: 0 350 | SAMUClk: 81000 351 | entries 5: 352 | VddcInd: 12 353 | VddgfxOffset: 65335 354 | DClk: 80000 355 | VClk: 95000 356 | EClk: 91000 357 | AClk: 0 358 | SAMUClk: 85000 359 | entries 6: 360 | VddcInd: 13 361 | VddgfxOffset: 65285 362 | DClk: 83000 363 | VClk: 98000 364 | EClk: 96000 365 | AClk: 0 366 | SAMUClk: 88000 367 | entries 7: 368 | VddcInd: 14 369 | VddgfxOffset: 0 370 | DClk: 86000 371 | VClk: 100000 372 | EClk: 100000 373 | AClk: 0 374 | SAMUClk: 91000 375 | VCEStateTable: 376 | RevId: 1 377 | NumEntries: 6 378 | entries: 379 | entries 0: 380 | VCEClockIndex: 0 381 | Flag: 0 382 | SCLKIndex: 1 383 | MCLKIndex: 1 384 | entries 1: 385 | VCEClockIndex: 0 386 | Flag: 1 387 | SCLKIndex: 1 388 | MCLKIndex: 1 389 | entries 2: 390 | VCEClockIndex: 0 391 | Flag: 2 392 | SCLKIndex: 1 393 | MCLKIndex: 1 394 | entries 3: 395 | VCEClockIndex: 0 396 | Flag: 2 397 | SCLKIndex: 1 398 | MCLKIndex: 1 399 | entries 4: 400 | VCEClockIndex: 0 401 | Flag: 2 402 | SCLKIndex: 1 403 | MCLKIndex: 1 404 | entries 5: 405 | VCEClockIndex: 0 406 | Flag: 2 407 | SCLKIndex: 1 408 | MCLKIndex: 1 409 | PPMTable: UNUSED 410 | PowerTuneTable: 411 | RevId: 4 412 | TDP: 110 413 | ConfigurableTDP: 0 414 | TDC: 107 415 | BatteryPowerLimit: 110 416 | SmallPowerLimit: 110 417 | LowCACLeakage: 0 418 | HighCACLeakage: 0 419 | MaximumPowerDeliveryLimit: 110 420 | TjMax: 90 421 | PowerTuneDataSetID: 0 422 | EDCLimit: 0 423 | SoftwareShutdownTemp: 94 424 | ClockStretchAmount: 2 425 | TemperatureLimitHotspot: 105 426 | TemperatureLimitLiquid1: 80 427 | TemperatureLimitLiquid2: 80 428 | TemperatureLimitVrVddc: 115 429 | TemperatureLimitVrMvdd: 115 430 | TemperatureLimitPlx: 95 431 | Liquid1_I2C_address: 0 432 | Liquid2_I2C_address: 0 433 | Liquid_I2C_Line: 144 434 | Vr_I2C_address: 16 435 | Vr_I2C_Line: 150 436 | Plx_I2C_address: 0 437 | Plx_I2C_Line: 144 438 | BoostPowerLimit: 0 439 | CKS_LDO_REFSEL: 6 440 | HotSpotOnly: 0 441 | Reserve: 0 442 | HardLimitTable: UNUSED 443 | PCIETable: 444 | RevId: 1 445 | NumEntries: 3 446 | entries: 447 | entries 0: 448 | PCIEGenSpeed: 0 449 | PCIELaneWidth: 16 450 | Reserved: 451 | Reserved 0: 0 452 | Reserved 1: 0 453 | PCIE_Sclk: 0 454 | entries 1: 455 | PCIEGenSpeed: 0 456 | PCIELaneWidth: 16 457 | Reserved: 458 | Reserved 0: 0 459 | Reserved 1: 0 460 | PCIE_Sclk: 0 461 | entries 2: 462 | PCIEGenSpeed: 2 463 | PCIELaneWidth: 16 464 | Reserved: 465 | Reserved 0: 0 466 | Reserved 1: 0 467 | PCIE_Sclk: 0 468 | GPIOTable: 469 | RevId: 0 470 | VRHotTriggeredSclkDpmIndex: 1 471 | Reserve: 472 | Reserve 0: 0 473 | Reserve 1: 0 474 | Reserve 2: 0 475 | Reserve 3: 0 476 | Reserve 4: 0 477 | Reserved: 478 | Reserved 0: 0 479 | Reserved 1: 0 480 | Reserved 2: 0 481 | Reserved 3: 0 482 | Reserved 4: 0 483 | Reserved 5: 0 484 | -------------------------------------------------------------------------------- /test/AMD.RX5700XT.8192.190616.rom.check: -------------------------------------------------------------------------------- 1 | 110 2 | 110 3 | 100 4 | 2800 5 | 3900 6 | 2800 7 | 3800 8 | -0.03 9 | 0 10 | 0 11 | 1650 12 | 4400 13 | 2600 14 | 4600 15 | 3200 16 | 4800 17 | 3200 18 | 5000 19 | 3200 20 | 750 21 | -------------------------------------------------------------------------------- /test/AMD.RX5700XT.8192.190616.rom.conf: -------------------------------------------------------------------------------- 1 | smc_pptable/SocketPowerLimitAc/0=110 2 | smc_pptable/SocketPowerLimitDc/0=110 3 | smc_pptable/FanStartTemp=100 4 | smc_pptable/MinVoltageGfx=2800 5 | smc_pptable/MaxVoltageGfx=3900 6 | smc_pptable/MinVoltageSoc=2800 7 | smc_pptable/MaxVoltageSoc=3800 8 | smc_pptable/qStaticVoltageOffset/0/c=-0.03 9 | smc_pptable/UlvVoltageOffsetSoc=0 10 | smc_pptable/UlvVoltageOffsetGfx=0 11 | smc_pptable/FreqTableGfx/1=1650 12 | smc_pptable/MemMvddVoltage/0=4400 13 | smc_pptable/MemVddciVoltage/0=2600 14 | smc_pptable/MemMvddVoltage/1=4600 15 | smc_pptable/MemVddciVoltage/1=3200 16 | smc_pptable/MemMvddVoltage/2=4800 17 | smc_pptable/MemVddciVoltage/2=3200 18 | smc_pptable/MemMvddVoltage/3=5000 19 | smc_pptable/MemVddciVoltage/3=3200 20 | smc_pptable/FreqTableUclk/3=750 21 | -------------------------------------------------------------------------------- /test/AMD.RX5700XT.8192.190616.rom.dump: -------------------------------------------------------------------------------- 1 | header: 2 | structuresize: 1674 3 | format_revision: 12 4 | content_revision: 0 5 | table_revision: 1 6 | table_size: 482 7 | golden_pp_id: 2247 8 | golden_revision: 14368 9 | format_id: 125 10 | platform_caps: 8 11 | thermal_controller_type: 27 12 | small_power_limit1: 0 13 | small_power_limit2: 0 14 | boost_power_limit: 0 15 | od_turbo_power_limit: 0 16 | od_power_save_power_limit: 0 17 | software_shutdown_temp: 118 18 | reserve: 19 | reserve 0: 0 20 | reserve 1: 0 21 | reserve 2: 0 22 | reserve 3: 0 23 | reserve 4: 0 24 | reserve 5: 0 25 | power_saving_clock: 26 | revision: 1 27 | reserve: 28 | reserve 0: 0 29 | reserve 1: 0 30 | reserve 2: 0 31 | count: 10 32 | max: 33 | max 0: 2100 (GFXCLK) 34 | max 1: 1267 (VCLK) 35 | max 2: 1086 (DCLK) 36 | max 3: 1267 (ECLK) 37 | max 4: 1267 (SOCCLK) 38 | max 5: 875 (UCLK) 39 | max 6: 1267 (DCEFCLK) 40 | max 7: 1284 (DISPCLK) 41 | max 8: 1284 (PIXCLK) 42 | max 9: 810 (PHYCLK) 43 | max 10: 0 44 | max 11: 0 45 | max 12: 0 46 | max 13: 0 47 | max 14: 0 48 | max 15: 0 49 | min: 50 | min 0: 300 (GFXCLK) 51 | min 1: 100 (VCLK) 52 | min 2: 100 (DCLK) 53 | min 3: 100 (ECLK) 54 | min 4: 507 (SOCCLK) 55 | min 5: 100 (UCLK) 56 | min 6: 507 (DCEFCLK) 57 | min 7: 308 (DISPCLK) 58 | min 8: 300 (PIXCLK) 59 | min 9: 300 (PHYCLK) 60 | min 10: 0 61 | min 11: 0 62 | min 12: 0 63 | min 13: 0 64 | min 14: 0 65 | min 15: 0 66 | overdrive_table: 67 | revision: 128 68 | reserve: 69 | reserve 0: 0 70 | reserve 1: 0 71 | reserve 2: 0 72 | feature_count: 14 73 | setting_count: 30 74 | cap: 75 | cap 0: 1 (GFXCLK_LIMITS) 76 | cap 1: 1 (GFXCLK_CURVE) 77 | cap 2: 1 (UCLK_MAX) 78 | cap 3: 1 (POWER_LIMIT) 79 | cap 4: 1 (FAN_ACOUSTIC_LIMIT) 80 | cap 5: 1 (FAN_SPEED_MIN) 81 | cap 6: 1 (TEMPERATURE_FAN) 82 | cap 7: 1 (TEMPERATURE_SYSTEM) 83 | cap 8: 1 (MEMORY_TIMING_TUNE) 84 | cap 9: 0 (FAN_ZERO_RPM_CONTROL) 85 | cap 10: 1 (AUTO_UV_ENGINE) 86 | cap 11: 1 (AUTO_OC_ENGINE) 87 | cap 12: 1 (AUTO_OC_MEMORY) 88 | cap 13: 1 (FAN_CURVE) 89 | cap 14: 0 90 | cap 15: 0 91 | cap 16: 0 92 | cap 17: 0 93 | cap 18: 0 94 | cap 19: 0 95 | cap 20: 0 96 | cap 21: 0 97 | cap 22: 0 98 | cap 23: 0 99 | cap 24: 0 100 | cap 25: 0 101 | cap 26: 0 102 | cap 27: 0 103 | cap 28: 0 104 | cap 29: 0 105 | cap 30: 0 106 | cap 31: 0 107 | max: 108 | max 0: 2150 (GFXCLKFMAX) 109 | max 1: 2150 (GFXCLKFMIN) 110 | max 2: 2150 (VDDGFXCURVEFREQ_P1) 111 | max 3: 1200 (VDDGFXCURVEVOLTAGE_P1) 112 | max 4: 2150 (VDDGFXCURVEFREQ_P2) 113 | max 5: 1200 (VDDGFXCURVEVOLTAGE_P2) 114 | max 6: 2150 (VDDGFXCURVEFREQ_P3) 115 | max 7: 1200 (VDDGFXCURVEVOLTAGE_P3) 116 | max 8: 950 (UCLKFMAX) 117 | max 9: 50 (POWERPERCENTAGE) 118 | max 10: 4950 (FANRPMMIN) 119 | max 11: 4950 (FANRPMACOUSTICLIMIT) 120 | max 12: 100 (FANTARGETTEMPERATURE) 121 | max 13: 110 (OPERATINGTEMPMAX) 122 | max 14: 2 (ACTIMING) 123 | max 15: 0 (FAN_ZERO_RPM_CONTROL) 124 | max 16: 1 (AUTOUVENGINE) 125 | max 17: 1 (AUTOOCENGINE) 126 | max 18: 1 (AUTOOCMEMORY) 127 | max 19: 100 128 | max 20: 100 129 | max 21: 100 130 | max 22: 100 131 | max 23: 100 132 | max 24: 100 133 | max 25: 100 134 | max 26: 100 135 | max 27: 100 136 | max 28: 100 137 | max 29: 0 138 | max 30: 0 139 | max 31: 0 140 | min: 141 | min 0: 800 (GFXCLKFMAX) 142 | min 1: 800 (GFXCLKFMIN) 143 | min 2: 800 (VDDGFXCURVEFREQ_P1) 144 | min 3: 750 (VDDGFXCURVEVOLTAGE_P1) 145 | min 4: 800 (VDDGFXCURVEFREQ_P2) 146 | min 5: 750 (VDDGFXCURVEVOLTAGE_P2) 147 | min 6: 800 (VDDGFXCURVEFREQ_P3) 148 | min 7: 750 (VDDGFXCURVEVOLTAGE_P3) 149 | min 8: 625 (UCLKFMAX) 150 | min 9: 50 (POWERPERCENTAGE) 151 | min 10: 1100 (FANRPMMIN) 152 | min 11: 1100 (FANRPMACOUSTICLIMIT) 153 | min 12: 25 (FANTARGETTEMPERATURE) 154 | min 13: 50 (OPERATINGTEMPMAX) 155 | min 14: 0 (ACTIMING) 156 | min 15: 0 (FAN_ZERO_RPM_CONTROL) 157 | min 16: 0 (AUTOUVENGINE) 158 | min 17: 0 (AUTOOCENGINE) 159 | min 18: 0 (AUTOOCMEMORY) 160 | min 19: 25 161 | min 20: 10 162 | min 21: 25 163 | min 22: 10 164 | min 23: 25 165 | min 24: 10 166 | min 25: 25 167 | min 26: 10 168 | min 27: 25 169 | min 28: 10 170 | min 29: 0 171 | min 30: 0 172 | min 31: 0 173 | smc_pptable: 174 | Version: 8 175 | FeaturesToRun: 176 | FeaturesToRun 0: 3017781247 177 | FeaturesToRun 1: 1571 178 | SocketPowerLimitAc: 179 | SocketPowerLimitAc 0: 180 180 | SocketPowerLimitAc 1: 0 181 | SocketPowerLimitAc 2: 0 182 | SocketPowerLimitAc 3: 0 183 | SocketPowerLimitAcTau: 184 | SocketPowerLimitAcTau 0: 0 185 | SocketPowerLimitAcTau 1: 0 186 | SocketPowerLimitAcTau 2: 0 187 | SocketPowerLimitAcTau 3: 0 188 | SocketPowerLimitDc: 189 | SocketPowerLimitDc 0: 180 190 | SocketPowerLimitDc 1: 0 191 | SocketPowerLimitDc 2: 0 192 | SocketPowerLimitDc 3: 0 193 | SocketPowerLimitDcTau: 194 | SocketPowerLimitDcTau 0: 0 195 | SocketPowerLimitDcTau 1: 0 196 | SocketPowerLimitDcTau 2: 0 197 | SocketPowerLimitDcTau 3: 0 198 | TdcLimitSoc: 14 199 | TdcLimitSocTau: 0 200 | TdcLimitGfx: 170 201 | TdcLimitGfxTau: 0 202 | TedgeLimit: 100 203 | ThotspotLimit: 110 204 | TmemLimit: 105 205 | Tvr_gfxLimit: 115 206 | Tvr_mem0Limit: 115 207 | Tvr_mem1Limit: 115 208 | Tvr_socLimit: 115 209 | Tliquid0Limit: 0 210 | Tliquid1Limit: 0 211 | TplxLimit: 0 212 | FitLimit: 0 213 | PpmPowerLimit: 0 214 | PpmTemperatureThreshold: 0 215 | ThrottlerControlMask: 28926 216 | FwDStateMask: 1 217 | UlvVoltageOffsetSoc: 100 218 | UlvVoltageOffsetGfx: 100 219 | GceaLinkMgrIdleThreshold: 0 220 | paddingRlcUlvParams: 221 | paddingRlcUlvParams 0: 0 222 | paddingRlcUlvParams 1: 0 223 | paddingRlcUlvParams 2: 0 224 | UlvSmnclkDid: 0 225 | UlvMp1clkDid: 0 226 | UlvGfxclkBypass: 0 227 | Padding234: 0 228 | MinVoltageUlvGfx: 2900 229 | MinVoltageUlvSoc: 2900 230 | MinVoltageGfx: 3000 231 | MinVoltageSoc: 3000 232 | MaxVoltageGfx: 4800 233 | MaxVoltageSoc: 4800 234 | LoadLineResistanceGfx: 76 235 | LoadLineResistanceSoc: 0 236 | DpmDescriptor: 237 | DpmDescriptor 0: 238 | VoltageMode: 1 239 | SnapToDiscrete: 0 240 | NumDiscreteLevels: 2 241 | Padding: 0 242 | ConversionToAvfsClk: 243 | m: 0 244 | b: 0 245 | SsCurve: 246 | a: 0.2542 247 | b:-0.21625 248 | c: 0.69572 249 | DpmDescriptor 1: 250 | VoltageMode: 1 251 | SnapToDiscrete: 0 252 | NumDiscreteLevels: 2 253 | Padding: 0 254 | ConversionToAvfsClk: 255 | m: 1 256 | b: 0 257 | SsCurve: 258 | a: 0.21751 259 | b:-0.05852 260 | c: 0.71468 261 | DpmDescriptor 2: 262 | VoltageMode: 1 263 | SnapToDiscrete: 1 264 | NumDiscreteLevels: 4 265 | Padding: 0 266 | ConversionToAvfsClk: 267 | m: 1 268 | b: 0 269 | SsCurve: 270 | a: 0.21751 271 | b:-0.05852 272 | c: 0.71468 273 | DpmDescriptor 3: 274 | VoltageMode: 1 275 | SnapToDiscrete: 0 276 | NumDiscreteLevels: 2 277 | Padding: 0 278 | ConversionToAvfsClk: 279 | m: 0.6443 280 | b: 0.5349 281 | SsCurve: 282 | a: 0 283 | b: 0.3851 284 | c: 0.5678 285 | DpmDescriptor 4: 286 | VoltageMode: 1 287 | SnapToDiscrete: 0 288 | NumDiscreteLevels: 2 289 | Padding: 0 290 | ConversionToAvfsClk: 291 | m: 0.5094 292 | b: 0.5925 293 | SsCurve: 294 | a: 0 295 | b: 0.3307 296 | c: 0.5685 297 | DpmDescriptor 5: 298 | VoltageMode: 1 299 | SnapToDiscrete: 0 300 | NumDiscreteLevels: 2 301 | Padding: 0 302 | ConversionToAvfsClk: 303 | m: 1.256 304 | b:-0.3438 305 | SsCurve: 306 | a: 0 307 | b: 0.5343 308 | c: 0.2453 309 | DpmDescriptor 6: 310 | VoltageMode: 1 311 | SnapToDiscrete: 0 312 | NumDiscreteLevels: 2 313 | Padding: 0 314 | ConversionToAvfsClk: 315 | m: 0.8216 316 | b: 0.0146 317 | SsCurve: 318 | a: 0 319 | b: 0.4776 320 | c: 0.2526 321 | DpmDescriptor 7: 322 | VoltageMode: 2 323 | SnapToDiscrete: 0 324 | NumDiscreteLevels: 2 325 | Padding: 0 326 | ConversionToAvfsClk: 327 | m: 0 328 | b: 0 329 | SsCurve: 330 | a: 0 331 | b: 0 332 | c: 0 333 | DpmDescriptor 8: 334 | VoltageMode: 2 335 | SnapToDiscrete: 0 336 | NumDiscreteLevels: 2 337 | Padding: 0 338 | ConversionToAvfsClk: 339 | m: 0 340 | b: 0 341 | SsCurve: 342 | a: 0 343 | b: 0 344 | c: 0 345 | FreqTableGfx: 346 | FreqTableGfx 0: 300 347 | FreqTableGfx 1: 2100 348 | FreqTableGfx 2: 1400 349 | FreqTableGfx 3: 1400 350 | FreqTableGfx 4: 1400 351 | FreqTableGfx 5: 1400 352 | FreqTableGfx 6: 1400 353 | FreqTableGfx 7: 1400 354 | FreqTableGfx 8: 1400 355 | FreqTableGfx 9: 1400 356 | FreqTableGfx 10: 1400 357 | FreqTableGfx 11: 1400 358 | FreqTableGfx 12: 1400 359 | FreqTableGfx 13: 1400 360 | FreqTableGfx 14: 1400 361 | FreqTableGfx 15: 1400 362 | FreqTableVclk: 363 | FreqTableVclk 0: 100 364 | FreqTableVclk 1: 1267 365 | FreqTableVclk 2: 1267 366 | FreqTableVclk 3: 1267 367 | FreqTableVclk 4: 1267 368 | FreqTableVclk 5: 1267 369 | FreqTableVclk 6: 1267 370 | FreqTableVclk 7: 1267 371 | FreqTableDclk: 372 | FreqTableDclk 0: 100 373 | FreqTableDclk 1: 1086 374 | FreqTableDclk 2: 1086 375 | FreqTableDclk 3: 1086 376 | FreqTableDclk 4: 1086 377 | FreqTableDclk 5: 1086 378 | FreqTableDclk 6: 1086 379 | FreqTableDclk 7: 1086 380 | FreqTableSocclk: 381 | FreqTableSocclk 0: 507 382 | FreqTableSocclk 1: 1267 383 | FreqTableSocclk 2: 950 384 | FreqTableSocclk 3: 950 385 | FreqTableSocclk 4: 950 386 | FreqTableSocclk 5: 950 387 | FreqTableSocclk 6: 950 388 | FreqTableSocclk 7: 950 389 | FreqTableUclk: 390 | FreqTableUclk 0: 100 391 | FreqTableUclk 1: 500 392 | FreqTableUclk 2: 625 393 | FreqTableUclk 3: 875 394 | FreqTableDcefclk: 395 | FreqTableDcefclk 0: 507 396 | FreqTableDcefclk 1: 1267 397 | FreqTableDcefclk 2: 1267 398 | FreqTableDcefclk 3: 1267 399 | FreqTableDcefclk 4: 1267 400 | FreqTableDcefclk 5: 1267 401 | FreqTableDcefclk 6: 1267 402 | FreqTableDcefclk 7: 1267 403 | FreqTableDispclk: 404 | FreqTableDispclk 0: 308 405 | FreqTableDispclk 1: 1284 406 | FreqTableDispclk 2: 1284 407 | FreqTableDispclk 3: 1284 408 | FreqTableDispclk 4: 1284 409 | FreqTableDispclk 5: 1284 410 | FreqTableDispclk 6: 1284 411 | FreqTableDispclk 7: 1284 412 | FreqTablePixclk: 413 | FreqTablePixclk 0: 300 414 | FreqTablePixclk 1: 1284 415 | FreqTablePixclk 2: 1188 416 | FreqTablePixclk 3: 1188 417 | FreqTablePixclk 4: 1188 418 | FreqTablePixclk 5: 1188 419 | FreqTablePixclk 6: 1188 420 | FreqTablePixclk 7: 1188 421 | FreqTablePhyclk: 422 | FreqTablePhyclk 0: 300 423 | FreqTablePhyclk 1: 810 424 | FreqTablePhyclk 2: 810 425 | FreqTablePhyclk 3: 810 426 | FreqTablePhyclk 4: 810 427 | FreqTablePhyclk 5: 810 428 | FreqTablePhyclk 6: 810 429 | FreqTablePhyclk 7: 810 430 | Paddingclks: 431 | Paddingclks 0: 30409168 432 | Paddingclks 1: 30409168 433 | Paddingclks 2: 30409168 434 | Paddingclks 3: 30409168 435 | Paddingclks 4: 30409168 436 | Paddingclks 5: 30409168 437 | Paddingclks 6: 30409168 438 | Paddingclks 7: 30409168 439 | Paddingclks 8: 30409168 440 | Paddingclks 9: 30409168 441 | Paddingclks 10: 30409168 442 | Paddingclks 11: 30409168 443 | Paddingclks 12: 30409168 444 | Paddingclks 13: 30409168 445 | Paddingclks 14: 30409168 446 | Paddingclks 15: 30409168 447 | DcModeMaxFreq: 448 | DcModeMaxFreq 0: 2100 449 | DcModeMaxFreq 1: 1267 450 | DcModeMaxFreq 2: 875 451 | DcModeMaxFreq 3: 1086 452 | DcModeMaxFreq 4: 1267 453 | DcModeMaxFreq 5: 1267 454 | DcModeMaxFreq 6: 1284 455 | DcModeMaxFreq 7: 1284 456 | DcModeMaxFreq 8: 810 457 | Padding8_Clks: 464 458 | FreqTableUclkDiv: 459 | FreqTableUclkDiv 0: 0 460 | FreqTableUclkDiv 1: 3 461 | FreqTableUclkDiv 2: 3 462 | FreqTableUclkDiv 3: 3 463 | Mp0clkFreq: 464 | Mp0clkFreq 0: 304 465 | Mp0clkFreq 1: 507 466 | Mp0DpmVoltage: 467 | Mp0DpmVoltage 0: 3000 468 | Mp0DpmVoltage 1: 3000 469 | MemVddciVoltage: 470 | MemVddciVoltage 0: 2700 471 | MemVddciVoltage 1: 3400 472 | MemVddciVoltage 2: 3400 473 | MemVddciVoltage 3: 3400 474 | MemMvddVoltage: 475 | MemMvddVoltage 0: 5000 476 | MemMvddVoltage 1: 5400 477 | MemMvddVoltage 2: 5400 478 | MemMvddVoltage 3: 5400 479 | GfxclkFgfxoffEntry: 800 480 | GfxclkFinit: 800 481 | GfxclkFidle: 800 482 | GfxclkSlewRate: 0 483 | GfxclkFopt: 0 484 | Padding567: 485 | Padding567 0: 208 486 | Padding567 1: 1 487 | GfxclkDsMaxFreq: 0 488 | GfxclkSource: 1 489 | Padding456: 2 490 | LowestUclkReservedForUlv: 0 491 | paddingUclk: 492 | paddingUclk 0: 0 493 | paddingUclk 1: 91 494 | paddingUclk 2: 0 495 | MemoryType: 0 496 | MemoryChannels: 16 497 | PaddingMem: 498 | PaddingMem 0: 0 499 | PaddingMem 1: 0 500 | PcieGenSpeed: 501 | PcieGenSpeed 0: 0 502 | PcieGenSpeed 1: 3 503 | PcieLaneCount: 504 | PcieLaneCount 0: 6 505 | PcieLaneCount 1: 6 506 | LclkFreq: 507 | LclkFreq 0: 619 508 | LclkFreq 1: 619 509 | EnableTdpm: 0 510 | TdpmHighHystTemperature: 0 511 | TdpmLowHystTemperature: 0 512 | GfxclkFreqHighTempLimit: 0 513 | FanStopTemp: 0 514 | FanStartTemp: 0 515 | FanGainEdge: 400 516 | FanGainHotspot: 400 517 | FanGainLiquid0: 400 518 | FanGainLiquid1: 400 519 | FanGainVrGfx: 400 520 | FanGainVrSoc: 400 521 | FanGainVrMem0: 400 522 | FanGainVrMem1: 400 523 | FanGainPlx: 400 524 | FanGainMem: 400 525 | FanPwmMin: 20 526 | FanAcousticLimitRpm: 2100 527 | FanThrottlingRpm: 2100 528 | FanMaximumRpm: 4950 529 | FanTargetTemperature: 90 530 | FanTargetGfxclk: 800 531 | FanTempInputSelect: 1 532 | FanPadding: 0 533 | FanZeroRpmEnable: 0 534 | FanTachEdgePerRev: 2 535 | FuzzyFan_ErrorSetDelta: 0 536 | FuzzyFan_ErrorRateSetDelta: 0 537 | FuzzyFan_PwmSetDelta: 0 538 | FuzzyFan_Reserved: 0 539 | OverrideAvfsGb: 540 | OverrideAvfsGb 0: 0 541 | OverrideAvfsGb 1: 0 542 | Padding8_Avfs: 543 | Padding8_Avfs 0: 0 544 | Padding8_Avfs 1: 0 545 | qAvfsGb: 546 | qAvfsGb 0: 547 | a: 0.01781 548 | b:-0.04728 549 | c: 0.05402 550 | qAvfsGb 1: 551 | a: 0 552 | b: 0 553 | c: 0.03 554 | dBtcGbGfxPll: 555 | a: 0 556 | b: 0 557 | c: 0 558 | dBtcGbGfxDfll: 559 | a: 0.09755 560 | b: 0.04839 561 | c:-0.07874 562 | dBtcGbSoc: 563 | a: 0.00234 564 | b:-0.00239 565 | c: 0.09239 566 | qAgingGb: 567 | qAgingGb 0: 568 | m: 0 569 | b: 0 570 | qAgingGb 1: 571 | m: 0 572 | b: 0 573 | qStaticVoltageOffset: 574 | qStaticVoltageOffset 0: 575 | a: 0 576 | b: 0 577 | c: 0 578 | qStaticVoltageOffset 1: 579 | a: 0 580 | b: 0 581 | c: 0 582 | DcTol: 583 | DcTol 0: 160 584 | DcTol 1: 160 585 | DcBtcEnabled: 586 | DcBtcEnabled 0: 1 587 | DcBtcEnabled 1: 1 588 | Padding8_GfxBtc: 589 | Padding8_GfxBtc 0: 0 590 | Padding8_GfxBtc 1: 0 591 | DcBtcMin: 592 | DcBtcMin 0: 0 593 | DcBtcMin 1: 0 594 | DcBtcMax: 595 | DcBtcMax 0: 160 596 | DcBtcMax 1: 160 597 | DebugOverrides: 512 598 | ReservedEquation0: 599 | a: 0 600 | b: 0 601 | c: 0 602 | ReservedEquation1: 603 | a: 0 604 | b: 0 605 | c: 0 606 | ReservedEquation2: 607 | a: 0 608 | b: 0 609 | c: 0 610 | ReservedEquation3: 611 | a: 0 612 | b: 0 613 | c: 0 614 | TotalPowerConfig: 1 615 | TotalPowerSpare1: 0 616 | TotalPowerSpare2: 0 617 | PccThresholdLow: 0 618 | PccThresholdHigh: 0 619 | MGpuFanBoostLimitRpm: 0 620 | PaddingAPCC: 621 | PaddingAPCC 0: 0 622 | PaddingAPCC 1: 0 623 | PaddingAPCC 2: 0 624 | PaddingAPCC 3: 0 625 | PaddingAPCC 4: 0 626 | VDDGFX_TVmin: 0 627 | VDDSOC_TVmin: 0 628 | VDDGFX_Vmin_HiTemp: 0 629 | VDDGFX_Vmin_LoTemp: 0 630 | VDDSOC_Vmin_HiTemp: 0 631 | VDDSOC_Vmin_LoTemp: 0 632 | VDDGFX_TVminHystersis: 0 633 | VDDSOC_TVminHystersis: 0 634 | BtcConfig: 0 635 | SsFmin: 636 | SsFmin 0: 425 637 | SsFmin 1: 135 638 | SsFmin 2: 135 639 | SsFmin 3: 0 640 | SsFmin 4: 0 641 | SsFmin 5: 0 642 | SsFmin 6: 0 643 | SsFmin 7: 0 644 | SsFmin 8: 0 645 | SsFmin 9: 0 646 | DcBtcGb: 647 | DcBtcGb 0: 25 648 | DcBtcGb 1: 25 649 | Reserved: 650 | Reserved 0: 0 651 | Reserved 1: 0 652 | Reserved 2: 0 653 | Reserved 3: 0 654 | Reserved 4: 0 655 | Reserved 5: 0 656 | Reserved 6: 0 657 | Reserved 7: 0 658 | I2cControllers: 659 | I2cControllers 0: 660 | Enabled: 0 661 | Speed: 0 662 | Padding: 663 | Padding 0: 0 664 | Padding 1: 0 665 | SlaveAddress: 0 666 | ControllerPort: 0 667 | ControllerName: 0 668 | ThermalThrotter: 0 669 | I2cProtocol: 0 670 | I2cControllers 1: 671 | Enabled: 0 672 | Speed: 0 673 | Padding: 674 | Padding 0: 0 675 | Padding 1: 0 676 | SlaveAddress: 0 677 | ControllerPort: 0 678 | ControllerName: 0 679 | ThermalThrotter: 0 680 | I2cProtocol: 0 681 | I2cControllers 2: 682 | Enabled: 0 683 | Speed: 0 684 | Padding: 685 | Padding 0: 0 686 | Padding 1: 0 687 | SlaveAddress: 0 688 | ControllerPort: 0 689 | ControllerName: 0 690 | ThermalThrotter: 0 691 | I2cProtocol: 0 692 | I2cControllers 3: 693 | Enabled: 0 694 | Speed: 0 695 | Padding: 696 | Padding 0: 0 697 | Padding 1: 0 698 | SlaveAddress: 0 699 | ControllerPort: 0 700 | ControllerName: 0 701 | ThermalThrotter: 0 702 | I2cProtocol: 0 703 | I2cControllers 4: 704 | Enabled: 0 705 | Speed: 0 706 | Padding: 707 | Padding 0: 0 708 | Padding 1: 0 709 | SlaveAddress: 0 710 | ControllerPort: 0 711 | ControllerName: 0 712 | ThermalThrotter: 0 713 | I2cProtocol: 0 714 | I2cControllers 5: 715 | Enabled: 0 716 | Speed: 0 717 | Padding: 718 | Padding 0: 0 719 | Padding 1: 0 720 | SlaveAddress: 0 721 | ControllerPort: 0 722 | ControllerName: 0 723 | ThermalThrotter: 0 724 | I2cProtocol: 0 725 | I2cControllers 6: 726 | Enabled: 0 727 | Speed: 0 728 | Padding: 729 | Padding 0: 0 730 | Padding 1: 0 731 | SlaveAddress: 0 732 | ControllerPort: 0 733 | ControllerName: 0 734 | ThermalThrotter: 0 735 | I2cProtocol: 0 736 | I2cControllers 7: 737 | Enabled: 0 738 | Speed: 0 739 | Padding: 740 | Padding 0: 0 741 | Padding 1: 0 742 | SlaveAddress: 0 743 | ControllerPort: 0 744 | ControllerName: 0 745 | ThermalThrotter: 0 746 | I2cProtocol: 0 747 | MaxVoltageStepGfx: 0 748 | MaxVoltageStepSoc: 0 749 | VddGfxVrMapping: 0 750 | VddSocVrMapping: 0 751 | VddMem0VrMapping: 0 752 | VddMem1VrMapping: 0 753 | GfxUlvPhaseSheddingMask: 0 754 | SocUlvPhaseSheddingMask: 0 755 | ExternalSensorPresent: 0 756 | Padding8_V: 0 757 | GfxMaxCurrent: 0 758 | GfxOffset: 0 759 | Padding_TelemetryGfx: 0 760 | SocMaxCurrent: 0 761 | SocOffset: 0 762 | Padding_TelemetrySoc: 0 763 | Mem0MaxCurrent: 0 764 | Mem0Offset: 0 765 | Padding_TelemetryMem0: 0 766 | Mem1MaxCurrent: 0 767 | Mem1Offset: 0 768 | Padding_TelemetryMem1: 0 769 | AcDcGpio: 0 770 | AcDcPolarity: 0 771 | VR0HotGpio: 0 772 | VR0HotPolarity: 0 773 | VR1HotGpio: 0 774 | VR1HotPolarity: 0 775 | GthrGpio: 0 776 | GthrPolarity: 0 777 | LedPin0: 0 778 | LedPin1: 0 779 | LedPin2: 0 780 | padding8_4: 0 781 | PllGfxclkSpreadEnabled: 0 782 | PllGfxclkSpreadPercent: 0 783 | PllGfxclkSpreadFreq: 0 784 | DfllGfxclkSpreadEnabled: 0 785 | DfllGfxclkSpreadPercent: 0 786 | DfllGfxclkSpreadFreq: 0 787 | UclkSpreadEnabled: 0 788 | UclkSpreadPercent: 0 789 | UclkSpreadFreq: 0 790 | SoclkSpreadEnabled: 0 791 | SocclkSpreadPercent: 0 792 | SocclkSpreadFreq: 0 793 | TotalBoardPower: 0 794 | BoardPadding: 0 795 | MvddRatio: 0 796 | RenesesLoadLineEnabled: 0 797 | GfxLoadlineResistance: 0 798 | SocLoadlineResistance: 0 799 | Padding8_Loadline: 0 800 | BoardReserved: 801 | BoardReserved 0: 0 802 | BoardReserved 1: 0 803 | BoardReserved 2: 0 804 | BoardReserved 3: 0 805 | BoardReserved 4: 0 806 | BoardReserved 5: 0 807 | BoardReserved 6: 0 808 | BoardReserved 7: 0 809 | MmHubPadding: 810 | MmHubPadding 0: 0 811 | MmHubPadding 1: 0 812 | MmHubPadding 2: 0 813 | MmHubPadding 3: 0 814 | MmHubPadding 4: 0 815 | MmHubPadding 5: 0 816 | MmHubPadding 6: 0 817 | MmHubPadding 7: 0 818 | -------------------------------------------------------------------------------- /test/AMD.RXVega64.8176.170719.rom.dump: -------------------------------------------------------------------------------- 1 | sHeader: 2 | structuresize: 694 3 | format_revision: 8 4 | content_revision: 1 5 | TableRevision: 0 6 | TableSize: 92 7 | GoldenPPID: 1761 8 | GoldenRevision: 11246 9 | FormatID: 27 10 | PlatformCaps: 72 11 | MaxODEngineClock: 240000 12 | MaxODMemoryClock: 150000 13 | PowerControlLimit: 50 14 | UlvVoltageOffset: 8 15 | UlvSmnclkDid: 0 16 | UlvMp1clkDid: 0 17 | UlvGfxclkBypass: 0 18 | GfxclkSlewRate: 0 19 | GfxVoltageMode: 0 20 | SocVoltageMode: 0 21 | UclkVoltageMode: 0 22 | UvdVoltageMode: 0 23 | VceVoltageMode: 0 24 | Mp0VoltageMode: 2 25 | DcefVoltageMode: 1 26 | StateArray: 27 | RevId: 2 28 | NumEntries: 2 29 | states: 30 | states 0: 31 | SocClockIndexHigh: 0 32 | SocClockIndexLow: 0 33 | GfxClockIndexHigh: 0 34 | GfxClockIndexLow: 0 35 | MemClockIndexHigh: 0 36 | MemClockIndexLow: 0 37 | Classification: 8 38 | CapsAndSettings: 0 39 | Classification2: 0 40 | states 1: 41 | SocClockIndexHigh: 5 42 | SocClockIndexLow: 0 43 | GfxClockIndexHigh: 7 44 | GfxClockIndexLow: 0 45 | MemClockIndexHigh: 3 46 | MemClockIndexLow: 0 47 | Classification: 5 48 | CapsAndSettings: 0 49 | Classification2: 0 50 | FanTable: 51 | RevId: 11 52 | FanOutputSensitivity: 4836 53 | FanAcousticLimitRpm: 2400 54 | ThrottlingRPM: 2400 55 | TargetTemperature: 75 56 | MinimumPWMLimit: 10 57 | TargetGfxClk: 852 58 | FanGainEdge: 400 59 | FanGainHotspot: 400 60 | FanGainLiquid: 400 61 | FanGainVrVddc: 400 62 | FanGainVrMvdd: 400 63 | FanGainPlx: 400 64 | FanGainHbm: 400 65 | EnableZeroRPM: 0 66 | FanStopTemperature: 0 67 | FanStartTemperature: 0 68 | FanParameters: 2 69 | FanMinRPM: 4 70 | FanMaxRPM: 49 71 | ThermalController: 72 | RevId: 1 73 | Type: 24 74 | I2cLine: 0 75 | I2cAddress: 0 76 | FanParameters: 0 77 | FanMinRPM: 0 78 | FanMaxRPM: 0 79 | Flags: 0 80 | SocclkDependencyTable: 81 | RevId: 0 82 | NumEntries: 8 83 | entries: 84 | entries 0: 85 | Clk: 60000 86 | VddInd: 0 87 | entries 1: 88 | Clk: 72000 89 | VddInd: 1 90 | entries 2: 91 | Clk: 80000 92 | VddInd: 2 93 | entries 3: 94 | Clk: 84700 95 | VddInd: 3 96 | entries 4: 97 | Clk: 90000 98 | VddInd: 4 99 | entries 5: 100 | Clk: 96000 101 | VddInd: 5 102 | entries 6: 103 | Clk: 102800 104 | VddInd: 6 105 | entries 7: 106 | Clk: 110700 107 | VddInd: 7 108 | MclkDependencyTable: 109 | RevId: 1 110 | NumEntries: 4 111 | entries: 112 | entries 0: 113 | MemClk: 16700 114 | VddInd: 0 115 | VddMemInd: 0 116 | VddciInd: 0 117 | entries 1: 118 | MemClk: 50000 119 | VddInd: 0 120 | VddMemInd: 0 121 | VddciInd: 0 122 | entries 2: 123 | MemClk: 80000 124 | VddInd: 2 125 | VddMemInd: 0 126 | VddciInd: 0 127 | entries 3: 128 | MemClk: 94500 129 | VddInd: 4 130 | VddMemInd: 0 131 | VddciInd: 0 132 | GfxclkDependencyTable: 133 | RevId: 1 134 | NumEntries: 8 135 | entries: 136 | entries 0: 137 | Clk: 85200 138 | VddInd: 0 139 | CKSVOffsetandDisable: 32768 140 | AVFSOffset: 0 141 | ACGEnable: 0 142 | Reserved: 143 | Reserved 0: 0 144 | Reserved 1: 0 145 | Reserved 2: 0 146 | entries 1: 147 | Clk: 99100 148 | VddInd: 1 149 | CKSVOffsetandDisable: 0 150 | AVFSOffset: 0 151 | ACGEnable: 0 152 | Reserved: 153 | Reserved 0: 0 154 | Reserved 1: 0 155 | Reserved 2: 0 156 | entries 2: 157 | Clk: 108400 158 | VddInd: 2 159 | CKSVOffsetandDisable: 0 160 | AVFSOffset: 0 161 | ACGEnable: 0 162 | Reserved: 163 | Reserved 0: 0 164 | Reserved 1: 0 165 | Reserved 2: 0 166 | entries 3: 167 | Clk: 113800 168 | VddInd: 3 169 | CKSVOffsetandDisable: 0 170 | AVFSOffset: 0 171 | ACGEnable: 0 172 | Reserved: 173 | Reserved 0: 0 174 | Reserved 1: 0 175 | Reserved 2: 0 176 | entries 4: 177 | Clk: 120000 178 | VddInd: 4 179 | CKSVOffsetandDisable: 0 180 | AVFSOffset: 0 181 | ACGEnable: 0 182 | Reserved: 183 | Reserved 0: 0 184 | Reserved 1: 0 185 | Reserved 2: 0 186 | entries 5: 187 | Clk: 140100 188 | VddInd: 5 189 | CKSVOffsetandDisable: 0 190 | AVFSOffset: 0 191 | ACGEnable: 1 192 | Reserved: 193 | Reserved 0: 0 194 | Reserved 1: 0 195 | Reserved 2: 0 196 | entries 6: 197 | Clk: 153600 198 | VddInd: 6 199 | CKSVOffsetandDisable: 0 200 | AVFSOffset: 0 201 | ACGEnable: 1 202 | Reserved: 203 | Reserved 0: 0 204 | Reserved 1: 0 205 | Reserved 2: 0 206 | entries 7: 207 | Clk: 163000 208 | VddInd: 7 209 | CKSVOffsetandDisable: 0 210 | AVFSOffset: 0 211 | ACGEnable: 1 212 | Reserved: 213 | Reserved 0: 0 214 | Reserved 1: 0 215 | Reserved 2: 0 216 | DcefclkDependencyTable: 217 | RevId: 0 218 | NumEntries: 5 219 | entries: 220 | entries 0: 221 | Clk: 60000 222 | VddInd: 0 223 | entries 1: 224 | Clk: 72000 225 | VddInd: 0 226 | entries 2: 227 | Clk: 80000 228 | VddInd: 0 229 | entries 3: 230 | Clk: 84700 231 | VddInd: 0 232 | entries 4: 233 | Clk: 90000 234 | VddInd: 0 235 | VddcLookupTable: 236 | RevId: 1 237 | NumEntries: 8 238 | entries: 239 | entries 0: 240 | Vdd: 800 241 | entries 1: 242 | Vdd: 900 243 | entries 2: 244 | Vdd: 950 245 | entries 3: 246 | Vdd: 1000 247 | entries 4: 248 | Vdd: 1050 249 | entries 5: 250 | Vdd: 1100 251 | entries 6: 252 | Vdd: 1150 253 | entries 7: 254 | Vdd: 1200 255 | VddmemLookupTable: 256 | RevId: 1 257 | NumEntries: 1 258 | entries: 259 | entries 0: 260 | Vdd: 1350 261 | MMDependencyTable: 262 | RevId: 1 263 | NumEntries: 8 264 | entries: 265 | entries 0: 266 | VddcInd: 0 267 | DClk: 34200 268 | VClk: 46400 269 | EClk: 60000 270 | PSPClk: 50000 271 | entries 1: 272 | VddcInd: 1 273 | DClk: 48000 274 | VClk: 60000 275 | EClk: 68500 276 | PSPClk: 50000 277 | entries 2: 278 | VddcInd: 2 279 | DClk: 57600 280 | VClk: 68500 281 | EClk: 72000 282 | PSPClk: 50000 283 | entries 3: 284 | VddcInd: 3 285 | DClk: 65400 286 | VClk: 72000 287 | EClk: 75400 288 | PSPClk: 50000 289 | entries 4: 290 | VddcInd: 4 291 | DClk: 72000 292 | VClk: 80000 293 | EClk: 80000 294 | PSPClk: 50000 295 | entries 5: 296 | VddcInd: 5 297 | DClk: 80000 298 | VClk: 84700 299 | EClk: 84700 300 | PSPClk: 50000 301 | entries 6: 302 | VddcInd: 6 303 | DClk: 96000 304 | VClk: 96000 305 | EClk: 90000 306 | PSPClk: 50000 307 | entries 7: 308 | VddcInd: 7 309 | DClk: 102800 310 | VClk: 102800 311 | EClk: 96000 312 | PSPClk: 50000 313 | VCEStateTable: UNUSED 314 | Reserve: 0 315 | PowerTuneTable: 316 | RevId: 7 317 | SocketPowerLimit: 220 318 | BatteryPowerLimit: 220 319 | SmallPowerLimit: 220 320 | TdcLimit: 300 321 | EdcLimit: 0 322 | SoftwareShutdownTemp: 89 323 | TemperatureLimitHotSpot: 105 324 | TemperatureLimitLiquid1: 74 325 | TemperatureLimitLiquid2: 74 326 | TemperatureLimitHBM: 95 327 | TemperatureLimitVrSoc: 115 328 | TemperatureLimitVrMem: 115 329 | TemperatureLimitPlx: 100 330 | LoadLineResistance: 64 331 | Liquid1_I2C_address: 144 332 | Liquid2_I2C_address: 146 333 | Liquid_I2C_Line: 151 334 | Vr_I2C_address: 96 335 | Vr_I2C_Line: 150 336 | Plx_I2C_address: 0 337 | Plx_I2C_Line: 144 338 | TemperatureLimitTedge: 85 339 | BoostStartTemperature: 0 340 | BoostStopTemperature: 0 341 | BoostClock: 0 342 | Reserved: 343 | Reserved 0: 0 344 | Reserved 1: 0 345 | HardLimitTable: UNUSED 346 | VddciLookupTable: 347 | RevId: 1 348 | NumEntries: 1 349 | entries: 350 | entries 0: 351 | Vdd: 900 352 | PCIETable: 353 | RevId: 2 354 | NumEntries: 2 355 | entries: 356 | entries 0: 357 | LCLK: 12500 358 | PCIEGenSpeed: 2 359 | PCIELaneWidth: 16 360 | entries 1: 361 | LCLK: 60000 362 | PCIEGenSpeed: 2 363 | PCIELaneWidth: 16 364 | PixclkDependencyTable: 365 | RevId: 0 366 | NumEntries: 8 367 | entries: 368 | entries 0: 369 | Clk: 14700 370 | VddInd: 0 371 | entries 1: 372 | Clk: 24100 373 | VddInd: 1 374 | entries 2: 375 | Clk: 34300 376 | VddInd: 2 377 | entries 3: 378 | Clk: 48300 379 | VddInd: 3 380 | entries 4: 381 | Clk: 53300 382 | VddInd: 4 383 | entries 5: 384 | Clk: 93800 385 | VddInd: 5 386 | entries 6: 387 | Clk: 104200 388 | VddInd: 6 389 | entries 7: 390 | Clk: 107500 391 | VddInd: 7 392 | DispClkDependencyTable: 393 | RevId: 0 394 | NumEntries: 8 395 | entries: 396 | entries 0: 397 | Clk: 28200 398 | VddInd: 0 399 | entries 1: 400 | Clk: 51500 401 | VddInd: 1 402 | entries 2: 403 | Clk: 68600 404 | VddInd: 2 405 | entries 3: 406 | Clk: 80000 407 | VddInd: 3 408 | entries 4: 409 | Clk: 90000 410 | VddInd: 4 411 | entries 5: 412 | Clk: 102900 413 | VddInd: 5 414 | entries 6: 415 | Clk: 110800 416 | VddInd: 6 417 | entries 7: 418 | Clk: 120000 419 | VddInd: 7 420 | PhyClkDependencyTable: 421 | RevId: 0 422 | NumEntries: 1 423 | entries: 424 | entries 0: 425 | Clk: 81000 426 | VddInd: 0 427 | -------------------------------------------------------------------------------- /test/AMD.RXVega64.8176.170719.rom.rawdump: -------------------------------------------------------------------------------- 1 | PowerPlay table rev 8.1 size 694 bytes 2 | Offset (dec.) t Raw val. Variable name Decoded value 3 | ------------------------------------------------------------------------------ 4 | 0x0000 (0000) H b602 structuresize : 694 5 | 0x0002 (0002) B 08 format_revision : 8 6 | 0x0003 (0003) B 01 content_revision : 1 7 | 0x0004 (0004) B 00 TableRevision : 0 8 | 0x0005 (0005) H 5c00 TableSize : 92 9 | 0x0007 (0007) I e1060000 GoldenPPID : 1761 10 | 0x000b (0011) I ee2b0000 GoldenRevision : 11246 11 | 0x000f (0015) H 1b00 FormatID : 27 12 | 0x0011 (0017) I 48000000 PlatformCaps : 72 13 | 0x0015 (0021) I 80a90300 MaxODEngineClock : 240000 14 | 0x0019 (0025) I f0490200 MaxODMemoryClock : 150000 15 | 0x001d (0029) H 3200 PowerControlLimit : 50 16 | 0x001f (0031) H 0800 UlvVoltageOffset : 8 17 | 0x0021 (0033) H 0000 UlvSmnclkDid : 0 18 | 0x0023 (0035) H 0000 UlvMp1clkDid : 0 19 | 0x0025 (0037) H 0000 UlvGfxclkBypass : 0 20 | 0x0027 (0039) H 0000 GfxclkSlewRate : 0 21 | 0x0029 (0041) B 00 GfxVoltageMode : 0 22 | 0x002a (0042) B 00 SocVoltageMode : 0 23 | 0x002b (0043) B 00 UclkVoltageMode : 0 24 | 0x002c (0044) B 00 UvdVoltageMode : 0 25 | 0x002d (0045) B 00 VceVoltageMode : 0 26 | 0x002e (0046) B 02 Mp0VoltageMode : 2 27 | 0x002f (0047) B 01 DcefVoltageMode : 1 28 | 0x0030 (0048) H 5c00 StateArrayOffset : 92 29 | 0x005c (0092) B 02 RevId : 2 30 | 0x005d (0093) B 02 NumEntries : 2 31 | 0x005e (0094) B 00 SocClockIndexHigh : 0 32 | 0x005f (0095) B 00 SocClockIndexLow : 0 33 | 0x0060 (0096) B 00 GfxClockIndexHigh : 0 34 | 0x0061 (0097) B 00 GfxClockIndexLow : 0 35 | 0x0062 (0098) B 00 MemClockIndexHigh : 0 36 | 0x0063 (0099) B 00 MemClockIndexLow : 0 37 | 0x0064 (0100) H 0800 Classification : 8 38 | 0x0066 (0102) I 00000000 CapsAndSettings : 0 39 | 0x006a (0106) H 0000 Classification2 : 0 40 | 0x006c (0108) B 05 SocClockIndexHigh : 5 41 | 0x006d (0109) B 00 SocClockIndexLow : 0 42 | 0x006e (0110) B 07 GfxClockIndexHigh : 7 43 | 0x006f (0111) B 00 GfxClockIndexLow : 0 44 | 0x0070 (0112) B 03 MemClockIndexHigh : 3 45 | 0x0071 (0113) B 00 MemClockIndexLow : 0 46 | 0x0072 (0114) H 0500 Classification : 5 47 | 0x0074 (0116) I 00000000 CapsAndSettings : 0 48 | 0x0078 (0120) H 0000 Classification2 : 0 49 | 0x0032 (0050) H 4f02 FanTableOffset : 591 50 | 0x024f (0591) B 0b RevId : 11 51 | 0x0250 (0592) H e412 FanOutputSensitivity : 4836 52 | 0x0252 (0594) H 6009 FanAcousticLimitRpm : 2400 53 | 0x0254 (0596) H 6009 ThrottlingRPM : 2400 54 | 0x0256 (0598) H 4b00 TargetTemperature : 75 55 | 0x0258 (0600) H 0a00 MinimumPWMLimit : 10 56 | 0x025a (0602) H 5403 TargetGfxClk : 852 57 | 0x025c (0604) H 9001 FanGainEdge : 400 58 | 0x025e (0606) H 9001 FanGainHotspot : 400 59 | 0x0260 (0608) H 9001 FanGainLiquid : 400 60 | 0x0262 (0610) H 9001 FanGainVrVddc : 400 61 | 0x0264 (0612) H 9001 FanGainVrMvdd : 400 62 | 0x0266 (0614) H 9001 FanGainPlx : 400 63 | 0x0268 (0616) H 9001 FanGainHbm : 400 64 | 0x026a (0618) B 00 EnableZeroRPM : 0 65 | 0x026b (0619) H 0000 FanStopTemperature : 0 66 | 0x026d (0621) H 0000 FanStartTemperature : 0 67 | 0x026f (0623) B 02 FanParameters : 2 68 | 0x0270 (0624) B 04 FanMinRPM : 4 69 | 0x0271 (0625) B 31 FanMaxRPM : 49 70 | 0x0034 (0052) H 4602 ThermalControllerOffset : 582 71 | 0x0246 (0582) B 01 RevId : 1 72 | 0x0247 (0583) B 18 Type : 24 73 | 0x0248 (0584) B 00 I2cLine : 0 74 | 0x0249 (0585) B 00 I2cAddress : 0 75 | 0x024a (0586) B 00 FanParameters : 0 76 | 0x024b (0587) B 00 FanMinRPM : 0 77 | 0x024c (0588) B 00 FanMaxRPM : 0 78 | 0x024d (0589) B 00 Flags : 0 79 | 0x0036 (0054) H 9400 SocclkDependencyTableOffset : 148 80 | 0x0094 (0148) B 00 RevId : 0 81 | 0x0095 (0149) B 08 NumEntries : 8 82 | 0x0096 (0150) I 60ea0000 Clk : 60000 83 | 0x009a (0154) B 00 VddInd : 0 84 | 0x009b (0155) I 40190100 Clk : 72000 85 | 0x009f (0159) B 01 VddInd : 1 86 | 0x00a0 (0160) I 80380100 Clk : 80000 87 | 0x00a4 (0164) B 02 VddInd : 2 88 | 0x00a5 (0165) I dc4a0100 Clk : 84700 89 | 0x00a9 (0169) B 03 VddInd : 3 90 | 0x00aa (0170) I 905f0100 Clk : 90000 91 | 0x00ae (0174) B 04 VddInd : 4 92 | 0x00af (0175) I 00770100 Clk : 96000 93 | 0x00b3 (0179) B 05 VddInd : 5 94 | 0x00b4 (0180) I 90910100 Clk : 102800 95 | 0x00b8 (0184) B 06 VddInd : 6 96 | 0x00b9 (0185) I 6cb00100 Clk : 110700 97 | 0x00bd (0189) B 07 VddInd : 7 98 | 0x0038 (0056) H 9e01 MclkDependencyTableOffset : 414 99 | 0x019e (0414) B 01 RevId : 1 100 | 0x019f (0415) B 04 NumEntries : 4 101 | 0x01a0 (0416) I 3c410000 MemClk : 16700 102 | 0x01a4 (0420) B 00 VddInd : 0 103 | 0x01a5 (0421) B 00 VddMemInd : 0 104 | 0x01a6 (0422) B 00 VddciInd : 0 105 | 0x01a7 (0423) I 50c30000 MemClk : 50000 106 | 0x01ab (0427) B 00 VddInd : 0 107 | 0x01ac (0428) B 00 VddMemInd : 0 108 | 0x01ad (0429) B 00 VddciInd : 0 109 | 0x01ae (0430) I 80380100 MemClk : 80000 110 | 0x01b2 (0434) B 02 VddInd : 2 111 | 0x01b3 (0435) B 00 VddMemInd : 0 112 | 0x01b4 (0436) B 00 VddciInd : 0 113 | 0x01b5 (0437) I 24710100 MemClk : 94500 114 | 0x01b9 (0441) B 04 VddInd : 4 115 | 0x01ba (0442) B 00 VddMemInd : 0 116 | 0x01bb (0443) B 00 VddciInd : 0 117 | 0x003a (0058) H be00 GfxclkDependencyTableOffset : 190 118 | 0x00be (0190) B 01 RevId : 1 119 | 0x00bf (0191) B 08 NumEntries : 8 120 | 0x00c0 (0192) I d04c0100 Clk : 85200 121 | 0x00c4 (0196) B 00 VddInd : 0 122 | 0x00c5 (0197) H 0080 CKSVOffsetandDisable : 32768 123 | 0x00c7 (0199) H 0000 AVFSOffset : 0 124 | 0x00c9 (0201) B 00 ACGEnable : 0 125 | 0x00ca (0202) B 00 Reserved : 0 126 | 0x00cb (0203) B 00 Reserved : 0 127 | 0x00cc (0204) B 00 Reserved : 0 128 | 0x00cd (0205) I 1c830100 Clk : 99100 129 | 0x00d1 (0209) B 01 VddInd : 1 130 | 0x00d2 (0210) H 0000 CKSVOffsetandDisable : 0 131 | 0x00d4 (0212) H 0000 AVFSOffset : 0 132 | 0x00d6 (0214) B 00 ACGEnable : 0 133 | 0x00d7 (0215) B 00 Reserved : 0 134 | 0x00d8 (0216) B 00 Reserved : 0 135 | 0x00d9 (0217) B 00 Reserved : 0 136 | 0x00da (0218) I 70a70100 Clk : 108400 137 | 0x00de (0222) B 02 VddInd : 2 138 | 0x00df (0223) H 0000 CKSVOffsetandDisable : 0 139 | 0x00e1 (0225) H 0000 AVFSOffset : 0 140 | 0x00e3 (0227) B 00 ACGEnable : 0 141 | 0x00e4 (0228) B 00 Reserved : 0 142 | 0x00e5 (0229) B 00 Reserved : 0 143 | 0x00e6 (0230) B 00 Reserved : 0 144 | 0x00e7 (0231) I 88bc0100 Clk : 113800 145 | 0x00eb (0235) B 03 VddInd : 3 146 | 0x00ec (0236) H 0000 CKSVOffsetandDisable : 0 147 | 0x00ee (0238) H 0000 AVFSOffset : 0 148 | 0x00f0 (0240) B 00 ACGEnable : 0 149 | 0x00f1 (0241) B 00 Reserved : 0 150 | 0x00f2 (0242) B 00 Reserved : 0 151 | 0x00f3 (0243) B 00 Reserved : 0 152 | 0x00f4 (0244) I c0d40100 Clk : 120000 153 | 0x00f8 (0248) B 04 VddInd : 4 154 | 0x00f9 (0249) H 0000 CKSVOffsetandDisable : 0 155 | 0x00fb (0251) H 0000 AVFSOffset : 0 156 | 0x00fd (0253) B 00 ACGEnable : 0 157 | 0x00fe (0254) B 00 Reserved : 0 158 | 0x00ff (0255) B 00 Reserved : 0 159 | 0x0100 (0256) B 00 Reserved : 0 160 | 0x0101 (0257) I 44230200 Clk : 140100 161 | 0x0105 (0261) B 05 VddInd : 5 162 | 0x0106 (0262) H 0000 CKSVOffsetandDisable : 0 163 | 0x0108 (0264) H 0000 AVFSOffset : 0 164 | 0x010a (0266) B 01 ACGEnable : 1 165 | 0x010b (0267) B 00 Reserved : 0 166 | 0x010c (0268) B 00 Reserved : 0 167 | 0x010d (0269) B 00 Reserved : 0 168 | 0x010e (0270) I 00580200 Clk : 153600 169 | 0x0112 (0274) B 06 VddInd : 6 170 | 0x0113 (0275) H 0000 CKSVOffsetandDisable : 0 171 | 0x0115 (0277) H 0000 AVFSOffset : 0 172 | 0x0117 (0279) B 01 ACGEnable : 1 173 | 0x0118 (0280) B 00 Reserved : 0 174 | 0x0119 (0281) B 00 Reserved : 0 175 | 0x011a (0282) B 00 Reserved : 0 176 | 0x011b (0283) I b87c0200 Clk : 163000 177 | 0x011f (0287) B 07 VddInd : 7 178 | 0x0120 (0288) H 0000 CKSVOffsetandDisable : 0 179 | 0x0122 (0290) H 0000 AVFSOffset : 0 180 | 0x0124 (0292) B 01 ACGEnable : 1 181 | 0x0125 (0293) B 00 Reserved : 0 182 | 0x0126 (0294) B 00 Reserved : 0 183 | 0x0127 (0295) B 00 Reserved : 0 184 | 0x003c (0060) H 2801 DcefclkDependencyTableOffset : 296 185 | 0x0128 (0296) B 00 RevId : 0 186 | 0x0129 (0297) B 05 NumEntries : 5 187 | 0x012a (0298) I 60ea0000 Clk : 60000 188 | 0x012e (0302) B 00 VddInd : 0 189 | 0x012f (0303) I 40190100 Clk : 72000 190 | 0x0133 (0307) B 00 VddInd : 0 191 | 0x0134 (0308) I 80380100 Clk : 80000 192 | 0x0138 (0312) B 00 VddInd : 0 193 | 0x0139 (0313) I dc4a0100 Clk : 84700 194 | 0x013d (0317) B 00 VddInd : 0 195 | 0x013e (0318) I 905f0100 Clk : 90000 196 | 0x0142 (0322) B 00 VddInd : 0 197 | 0x003e (0062) H 7a00 VddcLookupTableOffset : 122 198 | 0x007a (0122) B 01 RevId : 1 199 | 0x007b (0123) B 08 NumEntries : 8 200 | 0x007c (0124) H 2003 Vdd : 800 201 | 0x007e (0126) H 8403 Vdd : 900 202 | 0x0080 (0128) H b603 Vdd : 950 203 | 0x0082 (0130) H e803 Vdd : 1000 204 | 0x0084 (0132) H 1a04 Vdd : 1050 205 | 0x0086 (0134) H 4c04 Vdd : 1100 206 | 0x0088 (0136) H 7e04 Vdd : 1150 207 | 0x008a (0138) H b004 Vdd : 1200 208 | 0x0040 (0064) H 8c00 VddmemLookupTableOffset : 140 209 | 0x008c (0140) B 01 RevId : 1 210 | 0x008d (0141) B 01 NumEntries : 1 211 | 0x008e (0142) H 4605 Vdd : 1350 212 | 0x0042 (0066) H bc01 MMDependencyTableOffset : 444 213 | 0x01bc (0444) B 01 RevId : 1 214 | 0x01bd (0445) B 08 NumEntries : 8 215 | 0x01be (0446) B 00 VddcInd : 0 216 | 0x01bf (0447) I 98850000 DClk : 34200 217 | 0x01c3 (0451) I 40b50000 VClk : 46400 218 | 0x01c7 (0455) I 60ea0000 EClk : 60000 219 | 0x01cb (0459) I 50c30000 PSPClk : 50000 220 | 0x01cf (0463) B 01 VddcInd : 1 221 | 0x01d0 (0464) I 80bb0000 DClk : 48000 222 | 0x01d4 (0468) I 60ea0000 VClk : 60000 223 | 0x01d8 (0472) I 940b0100 EClk : 68500 224 | 0x01dc (0476) I 50c30000 PSPClk : 50000 225 | 0x01e0 (0480) B 02 VddcInd : 2 226 | 0x01e1 (0481) I 00e10000 DClk : 57600 227 | 0x01e5 (0485) I 940b0100 VClk : 68500 228 | 0x01e9 (0489) I 40190100 EClk : 72000 229 | 0x01ed (0493) I 50c30000 PSPClk : 50000 230 | 0x01f1 (0497) B 03 VddcInd : 3 231 | 0x01f2 (0498) I 78ff0000 DClk : 65400 232 | 0x01f6 (0502) I 40190100 VClk : 72000 233 | 0x01fa (0506) I 88260100 EClk : 75400 234 | 0x01fe (0510) I 50c30000 PSPClk : 50000 235 | 0x0202 (0514) B 04 VddcInd : 4 236 | 0x0203 (0515) I 40190100 DClk : 72000 237 | 0x0207 (0519) I 80380100 VClk : 80000 238 | 0x020b (0523) I 80380100 EClk : 80000 239 | 0x020f (0527) I 50c30000 PSPClk : 50000 240 | 0x0213 (0531) B 05 VddcInd : 5 241 | 0x0214 (0532) I 80380100 DClk : 80000 242 | 0x0218 (0536) I dc4a0100 VClk : 84700 243 | 0x021c (0540) I dc4a0100 EClk : 84700 244 | 0x0220 (0544) I 50c30000 PSPClk : 50000 245 | 0x0224 (0548) B 06 VddcInd : 6 246 | 0x0225 (0549) I 00770100 DClk : 96000 247 | 0x0229 (0553) I 00770100 VClk : 96000 248 | 0x022d (0557) I 905f0100 EClk : 90000 249 | 0x0231 (0561) I 50c30000 PSPClk : 50000 250 | 0x0235 (0565) B 07 VddcInd : 7 251 | 0x0236 (0566) I 90910100 DClk : 102800 252 | 0x023a (0570) I 90910100 VClk : 102800 253 | 0x023e (0574) I 00770100 EClk : 96000 254 | 0x0242 (0578) I 50c30000 PSPClk : 50000 255 | 0x0044 (0068) H 0000 VCEStateTableOffset : 0 256 | 0x0046 (0070) H 0000 Reserve : 0 257 | 0x0048 (0072) H 7202 PowerTuneTableOffset : 626 258 | 0x0272 (0626) B 07 RevId : 7 259 | 0x0273 (0627) H dc00 SocketPowerLimit : 220 260 | 0x0275 (0629) H dc00 BatteryPowerLimit : 220 261 | 0x0277 (0631) H dc00 SmallPowerLimit : 220 262 | 0x0279 (0633) H 2c01 TdcLimit : 300 263 | 0x027b (0635) H 0000 EdcLimit : 0 264 | 0x027d (0637) H 5900 SoftwareShutdownTemp : 89 265 | 0x027f (0639) H 6900 TemperatureLimitHotSpot : 105 266 | 0x0281 (0641) H 4a00 TemperatureLimitLiquid1 : 74 267 | 0x0283 (0643) H 4a00 TemperatureLimitLiquid2 : 74 268 | 0x0285 (0645) H 5f00 TemperatureLimitHBM : 95 269 | 0x0287 (0647) H 7300 TemperatureLimitVrSoc : 115 270 | 0x0289 (0649) H 7300 TemperatureLimitVrMem : 115 271 | 0x028b (0651) H 6400 TemperatureLimitPlx : 100 272 | 0x028d (0653) H 4000 LoadLineResistance : 64 273 | 0x028f (0655) B 90 Liquid1_I2C_address : 144 274 | 0x0290 (0656) B 92 Liquid2_I2C_address : 146 275 | 0x0291 (0657) B 97 Liquid_I2C_Line : 151 276 | 0x0292 (0658) B 60 Vr_I2C_address : 96 277 | 0x0293 (0659) B 96 Vr_I2C_Line : 150 278 | 0x0294 (0660) B 00 Plx_I2C_address : 0 279 | 0x0295 (0661) B 90 Plx_I2C_Line : 144 280 | 0x0296 (0662) H 5500 TemperatureLimitTedge : 85 281 | 0x0298 (0664) H 0000 BoostStartTemperature : 0 282 | 0x029a (0666) H 0000 BoostStopTemperature : 0 283 | 0x029c (0668) I 00000000 BoostClock : 0 284 | 0x02a0 (0672) I 00000000 Reserved : 0 285 | 0x02a4 (0676) I 00000000 Reserved : 0 286 | 0x004a (0074) H 0000 HardLimitTableOffset : 0 287 | 0x004c (0076) H 9000 VddciLookupTableOffset : 144 288 | 0x0090 (0144) B 01 RevId : 1 289 | 0x0091 (0145) B 01 NumEntries : 1 290 | 0x0092 (0146) H 8403 Vdd : 900 291 | 0x004e (0078) H a802 PCIETableOffset : 680 292 | 0x02a8 (0680) B 02 RevId : 2 293 | 0x02a9 (0681) B 02 NumEntries : 2 294 | 0x02aa (0682) I d4300000 LCLK : 12500 295 | 0x02ae (0686) B 02 PCIEGenSpeed : 2 296 | 0x02af (0687) B 10 PCIELaneWidth : 16 297 | 0x02b0 (0688) I 60ea0000 LCLK : 60000 298 | 0x02b4 (0692) B 02 PCIEGenSpeed : 2 299 | 0x02b5 (0693) B 10 PCIELaneWidth : 16 300 | 0x0050 (0080) H 6d01 PixclkDependencyTableOffset : 365 301 | 0x016d (0365) B 00 RevId : 0 302 | 0x016e (0366) B 08 NumEntries : 8 303 | 0x016f (0367) I 6c390000 Clk : 14700 304 | 0x0173 (0371) B 00 VddInd : 0 305 | 0x0174 (0372) I 245e0000 Clk : 24100 306 | 0x0178 (0376) B 01 VddInd : 1 307 | 0x0179 (0377) I fc850000 Clk : 34300 308 | 0x017d (0381) B 02 VddInd : 2 309 | 0x017e (0382) I acbc0000 Clk : 48300 310 | 0x0182 (0386) B 03 VddInd : 3 311 | 0x0183 (0387) I 34d00000 Clk : 53300 312 | 0x0187 (0391) B 04 VddInd : 4 313 | 0x0188 (0392) I 686e0100 Clk : 93800 314 | 0x018c (0396) B 05 VddInd : 5 315 | 0x018d (0397) I 08970100 Clk : 104200 316 | 0x0191 (0401) B 06 VddInd : 6 317 | 0x0192 (0402) I eca30100 Clk : 107500 318 | 0x0196 (0406) B 07 VddInd : 7 319 | 0x0052 (0082) H 4301 DispClkDependencyTableOffset : 323 320 | 0x0143 (0323) B 00 RevId : 0 321 | 0x0144 (0324) B 08 NumEntries : 8 322 | 0x0145 (0325) I 286e0000 Clk : 28200 323 | 0x0149 (0329) B 00 VddInd : 0 324 | 0x014a (0330) I 2cc90000 Clk : 51500 325 | 0x014e (0334) B 01 VddInd : 1 326 | 0x014f (0335) I f80b0100 Clk : 68600 327 | 0x0153 (0339) B 02 VddInd : 2 328 | 0x0154 (0340) I 80380100 Clk : 80000 329 | 0x0158 (0344) B 03 VddInd : 3 330 | 0x0159 (0345) I 905f0100 Clk : 90000 331 | 0x015d (0349) B 04 VddInd : 4 332 | 0x015e (0350) I f4910100 Clk : 102900 333 | 0x0162 (0354) B 05 VddInd : 5 334 | 0x0163 (0355) I d0b00100 Clk : 110800 335 | 0x0167 (0359) B 06 VddInd : 6 336 | 0x0168 (0360) I c0d40100 Clk : 120000 337 | 0x016c (0364) B 07 VddInd : 7 338 | 0x0054 (0084) H 9701 PhyClkDependencyTableOffset : 407 339 | 0x0197 (0407) B 00 RevId : 0 340 | 0x0198 (0408) B 01 NumEntries : 1 341 | 0x0199 (0409) I 683c0100 Clk : 81000 342 | 0x019d (0413) B 00 VddInd : 0 343 | -------------------------------------------------------------------------------- /test/AMD.RXVegaFrontier.16384.170628.rom.dump: -------------------------------------------------------------------------------- 1 | sHeader: 2 | structuresize: 642 3 | format_revision: 8 4 | content_revision: 1 5 | TableRevision: 0 6 | TableSize: 92 7 | GoldenPPID: 1810 8 | GoldenRevision: 11069 9 | FormatID: 27 10 | PlatformCaps: 72 11 | MaxODEngineClock: 240000 12 | MaxODMemoryClock: 150000 13 | PowerControlLimit: 50 14 | UlvVoltageOffset: 8 15 | UlvSmnclkDid: 0 16 | UlvMp1clkDid: 0 17 | UlvGfxclkBypass: 0 18 | GfxclkSlewRate: 0 19 | GfxVoltageMode: 0 20 | SocVoltageMode: 0 21 | UclkVoltageMode: 0 22 | UvdVoltageMode: 0 23 | VceVoltageMode: 0 24 | Mp0VoltageMode: 2 25 | DcefVoltageMode: 1 26 | StateArray: 27 | RevId: 2 28 | NumEntries: 2 29 | states: 30 | states 0: 31 | SocClockIndexHigh: 0 32 | SocClockIndexLow: 0 33 | GfxClockIndexHigh: 0 34 | GfxClockIndexLow: 0 35 | MemClockIndexHigh: 0 36 | MemClockIndexLow: 0 37 | Classification: 8 38 | CapsAndSettings: 0 39 | Classification2: 0 40 | states 1: 41 | SocClockIndexHigh: 5 42 | SocClockIndexLow: 0 43 | GfxClockIndexHigh: 7 44 | GfxClockIndexLow: 0 45 | MemClockIndexHigh: 3 46 | MemClockIndexLow: 0 47 | Classification: 5 48 | CapsAndSettings: 0 49 | Classification2: 0 50 | FanTable: 51 | RevId: 11 52 | FanOutputSensitivity: 4836 53 | FanAcousticLimitRpm: 1500 54 | ThrottlingRPM: 2300 55 | TargetTemperature: 65 56 | MinimumPWMLimit: 15 57 | TargetGfxClk: 852 58 | FanGainEdge: 400 59 | FanGainHotspot: 400 60 | FanGainLiquid: 400 61 | FanGainVrVddc: 400 62 | FanGainVrMvdd: 400 63 | FanGainPlx: 400 64 | FanGainHbm: 400 65 | EnableZeroRPM: 0 66 | FanStopTemperature: 0 67 | FanStartTemperature: 0 68 | FanParameters: 2 69 | FanMinRPM: 4 70 | FanMaxRPM: 33 71 | ThermalController: 72 | RevId: 1 73 | Type: 24 74 | I2cLine: 0 75 | I2cAddress: 0 76 | FanParameters: 0 77 | FanMinRPM: 0 78 | FanMaxRPM: 0 79 | Flags: 0 80 | SocclkDependencyTable: 81 | RevId: 0 82 | NumEntries: 6 83 | entries: 84 | entries 0: 85 | Clk: 60000 86 | VddInd: 0 87 | entries 1: 88 | Clk: 72000 89 | VddInd: 1 90 | entries 2: 91 | Clk: 84700 92 | VddInd: 2 93 | entries 3: 94 | Clk: 96000 95 | VddInd: 3 96 | entries 4: 97 | Clk: 102800 98 | VddInd: 4 99 | entries 5: 100 | Clk: 110700 101 | VddInd: 5 102 | MclkDependencyTable: 103 | RevId: 1 104 | NumEntries: 4 105 | entries: 106 | entries 0: 107 | MemClk: 16700 108 | VddInd: 0 109 | VddMemInd: 0 110 | VddciInd: 0 111 | entries 1: 112 | MemClk: 50000 113 | VddInd: 1 114 | VddMemInd: 0 115 | VddciInd: 0 116 | entries 2: 117 | MemClk: 80000 118 | VddInd: 2 119 | VddMemInd: 0 120 | VddciInd: 0 121 | entries 3: 122 | MemClk: 94500 123 | VddInd: 3 124 | VddMemInd: 0 125 | VddciInd: 0 126 | GfxclkDependencyTable: 127 | RevId: 0 128 | NumEntries: 8 129 | entries: 130 | entries 0: 131 | Clk: 85200 132 | VddInd: 0 133 | CKSVOffsetandDisable: 32768 134 | AVFSOffset: 0 135 | entries 1: 136 | Clk: 99100 137 | VddInd: 1 138 | CKSVOffsetandDisable: 0 139 | AVFSOffset: 0 140 | entries 2: 141 | Clk: 113800 142 | VddInd: 2 143 | CKSVOffsetandDisable: 0 144 | AVFSOffset: 0 145 | entries 3: 146 | Clk: 126900 147 | VddInd: 3 148 | CKSVOffsetandDisable: 0 149 | AVFSOffset: 0 150 | entries 4: 151 | Clk: 134800 152 | VddInd: 4 153 | CKSVOffsetandDisable: 0 154 | AVFSOffset: 0 155 | entries 5: 156 | Clk: 144000 157 | VddInd: 5 158 | CKSVOffsetandDisable: 0 159 | AVFSOffset: 0 160 | entries 6: 161 | Clk: 152800 162 | VddInd: 6 163 | CKSVOffsetandDisable: 0 164 | AVFSOffset: 0 165 | entries 7: 166 | Clk: 160000 167 | VddInd: 7 168 | CKSVOffsetandDisable: 0 169 | AVFSOffset: 0 170 | DcefclkDependencyTable: 171 | RevId: 0 172 | NumEntries: 3 173 | entries: 174 | entries 0: 175 | Clk: 60000 176 | VddInd: 0 177 | entries 1: 178 | Clk: 72000 179 | VddInd: 0 180 | entries 2: 181 | Clk: 80000 182 | VddInd: 0 183 | VddcLookupTable: 184 | RevId: 1 185 | NumEntries: 8 186 | entries: 187 | entries 0: 188 | Vdd: 800 189 | entries 1: 190 | Vdd: 900 191 | entries 2: 192 | Vdd: 950 193 | entries 3: 194 | Vdd: 1000 195 | entries 4: 196 | Vdd: 1050 197 | entries 5: 198 | Vdd: 1100 199 | entries 6: 200 | Vdd: 1150 201 | entries 7: 202 | Vdd: 1200 203 | VddmemLookupTable: 204 | RevId: 1 205 | NumEntries: 1 206 | entries: 207 | entries 0: 208 | Vdd: 1350 209 | MMDependencyTable: 210 | RevId: 1 211 | NumEntries: 8 212 | entries: 213 | entries 0: 214 | VddcInd: 0 215 | DClk: 34200 216 | VClk: 46200 217 | EClk: 60000 218 | PSPClk: 50000 219 | entries 1: 220 | VddcInd: 1 221 | DClk: 48000 222 | VClk: 60000 223 | EClk: 68500 224 | PSPClk: 50000 225 | entries 2: 226 | VddcInd: 2 227 | DClk: 65400 228 | VClk: 72000 229 | EClk: 75700 230 | PSPClk: 50000 231 | entries 3: 232 | VddcInd: 3 233 | DClk: 75700 234 | VClk: 84700 235 | EClk: 84700 236 | PSPClk: 50000 237 | entries 4: 238 | VddcInd: 4 239 | DClk: 84700 240 | VClk: 90000 241 | EClk: 90000 242 | PSPClk: 50000 243 | entries 5: 244 | VddcInd: 5 245 | DClk: 96000 246 | VClk: 102800 247 | EClk: 96000 248 | PSPClk: 50000 249 | entries 6: 250 | VddcInd: 6 251 | DClk: 102800 252 | VClk: 110700 253 | EClk: 96000 254 | PSPClk: 50000 255 | entries 7: 256 | VddcInd: 7 257 | DClk: 110700 258 | VClk: 110700 259 | EClk: 102800 260 | PSPClk: 50000 261 | VCEStateTable: UNUSED 262 | Reserve: 0 263 | PowerTuneTable: 264 | RevId: 7 265 | SocketPowerLimit: 220 266 | BatteryPowerLimit: 220 267 | SmallPowerLimit: 220 268 | TdcLimit: 300 269 | EdcLimit: 0 270 | SoftwareShutdownTemp: 74 271 | TemperatureLimitHotSpot: 105 272 | TemperatureLimitLiquid1: 74 273 | TemperatureLimitLiquid2: 74 274 | TemperatureLimitHBM: 95 275 | TemperatureLimitVrSoc: 115 276 | TemperatureLimitVrMem: 115 277 | TemperatureLimitPlx: 100 278 | LoadLineResistance: 64 279 | Liquid1_I2C_address: 144 280 | Liquid2_I2C_address: 146 281 | Liquid_I2C_Line: 151 282 | Vr_I2C_address: 96 283 | Vr_I2C_Line: 150 284 | Plx_I2C_address: 0 285 | Plx_I2C_Line: 144 286 | TemperatureLimitTedge: 70 287 | BoostStartTemperature: 0 288 | BoostStopTemperature: 0 289 | BoostClock: 0 290 | Reserved: 291 | Reserved 0: 0 292 | Reserved 1: 0 293 | HardLimitTable: UNUSED 294 | VddciLookupTable: 295 | RevId: 1 296 | NumEntries: 1 297 | entries: 298 | entries 0: 299 | Vdd: 900 300 | PCIETable: 301 | RevId: 2 302 | NumEntries: 2 303 | entries: 304 | entries 0: 305 | LCLK: 12500 306 | PCIEGenSpeed: 2 307 | PCIELaneWidth: 16 308 | entries 1: 309 | LCLK: 60000 310 | PCIEGenSpeed: 2 311 | PCIELaneWidth: 16 312 | PixclkDependencyTable: 313 | RevId: 0 314 | NumEntries: 8 315 | entries: 316 | entries 0: 317 | Clk: 14700 318 | VddInd: 0 319 | entries 1: 320 | Clk: 24100 321 | VddInd: 1 322 | entries 2: 323 | Clk: 34300 324 | VddInd: 2 325 | entries 3: 326 | Clk: 48300 327 | VddInd: 3 328 | entries 4: 329 | Clk: 53300 330 | VddInd: 4 331 | entries 5: 332 | Clk: 93800 333 | VddInd: 5 334 | entries 6: 335 | Clk: 104200 336 | VddInd: 6 337 | entries 7: 338 | Clk: 107500 339 | VddInd: 7 340 | DispClkDependencyTable: 341 | RevId: 0 342 | NumEntries: 8 343 | entries: 344 | entries 0: 345 | Clk: 28200 346 | VddInd: 0 347 | entries 1: 348 | Clk: 51500 349 | VddInd: 1 350 | entries 2: 351 | Clk: 68600 352 | VddInd: 2 353 | entries 3: 354 | Clk: 80000 355 | VddInd: 3 356 | entries 4: 357 | Clk: 90000 358 | VddInd: 4 359 | entries 5: 360 | Clk: 102900 361 | VddInd: 5 362 | entries 6: 363 | Clk: 110800 364 | VddInd: 6 365 | entries 7: 366 | Clk: 120000 367 | VddInd: 7 368 | PhyClkDependencyTable: 369 | RevId: 0 370 | NumEntries: 1 371 | entries: 372 | entries 0: 373 | Clk: 81000 374 | VddInd: 0 375 | -------------------------------------------------------------------------------- /test/AMD.RXVegaFrontier.16384.170628.rom.rawdump: -------------------------------------------------------------------------------- 1 | PowerPlay table rev 8.1 size 642 bytes 2 | Offset (dec.) t Raw val. Variable name Decoded value 3 | ------------------------------------------------------------------------------ 4 | 0x0000 (0000) H 8202 structuresize : 642 5 | 0x0002 (0002) B 08 format_revision : 8 6 | 0x0003 (0003) B 01 content_revision : 1 7 | 0x0004 (0004) B 00 TableRevision : 0 8 | 0x0005 (0005) H 5c00 TableSize : 92 9 | 0x0007 (0007) I 12070000 GoldenPPID : 1810 10 | 0x000b (0011) I 3d2b0000 GoldenRevision : 11069 11 | 0x000f (0015) H 1b00 FormatID : 27 12 | 0x0011 (0017) I 48000000 PlatformCaps : 72 13 | 0x0015 (0021) I 80a90300 MaxODEngineClock : 240000 14 | 0x0019 (0025) I f0490200 MaxODMemoryClock : 150000 15 | 0x001d (0029) H 3200 PowerControlLimit : 50 16 | 0x001f (0031) H 0800 UlvVoltageOffset : 8 17 | 0x0021 (0033) H 0000 UlvSmnclkDid : 0 18 | 0x0023 (0035) H 0000 UlvMp1clkDid : 0 19 | 0x0025 (0037) H 0000 UlvGfxclkBypass : 0 20 | 0x0027 (0039) H 0000 GfxclkSlewRate : 0 21 | 0x0029 (0041) B 00 GfxVoltageMode : 0 22 | 0x002a (0042) B 00 SocVoltageMode : 0 23 | 0x002b (0043) B 00 UclkVoltageMode : 0 24 | 0x002c (0044) B 00 UvdVoltageMode : 0 25 | 0x002d (0045) B 00 VceVoltageMode : 0 26 | 0x002e (0046) B 02 Mp0VoltageMode : 2 27 | 0x002f (0047) B 01 DcefVoltageMode : 1 28 | 0x0030 (0048) H 5c00 StateArrayOffset : 92 29 | 0x005c (0092) B 02 RevId : 2 30 | 0x005d (0093) B 02 NumEntries : 2 31 | 0x005e (0094) B 00 SocClockIndexHigh : 0 32 | 0x005f (0095) B 00 SocClockIndexLow : 0 33 | 0x0060 (0096) B 00 GfxClockIndexHigh : 0 34 | 0x0061 (0097) B 00 GfxClockIndexLow : 0 35 | 0x0062 (0098) B 00 MemClockIndexHigh : 0 36 | 0x0063 (0099) B 00 MemClockIndexLow : 0 37 | 0x0064 (0100) H 0800 Classification : 8 38 | 0x0066 (0102) I 00000000 CapsAndSettings : 0 39 | 0x006a (0106) H 0000 Classification2 : 0 40 | 0x006c (0108) B 05 SocClockIndexHigh : 5 41 | 0x006d (0109) B 00 SocClockIndexLow : 0 42 | 0x006e (0110) B 07 GfxClockIndexHigh : 7 43 | 0x006f (0111) B 00 GfxClockIndexLow : 0 44 | 0x0070 (0112) B 03 MemClockIndexHigh : 3 45 | 0x0071 (0113) B 00 MemClockIndexLow : 0 46 | 0x0072 (0114) H 0500 Classification : 5 47 | 0x0074 (0116) I 00000000 CapsAndSettings : 0 48 | 0x0078 (0120) H 0000 Classification2 : 0 49 | 0x0032 (0050) H 1b02 FanTableOffset : 539 50 | 0x021b (0539) B 0b RevId : 11 51 | 0x021c (0540) H e412 FanOutputSensitivity : 4836 52 | 0x021e (0542) H dc05 FanAcousticLimitRpm : 1500 53 | 0x0220 (0544) H fc08 ThrottlingRPM : 2300 54 | 0x0222 (0546) H 4100 TargetTemperature : 65 55 | 0x0224 (0548) H 0f00 MinimumPWMLimit : 15 56 | 0x0226 (0550) H 5403 TargetGfxClk : 852 57 | 0x0228 (0552) H 9001 FanGainEdge : 400 58 | 0x022a (0554) H 9001 FanGainHotspot : 400 59 | 0x022c (0556) H 9001 FanGainLiquid : 400 60 | 0x022e (0558) H 9001 FanGainVrVddc : 400 61 | 0x0230 (0560) H 9001 FanGainVrMvdd : 400 62 | 0x0232 (0562) H 9001 FanGainPlx : 400 63 | 0x0234 (0564) H 9001 FanGainHbm : 400 64 | 0x0236 (0566) B 00 EnableZeroRPM : 0 65 | 0x0237 (0567) H 0000 FanStopTemperature : 0 66 | 0x0239 (0569) H 0000 FanStartTemperature : 0 67 | 0x023b (0571) B 02 FanParameters : 2 68 | 0x023c (0572) B 04 FanMinRPM : 4 69 | 0x023d (0573) B 21 FanMaxRPM : 33 70 | 0x0034 (0052) H 1202 ThermalControllerOffset : 530 71 | 0x0212 (0530) B 01 RevId : 1 72 | 0x0213 (0531) B 18 Type : 24 73 | 0x0214 (0532) B 00 I2cLine : 0 74 | 0x0215 (0533) B 00 I2cAddress : 0 75 | 0x0216 (0534) B 00 FanParameters : 0 76 | 0x0217 (0535) B 00 FanMinRPM : 0 77 | 0x0218 (0536) B 00 FanMaxRPM : 0 78 | 0x0219 (0537) B 00 Flags : 0 79 | 0x0036 (0054) H 9400 SocclkDependencyTableOffset : 148 80 | 0x0094 (0148) B 00 RevId : 0 81 | 0x0095 (0149) B 06 NumEntries : 6 82 | 0x0096 (0150) I 60ea0000 Clk : 60000 83 | 0x009a (0154) B 00 VddInd : 0 84 | 0x009b (0155) I 40190100 Clk : 72000 85 | 0x009f (0159) B 01 VddInd : 1 86 | 0x00a0 (0160) I dc4a0100 Clk : 84700 87 | 0x00a4 (0164) B 02 VddInd : 2 88 | 0x00a5 (0165) I 00770100 Clk : 96000 89 | 0x00a9 (0169) B 03 VddInd : 3 90 | 0x00aa (0170) I 90910100 Clk : 102800 91 | 0x00ae (0174) B 04 VddInd : 4 92 | 0x00af (0175) I 6cb00100 Clk : 110700 93 | 0x00b3 (0179) B 05 VddInd : 5 94 | 0x0038 (0056) H 6a01 MclkDependencyTableOffset : 362 95 | 0x016a (0362) B 01 RevId : 1 96 | 0x016b (0363) B 04 NumEntries : 4 97 | 0x016c (0364) I 3c410000 MemClk : 16700 98 | 0x0170 (0368) B 00 VddInd : 0 99 | 0x0171 (0369) B 00 VddMemInd : 0 100 | 0x0172 (0370) B 00 VddciInd : 0 101 | 0x0173 (0371) I 50c30000 MemClk : 50000 102 | 0x0177 (0375) B 01 VddInd : 1 103 | 0x0178 (0376) B 00 VddMemInd : 0 104 | 0x0179 (0377) B 00 VddciInd : 0 105 | 0x017a (0378) I 80380100 MemClk : 80000 106 | 0x017e (0382) B 02 VddInd : 2 107 | 0x017f (0383) B 00 VddMemInd : 0 108 | 0x0180 (0384) B 00 VddciInd : 0 109 | 0x0181 (0385) I 24710100 MemClk : 94500 110 | 0x0185 (0389) B 03 VddInd : 3 111 | 0x0186 (0390) B 00 VddMemInd : 0 112 | 0x0187 (0391) B 00 VddciInd : 0 113 | 0x003a (0058) H b400 GfxclkDependencyTableOffset : 180 114 | 0x00b4 (0180) B 00 RevId : 0 115 | 0x00b5 (0181) B 08 NumEntries : 8 116 | 0x00b6 (0182) I d04c0100 Clk : 85200 117 | 0x00ba (0186) B 00 VddInd : 0 118 | 0x00bb (0187) H 0080 CKSVOffsetandDisable : 32768 119 | 0x00bd (0189) H 0000 AVFSOffset : 0 120 | 0x00bf (0191) I 1c830100 Clk : 99100 121 | 0x00c3 (0195) B 01 VddInd : 1 122 | 0x00c4 (0196) H 0000 CKSVOffsetandDisable : 0 123 | 0x00c6 (0198) H 0000 AVFSOffset : 0 124 | 0x00c8 (0200) I 88bc0100 Clk : 113800 125 | 0x00cc (0204) B 02 VddInd : 2 126 | 0x00cd (0205) H 0000 CKSVOffsetandDisable : 0 127 | 0x00cf (0207) H 0000 AVFSOffset : 0 128 | 0x00d1 (0209) I b4ef0100 Clk : 126900 129 | 0x00d5 (0213) B 03 VddInd : 3 130 | 0x00d6 (0214) H 0000 CKSVOffsetandDisable : 0 131 | 0x00d8 (0216) H 0000 AVFSOffset : 0 132 | 0x00da (0218) I 900e0200 Clk : 134800 133 | 0x00de (0222) B 04 VddInd : 4 134 | 0x00df (0223) H 0000 CKSVOffsetandDisable : 0 135 | 0x00e1 (0225) H 0000 AVFSOffset : 0 136 | 0x00e3 (0227) I 80320200 Clk : 144000 137 | 0x00e7 (0231) B 05 VddInd : 5 138 | 0x00e8 (0232) H 0000 CKSVOffsetandDisable : 0 139 | 0x00ea (0234) H 0000 AVFSOffset : 0 140 | 0x00ec (0236) I e0540200 Clk : 152800 141 | 0x00f0 (0240) B 06 VddInd : 6 142 | 0x00f1 (0241) H 0000 CKSVOffsetandDisable : 0 143 | 0x00f3 (0243) H 0000 AVFSOffset : 0 144 | 0x00f5 (0245) I 00710200 Clk : 160000 145 | 0x00f9 (0249) B 07 VddInd : 7 146 | 0x00fa (0250) H 0000 CKSVOffsetandDisable : 0 147 | 0x00fc (0252) H 0000 AVFSOffset : 0 148 | 0x003c (0060) H fe00 DcefclkDependencyTableOffset : 254 149 | 0x00fe (0254) B 00 RevId : 0 150 | 0x00ff (0255) B 03 NumEntries : 3 151 | 0x0100 (0256) I 60ea0000 Clk : 60000 152 | 0x0104 (0260) B 00 VddInd : 0 153 | 0x0105 (0261) I 40190100 Clk : 72000 154 | 0x0109 (0265) B 00 VddInd : 0 155 | 0x010a (0266) I 80380100 Clk : 80000 156 | 0x010e (0270) B 00 VddInd : 0 157 | 0x003e (0062) H 7a00 VddcLookupTableOffset : 122 158 | 0x007a (0122) B 01 RevId : 1 159 | 0x007b (0123) B 08 NumEntries : 8 160 | 0x007c (0124) H 2003 Vdd : 800 161 | 0x007e (0126) H 8403 Vdd : 900 162 | 0x0080 (0128) H b603 Vdd : 950 163 | 0x0082 (0130) H e803 Vdd : 1000 164 | 0x0084 (0132) H 1a04 Vdd : 1050 165 | 0x0086 (0134) H 4c04 Vdd : 1100 166 | 0x0088 (0136) H 7e04 Vdd : 1150 167 | 0x008a (0138) H b004 Vdd : 1200 168 | 0x0040 (0064) H 8c00 VddmemLookupTableOffset : 140 169 | 0x008c (0140) B 01 RevId : 1 170 | 0x008d (0141) B 01 NumEntries : 1 171 | 0x008e (0142) H 4605 Vdd : 1350 172 | 0x0042 (0066) H 8801 MMDependencyTableOffset : 392 173 | 0x0188 (0392) B 01 RevId : 1 174 | 0x0189 (0393) B 08 NumEntries : 8 175 | 0x018a (0394) B 00 VddcInd : 0 176 | 0x018b (0395) I 98850000 DClk : 34200 177 | 0x018f (0399) I 78b40000 VClk : 46200 178 | 0x0193 (0403) I 60ea0000 EClk : 60000 179 | 0x0197 (0407) I 50c30000 PSPClk : 50000 180 | 0x019b (0411) B 01 VddcInd : 1 181 | 0x019c (0412) I 80bb0000 DClk : 48000 182 | 0x01a0 (0416) I 60ea0000 VClk : 60000 183 | 0x01a4 (0420) I 940b0100 EClk : 68500 184 | 0x01a8 (0424) I 50c30000 PSPClk : 50000 185 | 0x01ac (0428) B 02 VddcInd : 2 186 | 0x01ad (0429) I 78ff0000 DClk : 65400 187 | 0x01b1 (0433) I 40190100 VClk : 72000 188 | 0x01b5 (0437) I b4270100 EClk : 75700 189 | 0x01b9 (0441) I 50c30000 PSPClk : 50000 190 | 0x01bd (0445) B 03 VddcInd : 3 191 | 0x01be (0446) I b4270100 DClk : 75700 192 | 0x01c2 (0450) I dc4a0100 VClk : 84700 193 | 0x01c6 (0454) I dc4a0100 EClk : 84700 194 | 0x01ca (0458) I 50c30000 PSPClk : 50000 195 | 0x01ce (0462) B 04 VddcInd : 4 196 | 0x01cf (0463) I dc4a0100 DClk : 84700 197 | 0x01d3 (0467) I 905f0100 VClk : 90000 198 | 0x01d7 (0471) I 905f0100 EClk : 90000 199 | 0x01db (0475) I 50c30000 PSPClk : 50000 200 | 0x01df (0479) B 05 VddcInd : 5 201 | 0x01e0 (0480) I 00770100 DClk : 96000 202 | 0x01e4 (0484) I 90910100 VClk : 102800 203 | 0x01e8 (0488) I 00770100 EClk : 96000 204 | 0x01ec (0492) I 50c30000 PSPClk : 50000 205 | 0x01f0 (0496) B 06 VddcInd : 6 206 | 0x01f1 (0497) I 90910100 DClk : 102800 207 | 0x01f5 (0501) I 6cb00100 VClk : 110700 208 | 0x01f9 (0505) I 00770100 EClk : 96000 209 | 0x01fd (0509) I 50c30000 PSPClk : 50000 210 | 0x0201 (0513) B 07 VddcInd : 7 211 | 0x0202 (0514) I 6cb00100 DClk : 110700 212 | 0x0206 (0518) I 6cb00100 VClk : 110700 213 | 0x020a (0522) I 90910100 EClk : 102800 214 | 0x020e (0526) I 50c30000 PSPClk : 50000 215 | 0x0044 (0068) H 0000 VCEStateTableOffset : 0 216 | 0x0046 (0070) H 0000 Reserve : 0 217 | 0x0048 (0072) H 3e02 PowerTuneTableOffset : 574 218 | 0x023e (0574) B 07 RevId : 7 219 | 0x023f (0575) H dc00 SocketPowerLimit : 220 220 | 0x0241 (0577) H dc00 BatteryPowerLimit : 220 221 | 0x0243 (0579) H dc00 SmallPowerLimit : 220 222 | 0x0245 (0581) H 2c01 TdcLimit : 300 223 | 0x0247 (0583) H 0000 EdcLimit : 0 224 | 0x0249 (0585) H 4a00 SoftwareShutdownTemp : 74 225 | 0x024b (0587) H 6900 TemperatureLimitHotSpot : 105 226 | 0x024d (0589) H 4a00 TemperatureLimitLiquid1 : 74 227 | 0x024f (0591) H 4a00 TemperatureLimitLiquid2 : 74 228 | 0x0251 (0593) H 5f00 TemperatureLimitHBM : 95 229 | 0x0253 (0595) H 7300 TemperatureLimitVrSoc : 115 230 | 0x0255 (0597) H 7300 TemperatureLimitVrMem : 115 231 | 0x0257 (0599) H 6400 TemperatureLimitPlx : 100 232 | 0x0259 (0601) H 4000 LoadLineResistance : 64 233 | 0x025b (0603) B 90 Liquid1_I2C_address : 144 234 | 0x025c (0604) B 92 Liquid2_I2C_address : 146 235 | 0x025d (0605) B 97 Liquid_I2C_Line : 151 236 | 0x025e (0606) B 60 Vr_I2C_address : 96 237 | 0x025f (0607) B 96 Vr_I2C_Line : 150 238 | 0x0260 (0608) B 00 Plx_I2C_address : 0 239 | 0x0261 (0609) B 90 Plx_I2C_Line : 144 240 | 0x0262 (0610) H 4600 TemperatureLimitTedge : 70 241 | 0x0264 (0612) H 0000 BoostStartTemperature : 0 242 | 0x0266 (0614) H 0000 BoostStopTemperature : 0 243 | 0x0268 (0616) I 00000000 BoostClock : 0 244 | 0x026c (0620) I 00000000 Reserved : 0 245 | 0x0270 (0624) I 00000000 Reserved : 0 246 | 0x004a (0074) H 0000 HardLimitTableOffset : 0 247 | 0x004c (0076) H 9000 VddciLookupTableOffset : 144 248 | 0x0090 (0144) B 01 RevId : 1 249 | 0x0091 (0145) B 01 NumEntries : 1 250 | 0x0092 (0146) H 8403 Vdd : 900 251 | 0x004e (0078) H 7402 PCIETableOffset : 628 252 | 0x0274 (0628) B 02 RevId : 2 253 | 0x0275 (0629) B 02 NumEntries : 2 254 | 0x0276 (0630) I d4300000 LCLK : 12500 255 | 0x027a (0634) B 02 PCIEGenSpeed : 2 256 | 0x027b (0635) B 10 PCIELaneWidth : 16 257 | 0x027c (0636) I 60ea0000 LCLK : 60000 258 | 0x0280 (0640) B 02 PCIEGenSpeed : 2 259 | 0x0281 (0641) B 10 PCIELaneWidth : 16 260 | 0x0050 (0080) H 3901 PixclkDependencyTableOffset : 313 261 | 0x0139 (0313) B 00 RevId : 0 262 | 0x013a (0314) B 08 NumEntries : 8 263 | 0x013b (0315) I 6c390000 Clk : 14700 264 | 0x013f (0319) B 00 VddInd : 0 265 | 0x0140 (0320) I 245e0000 Clk : 24100 266 | 0x0144 (0324) B 01 VddInd : 1 267 | 0x0145 (0325) I fc850000 Clk : 34300 268 | 0x0149 (0329) B 02 VddInd : 2 269 | 0x014a (0330) I acbc0000 Clk : 48300 270 | 0x014e (0334) B 03 VddInd : 3 271 | 0x014f (0335) I 34d00000 Clk : 53300 272 | 0x0153 (0339) B 04 VddInd : 4 273 | 0x0154 (0340) I 686e0100 Clk : 93800 274 | 0x0158 (0344) B 05 VddInd : 5 275 | 0x0159 (0345) I 08970100 Clk : 104200 276 | 0x015d (0349) B 06 VddInd : 6 277 | 0x015e (0350) I eca30100 Clk : 107500 278 | 0x0162 (0354) B 07 VddInd : 7 279 | 0x0052 (0082) H 0f01 DispClkDependencyTableOffset : 271 280 | 0x010f (0271) B 00 RevId : 0 281 | 0x0110 (0272) B 08 NumEntries : 8 282 | 0x0111 (0273) I 286e0000 Clk : 28200 283 | 0x0115 (0277) B 00 VddInd : 0 284 | 0x0116 (0278) I 2cc90000 Clk : 51500 285 | 0x011a (0282) B 01 VddInd : 1 286 | 0x011b (0283) I f80b0100 Clk : 68600 287 | 0x011f (0287) B 02 VddInd : 2 288 | 0x0120 (0288) I 80380100 Clk : 80000 289 | 0x0124 (0292) B 03 VddInd : 3 290 | 0x0125 (0293) I 905f0100 Clk : 90000 291 | 0x0129 (0297) B 04 VddInd : 4 292 | 0x012a (0298) I f4910100 Clk : 102900 293 | 0x012e (0302) B 05 VddInd : 5 294 | 0x012f (0303) I d0b00100 Clk : 110800 295 | 0x0133 (0307) B 06 VddInd : 6 296 | 0x0134 (0308) I c0d40100 Clk : 120000 297 | 0x0138 (0312) B 07 VddInd : 7 298 | 0x0054 (0084) H 6301 PhyClkDependencyTableOffset : 355 299 | 0x0163 (0355) B 00 RevId : 0 300 | 0x0164 (0356) B 01 NumEntries : 1 301 | 0x0165 (0357) I 683c0100 Clk : 81000 302 | 0x0169 (0361) B 00 VddInd : 0 303 | -------------------------------------------------------------------------------- /test/AMD.RadeonVII.16384.190116.rom.dump: -------------------------------------------------------------------------------- 1 | sHeader: 2 | structuresize: 1730 3 | format_revision: 11 4 | content_revision: 0 5 | TableRevision: 2 6 | TableSize: 1730 7 | GoldenPPID: 2100 8 | GoldenRevision: 13732 9 | FormatID: 124 10 | PlatformCaps: 9 11 | ThermalControllerType: 26 12 | SmallPowerLimit1: 250 13 | SmallPowerLimit2: 250 14 | BoostPowerLimit: 250 15 | ODTurboPowerLimit: 0 16 | ODPowerSavePowerLimit: 0 17 | SoftwareShutdownTemp: 118 18 | PowerSavingClockTable: 19 | TableRevision: 1 20 | PowerSavingClockCount: 11 21 | PowerSavingClockMax: 22 | PowerSavingClockMax 0: 1801 23 | PowerSavingClockMax 1: 1134 24 | PowerSavingClockMax 2: 972 25 | PowerSavingClockMax 3: 972 26 | PowerSavingClockMax 4: 972 27 | PowerSavingClockMax 5: 1000 28 | PowerSavingClockMax 6: 1225 29 | PowerSavingClockMax 7: 1134 30 | PowerSavingClockMax 8: 1134 31 | PowerSavingClockMax 9: 1076 32 | PowerSavingClockMax 10: 810 33 | PowerSavingClockMax 11: 0 34 | PowerSavingClockMax 12: 0 35 | PowerSavingClockMax 13: 0 36 | PowerSavingClockMax 14: 0 37 | PowerSavingClockMax 15: 0 38 | PowerSavingClockMin: 39 | PowerSavingClockMin 0: 700 40 | PowerSavingClockMin 1: 358 41 | PowerSavingClockMin 2: 310 42 | PowerSavingClockMin 3: 310 43 | PowerSavingClockMin 4: 310 44 | PowerSavingClockMin 5: 350 45 | PowerSavingClockMin 6: 550 46 | PowerSavingClockMin 7: 358 47 | PowerSavingClockMin 8: 358 48 | PowerSavingClockMin 9: 147 49 | PowerSavingClockMin 10: 270 50 | PowerSavingClockMin 11: 0 51 | PowerSavingClockMin 12: 0 52 | PowerSavingClockMin 13: 0 53 | PowerSavingClockMin 14: 0 54 | PowerSavingClockMin 15: 0 55 | OverDrive8Table: 56 | ODTableRevision: 1 57 | ODFeatureCount: 14 58 | ODFeatureCapabilities: 59 | ODFeatureCapabilities 0: 1 60 | ODFeatureCapabilities 1: 1 61 | ODFeatureCapabilities 2: 1 62 | ODFeatureCapabilities 3: 1 63 | ODFeatureCapabilities 4: 1 64 | ODFeatureCapabilities 5: 1 65 | ODFeatureCapabilities 6: 1 66 | ODFeatureCapabilities 7: 1 67 | ODFeatureCapabilities 8: 1 68 | ODFeatureCapabilities 9: 0 69 | ODFeatureCapabilities 10: 1 70 | ODFeatureCapabilities 11: 1 71 | ODFeatureCapabilities 12: 1 72 | ODFeatureCapabilities 13: 1 73 | ODFeatureCapabilities 14: 0 74 | ODFeatureCapabilities 15: 0 75 | ODFeatureCapabilities 16: 0 76 | ODFeatureCapabilities 17: 0 77 | ODFeatureCapabilities 18: 0 78 | ODFeatureCapabilities 19: 0 79 | ODFeatureCapabilities 20: 0 80 | ODFeatureCapabilities 21: 0 81 | ODFeatureCapabilities 22: 0 82 | ODFeatureCapabilities 23: 0 83 | ODFeatureCapabilities 24: 0 84 | ODFeatureCapabilities 25: 0 85 | ODFeatureCapabilities 26: 0 86 | ODFeatureCapabilities 27: 0 87 | ODFeatureCapabilities 28: 0 88 | ODFeatureCapabilities 29: 0 89 | ODFeatureCapabilities 30: 0 90 | ODFeatureCapabilities 31: 0 91 | ODSettingCount: 29 92 | ODSettingsMax: 93 | ODSettingsMax 0: 2200 94 | ODSettingsMax 1: 2200 95 | ODSettingsMax 2: 2200 96 | ODSettingsMax 3: 1218 97 | ODSettingsMax 4: 2200 98 | ODSettingsMax 5: 1218 99 | ODSettingsMax 6: 2200 100 | ODSettingsMax 7: 1218 101 | ODSettingsMax 8: 1200 102 | ODSettingsMax 9: 20 103 | ODSettingsMax 10: 3850 104 | ODSettingsMax 11: 3850 105 | ODSettingsMax 12: 95 106 | ODSettingsMax 13: 110 107 | ODSettingsMax 14: 2 108 | ODSettingsMax 15: 0 109 | ODSettingsMax 16: 1 110 | ODSettingsMax 17: 1 111 | ODSettingsMax 18: 1 112 | ODSettingsMax 19: 95 113 | ODSettingsMax 20: 100 114 | ODSettingsMax 21: 95 115 | ODSettingsMax 22: 100 116 | ODSettingsMax 23: 95 117 | ODSettingsMax 24: 100 118 | ODSettingsMax 25: 95 119 | ODSettingsMax 26: 100 120 | ODSettingsMax 27: 95 121 | ODSettingsMax 28: 100 122 | ODSettingsMax 29: 0 123 | ODSettingsMax 30: 0 124 | ODSettingsMax 31: 0 125 | ODSettingsMin: 126 | ODSettingsMin 0: 808 127 | ODSettingsMin 1: 808 128 | ODSettingsMin 2: 808 129 | ODSettingsMin 3: 738 130 | ODSettingsMin 4: 808 131 | ODSettingsMin 5: 738 132 | ODSettingsMin 6: 808 133 | ODSettingsMin 7: 738 134 | ODSettingsMin 8: 350 135 | ODSettingsMin 9: 20 136 | ODSettingsMin 10: 450 137 | ODSettingsMin 11: 450 138 | ODSettingsMin 12: 25 139 | ODSettingsMin 13: 50 140 | ODSettingsMin 14: 0 141 | ODSettingsMin 15: 0 142 | ODSettingsMin 16: 0 143 | ODSettingsMin 17: 0 144 | ODSettingsMin 18: 0 145 | ODSettingsMin 19: 25 146 | ODSettingsMin 20: 20 147 | ODSettingsMin 21: 25 148 | ODSettingsMin 22: 20 149 | ODSettingsMin 23: 25 150 | ODSettingsMin 24: 20 151 | ODSettingsMin 25: 25 152 | ODSettingsMin 26: 20 153 | ODSettingsMin 27: 25 154 | ODSettingsMin 28: 20 155 | ODSettingsMin 29: 0 156 | ODSettingsMin 30: 0 157 | ODSettingsMin 31: 0 158 | Reserve: 159 | Reserve 0: 0 160 | Reserve 1: 0 161 | Reserve 2: 0 162 | Reserve 3: 0 163 | Reserve 4: 0 164 | smcPPTable: 165 | Version: 3 166 | FeaturesToRun: 167 | FeaturesToRun 0: 972353535 168 | FeaturesToRun 1: 0 169 | SocketPowerLimitAc0: 250 170 | SocketPowerLimitAc0Tau: 0 171 | SocketPowerLimitAc1: 0 172 | SocketPowerLimitAc1Tau: 0 173 | SocketPowerLimitAc2: 0 174 | SocketPowerLimitAc2Tau: 0 175 | SocketPowerLimitAc3: 0 176 | SocketPowerLimitAc3Tau: 0 177 | SocketPowerLimitDc: 250 178 | SocketPowerLimitDcTau: 0 179 | TdcLimitSoc: 50 180 | TdcLimitSocTau: 0 181 | TdcLimitGfx: 330 182 | TdcLimitGfxTau: 0 183 | TedgeLimit: 100 184 | ThotspotLimit: 110 185 | ThbmLimit: 94 186 | Tvr_gfxLimit: 115 187 | Tvr_memLimit: 115 188 | Tliquid1Limit: 65535 189 | Tliquid2Limit: 65535 190 | TplxLimit: 65535 191 | FitLimit: 0 192 | PpmPowerLimit: 0 193 | PpmTemperatureThreshold: 0 194 | MemoryOnPackage: 1 195 | padding8_limits: 0 196 | Tvr_SocLimit: 115 197 | UlvVoltageOffsetSoc: 0 198 | UlvVoltageOffsetGfx: 0 199 | UlvSmnclkDid: 0 200 | UlvMp1clkDid: 0 201 | UlvGfxclkBypass: 0 202 | Padding234: 0 203 | MinVoltageGfx: 2950 204 | MinVoltageSoc: 2850 205 | MaxVoltageGfx: 4875 206 | MaxVoltageSoc: 4675 207 | LoadLineResistanceGfx: 38 208 | LoadLineResistanceSoc: 0 209 | DpmDescriptor: 210 | DpmDescriptor 0: 211 | VoltageMode: 1 212 | SnapToDiscrete: 1 213 | NumDiscreteLevels: 9 214 | padding: 0 215 | ConversionToAvfsClk: 216 | m: 0 217 | b: 0 218 | SsCurve: 219 | a: 0.3744 220 | b:-0.485 221 | c: 0.8207 222 | DpmDescriptor 1: 223 | VoltageMode: 0 224 | SnapToDiscrete: 1 225 | NumDiscreteLevels: 8 226 | padding: 0 227 | ConversionToAvfsClk: 228 | m: 1.244 229 | b:-0.08099 230 | SsCurve: 231 | a: 0 232 | b: 0 233 | c: 0 234 | DpmDescriptor 2: 235 | VoltageMode: 0 236 | SnapToDiscrete: 1 237 | NumDiscreteLevels: 8 238 | padding: 0 239 | ConversionToAvfsClk: 240 | m: 1.206 241 | b: 0.17013 242 | SsCurve: 243 | a: 0 244 | b: 0 245 | c: 0 246 | DpmDescriptor 3: 247 | VoltageMode: 0 248 | SnapToDiscrete: 1 249 | NumDiscreteLevels: 8 250 | padding: 0 251 | ConversionToAvfsClk: 252 | m: 1.3784 253 | b: 0.03667 254 | SsCurve: 255 | a: 0 256 | b: 0 257 | c: 0 258 | DpmDescriptor 4: 259 | VoltageMode: 0 260 | SnapToDiscrete: 1 261 | NumDiscreteLevels: 8 262 | padding: 0 263 | ConversionToAvfsClk: 264 | m: 1.2608 265 | b:-0.05297 266 | SsCurve: 267 | a: 0 268 | b: 0 269 | c: 0 270 | DpmDescriptor 5: 271 | VoltageMode: 0 272 | SnapToDiscrete: 1 273 | NumDiscreteLevels: 3 274 | padding: 0 275 | ConversionToAvfsClk: 276 | m: 1.0241 277 | b: 0.15026 278 | SsCurve: 279 | a: 0 280 | b: 0 281 | c: 0 282 | DpmDescriptor 6: 283 | VoltageMode: 0 284 | SnapToDiscrete: 1 285 | NumDiscreteLevels: 8 286 | padding: 0 287 | ConversionToAvfsClk: 288 | m: 1.0486 289 | b: 0.1726 290 | SsCurve: 291 | a: 0 292 | b: 0 293 | c: 0 294 | DpmDescriptor 7: 295 | VoltageMode: 0 296 | SnapToDiscrete: 1 297 | NumDiscreteLevels: 8 298 | padding: 0 299 | ConversionToAvfsClk: 300 | m: 0.8545 301 | b: 0.11896 302 | SsCurve: 303 | a: 0 304 | b: 0 305 | c: 0 306 | DpmDescriptor 8: 307 | VoltageMode: 2 308 | SnapToDiscrete: 1 309 | NumDiscreteLevels: 8 310 | padding: 0 311 | ConversionToAvfsClk: 312 | m: 0 313 | b: 0 314 | SsCurve: 315 | a: 1.105 316 | b:-1.0397 317 | c: 0.69885 318 | DpmDescriptor 9: 319 | VoltageMode: 2 320 | SnapToDiscrete: 1 321 | NumDiscreteLevels: 3 322 | padding: 0 323 | ConversionToAvfsClk: 324 | m: 0 325 | b: 0 326 | SsCurve: 327 | a: 0 328 | b: 0 329 | c: 0.69885 330 | DpmDescriptor 10: 331 | VoltageMode: 1 332 | SnapToDiscrete: 1 333 | NumDiscreteLevels: 8 334 | padding: 0 335 | ConversionToAvfsClk: 336 | m: 1 337 | b: 0 338 | SsCurve: 339 | a: 0.4933 340 | b:-0.67 341 | c: 0.95885 342 | FreqTableGfx: 343 | FreqTableGfx 0: 700 344 | FreqTableGfx 1: 808 345 | FreqTableGfx 2: 1134 346 | FreqTableGfx 3: 1372 347 | FreqTableGfx 4: 1546 348 | FreqTableGfx 5: 1683 349 | FreqTableGfx 6: 1749 350 | FreqTableGfx 7: 1773 351 | FreqTableGfx 8: 1801 352 | FreqTableGfx 9: 0 353 | FreqTableGfx 10: 0 354 | FreqTableGfx 11: 0 355 | FreqTableGfx 12: 0 356 | FreqTableGfx 13: 0 357 | FreqTableGfx 14: 0 358 | FreqTableGfx 15: 0 359 | FreqTableVclk: 360 | FreqTableVclk 0: 358 361 | FreqTableVclk 1: 486 362 | FreqTableVclk 2: 619 363 | FreqTableVclk 3: 756 364 | FreqTableVclk 4: 850 365 | FreqTableVclk 5: 972 366 | FreqTableVclk 6: 1134 367 | FreqTableVclk 7: 1134 368 | FreqTableDclk: 369 | FreqTableDclk 0: 310 370 | FreqTableDclk 1: 400 371 | FreqTableDclk 2: 524 372 | FreqTableDclk 3: 619 373 | FreqTableDclk 4: 680 374 | FreqTableDclk 5: 756 375 | FreqTableDclk 6: 850 376 | FreqTableDclk 7: 972 377 | FreqTableEclk: 378 | FreqTableEclk 0: 310 379 | FreqTableEclk 1: 400 380 | FreqTableEclk 2: 524 381 | FreqTableEclk 3: 619 382 | FreqTableEclk 4: 680 383 | FreqTableEclk 5: 756 384 | FreqTableEclk 6: 850 385 | FreqTableEclk 7: 972 386 | FreqTableSocclk: 387 | FreqTableSocclk 0: 310 388 | FreqTableSocclk 1: 524 389 | FreqTableSocclk 2: 567 390 | FreqTableSocclk 3: 619 391 | FreqTableSocclk 4: 680 392 | FreqTableSocclk 5: 756 393 | FreqTableSocclk 6: 850 394 | FreqTableSocclk 7: 972 395 | FreqTableUclk: 396 | FreqTableUclk 0: 350 397 | FreqTableUclk 1: 800 398 | FreqTableUclk 2: 1000 399 | FreqTableUclk 3: 1000 400 | FreqTableFclk: 401 | FreqTableFclk 0: 550 402 | FreqTableFclk 1: 610 403 | FreqTableFclk 2: 690 404 | FreqTableFclk 3: 760 405 | FreqTableFclk 4: 870 406 | FreqTableFclk 5: 960 407 | FreqTableFclk 6: 1080 408 | FreqTableFclk 7: 1225 409 | FreqTableDcefclk: 410 | FreqTableDcefclk 0: 358 411 | FreqTableDcefclk 1: 454 412 | FreqTableDcefclk 2: 567 413 | FreqTableDcefclk 3: 680 414 | FreqTableDcefclk 4: 756 415 | FreqTableDcefclk 5: 850 416 | FreqTableDcefclk 6: 972 417 | FreqTableDcefclk 7: 1134 418 | FreqTableDispclk: 419 | FreqTableDispclk 0: 358 420 | FreqTableDispclk 1: 454 421 | FreqTableDispclk 2: 567 422 | FreqTableDispclk 3: 680 423 | FreqTableDispclk 4: 756 424 | FreqTableDispclk 5: 850 425 | FreqTableDispclk 6: 972 426 | FreqTableDispclk 7: 1134 427 | FreqTablePixclk: 428 | FreqTablePixclk 0: 147 429 | FreqTablePixclk 1: 242 430 | FreqTablePixclk 2: 344 431 | FreqTablePixclk 3: 484 432 | FreqTablePixclk 4: 533 433 | FreqTablePixclk 5: 938 434 | FreqTablePixclk 6: 1043 435 | FreqTablePixclk 7: 1076 436 | FreqTablePhyclk: 437 | FreqTablePhyclk 0: 270 438 | FreqTablePhyclk 1: 540 439 | FreqTablePhyclk 2: 810 440 | FreqTablePhyclk 3: 0 441 | FreqTablePhyclk 4: 0 442 | FreqTablePhyclk 5: 0 443 | FreqTablePhyclk 6: 0 444 | FreqTablePhyclk 7: 0 445 | DcModeMaxFreq: 446 | DcModeMaxFreq 0: 1801 447 | DcModeMaxFreq 1: 1134 448 | DcModeMaxFreq 2: 972 449 | DcModeMaxFreq 3: 972 450 | DcModeMaxFreq 4: 972 451 | DcModeMaxFreq 5: 1000 452 | DcModeMaxFreq 6: 1134 453 | DcModeMaxFreq 7: 1134 454 | DcModeMaxFreq 8: 1076 455 | DcModeMaxFreq 9: 810 456 | DcModeMaxFreq 10: 1225 457 | Padding8_Clks: 0 458 | Mp0clkFreq: 459 | Mp0clkFreq 0: 200 460 | Mp0clkFreq 1: 300 461 | Mp0DpmVoltage: 462 | Mp0DpmVoltage 0: 2400 463 | Mp0DpmVoltage 1: 2800 464 | GfxclkFidle: 808 465 | GfxclkSlewRate: 0 466 | CksEnableFreq: 0 467 | Padding789: 0 468 | CksVoltageOffset: 469 | a: 0 470 | b: 0 471 | c: 0 472 | Padding567: 473 | Padding567 0: 0 474 | Padding567 1: 0 475 | Padding567 2: 0 476 | Padding567 3: 0 477 | GfxclkDsMaxFreq: 1801 478 | GfxclkSource: 1 479 | Padding456: 0 480 | LowestUclkReservedForUlv: 0 481 | Padding8_Uclk: 482 | Padding8_Uclk 0: 0 483 | Padding8_Uclk 1: 0 484 | Padding8_Uclk 2: 0 485 | PcieGenSpeed: 486 | PcieGenSpeed 0: 0 487 | PcieGenSpeed 1: 2 488 | PcieLaneCount: 489 | PcieLaneCount 0: 6 490 | PcieLaneCount 1: 6 491 | LclkFreq: 492 | LclkFreq 0: 80 493 | LclkFreq 1: 308 494 | EnableTdpm: 0 495 | TdpmHighHystTemperature: 0 496 | TdpmLowHystTemperature: 0 497 | GfxclkFreqHighTempLimit: 0 498 | FanStopTemp: 0 499 | FanStartTemp: 0 500 | FanGainEdge: 400 501 | FanGainHotspot: 400 502 | FanGainLiquid: 400 503 | FanGainVrGfx: 400 504 | FanGainVrSoc: 400 505 | FanGainPlx: 400 506 | FanGainHbm: 400 507 | FanPwmMin: 20 508 | FanAcousticLimitRpm: 2900 509 | FanThrottlingRpm: 2900 510 | FanMaximumRpm: 3850 511 | FanTargetTemperature: 95 512 | FanTargetGfxclk: 0 513 | FanZeroRpmEnable: 0 514 | FanTachEdgePerRev: 2 515 | FuzzyFan_ErrorSetDelta: 0 516 | FuzzyFan_ErrorRateSetDelta: 0 517 | FuzzyFan_PwmSetDelta: 0 518 | FuzzyFan_Reserved: 0 519 | OverrideAvfsGb: 520 | OverrideAvfsGb 0: 0 521 | OverrideAvfsGb 1: 1 522 | Padding8_Avfs: 523 | Padding8_Avfs 0: 0 524 | Padding8_Avfs 1: 0 525 | qAvfsGb: 526 | qAvfsGb 0: 527 | a: 0 528 | b: 0.0185 529 | c: 0.005 530 | qAvfsGb 1: 531 | a: 0 532 | b: 0.01864 533 | c: 0.04703 534 | dBtcGbGfxCksOn: 535 | a: 0 536 | b: 0 537 | c: 0 538 | dBtcGbGfxCksOff: 539 | a: 0 540 | b: 0 541 | c: 0 542 | dBtcGbGfxAfll: 543 | a: 0 544 | b: 0 545 | c: 0 546 | dBtcGbSoc: 547 | a: 0 548 | b: 0 549 | c: 0 550 | qAgingGb: 551 | qAgingGb 0: 552 | m: 0 553 | b: 0 554 | qAgingGb 1: 555 | m: 0 556 | b: 0 557 | qStaticVoltageOffset: 558 | qStaticVoltageOffset 0: 559 | a: 0 560 | b: 0 561 | c: 0 562 | qStaticVoltageOffset 1: 563 | a: 0 564 | b: 0 565 | c: 0 566 | DcTol: 567 | DcTol 0: 0 568 | DcTol 1: 160 569 | DcBtcEnabled: 570 | DcBtcEnabled 0: 1 571 | DcBtcEnabled 1: 0 572 | Padding8_GfxBtc: 573 | Padding8_GfxBtc 0: 0 574 | Padding8_GfxBtc 1: 0 575 | DcBtcMin: 576 | DcBtcMin 0: 0 577 | DcBtcMin 1: 0 578 | DcBtcMax: 579 | DcBtcMax 0: 160 580 | DcBtcMax 1: 0 581 | XgmiLinkSpeed: 582 | XgmiLinkSpeed 0: 8 583 | XgmiLinkSpeed 1: 16 584 | XgmiLinkWidth: 585 | XgmiLinkWidth 0: 2 586 | XgmiLinkWidth 1: 16 587 | XgmiFclkFreq: 588 | XgmiFclkFreq 0: 1050 589 | XgmiFclkFreq 1: 1100 590 | XgmiUclkFreq: 591 | XgmiUclkFreq 0: 1000 592 | XgmiUclkFreq 1: 1000 593 | XgmiSocclkFreq: 594 | XgmiSocclkFreq 0: 1000 595 | XgmiSocclkFreq 1: 1000 596 | XgmiSocVoltage: 597 | XgmiSocVoltage 0: 0 598 | XgmiSocVoltage 1: 0 599 | DebugOverrides: 0 600 | ReservedEquation0: 601 | a: 0 602 | b: 0 603 | c: 0 604 | ReservedEquation1: 605 | a: 0 606 | b: 0 607 | c: 0 608 | ReservedEquation2: 609 | a: 0 610 | b: 0 611 | c: 0 612 | ReservedEquation3: 613 | a: 0 614 | b: 0 615 | c: 0 616 | MinVoltageUlvGfx: 2950 617 | MinVoltageUlvSoc: 2850 618 | MGpuFanBoostLimitRpm: 2900 619 | padding16_Fan: 0 620 | FanGainVrMem0: 400 621 | FanGainVrMem1: 400 622 | DcBtcGb: 623 | DcBtcGb 0: 56 624 | DcBtcGb 1: 0 625 | Reserved: 626 | Reserved 0: 0 627 | Reserved 1: 0 628 | Reserved 2: 0 629 | Reserved 3: 0 630 | Reserved 4: 0 631 | Reserved 5: 0 632 | Reserved 6: 0 633 | Reserved 7: 0 634 | Reserved 8: 0 635 | Reserved 9: 0 636 | Reserved 10: 0 637 | Padding32: 638 | Padding32 0: 0 639 | Padding32 1: 0 640 | Padding32 2: 0 641 | MaxVoltageStepGfx: 0 642 | MaxVoltageStepSoc: 0 643 | VddGfxVrMapping: 0 644 | VddSocVrMapping: 0 645 | VddMem0VrMapping: 0 646 | VddMem1VrMapping: 0 647 | GfxUlvPhaseSheddingMask: 0 648 | SocUlvPhaseSheddingMask: 0 649 | ExternalSensorPresent: 0 650 | Padding8_V: 0 651 | GfxMaxCurrent: 0 652 | GfxOffset: 0 653 | Padding_TelemetryGfx: 0 654 | SocMaxCurrent: 0 655 | SocOffset: 0 656 | Padding_TelemetrySoc: 0 657 | Mem0MaxCurrent: 0 658 | Mem0Offset: 0 659 | Padding_TelemetryMem0: 0 660 | Mem1MaxCurrent: 0 661 | Mem1Offset: 0 662 | Padding_TelemetryMem1: 0 663 | AcDcGpio: 0 664 | AcDcPolarity: 0 665 | VR0HotGpio: 0 666 | VR0HotPolarity: 0 667 | VR1HotGpio: 0 668 | VR1HotPolarity: 0 669 | Padding1: 0 670 | Padding2: 0 671 | LedPin0: 0 672 | LedPin1: 0 673 | LedPin2: 0 674 | padding8_4: 0 675 | PllGfxclkSpreadEnabled: 0 676 | PllGfxclkSpreadPercent: 0 677 | PllGfxclkSpreadFreq: 0 678 | UclkSpreadEnabled: 0 679 | UclkSpreadPercent: 0 680 | UclkSpreadFreq: 0 681 | FclkSpreadEnabled: 0 682 | FclkSpreadPercent: 0 683 | FclkSpreadFreq: 0 684 | FllGfxclkSpreadEnabled: 0 685 | FllGfxclkSpreadPercent: 0 686 | FllGfxclkSpreadFreq: 0 687 | I2cControllers: 688 | I2cControllers 0: 689 | Enabled: 0 690 | SlaveAddress: 0 691 | ControllerPort: 0 692 | ControllerName: 0 693 | ThermalThrottler: 0 694 | I2cProtocol: 0 695 | I2cSpeed: 0 696 | I2cControllers 1: 697 | Enabled: 0 698 | SlaveAddress: 0 699 | ControllerPort: 0 700 | ControllerName: 0 701 | ThermalThrottler: 0 702 | I2cProtocol: 0 703 | I2cSpeed: 0 704 | I2cControllers 2: 705 | Enabled: 0 706 | SlaveAddress: 0 707 | ControllerPort: 0 708 | ControllerName: 0 709 | ThermalThrottler: 0 710 | I2cProtocol: 0 711 | I2cSpeed: 0 712 | I2cControllers 3: 713 | Enabled: 0 714 | SlaveAddress: 0 715 | ControllerPort: 0 716 | ControllerName: 0 717 | ThermalThrottler: 0 718 | I2cProtocol: 0 719 | I2cSpeed: 0 720 | I2cControllers 4: 721 | Enabled: 0 722 | SlaveAddress: 0 723 | ControllerPort: 0 724 | ControllerName: 0 725 | ThermalThrottler: 0 726 | I2cProtocol: 0 727 | I2cSpeed: 0 728 | I2cControllers 5: 729 | Enabled: 0 730 | SlaveAddress: 0 731 | ControllerPort: 0 732 | ControllerName: 0 733 | ThermalThrottler: 0 734 | I2cProtocol: 0 735 | I2cSpeed: 0 736 | I2cControllers 6: 737 | Enabled: 0 738 | SlaveAddress: 0 739 | ControllerPort: 0 740 | ControllerName: 0 741 | ThermalThrottler: 0 742 | I2cProtocol: 0 743 | I2cSpeed: 0 744 | BoardReserved: 745 | BoardReserved 0: 0 746 | BoardReserved 1: 0 747 | BoardReserved 2: 0 748 | BoardReserved 3: 0 749 | BoardReserved 4: 0 750 | BoardReserved 5: 0 751 | BoardReserved 6: 0 752 | BoardReserved 7: 0 753 | BoardReserved 8: 0 754 | BoardReserved 9: 0 755 | MmHubPadding: 756 | MmHubPadding 0: 0 757 | MmHubPadding 1: 0 758 | MmHubPadding 2: 0 759 | MmHubPadding 3: 0 760 | MmHubPadding 4: 0 761 | MmHubPadding 5: 0 762 | MmHubPadding 6: 0 763 | MmHubPadding 7: 0 764 | -------------------------------------------------------------------------------- /test/MI100_000.000.000.000.016113_113-D3431401-100.rom.dump: -------------------------------------------------------------------------------- 1 | header: 2 | structuresize: 1494 3 | format_revision: 13 4 | content_revision: 0 5 | table_revision: 1 6 | table_size: 482 7 | golden_pp_id: 2462 8 | golden_revision: 16007 9 | format_id: 126 10 | platform_caps: 8 11 | thermal_controller_type: 28 12 | small_power_limit1: 290 13 | small_power_limit2: 290 14 | boost_power_limit: 290 15 | od_turbo_power_limit: 0 16 | od_power_save_power_limit: 0 17 | software_shutdown_temp: 108 18 | reserve: 19 | reserve 0: 0 20 | reserve 1: 0 21 | reserve 2: 0 22 | reserve 3: 0 23 | reserve 4: 0 24 | reserve 5: 0 25 | power_saving_clock: 26 | revision: 1 27 | reserve: 28 | reserve 0: 0 29 | reserve 1: 0 30 | reserve 2: 0 31 | count: 10 32 | max: 33 | max 0: 0 34 | max 1: 0 35 | max 2: 0 36 | max 3: 0 37 | max 4: 0 38 | max 5: 0 39 | max 6: 0 40 | max 7: 0 41 | max 8: 0 42 | max 9: 0 43 | max 10: 0 44 | max 11: 0 45 | max 12: 0 46 | max 13: 0 47 | max 14: 0 48 | max 15: 0 49 | min: 50 | min 0: 0 51 | min 1: 0 52 | min 2: 0 53 | min 3: 0 54 | min 4: 0 55 | min 5: 0 56 | min 6: 0 57 | min 7: 0 58 | min 8: 0 59 | min 9: 0 60 | min 10: 0 61 | min 11: 0 62 | min 12: 0 63 | min 13: 0 64 | min 14: 0 65 | min 15: 0 66 | overdrive_table: 67 | revision: 128 68 | reserve: 69 | reserve 0: 0 70 | reserve 1: 0 71 | reserve 2: 0 72 | feature_count: 14 73 | setting_count: 19 74 | cap: 75 | cap 0: 0 76 | cap 1: 0 77 | cap 2: 0 78 | cap 3: 0 79 | cap 4: 0 80 | cap 5: 0 81 | cap 6: 0 82 | cap 7: 0 83 | cap 8: 0 84 | cap 9: 0 85 | cap 10: 0 86 | cap 11: 0 87 | cap 12: 0 88 | cap 13: 0 89 | cap 14: 0 90 | cap 15: 0 91 | cap 16: 0 92 | cap 17: 0 93 | cap 18: 0 94 | cap 19: 0 95 | cap 20: 0 96 | cap 21: 0 97 | cap 22: 0 98 | cap 23: 0 99 | cap 24: 0 100 | cap 25: 0 101 | cap 26: 0 102 | cap 27: 0 103 | cap 28: 0 104 | cap 29: 0 105 | cap 30: 0 106 | cap 31: 0 107 | max: 108 | max 0: 0 109 | max 1: 0 110 | max 2: 0 111 | max 3: 0 112 | max 4: 0 113 | max 5: 0 114 | max 6: 0 115 | max 7: 0 116 | max 8: 0 117 | max 9: 0 118 | max 10: 0 119 | max 11: 0 120 | max 12: 0 121 | max 13: 0 122 | max 14: 0 123 | max 15: 0 124 | max 16: 0 125 | max 17: 0 126 | max 18: 0 127 | max 19: 0 128 | max 20: 0 129 | max 21: 0 130 | max 22: 0 131 | max 23: 0 132 | max 24: 0 133 | max 25: 0 134 | max 26: 0 135 | max 27: 0 136 | max 28: 0 137 | max 29: 0 138 | max 30: 0 139 | max 31: 0 140 | min: 141 | min 0: 0 142 | min 1: 0 143 | min 2: 0 144 | min 3: 0 145 | min 4: 0 146 | min 5: 0 147 | min 6: 0 148 | min 7: 0 149 | min 8: 0 150 | min 9: 0 151 | min 10: 0 152 | min 11: 0 153 | min 12: 0 154 | min 13: 0 155 | min 14: 0 156 | min 15: 0 157 | min 16: 0 158 | min 17: 0 159 | min 18: 0 160 | min 19: 0 161 | min 20: 0 162 | min 21: 0 163 | min 22: 0 164 | min 23: 0 165 | min 24: 0 166 | min 25: 0 167 | min 26: 0 168 | min 27: 0 169 | min 28: 0 170 | min 29: 0 171 | min 30: 0 172 | min 31: 0 173 | smc_pptable: 174 | Version: 4 175 | FeaturesToRun: 176 | FeaturesToRun 0: 95155971 177 | FeaturesToRun 1: 0 178 | SocketPowerLimitAc: 179 | SocketPowerLimitAc 0: 290 180 | SocketPowerLimitAc 1: 391 181 | SocketPowerLimitAc 2: 0 182 | SocketPowerLimitAc 3: 0 183 | SocketPowerLimitAcTau: 184 | SocketPowerLimitAcTau 0: 5 185 | SocketPowerLimitAcTau 1: 1 186 | SocketPowerLimitAcTau 2: 0 187 | SocketPowerLimitAcTau 3: 0 188 | TdcLimitSoc: 50 189 | TdcLimitSocTau: 0 190 | TdcLimitGfx: 320 191 | TdcLimitGfxTau: 0 192 | TedgeLimit: 100 193 | ThotspotLimit: 100 194 | TmemLimit: 94 195 | Tvr_gfxLimit: 103 196 | Tvr_memLimit: 103 197 | Tvr_socLimit: 103 198 | FitLimit: 0 199 | PpmPowerLimit: 0 200 | PpmTemperatureThreshold: 0 201 | ThrottlerControlMask: 2044 202 | UlvVoltageOffsetGfx: 0 203 | UlvPadding: 0 204 | UlvGfxclkBypass: 0 205 | Padding234: 206 | Padding234 0: 0 207 | Padding234 1: 0 208 | Padding234 2: 0 209 | MinVoltageGfx: 2700 210 | MinVoltageSoc: 3500 211 | MaxVoltageGfx: 4150 212 | MaxVoltageSoc: 4200 213 | LoadLineResistanceGfx: 25 214 | LoadLineResistanceSoc: 0 215 | DpmDescriptor: 216 | DpmDescriptor 0: 217 | VoltageMode: 1 218 | SnapToDiscrete: 1 219 | NumDiscreteLevels: 16 220 | padding: 0 221 | ConversionToAvfsClk: 222 | m: 0 223 | b: 0 224 | SsCurve: 225 | a: 0.17702 226 | b: 0.0013 227 | c: 0.60972 228 | SsFmin: 300 229 | Padding16: 0 230 | DpmDescriptor 1: 231 | VoltageMode: 1 232 | SnapToDiscrete: 1 233 | NumDiscreteLevels: 8 234 | padding: 0 235 | ConversionToAvfsClk: 236 | m: 0.7374 237 | b: 0.2015 238 | SsCurve: 239 | a: 0.2395 240 | b:-0.198 241 | c: 0.7078 242 | SsFmin: 413 243 | Padding16: 0 244 | DpmDescriptor 2: 245 | VoltageMode: 1 246 | SnapToDiscrete: 1 247 | NumDiscreteLevels: 8 248 | padding: 0 249 | ConversionToAvfsClk: 250 | m: 1.114 251 | b: 0.03267 252 | SsCurve: 253 | a: 0.4971 254 | b:-0.419 255 | c: 0.7549 256 | SsFmin: 421 257 | Padding16: 0 258 | DpmDescriptor 3: 259 | VoltageMode: 1 260 | SnapToDiscrete: 1 261 | NumDiscreteLevels: 8 262 | padding: 0 263 | ConversionToAvfsClk: 264 | m: 1.075 265 | b: 0.0286 266 | SsCurve: 267 | a: 0.4573 268 | b:-0.432 269 | c: 0.8233 270 | SsFmin: 472 271 | Padding16: 0 272 | DpmDescriptor 4: 273 | VoltageMode: 1 274 | SnapToDiscrete: 1 275 | NumDiscreteLevels: 4 276 | padding: 0 277 | ConversionToAvfsClk: 278 | m: 1.2161 279 | b:-0.05914 280 | SsCurve: 281 | a: 0.5357 282 | b:-0.549 283 | c: 0.8838 284 | SsFmin: 512 285 | Padding16: 0 286 | DpmDescriptor 5: 287 | VoltageMode: 1 288 | SnapToDiscrete: 1 289 | NumDiscreteLevels: 8 290 | padding: 0 291 | ConversionToAvfsClk: 292 | m: 1 293 | b: 0 294 | SsCurve: 295 | a: 0.4561 296 | b:-0.576 297 | c: 0.9238 298 | SsFmin: 631 299 | Padding16: 0 300 | FreqTableGfx: 301 | FreqTableGfx 0: 300 302 | FreqTableGfx 1: 495 303 | FreqTableGfx 2: 731 304 | FreqTableGfx 3: 962 305 | FreqTableGfx 4: 1029 306 | FreqTableGfx 5: 1086 307 | FreqTableGfx 6: 1146 308 | FreqTableGfx 7: 1188 309 | FreqTableGfx 8: 1235 310 | FreqTableGfx 9: 1283 311 | FreqTableGfx 10: 1318 312 | FreqTableGfx 11: 1363 313 | FreqTableGfx 12: 1404 314 | FreqTableGfx 13: 1430 315 | FreqTableGfx 14: 1471 316 | FreqTableGfx 15: 1502 317 | FreqTableVclk: 318 | FreqTableVclk 0: 600 319 | FreqTableVclk 1: 706 320 | FreqTableVclk 2: 800 321 | FreqTableVclk 3: 858 322 | FreqTableVclk 4: 924 323 | FreqTableVclk 5: 1091 324 | FreqTableVclk 6: 1200 325 | FreqTableVclk 7: 1334 326 | FreqTableDclk: 327 | FreqTableDclk 0: 546 328 | FreqTableDclk 1: 600 329 | FreqTableDclk 2: 706 330 | FreqTableDclk 3: 750 331 | FreqTableDclk 4: 800 332 | FreqTableDclk 5: 924 333 | FreqTableDclk 6: 1000 334 | FreqTableDclk 7: 1091 335 | FreqTableSocclk: 336 | FreqTableSocclk 0: 600 337 | FreqTableSocclk 1: 667 338 | FreqTableSocclk 2: 706 339 | FreqTableSocclk 3: 750 340 | FreqTableSocclk 4: 800 341 | FreqTableSocclk 5: 858 342 | FreqTableSocclk 6: 924 343 | FreqTableSocclk 7: 1000 344 | FreqTableUclk: 345 | FreqTableUclk 0: 600 346 | FreqTableUclk 1: 800 347 | FreqTableUclk 2: 1000 348 | FreqTableUclk 3: 1200 349 | FreqTableFclk: 350 | FreqTableFclk 0: 650 351 | FreqTableFclk 1: 848 352 | FreqTableFclk 2: 955 353 | FreqTableFclk 3: 1060 354 | FreqTableFclk 4: 1179 355 | FreqTableFclk 5: 1236 356 | FreqTableFclk 6: 1291 357 | FreqTableFclk 7: 1403 358 | Paddingclks: 359 | Paddingclks 0: 0 360 | Paddingclks 1: 0 361 | Paddingclks 2: 0 362 | Paddingclks 3: 0 363 | Paddingclks 4: 0 364 | Paddingclks 5: 0 365 | Paddingclks 6: 0 366 | Paddingclks 7: 0 367 | Paddingclks 8: 0 368 | Paddingclks 9: 0 369 | Paddingclks 10: 0 370 | Paddingclks 11: 0 371 | Paddingclks 12: 0 372 | Paddingclks 13: 0 373 | Paddingclks 14: 0 374 | Paddingclks 15: 0 375 | Mp0clkFreq: 376 | Mp0clkFreq 0: 300 377 | Mp0clkFreq 1: 500 378 | Mp0DpmVoltage: 379 | Mp0DpmVoltage 0: 2850 380 | Mp0DpmVoltage 1: 2850 381 | GfxclkFidle: 300 382 | GfxclkSlewRate: 0 383 | Padding567: 384 | Padding567 0: 0 385 | Padding567 1: 0 386 | Padding567 2: 0 387 | Padding567 3: 0 388 | GfxclkDsMaxFreq: 1502 389 | GfxclkSource: 1 390 | Padding456: 0 391 | EnableTdpm: 0 392 | TdpmHighHystTemperature: 0 393 | TdpmLowHystTemperature: 0 394 | GfxclkFreqHighTempLimit: 0 395 | FanStopTemp: 0 396 | FanStartTemp: 0 397 | FanGainEdge: 0 398 | FanGainHotspot: 400 399 | FanGainVrGfx: 400 400 | FanGainVrSoc: 400 401 | FanGainVrMem: 400 402 | FanGainHbm: 400 403 | FanPwmMin: 20 404 | FanAcousticLimitRpm: 2900 405 | FanThrottlingRpm: 2900 406 | FanMaximumRpm: 3850 407 | FanTargetTemperature: 90 408 | FanTargetGfxclk: 300 409 | FanZeroRpmEnable: 0 410 | FanTachEdgePerRev: 2 411 | FanTempInputSelect: 1 412 | padding8_Fan: 0 413 | FuzzyFan_ErrorSetDelta: 0 414 | FuzzyFan_ErrorRateSetDelta: 0 415 | FuzzyFan_PwmSetDelta: 0 416 | FuzzyFan_Reserved: 0 417 | OverrideAvfsGb: 418 | OverrideAvfsGb 0: 1 419 | OverrideAvfsGb 1: 1 420 | Padding8_Avfs: 421 | Padding8_Avfs 0: 0 422 | Padding8_Avfs 1: 0 423 | qAvfsGb: 424 | qAvfsGb 0: 425 | a: 0.03647 426 | b:-0.03839 427 | c: 0.03198 428 | qAvfsGb 1: 429 | a: 0 430 | b: 0 431 | c: 0.04 432 | dBtcGbGfxPll: 433 | a: 0 434 | b: 0 435 | c: 0 436 | dBtcGbGfxAfll: 437 | a:-0.0336 438 | b: 0.0957 439 | c:-0.06153 440 | dBtcGbSoc: 441 | a: 0.16426 442 | b: 0.03781 443 | c:-0.07586 444 | qAgingGb: 445 | qAgingGb 0: 446 | m: 0 447 | b: 0 448 | qAgingGb 1: 449 | m: 0 450 | b: 0 451 | qStaticVoltageOffset: 452 | qStaticVoltageOffset 0: 453 | a: 0 454 | b: 0 455 | c: 0 456 | qStaticVoltageOffset 1: 457 | a: 0 458 | b: 0 459 | c: 0 460 | DcTol: 461 | DcTol 0: 308 462 | DcTol 1: 308 463 | DcBtcEnabled: 464 | DcBtcEnabled 0: 1 465 | DcBtcEnabled 1: 1 466 | Padding8_GfxBtc: 467 | Padding8_GfxBtc 0: 0 468 | Padding8_GfxBtc 1: 0 469 | DcBtcMin: 470 | DcBtcMin 0: 95 471 | DcBtcMin 1: 95 472 | DcBtcMax: 473 | DcBtcMax 0: 308 474 | DcBtcMax 1: 308 475 | DcBtcGb: 476 | DcBtcGb 0: 25 477 | DcBtcGb 1: 25 478 | XgmiDpmPstates: 479 | XgmiDpmPstates 0: 3 480 | XgmiDpmPstates 1: 0 481 | XgmiDpmSpare: 482 | XgmiDpmSpare 0: 0 483 | XgmiDpmSpare 1: 0 484 | VDDGFX_TVmin: 0 485 | VDDSOC_TVmin: 0 486 | VDDGFX_Vmin_HiTemp: 0 487 | VDDGFX_Vmin_LoTemp: 0 488 | VDDSOC_Vmin_HiTemp: 0 489 | VDDSOC_Vmin_LoTemp: 0 490 | VDDGFX_TVminHystersis: 0 491 | VDDSOC_TVminHystersis: 0 492 | DebugOverrides: 0 493 | ReservedEquation0: 494 | a: 0 495 | b: 0 496 | c: 0 497 | ReservedEquation1: 498 | a: 0 499 | b: 0 500 | c: 0 501 | ReservedEquation2: 502 | a: 0 503 | b: 0 504 | c: 0 505 | ReservedEquation3: 506 | a: 0 507 | b: 0 508 | c: 0 509 | MinVoltageUlvGfx: 2700 510 | PaddingUlv: 0 511 | TotalPowerConfig: 3 512 | TotalPowerSpare1: 0 513 | TotalPowerSpare2: 0 514 | PccThresholdLow: 0 515 | PccThresholdHigh: 0 516 | PaddingAPCC: 517 | PaddingAPCC 0: 0 518 | PaddingAPCC 1: 0 519 | PaddingAPCC 2: 0 520 | PaddingAPCC 3: 0 521 | PaddingAPCC 4: 0 522 | PaddingAPCC 5: 0 523 | BasePerformanceCardPower: 300 524 | MaxPerformanceCardPower: 300 525 | BasePerformanceFrequencyCap: 0 526 | MaxPerformanceFrequencyCap: 0 527 | VDDGFX_VminLow: 2550 528 | VDDGFX_TVminLow: 0 529 | VDDGFX_VminLow_HiTemp: 0 530 | VDDGFX_VminLow_LoTemp: 0 531 | Reserved: 532 | Reserved 0: 0 533 | Reserved 1: 0 534 | Reserved 2: 0 535 | Reserved 3: 0 536 | Reserved 4: 0 537 | Reserved 5: 0 538 | Reserved 6: 0 539 | MaxVoltageStepGfx: 0 540 | MaxVoltageStepSoc: 0 541 | VddGfxVrMapping: 0 542 | VddSocVrMapping: 0 543 | VddMemVrMapping: 0 544 | BoardVrMapping: 0 545 | GfxUlvPhaseSheddingMask: 0 546 | ExternalSensorPresent: 0 547 | Padding8_V: 548 | Padding8_V 0: 0 549 | Padding8_V 1: 0 550 | GfxMaxCurrent: 0 551 | GfxOffset: 0 552 | Padding_TelemetryGfx: 0 553 | SocMaxCurrent: 0 554 | SocOffset: 0 555 | Padding_TelemetrySoc: 0 556 | MemMaxCurrent: 0 557 | MemOffset: 0 558 | Padding_TelemetryMem: 0 559 | BoardMaxCurrent: 0 560 | BoardOffset: 0 561 | Padding_TelemetryBoardInput: 0 562 | VR0HotGpio: 0 563 | VR0HotPolarity: 0 564 | VR1HotGpio: 0 565 | VR1HotPolarity: 0 566 | PllGfxclkSpreadEnabled: 0 567 | PllGfxclkSpreadPercent: 0 568 | PllGfxclkSpreadFreq: 0 569 | UclkSpreadEnabled: 0 570 | UclkSpreadPercent: 0 571 | UclkSpreadFreq: 0 572 | FclkSpreadEnabled: 0 573 | FclkSpreadPercent: 0 574 | FclkSpreadFreq: 0 575 | FllGfxclkSpreadEnabled: 0 576 | FllGfxclkSpreadPercent: 0 577 | FllGfxclkSpreadFreq: 0 578 | I2cControllers: 579 | I2cControllers 0: 580 | Enabled: 0 581 | Speed: 0 582 | Padding: 583 | Padding 0: 0 584 | Padding 1: 0 585 | SlaveAddress: 0 586 | ControllerPort: 0 587 | ControllerName: 0 588 | ThermalThrotter: 0 589 | I2cProtocol: 0 590 | I2cControllers 1: 591 | Enabled: 0 592 | Speed: 0 593 | Padding: 594 | Padding 0: 0 595 | Padding 1: 0 596 | SlaveAddress: 0 597 | ControllerPort: 0 598 | ControllerName: 0 599 | ThermalThrotter: 0 600 | I2cProtocol: 0 601 | I2cControllers 2: 602 | Enabled: 0 603 | Speed: 0 604 | Padding: 605 | Padding 0: 0 606 | Padding 1: 0 607 | SlaveAddress: 0 608 | ControllerPort: 0 609 | ControllerName: 0 610 | ThermalThrotter: 0 611 | I2cProtocol: 0 612 | I2cControllers 3: 613 | Enabled: 0 614 | Speed: 0 615 | Padding: 616 | Padding 0: 0 617 | Padding 1: 0 618 | SlaveAddress: 0 619 | ControllerPort: 0 620 | ControllerName: 0 621 | ThermalThrotter: 0 622 | I2cProtocol: 0 623 | I2cControllers 4: 624 | Enabled: 0 625 | Speed: 0 626 | Padding: 627 | Padding 0: 0 628 | Padding 1: 0 629 | SlaveAddress: 0 630 | ControllerPort: 0 631 | ControllerName: 0 632 | ThermalThrotter: 0 633 | I2cProtocol: 0 634 | I2cControllers 5: 635 | Enabled: 0 636 | Speed: 0 637 | Padding: 638 | Padding 0: 0 639 | Padding 1: 0 640 | SlaveAddress: 0 641 | ControllerPort: 0 642 | ControllerName: 0 643 | ThermalThrotter: 0 644 | I2cProtocol: 0 645 | I2cControllers 6: 646 | Enabled: 0 647 | Speed: 0 648 | Padding: 649 | Padding 0: 0 650 | Padding 1: 0 651 | SlaveAddress: 0 652 | ControllerPort: 0 653 | ControllerName: 0 654 | ThermalThrotter: 0 655 | I2cProtocol: 0 656 | I2cControllers 7: 657 | Enabled: 0 658 | Speed: 0 659 | Padding: 660 | Padding 0: 0 661 | Padding 1: 0 662 | SlaveAddress: 0 663 | ControllerPort: 0 664 | ControllerName: 0 665 | ThermalThrotter: 0 666 | I2cProtocol: 0 667 | MemoryChannelEnabled: 0 668 | DramBitWidth: 0 669 | PaddingMem: 670 | PaddingMem 0: 0 671 | PaddingMem 1: 0 672 | PaddingMem 2: 0 673 | TotalBoardPower: 0 674 | BoardPadding: 0 675 | XgmiLinkSpeed: 676 | XgmiLinkSpeed 0: 0 677 | XgmiLinkSpeed 1: 0 678 | XgmiLinkSpeed 2: 0 679 | XgmiLinkSpeed 3: 0 680 | XgmiLinkWidth: 681 | XgmiLinkWidth 0: 0 682 | XgmiLinkWidth 1: 0 683 | XgmiLinkWidth 2: 0 684 | XgmiLinkWidth 3: 0 685 | XgmiFclkFreq: 686 | XgmiFclkFreq 0: 0 687 | XgmiFclkFreq 1: 0 688 | XgmiFclkFreq 2: 0 689 | XgmiFclkFreq 3: 0 690 | XgmiSocVoltage: 691 | XgmiSocVoltage 0: 0 692 | XgmiSocVoltage 1: 0 693 | XgmiSocVoltage 2: 0 694 | XgmiSocVoltage 3: 0 695 | GpioI2cScl: 0 696 | GpioI2cSda: 0 697 | GpioPadding: 0 698 | BoardVoltageCoeffA: 0 699 | BoardVoltageCoeffB: 0 700 | BoardReserved: 701 | BoardReserved 0: 0 702 | BoardReserved 1: 0 703 | BoardReserved 2: 0 704 | BoardReserved 3: 0 705 | BoardReserved 4: 0 706 | BoardReserved 5: 0 707 | BoardReserved 6: 0 708 | MmHubPadding: 709 | MmHubPadding 0: 0 710 | MmHubPadding 1: 0 711 | MmHubPadding 2: 0 712 | MmHubPadding 3: 0 713 | MmHubPadding 4: 0 714 | MmHubPadding 5: 0 715 | MmHubPadding 6: 0 716 | MmHubPadding 7: 0 717 | -------------------------------------------------------------------------------- /test/navi23.mpt: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sibradzic/upp/3db7f14910211a82f8e2fd2f85cfd9ebbfa7192d/test/navi23.mpt -------------------------------------------------------------------------------- /test/test.sh: -------------------------------------------------------------------------------- 1 | #!/bin/bash 2 | 3 | TPU_VBIOS_URL=https://www.techpowerup.com/vgabios 4 | # RX 480 8 GB 5 | ROM_RX480=184327/AMD.RX480.8192.160603.rom 6 | # RX Vega 64 8 GB 7 | ROM_VEGA64=194441/AMD.RXVega64.8176.170719.rom 8 | # RX Vega Frontier 16 GB 9 | ROM_VEGAFRONTIER=224185/AMD.RXVegaFrontier.16384.170628.rom 10 | # Radeon VII 16 GB 11 | ROM_RADEON7=208116/AMD.RadeonVII.16384.190116.rom 12 | # RX 5700 XT 8 GB 13 | ROM_RX5700=212120/AMD.RX5700XT.8192.190616.rom 14 | # RX 6800 16 GB Reference 15 | ROM_RX6800=226802/AMD.RX6800.16384.201007.rom 16 | # RX 6900 16 GB Reference 17 | ROM_RX6900=230799/AMD.RX6900XT.16384.201104.rom 18 | # RX 7900 XTX 24GB Reference 19 | ROM_RX7900=262809/AMD.RX7900XTX.24576.230323.rom 20 | # MI100 21 | ROM_MI100=MI100_000.000.000.000.016113_113-D3431401-100.rom 22 | # RX 9070 PowerColor Reaper 23 | ROM_RX9070=274452/Powercolor.RX9070.16384.241204_1.rom 24 | 25 | # Fetch ROMs not available at TechPowerUp from these links: 26 | ROM_LINKSs=" 27 | https://github.com/sibradzic/upp/files/15254133/arcturus_vbios.zip 28 | " 29 | 30 | # ROMs to be tested: 31 | TEST_ROMS="${ROM_RX480} ${ROM_VEGA64} ${ROM_VEGAFRONTIER} 32 | ${ROM_RADEON7} ${ROM_RX5700} ${ROM_RX6900} ${ROM_RX7900} ${ROM_RX9070} 33 | ${ROM_MI100}" 34 | TEST_ROOT=${PWD} 35 | ROM_DIR=${PWD}/ROMs 36 | TMP_DIR=${PWD}/tmp 37 | 38 | [ ! -d ${ROM_DIR} ] && mkdir ${ROM_DIR} 39 | [ ! -d ${TMP_DIR} ] && mkdir ${TMP_DIR} 40 | 41 | pushd ../src 42 | 43 | # Fetch non TehcPowerUp ROMs 44 | for VBIOS in ${ROM_LINKSs}; do 45 | if [ ! -r ${ROM_DIR}/${VBIOS##*/} ]; then 46 | wget -P ${ROM_DIR} ${VBIOS} 47 | if [[ "${VBIOS##*.}" == "zip" ]]; then 48 | unzip ${ROM_DIR}/${VBIOS##*/} -d ${ROM_DIR} 49 | fi 50 | fi 51 | done 52 | 53 | # Fetch TehcPowerUp ROMs and test all ROMs 54 | for VBIOS in ${TEST_ROMS}; do 55 | if [ ! -r ${ROM_DIR}/${VBIOS#*/} ]; then 56 | wget -P ${ROM_DIR} ${TPU_VBIOS_URL}/${VBIOS} 57 | fi 58 | python3 -m upp.upp -p ${TMP_DIR}/${VBIOS#*/}.pp_table extract -r ${ROM_DIR}/${VBIOS#*/} 59 | python3 -m upp.upp -p ${TMP_DIR}/${VBIOS#*/}.pp_table dump > ${TMP_DIR}/${VBIOS#*/}.dump 60 | python3 -m upp.upp -p ${TMP_DIR}/${VBIOS#*/}.pp_table dump -r > ${TMP_DIR}/${VBIOS#*/}.rawdump 61 | diff -s ${TEST_ROOT}/${VBIOS#*/}.dump ${TMP_DIR}/${VBIOS#*/}.dump 62 | if [ $? -ne "0" ]; then 63 | echo "ERROR in ${TMP_DIR}/${VBIOS#*/}.dump:" 64 | diff -u ${TEST_ROOT}/${VBIOS#*/}.dump ${TMP_DIR}/${VBIOS#*/}.dump 65 | printf "\033[1m${VBIOS#*/} dump check \033[1;31mERROR\033[0m\n" 66 | exit 2 67 | else 68 | printf "\033[1m${VBIOS#*/} dump check \033[1;32mOK\033[0m\n\n" 69 | fi 70 | diff -s ${TEST_ROOT}/${VBIOS#*/}.rawdump ${TMP_DIR}/${VBIOS#*/}.rawdump 71 | if [ $? -ne "0" ]; then 72 | echo "ERROR in ${TMP_DIR}/${VBIOS#*/}.rawdump:" 73 | diff -u ${TEST_ROOT}/${VBIOS#*/}.rawdump ${TMP_DIR}/${VBIOS#*/}.rawdump 74 | printf "\033[1m${VBIOS#*/} raw dump check \033[1;31mERROR\033[0m\n" 75 | exit 2 76 | else 77 | printf "\033[1m${VBIOS#*/} raw dump check \033[1;32mOK\033[0m\n\n" 78 | fi 79 | done 80 | 81 | cp ${TMP_DIR}/${ROM_RX5700#*/}.pp_table ${TMP_DIR}/${ROM_RX5700#*/}.conf.pp_table 82 | 83 | # Value write test 84 | python3 -m upp.upp -p ${TMP_DIR}/${ROM_RX5700#*/}.pp_table set --write \ 85 | smc_pptable/SocketPowerLimitAc/0=110 \ 86 | smc_pptable/SocketPowerLimitDc/0=110 \ 87 | smc_pptable/FanStartTemp=100 \ 88 | smc_pptable/MinVoltageGfx=2800 \ 89 | smc_pptable/MaxVoltageGfx=3900 \ 90 | smc_pptable/MinVoltageSoc=2800 \ 91 | smc_pptable/MaxVoltageSoc=3800 \ 92 | smc_pptable/qStaticVoltageOffset/0/c=-0.03 \ 93 | smc_pptable/UlvVoltageOffsetSoc=0 \ 94 | smc_pptable/UlvVoltageOffsetGfx=0 \ 95 | smc_pptable/FreqTableGfx/1=1650 \ 96 | smc_pptable/MemMvddVoltage/0=4400 \ 97 | smc_pptable/MemVddciVoltage/0=2600 \ 98 | smc_pptable/MemMvddVoltage/1=4600 \ 99 | smc_pptable/MemVddciVoltage/1=3200 \ 100 | smc_pptable/MemMvddVoltage/2=4800 \ 101 | smc_pptable/MemVddciVoltage/2=3200 \ 102 | smc_pptable/MemMvddVoltage/3=5000 \ 103 | smc_pptable/MemVddciVoltage/3=3200 \ 104 | smc_pptable/FreqTableUclk/3=750 105 | 106 | python3 -m upp.upp -p ${TMP_DIR}/${ROM_RX5700#*/}.pp_table get \ 107 | smc_pptable/SocketPowerLimitAc/0 \ 108 | smc_pptable/SocketPowerLimitDc/0 \ 109 | smc_pptable/FanStartTemp \ 110 | smc_pptable/MinVoltageGfx \ 111 | smc_pptable/MaxVoltageGfx \ 112 | smc_pptable/MinVoltageSoc \ 113 | smc_pptable/MaxVoltageSoc \ 114 | smc_pptable/qStaticVoltageOffset/0/c \ 115 | smc_pptable/UlvVoltageOffsetSoc \ 116 | smc_pptable/UlvVoltageOffsetGfx \ 117 | smc_pptable/FreqTableGfx/1 \ 118 | smc_pptable/MemMvddVoltage/0 \ 119 | smc_pptable/MemVddciVoltage/0 \ 120 | smc_pptable/MemMvddVoltage/1 \ 121 | smc_pptable/MemVddciVoltage/1 \ 122 | smc_pptable/MemMvddVoltage/2 \ 123 | smc_pptable/MemVddciVoltage/2 \ 124 | smc_pptable/MemMvddVoltage/3 \ 125 | smc_pptable/MemVddciVoltage/3 \ 126 | smc_pptable/FreqTableUclk/3 \ 127 | > ${TMP_DIR}/${ROM_RX5700#*/}.check 128 | 129 | diff -s ${TEST_ROOT}/${ROM_RX5700#*/}.check ${TMP_DIR}/${ROM_RX5700#*/}.check 130 | if [ $? -ne "0" ]; then 131 | echo "ERROR in ${TMP_DIR}/${ROM_RX5700#*/}.check:" 132 | diff -u ${TEST_ROOT}/${ROM_RX5700#*/}.check ${TMP_DIR}/${ROM_RX5700#*/}.check 133 | printf "\033[1m${ROM_RX5700#*/} value write check \033[1;31mERROR\033[0m\n" 134 | exit 2 135 | else 136 | printf "\033[1m${ROM_RX5700#*/} value write check \033[1;32mOK\033[0m\n\n" 137 | fi 138 | 139 | # Value write from .conf test 140 | python3 -m upp.upp -p ${TMP_DIR}/${ROM_RX5700#*/}.conf.pp_table set \ 141 | --from-conf=${TEST_ROOT}/${ROM_RX5700#*/}.conf --write 142 | 143 | python3 -m upp.upp -p ${TMP_DIR}/${ROM_RX5700#*/}.conf.pp_table get \ 144 | smc_pptable/SocketPowerLimitAc/0 \ 145 | smc_pptable/SocketPowerLimitDc/0 \ 146 | smc_pptable/FanStartTemp \ 147 | smc_pptable/MinVoltageGfx \ 148 | smc_pptable/MaxVoltageGfx \ 149 | smc_pptable/MinVoltageSoc \ 150 | smc_pptable/MaxVoltageSoc \ 151 | smc_pptable/qStaticVoltageOffset/0/c \ 152 | smc_pptable/UlvVoltageOffsetSoc \ 153 | smc_pptable/UlvVoltageOffsetGfx \ 154 | smc_pptable/FreqTableGfx/1 \ 155 | smc_pptable/MemMvddVoltage/0 \ 156 | smc_pptable/MemVddciVoltage/0 \ 157 | smc_pptable/MemMvddVoltage/1 \ 158 | smc_pptable/MemVddciVoltage/1 \ 159 | smc_pptable/MemMvddVoltage/2 \ 160 | smc_pptable/MemVddciVoltage/2 \ 161 | smc_pptable/MemMvddVoltage/3 \ 162 | smc_pptable/MemVddciVoltage/3 \ 163 | smc_pptable/FreqTableUclk/3 \ 164 | > ${TMP_DIR}/${ROM_RX5700#*/}.conf.check 165 | 166 | diff -s ${TEST_ROOT}/${ROM_RX5700#*/}.check ${TMP_DIR}/${ROM_RX5700#*/}.check 167 | if [ $? -ne "0" ]; then 168 | echo "ERROR in ${TMP_DIR}/${ROM_RX5700#*/}.check:" 169 | diff -u ${TEST_ROOT}/${ROM_RX5700#*/}.check ${TMP_DIR}/${ROM_RX5700#*/}.check 170 | printf "\033[1m${ROM_RX5700#*/} value write from conf check \033[1;31mERROR\033[0m\n" 171 | exit 2 172 | else 173 | printf "\033[1m${ROM_RX5700#*/} value write from conf check \033[1;32mOK\033[0m\n\n" 174 | fi 175 | -------------------------------------------------------------------------------- /upliftpowerplay@.service: -------------------------------------------------------------------------------- 1 | [Unit] 2 | Description=Uplift Power Play 3 | Before=amdgpu-clocks.service 4 | Wants=modprobe@amdgpu.service 5 | 6 | [Service] 7 | Type=oneshot 8 | ExecStartPre=/usr/bin/bash -c "echo "profile_peak" > /sys/class/drm/%i/device/power_dpm_force_performance_level" 9 | ExecStart=/usr/bin/upp --pp-file=/sys/class/drm/%i/device/pp_table set --from-conf=/etc/upliftpowerplay/%i.conf --write 10 | ExecStopPost=/usr/bin/bash -c "echo "auto" > /sys/class/drm/%i/device/power_dpm_force_performance_level" 11 | 12 | [Install] 13 | WantedBy=multi-user.target 14 | --------------------------------------------------------------------------------