├── .gitignore ├── cores ├── and │ ├── boards │ │ ├── tinyfpga_bx │ │ │ └── pinout.pcf │ │ └── nexys_a7 │ │ │ └── pinout.xdc │ ├── rtl │ │ └── and.v │ ├── synth │ │ └── top.v │ ├── tb │ │ └── and.tb.v │ ├── scripts │ │ └── proginfo.py │ └── and.core ├── or │ ├── boards │ │ ├── tinyfpga_bx │ │ │ └── pinout.pcf │ │ └── nexys_a7 │ │ │ └── pinout.xdc │ ├── rtl │ │ └── or.v │ ├── synth │ │ └── top.v │ ├── tb │ │ └── or.tb.v │ ├── scripts │ │ └── proginfo.py │ └── or.core └── and_or │ ├── boards │ ├── tinyfpga_bx │ │ └── pinout.pcf │ └── nexys_a7 │ │ └── pinout.xdc │ ├── synth │ └── top.v │ ├── tb │ └── and_or.tb.v │ ├── scripts │ └── proginfo.py │ └── and_or.core ├── .vscode ├── extensions.json └── settings.json └── README.md /.gitignore: -------------------------------------------------------------------------------- 1 | 2 | # From FuseSoC Testing 3 | **/build 4 | **/fusesoc.conf 5 | -------------------------------------------------------------------------------- /cores/and/boards/tinyfpga_bx/pinout.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io a A1 3 | set_io b A2 4 | set_io c B3 5 | -------------------------------------------------------------------------------- /cores/or/boards/tinyfpga_bx/pinout.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io a A1 3 | set_io b A2 4 | set_io c B3 5 | -------------------------------------------------------------------------------- /.vscode/extensions.json: -------------------------------------------------------------------------------- 1 | { 2 | "recommendations": [ 3 | "mshr-h.veriloghdl" 4 | ] 5 | } 6 | -------------------------------------------------------------------------------- /cores/and_or/boards/tinyfpga_bx/pinout.pcf: -------------------------------------------------------------------------------- 1 | 2 | set_io a A1 3 | set_io b A2 4 | set_io and_o B1 5 | set_io or_o C2 6 | -------------------------------------------------------------------------------- /.vscode/settings.json: -------------------------------------------------------------------------------- 1 | { 2 | "verilog.linting.iverilog.arguments": "-Wall -g2012 -DLINTER=1", 3 | "verilog.linting.linter": "iverilog" 4 | } 5 | -------------------------------------------------------------------------------- /cores/or/rtl/or.v: -------------------------------------------------------------------------------- 1 | 2 | /* or.v */ 3 | 4 | 5 | module or_m ( 6 | input a, b, 7 | output wire c 8 | ); 9 | 10 | assign c = a | b; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /cores/and/rtl/and.v: -------------------------------------------------------------------------------- 1 | 2 | /* and.v */ 3 | 4 | 5 | module and_m ( 6 | input a, b, 7 | output wire c 8 | ); 9 | 10 | assign c = a & b; 11 | 12 | endmodule 13 | -------------------------------------------------------------------------------- /cores/or/synth/top.v: -------------------------------------------------------------------------------- 1 | 2 | /* or.tb.v */ 3 | 4 | 5 | `ifdef LINTER 6 | `include "cores/or/rtl/or.v" 7 | `endif 8 | 9 | 10 | module top_m ( 11 | input a, b, 12 | output wire c 13 | ); 14 | 15 | or_m or_gate ( 16 | .a(a), 17 | .b(b), 18 | .c(c) 19 | ); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /cores/and/synth/top.v: -------------------------------------------------------------------------------- 1 | 2 | /* and.tb.v */ 3 | 4 | 5 | `ifdef LINTER 6 | `include "cores/and/rtl/and.v" 7 | `endif 8 | 9 | 10 | module top_m ( 11 | input a, b, 12 | output wire c 13 | ); 14 | 15 | and_m and_gate ( 16 | .a(a), 17 | .b(b), 18 | .c(c) 19 | ); 20 | 21 | endmodule 22 | -------------------------------------------------------------------------------- /cores/and/boards/nexys_a7/pinout.xdc: -------------------------------------------------------------------------------- 1 | 2 | set_property PACKAGE_PIN V10 [get_ports a] 3 | set_property IOSTANDARD LVCMOS33 [get_ports a] 4 | 5 | set_property PACKAGE_PIN U11 [get_ports b] 6 | set_property IOSTANDARD LVCMOS33 [get_ports b] 7 | 8 | set_property PACKAGE_PIN V11 [get_ports c] 9 | set_property IOSTANDARD LVCMOS33 [get_ports c] 10 | set_property DRIVE 12 [get_ports c] 11 | set_property SLEW FAST [get_ports c] 12 | -------------------------------------------------------------------------------- /cores/or/boards/nexys_a7/pinout.xdc: -------------------------------------------------------------------------------- 1 | 2 | set_property PACKAGE_PIN V10 [get_ports a] 3 | set_property IOSTANDARD LVCMOS33 [get_ports a] 4 | 5 | set_property PACKAGE_PIN U11 [get_ports b] 6 | set_property IOSTANDARD LVCMOS33 [get_ports b] 7 | 8 | set_property PACKAGE_PIN V12 [get_ports c] 9 | set_property IOSTANDARD LVCMOS33 [get_ports c] 10 | set_property DRIVE 12 [get_ports c] 11 | set_property SLEW FAST [get_ports c] 12 | -------------------------------------------------------------------------------- /cores/and_or/synth/top.v: -------------------------------------------------------------------------------- 1 | 2 | /* and_or.tb.v */ 3 | 4 | 5 | `ifdef LINTER 6 | `include "cores/and/rtl/and.v" 7 | `include "cores/or/rtl/or.v" 8 | `endif 9 | 10 | 11 | module top_m ( 12 | input a, b, 13 | output wire and_o, or_o 14 | ); 15 | 16 | and_m and_gate ( 17 | .a(a), 18 | .b(b), 19 | .c(and_o) 20 | ); 21 | 22 | or_m or_gate ( 23 | .a(a), 24 | .b(b), 25 | .c(or_o) 26 | ); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /cores/and_or/boards/nexys_a7/pinout.xdc: -------------------------------------------------------------------------------- 1 | 2 | set_property PACKAGE_PIN V10 [get_ports a] 3 | set_property IOSTANDARD LVCMOS33 [get_ports a] 4 | 5 | set_property PACKAGE_PIN U11 [get_ports b] 6 | set_property IOSTANDARD LVCMOS33 [get_ports b] 7 | 8 | set_property PACKAGE_PIN V11 [get_ports and_o] 9 | set_property IOSTANDARD LVCMOS33 [get_ports and_o] 10 | set_property DRIVE 12 [get_ports and_o] 11 | set_property SLEW FAST [get_ports and_o] 12 | 13 | set_property PACKAGE_PIN V12 [get_ports or_o] 14 | set_property IOSTANDARD LVCMOS33 [get_ports or_o] 15 | set_property DRIVE 12 [get_ports or_o] 16 | set_property SLEW FAST [get_ports or_o] 17 | -------------------------------------------------------------------------------- /cores/or/tb/or.tb.v: -------------------------------------------------------------------------------- 1 | 2 | /* or.tb.v */ 3 | 4 | 5 | `ifdef LINTER 6 | `include "cores/or/rtl/or.v" 7 | `endif 8 | 9 | 10 | module or_tb (); 11 | 12 | reg a, b; 13 | wire c; 14 | 15 | or_m or_gate ( 16 | .a(a), 17 | .b(b), 18 | .c(c) 19 | ); 20 | 21 | initial begin 22 | $dumpfile( "dump.vcd" ); 23 | $dumpvars; 24 | $display( "Begin simulation."); 25 | //\\ =========================== \\// 26 | 27 | { a, b } = 2'b00; #1 28 | { a, b } = 2'b01; #1 29 | { a, b } = 2'b10; #1 30 | { a, b } = 2'b11; #1 31 | 32 | //\\ =========================== \\// 33 | $display( "End simulation."); 34 | $finish; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /cores/and/tb/and.tb.v: -------------------------------------------------------------------------------- 1 | 2 | /* and.tb.v */ 3 | 4 | 5 | `ifdef LINTER 6 | `include "cores/and/rtl/and.v" 7 | `endif 8 | 9 | 10 | module and_tb (); 11 | 12 | reg a, b; 13 | wire c; 14 | 15 | and_m and_gate ( 16 | .a(a), 17 | .b(b), 18 | .c(c) 19 | ); 20 | 21 | initial begin 22 | $dumpfile( "dump.vcd" ); 23 | $dumpvars; 24 | $display( "Begin simulation."); 25 | //\\ =========================== \\// 26 | 27 | { a, b } = 2'b00; #1 28 | { a, b } = 2'b01; #1 29 | { a, b } = 2'b10; #1 30 | { a, b } = 2'b11; #1 31 | 32 | //\\ =========================== \\// 33 | $display( "End simulation."); 34 | $finish; 35 | end 36 | 37 | endmodule 38 | -------------------------------------------------------------------------------- /cores/and_or/tb/and_or.tb.v: -------------------------------------------------------------------------------- 1 | 2 | /* and_or.tb.v */ 3 | 4 | 5 | `ifdef LINTER 6 | `include "cores/and/rtl/and.v" 7 | `include "cores/or/rtl/or.v" 8 | `endif 9 | 10 | 11 | module and_or_tb (); 12 | 13 | reg a, b; 14 | wire and_o, or_o; 15 | 16 | and_m and_gate ( 17 | .a(a), 18 | .b(b), 19 | .c(and_o) 20 | ); 21 | 22 | or_m or_gate ( 23 | .a(a), 24 | .b(b), 25 | .c(or_o) 26 | ); 27 | 28 | initial begin 29 | $dumpfile( "dump.vcd" ); 30 | $dumpvars; 31 | $display( "Begin simulation."); 32 | //\\ =========================== \\// 33 | 34 | { a, b } = 2'b00; #1 35 | { a, b } = 2'b01; #1 36 | { a, b } = 2'b10; #1 37 | { a, b } = 2'b11; #1 38 | 39 | //\\ =========================== \\// 40 | $display( "End simulation."); 41 | $finish; 42 | end 43 | 44 | endmodule 45 | -------------------------------------------------------------------------------- /cores/and/scripts/proginfo.py: -------------------------------------------------------------------------------- 1 | # https://github.com/fusesoc/blinky/blob/c1c2636c172f471718bfc78cba9e4c8076ac96df/sw/proginfo.py 2 | 3 | import os 4 | import sys 5 | 6 | system_name = "e4tham_templates_and_1.0.0" 7 | print("") 8 | print("Build was completed") 9 | print("") 10 | print("To program the board run:") 11 | if sys.argv[1] == 'tinyprog': 12 | print("tinyprog --program {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 13 | elif sys.argv[1] == 'iceprog': 14 | print("iceprog {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 15 | elif sys.argv[1] == 'ujprog': 16 | print("ujprog {}".format(os.path.join(os.getcwd(), "Implementation0", system_name+"_Implementation0.bit"))) 17 | print("Other programming options are listed here https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md#programming-options") 18 | elif sys.argv[1] == 'dfu-util': 19 | print("dfu-util -d 1209:5af0 -D {}".format(os.path.join(os.getcwd(), system_name+".bit"))) 20 | elif sys.argv[1] == 'dfu-util-fomu': 21 | print("Download and install dfu-util from http://dfu-util.sourceforge.net/") 22 | print("dfu-util -e -d 1209:5bf0 -D {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 23 | -------------------------------------------------------------------------------- /cores/or/scripts/proginfo.py: -------------------------------------------------------------------------------- 1 | # https://github.com/fusesoc/blinky/blob/c1c2636c172f471718bfc78cba9e4c8076ac96df/sw/proginfo.py 2 | 3 | import os 4 | import sys 5 | 6 | system_name = "e4tham_templates_or_1.0.0" 7 | print("") 8 | print("Build was completed") 9 | print("") 10 | print("To program the board run:") 11 | if sys.argv[1] == 'tinyprog': 12 | print("tinyprog --program {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 13 | elif sys.argv[1] == 'iceprog': 14 | print("iceprog {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 15 | elif sys.argv[1] == 'ujprog': 16 | print("ujprog {}".format(os.path.join(os.getcwd(), "Implementation0", system_name+"_Implementation0.bit"))) 17 | print("Other programming options are listed here https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md#programming-options") 18 | elif sys.argv[1] == 'dfu-util': 19 | print("dfu-util -d 1209:5af0 -D {}".format(os.path.join(os.getcwd(), system_name+".bit"))) 20 | elif sys.argv[1] == 'dfu-util-fomu': 21 | print("Download and install dfu-util from http://dfu-util.sourceforge.net/") 22 | print("dfu-util -e -d 1209:5bf0 -D {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 23 | -------------------------------------------------------------------------------- /cores/and_or/scripts/proginfo.py: -------------------------------------------------------------------------------- 1 | # https://github.com/fusesoc/blinky/blob/c1c2636c172f471718bfc78cba9e4c8076ac96df/sw/proginfo.py 2 | 3 | import os 4 | import sys 5 | 6 | system_name = "e4tham_templates_and_or_1.0.0" 7 | print("") 8 | print("Build was completed") 9 | print("") 10 | print("To program the board run:") 11 | if sys.argv[1] == 'tinyprog': 12 | print("tinyprog --program {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 13 | elif sys.argv[1] == 'iceprog': 14 | print("iceprog {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 15 | elif sys.argv[1] == 'ujprog': 16 | print("ujprog {}".format(os.path.join(os.getcwd(), "Implementation0", system_name+"_Implementation0.bit"))) 17 | print("Other programming options are listed here https://github.com/emard/ulx3s/blob/master/doc/MANUAL.md#programming-options") 18 | elif sys.argv[1] == 'dfu-util': 19 | print("dfu-util -d 1209:5af0 -D {}".format(os.path.join(os.getcwd(), system_name+".bit"))) 20 | elif sys.argv[1] == 'dfu-util-fomu': 21 | print("Download and install dfu-util from http://dfu-util.sourceforge.net/") 22 | print("dfu-util -e -d 1209:5bf0 -D {}".format(os.path.join(os.getcwd(), system_name+".bin"))) 23 | -------------------------------------------------------------------------------- /cores/and/and.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: e4tham:templates:and:1.0.0 3 | description: And gate 4 | 5 | # Source Files https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html#targets 6 | filesets: 7 | # default 8 | rtl: 9 | files: 10 | - rtl/and.v: {file_type: verilogSource} 11 | # simulation 12 | tb: 13 | files: 14 | - tb/and.tb.v: {file_type: verilogSource} 15 | # synthesis 16 | synth: 17 | files: 18 | - synth/top.v: {file_type: verilogSource} 19 | proginfo: 20 | files: 21 | - scripts/proginfo.py: {file_type : user, copyto : proginfo.py} 22 | # boards 23 | tinyfpga_bx: 24 | files: 25 | - boards/tinyfpga_bx/pinout.pcf: {file_type: PCF} 26 | nexys_a7: 27 | files: 28 | - boards/nexys_a7/pinout.xdc: {file_type: xdc} 29 | 30 | 31 | # Targets https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html#targets 32 | targets: 33 | default: &default 34 | filesets: 35 | - rtl 36 | synth: &synth 37 | filesets: 38 | - rtl 39 | - synth 40 | toplevel: top_m 41 | 42 | sim: # fusesoc run --target sim e4tham:templates:and 43 | <<: *default 44 | description: Simulate the design 45 | default_tool: icarus 46 | filesets_append: 47 | - tb 48 | toplevel: and_tb 49 | tools: 50 | icarus: 51 | iverilog_options: 52 | - -g2012 # Use SystemVerilog-2012 53 | 54 | tinyfpga_bx: 55 | <<: *synth 56 | description: Synthesize on TinyFPGA BX 57 | filesets_append: 58 | - proginfo 59 | - tinyfpga_bx 60 | default_tool: icestorm 61 | hooks: 62 | post_run: [tinyprog] 63 | tools: 64 | icestorm: 65 | nextpnr_options : [--lp8k, --package, cm81] 66 | pnr: next 67 | 68 | nexys_a7: 69 | <<: *synth 70 | description: Synthesize on Nexys A7 71 | filesets_append: 72 | - nexys_a7 73 | default_tool: vivado 74 | tools: 75 | vivado: 76 | part : xc7a100tcsg324-1 77 | 78 | 79 | scripts: 80 | tinyprog: 81 | cmd: [python3, proginfo.py, tinyprog] 82 | -------------------------------------------------------------------------------- /cores/or/or.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: e4tham:templates:or:1.0.0 3 | description: Or gate 4 | 5 | # Source Files https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html#targets 6 | filesets: 7 | # default 8 | rtl: 9 | files: 10 | - rtl/or.v: {file_type: verilogSource} 11 | # simulation 12 | tb: 13 | files: 14 | - tb/or.tb.v: {file_type: verilogSource} 15 | # synthesis 16 | synth: 17 | files: 18 | - synth/top.v: {file_type: verilogSource} 19 | proginfo: 20 | files: 21 | - scripts/proginfo.py: {file_type : user, copyto : proginfo.py} 22 | # boards 23 | tinyfpga_bx: 24 | files: 25 | - boards/tinyfpga_bx/pinout.pcf: {file_type: PCF} 26 | nexys_a7: 27 | files: 28 | - boards/nexys_a7/pinout.xdc: {file_type: xdc} 29 | 30 | 31 | # Targets https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html#targets 32 | targets: 33 | default: &default 34 | filesets: 35 | - rtl 36 | synth: &synth 37 | filesets: 38 | - rtl 39 | - synth 40 | toplevel: top_m 41 | 42 | # The "sim" target simulates the design 43 | sim: # fusesoc run --target=sim e4tham:templates:or:1.0.0 44 | <<: *default 45 | description: Simulate the design 46 | default_tool: icarus 47 | filesets_append: 48 | - tb 49 | toplevel: or_tb 50 | tools: 51 | icarus: 52 | iverilog_options: 53 | - -g2012 # Use SystemVerilog-2012 54 | 55 | tinyfpga_bx: 56 | <<: *synth 57 | description: Synthesize on TinyFPGA BX 58 | filesets_append: 59 | - proginfo 60 | - tinyfpga_bx 61 | default_tool: icestorm 62 | hooks: 63 | post_run: [tinyprog] 64 | tools: 65 | icestorm: 66 | nextpnr_options : [--lp8k, --package, cm81] 67 | pnr: next 68 | 69 | nexys_a7: 70 | <<: *synth 71 | description: Synthesize on Nexys A7 72 | filesets_append: 73 | - nexys_a7 74 | default_tool: vivado 75 | tools: 76 | vivado: 77 | part : xc7a100tcsg324-1 78 | 79 | 80 | scripts: 81 | tinyprog: 82 | cmd: [python3, proginfo.py, tinyprog] 83 | -------------------------------------------------------------------------------- /cores/and_or/and_or.core: -------------------------------------------------------------------------------- 1 | CAPI=2: 2 | name: e4tham:templates:and_or:1.0.0 3 | description: And & or gate 4 | 5 | # Source Files https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html#targets 6 | filesets: 7 | # default 8 | rtl: 9 | depend: 10 | - e4tham:templates:and 11 | - e4tham:templates:or 12 | # simulation 13 | tb: 14 | files: 15 | - tb/and_or.tb.v: {file_type: verilogSource} 16 | # synthesis 17 | synth: 18 | files: 19 | - synth/top.v: {file_type: verilogSource} 20 | proginfo: 21 | files: 22 | - scripts/proginfo.py: {file_type : user, copyto : proginfo.py} 23 | # boards 24 | tinyfpga_bx: 25 | files: 26 | - boards/tinyfpga_bx/pinout.pcf: {file_type: PCF} 27 | nexys_a7: 28 | files: 29 | - boards/nexys_a7/pinout.xdc: {file_type: xdc} 30 | 31 | 32 | # Targets https://fusesoc.readthedocs.io/en/stable/user/build_system/core_files.html#targets 33 | targets: 34 | default: &default 35 | filesets: 36 | - rtl 37 | synth: &synth 38 | filesets: 39 | - rtl 40 | - synth 41 | toplevel: top_m 42 | 43 | # The "sim" target simulates the design 44 | sim: # fusesoc run --target=sim e4tham:templates:and_or:1.0 45 | <<: *default 46 | description: Simulate the design 47 | default_tool: icarus 48 | filesets_append: 49 | - tb 50 | toplevel: and_or_tb 51 | tools: 52 | icarus: 53 | iverilog_options: 54 | - -g2012 # Use SystemVerilog-2012 55 | 56 | tinyfpga_bx: 57 | <<: *synth 58 | description: Synthesize on TinyFPGA BX 59 | filesets_append: 60 | - proginfo 61 | - tinyfpga_bx 62 | default_tool: icestorm 63 | hooks: 64 | post_run: [tinyprog] 65 | tools: 66 | icestorm: 67 | nextpnr_options : [--lp8k, --package, cm81] 68 | pnr: next 69 | 70 | nexys_a7: 71 | <<: *synth 72 | description: Synthesize on Nexys A7 73 | filesets_append: 74 | - nexys_a7 75 | default_tool: vivado 76 | tools: 77 | vivado: 78 | part : xc7a100tcsg324-1 79 | 80 | 81 | scripts: 82 | tinyprog: 83 | cmd: [python3, proginfo.py, tinyprog] 84 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | # FuseSoC 5 | 6 | Repository: 7 | 8 | ## About 9 | 10 | This repository gives an example of getting started with [FuseSoC](https://github.com/olofk/fusesoc), the best HDL package manager available. 11 | 12 | [Install FuseSoc from here](https://fusesoc.readthedocs.io/en/stable/user/installation.html) 13 | 14 | This repository has three different cores: 15 | 16 | * `e4tham:templates:and` 17 | * `e4tham:templates:or` 18 | * `e4tham:templates:and_or` 19 | 20 | ## Supported Software 21 | 22 | * [Icarus Verilog](https://www.howtoinstall.me/ubuntu/18-04/iverilog/) 23 | * [IceStorm, nextpnr, Yosys](http://bygone.clairexen.net/icestorm/#install) 24 | * [Vivado](https://www.xilinx.com/support/download.html) 25 | 26 | ## Supported Hardware 27 | 28 | * [TinyFPGA BX](https://tinyfpga.com/) 29 | * [Nexys A7](https://store.digilentinc.com/nexys-a7-fpga-trainer-board-recommended-for-ece-curriculum/) 30 | 31 | ## Getting Started 32 | 33 | ### To add this library via Git 34 | 35 | ```bash 36 | fusesoc library add e4tham_templates https://github.com/E4tHam/fusesoc_template --sync-type=git 37 | ``` 38 | 39 | ### To add this library from local clone 40 | 41 | ```bash 42 | fusesoc library add e4tham_templates ${fusesoc_template_location}/cores --sync-type=local 43 | ``` 44 | 45 | ## Usage 46 | 47 | ### `e4tham:templates:and` 48 | 49 | ```bash 50 | # Simulate in Icarus Verilog 51 | fusesoc run --target=sim e4tham:templates:and:1.0.0 52 | # Synthesize for TinyFPGA BX 53 | fusesoc run --target=tinyfpga_bx e4tham:templates:and:1.0.0 54 | # Synthesize for Nexys A7 55 | fusesoc run --target=nexys_a7 e4tham:templates:and:1.0.0 56 | ``` 57 | 58 | ### `e4tham:templates:or` 59 | 60 | ```bash 61 | # Simulate in Icarus Verilog 62 | fusesoc run --target=sim e4tham:templates:or:1.0.0 63 | # Synthesize for TinyFPGA BX 64 | fusesoc run --target=tinyfpga_bx e4tham:templates:or:1.0.0 65 | # Synthesize for Nexys A7 66 | fusesoc run --target=nexys_a7 e4tham:templates:or:1.0.0 67 | ``` 68 | 69 | ### `e4tham:templates:and_or` 70 | 71 | ```bash 72 | # Simulate in Icarus Verilog 73 | fusesoc run --target=sim e4tham:templates:and_or:1.0.0 74 | # Synthesize for TinyFPGA BX 75 | fusesoc run --target=tinyfpga_bx e4tham:templates:and_or:1.0.0 76 | # Synthesize for Nexys A7 77 | fusesoc run --target=nexys_a7 e4tham:templates:and_or:1.0.0 78 | ``` 79 | --------------------------------------------------------------------------------