├── LICENSE ├── README.md ├── docs ├── AHMY_SP6LX9_LT_Spartan6-TechRef.pdf ├── datasheet-LM70-TI-tempSensor.pdf ├── datasheet-temp-humidity-5193-DHT20.pdf └── tempMonitor-blockDiag-v1-0322.png └── verilog ├── TB-tsense-SPI.v ├── cheatsheet.v ├── run └── tsense-SPI.v /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2022 Advanced VLSI Lab, Silicon Institute of Technology 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # VLSI-2024 2 | Portal for 2024 SIT batch being mentored at the Advnaced VLSI Lab. 3 | 4 | # TABLE OF CONTENT 5 | 6 | - [Resources](#RESOURCES) 7 | - [Reference](#References) 8 | - [Tasks & Assignments](#TASKS-and-ASSIGNMENTS) 9 | - [Projects](#projects) 10 | - [SPI-based TEMPERATURE MONITOR](#SPI-based-TEMPERATURE-MONITOR) 11 | - [Temperature and Humidity Monitor](#TEMPERATURE-and-HUMIDITY-MONITOR) 12 | - [A Simple 8-bit MIPS Microprocessor](#A-SIMPLE-8-bit-MIPS-MICROPROCESSOR) 13 | - [Electronic Design Automation (EDA) Software](#ELECTRONIC-DESIGN-AUTOMATION-SOFTWARE) 14 | - [Installing Icarus Verilog with GTKWave](#INSTALLING-ICARUS-VERILOG-with-GTKWAVE) 15 | 16 | # RESOURCES 17 | 18 | ## References 19 | - [**Mano**] Mano, M. Morris, and Michael D. Ciletti. **Digital Design**: With an Introduction to the **Verilog** HDL. Pearson, 2012. [`DBURL/s/54xsb46wcj6hdn9/ManoCiletti-DigitalDesignWithIntroToVerilog-5thEd-2012.pdf`]. -- Classic text on digital theory with a nice intro to HDL. 20 | - [**West**] Weste, Neil, and David **Harris**. **CMOS VLSI Design**: A Circuits and Systems Perspective. Pearson Education, 2011. [`DBURL/s/ard8jntcpq1pt45/Weste-Harris-CMOS-VLSI-design-Pearson-4thEd-2011.pdf`] -- An excellent reference on Digital VLSI design and VLSI design process as well. 21 | - [**Web Companion**] http://pages.hmc.edu/harris/cmosvlsi/4e/index.html 22 | - **Annotated Chapters for Processing** [`DBURL/s/zxp1dnwknvpfz8y/Weste-JohnsMartin-CMOSprocessing-Layout-Highlight-annotate.pdf` 23 | - [**Kang**] Leblebici, Yusuf, Chul Woo Kim, and Sung-Mo (Steve) Kang. **CMOS Digital Integrated Circuits Analysis & Design**. 4th ed. McGraw-Hill Education, 2014. [`DBURL/s/axtrki5yilzg8zs/Kang-CMOS-DigitalIC-4thIE-McGrawHill-2015.pdf`] -- Classic text on CMOS VLSI Design. 24 | - [**Hodges**]] Hodges, David A., and David. **Analysis And Design Of Digital Integrated Circuits**, In Deep Submicron Technology (Special Indian Edition). Tata McGraw-Hill Education, 2005. [`DBURL/s/olc3j7hkarlwila/HodgesJackson-DesignAndAnalysisOfDigitalIC-3Ed-McGraw-2005.pdf`]. -- Another classic text on CMOS VLSI Design. 25 | - [**Palnitkar**] Palnitkar, Samir. **Verilog HDL**: A Guide to Digital Design and Synthesis. Prentice Hall Professional, 2003. [`DBURL/s/h5qxwwff3qxl58z/PalnitkarSamir-VerilogHDL-2ndEd-2003.pdf`]. -- Classic text on Verilog. 26 | - [**Mishra**] Mishra, Kishore. **Advanced Chip Design**: Practical Examples in Verilog, 2013. [`DBURL/s/qb3rm97rqvri6my/MishraKishore-AdvancedChipDesign-Verilog.pdf`]. -- Lots of Verilog examples. 27 | 28 | 29 | # TASKS and ASSIGNMENTS 30 | 31 | - [23 Dec 2022]: 32 | - Research and understand the I2C protocol. You can start with some of the links provided below. 33 | - Create a Verilog model for the [DHT20](https://www.dropbox.com/s/h3shzfsain3r9li/datasheet-temp-humidity-5193-DHT20.pdf) temp & humidity sensor. 34 | - Continue with the Verilog lessons from chipverify.com 35 | - [21 Sep 2022]: Follow the first 8 lessons in this [GitHub page](https://github.com/silicon-vlsi-org/module-cs3-301) to get familiar with and improve your skill in using Unix/Linux commands. You can use any Linux machine (webinal or your Virtual Box) to complete the assignement. 36 | 37 | # PROJECTS 38 | 39 | ## SPI-based TEMPERATURE MONITOR 40 | 41 | This project will aim at design and immplemention of a SPI-based temperature monitor. The students will design a controller in Verilog to read the data from the sensor ([LM70][datasheetLM70]) using the industry-standard SPI protocol, convert the data to a human readable format (deg-C) and drive a set of 7-segment display to display the data. In order to test the Verilog code in realtime application, the Verilog code will be synthesized into a Xilinx's Spartan FPGA board. This will allow the students to test their Verilog code in real time. 42 | 43 | ![Temperature Monitor Block Diagram](docs/tempMonitor-blockDiag-v1-0322.png) 44 | 45 | **SOME USEFUL LINKS** 46 | 47 | - [An easy-to-read SPI tutorial from sparkfun](https://learn.sparkfun.com/tutorials/serial-peripheral-interface-spi) 48 | - [Datasheet: TI SPI-based temperature sensor LM70][datasheetLM70] 49 | - [Technical Reference: Xilinx Spartan-6 FPGA Development Board][TechRefSpartan6] 50 | 51 | :exclamation: **TASKS:** :exclamation: 52 | - :one: Convert the shift register code to a compact format like this `shift_reg <= shifte_reg<<1;` 53 | - :two: Latch the 8-bit output from the LM70 to `outreg[7:0]` at the end of read cycle and verify you the value is the same as set in the temperature sensor. 54 | - :three: Follow [chipverify.com](https://www.chipverify.com/verilog/verilog-tutorial) excercises till the __Behavioural modeling__ section. Now you can use iverilog to complete the assignments. 55 | 56 | 57 | ## I2C-based TEMPERATURE and HUMIDITY MONITOR 58 | 59 | This project will aim at design and immplemention of a temperature & humidity monitor. The students will design a controller in Verilog to read the data from the sensor ([DHT20](https://www.dropbox.com/s/h3shzfsain3r9li/datasheet-temp-humidity-5193-DHT20.pdf)), convert the data to a human readable format (deg-C and Rh-%) and drive a set of 7-segment display to display the data. In order to test the Verilog code in realtime application, the Verilog code will be synthesized into a Digilent [Arty A7 FPGA development board](https://digilentinc.com/start/ArtyA7). This will allow the students to test their Verilog code in real time. 60 | 61 | **SOME USEFUL LINKS** 62 | 63 | - [An easy-to-read I2C tutorial from sparkfun](https://learn.sparkfun.com/tutorials/i2c/) 64 | - [An detail IC implementation of a I2C controller](https://github.com/vsao/I2C) 65 | - [Datasheet: DHT20 Temperature & Humidity Sensor](https://www.dropbox.com/s/h3shzfsain3r9li/datasheet-temp-humidity-5193-DHT20.pdf) 66 | - [Arty A7 FGPA Development Board Resources](https://digilentinc.com/start/ArtyA7) 67 | 68 | ## A SIMPLE 8-bit MIPS MICROPROCESSOR 69 | 70 | For this project we will design and immplement a 8-bit subset of the MIPS microprocessor architecture as outlined in [**Weste**] Chapter 1.7 as an example case study. The major development steps for this project will be: 71 | - Study chapter 1.7, understand it **well** and prepare a short presentation summarizing the project. 72 | - Create a behavioural model in Verilog of the whole microprocessor and test it with a machine code of a simple program. 73 | - Create structural models of each sub-system of the processor using Verilog structural flow using a basic set digital gates. 74 | - Verify each subsystem and the entire processor using the structural models. 75 | - Design, layout and characterize each of the digital gates used in the processor using SKY130 technology. 76 | - Back annotate the chracterized delays into the Verilog models and do timing checks and find the highest frequency of operation. 77 | 78 | 79 | # ELECTRONIC DESIGN AUTOMATION SOFTWARE 80 | 81 | ## INSTALLING ICARUS VERILOG with GTKWAVE 82 | 83 | In this section we will demonstrate on how to install the open-source Verilog simulator **Icarus Verilog** (`iverilog`) and view the result using an open-source viewer **GTKWave**. 84 | 85 | **SOME USEFUL LINKS**: 86 | - [iVerilog creator Steve Icarus's document page](https://steveicarus.github.io/iverilog) 87 | 88 | 89 | The following instructions are for `iverilog` and `gtkwave` from a standard **Ubuntu 18.04** repository: 90 | 91 | - `sudo apt update && sudo apt upgrade -y` : To update your distribution. 92 | - `sudo apt install iverilog` 93 | - `sudo apt install gtkwave` 94 | - Now let's compile a simple verilog module and it's testbench: `mydut.v` and `tb_mydut.v`. An example contnet of the Verilog code is given below. 95 | - Create project directory say `mkdir -p ~/iverilog/test` and `cd` to that directory. 96 | - `iverilog -o tb_mydut.vvp mydut.v tb_mydut.v` : Compile the verilog codes and create an output `tb_mydut.vvp` 97 | - `vvp tb_mydut.vvp` : Convert the compiled output to a VCD format for GTKWave. 98 | - `gtkwave dump.vcd` : Note: the filename `dump.vcd` is assumed to be in `tb_mydut.v` 99 | 100 | - If you want to execute the first two commands as script, you can add the first two commands to a file called say `run`: 101 | 102 | ```bash 103 | iverilog -o tb_mydut.vvp mydut.v tb_mydut.v 104 | vvp tb_mydut.vvp 105 | ``` 106 | 107 | - Now mamke the file executable by typing the follwoing command: `chmod +x run` 108 | - And from now on, you can simply execute the script by typing `./run` 109 | 110 | - Example content of `mydut.v`: 111 | 112 | ```verilog 113 | // Simple DUT with NAND expression 114 | module mydut ( input A, input B, output Y); 115 | assign Y = ~(A & B); 116 | endmodule 117 | ``` 118 | 119 | - Example content of `tb_mydut.v` : 120 | 121 | ```verilog 122 | module tb_mydut; 123 | reg A; 124 | reg B; 125 | wire Y, Z; 126 | 127 | mydut dut0 (.A(A), .B(B), .Y(Y)); 128 | 129 | initial begin 130 | // Dump waves 131 | $dumpfile("dump.vcd"); 132 | $dumpvars(1); 133 | 134 | A <= 0; 135 | B <= 0; 136 | #2 137 | A <= 0; 138 | B <= 1'bx; 139 | #2 140 | A <= 1; 141 | B <= 1'bz; 142 | #2 143 | A <= 1; 144 | B <= 1'bx; 145 | 146 | #2 $finish; 147 | end 148 | endmodule 149 | ``` 150 | 151 | * * * 152 | 153 | [datasheetLM70]: https://www.dropbox.com/s/ot6h1511lpuxlmx/datasheet-LM70-TI-tempSensor.pdf 154 | [datasheetDHT20]: https://www.dropbox.com/s/9vpyqqnqopvtvbh/datasheet-temp-humidity-5193-DHT20.pdf 155 | [TechRefSpartan6]: https://www.dropbox.com/s/s53w0m665e083ni/AHMY_SP6LX9_LT_Spartan6-TechRef.pdf 156 | -------------------------------------------------------------------------------- /docs/AHMY_SP6LX9_LT_Spartan6-TechRef.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silicon-vlsi/VLSI-2024/84419f20b2deb4f61177fd438be693b4af02b235/docs/AHMY_SP6LX9_LT_Spartan6-TechRef.pdf -------------------------------------------------------------------------------- /docs/datasheet-LM70-TI-tempSensor.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silicon-vlsi/VLSI-2024/84419f20b2deb4f61177fd438be693b4af02b235/docs/datasheet-LM70-TI-tempSensor.pdf -------------------------------------------------------------------------------- /docs/datasheet-temp-humidity-5193-DHT20.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silicon-vlsi/VLSI-2024/84419f20b2deb4f61177fd438be693b4af02b235/docs/datasheet-temp-humidity-5193-DHT20.pdf -------------------------------------------------------------------------------- /docs/tempMonitor-blockDiag-v1-0322.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silicon-vlsi/VLSI-2024/84419f20b2deb4f61177fd438be693b4af02b235/docs/tempMonitor-blockDiag-v1-0322.png -------------------------------------------------------------------------------- /verilog/TB-tsense-SPI.v: -------------------------------------------------------------------------------- 1 | // Code your testbench here 2 | // or browse Examples 3 | // 4 | `timescale 1ns/1ps 5 | 6 | 7 | module tsense_read_tb(); 8 | wire CS, SCK, SIO; 9 | reg RSTN, SYSCLK; 10 | wire [7:0] dbugout; 11 | wire [7:0] dataSeg; 12 | wire [1:0] disp; 13 | 14 | 15 | //Task for simple test 16 | task testRead; 17 | begin 18 | #15 RSTN = 1'b1; 19 | end 20 | endtask 21 | 22 | 23 | //Instiate LM07 24 | LM07 tsense(.CS(CS), .SCK(SCK), .SIO(SIO)); 25 | //Instiate DUT 26 | LM07_read dut(.SYSCLK(SYSCLK), .RSTN(RSTN), .CS(CS), .SCK(SCK), .SIO(SIO), .disp(disp), .dataSeg(dataSeg), .dbugout(dbugout) ); 27 | 28 | //Initialize CS 29 | initial RSTN = 1'b0; 30 | 31 | //Generate test clock 32 | initial SYSCLK= 1'b1; 33 | initial forever #10 SYSCLK = ~SYSCLK; 34 | 35 | //Testbench 36 | initial 37 | begin 38 | //$monitor("time= %0t;data[]=,CS=%b,CLK=%b,SIO=%b,",$time,CS,CLK,SIO); 39 | 40 | $dumpfile("dump.vcd"); 41 | $dumpvars(1); 42 | testRead; 43 | #1500 44 | $finish(2); 45 | end 46 | endmodule 47 | 48 | //Define 49 | `define TEMP_SET 16'h0F00 50 | 51 | // Verilog model for the SPI-based temperature 52 | // sensor LM07 or it's equivalent family. 53 | // 54 | module LM07(CS, SCK, SIO); 55 | output SIO; 56 | input SCK, CS; 57 | // 58 | // lm07_reg represents the register that stores 59 | // temperature value after A2D conversion 60 | // FIXME: Model the A2D 61 | reg [15:0] shift_reg; 62 | wire clk_gated; 63 | 64 | //Reset at startup 65 | initial begin 66 | shift_reg = `TEMP_SET; 67 | //shift_reg = shift_reg>>1; 68 | end 69 | 70 | //SIO bit of the LM07 is hardwired output of 71 | // the MSB of the shift register 72 | assign SIO = shift_reg[15]; 73 | 74 | //Gate the clock with CS 75 | assign clk_gated = ~CS & SCK; 76 | 77 | // When CS goes low, load temp_shift_reg with lm07_reg 78 | // If high, reset 79 | always @(CS) 80 | begin 81 | shift_reg = `TEMP_SET; 82 | //shift_reg = shift_reg>>1; 83 | end 84 | 85 | //Shift register to shift the loaded temp reg 86 | //every negedge of the gated clock 87 | always @(negedge clk_gated) 88 | begin 89 | shift_reg = shift_reg<<1; 90 | end 91 | endmodule 92 | -------------------------------------------------------------------------------- /verilog/cheatsheet.v: -------------------------------------------------------------------------------- 1 | //7-Segment select lines for MSB and LSB 2 | assign disp[1] = (spi_state == `DISP_WRITE_MSB); 3 | assign disp[0] = (spi_state == `DISP_WRITE_LSB); 4 | 5 | //2:1 MUX for sending MSB/LSB data to the 7-segment display 6 | assign bcd_data = (spi_state == `DISP_WRITE_MSB) ? bcd_msb : bcd_lsb ; 7 | 8 | //BCD to 7-segment decoder 9 | assign dataSeg[7] = (~bcd_data[2] && ~bcd_data[0]) || bcd_data[1] || bcd_data[0] || (bcd_data[2] && bcd_data[0]); //a 10 | assign dataSeg[6] = ~bcd_data[2] || (~bcd_data[1] && ~bcd_data[0]) || (bcd_data[1] && bcd_data[0]); //b 11 | assign dataSeg[5] = ~bcd_data[1] || bcd_data[0] || bcd_data[2]; //c 12 | assign dataSeg[4] = (~bcd_data[2] && ~bcd_data[0]) || (~bcd_data[2] && bcd_data[1]) || (bcd_data[2] && ~bcd_data[1] && bcd_data[0]) || (bcd_data[1] && ~bcd_data[0]) || bcd_data[3]; //d 13 | assign dataSeg[3] = (~bcd_data[2] && ~bcd_data[0]) || (bcd_data[1] && ~bcd_data[0]); //e 14 | assign dataSeg[2] = (~bcd_data[1] && ~bcd_data[0]) || (bcd_data[2] && ~bcd_data[1]) || (bcd_data[2] && ~bcd_data[0]) || bcd_data[3]; //f 15 | assign dataSeg[1] = (~bcd_data[2] && bcd_data[1]) || (bcd_data[2] && ~bcd_data[1]) || bcd_data[3] || (bcd_data[2] && ~bcd_data[0]); //g 16 | assign dataSeg[0] = 1'b0; //DP 17 | 18 | //Converting 7-bit binary to BCD value 19 | //BCD(MSB) = Temp./10 approx= Temp(1/16 + 1/32) 20 | //NOTE: First add then shift by 4 to avoid truncation error. 21 | assign bcd_msb = (temp_bin + (temp_bin>>1))>>4; 22 | 23 | //BCD(LSB) = temp - 10*MSB = temp - (8*MSB + 2*MSB) 24 | assign bcd_lsb = temp_bin - ((bcd_msb<<3) + (bcd_msb<<1)); 25 | 26 | -------------------------------------------------------------------------------- /verilog/run: -------------------------------------------------------------------------------- 1 | #!/bin/sh 2 | 3 | iverilog -o out.vvp TB-tsense-SPI.v tsense-SPI.v 4 | vvp out.vvp 5 | #gtkwave dump.vcd 6 | -------------------------------------------------------------------------------- /verilog/tsense-SPI.v: -------------------------------------------------------------------------------- 1 | //DEFINES 2 | `define RST_COUNT 5'd0 3 | `define CS_LOW_COUNT 5'd4 4 | `define CS_HIGH_COUNT 5'd20 5 | `define WRITE_LSB_COUNT 5'd22 6 | //`define WRITE_LSB_COUNT 5'd24 7 | `define MAX_COUNT 5'd28 8 | `define SPI_IDLE 2'b00 9 | `define SPI_READ 2'b01 10 | `define DISP_WRITE_MSB 2'b10 11 | `define DISP_WRITE_LSB 2'b11 12 | 13 | //Verilog code for continous SPI read of LM07 14 | // 15 | module LM07_read(SYSCLK, RSTN, CS, SCK, SIO, disp, dataSeg, dbugout); 16 | input SYSCLK; //System clock from the testbench 17 | input RSTN; //Active-low reset signal 18 | input SIO; //Serial data output from the temp sensor. 19 | output CS; //Generate the Chip select for temp sensor 20 | output reg SCK; //Generate the SPI clock for temp sensor 21 | output [1:0] disp; //7-segment display select lines. 22 | output [7:0] dataSeg; //7-segment data 23 | output [7:0] dbugout; //the 8-bit data is latched for display 24 | 25 | reg SYSCLK_HALF; 26 | reg [7:0] shift_reg; 27 | reg [1:0] spi_state; 28 | reg [4:0] count; 29 | wire sysclk_gated; 30 | wire [7:0] temp_bin; 31 | wire [3:0] bcd_msb; 32 | wire [3:0] bcd_lsb; 33 | wire [3:0] bcd_data; 34 | 35 | //This output register is for debug purpose. 36 | //assign dbugout[7:4] = bcd_msb; 37 | //assign dbugout[3:0] = bcd_data; 38 | 39 | //7-Segment select lines for MSB and LSB 40 | //FIXME 41 | 42 | //2:1 MUX for sending MSB/LSB data to the 7-segment display 43 | //FIXME 44 | 45 | //BCD to 7-segment decoder 46 | //FIXME 47 | 48 | //If you are reading 8-bits from the sensor, the LSB is 2-deg C 49 | //So multiply it by 2 to convert it to the right magnitude. 50 | assign temp_bin = shift_reg<<1; 51 | 52 | //Converting 7-bit binary to BCD value 53 | //BCD(MSB) = Temp./10 approx= Temp(1/16 + 1/32) 54 | //NOTE: First add then shift by 4 to avoid truncation error. 55 | //FIXME 56 | 57 | //BCD(LSB) = temp - 10*MSB = temp - (8*MSB + 2*MSB) 58 | //FIXME 59 | 60 | //shift register for the input (SIO) 61 | always @(posedge SCK or negedge RSTN) 62 | if (~RSTN) 63 | shift_reg <= 8'h00; 64 | else 65 | begin 66 | shift_reg <= shift_reg<<1; 67 | shift_reg[0] <= SIO; 68 | end 69 | 70 | //SPI CLOCK SCK generator 71 | always @(negedge SYSCLK or negedge RSTN) 72 | if (~RSTN || CS) 73 | SCK <= 1'b0; 74 | else 75 | SCK <= ~SCK; 76 | 77 | // Chip Select CS generator 78 | assign CS = ~(spi_state == `SPI_READ); 79 | 80 | // 4-state (IDLE, READ, MSB_WRITE, LSB_WRITE) state-machine 81 | always @(posedge SYSCLK or negedge RSTN) 82 | if (~RSTN) 83 | begin 84 | spi_state <= `SPI_IDLE; 85 | end 86 | else if ((count >= `CS_LOW_COUNT) && (count < `CS_HIGH_COUNT) ) 87 | begin 88 | spi_state <= `SPI_READ; 89 | end 90 | else if (count == `CS_HIGH_COUNT) 91 | begin 92 | spi_state <= `DISP_WRITE_MSB; 93 | end 94 | else if (count == `WRITE_LSB_COUNT) 95 | begin 96 | spi_state <= `DISP_WRITE_LSB; 97 | end 98 | else 99 | begin 100 | spi_state <= `SPI_IDLE; 101 | end 102 | 103 | //5-bit Counter 104 | always @(negedge SYSCLK or negedge RSTN) 105 | if (~RSTN) 106 | count <= `RST_COUNT; 107 | else if (count == `MAX_COUNT) 108 | count <= `RST_COUNT; 109 | else 110 | count <= count + 1'b1; 111 | 112 | endmodule 113 | --------------------------------------------------------------------------------