├── .gitignore ├── README.md └── data ├── README.txt ├── buildLanguage.xml ├── languages ├── m16c.cspec ├── m16c.ldefs ├── m16c.opinion ├── m16c.pspec ├── m16c.sinc ├── m16c.slaspec ├── sfrs.txt ├── test.sla └── test.slaspec └── sleighArgs.txt /.gitignore: -------------------------------------------------------------------------------- 1 | # Eclipse Ghidra Build Files 2 | .antProperties.xml 3 | .classpath 4 | .project 5 | .settings/ 6 | Module.manifest 7 | bin/ 8 | build.gradle 9 | extension.properties 10 | ghidra_scripts/ 11 | lib/ 12 | os/ 13 | src/ 14 | 15 | # Vim tags file 16 | tags 17 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Ghidra Processor Module for Renesas M16C Architecture 2 | 3 | ## Build Instructions 4 | 5 | Install Eclipse, set up a development environment following [this guide](https://github.com/NationalSecurityAgency/ghidra/blob/master/DevGuide.md). 6 | 7 | Add GhidraDev Plugin to Eclipse and create a new Ghidra Processor Module following [this other guide](https://spinsel.dev/2020/06/17/ghidra-brainfuck-processor-1.html). 8 | 9 | Clone this repo into the newly created module path. 10 | 11 | Build and run! 12 | -------------------------------------------------------------------------------- /data/README.txt: -------------------------------------------------------------------------------- 1 | The "data" directory is intended to hold data files that will be used by this module and will 2 | not end up in the .jar file, but will be present in the zip or tar file. Typically, data 3 | files are placed here rather than in the resources directory if the user may need to edit them. 4 | 5 | An optional data/languages directory can exist for the purpose of containing various Sleigh language 6 | specification files and importer opinion files. 7 | 8 | The data/buildLanguage.xml is used for building the contents of the data/languages directory. 9 | 10 | The skel language definition has been commented-out within the skel.ldefs file so that the 11 | skeleton language does not show-up within Ghidra. 12 | 13 | See the Sleigh language documentation (docs/languages/index.html) for details Sleigh language 14 | specification syntax. 15 | -------------------------------------------------------------------------------- /data/buildLanguage.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | -------------------------------------------------------------------------------- /data/languages/m16c.cspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | -------------------------------------------------------------------------------- /data/languages/m16c.ldefs: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 14 | Renesas M16C 15 | 16 | 17 | 18 | -------------------------------------------------------------------------------- /data/languages/m16c.opinion: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 12 | 13 | -------------------------------------------------------------------------------- /data/languages/m16c.pspec: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | -------------------------------------------------------------------------------- /data/languages/m16c.sinc: -------------------------------------------------------------------------------- 1 | # sleigh include file for Skeleton language instructions 2 | 3 | -------------------------------------------------------------------------------- /data/languages/m16c.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | define alignment=1; 4 | 5 | define space ram type=ram_space size=4 default; 6 | define space near type=ram_space size=2; 7 | define space register type=register_space size=2; 8 | 9 | define register offset=0x01 size=3 [ INTB]; 10 | define register offset=0x00 size=2 [ INTBH INTBL]; 11 | define register offset=0x30 size=4 [ PC]; 12 | 13 | 14 | define register offset=0x50 size=2 [ R0 R2 R1 R3 A0 A1 USP ISP SB FLAG SP FB]; 15 | define register offset=0x50 size=4 [ R2R0 R3R1 A1A0]; 16 | define register offset=0x50 size=1 [ R0L R0H _ _ R1L R1H _ _ _ _ _ _ ]; 17 | 18 | define register offset=0x100 size=1 [Cflg Dflg Zflg Sflg Bflg Oflg Iflg Uflg IPLflg]; 19 | define register offset=0x120 size=4 [ contextreg ]; 20 | 21 | define token operand_g (16) 22 | size0 = ( 0, 0) 23 | op1_7 = ( 1, 7) 24 | op0_7 = ( 0, 7) 25 | dest8_11 = ( 8,11) 26 | dest8_11b = ( 8,11) 27 | op8_11 = ( 8,11) 28 | imm8_11 = ( 8,11) 29 | shl_imm8_11 = ( 8,11) 30 | cnd8_11 = ( 8,11) 31 | op12_15 = (12,15) 32 | src12_15 = (12,15) 33 | src12_15b = (12,15) 34 | imm12_15 = (12,15) 35 | sha_imm12_15 = (12,15) 36 | op0_15 = ( 0,15) 37 | op8_15 = ( 8,15) 38 | flg12_14 = (12,14) 39 | ldc12_14 = (12,14) 40 | imm8_10 = ( 8,10) 41 | dest12_14 = (12,14) 42 | src32_8_11 = ( 8,11) 43 | mul8_11 = ( 8,11) 44 | mul8b8_11 = ( 8,11) 45 | srcb12_13 = (12,13) 46 | srcw12_13 = (12,13) 47 | dir = (12,13) 48 | bit8 = (8,8) 49 | bit9 = (9,9) 50 | bit10 = (10,10) 51 | bit11 = (11,11) 52 | bit12 = (12,12) 53 | bit13 = (13,13) 54 | bit14 = (14,14) 55 | bit15 = (15,15) 56 | ; 57 | 58 | define token operand_s (8) 59 | op = (3,7) 60 | op4_7 = (4,7) 61 | dest0_2 = (0,2) 62 | dest2_2 = (2,2) 63 | dest2_a0_a1 = (2,2) 64 | src2 = (0,1) 65 | bit0_2 = (0,2) 66 | ops0_7 = (0,7) 67 | dest_a0_a1 = (3,3) 68 | dest3_r0l_r0h = (3,3) 69 | cnd0_2 = (0,2) 70 | dsp0_2 = (0,2) 71 | dest0_1 = (0,1) 72 | ; 73 | 74 | define token data8 (8) 75 | dsp8 = (0,7) signed 76 | imm8 = (0,7) 77 | cnd8 = (0,7) 78 | interrupt = (0,5) 79 | data8_bit6 = (6,6) 80 | data8_bit7 = (7,7) 81 | ; 82 | 83 | define token dest_data8 (8) 84 | dest_dsp8 = (0,7) signed 85 | dest_imm8 = (0,7) 86 | dest_cnd8 = (0,7) 87 | ; 88 | 89 | define token data16 (16) 90 | dsp16 = (0,15) signed 91 | abs16 = (0,15) 92 | imm16 = (0,15) 93 | ; 94 | 95 | define token dest_data16 (16) 96 | dest_dsp16 = (0,15) signed 97 | dest_abs16 = (0,15) 98 | dest_imm16 = (0,15) 99 | ; 100 | 101 | define token data32 (24) 102 | abs20 = (0,19) 103 | dsp20 = (0,19) 104 | ; 105 | 106 | define token operand_s_imm8 (16) 107 | op3_7_imm8 = (3, 7) 108 | dest0_2_imm8 = (0, 2) 109 | imm8_15 = (8,15) 110 | ; 111 | 112 | define context contextreg 113 | guard = (0, 0) 114 | destmode = (1, 4) 115 | srcmode = (5, 8) 116 | addrmode = (9,12) ; 117 | 118 | define pcodeop segment; 119 | 120 | 121 | attach variables [dest8_11 src12_15] [R0 R1 R2 R3 A0 A1 A0 A1 A0 A1 SB _ A0 A1 SB _ ]; 122 | attach variables [mul8_11] [R2R0 R3R1 _ _ A1A0 _ _ _ _ _ _ _ _ _ _ _]; 123 | attach variables [mul8b8_11] [R0L R0H R1L R1H _ _ _ _ _ _ _ _ _ _ _ _]; 124 | attach variables [dest2_2] [R0L R0H]; 125 | attach variables [dest3_r0l_r0h] [R0L R0H]; 126 | attach variables [dest2_a0_a1 dest_a0_a1] [A0 A1]; 127 | #attach variables [dest_a0_a1] [A0 A1]; 128 | attach variables [flg12_14] [Cflg Dflg Zflg Sflg Bflg Oflg Iflg Uflg]; 129 | attach variables [dest12_14] [R0 R1 R2 R3 A0 A1 _ _]; 130 | 131 | attach values [imm8_11 imm12_15] [0 1 2 3 4 5 6 7 -8 -7 -6 -5 -4 -3 -2 -1]; 132 | attach values [shl_imm8_11 sha_imm12_15] [1 2 3 4 5 6 7 8 -1 -2 -3 -4 -5 -6 -7 -8]; 133 | 134 | attach variables [src32_8_11] [R2R0 R3R1 _ _ A1A0 _ _ _ _ _ _ _ _ _ _ _]; 135 | 136 | 137 | attach variables [ldc12_14] [_ INTBL INTBH FLAG ISP USP SB _]; 138 | 139 | attach variables [srcb12_13] [R0L R0H R1L R1H]; 140 | attach variables [srcw12_13] [R0 R1 R2 R3]; 141 | 142 | d_addr: dsp8[A0] is A0 & destmode=8; dsp8 { local temp:2 = A0 + dsp8; export temp; } 143 | d_addr: dsp8[A1] is A1 & destmode=9; dsp8 { local temp:2 = A1 + dsp8; export temp; } 144 | d_addr: dsp8[SB] is SB & destmode=10; dsp8 { local temp:2 = SB + dsp8; export temp; } 145 | d_addr: dsp8[FB] is FB & destmode=11; dsp8 { local temp:2 = FB + sext(dsp8:1); export temp; } 146 | d_addr: dsp16[A0] is A0 & destmode=12; dsp16 { local temp:2 = A0 + dsp16; export temp; } 147 | d_addr: dsp16[A1] is A1 & destmode=13; dsp16 { local temp:2 = A1 + dsp16; export temp; } 148 | d_addr: dsp16[SB] is SB & destmode=14; dsp16 { local temp:2 = SB + dsp16; export temp; } 149 | d_addr: abs16 is destmode=15; abs16 { local temp:2 = abs16; export temp; } 150 | 151 | s_addr: dsp8[A0] is A0 & srcmode=8; dsp8 { local temp:2 = A0 + dsp8; export temp; } 152 | s_addr: dsp8[A1] is A1 & srcmode=9; dsp8 { local temp:2 = A1 + dsp8; export temp; } 153 | s_addr: dsp8[SB] is SB & srcmode=10; dsp8 { local temp:2 = SB + dsp8; export temp; } 154 | s_addr: dsp8[FB] is FB & srcmode=11; dsp8 { local temp:2 = FB + sext(dsp8:1); export temp; } 155 | s_addr: dsp16[A0] is A0 & srcmode=12; dsp16 { local temp:2 = A0 + dsp16; export temp; } 156 | s_addr: dsp16[A1] is A1 & srcmode=13; dsp16 { local temp:2 = A1 + dsp16; export temp; } 157 | s_addr: dsp16[SB] is SB & srcmode=14; dsp16 { local temp:2 = SB + dsp16; export temp; } 158 | s_addr: abs16 is srcmode=15; abs16 { local temp:2 = abs16; export temp; } 159 | 160 | #d_eal1: R2R0 is R2R0 & destmode=0 { export R2R0; } 161 | #d_eal1: R3R1 is R3R1 & destmode=1 { export R3R1; } 162 | #d_eal1: A1A0 is A1A0 & destmode=4 { export A1A0; } 163 | #d_eal1: [A0] is A0 & destmode=6 { export *:4 A0; } 164 | #d_eal1: [A1] is A1 & destmode=7 { export *:4 A1; } 165 | #d_eal1: d_addr is d_addr { local temp = d_addr; export *:4 temp; } 166 | d_eaw1: R0 is R0 & destmode=0 { export R0; } 167 | d_eaw1: R1 is R1 & destmode=1 { export R1; } 168 | d_eaw1: R2 is R2 & destmode=2 { export R2; } 169 | d_eaw1: R3 is R3 & destmode=3 { export R3; } 170 | d_eaw1: A0 is A0 & destmode=4 { export A0; } 171 | d_eaw1: A1 is A1 & destmode=5 { export A1; } 172 | d_eaw1: [A0] is A0 & destmode=6 { export *[near]:2 A0; } 173 | d_eaw1: [A1] is A1 & destmode=7 { export *[near]:2 A1; } 174 | d_eaw1: d_addr is d_addr { local temp = d_addr; export *[near]:2 temp; } 175 | 176 | d_eab1: R0L is destmode=0 & R0L { export R0L; } 177 | d_eab1: R0H is destmode=1 & R0H { export R0H; } 178 | d_eab1: R1L is destmode=2 & R1L { export R1L; } 179 | d_eab1: R1H is destmode=3 & R1H { export R1H; } 180 | d_eab1: A0 is A0 & destmode=4 { local temp = (A0:1); export temp; } 181 | d_eab1: A1 is A1 & destmode=5 { local temp = (A1:1); export temp; } 182 | d_eab1: [A0] is A0 & destmode=6 { local temp = A0; export *[near]:1 temp; } 183 | d_eab1: [A1] is A1 & destmode=7 { local temp = A1; export *[near]:1 temp; } 184 | d_eab1: d_addr is d_addr { local temp = d_addr; export *[near]:1 temp; } 185 | 186 | s_eaw1: R0 is R0 & srcmode=0 { export R0; } 187 | s_eaw1: R1 is R1 & srcmode=1 { export R1; } 188 | s_eaw1: R2 is R2 & srcmode=2 { export R2; } 189 | s_eaw1: R3 is R3 & srcmode=3 { export R3; } 190 | s_eaw1: A0 is A0 & srcmode=4 { export A0; } 191 | s_eaw1: A1 is A1 & srcmode=5 { export A1; } 192 | s_eaw1: [A0] is A0 & srcmode=6 { export *[near]:2 A0; } 193 | s_eaw1: [A1] is A1 & srcmode=7 { export *[near]:2 A1; } 194 | s_eaw1: s_addr is s_addr { local temp = s_addr; export *[near]:2 temp; } 195 | 196 | s_eab1: R0L is srcmode=0 & R0L { export R0L; } 197 | s_eab1: R0H is srcmode=1 & R0H { export R0H; } 198 | s_eab1: R1L is srcmode=2 & R1L { export R1L; } 199 | s_eab1: R1H is srcmode=3 & R1H { export R1H; } 200 | s_eab1: A0 is A0 & srcmode=4 { local temp = (A0:1); export temp; } 201 | s_eab1: A1 is A1 & srcmode=5 { local temp = (A1:1); export temp; } 202 | s_eab1: [A0] is A0 & srcmode=6 { local temp = A0; export *[near]:1 temp; } 203 | s_eab1: [A1] is A1 & srcmode=7 { local temp = A1; export *[near]:1 temp; } 204 | s_eab1: s_addr is s_addr { local temp = s_addr; export *[near]:1 temp; } 205 | 206 | d_eaw: R0 is R0 & dest8_11=0 { export R0; } 207 | d_eaw: R1 is R1 & dest8_11=1 { export R1; } 208 | d_eaw: R2 is R2 & dest8_11=2 { export R2; } 209 | d_eaw: R3 is R3 & dest8_11=3 { export R3; } 210 | d_eaw: A0 is A0 & dest8_11=4 { export A0; } 211 | d_eaw: A1 is A1 & dest8_11=5 { export A1; } 212 | d_eaw: [A0] is A0 & dest8_11=6 { export *[near]:2 A0; } 213 | d_eaw: [A1] is A1 & dest8_11=7 { export *[near]:2 A1; } 214 | d_eaw: dsp8[A0] is A0 & dest8_11=8; dsp8 { local temp:2 = A0 + dsp8; export *[near]:2 temp; } 215 | d_eaw: dsp8[A1] is A1 & dest8_11=9; dsp8 { local temp:2 = A1 + dsp8; export *[near]:2 temp; } 216 | d_eaw: dsp8[SB] is SB & dest8_11=10; dsp8 { local temp:2 = SB + dsp8; export *[near]:2 temp; } 217 | d_eaw: dsp8[FB] is FB & dest8_11=11 ; dsp8 { local temp:2 = FB+sext(dsp8:1); export *[near]:2 temp; } 218 | d_eaw: dsp16[A0] is A0 & dest8_11=12; dsp16 { local temp:2 = A0 + dsp16; export *[near]:2 temp; } 219 | d_eaw: dsp16[A1] is A1 & dest8_11=13; dsp16 { local temp:2 = A1 + dsp16; export *[near]:2 temp; } 220 | d_eaw: dsp16[SB] is SB & dest8_11=14; dsp16 { local temp:2 = SB + dsp16; export *[near]:2 temp; } 221 | d_eaw: abs16 is dest8_11=15; abs16 { export *[near]:2 abs16; } 222 | 223 | 224 | d_eab: R0L is dest8_11=0 & R0L { export R0L; } 225 | d_eab: R0H is dest8_11=1 & R0H { export R0H; } 226 | d_eab: R1L is dest8_11=2 & R1L { export R1L; } 227 | d_eab: R1H is dest8_11=3 & R1H { export R1H; } 228 | d_eab: dest8_11 is dest8_11 & dest8_11=4 { local temp = (dest8_11:1); export temp; } 229 | d_eab: dest8_11 is dest8_11 & dest8_11=5 { local temp = (dest8_11:1); export temp; } 230 | d_eab: dest8_11 is dest8_11 & dest8_11=6 { export *[near]:1 dest8_11; } 231 | d_eab: dest8_11 is dest8_11 & dest8_11=7 { export *[near]:1 dest8_11; } 232 | d_eab: dest_dsp8[dest8_11] is dest8_11 & dest8_11=8; dest_dsp8 { local temp:2 = dest8_11 + dest_dsp8; export *[near]:1 temp; } 233 | d_eab: dest_dsp8[dest8_11] is dest8_11 & dest8_11=9; dest_dsp8 { local temp:2 = dest8_11 + dest_dsp8; export *[near]:1 temp; } 234 | d_eab: dest_dsp8[dest8_11] is dest8_11 & dest8_11=10; dest_dsp8 { local temp:2 = dest8_11 + dest_dsp8; export *[near]:1 temp; } 235 | d_eab: dest_dsp8[FB] is FB & dest8_11=11; dest_dsp8 { local temp:2 = FB+sext(dest_dsp8:1); export *[near]:1 temp; } 236 | d_eab: dest_dsp16[dest8_11] is dest8_11 & dest8_11=12; dest_dsp16 { local temp:2 = dest8_11 + dest_dsp16; export *[near]:1 temp; } 237 | d_eab: dest_dsp16[dest8_11] is dest8_11 & dest8_11=13; dest_dsp16 { local temp:2 = dest8_11 + dest_dsp16; export *[near]:1 temp; } 238 | d_eab: dest_dsp16[SB] is SB & dest8_11=14; dest_dsp16 { local temp:2 = SB + dest_dsp16; export *[near]:1 temp; } 239 | d_eab: dest_abs16 is dest8_11=15; dest_abs16 { local temp:2 = dest_abs16; export *[near]:1 temp; } 240 | 241 | s_eab: R0L is src12_15=0 & R0L { export R0L; } 242 | s_eab: R0H is src12_15=1 & R0H { export R0H; } 243 | s_eab: R1L is src12_15=2 & R1L { export R1L; } 244 | s_eab: R1H is src12_15=3 & R1H { export R1H; } 245 | s_eab: src12_15 is src12_15 & src12_15=4 { local temp = src12_15:1; export temp; } 246 | s_eab: src12_15 is src12_15 & src12_15=5 { local temp = src12_15:1; export temp; } 247 | s_eab: src12_15 is src12_15 & src12_15=6 { local temp = src12_15; export *[near]:1 temp; } 248 | s_eab: src12_15 is src12_15 & src12_15=7 { local temp = src12_15; export *[near]:1 temp; } 249 | s_eab: dsp8[src12_15] is src12_15 & src12_15=8; dsp8 { local temp = (src12_15 + dsp8); export *[near]:1 temp; } 250 | s_eab: dsp8[src12_15] is src12_15 & src12_15=9; dsp8 { local temp = (src12_15 + dsp8); export *[near]:1 temp; } 251 | s_eab: dsp8[src12_15] is src12_15 & src12_15=10; dsp8 { local temp = (src12_15 + dsp8); export *[near]:1 temp; } 252 | s_eab: dsp8[FB] is FB & src12_15=11; dsp8 { local temp = FB + sext(dsp8:1); export *[near]:1 temp; } 253 | s_eab: dsp16[src12_15] is src12_15 & src12_15=12; dsp16 { local temp = (src12_15 + dsp16); export *[near]:1 temp; } 254 | s_eab: dsp16[src12_15] is src12_15 & src12_15=13; dsp16 { local temp = (src12_15 + dsp16); export *[near]:1 temp; } 255 | s_eab: dsp16[src12_15] is src12_15 & src12_15=14; dsp16 { local temp = (src12_15 + dsp16); export *[near]:1 temp; } 256 | s_eab: abs16 is src12_15=15; abs16 { local temp = (abs16:2); export *[near]:1 temp; } 257 | 258 | SRC2: R0L is src2=0x00 & dest2_2=1 & R0L { export R0L; } 259 | SRC2: R0H is src2=0x00 & dest2_2=0 & R0H { export R0H; } 260 | SRC2: dsp8[SB] is src2=1 & SB; dsp8 { local temp = (SB + dsp8); export *[near]:1 temp; } 261 | SRC2: dsp8[FB] is src2=2 & FB; dsp8 { local temp = FB + sext(dsp8:1); export *[near]:1 temp; } 262 | SRC2: abs16 is src2=3; abs16 { export *[near]:1 abs16; } 263 | 264 | d_d_eab: R0H is R0H & dest0_2=3 { export R0H; } 265 | d_d_eab: R0L is R0L & dest0_2=4 { export R0L; } 266 | d_d_eab: dsp8[SB] is SB & dest0_2=5;dsp8 { local temp = (SB +dsp8); export *[near]:1 temp; } 267 | d_d_eab: dsp8[FB] is FB & dest0_2=6;dsp8 { local temp = FB + sext(dsp8:1); export *[near]:1 temp; } 268 | d_d_eab: abs16 is dest0_2=7;abs16 { export *[near]:1 abs16; } 269 | 270 | d_imm: R0H is R0H & dest0_2_imm8=3 { export R0H; } 271 | d_imm: R0L is R0L & dest0_2_imm8=4 { export R0L; } 272 | d_imm: dsp8[SB] is SB & dest0_2_imm8=5;dsp8 { local temp = (SB +dsp8); export *[near]:1 temp; } 273 | d_imm: dsp8[FB] is FB & dest0_2_imm8=6;dsp8 { local temp = FB + sext(dsp8:1); export *[near]:1 temp; } 274 | d_imm: abs16 is dest0_2_imm8=7;abs16 { export *[near]:1 abs16; } 275 | 276 | j_n_eaw: [A0] is A0 & dest8_11=6 { local temp:2 = A0; export temp; } 277 | j_n_eaw: [A1] is A1 & dest8_11=7 { local temp:2 = A1; export temp; } 278 | j_n_eaw: dsp8[A0] is A0 & dest8_11=8; dsp8 { local temp:2 = A0 + dsp8; export temp; } 279 | j_n_eaw: dsp8[A1] is A1 & dest8_11=9; dsp8 { local temp:2 = A1 + dsp8; export temp; } 280 | j_n_eaw: dsp8[SB] is SB & dest8_11=10; dsp8 { local temp:2 = SB + dsp8; export temp; } 281 | j_n_eaw: dsp8[FB] is FB & dest8_11=11 ; dsp8 { local temp:2 = FB+sext(dsp8:1); export temp; } 282 | j_n_eaw: dsp16[A0] is A0 & dest8_11=12; dsp16 { local temp:2 = A0 + dsp16; export temp; } 283 | j_n_eaw: dsp16[A1] is A1 & dest8_11=13; dsp16 { local temp:2 = A1 + dsp16; export temp; } 284 | j_n_eaw: dsp16[SB] is SB & dest8_11=14; dsp16 { local temp:2 = SB + dsp16; export temp; } 285 | j_n_eaw: abs16 is dest8_11=15; abs16 { local temp:2 = abs16; export temp; } 286 | 287 | j_eaw: [A0] is A0 & dest8_11=6 { local temp:4 = zext(A0); export *:2 temp; } 288 | j_eaw: [A1] is A1 & dest8_11=7 { local temp:4 = zext(A1); export *:2 temp; } 289 | j_eaw: dsp8[A0] is A0 & dest8_11=8; dsp8 { local temp:4 = zext(A0 + dsp8); export *:2 temp; } 290 | j_eaw: dsp8[A1] is A1 & dest8_11=9; dsp8 { local temp:4 = zext(A1 + dsp8); export *:2 temp; } 291 | j_eaw: dsp8[SB] is SB & dest8_11=10; dsp8 { local temp:4 = zext(SB + dsp8); export *:2 temp; } 292 | j_eaw: dsp8[FB] is FB & dest8_11=11 ; dsp8 { local temp:4 = zext(FB+sext(dsp8:1)); export *:2 temp; } 293 | j_eaw: dsp20[A0] is A0 & dest8_11=12; dsp20 { local temp:4 = zext(zext(A0) + dsp20:3); export *:2 temp; } 294 | j_eaw: dsp20[A1] is A1 & dest8_11=13; dsp20 { local temp:4 = zext(zext(A1) + dsp20:3); export *:2 temp; } 295 | j_eaw: dsp16[SB] is SB & dest8_11=14; dsp16 { local temp:4 = zext(SB + dsp16:2); export *:2 temp; } 296 | j_eaw: abs16 is dest8_11=15; abs16 { local temp:4 = zext(abs16:2); export *:2 temp; } 297 | 298 | COND8: "GEU/C" is cnd8=0x00 { local tmp:1 = Cflg; export tmp; } 299 | COND8: "GTU" is cnd8=0x01 { local tmp:1 = (Cflg && !Zflg); export tmp; } 300 | COND8: "EQ/Z" is cnd8=0x02 { local tmp:1 = Zflg == 1; export tmp; } 301 | COND8: "N" is cnd8=0x03 { local tmp:1 = Sflg; export tmp; } 302 | COND8: "LE" is cnd8=0x04 { local tmp:1 = Zflg || (Oflg != Sflg); export tmp; } 303 | COND8: "O" is cnd8=0x05 { local tmp:1 = Oflg; export tmp; } 304 | COND8: "GE" is cnd8=0x06 { local tmp:1 = (Oflg == Sflg); export tmp; } 305 | COND8: "LTU/NC" is cnd8=0xf8 { local tmp:1 = !Cflg; export tmp; } 306 | COND8: "LEU" is cnd8=0xf9 { local tmp:1 = (!Cflg || Zflg); export tmp; } 307 | COND8: "NE/NZ" is cnd8=0xfa { local tmp:1 = Zflg == 0; export tmp; } 308 | COND8: "PZ" is cnd8=0xfb { local tmp:1 = !Sflg; export tmp; } 309 | COND8: "GT" is cnd8=0xfc { local tmp:1 = !Zflg && (Oflg == Sflg); export tmp; } 310 | COND8: "NO" is cnd8=0xfd { local tmp:1 = !Oflg; export tmp; } 311 | COND8: "LT" is cnd8=0xfe { local tmp:1 = (Oflg != Sflg); export tmp; } 312 | 313 | #COND4: "GEU/C" is cnd8_11=0x00 { local tmp:1 = Cflg; export tmp; } 314 | #COND4: "GTU" is cnd8_11=0x01 { local tmp:1 = Cflg==!Zflg; export tmp; } 315 | #COND4: "EQ/Z" is cnd8_11=0x02 { local tmp:1 = Zflg; export tmp; } 316 | #COND4: "N" is cnd8_11=0x03 { local tmp:1 = Sflg; export tmp; } 317 | #COND4: "LTU/NC" is cnd8_11=0x04 { local tmp:1 = !Cflg; export tmp; } 318 | #COND4: "LEU" is cnd8_11=0x05 { local tmp:1 = !(Cflg==!Zflg); export tmp; } 319 | #COND4: "NE/NZ" is cnd8_11=0x06 { local tmp:1 = !Zflg; export tmp; } 320 | #COND4: "PZ" is cnd8_11=0x07 { local tmp:1 = !Sflg; export tmp; } 321 | COND4: "LE" is cnd8_11=0x08 { local tmp:1 = Zflg || (Oflg != Sflg); export tmp; } 322 | COND4: "O" is cnd8_11=0x09 { local tmp:1 = Oflg; export tmp; } 323 | COND4: "GE" is cnd8_11=0x0A { local tmp:1 = (Oflg == Sflg); export tmp; } 324 | COND4: "GT" is cnd8_11=0x0C { local tmp:1 = !Zflg && (Oflg == Sflg); export tmp; } 325 | COND4: "NO" is cnd8_11=0x0D { local tmp:1 = !Oflg; export tmp; } 326 | COND4: "LT" is cnd8_11=0x0E { local tmp:1 = (Oflg != Sflg); export tmp; } 327 | 328 | COND3: "GEU/C" is cnd0_2=0x00 { local tmp:1 = Cflg; export tmp; } 329 | COND3: "GTU" is cnd0_2=0x01 { local tmp:1 = (Cflg && !Zflg); export tmp; } 330 | COND3: "EQ/Z" is cnd0_2=0x02 { local tmp:1 = Zflg; export tmp; } 331 | COND3: "N" is cnd0_2=0x03 { local tmp:1 = Sflg; export tmp; } 332 | COND3: "LTU/NC" is cnd0_2=0x04 { local tmp:1 = !Cflg; export tmp; } 333 | COND3: "LEU" is cnd0_2=0x05 { local tmp:1 = (!Cflg || Zflg); export tmp; } 334 | COND3: "NE/NZ" is cnd0_2=0x06 { local tmp:1 = !Zflg; export tmp; } 335 | COND3: "PZ" is cnd0_2=0x07 { local tmp:1 = !Sflg; export tmp; } 336 | 337 | macro macro_adc8(src, dest) { 338 | local tmp = dest + src + Cflg; 339 | Cflg = (tmp > 255); 340 | Zflg = (tmp == 0); 341 | Sflg = (tmp s< 0); 342 | Oflg = (tmp s< -128) | (tmp s> 127); 343 | dest = tmp; 344 | } 345 | 346 | macro macro_adc16(src, dest) { 347 | local c:2 = zext(Cflg); 348 | Cflg = carry(dest, src) || carry(src+dest, c); 349 | Oflg = scarry(dest, src) || scarry(src+dest, c); 350 | dest = src+dest+c; 351 | Zflg = (dest == 0); 352 | Sflg = (dest s< 0); 353 | } 354 | 355 | macro macro_add(src, dest) { 356 | Cflg = carry(dest, src); 357 | Oflg = scarry(dest, src); 358 | dest = dest+src; 359 | Zflg = (dest == 0); 360 | Sflg = (dest s< 0); 361 | } 362 | 363 | macro macro_and (src, dest) { 364 | dest = dest & src; 365 | Sflg = (dest s< 0); 366 | Zflg = (dest == 0); 367 | } 368 | 369 | macro macro_bm(cond, bit, dest) { 370 | if (cond == 1) goto ; 371 | dest = dest & ~(1 << zext(bit)); 372 | goto ; 373 | 374 | dest = dest | (1 << zext(bit)); 375 | 376 | } 377 | 378 | macro macro_cmp(src, dest) { 379 | local tmp = dest - src; 380 | Cflg = (dest >= src); 381 | Zflg = (dest == src); 382 | Sflg = (tmp s< 0); 383 | Oflg = sborrow(dest, src); 384 | } 385 | 386 | macro macro_mov(src, dest) { 387 | dest = src; 388 | Sflg = (dest s< 0); 389 | Zflg = (dest == 0); 390 | } 391 | 392 | macro macro_not(dest) { 393 | dest = ~dest; 394 | Sflg = (dest s< 0); 395 | Zflg = (dest == 0); 396 | } 397 | 398 | macro macro_or(src, dest) { 399 | dest = dest | src; 400 | Sflg = (dest s< 0); 401 | Zflg = (dest == 0); 402 | } 403 | 404 | macro macro_sbb8(src, dest) { 405 | local tmp = dest-(src-Cflg); 406 | Cflg = (tmp s>= 0); 407 | Zflg = (tmp == 0); 408 | Sflg = (tmp s< 0); 409 | Oflg = (tmp s< -128) | (tmp s> 127); 410 | dest = tmp; 411 | } 412 | 413 | macro macro_sbb16(src, dest) { 414 | local tmp = dest-(src+zext(Cflg)); 415 | Cflg = (tmp s>= 0); 416 | Zflg = (tmp == 0); 417 | Sflg = (tmp s< 0); 418 | Oflg = (tmp s< -32768) | (tmp s> 32767); 419 | dest = tmp; 420 | } 421 | 422 | macro macro_sub(src, dest) { 423 | local tmp = dest - src; 424 | Cflg = (tmp s>= 0); 425 | Zflg = (tmp == 0); 426 | Sflg = (tmp s< 0); 427 | Oflg = sborrow(dest, src); 428 | dest = tmp; 429 | } 430 | 431 | @define DEST_IS_An "(dest8_11=4 | dest8_11=5)" 432 | 433 | @define SRCDEST8 "op8_11 & op12_15 ; s_eab1 ; d_eab1 [srcmode=op12_15; destmode=op8_11;]" 434 | 435 | @define SRCDEST16 "op8_11 & op12_15 ; s_eaw1 ; d_eaw1 [srcmode=op12_15; destmode=op8_11;]" 436 | 437 | #:ABS.b d_eab is (op1_7=0x3b & size0=0 & op12_15=0xf) ... & d_eab { 438 | #} 439 | # 440 | #:ABS.w d_eaw is (op1_7=0x3b & size0=1 & op12_15=0xf) ... & d_eaw { 441 | # 442 | 443 | u8: "#"imm8 is imm8 { 444 | export *[const]:1 imm8; 445 | } 446 | 447 | u16: "#"imm16 is imm16 { 448 | export *[const]:2 imm16; 449 | } 450 | 451 | :ADC.b u8, dest8_11 is op1_7=0x3b & size0=0 & op12_15=0x6 & dest8_11 & $(DEST_IS_An); u8 { 452 | macro_adc16(zext(u8:1), dest8_11); 453 | } 454 | 455 | :ADC.b u8 ,d_eab is (op1_7=0x3b & size0=0 & op12_15=0x6) ... & d_eab; u8 { 456 | macro_adc8(u8, d_eab); 457 | } 458 | 459 | :ADC.w u16,d_eaw is (op1_7=0x3b & size0=1 & op12_15=0x6) ... & d_eaw; u16 { 460 | macro_adc16(u16, d_eaw); 461 | } 462 | 463 | :ADC.b s_eab,dest8_11 is (op1_7=0x58 & size0=0 & dest8_11 & $(DEST_IS_An)) ...& s_eab { 464 | macro_adc16(zext(s_eab), dest8_11); 465 | } 466 | 467 | :ADC.b s_eab1,d_eab1 is op1_7=0x58 & size0=0 & $(SRCDEST8) { 468 | macro_adc8(s_eab1, d_eab1); 469 | } 470 | 471 | :ADC.w s_eaw1,d_eaw1 is op1_7=0x58 & size0=1 & $(SRCDEST16) { 472 | macro_adc16(s_eaw1, d_eaw1); 473 | } 474 | 475 | :ADCF.b d_eab is (op1_7=0x3b & size0=0 & op12_15=0xe) ... & d_eab { 476 | local c:1 = Cflg; 477 | macro_add(c, d_eab); 478 | } 479 | :ADCF.w d_eaw is (op1_7=0x3b & size0=1 & op12_15=0xe) ... & d_eaw { 480 | macro_adc16(0, d_eaw); 481 | } 482 | 483 | :ADD.b u8, dest8_11 is op1_7=0x3b & size0=0 & op12_15=0x04 & dest8_11 & $(DEST_IS_An); u8 { 484 | macro_add(zext(u8:1), dest8_11); 485 | } 486 | 487 | :ADD.b u8, d_eab is (op1_7=0x3b & size0=0 & op12_15=0x04) ...& d_eab; u8 { 488 | macro_add(u8, d_eab); 489 | } 490 | 491 | :ADD.w u16, d_eaw is (op1_7=0x3b & size0=1 & op12_15=0x04) ... & d_eaw; u16 { 492 | macro_add(u16, d_eaw); 493 | } 494 | 495 | :ADD.b imm12_15, dest8_11 is op1_7=0x64 & size0=0 & imm12_15 & dest8_11 & $(DEST_IS_An) { 496 | macro_add(zext(imm12_15:1), dest8_11); 497 | } 498 | 499 | :ADD.b imm12_15, d_eab is (op1_7=0x64 & size0=0 & imm12_15) ... & d_eab { 500 | macro_add(imm12_15, d_eab); 501 | } 502 | 503 | :ADD.w imm12_15, d_eaw is (op1_7=0x64 & size0=1 & imm12_15) ... & d_eaw { 504 | macro_add(imm12_15, d_eaw); 505 | } 506 | 507 | :ADD.b imm8_15,d_imm is (op3_7_imm8=0x10 & imm8_15) ... & d_imm { 508 | macro_add(imm8_15, d_imm); 509 | } 510 | 511 | :ADD.b s_eab1,d_eab1 is op1_7=0x50 & size0=0 & $(SRCDEST8){ 512 | macro_add(s_eab1, d_eab1); 513 | } 514 | 515 | :ADD.w s_eaw1,d_eaw1 is op1_7=0x50 & size0=1 & $(SRCDEST16) { 516 | macro_add(s_eaw1, d_eaw1); 517 | } 518 | 519 | :ADD.b SRC2, dest2_2 is (op=0x04 & dest2_2) ... & SRC2 { 520 | macro_add(SRC2, dest2_2); 521 | } 522 | 523 | :ADD.b u8, SP is op1_7=0x3E & size0=0 & op12_15=0xE & op8_11=0x0b & SP; u8 { 524 | macro_add(sext(u8:1), SP); 525 | } 526 | 527 | :ADD.w u16, SP is op1_7=0x3E & size0=1 & op12_15=0xE & op8_11=0x0b & SP ; u16 { 528 | macro_add(u16, SP); 529 | } 530 | 531 | :ADD imm8_11,SP is op1_7=0x3E & size0 & op12_15=0xb & imm8_11 & SP { 532 | macro_add(sext(imm8_11:1), SP); 533 | } 534 | 535 | ADJNZ_DEST: addr is dsp8 [addr = dsp8 + (inst_start + 2);] { 536 | export *:3 addr; 537 | } 538 | 539 | :ADJNZ.b imm12_15, d_eab, ADJNZ_DEST is (op1_7=0x7c & size0=0 & imm12_15) ... & d_eab; ADJNZ_DEST { 540 | d_eab = d_eab + imm12_15; 541 | if(d_eab != 0) goto ADJNZ_DEST; 542 | } 543 | 544 | :ADJNZ.w imm12_15, d_eaw, ADJNZ_DEST is (op1_7=0x7c & size0=1 & imm12_15) ... & d_eaw; ADJNZ_DEST { 545 | d_eaw = d_eaw + imm12_15; 546 | if(d_eaw != 0) goto ADJNZ_DEST; 547 | } 548 | 549 | :AND.b u8,d_eab is (op1_7=0x3b & size0=0 & op12_15=0x2) ... & d_eab; u8 { 550 | macro_and(u8, d_eab); 551 | } 552 | 553 | :AND.w u16,d_eaw is (op1_7=0x3b & size0=1 & op12_15=0x2)...& d_eaw; u16 { 554 | macro_and(u16, d_eaw); 555 | } 556 | 557 | :AND.b imm8_15, d_imm is (op3_7_imm8=0x12 & imm8_15) ... & d_imm { 558 | macro_and(imm8_15, d_imm); 559 | } 560 | 561 | :AND.b s_eab1,d_eab1 is op1_7=0x48 & size0=0 & $(SRCDEST8) { 562 | macro_and(s_eab1, d_eab1); 563 | } 564 | 565 | :AND.w s_eaw1,d_eaw1 is op1_7=0x48 & size0=1 & $(SRCDEST16) { 566 | macro_and(s_eaw1, d_eaw1); 567 | } 568 | 569 | :AND.b SRC2, dest2_2 is (op=0x2 & dest2_2)...& SRC2 { 570 | macro_and(SRC2, dest2_2); 571 | } 572 | 573 | #:BAND d_eaw is (op1_7=0x3f &size0=0 & op12_15=0x4) ... & d_eaw { 574 | #} 575 | 576 | :BCLR dsp8, dest8_11 is op1_7=0x3f &size0=0 &op12_15=0x8 & dest8_11 & (dest8_11=0 |dest8_11=1 | dest8_11=2 |dest8_11 =3 |dest8_11=4 |dest8_11=5);dsp8 { 577 | dest8_11 = dest8_11&~(1 << zext(dsp8:1)); 578 | } 579 | 580 | :BCLR bit, addr is op1_7=0x3f &size0=0 &op12_15=0x8 & dest8_11 & (dest8_11=6 | dest8_11=7) [addr=dest8_11/8; bit=dest8_11-(addr*8);] { 581 | *[near]:1 addr:2 = *[near]:1 addr:2&~(1 << zext(bit:1)); 582 | } 583 | 584 | :BCLR bit, addr is op1_7=0x3f &size0=0 &op12_15=0x8 & dest8_11 & (dest8_11=8 | dest8_11=9 | dest8_11=10); dsp8 [addr=(dest8_11+dsp8)/8; bit=(dest8_11+dsp8)-(addr*8);] { 585 | *[near]:1 addr:2 = *[near]:1 addr:2&~(1 << zext(bit:1)); 586 | } 587 | 588 | :BCLR bit, addr[FB] is FB & op1_7=0x3f &size0=0 &op12_15=0x8 & dest8_11=11; dsp8 [addr=((8+dsp8)/8)-1; bit=(addr*8)-dsp8;]{ 589 | local tmp:2 = FB+addr; 590 | *[near]:1 tmp = *[near]:1 tmp&~(1 << zext(bit:1)); 591 | } 592 | 593 | :BCLR bit, addr is op1_7=0x3f &size0=0 &op12_15=0x8 & dest8_11 & (dest8_11=12 | dest8_11=13 | dest8_11=14); dsp16 [addr=(dest8_11+dsp16)/8; bit=(dest8_11+dsp16)-(addr*8);] { 594 | *[near]:1 addr:2 = *[near]:1 addr:2&~(1 << zext(bit:1)); 595 | } 596 | 597 | :BCLR bit, addr is op1_7=0x3f &size0=0 &op12_15=0x8 & dest8_11=15; abs16 [addr=abs16/8; bit=abs16-(addr*8);] { 598 | *[near]:1 addr:2 = *[near]:1 addr:2&~(1 << zext(bit:1)); 599 | } 600 | 601 | #:BCLR bit0_2, SB[dsp8] is op=0x8 & bit0_2 & SB;dsp8 { 602 | #} 603 | 604 | :BM^COND8 dsp8, dest8_11 is op1_7=0x3F & size0=0 & op12_15=0x2 & dest8_11 & (dest8_11 = 0 | dest8_11=1 | dest8_11=2 |dest8_11 =3 |dest8_11=4 |dest8_11=5);dsp8; COND8 { 605 | macro_bm(COND8:1, dsp8:1, dest8_11); 606 | } 607 | 608 | :BM^COND8 bit, addr is op1_7=0x3F & size0=0 & op12_15=0x2 & dest8_11 & (dest8_11=6 | dest8_11=7); COND8 [addr=dest8_11/8; bit=dest8_11-(addr*8);] { 609 | macro_bm(COND8:1, bit:1, *[near]:1 addr:2); 610 | } 611 | 612 | :BM^COND8 bit, addr is op1_7=0x3F & size0=0 & op12_15=0x2 & dest8_11 & (dest8_11=8 | dest8_11=9 | dest8_11=10); dsp8; COND8 [addr=(dest8_11+dsp8)/8; bit=(dest8_11+dsp8)-(addr*8);] { 613 | macro_bm(COND8:1, bit:1, *[near]:1 addr:2); 614 | } 615 | 616 | :BM^COND8 bit, addr[FB] is FB & op0_7=0x7E & op12_15=0x2 & dest8_11=11; dsp8; COND8 [addr=((8+dsp8)/8)-1; bit=(addr*8)-dsp8;]{ 617 | local tmp:2 = FB+addr; 618 | macro_bm(COND8:1, bit:1, *[near]:1 tmp); 619 | } 620 | 621 | :BM^COND8 bit, addr is op1_7=0x3F & size0=0 & op12_15=0x2 & dest8_11 & (dest8_11=12 | dest8_11=13 | dest8_11=14); dsp16; COND8 [addr=(dest8_11+dsp16)/8; bit=(dest8_11+dsp16)-(addr*8);] { 622 | macro_bm(COND8:1, bit:1, *[near]:1 addr:2); 623 | } 624 | 625 | :BM^COND8 bit, addr is op1_7=0x3F & size0=0 & op12_15=0x2 & dest8_11=15; abs16; COND8 [addr=abs16/8; bit=abs16-(addr*8);] { 626 | macro_bm(COND8:1, bit:1, *[near]:1 addr:2); 627 | } 628 | 629 | ##:BM^COND4 "C" is (op1_7=0x3E & size0=1 &op12_15=0xD) ... & COND4 { 630 | ##} 631 | # 632 | #:BNAND d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x05) ... & d_eaw { 633 | #} 634 | # 635 | #:BNOR d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x07) ... & d_eaw { 636 | #} 637 | # 638 | #:BNOT d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x0A) ... & d_eaw { 639 | #} 640 | # 641 | #:BNOT bit0_2, SB[dsp8] is op=0x0A & bit0_2 & SB; dsp8 { 642 | #} 643 | # 644 | #:BNTST d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x03) ... & d_eaw { 645 | #} 646 | # 647 | #:BNXOR d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x0D) ... & d_eaw { 648 | #} 649 | # 650 | #:BOR d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x06) ... & d_eaw { 651 | #} 652 | 653 | :BRK is ops0_7=0 { 654 | } 655 | 656 | 657 | :BSET dsp8, dest8_11 is op1_7=0x3F & size0=0 & op12_15=0x09 & dest8_11 & (dest8_11 = 0 | dest8_11=1 | dest8_11=2 |dest8_11 =3 |dest8_11=4 |dest8_11=5);dsp8 { 658 | dest8_11 = dest8_11|(1 << zext(dsp8:1)); 659 | } 660 | 661 | :BSET bit, addr is op1_7=0x3F & size0=0 & op12_15=0x09 & dest8_11 & (dest8_11=6 | dest8_11=7) [addr=dest8_11/8; bit=dest8_11-(addr*8);] { 662 | *[near]:1 addr:2 = *[near]:1 addr:2|(1 << zext(bit:1)); 663 | } 664 | 665 | :BSET bit, addr is op1_7=0x3F & size0=0 & op12_15=0x09 & dest8_11 & (dest8_11=8 | dest8_11=9 | dest8_11=10); dsp8 [addr=(dest8_11+dsp8)/8; bit=(dest8_11+dsp8)-(addr*8);] { 666 | *[near]:1 addr:2 = *[near]:1 addr:2|(1 << zext(bit:1)); 667 | } 668 | 669 | :BSET bit, addr[FB] is FB & op1_7=0x3F & size0=0 & op12_15=0x09 & dest8_11=11; dsp8 [addr=((8+dsp8)/8)-1; bit=(addr*8)-dsp8;]{ 670 | local tmp:2 = FB+addr; 671 | *[near]:1 tmp = *[near]:1 tmp|(1 << zext(bit:1)); 672 | } 673 | 674 | :BSET bit, addr is op1_7=0x3F & size0=0 & op12_15=0x09 & dest8_11 & (dest8_11=12 | dest8_11=13 | dest8_11=14); dsp16 [addr=(dest8_11+dsp16)/8; bit=(dest8_11+dsp16)-(addr*8);] { 675 | *[near]:1 addr:2 = *[near]:1 addr:2|(1 << zext(bit:1)); 676 | } 677 | 678 | :BSET bit, addr is op1_7=0x3F & size0=0 & op12_15=0x09 & dest8_11=15; abs16 [addr=abs16/8; bit=abs16-(addr*8);] { 679 | *[near]:1 addr:2 = *[near]:1 addr:2|(1 << zext(bit:1)); 680 | } 681 | 682 | #:BSET bit0_2, SB[dsp8] is op=0x09 & bit0_2 &SB; dsp8 { 683 | #} 684 | 685 | :BTST dsp8, dest8_11 is op0_7=0x7E & op12_15=0x0B & dest8_11 & (dest8_11=0 |dest8_11=1 | dest8_11=2 |dest8_11 =3 |dest8_11=4 |dest8_11=5);dsp8 { 686 | local newv = dest8_11&(1 << zext(dsp8:1)); 687 | Cflg = (newv != 0); 688 | Zflg = (newv == 0); 689 | } 690 | 691 | :BTST bit, addr is op0_7=0x7E & op12_15=0x0B & dest8_11 & (dest8_11=6 | dest8_11=7) [addr=dest8_11/8; bit=dest8_11-(addr*8);] { 692 | local newv = *[near]:1 addr:2&(1 << zext(bit:1)); 693 | Cflg = (newv != 0); 694 | Zflg = (newv == 0); 695 | } 696 | 697 | :BTST bit, addr is op0_7=0x7E & op12_15=0x0B & dest8_11 & (dest8_11=8 | dest8_11=9 | dest8_11=10); dsp8 [addr=(dest8_11+dsp8)/8; bit=(dest8_11+dsp8)-(addr*8);] { 698 | local newv = *[near]:1 addr:2&(1 << zext(bit:1)); 699 | Cflg = (newv != 0); 700 | Zflg = (newv == 0); 701 | } 702 | 703 | :BTST bit, addr[FB] is FB & op0_7=0x7E & op12_15=0x0B & dest8_11=11; dsp8 [addr=((8+dsp8)/8)-1; bit=(addr*8)-dsp8;]{ 704 | local tmp:2 = FB+addr; 705 | local newv = *[near]:1 tmp&(1 << zext(bit:1)); 706 | Cflg = (newv != 0); 707 | Zflg = (newv == 0); 708 | } 709 | 710 | :BTST bit, addr is op0_7=0x7E & op12_15=0x0B & dest8_11 & (dest8_11=12 | dest8_11=13); dsp16 [addr=(dest8_11+dsp16)/8; bit=(dest8_11+dsp16)-(addr*8);] { 711 | local newv = *[near]:1 addr:2&(1 << zext(bit:1)); 712 | Cflg = (newv != 0); 713 | Zflg = (newv == 0); 714 | } 715 | 716 | :BTST bit, addr is op0_7=0x7E & op12_15=0x0B & dest8_11=14; dsp16 [addr=(FB+dsp16)/8; bit=(FB+dsp16)-(addr*8);] { 717 | local newv = *[near]:1 addr:2&(1 << zext(bit:1)); 718 | Cflg = (newv != 0); 719 | Zflg = (newv == 0); 720 | } 721 | 722 | 723 | :BTST bit, addr is op0_7=0x7E & op12_15=0x0B & dest8_11=15; abs16 [addr=abs16/8; bit=abs16-(addr*8);] { 724 | local newv = *[near]:1 addr:2&(1 << zext(bit:1)); 725 | Cflg = (newv != 0); 726 | Zflg = (newv == 0); 727 | } 728 | 729 | #:BTST bit0_2, SB[dsp8] is op=0x0B & bit0_2 & SB; dsp8 { 730 | #} 731 | 732 | #:BTSTC d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x00) ...& d_eaw { 733 | #} 734 | # 735 | #:BTSTS d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x01) ... & d_eaw { 736 | #} 737 | # 738 | #:BXOR d_eaw is (op1_7=0x3F & size0=0 & op12_15=0x0C) ...& d_eaw { 739 | #} 740 | 741 | :CMP.b u8, d_eab is (op1_7=0x3B & size0=0 & op12_15=0x08) ... & d_eab; u8 { 742 | macro_cmp(u8, d_eab); 743 | } 744 | 745 | :CMP.w u16,d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x08) ... & d_eaw; u16 { 746 | macro_cmp(u16, d_eaw); 747 | } 748 | 749 | :CMP.b imm12_15, d_eab is (op1_7=0x68 & size0=0 & imm12_15) ... & d_eab { 750 | macro_cmp(imm12_15, d_eab); 751 | } 752 | 753 | 754 | :CMP.w imm12_15, d_eaw is (op1_7=0x68 & size0=1 & imm12_15) ... & d_eaw { 755 | macro_cmp(imm12_15, d_eaw); 756 | } 757 | 758 | 759 | :CMP.b imm8_15, d_imm is (op3_7_imm8=0x1C & imm8_15) ... & d_imm { 760 | macro_cmp(imm8_15, d_imm); 761 | } 762 | 763 | :CMP.b s_eab1, d_eab1 is op1_7=0x60 & size0=0 & $(SRCDEST8) { 764 | macro_cmp(s_eab1, d_eab1); 765 | } 766 | 767 | :CMP.w s_eaw1, d_eaw1 is op1_7=0x60 & size0=1 & $(SRCDEST16) { 768 | macro_cmp(s_eaw1, d_eaw1); 769 | } 770 | 771 | :CMP.B SRC2, dest2_2 is (op=0x07 & dest2_2) ... & SRC2 { 772 | macro_cmp(SRC2, dest2_2); 773 | } 774 | 775 | #:DADC.b imm8,R0L is op0_15=0x7CEE &R0L; imm8 { 776 | #} 777 | # 778 | #:DADC.w imm16,R0 is op0_15=0x7DEE &R0; imm16 { 779 | #} 780 | # 781 | #:DADC.b R0H,R0L is op0_15=0x7CE6 & R0H &R0L { 782 | #} 783 | # 784 | #:DADC.b R1,R0 is op0_15=0x7DE6 & R1 &R0 { 785 | #} 786 | # 787 | #:DADD.b imm8, R0L is op0_15=0x7CEC & R0L; imm8 { 788 | #} 789 | # 790 | #:DADD.w imm16,R0 is op0_15=0x7DEC & R0; imm16 { 791 | #} 792 | # 793 | #:DADD.b R0H, R0L is op0_15=0x7CE4 & R0L & R0H { 794 | #} 795 | # 796 | #:DADD.w R1, R0 is op0_15=0x7DE4 & R1 & R0 { 797 | #} 798 | 799 | :DEC.b d_d_eab is op=0x15 ... & d_d_eab { 800 | d_d_eab = d_d_eab-1; 801 | Sflg = (d_d_eab s< 0); 802 | Zflg = (d_d_eab == 0); 803 | } 804 | 805 | :DEC.w dest_a0_a1 is op4_7=0xF & dest_a0_a1 & bit0_2=0x2 { 806 | local tmp:2 = dest_a0_a1 -1; 807 | dest_a0_a1 = tmp-1; 808 | Sflg = (tmp s< 0); 809 | Zflg = (tmp == 0); 810 | dest_a0_a1 = tmp; 811 | } 812 | 813 | :DIV.b u8 is op1_7=0x3e & size0=0 & op8_15=0xe1; u8 { 814 | local q = R0 / sext(u8); 815 | local r = R0 % sext(u8); 816 | Oflg = (u8 == 0); 817 | Oflg = (q > 255); 818 | R0L = q:2; 819 | R0H = r:2; 820 | } 821 | 822 | :DIV.w u16 is op1_7=0x3e & size0=1 & op8_15=0xe1; u16 { 823 | local q = R2R0 / sext(u16); 824 | local r = R2R0 % sext(u16); 825 | Oflg = (u16 == 0); 826 | Oflg = (q > 65535); 827 | R0 = q:2; 828 | R2 = r:2; 829 | } 830 | 831 | :DIV.b d_eab is (op1_7=0x3B & size0=0 & op12_15=0xD) ... & d_eab { 832 | local q = R0 / sext(d_eab); 833 | local r = R0 % sext(d_eab); 834 | Oflg = (d_eab == 0); 835 | Oflg = (q > 255); 836 | R0L = q:2; 837 | R0H = r:2; 838 | } 839 | 840 | :DIV.w d_eaw is (op1_7=0x3B & size0=1 & op12_15=0xD) ... & d_eaw { 841 | local q = R2R0 / sext(d_eaw); 842 | local r = R2R0 % sext(d_eaw); 843 | Oflg = (d_eaw == 0); 844 | Oflg = (q > 65535); 845 | R0 = q:2; 846 | R2 = r:2; 847 | } 848 | 849 | :DIVU.b u8 is op1_7=0x3e & size0=0 & op8_15=0xe0; u8 { 850 | local q = R0 / zext(u8); 851 | local r = R0 % zext(u8); 852 | Oflg = (u8 == 0); 853 | Oflg = (q > 255); 854 | R0L = q:2; 855 | R0H = r:2; 856 | } 857 | 858 | :DIVU.w u16 is op1_7=0x3e & size0=1 & op8_15=0xe0; u16 { 859 | local q = R2R0 / zext(u16); 860 | local r = R2R0 % zext(u16); 861 | Oflg = (u16 == 0); 862 | Oflg = (q > 65535); 863 | R0 = q:2; 864 | R2 = r:2; 865 | } 866 | 867 | #:DIVU.b d_eab is (op1_7=0x3B & size0=0 & op12_15=0xC) ... & d_eab { 868 | #} 869 | 870 | :DIVU.w d_eaw is (op1_7=0x3B & size0=1 & op12_15=0xC) ... & d_eaw { 871 | local q = R2R0 / zext(d_eaw); 872 | local r = R2R0 % zext(d_eaw); 873 | Oflg = (d_eaw == 0); 874 | Oflg = (q > 65535); 875 | R0 = q:2; 876 | R2 = r:2; 877 | } 878 | 879 | #:DIVX.b imm8 is op1_7=0x3e & size0=0 & op8_15=0xe3; imm8 { 880 | #} 881 | # 882 | #:DIVX.b imm16 is op1_7=0x3e & size0=1 & op8_15=0xe3; imm16 { 883 | #} 884 | # 885 | #:DIVX.b d_eab is (op1_7=0x3B & size0=0 & op12_15=0x9) ... & d_eab { 886 | #} 887 | # 888 | #:DIVX.w d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x9) ... & d_eaw { 889 | #} 890 | # 891 | #:DSBB.b imm8, R0L is op0_15=0x7CEF & R0L; imm8 { 892 | #} 893 | # 894 | #:DSBB.w imm16, R0 is op0_15=0x7DEF & R0; imm16 { 895 | #} 896 | # 897 | #:DSBB.b R0H, R0L is op0_15=0x7CE7 & R0H & R0L { 898 | #} 899 | # 900 | #:DSBB.w R1, R0 is op0_15=0x7DE7 & R1 & R0 { 901 | #} 902 | # 903 | #:DSUB.b imm8, R0L is op0_15=0x7CED & R0L; imm8 { 904 | #} 905 | # 906 | #:DSUB.w imm16, R0 is op0_15=0x7DED & R0; imm16 { 907 | #} 908 | # 909 | #:DSUB.b R0H, R0L is op0_15=0x7CE5 & R0H &R0L { 910 | #} 911 | # 912 | #:DSUB.w R1, R0 is op0_15=0x7DE5 & R1 & R0 { 913 | #} 914 | 915 | :ENTER imm8 is op0_15=0xF27C;imm8 { 916 | SP = SP -2; 917 | *[near]:2 SP = FB:2; 918 | FB = SP; 919 | 920 | SP = SP - imm8; 921 | } 922 | 923 | :EXITD is op0_15=0xF27D { 924 | SP = FB; 925 | FB = *[near]:2 SP; 926 | SP = SP+2; 927 | local return_addr:3 = *[near]:2 SP; 928 | SP = SP+2; 929 | local pc_h:3 = zext(*[near]:2 SP) << 16; 930 | SP = SP-1; 931 | return_addr = return_addr & pc_h; 932 | return [return_addr]; 933 | } 934 | 935 | :EXTS.b R0L is R0L & op0_7=0x7C & op12_15=0x06 & dest8_11=0 { 936 | R0 = sext(R0L); 937 | Sflg = (R0 s< 0); 938 | Zflg = (R0 == 0); 939 | } 940 | 941 | :EXTS.b R1L is R1L & op0_7=0x7C & op12_15=0x06 & dest8_11=2 { 942 | R1 = sext(R1L); 943 | Sflg = (R1 s< 0); 944 | Zflg = (R1 == 0); 945 | } 946 | 947 | :EXTS.b j_n_eaw is (op0_7=0x7C & op12_15=0x06) ... & j_n_eaw { 948 | *[near]:2 j_n_eaw = sext(*[near]:1 j_n_eaw); 949 | Sflg = (*[near]:2 j_n_eaw s< 0); 950 | Zflg = (*[near]:2 j_n_eaw == 0); 951 | } 952 | 953 | :EXTS.w R0 is op0_15=0xF37C & R0 { 954 | R2R0 = sext(R0); 955 | } 956 | 957 | define pcodeop FLAG_CLEAR; 958 | define pcodeop FLAG_SET; 959 | define pcodeop INTERRUPTS_ENABLE; 960 | define pcodeop INTERRUPTS_DISABLE; 961 | 962 | :FCLR flg12_14 is op0_7=0xEB & op8_11=0x05 & bit15=0 & flg12_14 & flg12_14=6 { 963 | INTERRUPTS_DISABLE(); 964 | flg12_14 = 0; 965 | } 966 | 967 | :FSET flg12_14 is op0_7=0xEB & op8_11=0x04 & bit15=0 & flg12_14 & flg12_14=6 { 968 | INTERRUPTS_ENABLE(); 969 | flg12_14 = 1; 970 | } 971 | 972 | :FCLR flg12_14 is op0_7=0xEB & op8_11=0x05 & bit15=0 & flg12_14 { 973 | FLAG_CLEAR(flg12_14); 974 | } 975 | 976 | :FSET flg12_14 is op0_7=0xEB & op8_11=0x04 & bit15=0 & flg12_14 { 977 | FLAG_SET(flg12_14); 978 | } 979 | 980 | 981 | :INC.b d_d_eab is op=0x14 ... & d_d_eab { 982 | d_d_eab = d_d_eab+1; 983 | Sflg = (d_d_eab s< 0); 984 | Zflg = (d_d_eab == 0); 985 | } 986 | 987 | :INC.w dest_a0_a1 is op4_7=0x0B & dest_a0_a1 & bit0_2=0x02 { 988 | local tmp:2 = dest_a0_a1+1; 989 | Sflg = (tmp s< 0); 990 | Zflg = (tmp == 0); 991 | dest_a0_a1 = tmp; 992 | } 993 | 994 | define pcodeop INTERRUPT; 995 | 996 | :INT interrupt is ops0_7=0xEB; data8_bit6=1 & data8_bit7=1 & interrupt { 997 | INTERRUPT(interrupt:1); 998 | } 999 | 1000 | :INTO is ops0_7=0xF6 { 1001 | } 1002 | 1003 | dest: addr is dsp8 [addr = (inst_start+1)+dsp8;] { 1004 | export *:4 addr; 1005 | } 1006 | 1007 | dest4: addr is dsp8 [addr = (inst_start+2)+dsp8;] { 1008 | export *:4 addr; 1009 | } 1010 | 1011 | # TODO: Actually evalulate condition 1012 | :J^COND3 dest is op=0x0D & COND3; dest { 1013 | if (COND3) goto dest; 1014 | } 1015 | 1016 | :J^COND4 dest4 is op0_7=0x7D & op12_15=0x0C & COND4; dest4 { 1017 | if (COND4) goto dest4; 1018 | } 1019 | 1020 | :JMP.s addr is op=0x0C & dsp0_2 [addr = (inst_start+2)+dsp0_2;] { 1021 | goto [addr:4]; 1022 | } 1023 | 1024 | :JMP.b addr is ops0_7=0xFE; dsp8 [addr = (inst_start+1)+dsp8;] { 1025 | goto [addr:4]; 1026 | } 1027 | 1028 | :JMP.w addr is ops0_7=0xF4; dsp16 [addr = (inst_start+1)+dsp16;] { 1029 | goto [addr:4]; 1030 | } 1031 | 1032 | :JMP.A abs20 is ops0_7=0xFC; abs20 { 1033 | goto [abs20:4]; 1034 | } 1035 | 1036 | 1037 | 1038 | :JMPI.w j_eaw is (op0_7=0x7D & op12_15=0x02) ... & j_eaw { 1039 | local addr:4 = inst_start+sext(j_eaw); 1040 | goto [addr]; 1041 | } 1042 | 1043 | #:JMPI.a j_eaw is op0_7=0x7D & op12_15=0x00 & dest8_11; j_eaw { 1044 | # goto [j_eaw]; 1045 | #} 1046 | # 1047 | #:JMPS imm8 is ops0_7=0xEE; imm8 { 1048 | #} 1049 | # 1050 | :JSR.w addr is ops0_7=0xF5; dsp16 [addr = dsp16+inst_start+1;] { 1051 | SP = SP-3; 1052 | *[near]:3 SP = inst_next; 1053 | call [addr:3]; 1054 | } 1055 | 1056 | :JSR.a abs20 is ops0_7=0xFD; abs20 { 1057 | SP = SP-3; 1058 | *[near]:3 SP = inst_next; 1059 | call [abs20:3]; 1060 | } 1061 | # 1062 | #:JSRI.w j_eaw is (op0_7=0x7D & op12_15=0x03) ... & j_eaw { 1063 | #} 1064 | 1065 | 1066 | :JSRI.a src32_8_11 is op0_7=0x7D & op12_15=0x01 & src32_8_11 & (src32_8_11=0 | src32_8_11 = 1 | src32_8_11 =4) { 1067 | SP = SP-3; 1068 | *[near]:3 SP = inst_next; 1069 | call [src32_8_11]; 1070 | } 1071 | 1072 | 1073 | 1074 | :JSRI.a j_eaw is (op0_7=0x7D & op12_15=0x01) ...& j_eaw { 1075 | SP = SP-3; 1076 | *[near]:3 SP = inst_next; 1077 | call [j_eaw]; 1078 | } 1079 | 1080 | #:JSRS imm8 is op0_7=0xEF; imm8 { 1081 | #} 1082 | ## 1083 | #:LDC imm16, "USP" is op0_7=0xEB & op8_11=0x00 & ldc12_14=5 & bit15=0; imm16 { 1084 | # SP = zext(imm16:2); 1085 | ## SP = zext(USP); 1086 | #} 1087 | 1088 | :LDC u16, FB is FB & op0_7=0xEB & op8_11=0x00 & ldc12_14=0x7 & bit15=0; u16 { 1089 | FB = u16; 1090 | # SP = zext(USP); 1091 | } 1092 | 1093 | :LDC u16, ldc12_14 is op0_7=0xEB & op8_11=0x00 & ldc12_14 & bit15=0; u16 { 1094 | ldc12_14 = u16; 1095 | # SP = zext(USP); 1096 | } 1097 | 1098 | :LDC d_eaw, FB is (FB & op0_7=0x7A & ldc12_14=0x07 & bit15=1) ... & d_eaw { 1099 | FB = d_eaw; 1100 | } 1101 | 1102 | :LDC d_eaw, ldc12_14 is (op0_7=0x7A & ldc12_14 & bit15=1) ... & d_eaw { 1103 | ldc12_14 = d_eaw; 1104 | } 1105 | 1106 | # TODO: Implement this? 1107 | define pcodeop LOAD_CONTEXT; 1108 | 1109 | :LDCTX abs16, abs20 is op0_15=0xF07C; abs16; abs20 { 1110 | LOAD_CONTEXT(abs16:2, abs20:3); 1111 | } 1112 | 1113 | :LDE.b abs20, dest8_11 is op1_7=0x3A & size0=0 & op12_15=0x08 & dest8_11 & $(DEST_IS_An); abs20 { 1114 | local addr:4 = zext(abs20:3); 1115 | dest8_11 = zext(*:1 addr); 1116 | Zflg = (dest8_11 == 0); 1117 | Sflg = (dest8_11 s< 0); 1118 | } 1119 | 1120 | :LDE.b abs20, d_eab is (op1_7=0x3A & size0=0 & op12_15=0x08) ... & d_eab; abs20 { 1121 | local addr:4 = zext(abs20:3); 1122 | d_eab = *:1 addr; 1123 | Zflg = (d_eab == 0); 1124 | Sflg = (d_eab s< 0); 1125 | } 1126 | 1127 | :LDE.w abs20, d_eaw is (op1_7=0x3A & size0=1 & op12_15=0x08) ... & d_eaw; abs20 { 1128 | local addr:4 = zext(abs20:3); 1129 | d_eaw = *:2 addr; 1130 | Zflg = (d_eaw == 0); 1131 | Sflg = (d_eaw s< 0); 1132 | } 1133 | 1134 | :LDE.b dsp20[A0], dest8_11 is A0 & op1_7=0x3A & size0=0 & op12_15=0x09 & dest8_11 & $(DEST_IS_An); dsp20 { 1135 | local addr:4 = zext(zext(A0)+dsp20:3); 1136 | local tmp:1 = *:1 addr; 1137 | Zflg = (tmp == 0); 1138 | Sflg = (tmp s< 0); 1139 | dest8_11 = zext(tmp); 1140 | } 1141 | 1142 | :LDE.b dsp20[A0], d_eab is (A0 & op1_7=0x3A & size0=0 & op12_15=0x09) ... & d_eab; dsp20 { 1143 | local addr:4 = zext(zext(A0)+dsp20:3); 1144 | local tmp:1 = *:1 addr; 1145 | Zflg = (tmp == 0); 1146 | Sflg = (tmp s< 0); 1147 | d_eab = tmp; 1148 | } 1149 | 1150 | :LDE.w dsp20[A0], d_eaw is (A0 & op1_7=0x3A & size0=1 & op12_15=0x09) ... & d_eaw; dsp20 { 1151 | local addr:4 = zext(A0)+zext(dsp20:3); 1152 | d_eaw = *:2 addr; 1153 | Zflg = (d_eaw == 0); 1154 | Sflg = (d_eaw s< 0); 1155 | } 1156 | 1157 | :LDE.b A1A0, d_eab is (op1_7=0x3A & size0=0 & op12_15=0x0A &A1A0) ... & d_eab { 1158 | d_eab = *:1 A1A0; 1159 | Zflg = (d_eab == 0); 1160 | Sflg = (d_eab s< 0); 1161 | } 1162 | 1163 | :LDE.w A1A0, d_eaw is (op1_7=0x3A & size0=1 & op12_15=0x0A &A1A0) ... & d_eaw { 1164 | d_eaw = *:2 A1A0; 1165 | Zflg = (d_eaw == 0); 1166 | Sflg = (d_eaw s< 0); 1167 | } 1168 | 1169 | # 1170 | ## TODO LDINTB PDF page 212 1171 | ##:LDINTB 1172 | define pcodeop IPL_LOAD; 1173 | 1174 | :LDIPL imm8_10 is op0_7=0x7D & op12_15=0x0A & bit11=0 & imm8_10 { 1175 | IPL_LOAD(imm8_10:1); 1176 | IPLflg = imm8_10:1; 1177 | } 1178 | 1179 | 1180 | :MOV.b u8, d_eab is (op1_7=0x3A & size0=0 & op12_15=0x0C) ... & d_eab; u8 { 1181 | macro_mov(u8, d_eab); 1182 | } 1183 | 1184 | :MOV.w u16, d_eaw is (op1_7=0x3A & size0=1 & op12_15=0x0C) ... & d_eaw; u16 { 1185 | macro_mov(u16, d_eaw); 1186 | } 1187 | 1188 | #Handle zero extending to fill A0/A1 when moving to them 1189 | :MOV.b "#"imm12_15, dest8_11 is op1_7=0x6C & size0=0 & imm12_15 & dest8_11 & $(DEST_IS_An) { 1190 | macro_mov(zext(imm12_15:1), dest8_11); 1191 | } 1192 | 1193 | :MOV.b "#"imm12_15, d_eab is (op1_7=0x6C & size0=0 & imm12_15) ... & d_eab { 1194 | macro_mov(imm12_15, d_eab); 1195 | } 1196 | 1197 | :MOV.w "#"imm12_15, d_eaw is (op1_7=0x6C & size0=1 & imm12_15) ... & d_eaw { 1198 | macro_mov(zext(imm12_15:1), d_eaw); 1199 | } 1200 | 1201 | :MOV.b "#"imm8_15, d_imm is (op3_7_imm8=0x18 & imm8_15) ... & d_imm { 1202 | macro_mov(imm8_15, d_imm); 1203 | } 1204 | 1205 | ## Size is 1 for byte and 0 for word. Opposite of everything else? 1206 | :MOV.b u8, A0 is A0 & op4_7=0x0E & bit0_2=0x02 & dest_a0_a1=0; u8 { 1207 | macro_mov(zext(u8:1), A0); 1208 | } 1209 | 1210 | :MOV.b u8, A1 is A1 & op4_7=0x0E & bit0_2=0x02 & dest_a0_a1=1; u8 { 1211 | macro_mov(zext(u8:1), A1); 1212 | } 1213 | 1214 | 1215 | # TODO: Why these need to be seperated I do not know, otherwise they would be fixed by now 1216 | # Size is 1 for byte and 0 for word. Opposite of everything else? 1217 | :MOV.w u16, A0 is A0 & op4_7=0x0A & dest_a0_a1=0 & bit0_2=0x02; u16 { 1218 | macro_mov(u16, A0); 1219 | } 1220 | 1221 | # Size is 1 for byte and 0 for word. Opposite of everything else? 1222 | :MOV.w u16, A1 is A1 & op4_7=0x0A & dest_a0_a1=1 & bit0_2=0x02; u16 { 1223 | macro_mov(u16, A1); 1224 | } 1225 | 1226 | ZERO: "0" is epsilon { 1227 | local tmp:1 = 0; 1228 | export *[const]:1 tmp; 1229 | } 1230 | 1231 | :MOV.b ZERO, d_d_eab is op=0x16 ... & d_d_eab; ZERO { 1232 | macro_mov(ZERO, d_d_eab); 1233 | } 1234 | 1235 | #Handle zero extending to fill A0/A1 when moving to them 1236 | :MOV.b s_eab, dest8_11 is (op1_7=0x39 & size0=0 & dest8_11 & $(DEST_IS_An)) ...& s_eab { 1237 | macro_mov(zext(s_eab:1), dest8_11); 1238 | } 1239 | 1240 | :MOV.b s_eab1, d_eab1 is op1_7=0x39 & size0=0 & $(SRCDEST8) { 1241 | macro_mov(s_eab1, d_eab1); 1242 | } 1243 | 1244 | :MOV.w s_eaw1, d_eaw1 is op1_7=0x39 & size0=1 & $(SRCDEST16) { 1245 | macro_mov(s_eaw1, d_eaw1); 1246 | } 1247 | 1248 | :MOV.b SRC2, dest2_a0_a1 is (op=0x06 & dest2_a0_a1) ... & SRC2 { 1249 | macro_mov(zext(SRC2), dest2_a0_a1); 1250 | } 1251 | 1252 | :MOV.b dest2_2,SRC2 is (op=0x00 &dest2_2) ... & SRC2 { 1253 | macro_mov(dest2_2, SRC2); 1254 | } 1255 | 1256 | :MOV.b SRC2, dest2_2 is (op=0x01 &dest2_2) ... & SRC2 { 1257 | macro_mov(SRC2, dest2_2); 1258 | } 1259 | 1260 | #Handle zero extending to fill A0/A1 when moving to them 1261 | :MOV.b dsp8[SP], dest8_11 is SP &op1_7=0x3A & size0=0 & op12_15=0x0B & dest8_11 & $(DEST_IS_An); dsp8 { 1262 | local addr:2 = SP+sext(dsp8:1); 1263 | macro_mov(zext(*[near]:1 addr), dest8_11); 1264 | } 1265 | 1266 | :MOV.b dsp8[SP], d_eab is (SP & op1_7=0x3A & size0=0 & op12_15=0x0B) ... & d_eab ; dsp8 { 1267 | local addr:2 = SP+sext(dsp8:1); 1268 | macro_mov(*[near]:1 addr, d_eab); 1269 | } 1270 | 1271 | :MOV.w dsp8[SP], d_eaw is (SP & op1_7=0x3A & size0=1 & op12_15=0x0b) ... & d_eaw; dsp8 { 1272 | local addr:2 = SP+sext(dsp8:1); 1273 | macro_mov(*[near]:2 addr, d_eaw); 1274 | } 1275 | 1276 | :MOV.b d_eab, dsp8[SP] is (SP & op1_7=0x3A & size0=0 & op12_15=0x03) ... & d_eab; dsp8 { 1277 | local addr:2 = SP+sext(dsp8:1); 1278 | macro_mov(d_eab, *[near]:1 addr); 1279 | } 1280 | 1281 | :MOV.w d_eaw, dsp8[SP] is (SP & op1_7=0x3A & size0=1 & op12_15=0x03) ... & d_eaw; dsp8 { 1282 | local addr:2 = SP+sext(dsp8:1); 1283 | macro_mov(d_eaw, *[near]:2 addr); 1284 | } 1285 | 1286 | MOVA_ADDRESS: dsp8[dest8_11] is dest8_11 & dest8_11=8; dsp8 { local addr:2 = dest8_11+zext(dsp8:1); export addr; } 1287 | MOVA_ADDRESS: dsp8[dest8_11] is dest8_11 & dest8_11=9; dsp8 { local addr:2 = dest8_11+zext(dsp8:1); export addr; } 1288 | MOVA_ADDRESS: dsp8[dest8_11] is dest8_11 & dest8_11=10; dsp8 { local addr:2 = dest8_11+zext(dsp8:1); export addr; } 1289 | MOVA_ADDRESS: dsp8[FB] is FB & dest8_11=11; dsp8 { local addr:2 = FB+sext(dsp8:1); export addr; } 1290 | MOVA_ADDRESS: dsp16[dest8_11] is dest8_11 & dest8_11=12; dsp16 { local addr:2 = dest8_11+dsp16; export addr; } 1291 | MOVA_ADDRESS: dsp16[dest8_11] is dest8_11 & dest8_11=13; dsp16 { local addr:2 = dest8_11+dsp16; export addr; } 1292 | MOVA_ADDRESS: dsp16[dest8_11] is dest8_11 & dest8_11=14; dsp16 { local addr:2 = dest8_11+dsp16; export addr; } 1293 | MOVA_ADDRESS: abs16 is dest8_11 & dest8_11=15; abs16 { local addr:2 = abs16; export addr; } 1294 | 1295 | :MOVA MOVA_ADDRESS, dest12_14 is (op0_7=0xEB & bit15=0 & dest12_14) ... & MOVA_ADDRESS { 1296 | dest12_14 = MOVA_ADDRESS:2; 1297 | } 1298 | 1299 | :MOVLL R0L, d_eab is (R0L & op0_7=0x7C & bit15=1 & bit14=0 & dir=0x00) ... & d_eab { 1300 | d_eab = (d_eab & 0xF)|(R0L & 0xF); 1301 | } 1302 | :MOVLH R0L, d_eab is (R0L & op0_7=0x7C & bit15=1 & bit14=0 & dir=0x02) ... & d_eab { 1303 | d_eab = (d_eab &0xF0)|(R0L << 4); 1304 | } 1305 | :MOVHL R0L, d_eab is (R0L & op0_7=0x7C & bit15=1 & bit14=0 & dir=0x01) ... & d_eab { 1306 | d_eab = (d_eab & 0xF0)|(R0L >> 4); 1307 | } 1308 | :MOVHH R0L, d_eab is (R0L & op0_7=0x7C & bit15=1 & bit14=0 & dir=0x03) ... & d_eab { 1309 | d_eab = (d_eab & 0xF0)|(R0L & 0xF0); 1310 | } 1311 | 1312 | :MOVLL d_eab, R0L is (R0L & op0_7=0x7C & bit15=0 & bit14=0 & dir=0x00) ... & d_eab { 1313 | R0L = (R0L & 0xF)|(d_eab & 0xF); 1314 | } 1315 | :MOVLH d_eab, R0L is (R0L & op0_7=0x7C & bit15=0 & bit14=0 & dir=0x02) ... & d_eab { 1316 | R0L = (R0L &0xF0)|(d_eab << 4); 1317 | } 1318 | :MOVHL d_eab, R0L is (R0L & op0_7=0x7C & bit15=0 & bit14=0 & dir=0x01) ... & d_eab { 1319 | R0L = (R0L & 0xF0)|(d_eab >> 4); 1320 | } 1321 | :MOVHH d_eab, R0L is (R0L & op0_7=0x7C & bit15=0 & bit14=0 & dir=0x03) ... & d_eab { 1322 | R0L = (R0L & 0xF0)|(d_eab & 0xF0); 1323 | } 1324 | 1325 | #:MUL.b imm8, d_eab is (op1_7=0x3E & size0=0 & op12_15=0x05) ... & d_eab; imm8 { 1326 | #} 1327 | 1328 | :MUL.b u8, mul8b8_11 is op1_7=0x3E & size0=0 & op12_15=0x05 & dest8_11 & (dest8_11=0|dest8_11=1|dest8_11=2|dest8_11=3) & mul8b8_11; u8 { 1329 | local tmp:2 = sext(u8:1)*sext(mul8b8_11); 1330 | dest8_11 = tmp; 1331 | } 1332 | 1333 | # TODO: Implement everything else other than destination being R2R0 R3R1 A1A0 1334 | :MUL.w u16, dest8_11 is op1_7=0x3E & size0=1 & op12_15=0x05 & (mul8_11=0|mul8_11=1|mul8_11=4) & mul8_11 & dest8_11; u16 { 1335 | local temp:4 = sext(dest8_11:2)*sext(u16); 1336 | mul8_11 = temp; 1337 | } 1338 | 1339 | #:MUL.b s_eab, d_eab is op1_7=0x3C & size0=0 & src12_15 & dest8_11; s_eab; d_eab { 1340 | #} 1341 | 1342 | :MUL.w src12_15, dest8_11 is op1_7=0x3C & size0=1 & dest8_11 & src12_15 & (mul8_11=0|mul8_11=1|mul8_11=4) & (src12_15=0|src12_15=1|src12_15=2|src12_15=3|src12_15=4) & mul8_11 { 1343 | mul8_11 = sext(src12_15)*sext(dest8_11); 1344 | } 1345 | 1346 | 1347 | :MULU.b u8, mul8b8_11 is op1_7=0x3E & size0=0 & op12_15=0x04 & dest8_11 & (dest8_11=0|dest8_11=1|dest8_11=2|dest8_11=3) & mul8b8_11; u8 { 1348 | local tmp:2 = zext(u8:1)*zext(mul8b8_11); 1349 | dest8_11 = tmp; 1350 | } 1351 | 1352 | #:MULU.b imm8, dest8_11 is op1_7=0x3E & size0=0 & op12_15=0x04 & dest8_11 & (dest8_11=0|dest8_11=1|dest8_11=2|dest8_11=3|dest8_11=4|dest8_11=5); imm8 { 1353 | # local tmp:2 = zext(imm8:1)*dest8_11; 1354 | # dest8_11 = tmp; 1355 | #} 1356 | 1357 | #:MULU.b imm8, d_eab is (op1_7=0x3E & size0=0 & op12_15=0x04) ... & d_eab; imm8 { 1358 | #} 1359 | 1360 | # TODO: Implement everything else other than destination being R2R0 R3R1 A1A0 1361 | :MULU.w u16, dest8_11 is op1_7=0x3E & size0=1 & op12_15=0x04 & (mul8_11=0|mul8_11=1|mul8_11=4) & mul8_11 & dest8_11; u16 { 1362 | local temp:4 = zext(dest8_11:2)*zext(u16:2); 1363 | mul8_11 = temp; 1364 | } 1365 | 1366 | #:MULU.b s_eab1, dest8_11 is (op1_7=0x38 & size0=0 & op8_11 & op12_15 & dest8_11 & $(DEST_IS_An)) ... & s_eab1 [srcmode=op12_15; destmode=op8_11;] { 1367 | # local tmp:2 = zext(s_eab1:1)*dest8_11; 1368 | # dest8_11 = tmp; 1369 | #} 1370 | # 1371 | #:MULU.b s_eab1, d_eab1 is op1_7=0x38 & size0=0 & $(SRCDEST8) { 1372 | #} 1373 | 1374 | :MULU.w s_eaw1, d_eaw1 is (op1_7=0x38 & size0=1 & op8_11 & op12_15 & src32_8_11 & (src32_8_11=0 | src32_8_11=1 | src32_8_11=3)); s_eaw1; d_eaw1 [srcmode=op12_15; destmode=op8_11;] { 1375 | src32_8_11 = zext(d_eaw1)*zext(s_eaw1); 1376 | } 1377 | 1378 | :NEG.b d_eab is (op1_7=0x3A & size0=0 & op12_15=0x05) ... & d_eab { 1379 | Oflg = (d_eab == -128); 1380 | d_eab = -d_eab; 1381 | Sflg = (d_eab s< 0); 1382 | Zflg = (d_eab == 0); 1383 | Cflg = (d_eab == 0); 1384 | } 1385 | 1386 | :NEG.w d_eaw is (op1_7=0x3A & size0=1 & op12_15=0x05) ... & d_eaw { 1387 | Oflg = (d_eaw == -32768); 1388 | d_eaw = -d_eaw; 1389 | Sflg = (d_eaw s< 0); 1390 | Zflg = (d_eaw == 0); 1391 | Cflg = (d_eaw == 0); 1392 | } 1393 | 1394 | :NOP is ops0_7=0x04 { 1395 | } 1396 | 1397 | :NOT.b dest8_11 is op1_7=0x3A & size0=0 & op12_15=0x07 & dest8_11 & $(DEST_IS_An) { 1398 | macro_not(dest8_11:1); 1399 | } 1400 | 1401 | :NOT.b d_eab is (op1_7=0x3A & size0=0 & op12_15=0x07) ... & d_eab { 1402 | macro_not(d_eab); 1403 | } 1404 | 1405 | :NOT.w d_eaw is (op1_7=0x3A & size0=1 & op12_15=0x07) ... & d_eaw { 1406 | macro_not(d_eaw); 1407 | } 1408 | 1409 | :NOT.b d_d_eab is op=0x17 ... & d_d_eab { 1410 | macro_not(d_d_eab); 1411 | } 1412 | 1413 | 1414 | :OR.b u8, dest8_11 is op1_7=0x3B & size0=0 & op12_15=0x03 & dest8_11 & $(DEST_IS_An); u8 { 1415 | macro_or(zext(u8:1), dest8_11); 1416 | } 1417 | 1418 | :OR.b u8, d_eab is (op1_7=0x3B & size0=0 & op12_15=0x03) ... & d_eab; u8 { 1419 | macro_or(u8, d_eab); 1420 | } 1421 | 1422 | :OR.w u16, d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x03) ... & d_eaw; u16 { 1423 | macro_or(u16, d_eaw); 1424 | } 1425 | 1426 | :OR.b imm8_15, d_imm is (op3_7_imm8=0x13 & imm8_15) ... & d_imm { 1427 | macro_or(imm8_15, d_imm); 1428 | } 1429 | 1430 | :OR.b s_eab, dest8_11 is (op1_7=0x4C & size0=0 & op12_15=0x03 & dest8_11 & $(DEST_IS_An)) ... & s_eab { 1431 | macro_or(zext(s_eab), dest8_11); 1432 | } 1433 | 1434 | :OR.b s_eab1, d_eab1 is op1_7=0x4C & size0=0 & $(SRCDEST8) { 1435 | macro_or(s_eab1, d_eab1); 1436 | } 1437 | 1438 | :OR.w s_eaw1, d_eaw1 is op1_7=0x4C & size0=1 & $(SRCDEST16) { 1439 | macro_or(s_eaw1, d_eaw1); 1440 | } 1441 | 1442 | :OR.b SRC2, dest2_2 is (op=0x03 & dest2_2) ... & SRC2 { 1443 | macro_or(SRC2, dest2_2); 1444 | } 1445 | 1446 | :POP.b d_eab is (op1_7=0x3A & size0=0 & op12_15=0x0D) ... & d_eab { 1447 | d_eab = *[near]:1 SP; 1448 | SP = SP + 1; 1449 | } 1450 | 1451 | :POP.w d_eaw is (op1_7=0x3A & size0=1 & op12_15=0x0D) ... & d_eaw { 1452 | d_eaw = *[near]:2 SP; 1453 | SP = SP + 2; 1454 | } 1455 | 1456 | :POP.b R0L is R0L & op4_7=0x09 & dest3_r0l_r0h=0 &bit0_2=0x02 { 1457 | R0L = *[near]:1 SP; 1458 | SP = SP + 1; 1459 | } 1460 | 1461 | :POP.b R0H is R0H & op4_7=0x09 & dest3_r0l_r0h=1 &bit0_2=0x02 { 1462 | R0H = *[near]:1 SP; 1463 | SP = SP + 1; 1464 | } 1465 | 1466 | :POP.w A0 is A0 & op4_7=0x0D & dest_a0_a1=0 &bit0_2=0x02 { 1467 | A0 = *[near]:2 SP; 1468 | SP = SP + 2; 1469 | } 1470 | 1471 | :POP.w A1 is A1 & op4_7=0x0D & dest_a0_a1=1 &bit0_2=0x02 { 1472 | A1 = *[near]:2 SP; 1473 | SP = SP + 2; 1474 | } 1475 | 1476 | 1477 | #:POPC ldc12_14 is op0_7=0xEB & ldc12_14 & op8_11=0x03 { 1478 | #} 1479 | 1480 | POPFB: FB is FB & bit15=1 {FB = *[near]:2 SP; SP = SP+2;} 1481 | POPFB: is bit15=0 {} 1482 | POPSB: SB is SB & bit14=1 {SB = *[near]:2 SP; SP = SP+2;} 1483 | POPSB: is bit14=0 {} 1484 | POPA1: A1 is A1 & bit13=1 {A1 = *[near]:2 SP; SP = SP+2;} 1485 | POPA1: is bit13=0 {} 1486 | POPA0: A0 is A0 & bit12=1 {A0 = *[near]:2 SP; SP = SP+2;} 1487 | POPA0: is bit12=0 {} 1488 | POPR3: R3 is R3 & bit11=1 {R3 = *[near]:2 SP; SP = SP+2;} 1489 | POPR3: is bit11=0 {} 1490 | POPR2: R2 is R2 & bit10=1 {R2 = *[near]:2 SP; SP = SP+2;} 1491 | POPR2: is bit10=0 {} 1492 | POPR1: R1 is R1 & bit9=1 {R1 = *[near]:2 SP; SP = SP+2;} 1493 | POPR1: is bit9=0 {} 1494 | POPR0: R0 is R0 & bit8=1 {R0 = *[near]:2 SP; SP = SP+2;} 1495 | POPR0: is bit8=0 {} 1496 | 1497 | POPMDISP: POPFB POPSB POPA1 POPA0 POPR3 POPR2 POPR1 POPR0 is POPFB & POPSB & POPA1 & POPA0 & POPR3 & POPR2 & POPR1 & POPR0 { 1498 | build POPFB; 1499 | build POPSB; 1500 | build POPA1; 1501 | build POPA0; 1502 | build POPR3; 1503 | build POPR2; 1504 | build POPR1; 1505 | build POPR0; 1506 | } 1507 | 1508 | :POPM POPMDISP is op0_7=0xED & POPMDISP { 1509 | } 1510 | 1511 | :PUSH.b u8 is op1_7=0x3E & size0=0 &op8_15=0xE2; u8 { 1512 | SP = SP-1; 1513 | *[near]:1 SP = u8; 1514 | } 1515 | 1516 | :PUSH.w u16 is op1_7=0x3E & size0=1 &op8_15=0xE2; u16 { 1517 | SP = SP-2; 1518 | *[near]:2 SP = u16; 1519 | } 1520 | 1521 | :PUSH.b d_eab is (op1_7=0x3A &size0=0 & op12_15=0x04) ... & d_eab { 1522 | SP = SP-1; 1523 | *[near]:1 SP = d_eab; 1524 | } 1525 | 1526 | :PUSH.w d_eaw is (op1_7=0x3A &size0=1 & op12_15=0x04) ... & d_eaw { 1527 | SP = SP-2; 1528 | *[near]:2 SP = d_eaw; 1529 | } 1530 | 1531 | :PUSH.b R0L is R0L & op4_7=0x08 & dest3_r0l_r0h=0 & bit0_2=0x02 { 1532 | SP = SP-1; 1533 | *[near]:1 SP = R0L; 1534 | } 1535 | 1536 | :PUSH.b R0H is R0H & op4_7=0x08 & dest3_r0l_r0h=1 & bit0_2=0x02 { 1537 | SP = SP-1; 1538 | *[near]:1 SP = R0H; 1539 | } 1540 | 1541 | :PUSH.w A0 is A0 & op4_7=0x0C & dest_a0_a1=0 & bit0_2=0x02 { 1542 | SP = SP-2; 1543 | *[near]:2 SP = A0; 1544 | } 1545 | 1546 | :PUSH.w A1 is A1 & op4_7=0x0C & dest_a0_a1=1 & bit0_2=0x02 { 1547 | SP = SP-2; 1548 | *[near]:2 SP = A1; 1549 | } 1550 | 1551 | _addr: dsp8[A0] is A0 & op8_11=8; dsp8 { local temp:2 = A0 + zext(dsp8:1); export temp; } 1552 | _addr: dsp8[A1] is A1 & op8_11=9; dsp8 { local temp:2 = A1 + zext(dsp8:1); export temp; } 1553 | _addr: dsp8[SB] is SB & op8_11=10; dsp8 { local temp:2 = SB + zext(dsp8:1); export temp; } 1554 | _addr: dsp8[FB] is FB & op8_11=11; dsp8 { local temp:2 = FB:2 + zext(dsp8:1); export temp; } 1555 | _addr: dsp16[A0] is A0 & op8_11=12; dsp16 { local temp:2 = A0 + dsp16:2; export temp; } 1556 | _addr: dsp16[A1] is A1 & op8_11=13; dsp16 { local temp:2 = A1 + dsp16:2; export temp; } 1557 | _addr: dsp16[FB] is FB & op8_11=14; dsp16 { local temp:2 = FB:2 + dsp16:2; export temp; } 1558 | _addr: abs16 is op8_11=15; abs16 { local temp:2 = abs16:2; export temp; } 1559 | 1560 | :PUSHA _addr is (op0_7=0x7D & op12_15=0x09) ... & _addr { 1561 | SP = SP-2; 1562 | *[near]:2 SP = _addr; 1563 | } 1564 | 1565 | :PUSHC FB is FB & op0_7=0xEB & op8_11=0x02 & ldc12_14=0x7 & bit15=0 { 1566 | SP = SP-2; 1567 | *[near]:2 SP = FB:2; 1568 | } 1569 | 1570 | :PUSHC FLAG is FLAG & op0_7=0xEB & op8_11=0x02 & ldc12_14=0x03 & bit15=0 { 1571 | SP = SP-2; 1572 | local flags = (Cflg == 1) & ((Zflg == 1) << 2) & ((Sflg == 1) << 3) & ((Bflg == 1) << 4) & ((Oflg == 1) << 5) & ((Iflg == 1) << 6) & ((Uflg == 1) << 7); 1573 | *[near]:2 SP = zext(flags); 1574 | } 1575 | 1576 | :PUSHC ldc12_14 is op0_7=0xEB & op8_11=0x02 & ldc12_14 & bit15=0 { 1577 | SP = SP-2; 1578 | *[near]:2 SP = ldc12_14; 1579 | } 1580 | 1581 | PUSHFB: FB is FB & bit8=1 {SP = SP-2; *[near]:2 SP = FB;} 1582 | PUSHFB: is bit8=0 {} 1583 | PUSHSB: SB is SB & bit8=1 {SP = SP-2; *[near]:2 SP = SB;} 1584 | PUSHSB: is bit8=0 {} 1585 | PUSHA1: A1 is A1 & bit10=1 {SP = SP-2; *[near]:2 SP = A1;} 1586 | PUSHA1: is bit10=0 {} 1587 | PUSHA0: A0 is A0 & bit11=1 {SP = SP-2; *[near]:2 SP = A0;} 1588 | PUSHA0: is bit11=0 {} 1589 | PUSHR3: R3 is R3 & bit12=1 {SP = SP-2; *[near]:2 SP = R3;} 1590 | PUSHR3: is bit12=0 {} 1591 | PUSHR2: R2 is R2 & bit13=1 {SP = SP-2; *[near]:2 SP = R2;} 1592 | PUSHR2: is bit13=0 {} 1593 | PUSHR1: R1 is R1 & bit14=1 {SP = SP-2; *[near]:2 SP = R1;} 1594 | PUSHR1: is bit14=0 {} 1595 | PUSHR0: R0 is R0 & bit15=1 {SP = SP-2; *[near]:2 SP = R0;} 1596 | PUSHR0: is bit15=0 {} 1597 | 1598 | PUSHMDISP: PUSHFB PUSHSB PUSHA1 PUSHA0 PUSHR3 PUSHR2 PUSHR1 PUSHR0 is PUSHFB & PUSHSB & PUSHA1 & PUSHA0 & PUSHR3 & PUSHR2 & PUSHR1 & PUSHR0 { 1599 | build PUSHFB; 1600 | build PUSHSB; 1601 | build PUSHA1; 1602 | build PUSHA0; 1603 | build PUSHR3; 1604 | build PUSHR2; 1605 | build PUSHR1; 1606 | build PUSHR0; 1607 | } 1608 | 1609 | :PUSHM PUSHMDISP is op0_7=0xEC & PUSHMDISP { 1610 | build PUSHMDISP; 1611 | } 1612 | 1613 | :REIT is ops0_7=0xFB { 1614 | # TODO Handle flag restoration 1615 | SP = SP+2; 1616 | local return_addr:3 = *[near]:2 SP; 1617 | SP = SP+2; 1618 | local pc_h:3 = zext(*[near]:2 SP) << 16; 1619 | return_addr = return_addr & pc_h; 1620 | return [return_addr]; 1621 | } 1622 | 1623 | #:RMPA.b is op1_7=0x3E & size0=0 & op8_15=0xF1 { 1624 | #} 1625 | # 1626 | #:RMPA.w is op1_7=0x3E & size0=1 & op8_15=0xF1 { 1627 | #} 1628 | # 1629 | #:ROLC.b d_eab is (op1_7=0x3B & size0=0 & op12_15=0x0A) ... & d_eab { 1630 | #} 1631 | 1632 | :ROLC.w d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x0A) ... & d_eaw { 1633 | local carryIn = Cflg; 1634 | local carryout = d_eaw >> 15; 1635 | Cflg = carryout:1; 1636 | d_eaw = (d_eaw << 1) | zext(carryIn); 1637 | Sflg = (d_eaw s< 0); 1638 | Zflg = (d_eaw == 0); 1639 | } 1640 | 1641 | #:RORC.b d_eab is (op1_7=0x3B & size0=0 & op12_15=0x0B) ... & d_eab { 1642 | #} 1643 | 1644 | :RORC.w d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x0B) ... & d_eaw { 1645 | local carryOut = Cflg << 15; 1646 | local carryflag = d_eaw&1; 1647 | Cflg = carryflag:1; 1648 | d_eaw = (d_eaw >> 1) | zext(carryOut); 1649 | Sflg = (d_eaw s< 0); 1650 | Zflg = (d_eaw == 0); 1651 | } 1652 | 1653 | 1654 | # TODO FLAGS 1655 | :ROT.b sha_imm12_15, d_eab is (op1_7=0x70 & size0=0 & sha_imm12_15 & bit15=0) ... & d_eab { 1656 | d_eab = (d_eab << sha_imm12_15)|(d_eab >> (8-sha_imm12_15)); 1657 | } 1658 | 1659 | :ROT.b sha_imm12_15, d_eab is (op1_7=0x70 & size0=0 & sha_imm12_15 & bit15=1) ... & d_eab { 1660 | d_eab = (d_eab << (8-sha_imm12_15))|(d_eab >> sha_imm12_15); 1661 | } 1662 | 1663 | #:ROT.w imm12_15, d_eaw is (op1_7=0x70 & size0=1 & imm12_15) ... & d_eaw { 1664 | #} 1665 | # 1666 | #:ROT.b R1H, d_eab is (R1H & op1_7=0x3A & size0=0 & op12_15=0x06) ... & d_eab { 1667 | #} 1668 | # 1669 | #:ROT.w R1H, d_eaw is (R1H & op1_7=0x3A & size0=1 & op12_15=0x06) ... & d_eaw { 1670 | #} 1671 | 1672 | 1673 | :RTS is ops0_7=0xF3 { 1674 | local return_addr:3 = *[near]:3 SP; 1675 | SP = SP+3; 1676 | return [return_addr]; 1677 | } 1678 | 1679 | 1680 | :SBB.b u8, dest8_11 is op1_7=0x3B & size0=0 & op12_15=0x07 & dest8_11 & $(DEST_IS_An); u8 { 1681 | macro_sbb16(zext(u8), dest8_11); 1682 | } 1683 | 1684 | :SBB.b u8, d_eab is (op1_7=0x3B & size0=0 & op12_15=0x07) ... & d_eab; u8 { 1685 | macro_sbb8(u8, d_eab); 1686 | } 1687 | 1688 | :SBB.w u16, d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x07) ... & d_eaw; u16 { 1689 | macro_sbb16(u16, d_eaw); 1690 | } 1691 | 1692 | :SBB.b s_eab, dest8_11 is (op1_7=0x5C & size0=0 &src12_15 & dest8_11 & $(DEST_IS_An)) ... & s_eab { 1693 | macro_sbb16(zext(s_eab), dest8_11); 1694 | } 1695 | 1696 | :SBB.b s_eab1, d_eab1 is op1_7=0x5C & size0=0 & $(SRCDEST8) { 1697 | macro_sbb8(s_eab1, d_eab1); 1698 | } 1699 | 1700 | :SBB.w s_eaw1, d_eaw1 is op1_7=0x5C & size0=1 &$(SRCDEST16) { 1701 | macro_sbb16(s_eaw1, d_eaw1); 1702 | } 1703 | 1704 | #:SBJNZ 1705 | #:SHA 1706 | 1707 | # TODO C Flag 1708 | :SHA.w sha_imm12_15, d_eaw is (op1_7=0x78 & size0=1 & sha_imm12_15 &bit15=0) ... & d_eaw { 1709 | d_eaw = d_eaw << sha_imm12_15; 1710 | Sflg = (d_eaw s< 0); 1711 | Zflg = (d_eaw == 0); 1712 | } 1713 | 1714 | # TODO C Flag 1715 | :SHA.w sha_imm12_15, d_eaw is (op1_7=0x78 & size0=1 & sha_imm12_15 &bit15=1) ... & d_eaw { 1716 | d_eaw = d_eaw s>> sha_imm12_15; 1717 | Sflg = (d_eaw s< 0); 1718 | Zflg = (d_eaw == 0); 1719 | } 1720 | 1721 | # TODO C Flag 1722 | :SHL.b sha_imm12_15, d_eab is (op1_7=0x74 & size0=0 & sha_imm12_15) ... & d_eab { 1723 | d_eab = d_eab << sha_imm12_15; 1724 | Sflg = (d_eab s< 0); 1725 | Zflg = (d_eab == 0); 1726 | } 1727 | 1728 | # TODO C Flag 1729 | :SHL.w sha_imm12_15, d_eaw is (op1_7=0x74 & size0=1 & sha_imm12_15) ... & d_eaw { 1730 | d_eaw = d_eaw << sha_imm12_15; 1731 | Sflg = (d_eaw s< 0); 1732 | Zflg = (d_eaw == 0); 1733 | } 1734 | 1735 | # TODO C Flag 1736 | :SHL.b R1H, d_eab is (R1H & op1_7=0x3A & size0=0 & op12_15=0x0E) ... & d_eab { 1737 | d_eab = d_eab << R1H; 1738 | Sflg = (d_eab s< 0); 1739 | Zflg = (d_eab == 0); 1740 | } 1741 | 1742 | # TODO C Flag 1743 | :SHL.w R1H, d_eaw is (R1H & op1_7=0x3A & size0=1 & op12_15=0x0E) ... & d_eaw { 1744 | d_eaw = d_eaw << R1H; 1745 | Sflg = (d_eaw s< 0); 1746 | Zflg = (d_eaw == 0); 1747 | } 1748 | 1749 | :SHL.l shl_imm8_11, R2R0 is R2R0 & op0_7=0xEB & op12_15=0x08 & shl_imm8_11 { 1750 | R2R0 = R2R0 << shl_imm8_11; 1751 | } 1752 | 1753 | :SHL.l shl_imm8_11, R3R1 is R3R1 & op0_7=0xEB & op12_15=0x09 & shl_imm8_11 { 1754 | R3R1 = R3R1 << shl_imm8_11; 1755 | } 1756 | 1757 | :SHL.l R1H, R2R0 is R1H & R2R0 & op0_7=0xEB & op12_15=0x0 & shl_imm8_11 { 1758 | R2R0 = R2R0 << R1H; 1759 | } 1760 | 1761 | :SHL.l R1H, R3R1 is R1H & R3R1 & op0_7=0xEB & op12_15=0x01 & shl_imm8_11 { 1762 | R3R1 = R3R1 << R1H; 1763 | } 1764 | 1765 | 1766 | 1767 | :SMOVF.b is op1_7=0x3E & size0=0 & op8_15=0xE8 { 1768 | local dest_addr:2 = A1; 1769 | local src_addr:4 = (zext(R1H) << 16) | zext(A0); 1770 | 1771 | if(R3 == 0) goto ; 1772 | *[near]:1 dest_addr = *:1 src_addr; 1773 | dest_addr = dest_addr+1; 1774 | src_addr = src_addr+1; 1775 | R3 = R3-1; 1776 | goto ; 1777 | 1778 | A1 = dest_addr; 1779 | local tmp = src_addr >> 16; 1780 | R1H = tmp:1; 1781 | A0 = src_addr:2; 1782 | } 1783 | 1784 | :SMOVF.w is op1_7=0x3E & size0=1 & op8_15=0xE8 { 1785 | local dest_addr:2 = A1; 1786 | local src_addr:4 = (zext(R1H) << 16) | zext(A0); 1787 | 1788 | if(R3 == 0) goto ; 1789 | *[near]:2 dest_addr = *:2 src_addr; 1790 | dest_addr = dest_addr+2; 1791 | src_addr = src_addr+2; 1792 | R3 = R3-1; 1793 | goto ; 1794 | 1795 | A1 = dest_addr; 1796 | local tmp = src_addr >> 16; 1797 | R1H = tmp:1; 1798 | A0 = src_addr:2; 1799 | } 1800 | 1801 | :SSTR.b is op1_7=0x3E & size0=0 & op8_15=0xEA { 1802 | local addr:2 = A1; 1803 | 1804 | if(R3 == 0) goto ; 1805 | *[near]:1 addr = R0L; 1806 | addr = addr+1; 1807 | R3 = R3-1; 1808 | goto ; 1809 | 1810 | A1 = addr; 1811 | } 1812 | 1813 | :SSTR.w is op1_7=0x3E & size0=1 & op8_15=0xEA { 1814 | local addr:2 = A1; 1815 | 1816 | if(R3 == 0) goto ; 1817 | *[near]:2 addr = R0; 1818 | addr = addr+2; 1819 | R3 = R3-1; 1820 | goto ; 1821 | 1822 | A1 = addr; 1823 | } 1824 | 1825 | :STC FB, d_eaw is (FB & op0_7=0x7B & bit15=1 & ldc12_14=0x07) ... & d_eaw { 1826 | d_eaw = FB:2; 1827 | } 1828 | 1829 | :STC ldc12_14, d_eaw is (op0_7=0x7B & bit15=1 & ldc12_14) ... & d_eaw { 1830 | d_eaw = ldc12_14; 1831 | } 1832 | 1833 | # TODO: Implement this? 1834 | define pcodeop STORE_CONTEXT; 1835 | 1836 | :STCTX abs16, abs20 is op0_15=0xF07D; abs16; abs20 { 1837 | STORE_CONTEXT(abs16:2, abs20:3); 1838 | } 1839 | 1840 | 1841 | :STE.b dest8_11, abs20 is op1_7=0x3A & size0=0 & op12_15=0x00 & dest8_11 & $(DEST_IS_An); abs20 { 1842 | local addr:4 = zext(abs20:3); 1843 | *:1 addr = dest8_11:1; 1844 | Sflg = (dest8_11 s< 0); 1845 | Zflg = (dest8_11 == 0); 1846 | } 1847 | 1848 | :STE.b d_eab, abs20 is (op1_7=0x3A & size0=0 & op12_15=0x00) ... & d_eab; abs20 { 1849 | local addr:4 = zext(abs20:3); 1850 | *:1 addr = d_eab:1; 1851 | Sflg = (d_eab s< 0); 1852 | Zflg = (d_eab == 0); 1853 | } 1854 | 1855 | :STE.w d_eaw, abs20 is (op1_7=0x3A & size0=1 & op12_15=0x00) ... & d_eaw; abs20 { 1856 | local addr:4 = zext(abs20:3); 1857 | *:2 addr = d_eaw; 1858 | Sflg = (d_eaw s< 0); 1859 | Zflg = (d_eaw == 0); 1860 | } 1861 | 1862 | :STE.b dest8_11, addr is op1_7=0x3A & size0=0 & op12_15=0x01 & dest8_11 & $(DEST_IS_An); abs20 [addr = A0+abs20;] { 1863 | *:1 addr:4 = dest8_11:1; 1864 | Sflg = (dest8_11 s< 0); 1865 | Zflg = (dest8_11 == 0); 1866 | } 1867 | 1868 | :STE.b d_eab, addr is (op1_7=0x3A & size0=0 & op12_15=0x01) ... & d_eab; abs20 [addr = A0+abs20;] { 1869 | *:1 addr:4 = d_eab:1; 1870 | Sflg = (d_eab s< 0); 1871 | Zflg = (d_eab == 0); 1872 | } 1873 | 1874 | :STE.w d_eaw, addr is (op1_7=0x3A & size0=1 & op12_15=0x01) ... & d_eaw; abs20 [addr = A0+abs20;] { 1875 | *:2 addr:4 = d_eaw; 1876 | Sflg = (d_eaw s< 0); 1877 | Zflg = (d_eaw == 0); 1878 | } 1879 | 1880 | :STE.b dest8_11, A1A0 is A1A0 & op1_7=0x3A & size0=0 & op12_15=0x02 & dest8_11 & $(DEST_IS_An) { 1881 | *:1 A1A0 = dest8_11:1; 1882 | Sflg = (dest8_11 s< 0); 1883 | Zflg = (dest8_11 == 0); 1884 | } 1885 | 1886 | :STE.b d_eab, A1A0 is (A1A0 & op1_7=0x3A & size0=0 & op12_15=0x02) ... & d_eab { 1887 | *:1 A1A0 = d_eab:1; 1888 | Sflg = (d_eab s< 0); 1889 | Zflg = (d_eab == 0); 1890 | } 1891 | 1892 | :STE.w d_eaw, A1A0 is (A1A0 &op1_7=0x3A & size0=1 & op12_15=0x02) ... & d_eaw { 1893 | *:2 A1A0 = d_eaw; 1894 | Sflg = (d_eaw s< 0); 1895 | Zflg = (d_eaw == 0); 1896 | } 1897 | 1898 | :STNZ imm8_15, d_imm is (op3_7_imm8=0x1A & imm8_15 ) ... & d_imm { 1899 | if (Zflg) goto ; 1900 | d_imm = imm8_15; 1901 | 1902 | } 1903 | 1904 | :STZ imm8_15, d_imm is (op3_7_imm8=0x19 & imm8_15 ) ... & d_imm { 1905 | if (!Zflg) goto ; 1906 | d_imm = imm8_15; 1907 | 1908 | } 1909 | 1910 | :STZX imm8_15, imm8, d_imm is (op3_7_imm8=0x1b & imm8_15) ... & d_imm; imm8 { 1911 | if (Zflg) goto ; 1912 | if (!Zflg) goto ; 1913 | 1914 | d_imm = imm8_15; 1915 | goto ; 1916 | 1917 | d_imm = imm8; 1918 | 1919 | } 1920 | 1921 | 1922 | :SUB.b u8, dest8_11 is op1_7=0x3B & size0=0 & op12_15=0x05 & dest8_11 & $(DEST_IS_An); u8 { 1923 | macro_sub(zext(u8), dest8_11); 1924 | } 1925 | 1926 | :SUB.b u8, d_eab is (op1_7=0x3B & size0=0 & op12_15=0x05) ... & d_eab; u8 { 1927 | macro_sub(u8, d_eab); 1928 | } 1929 | 1930 | :SUB.w u16, d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x05) ... & d_eaw; u16 { 1931 | macro_sub(u16, d_eaw); 1932 | } 1933 | 1934 | 1935 | :SUB.b imm8_15, d_imm is (op3_7_imm8=0x11 & imm8_15) ... & d_imm { 1936 | macro_sub(imm8_15, d_imm); 1937 | } 1938 | 1939 | 1940 | :SUB.b s_eab, dest8_11 is (op1_7=0x54 & size0=0 &src12_15 & dest8_11 & $(DEST_IS_An)) ... & s_eab { 1941 | macro_sub(zext(s_eab), dest8_11); 1942 | } 1943 | 1944 | :SUB.b s_eab1, d_eab1 is op1_7=0x54 & size0=0 & $(SRCDEST8) { 1945 | macro_sub(s_eab1, d_eab1); 1946 | } 1947 | 1948 | :SUB.w s_eaw1, d_eaw1 is op1_7=0x54 & size0=1 &$(SRCDEST16) { 1949 | macro_sub(s_eaw1, d_eaw1); 1950 | } 1951 | 1952 | :SUB.b SRC2, dest2_2 is (op=0x05 & dest2_2) ... & SRC2 { 1953 | macro_sub(SRC2, dest2_2); 1954 | } 1955 | 1956 | :TST.b u8, dest8_11 is op0_7=0x76 & op12_15=0 & dest8_11 & (dest8_11=4|dest8_11=5); u8 { 1957 | local tmp = dest8_11 & zext(u8); 1958 | Sflg = (tmp s< 0); 1959 | Zflg = (tmp == 0); 1960 | } 1961 | 1962 | # TODO, need to handle special case when comparing A0/A1 1963 | :TST.b u8, d_eab is (op0_7=0x76 & op12_15=0) ...& d_eab; u8 { 1964 | local tmp = d_eab & u8; 1965 | Sflg = (tmp s< 0); 1966 | Zflg = (tmp == 0); 1967 | } 1968 | 1969 | :TST.w u16, d_eaw is (op1_7=0x3B & size0=1 & op12_15=0) ... & d_eaw ; u16 { 1970 | local tmp = d_eaw & u16; 1971 | Sflg = (tmp s< 0); 1972 | Zflg = (tmp == 0); 1973 | } 1974 | 1975 | :TST.b s_eab, dest8_11 is (op1_7=0x40 & size0=0 & dest8_11 & $(DEST_IS_An)) ... & s_eab { 1976 | local tmp = dest8_11 & zext(s_eab); 1977 | Sflg = (tmp s< 0); 1978 | Zflg = (tmp == 0); 1979 | } 1980 | 1981 | 1982 | :TST.b s_eab1, d_eab1 is op1_7=0x40 & size0=0 &$(SRCDEST8) { 1983 | local tmp = d_eab1 & s_eab1; 1984 | Sflg = (tmp s< 0); 1985 | Zflg = (tmp == 0); 1986 | } 1987 | 1988 | :TST.w s_eaw1, d_eaw1 is op1_7=0x40 & size0=1 & $(SRCDEST16) { 1989 | local tmp = d_eaw1 & s_eaw1; 1990 | Sflg = (tmp s< 0); 1991 | Zflg = (tmp == 0); 1992 | } 1993 | 1994 | 1995 | :XCHG srcb12_13, dest8_11 is op1_7=0x3D & size0=0 & bit15=0 & bit14=0 & srcb12_13 & dest8_11 & $(DEST_IS_An) { 1996 | local temp:1 = dest8_11:1; 1997 | dest8_11 = zext(srcb12_13:1); 1998 | srcb12_13 = temp; 1999 | } 2000 | 2001 | :XCHG srcb12_13, d_eab is (op1_7=0x3D & size0=0 & bit15=0 & bit14=0 & srcb12_13) ... & d_eab { 2002 | local temp:1 = d_eab; 2003 | d_eab = srcb12_13; 2004 | srcb12_13 = temp; 2005 | } 2006 | 2007 | :XCHG srcw12_13, d_eaw is (op1_7=0x3D & size0=1 & bit15=0 & bit14=0 & srcw12_13) ... & d_eaw { 2008 | local temp:2 = d_eaw; 2009 | d_eaw= srcw12_13; 2010 | srcw12_13 = temp; 2011 | } 2012 | 2013 | 2014 | :XOR.b u8, dest8_11 is op1_7=0x3B & size0=0 & op12_15=0x01 & dest8_11 & $(DEST_IS_An); u8 { 2015 | dest8_11 = dest8_11 ^ zext(u8:1); 2016 | Zflg = (dest8_11 == 0); 2017 | Sflg = (dest8_11 s< 0); 2018 | } 2019 | 2020 | :XOR.b u8, d_eab is (op1_7=0x3B & size0=0 & op12_15=0x01) ... & d_eab; u8 { 2021 | d_eab = d_eab ^ u8; 2022 | Zflg = (d_eab == 0); 2023 | Sflg = (d_eab s< 0); 2024 | } 2025 | 2026 | :XOR.w u16, d_eaw is (op1_7=0x3B & size0=1 & op12_15=0x01) ... & d_eaw; u16 { 2027 | d_eaw = d_eaw ^ u16; 2028 | Zflg = (d_eaw == 0); 2029 | Sflg = (d_eaw s< 0); 2030 | } 2031 | 2032 | :XOR.b s_eab, dest8_11 is op1_7=0x44 & size0=0 & op12_15=0x01 & dest8_11 & $(DEST_IS_An); s_eab { 2033 | dest8_11 = dest8_11 ^ zext(s_eab:1); 2034 | Zflg = (dest8_11 == 0); 2035 | Sflg = (dest8_11 s< 0); 2036 | } 2037 | 2038 | :XOR.b s_eab1, d_eab1 is op1_7=0x44 & size0=0 & $(SRCDEST8) { 2039 | d_eab1 = d_eab1 ^ s_eab1; 2040 | Zflg = (d_eab1 == 0); 2041 | Sflg = (d_eab1 s< 0); 2042 | } 2043 | 2044 | :XOR.w s_eaw1, d_eaw1 is op1_7=0x44 & size0=1 & $(SRCDEST16) { 2045 | d_eaw1 = d_eaw1 ^ s_eaw1; 2046 | Zflg = (d_eaw1 == 0); 2047 | Sflg = (d_eaw1 s< 0); 2048 | } 2049 | 2050 | -------------------------------------------------------------------------------- /data/languages/sfrs.txt: -------------------------------------------------------------------------------- 1 | pm0 0x4 l 2 | pm1 0x5 l 3 | cm0 0x6 l 4 | cm1 0x7 l 5 | prcr 0xa l 6 | cm2 0xc l 7 | prg2c 0x10 l 8 | pclkr 0x12 l 9 | cpsrf 0x15 l 10 | rstfr 0x18 l 11 | vcr1 0x19 l 12 | vcr2 0x1a l 13 | plc0 0x1c l 14 | pm2 0x1e l 15 | vwce 0x26 l 16 | vd2ls 0x28 l 17 | vw0c 0x2a l 18 | vw2c 0x2c l 19 | e2fic 0x41 l 20 | int7ic 0x42 l 21 | int6ic 0x43 l 22 | int3ic 0x44 l 23 | tb5ic 0x45 l 24 | tb4ic 0x46 l 25 | tb3ic 0x47 l 26 | int5ic 0x48 l 27 | int4ic 0x49 l 28 | bcnic 0x4a l 29 | dm0ic 0x4b l 30 | dm1ic 0x4c l 31 | kupic 0x4d l 32 | s2tic 0x4f l 33 | s2ric 0x50 l 34 | s0tic 0x51 l 35 | s0ric 0x52 l 36 | s1tic 0x53 l 37 | s1ric 0x54 l 38 | ta0ic 0x55 l 39 | ta1ic 0x56 l 40 | ta2ic 0x57 l 41 | ta3ic 0x58 l 42 | ta4ic 0x59 l 43 | tb0ic 0x5a l 44 | tb1ic 0x5b l 45 | tb2ic 0x5c l 46 | int0ic 0x5d l 47 | int1ic 0x5e l 48 | int2ic 0x5f l 49 | dm2ic 0x69 l 50 | dm3ic 0x6a l 51 | c1ric 0x6b l 52 | c1tic 0x6c l 53 | c1fric 0x6d l 54 | c1ftic 0x6e l 55 | s4tic 0x6f l 56 | s4ric 0x70 l 57 | c0wic 0x71 l 58 | s3tic 0x72 l 59 | s3ric 0x73 l 60 | c1eic 0x74 l 61 | c0ric 0x75 l 62 | c0tic 0x76 l 63 | c0fric 0x77 l 64 | c0ftic 0x78 l 65 | e2fa 0x80 l 66 | e2fah 0x82 l 67 | e2fi 0x88 l 68 | e2fd 0x8c l 69 | e2fm 0x90 l 70 | e2fc 0x92 l 71 | e2fs1 0x94 l 72 | e2fs0 0xa1 l 73 | lbrp0 0x162 l 74 | lbrp1 0x163 l 75 | lpc 0x165 l 76 | l0md 0x168 l 77 | l0brk 0x169 l 78 | l0spc 0x16a l 79 | l0ie 0x16c l 80 | l0ede 0x16d l 81 | l0c 0x16e l 82 | l0tc 0x170 l 83 | l0mst 0x171 l 84 | l0st 0x172 l 85 | l0est 0x173 l 86 | l0rfc 0x174 l 87 | l0idb 0x175 l 88 | l0cb 0x176 l 89 | l0db1 0x178 l 90 | l0db2 0x179 l 91 | l0db3 0x17a l 92 | l0db4 0x17b l 93 | l0db5 0x17c l 94 | l0db6 0x17d l 95 | l0db7 0x17e l 96 | l0db8 0x17f l 97 | sar0 0x180 l 98 | sar0m 0x181 l 99 | sar0h 0x182 l 100 | dar0 0x184 l 101 | dar0m 0x185 l 102 | dar0h 0x186 l 103 | tcr0 0x188 l 104 | tcr0h 0x189 l 105 | dm0con 0x18c l 106 | sar1 0x190 l 107 | sar1m 0x191 l 108 | sar1h 0x192 l 109 | dar1 0x194 l 110 | dar1m 0x195 l 111 | dar1h 0x196 l 112 | tcr1 0x198 l 113 | tcr1h 0x199 l 114 | dm1con 0x19c l 115 | sar2 0x1a0 l 116 | sar2m 0x1a1 l 117 | sar2h 0x1a2 l 118 | dar2 0x1a4 l 119 | dar2m 0x1a5 l 120 | dar2h 0x1a6 l 121 | tcr2 0x1a8 l 122 | tcr2h 0x1a9 l 123 | dm2con 0x1ac l 124 | sar3 0x1b0 l 125 | sar3m 0x1b1 l 126 | sar3h 0x1b2 l 127 | dar3 0x1b4 l 128 | dar3m 0x1b5 l 129 | dar3h 0x1b6 l 130 | tcr3 0x1b8 l 131 | tcr3h 0x1b9 l 132 | dm3con 0x1bc l 133 | tbcs0 0x1c8 l 134 | tbcs1 0x1c9 l 135 | tckdivc0 0x1cb l 136 | tacs0 0x1d0 l 137 | tacs1 0x1d1 l 138 | tacs2 0x1d2 l 139 | tapofs 0x1d5 l 140 | taow 0x1d8 l 141 | tbcs2 0x1e8 l 142 | tbcs3 0x1e9 l 143 | tmos 0x1f0 l 144 | tmossr 0x1f2 l 145 | tmoscs 0x1f3 l 146 | tmospr 0x1f4 l 147 | ifsr4a 0x204 l 148 | ifsr3a 0x205 l 149 | ifsr2a 0x206 l 150 | ifsr 0x207 l 151 | aier 0x20e l 152 | aier2 0x20f l 153 | rmad0 0x210 l 154 | rmad0m 0x211 l 155 | rmad0h 0x212 l 156 | rmad1 0x214 l 157 | rmad1m 0x215 l 158 | rmad1h 0x216 l 159 | rmad2 0x218 l 160 | rmad2m 0x219 l 161 | rmad2h 0x21a l 162 | rmad3 0x21c l 163 | rmad3m 0x21d l 164 | rmad3h 0x21e l 165 | fmr0 0x220 l 166 | fmr1 0x221 l 167 | fmr2 0x222 l 168 | fmr3 0x223 l 169 | fmr6 0x230 l 170 | u0brg 0x249 l 171 | u0tb 0x24a l 172 | u0tbh 0x24b l 173 | u0rb 0x24e l 174 | u0rbh 0x24f l 175 | uclksel0 0x252 l 176 | u1brg 0x259 l 177 | u1tb 0x25a l 178 | u1tbh 0x25b l 179 | u1rb 0x25e l 180 | u1rbh 0x25f l 181 | u2smr4 0x264 l 182 | u2smr3 0x265 l 183 | u2smr2 0x266 l 184 | u2smr 0x267 l 185 | u2brg 0x269 l 186 | u2tb 0x26a l 187 | u2tbh 0x26b l 188 | u2rb 0x26e l 189 | u2rbh 0x26f l 190 | u4brg 0x299 l 191 | u4tb 0x29a l 192 | u4tbh 0x29b l 193 | u4rb 0x29e l 194 | u4rbh 0x29f l 195 | u3brg 0x2a9 l 196 | u3tb 0x2aa l 197 | u3tbh 0x2ab l 198 | u3rb 0x2ae l 199 | u3rbh 0x2af l 200 | s00 0x2b0 l 201 | s0d0 0x2b2 l 202 | s1d0 0x2b3 l 203 | s20 0x2b4 l 204 | s3d0 0x2b6 l 205 | s4d0 0x2b7 l 206 | s10 0x2b8 l 207 | s11 0x2b9 l 208 | s0d1 0x2ba l 209 | s0d2 0x2bb l 210 | g1tm0 0x2c0 l 211 | g1tm1 0x2c2 l 212 | g1tm2 0x2c4 l 213 | g1tm3 0x2c6 l 214 | g1tm4 0x2c8 l 215 | g1tm5 0x2ca l 216 | g1tm6 0x2cc l 217 | g1tm7 0x2ce l 218 | g1pocr0 0x2d0 l 219 | g1pocr1 0x2d1 l 220 | g1pocr2 0x2d2 l 221 | g1pocr3 0x2d3 l 222 | g1pocr4 0x2d4 l 223 | g1pocr5 0x2d5 l 224 | g1pocr6 0x2d6 l 225 | g1pocr7 0x2d7 l 226 | g1tmcr0 0x2d8 l 227 | g1tmcr1 0x2d9 l 228 | g1tmcr2 0x2da l 229 | g1tmcr3 0x2db l 230 | g1tmcr4 0x2dc l 231 | g1tmcr5 0x2dd l 232 | g1tmcr6 0x2de l 233 | g1tmcr7 0x2df l 234 | g1bt 0x2e0 l 235 | g1bcr0 0x2e2 l 236 | g1bcr1 0x2e3 l 237 | g1tpr6 0x2e4 l 238 | g1tpr7 0x2e5 l 239 | g1fe 0x2e6 l 240 | g1fs 0x2e7 l 241 | g1btrr 0x2e8 l 242 | g1dv 0x2ea l 243 | g1oer 0x2ec l 244 | g1ir 0x2f0 l 245 | g1ie0 0x2f1 l 246 | g1ie1 0x2f2 l 247 | nddr 0x2fe l 248 | p17ddr 0x2ff l 249 | dtt 0x30c l 250 | ictb2 0x30d l 251 | tb3 0x310 l 252 | tb4 0x312 l 253 | tb5 0x314 l 254 | pfcr 0x318 l 255 | tb3mr 0x31b l 256 | tb4mr 0x31c l 257 | tb5mr 0x31d l 258 | tabsr 0x320 l 259 | trgsr 0x323 l 260 | ta0 0x326 l 261 | ta1 0x328 l 262 | ta2 0x32a l 263 | ta3 0x32c l 264 | ta4 0x32e l 265 | tb0 0x330 l 266 | tb1 0x332 l 267 | tb2 0x334 l 268 | ta0mr 0x336 l 269 | ta1mr 0x337 l 270 | ta2mr 0x338 l 271 | ta3mr 0x339 l 272 | ta4mr 0x33a l 273 | tb0mr 0x33b l 274 | tb1mr 0x33c l 275 | tb2mr 0x33d l 276 | tb2sc 0x33e l 277 | ss0br 0x353 l 278 | ss0tdr 0x354 l 279 | ss0tdrh 0x355 l 280 | ss0rdr 0x356 l 281 | ss0rdrh 0x357 l 282 | ss0crh 0x358 l 283 | ss0crl 0x359 l 284 | ss0mr 0x35a l 285 | ss0er 0x35b l 286 | ss0sr 0x35c l 287 | ss0mr2 0x35d l 288 | pcr 0x366 l 289 | vlt0 0x36c l 290 | vlt1 0x36d l 291 | vlt2 0x36e l 292 | pacr 0x370 l 293 | cspr 0x37c l 294 | wdtr 0x37d l 295 | wdts 0x37e l 296 | wdc 0x37f l 297 | dm2sl 0x390 l 298 | dm3sl 0x392 l 299 | dm0sl 0x398 l 300 | dm1sl 0x39a l 301 | crcsar 0x3b4 l 302 | crcsarh 0x3b5 l 303 | crcmr 0x3b6 l 304 | crcd 0x3bc l 305 | crcdh 0x3bd l 306 | crcin 0x3be l 307 | p0 0x3e0 l 308 | p1 0x3e1 l 309 | pd0 0x3e2 l 310 | pd1 0x3e3 l 311 | p2 0x3e4 l 312 | p3 0x3e5 l 313 | pd2 0x3e6 l 314 | pd3 0x3e7 l 315 | p4 0x3e8 l 316 | p5 0x3e9 l 317 | pd4 0x3ea l 318 | pd5 0x3eb l 319 | p6 0x3ec l 320 | p7 0x3ed l 321 | pd6 0x3ee l 322 | pd7 0x3ef l 323 | p8 0x3f0 l 324 | p9 0x3f1 l 325 | pd8 0x3f2 l 326 | pd9 0x3f3 l 327 | p10 0x3f4 l 328 | pd10 0x3f6 l 329 | c1mb0 0xd200 l 330 | c1mb1 0xd210 l 331 | c1mb2 0xd220 l 332 | c1mb3 0xd230 l 333 | c1mb4 0xd240 l 334 | c1mb5 0xd250 l 335 | c1mb6 0xd260 l 336 | c1mb7 0xd270 l 337 | c1mb8 0xd280 l 338 | c1mb9 0xd290 l 339 | c1mb10 0xd2a0 l 340 | c1mb11 0xd2b0 l 341 | c1mb12 0xd2c1 l 342 | c1mb13 0xd2d0 l 343 | c1mb14 0xd2e0 l 344 | c1mb15 0xd2f0 l 345 | c1mb16 0xd300 l 346 | c1mb17 0xd310 l 347 | c1mb18 0xd320 l 348 | c1mb19 0xd330 l 349 | c1mb20 0xd340 l 350 | c1mb21 0xd350 l 351 | c1mb22 0xd360 l 352 | c1mb23 0xd370 l 353 | c1mb24 0xd380 l 354 | c1mb25 0xd390 l 355 | c1mb26 0xd3a0 l 356 | c1mb27 0xd3b0 l 357 | c1mb28 0xd3c1 l 358 | c1mb29 0xd3d0 l 359 | c1mb30 0xd3e0 l 360 | c1mb31 0xd3f0 l 361 | c1mkr0 0xd400 l 362 | c1mkr1 0xd404 l 363 | c1mkr2 0xd408 l 364 | c1mkr3 0xd40c l 365 | c1mkr4 0xd410 l 366 | c1mkr5 0xd414 l 367 | c1mkr6 0xd418 l 368 | c1mkr7 0xd41c l 369 | c1fidcr0 0xd420 l 370 | c1fidcr1 0xd424 l 371 | c1mkivlr 0xd428 l 372 | c1mier0 0xd42c l 373 | c1mier1 0xd42d l 374 | c1mier3 0xd42e l 375 | c1mier4 0xd42f l 376 | c1mctl0 0xd4a0 l 377 | c1mctl1 0xd4a1 l 378 | c1mctl2 0xd4a2 l 379 | c1mctl3 0xd4a3 l 380 | c1mctl4 0xd4a4 l 381 | c1mctl5 0xd4a5 l 382 | c1mctl6 0xd4a6 l 383 | c1mctl7 0xd4a7 l 384 | c1mctl8 0xd4a8 l 385 | c1mctl9 0xd4a9 l 386 | c1mctl10 0xd4aa l 387 | c1mctl11 0xd4ab l 388 | c1mctl12 0xd4ac l 389 | c1mctl13 0xd4ad l 390 | c1mctl14 0xd4ae l 391 | c1mctl15 0xd4af l 392 | c1mctl16 0xd4b0 l 393 | c1mctl17 0xd4b1 l 394 | c1mctl18 0xd4b2 l 395 | c1mctl19 0xd4b3 l 396 | c1mctl20 0xd4b4 l 397 | c1mctl21 0xd4b5 l 398 | c1mctl22 0xd4b6 l 399 | c1mctl23 0xd4b7 l 400 | c1mctl24 0xd4b8 l 401 | c1mctl25 0xd4b9 l 402 | c1mctl26 0xd4ba l 403 | c1mctl27 0xd4bb l 404 | c1mctl28 0xd4bc l 405 | c1mctl29 0xd4bd l 406 | c1mctl30 0xd4be l 407 | c1mctl31 0xd4bf l 408 | c1ctlr 0xd4c0 l 409 | c1str 0xd4c2 l 410 | c1strh 0xd4c3 l 411 | c1bcr0 0xd4c4 l 412 | c1bcr1 0xd4c5 l 413 | c1bcr2 0xd4c6 l 414 | c1clkr 0xd4c7 l 415 | c1rfcr 0xd4c8 l 416 | c1rfpcr 0xd4c9 l 417 | c1tfcr 0xd4ca l 418 | c1tfpcr 0xd4cb l 419 | c1eier 0xd4cc l 420 | c1eifr 0xd4cd l 421 | c1recr 0xd4ce l 422 | c1tecr 0xd4cf l 423 | c1ecsr 0xd4d0 l 424 | c1cssr 0xd4d1 l 425 | c1mssr 0xd4d2 l 426 | c1msmr 0xd4d3 l 427 | c1tsr 0xd4d4 l 428 | c1afsr 0xd4d6 l 429 | c1afsrh 0xd4d7 l 430 | c1tcr 0xd4d8 l 431 | c0mb0 0xd500 l 432 | c0mb1 0xd510 l 433 | c0mb2 0xd520 l 434 | c0mb3 0xd530 l 435 | c0mb4 0xd540 l 436 | c0mb5 0xd550 l 437 | c0mb6 0xd560 l 438 | c0mb7 0xd570 l 439 | c0mb8 0xd580 l 440 | c0mb9 0xd590 l 441 | c0mb10 0xd5a0 l 442 | c0mb11 0xd5b0 l 443 | c0mb12 0xd5c0 l 444 | c0mb13 0xd5d0 l 445 | c0mb14 0xd5e0 l 446 | c0mb15 0xd5f0 l 447 | c0mb16 0xd600 l 448 | c0mb17 0xd610 l 449 | c0mb18 0xd620 l 450 | c0mb19 0xd630 l 451 | c0mb20 0xd640 l 452 | c0mb21 0xd650 l 453 | c0mb22 0xd660 l 454 | c0mb23 0xd670 l 455 | c0mb24 0xd680 l 456 | c0mb25 0xd690 l 457 | c0mb26 0xd6a0 l 458 | c0mb27 0xd6b0 l 459 | c0mb28 0xd6c0 l 460 | c0mb29 0xd6d0 l 461 | c0mb30 0xd6e0 l 462 | c0mb31 0xd6f0 l 463 | c0mkr0 0xd700 l 464 | c0mkr1 0xd704 l 465 | c0mkr2 0xd708 l 466 | c0mkr3 0xd70c l 467 | c0mkr4 0xd710 l 468 | c0mkr5 0xd714 l 469 | c0mkr6 0xd718 l 470 | c0mkr7 0xd71c l 471 | c0fidcr0 0xd720 l 472 | c0fidcr1 0xd724 l 473 | c0mkivlr 0xd728 l 474 | c0mier 0xd72c l 475 | c0mctl0 0xd7a0 l 476 | c0mctl1 0xd7a1 l 477 | c0mctl2 0xd7a2 l 478 | c0mctl3 0xd7a3 l 479 | c0mctl4 0xd7a4 l 480 | c0mctl5 0xd7a5 l 481 | c0mctl6 0xd7a6 l 482 | c0mctl7 0xd7a7 l 483 | c0mctl8 0xd7a8 l 484 | c0mctl9 0xd7a9 l 485 | c0mctl10 0xd7aa l 486 | c0mctl11 0xd7ab l 487 | c0mctl12 0xd7ac l 488 | c0mctl13 0xd7ad l 489 | c0mctl14 0xd7ae l 490 | c0mctl15 0xd7af l 491 | c0mctl16 0xd7b0 l 492 | c0mctl17 0xd7b1 l 493 | c0mctl18 0xd7b2 l 494 | c0mctl19 0xd7b3 l 495 | c0mctl20 0xd7b4 l 496 | c0mctl21 0xd7b5 l 497 | c0mctl22 0xd7b6 l 498 | c0mctl23 0xd7b7 l 499 | c0mctl24 0xd7b8 l 500 | c0mctl25 0xd7b9 l 501 | c0mctl26 0xd7ba l 502 | c0mctl27 0xd7bb l 503 | c0mctl28 0xd7bc l 504 | c0mctl29 0xd7bd l 505 | c0mctl30 0xd7be l 506 | c0mctl31 0xd7bf l 507 | c0ctlr 0xd7c0 l 508 | c0str 0xd7c2 l 509 | c0strh 0xd7c3 l 510 | c0bcr 0xd7c4 l 511 | c0clkr 0xd7c7 l 512 | c0rfcr 0xd7c8 l 513 | c0rfpcr 0xd7c9 l 514 | c0tfcr 0xd7ca l 515 | c0tfpcr 0xd7cb l 516 | c0eier 0xd7cc l 517 | c0eifr 0xd7cd l 518 | c0recr 0xd7ce l 519 | c0tecr 0xd7cf l 520 | c0ecsr 0xd7d0 l 521 | c0cssr 0xd7d1 l 522 | c0mssr 0xd7d2 l 523 | c0msmr 0xd7d3 l 524 | c0tsr 0xd7d4 l 525 | c0afsr 0xd7d6 l 526 | c0afsrh 0xd7d7 l -------------------------------------------------------------------------------- /data/languages/test.sla: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 67 | 68 | 69 | 70 | 71 | 72 | 73 | 74 | 75 | 76 | 77 | 78 | 79 | 80 | 81 | 82 | 83 | 84 | 85 | 86 | 87 | 88 | 89 | 90 | 91 | 92 | 93 | 94 | 95 | 96 | 97 | 98 | 99 | 100 | 101 | 102 | 103 | 104 | 105 | 106 | 107 | 108 | 109 | 110 | 111 | 112 | 113 | 114 | 115 | 116 | 117 | 118 | 119 | 120 | 121 | 122 | 123 | 124 | 125 | 126 | 127 | 128 | 129 | 130 | 131 | 132 | 133 | 134 | 135 | 136 | 137 | 138 | 139 | 140 | 141 | 142 | 143 | 144 | 145 | 146 | 147 | 148 | 149 | 150 | 151 | 152 | 153 | 154 | 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | 166 | 167 | 168 | 169 | 170 | 171 | 172 | 173 | 174 | 175 | 176 | 177 | 178 | 179 | 180 | 181 | 182 | 183 | 184 | 185 | 186 | 187 | 188 | 189 | 190 | 191 | 192 | 193 | 194 | 195 | 196 | 197 | 198 | 199 | 200 | 201 | 202 | 203 | 204 | 205 | 206 | 207 | 208 | 209 | 210 | 211 | 212 | 213 | 214 | 215 | 216 | 217 | 218 | 219 | 220 | 221 | 222 | 223 | 224 | 225 | 226 | 227 | 228 | 229 | 230 | 231 | 232 | 233 | 234 | 235 | 236 | 237 | 238 | 239 | 240 | 241 | 242 | 243 | 244 | 245 | 246 | 247 | 248 | 249 | 250 | 251 | 252 | 253 | 254 | 255 | 256 | 257 | 258 | 259 | 260 | 261 | 262 | 263 | 264 | 265 | 266 | 267 | 268 | 269 | 270 | 271 | 272 | 273 | 274 | 275 | 276 | 277 | 278 | 279 | 280 | 281 | 282 | 283 | 284 | 285 | 286 | 287 | 288 | 289 | 290 | 291 | 292 | 293 | 294 | 295 | 296 | 297 | 298 | 299 | 300 | 301 | 302 | 303 | 304 | 305 | 306 | 307 | 308 | 309 | 310 | 311 | 312 | 313 | 314 | 315 | 316 | 317 | 318 | 319 | 320 | 321 | 322 | 323 | 324 | 325 | 326 | 327 | 328 | 329 | 330 | 331 | 332 | 333 | -------------------------------------------------------------------------------- /data/languages/test.slaspec: -------------------------------------------------------------------------------- 1 | define endian=little; 2 | 3 | define alignment=1; 4 | 5 | define space ram type=ram_space size=3 default; 6 | define space register type=register_space size=1; 7 | 8 | define register offset=0x00 size=3 [ PC _ INTB ]; 9 | define register offset=0x05 size=2 [ INTBH INTBL]; 10 | 11 | define register offset=0x08 size=2 [ R0 R2 R1 R3 A0 A1 FB USP ISP SB FLAG SP]; 12 | define register offset=0x08 size=4 [ R2R0 R3R1 A1A0]; 13 | define register offset=0x08 size=1 [ R0H R0L _ _ R1H R1L _ _ ]; 14 | 15 | define register offset=0x30 size=4 [statusreg]; 16 | define register offset=0x34 size=1 [Cflg Dflg Zflg Sflg Bflg Oflg Iflg Uflg IPLflg]; 17 | 18 | define token operand_g (16) 19 | size0 = ( 0, 0) 20 | op1_7 = ( 1, 7) 21 | op0_7 = ( 0, 7) 22 | destmode = ( 8,11) 23 | dest8_11 = ( 8,11) 24 | dest8_11b = ( 8,11) 25 | op8_11 = ( 8,11) 26 | imm8_11 = ( 8,11) 27 | cnd8_11 = ( 8,11) 28 | op12_15 = (12,15) 29 | srcmode = (12,15) 30 | src12_15 = (12,15) 31 | src12_15b = (12,15) 32 | imm12_15 = (12,15) 33 | op0_15 = ( 0,15) 34 | op8_15 = ( 8,15) 35 | bit15 = (15,15) 36 | flg12_14 = (12,14) 37 | ldc12_14 = (12,14) 38 | bit11 = (11,11) 39 | imm8_10 = ( 8,10) 40 | dest12_14 = (12,14) 41 | ; 42 | 43 | define token data8 (8) 44 | dsp8 = (0,7) 45 | imm8 = (0,7) 46 | cnd8 = (0,7) 47 | ; 48 | 49 | define token data16 (16) 50 | dsp16 = (0,15) 51 | abs16 = (0,15) 52 | imm16 = (0,15) 53 | ; 54 | 55 | define token data32 (32) 56 | abs20 = (0,19) 57 | dsp20 = (0,19) 58 | ; 59 | 60 | 61 | attach variables [dest8_11 src12_15] [R0 R1 R2 R3 A0 A1 A0 A1 A0 A1 SB FB A0 A1 SB _ ]; 62 | 63 | #d_eab: dest8_11 is dest8_11 & dest8_11=0 { export dest8_11; } 64 | #d_eab: dest8_11 is dest8_11 & dest8_11=1 {export dest8_11; } 65 | #d_eab: dest8_11 is dest8_11 & dest8_11=2 {export dest8_11; } 66 | #d_eab: dest8_11 is dest8_11 & dest8_11=3 { export dest8_11; } 67 | #d_eab: dest8_11 is dest8_11 & dest8_11=4 { local temp = dest8_11:1; export temp; } 68 | #d_eab: dest8_11 is dest8_11 & dest8_11=5 { local temp = dest8_11:1; export temp; } 69 | #d_eab: dest8_11 is dest8_11 & dest8_11=6 { local temp = dest8_11; export *temp; } 70 | #d_eab: dest8_11 is dest8_11 & dest8_11=7 { local temp = dest8_11; export *temp; } 71 | #d_eab: dest8_11 is dest8_11 & dest8_11=8; dsp8 { local temp = (dest8_11 + dsp8); export *temp;} 72 | #d_eab: dest8_11[dsp8] is dest8_11 & dest8_11=9; dsp8 { local temp = (dest8_11 + dsp8); export *temp; } 73 | #d_eab: dest8_11[dsp8] is dest8_11 & dest8_11=10; dsp8 { local temp = (dest8_11 + dsp8); export *temp; } 74 | #d_eab: dest8_11[dsp8] is dest8_11 & dest8_11=11 ; dsp8 { local temp = (dest8_11 + dsp8); export *temp; } 75 | #d_eab: dest8_11[dsp16] is dest8_11 & dest8_11=12; dsp16 { local temp = (dest8_11 + dsp16); export *temp; } 76 | #d_eab: dest8_11[dsp16] is dest8_11 & dest8_11=13; dsp16 { local temp = (dest8_11 + dsp16); export *temp; } 77 | #d_eab: dest8_11[dsp16] is dest8_11 & dest8_11=14; dsp16 { local temp = (dest8_11 + dsp16); export *temp; } 78 | d_eab: abs16 is dest8_11 & dest8_11=15; abs16 {local temp = (abs16:2); export *temp; } 79 | 80 | :ROLC.b d_eab is (op1_7=0x3B & size0=0 & op12_15=0x0A) ... & d_eab { 81 | } 82 | 83 | 84 | -------------------------------------------------------------------------------- /data/sleighArgs.txt: -------------------------------------------------------------------------------- 1 | # Add sleigh compiler options to this file (one per line) which will 2 | # be used when compiling each language within this module. 3 | # All options should start with a '-' character. 4 | # 5 | # IMPORTANT: The -a option should NOT be specified 6 | # 7 | -u --------------------------------------------------------------------------------