├── 8bit-calculator ├── .svn_ignore ├── add.vhd ├── add16.vhd ├── build.do ├── calc_fsm.scd ├── calc_package.vhd ├── calc_testbench.vhd ├── calculator.vhd ├── divide.vhd ├── divide_old.vhd ├── ece338_8bit_calc.pdf ├── full_adder.dia ├── full_adder.dia~ ├── full_subtractor.dia ├── full_subtractor.dia~ ├── ghdl_load.do ├── multiply.vhd ├── one_bit_adder.vhd ├── one_bit_subtractor.vhd ├── report.doc ├── report.sxw ├── sim.do └── subtract.vhd ├── README.md ├── ieee-754-multiplier ├── add_16.vhd ├── add_64.vhd ├── exp_add.vhd ├── fp_mult.vhd ├── ieee_754_mult.doc ├── left_shifter.vhd ├── mant_mult.vhd ├── outputvals.txt ├── post_norm.vhd ├── right_shifter.vhd ├── sub_8.vhd ├── tb_add_16.vhd ├── tb_mult_32.vhd ├── tb_right_shifter.vhd ├── vhd.pdf ├── x_2_to_1_mux.vhd └── x_2_to_1_mux_46.vhd └── vending-machine ├── design.pdf ├── design.sxw ├── plist.py ├── state_diagram.pdf ├── state_diagram.scd ├── vmc.do ├── vmc.vhd ├── vmc_tb.vhd ├── vmc_tb_2.vhd ├── wave_all.pdf ├── wave_change.pdf ├── wave_coin_return.pdf ├── wave_nochange.pdf └── wave_reset.pdf /8bit-calculator/.svn_ignore: -------------------------------------------------------------------------------- 1 | .*.swp 2 | *.o 3 | work 4 | calc 5 | *.wlf 6 | *.mpf 7 | *.mti 8 | *.wav 9 | *.cf 10 | -------------------------------------------------------------------------------- /8bit-calculator/add.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.std_logic_unsigned.all; 5 | use IEEE.numeric_std.all; 6 | 7 | entity add is 8 | port ( 9 | clk, rst : in std_logic; 10 | in1, in2 : in std_logic_vector (0 to 7); 11 | output : out std_logic_vector (0 to 7); 12 | start : in std_logic; 13 | done : out std_logic 14 | ); 15 | end add; 16 | 17 | architecture add_impl of add is 18 | 19 | component one_bit_adder is 20 | port( 21 | x, y, c_in : in std_logic; 22 | o, c_out : out std_logic 23 | ); 24 | end component; 25 | 26 | signal carry_bus : std_logic_vector (0 to 7); 27 | signal output_sig : std_logic_vector (0 to 7); 28 | signal output_valid_sig : std_logic; 29 | signal clk_count : integer := 0; 30 | 31 | begin 32 | 33 | output <= 34 | output_sig when (rst = '0' and carry_bus(0) = '0') else 35 | "11111111" when (rst = '0' and carry_bus(0) = '1') else 36 | "00000000"; 37 | done <= output_valid_sig when rst = '0' else '0'; 38 | output_valid_sig <= '1' when clk_count = 8 else '0'; 39 | 40 | add_last : one_bit_adder port map( 41 | x => in1(0), 42 | y => in2(0), 43 | o => output_sig(0), 44 | c_in => carry_bus(1), 45 | c_out => carry_bus(0) 46 | ); 47 | 48 | add_first : one_bit_adder port map( 49 | x => in1(7), 50 | y => in2(7), 51 | c_in => '0', 52 | o => output_sig(7), 53 | c_out => carry_bus(7) 54 | ); 55 | 56 | addgen : for x in 1 to 6 generate 57 | adder : one_bit_adder port map( 58 | x => in1(x), 59 | y => in2(x), 60 | o => output_sig(x), 61 | c_in => carry_bus(x + 1), 62 | c_out => carry_bus(x) 63 | ); 64 | end generate; 65 | 66 | assure_valid : process (start, rst, clk) 67 | begin 68 | if (start = '1') then 69 | clk_count <= 0; 70 | elsif (rst = '1') then 71 | clk_count <= 0; 72 | else 73 | clk_count <= clk_count + 1; 74 | end if; 75 | end process; 76 | 77 | end add_impl; 78 | 79 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 80 | -------------------------------------------------------------------------------- /8bit-calculator/add16.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.std_logic_unsigned.all; 5 | use IEEE.numeric_std.all; 6 | 7 | entity add16 is 8 | port ( 9 | clk, rst : in std_logic; 10 | in1, in2 : in std_logic_vector (0 to 15); 11 | output : out std_logic_vector (0 to 15); 12 | start : in std_logic; 13 | done : out std_logic 14 | ); 15 | end add16; 16 | 17 | architecture add_impl of add16 is 18 | 19 | component one_bit_adder is 20 | port( 21 | x, y, c_in : in std_logic; 22 | o, c_out : out std_logic 23 | ); 24 | end component; 25 | 26 | signal carry_bus : std_logic_vector (0 to 15); 27 | signal output_sig : std_logic_vector (0 to 15); 28 | signal output_valid_sig : std_logic; 29 | signal clk_count : integer := 0; 30 | 31 | begin 32 | 33 | output <= output_sig when rst = '0' else "0000000000000000"; 34 | done <= output_valid_sig when rst = '0' else '0'; 35 | output_valid_sig <= '1' when clk_count = 16 else '0'; 36 | 37 | add_first : one_bit_adder port map( 38 | x => in1(15), 39 | y => in2(15), 40 | c_in => '0', 41 | o => output_sig(15), 42 | c_out => carry_bus(15) 43 | ); 44 | 45 | addgen : for x in 0 to 14 generate 46 | adder : one_bit_adder port map( 47 | x => in1(x), 48 | y => in2(x), 49 | o => output_sig(x), 50 | c_in => carry_bus(x + 1), 51 | c_out => carry_bus(x) 52 | ); 53 | end generate; 54 | 55 | assure_valid : process (start, rst, clk) 56 | begin 57 | if (start = '1') then 58 | clk_count <= 0; 59 | elsif (rst = '1') then 60 | clk_count <= 0; 61 | else 62 | clk_count <= clk_count + 1; 63 | end if; 64 | end process; 65 | 66 | end add_impl; 67 | 68 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 69 | -------------------------------------------------------------------------------- /8bit-calculator/build.do: -------------------------------------------------------------------------------- 1 | # compile and test the calculator project 2 | 3 | #vcom -reportprogress 300 -work calc one_bit_subtractor.vhd; 4 | #vcom -reportprogress 300 -work calc one_bit_adder.vhd; 5 | #vcom -reportprogress 300 -work calc add.vhd; 6 | #vcom -reportprogress 300 -work calc add16.vhd; 7 | #vcom -reportprogress 300 -work calc subtract.vhd; 8 | #vcom -reportprogress 300 -work calc multiply.vhd; 9 | #vcom -reportprogress 300 -work calc divide.vhd; 10 | #vcom -reportprogress 300 -work calc calc_package.vhd; 11 | #vcom -reportprogress 300 -work work calculator.vhd; 12 | #vcom -reportprogress 300 -work work calc_testbench.vhd; 13 | 14 | vcom -work calc one_bit_subtractor.vhd; 15 | vcom -work calc one_bit_adder.vhd; 16 | vcom -work calc add.vhd; 17 | vcom -work calc add16.vhd; 18 | vcom -work calc subtract.vhd; 19 | vcom -work calc multiply.vhd; 20 | vcom -work calc divide.vhd; 21 | vcom -work calc calc_package.vhd; 22 | vcom -work work calculator.vhd; 23 | vcom -work work calc_testbench.vhd; 24 | -------------------------------------------------------------------------------- /8bit-calculator/calc_fsm.scd: -------------------------------------------------------------------------------- 1 | Storage 2 | { 3 | { Format 1.33 } 4 | { GeneratedFrom TSCD-version-2.20 } 5 | { WrittenBy jmob } 6 | { WrittenOn "" } 7 | } 8 | 9 | Document 10 | { 11 | { Type "Statechart Diagram" } 12 | { Name calc_fsm.scd } 13 | { Author jmob } 14 | { CreatedOn "" } 15 | { Annotation "" } 16 | { Hierarchy True } 17 | } 18 | 19 | Page 20 | { 21 | { PageOrientation Portrait } 22 | { PageSize A4 } 23 | { ShowHeaders False } 24 | { ShowFooters False } 25 | { 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TextAlignment Center } 693 | { TextColor "black" } 694 | { NameUnderlined False } 695 | } 696 | 697 | -------------------------------------------------------------------------------- /8bit-calculator/calc_package.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.numeric_std.all; 5 | 6 | package operators is 7 | 8 | component add 9 | port ( 10 | clk, rst : in std_logic; 11 | in1, in2 : in std_logic_vector (0 to 7); 12 | output : out std_logic_vector (0 to 7); 13 | start : in std_logic; 14 | done : out std_logic 15 | ); 16 | end component; 17 | 18 | component subtract 19 | port ( 20 | clk, rst : in std_logic; 21 | in1, in2 : in std_logic_vector (0 to 7); 22 | output : out std_logic_vector (0 to 7); 23 | start : in std_logic; 24 | done : out std_logic 25 | --output_valid : out std_logic 26 | ); 27 | end component; 28 | 29 | component multiply 30 | port ( 31 | clk, rst : in std_logic; 32 | in1, in2 : in std_logic_vector (0 to 7); 33 | output : out std_logic_vector (0 to 7); 34 | --output_valid : out std_logic 35 | start : in std_logic; 36 | done : out std_logic 37 | ); 38 | end component; 39 | 40 | component divide 41 | port ( 42 | clk, rst : in std_logic; 43 | in1, in2 : in std_logic_vector (0 to 7); 44 | output : out std_logic_vector (0 to 7); 45 | --output_valid : out std_logic 46 | start : in std_logic; 47 | done : out std_logic 48 | ); 49 | end component; 50 | 51 | end package operators; 52 | 53 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 54 | -------------------------------------------------------------------------------- /8bit-calculator/calc_testbench.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | 5 | entity calc_testbench is end calc_testbench; 6 | 7 | architecture tb of calc_testbench is 8 | 9 | component calculator is 10 | port( 11 | input : in std_logic_vector (0 to 7); 12 | input_valid : in std_logic; 13 | 14 | output : out std_logic_vector (0 to 7); 15 | output_valid : out std_logic; 16 | 17 | clk : in std_logic; 18 | rst : in std_logic); 19 | end component; 20 | 21 | signal input : std_logic_vector (0 to 7); 22 | signal input_valid : std_logic; 23 | 24 | signal output : std_logic_vector (0 to 7); 25 | signal output_valid : std_logic; 26 | 27 | signal clk : std_logic; 28 | signal rst : std_logic; 29 | 30 | constant clk_period : time := 10 ns; 31 | constant clk_cycle : time := clk_period * 2; 32 | 33 | begin 34 | 35 | calc_comp : calculator port map( 36 | input => input, 37 | input_valid => input_valid, 38 | output => output, 39 | output_valid => output_valid, 40 | clk => clk, 41 | rst => rst 42 | ); 43 | 44 | rst_proc : process 45 | begin 46 | rst <= '0'; 47 | wait; 48 | end process; 49 | 50 | clock_proc : process 51 | begin 52 | clk <= '0'; 53 | wait for clk_period; 54 | clk <= '1'; 55 | wait for clk_period; 56 | end process; 57 | 58 | input_proc : process 59 | begin 60 | 61 | -- sync 62 | wait for clk_period; 63 | 64 | ------------------------ 65 | -- Test add operation -- 66 | ------------------------ 67 | 68 | -- Test: 1 + 1 = 2 69 | -- input 1 70 | input <= "00000001"; 71 | input_valid <= '0'; 72 | wait for clk_cycle; 73 | -- pulse input_valid 74 | input_valid <= '1'; 75 | wait for clk_cycle; 76 | -- operator + 77 | input <= "00000000"; 78 | input_valid <= '0'; 79 | wait for clk_cycle; 80 | -- pulse input_valid 81 | input_valid <= '1'; 82 | wait for clk_cycle; 83 | -- input 2 84 | input <= "00000001"; 85 | input_valid <= '0'; 86 | wait for clk_cycle; 87 | -- pulse input_valid 88 | input_valid <= '1'; 89 | wait for clk_cycle; 90 | 91 | -- wait for output 92 | input <= "00000000"; 93 | wait for 16 * clk_cycle; 94 | 95 | -- Test: 5 + 12 = 17 (00010001) 96 | -- input 1 97 | input <= "00000101"; 98 | input_valid <= '0'; 99 | wait for clk_cycle; 100 | -- pulse input_valid 101 | input_valid <= '1'; 102 | wait for clk_cycle; 103 | -- operator + 104 | input <= "00000000"; 105 | input_valid <= '0'; 106 | wait for clk_cycle; 107 | -- pulse input_valid 108 | input_valid <= '1'; 109 | wait for clk_cycle; 110 | -- input 2 111 | input <= "00001100"; 112 | input_valid <= '0'; 113 | wait for clk_cycle; 114 | -- pulse input_valid 115 | input_valid <= '1'; 116 | wait for clk_cycle; 117 | 118 | -- wait for output 119 | input <= "00000000"; 120 | wait for 16 * clk_cycle; 121 | 122 | -- Test: 255 + 255 = 255 123 | -- input 1 124 | input <= "11111111"; 125 | input_valid <= '0'; 126 | wait for clk_cycle; 127 | -- pulse input_valid 128 | input_valid <= '1'; 129 | wait for clk_cycle; 130 | -- operator + 131 | input <= "00000000"; 132 | input_valid <= '0'; 133 | wait for clk_cycle; 134 | -- pulse input_valid 135 | input_valid <= '1'; 136 | wait for clk_cycle; 137 | -- input 2 138 | input <= "11111111"; 139 | input_valid <= '0'; 140 | wait for clk_cycle; 141 | -- pulse input_valid 142 | input_valid <= '1'; 143 | wait for clk_cycle; 144 | 145 | -- wait for output 146 | input <= "00000000"; 147 | wait for 16 * clk_cycle; 148 | 149 | 150 | ----------------------------- 151 | -- Test subtract operation -- 152 | ----------------------------- 153 | 154 | -- Test: 3 - 1 = 2 155 | -- input 1 156 | input <= "00000011"; 157 | input_valid <= '0'; 158 | wait for clk_cycle; 159 | -- pulse input_valid 160 | input_valid <= '1'; 161 | wait for clk_cycle; 162 | -- operator - 163 | input <= "00000001"; 164 | input_valid <= '0'; 165 | wait for clk_cycle; 166 | -- pulse input_valid 167 | input_valid <= '1'; 168 | wait for clk_cycle; 169 | -- input 2 170 | input <= "00000001"; 171 | input_valid <= '0'; 172 | wait for clk_cycle; 173 | -- pulse input_valid 174 | input_valid <= '1'; 175 | wait for clk_cycle; 176 | 177 | -- wait for output 178 | input <= "00000000"; 179 | wait for 16 * clk_cycle; 180 | 181 | -- Test: 15 - 16 = 0 182 | -- input 1 183 | input <= "00001111"; 184 | input_valid <= '0'; 185 | wait for clk_cycle; 186 | -- pulse input_valid 187 | input_valid <= '1'; 188 | wait for clk_cycle; 189 | -- operator - 190 | input <= "00000001"; 191 | input_valid <= '0'; 192 | wait for clk_cycle; 193 | -- pulse input_valid 194 | input_valid <= '1'; 195 | wait for clk_cycle; 196 | -- input 2 197 | input <= "00010000"; 198 | input_valid <= '0'; 199 | wait for clk_cycle; 200 | -- pulse input_valid 201 | input_valid <= '1'; 202 | wait for clk_cycle; 203 | 204 | -- wait for output 205 | input <= "00000000"; 206 | wait for 16 * clk_cycle; 207 | 208 | ----------------------------- 209 | -- Test multiply operation -- 210 | ----------------------------- 211 | 212 | -- Test: 3 * 3 = 9 213 | -- input 1 214 | input <= "00000011"; 215 | input_valid <= '0'; 216 | wait for clk_cycle; 217 | -- pulse input_valid 218 | input_valid <= '1'; 219 | wait for clk_cycle; 220 | -- operator * 221 | input <= "00000010"; 222 | input_valid <= '0'; 223 | wait for clk_cycle; 224 | -- pulse input_valid 225 | input_valid <= '1'; 226 | wait for clk_cycle; 227 | -- input 2 228 | input <= "00000011"; 229 | input_valid <= '0'; 230 | wait for clk_cycle; 231 | -- pulse input_valid 232 | input_valid <= '1'; 233 | wait for clk_cycle; 234 | 235 | -- wait for output 236 | input <= "00000000"; 237 | wait for 128 * clk_cycle; 238 | 239 | -- Test: 14 * 8 = 112 (01110000) 240 | -- input 1 241 | input <= "00001110"; 242 | input_valid <= '0'; 243 | wait for clk_cycle; 244 | -- pulse input_valid 245 | input_valid <= '1'; 246 | wait for clk_cycle; 247 | -- operator * 248 | input <= "00000010"; 249 | input_valid <= '0'; 250 | wait for clk_cycle; 251 | -- pulse input_valid 252 | input_valid <= '1'; 253 | wait for clk_cycle; 254 | -- input 2 255 | input <= "00001000"; 256 | input_valid <= '0'; 257 | wait for clk_cycle; 258 | -- pulse input_valid 259 | input_valid <= '1'; 260 | wait for clk_cycle; 261 | 262 | -- wait for output 263 | input <= "00000000"; 264 | wait for 128 * clk_cycle; 265 | 266 | -- Test: 200 * 2 = 255 267 | -- input 1 268 | input <= "11001000"; 269 | input_valid <= '0'; 270 | wait for clk_cycle; 271 | -- pulse input_valid 272 | input_valid <= '1'; 273 | wait for clk_cycle; 274 | -- operator * 275 | input <= "00000010"; 276 | input_valid <= '0'; 277 | wait for clk_cycle; 278 | -- pulse input_valid 279 | input_valid <= '1'; 280 | wait for clk_cycle; 281 | -- input 2 282 | input <= "00000010"; 283 | input_valid <= '0'; 284 | wait for clk_cycle; 285 | -- pulse input_valid 286 | input_valid <= '1'; 287 | wait for clk_cycle; 288 | 289 | -- wait for output 290 | input_valid <= '0'; 291 | input <= "00000000"; 292 | wait for 128 * clk_cycle; 293 | 294 | 295 | ----------------------------- 296 | -- Test divide operation -- 297 | ----------------------------- 298 | 299 | -- Test: 9 / 3 = 3 300 | -- input 1 301 | input <= "00001001"; 302 | input_valid <= '0'; 303 | wait for clk_cycle; 304 | -- pulse input_valid 305 | input_valid <= '1'; 306 | wait for clk_cycle; 307 | -- input 2 - divide 308 | input <= "00000011"; 309 | input_valid <= '0'; 310 | wait for clk_cycle; 311 | -- pulse input_valid 312 | input_valid <= '1'; 313 | wait for clk_cycle; 314 | -- input 3 315 | input <= "00000011"; 316 | input_valid <= '0'; 317 | wait for clk_cycle; 318 | -- pulse input_valid 319 | input_valid <= '1'; 320 | wait for clk_cycle; 321 | 322 | -- wait for output 323 | input_valid <= '0'; 324 | input <= "00000000"; 325 | wait for 128 * clk_cycle; 326 | 327 | -- Test: 128 / 2 = 64 328 | -- input 1 329 | input <= "10000000"; 330 | input_valid <= '0'; 331 | wait for clk_cycle; 332 | -- pulse input_valid 333 | input_valid <= '1'; 334 | wait for clk_cycle; 335 | -- input 2 - divide 336 | input <= "00000011"; 337 | input_valid <= '0'; 338 | wait for clk_cycle; 339 | -- pulse input_valid 340 | input_valid <= '1'; 341 | wait for clk_cycle; 342 | -- input 3 343 | input <= "00000010"; 344 | input_valid <= '0'; 345 | wait for clk_cycle; 346 | -- pulse input_valid 347 | input_valid <= '1'; 348 | wait for clk_cycle; 349 | 350 | -- wait for output 351 | input_valid <= '0'; 352 | input <= "00000000"; 353 | wait for 128 * clk_cycle; 354 | 355 | -- Test: 136 / 4 = 34 356 | -- input 1 357 | input <= "10001000"; 358 | input_valid <= '0'; 359 | wait for clk_cycle; 360 | -- pulse input_valid 361 | input_valid <= '1'; 362 | wait for clk_cycle; 363 | -- input 2 - divide 364 | input <= "00000011"; 365 | input_valid <= '0'; 366 | wait for clk_cycle; 367 | -- pulse input_valid 368 | input_valid <= '1'; 369 | wait for clk_cycle; 370 | -- input 3 371 | input <= "00000100"; 372 | input_valid <= '0'; 373 | wait for clk_cycle; 374 | -- pulse input_valid 375 | input_valid <= '1'; 376 | wait for clk_cycle; 377 | 378 | -- wait for output 379 | input_valid <= '0'; 380 | input <= "00000000"; 381 | wait; 382 | --wait for 128 * clk_cycle; 383 | 384 | 385 | end process; 386 | 387 | end tb; 388 | 389 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 390 | -------------------------------------------------------------------------------- /8bit-calculator/calculator.vhd: -------------------------------------------------------------------------------- 1 | ----------------------------------------------------- 2 | -- ECE 338 -- Assignment 3 -- Eight Bit Calculator -- 3 | -- Jason Mobarak -- Fall 2005 ----------------------- 4 | ----------------------------------------------------- 5 | 6 | library IEEE; 7 | library calc; 8 | 9 | use IEEE.std_logic_1164.all; 10 | use IEEE.numeric_std.all; 11 | 12 | use calc.operators.all; 13 | 14 | entity calculator is 15 | port( 16 | input : in std_logic_vector (0 to 7); 17 | input_valid : in std_logic; 18 | 19 | output : out std_logic_vector (0 to 7); 20 | output_valid : out std_logic; 21 | 22 | clk : in std_logic; 23 | rst : in std_logic 24 | ); 25 | end calculator; 26 | 27 | architecture simple of calculator is 28 | 29 | type calc_state is ( 30 | calc_idle, 31 | calc_recv_in1, 32 | calc_recv_op, 33 | calc_recv_in2, 34 | --calc_start_operation, 35 | calc_wait_for_result, 36 | calc_output_result 37 | ); 38 | 39 | signal rising_clk : std_logic; 40 | 41 | signal operand_one : std_logic_vector (0 to 7); 42 | signal operand_two : std_logic_vector (0 to 7); 43 | signal operator : std_logic_vector (0 to 1); 44 | 45 | signal current_state : calc_state := calc_idle; 46 | signal next_state : calc_state := calc_idle; 47 | 48 | signal rst_v : std_logic_vector (0 to 3); 49 | signal done_v : std_logic_vector (0 to 3); 50 | signal start_v : std_logic_vector (0 to 3); 51 | 52 | signal start_v_sig : std_logic_vector (0 to 3); 53 | signal rst_v_sig : std_logic_vector (0 to 3); 54 | 55 | type ov is array (0 to 3) of std_logic_vector(0 to 7); 56 | signal output_v : ov; 57 | 58 | signal output_valid_sig : std_logic; 59 | signal output_buffer : std_logic_vector(0 to 7); 60 | 61 | begin 62 | 63 | output_valid <= output_valid_sig; 64 | 65 | output <= output_buffer when 66 | (current_state = calc_output_result) else "00000000"; 67 | 68 | output_buffer <= 69 | output_v(0) when 70 | (done_v(0) = '1' and current_state = calc_wait_for_result) else 71 | output_v(1) when 72 | (done_v(1) = '1' and current_state = calc_wait_for_result) else 73 | output_v(2) when 74 | (done_v(2) = '1' and current_state = calc_wait_for_result) else 75 | output_v(3) when 76 | (done_v(3) = '1' and current_state = calc_wait_for_result); 77 | 78 | add_comp : add port map( 79 | in1 => operand_one, 80 | in2 => operand_two, 81 | rst => rst_v(0), 82 | clk => clk, 83 | start => start_v(0), 84 | done => done_v(0), 85 | output => output_v(0) 86 | ); 87 | 88 | subtract_comp : subtract port map( 89 | in1 => operand_one, 90 | in2 => operand_two, 91 | rst => rst_v(1), 92 | clk => clk, 93 | start => start_v(1), 94 | done => done_v(1), 95 | output => output_v(1) 96 | ); 97 | 98 | multiply_comp : multiply port map( 99 | in1 => operand_one, 100 | in2 => operand_two, 101 | rst => rst_v(2), 102 | clk => clk, 103 | start => start_v(2), 104 | done => done_v(2), 105 | output => output_v(2) 106 | ); 107 | 108 | divide_comp : divide port map( 109 | in1 => operand_one, 110 | in2 => operand_two, 111 | rst => rst_v(3), 112 | clk => clk, 113 | start => start_v(3), 114 | done => done_v(3), 115 | output => output_v(3) 116 | ); 117 | 118 | clocking : process (clk, rst) 119 | begin 120 | if (rising_edge(clk)) then 121 | rising_clk <= '1'; 122 | if (rst = '1') then 123 | current_state <= calc_idle; 124 | else 125 | current_state <= next_state; 126 | end if; 127 | else 128 | rising_clk <= '0'; 129 | end if; 130 | end process; 131 | 132 | output_valid_sig <= '1' when (current_state = calc_output_result) else '0'; 133 | start_v <= start_v_sig when (current_state = calc_recv_in2) else "0000"; 134 | rst_v <= 135 | rst_v_sig when 136 | ((current_state = calc_recv_in2) or 137 | (current_state = calc_wait_for_result) or 138 | (current_state = calc_output_result)) 139 | else "1111"; 140 | 141 | calc_fsm : process (current_state, input_valid, done_v) 142 | begin 143 | case current_state is 144 | when calc_idle => 145 | if (rising_edge(input_valid)) then 146 | operand_one <= input; 147 | next_state <= calc_recv_in1; 148 | else 149 | next_state <= calc_idle; 150 | end if; 151 | when calc_recv_in1 => 152 | if (rising_edge(input_valid)) then 153 | operator <= input(6 to 7); 154 | next_state <= calc_recv_op; 155 | else 156 | next_state <= calc_recv_in1; 157 | end if; 158 | when calc_recv_op => 159 | if (rising_edge(input_valid)) then 160 | operand_two <= input; 161 | next_state <= calc_recv_in2; 162 | else 163 | next_state <= calc_recv_op; 164 | end if; 165 | when calc_recv_in2 => 166 | next_state <= calc_wait_for_result; 167 | case operator is 168 | when "00" => 169 | start_v_sig <= "1000"; 170 | rst_v_sig <= "0111"; 171 | when "01" => 172 | start_v_sig <= "0100"; 173 | rst_v_sig <= "1011"; 174 | when "10" => 175 | start_v_sig <= "0010"; 176 | rst_v_sig <= "1101"; 177 | when "11" => 178 | start_v_sig <= "0001"; 179 | rst_v_sig <= "1110"; 180 | when others => 181 | start_v_sig <= "0000"; 182 | rst_v_sig <= "1111"; 183 | end case; 184 | when calc_wait_for_result => 185 | case operator is 186 | when "00" => 187 | if (done_v(0) = '1') then 188 | next_state <= calc_output_result; 189 | else 190 | next_state <= calc_wait_for_result; 191 | end if; 192 | when "01" => 193 | if (done_v(1) = '1') then 194 | next_state <= calc_output_result; 195 | else 196 | next_state <= calc_wait_for_result; 197 | end if; 198 | when "10" => 199 | if (done_v(2) = '1') then 200 | next_state <= calc_output_result; 201 | else 202 | next_state <= calc_wait_for_result; 203 | end if; 204 | when "11" => 205 | if (done_v(3) = '1') then 206 | next_state <= calc_output_result; 207 | else 208 | next_state <= calc_wait_for_result; 209 | end if; 210 | when others => 211 | next_state <= calc_wait_for_result; 212 | end case; 213 | when calc_output_result => 214 | next_state <= calc_idle; 215 | end case; 216 | end process; 217 | 218 | end simple; 219 | 220 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 221 | -------------------------------------------------------------------------------- /8bit-calculator/divide.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_unsigned.all; 4 | use IEEE.std_logic_1164.all; 5 | --use IEEE.numeric_std.all; 6 | 7 | entity divide is 8 | port ( 9 | clk, rst : in std_logic; 10 | in1, in2 : in std_logic_vector (0 to 7); 11 | output : out std_logic_vector (0 to 7); 12 | start : in std_logic; 13 | done : out std_logic 14 | ); 15 | end divide; 16 | 17 | architecture divide_impl of divide is 18 | 19 | component subtract is 20 | port ( 21 | clk, rst : in std_logic; 22 | in1, in2 : in std_logic_vector (0 to 7); 23 | output : out std_logic_vector (0 to 7); 24 | start : in std_logic; 25 | done : out std_logic 26 | ); 27 | end component; 28 | 29 | constant zero_v_8 : std_logic_vector := "00000000"; 30 | 31 | signal in1_reg : std_logic_vector (0 to 7); 32 | signal in2_reg : std_logic_vector (0 to 7); 33 | 34 | signal shift_reg : std_logic_vector (0 to 8) := "000000000"; 35 | 36 | signal remainder : std_logic_vector (0 to 7) := zero_v_8; 37 | signal output_reg : std_logic_vector (0 to 7) := zero_v_8; 38 | signal done_sig : std_logic; 39 | 40 | signal shift_level : integer := 0; 41 | signal num_length : integer := 0; 42 | 43 | type div_state is ( 44 | div_idle, 45 | div_zero_result, 46 | div_ini_shift, 47 | div_check_shift, 48 | div_adj_shift, 49 | div_push_result, 50 | div_wait_for_sub, 51 | div_sub_done, 52 | div_zeros, 53 | div_shift, 54 | div_done 55 | ); 56 | 57 | signal current_state : div_state := div_idle; 58 | signal next_state : div_state := div_idle; 59 | 60 | signal sub_output_sig : std_logic_vector (0 to 7); 61 | signal start_subtracting : std_logic; 62 | 63 | signal sub_done_sig : std_logic; 64 | signal sub_in1 : std_logic_vector (0 to 7); 65 | signal sub_in2 : std_logic_vector (0 to 7); 66 | 67 | signal rising_clk : std_logic; 68 | signal shift_tmp : std_logic_vector (0 to 8) := "000000000"; 69 | 70 | begin 71 | 72 | sub_comp : subtract port map( 73 | clk => clk, 74 | rst => rst, 75 | output => sub_output_sig, 76 | start => start_subtracting, 77 | done => sub_done_sig, 78 | in1 => sub_in1, 79 | in2 => sub_in2 80 | ); 81 | 82 | output <= output_reg when (rst = '0' and current_state = div_done) else zero_v_8; 83 | done <= done_sig when rst = '0' else '0'; 84 | 85 | done_sig <= 86 | '1' when (current_state = div_done) else 87 | '0'; 88 | 89 | clocking : process (clk, rst) 90 | begin 91 | if (rising_edge(clk)) then 92 | rising_clk <= '1'; 93 | if (rst = '1') then 94 | current_state <= div_idle; 95 | else 96 | current_state <= next_state; 97 | end if; 98 | else 99 | rising_clk <= '0'; 100 | end if; 101 | end process; 102 | 103 | div_fsm : process (current_state, start, sub_done_sig) 104 | begin 105 | case current_state is 106 | when div_idle => 107 | shift_level <= 0; 108 | num_length <= 0; 109 | shift_reg <= "000000000"; 110 | output_reg <= zero_v_8; 111 | if (rising_edge(start)) then 112 | in1_reg <= in1; 113 | in2_reg <= in2; 114 | shift_reg(1 to 8) <= in2; 115 | next_state <= div_zero_result; 116 | else 117 | next_state <= div_idle; 118 | end if; 119 | when div_zero_result => 120 | if (in2_reg > in1_reg) then 121 | output_reg <= zero_v_8; 122 | next_state <= div_done; 123 | else 124 | next_state <= div_ini_shift; 125 | end if; 126 | when div_ini_shift => 127 | shift_tmp(0 to 7) <= shift_reg(1 to 8); 128 | shift_tmp(0 to 7) <= shift_reg(1 to 8); 129 | shift_tmp(8) <= '0'; 130 | next_state <= div_check_shift; 131 | shift_level <= shift_level + 1; 132 | when div_check_shift => 133 | if (shift_tmp < in1_reg) then -- and (not (shift_reg = in1_reg))) then 134 | shift_reg <= shift_tmp; 135 | next_state <= div_ini_shift; 136 | else 137 | remainder <= in1_reg; 138 | next_state <= div_adj_shift; 139 | end if; 140 | when div_adj_shift => 141 | shift_level <= shift_level - 2; 142 | next_state <= div_push_result; 143 | when div_push_result => 144 | next_state <= div_shift; 145 | shift_reg(1 to 8) <= shift_reg (0 to 7); 146 | shift_reg(0) <= '0'; 147 | output_reg(num_length) <= '1'; 148 | num_length <= num_length + 1; 149 | when div_shift => 150 | sub_in1 <= remainder; 151 | sub_in2 <= shift_reg(1 to 8); 152 | start_subtracting <= '1'; 153 | next_state <= div_wait_for_sub; 154 | when div_wait_for_sub => 155 | start_subtracting <= '0'; 156 | if (rising_edge(sub_done_sig)) then 157 | remainder <= sub_output_sig; 158 | next_state <= div_sub_done; 159 | else 160 | next_state <= div_wait_for_sub; 161 | end if; 162 | when div_sub_done => 163 | if (shift_level < 0) then 164 | next_state <= div_done; 165 | elsif (remainder = shift_reg) then 166 | next_state <= div_done; 167 | --output_reg(num_length) <= '1'; 168 | --num_length <= num_length + 1; 169 | elsif (remainder < shift_reg) then 170 | shift_reg(1 to 8) <= shift_reg (0 to 7); 171 | shift_reg(0) <= '0'; 172 | output_reg(num_length) <= '0'; 173 | num_length <= num_length + 1; 174 | shift_level <= shift_level - 1; 175 | next_state <= div_zeros; 176 | elsif (remainder > shift_reg) then 177 | output_reg(num_length) <= '1'; 178 | num_length <= num_length + 1; 179 | next_state <= div_shift; 180 | --elsif (shift_level > 0) then 181 | -- output_reg(7 - shift_level) <= '1'; 182 | end if; 183 | when div_zeros => 184 | next_state <= div_sub_done; 185 | when div_done => 186 | next_state <= div_idle; 187 | end case; 188 | end process; 189 | 190 | end divide_impl; 191 | 192 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 193 | -------------------------------------------------------------------------------- /8bit-calculator/divide_old.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.std_logic_unsigned.all; 5 | use IEEE.numeric_std.all; 6 | 7 | entity divide is 8 | port ( 9 | clk, rst : in std_logic; 10 | in1, in2 : in std_logic_vector (0 to 7); 11 | output : out std_logic_vector (0 to 7); 12 | output_valid : out std_logic 13 | ); 14 | end divide; 15 | 16 | architecture divide_impl of divide is 17 | begin 18 | output <= 19 | std_logic_vector( 20 | to_unsigned(conv_integer(in1)/conv_integer(in2), 8)) 21 | when rst = '0' else 22 | "00000000"; 23 | 24 | output_valid <= 25 | '1' when rst = '0' else 26 | '0'; 27 | 28 | end divide_impl; 29 | 30 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 31 | -------------------------------------------------------------------------------- /8bit-calculator/ece338_8bit_calc.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/ece338_8bit_calc.pdf -------------------------------------------------------------------------------- /8bit-calculator/full_adder.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/full_adder.dia -------------------------------------------------------------------------------- /8bit-calculator/full_adder.dia~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/full_adder.dia~ -------------------------------------------------------------------------------- /8bit-calculator/full_subtractor.dia: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/full_subtractor.dia -------------------------------------------------------------------------------- /8bit-calculator/full_subtractor.dia~: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/full_subtractor.dia~ -------------------------------------------------------------------------------- /8bit-calculator/ghdl_load.do: -------------------------------------------------------------------------------- 1 | # create working directories 2 | 3 | # analyze and elaborate sources 4 | eval ghdl -a --ieee=synopsys calctb.vhd 5 | eval ghdl -m --ieee=synopsys calctb 6 | 7 | file rename -force calctb calctb.ghdl 8 | 9 | # load design, run simulation 10 | load_design calctb.ghdl 11 | -------------------------------------------------------------------------------- /8bit-calculator/multiply.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.std_logic_unsigned.all; 5 | use IEEE.numeric_std.all; 6 | 7 | entity multiply is 8 | port ( 9 | clk, rst : in std_logic; 10 | in1, in2 : in std_logic_vector (0 to 7); 11 | output : out std_logic_vector (0 to 7); 12 | start : in std_logic; 13 | done : out std_logic 14 | ); 15 | end multiply; 16 | 17 | architecture multiply_impl of multiply is 18 | 19 | component add16 is 20 | port ( 21 | clk, rst : in std_logic; 22 | in1, in2 : in std_logic_vector (0 to 15); 23 | output : out std_logic_vector (0 to 15); 24 | start : in std_logic; 25 | done : out std_logic 26 | ); 27 | end component; 28 | 29 | constant zero_v_16 : std_logic_vector := "0000000000000000"; 30 | constant zero_v_8 : std_logic_vector := "00000000"; 31 | 32 | signal product_reg : std_logic_vector (0 to 15) := zero_v_16; 33 | signal shift_reg : std_logic_vector (0 to 15) := zero_v_16; 34 | 35 | signal in1_reg : std_logic_vector (0 to 7); 36 | signal in2_reg : std_logic_vector (0 to 7); 37 | 38 | signal output_sig : std_logic_vector (0 to 7); 39 | signal done_sig : std_logic; 40 | 41 | signal shift_level : integer := 0; 42 | 43 | type mult_state is ( 44 | mult_idle, 45 | mult_add_start, 46 | mult_add_wait, 47 | mult_add_done, 48 | mult_shift_start, 49 | mult_shift, 50 | mult_add_iter, 51 | mult_done 52 | ); 53 | 54 | signal current_state : mult_state := mult_idle; 55 | signal next_state : mult_state := mult_idle; 56 | 57 | signal add16_output_sig : std_logic_vector (0 to 15); 58 | signal start_adding : std_logic; 59 | signal add_done_sig : std_logic; 60 | signal add_in1 : std_logic_vector (0 to 15); 61 | signal add_in2 : std_logic_vector (0 to 15); 62 | 63 | signal rising_clk : std_logic; 64 | 65 | signal xor_oper : std_logic := '0'; 66 | 67 | begin 68 | 69 | add16_comp : add16 port map( 70 | clk => clk, 71 | rst => rst, 72 | output => add16_output_sig, 73 | start => start_adding, 74 | done => add_done_sig, 75 | in1 => add_in1, 76 | in2 => add_in2 77 | ); 78 | 79 | output <= output_sig when rst = '0' else zero_v_8; 80 | done <= done_sig when rst = '0' else '0'; 81 | 82 | output_sig <= 83 | product_reg(8 to 15) when ((current_state = mult_done) and (product_reg(7) = '0')) else 84 | "11111111" when ((current_state = mult_done) and (product_reg(7) = '1')) else 85 | zero_v_8; 86 | 87 | done_sig <= 88 | '1' when (current_state = mult_done) else 89 | '0'; 90 | 91 | clocking : process (clk, rst) 92 | begin 93 | if (rising_edge(clk)) then 94 | rising_clk <= '1'; 95 | if (rst = '1') then 96 | current_state <= mult_idle; 97 | else 98 | current_state <= next_state; 99 | end if; 100 | else 101 | rising_clk <= '0'; 102 | end if; 103 | end process; 104 | 105 | start_adding <= 106 | '1' when (current_state = mult_add_start) else 107 | '0'; 108 | 109 | add_in1 <= 110 | product_reg when ((current_state = mult_add_start) or 111 | (current_state = mult_add_wait)) else 112 | zero_v_16; 113 | 114 | add_in2 <= 115 | shift_reg when ((current_state = mult_add_start) or 116 | (current_state = mult_add_wait)) else 117 | zero_v_16; 118 | 119 | mult_fsm : process (current_state, start, add_done_sig) 120 | begin 121 | case current_state is 122 | when mult_idle => 123 | shift_level <= 0; 124 | shift_reg <= zero_v_16; 125 | product_reg <= zero_v_16; 126 | if (rising_edge(start)) then 127 | in1_reg <= in1; 128 | in2_reg <= in2; 129 | next_state <= mult_add_start; 130 | else 131 | next_state <= mult_idle; 132 | end if; 133 | when mult_add_start => 134 | next_state <= mult_add_wait; 135 | when mult_add_wait => 136 | if (rising_edge(add_done_sig)) then 137 | next_state <= mult_add_done; 138 | else 139 | next_state <= mult_add_wait; 140 | end if; 141 | when mult_add_done => 142 | next_state <= mult_shift_start; 143 | product_reg <= add16_output_sig; 144 | xor_oper <= in2_reg(7 - shift_level); 145 | when mult_shift_start => 146 | shift_reg <= zero_v_16; 147 | next_state <= mult_shift; 148 | when mult_shift => 149 | for idx in 0 to 7 loop 150 | shift_reg (15 - (idx + shift_level)) <= xor_oper and in1_reg(7 - idx); 151 | end loop; 152 | next_state <= mult_add_iter; 153 | when mult_add_iter => 154 | if (shift_level = 7 or shift_level > 7) then 155 | next_state <= mult_done; 156 | else 157 | shift_level <= shift_level + 1; 158 | next_state <= mult_add_start; 159 | end if; 160 | when mult_done => 161 | next_state <= mult_idle; 162 | end case; 163 | end process; 164 | 165 | end multiply_impl; 166 | 167 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 168 | -------------------------------------------------------------------------------- /8bit-calculator/one_bit_adder.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | 5 | entity one_bit_adder is 6 | port( 7 | x, y, c_in : in std_logic; 8 | o, c_out : out std_logic 9 | ); 10 | end one_bit_adder; 11 | 12 | architecture behavioral of one_bit_adder is 13 | 14 | begin 15 | 16 | o <= (x xor (y xor c_in)); 17 | c_out <= ((y and c_in) or (x and c_in) or (x and y)); 18 | 19 | end behavioral; 20 | -------------------------------------------------------------------------------- /8bit-calculator/one_bit_subtractor.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | 5 | entity one_bit_subtractor is 6 | port( 7 | x, y, b_in : in std_logic; 8 | d, b_out : out std_logic 9 | ); 10 | end one_bit_subtractor; 11 | 12 | architecture behavioral of one_bit_subtractor is 13 | 14 | begin 15 | 16 | d <= b_in xor (x xor y); 17 | b_out <= ((not x) and y) or (b_in and (not (x xor y))); 18 | 19 | end behavioral; 20 | -------------------------------------------------------------------------------- /8bit-calculator/report.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/report.doc -------------------------------------------------------------------------------- /8bit-calculator/report.sxw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/8bit-calculator/report.sxw -------------------------------------------------------------------------------- /8bit-calculator/sim.do: -------------------------------------------------------------------------------- 1 | quit -sim; 2 | vsim work.calc_testbench; 3 | add wave -r /*; 4 | run 20000ns; 5 | -------------------------------------------------------------------------------- /8bit-calculator/subtract.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | 3 | use IEEE.std_logic_1164.all; 4 | use IEEE.std_logic_unsigned.all; 5 | 6 | entity subtract is 7 | port ( 8 | clk, rst : in std_logic; 9 | in1, in2 : in std_logic_vector (0 to 7); 10 | output : out std_logic_vector (0 to 7); 11 | start : in std_logic; 12 | done : out std_logic 13 | ); 14 | end subtract; 15 | 16 | architecture subtract_impl of subtract is 17 | 18 | component one_bit_subtractor is 19 | port( 20 | x, y, b_in : in std_logic; 21 | d, b_out : out std_logic 22 | ); 23 | end component; 24 | 25 | signal borrow_bus : std_logic_vector (0 to 7); 26 | signal output_sig : std_logic_vector (0 to 7); 27 | signal output_valid_sig : std_logic; 28 | signal clk_count : integer := 0; 29 | 30 | begin 31 | 32 | output <= 33 | output_sig when (rst = '0' and borrow_bus(0) = '0') else 34 | "00000000"; 35 | done <= output_valid_sig when rst = '0' else '0'; 36 | output_valid_sig <= '1' when clk_count = 8 else '0'; 37 | 38 | sub_first : one_bit_subtractor port map( 39 | x => in1(7), 40 | y => in2(7), 41 | b_in => '0', 42 | d => output_sig(7), 43 | b_out => borrow_bus(7) 44 | ); 45 | 46 | subgen : for x in 0 to 6 generate 47 | subber : one_bit_subtractor port map( 48 | x => in1(x), 49 | y => in2(x), 50 | d => output_sig(x), 51 | b_in => borrow_bus(x + 1), 52 | b_out => borrow_bus(x) 53 | ); 54 | end generate; 55 | 56 | assure_valid : process (start, rst, clk) 57 | begin 58 | if (start = '1') then 59 | clk_count <= 0; 60 | elsif (rst = '1') then 61 | clk_count <= 0; 62 | else 63 | clk_count <= clk_count + 1; 64 | end if; 65 | end process; 66 | 67 | end subtract_impl; 68 | 69 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 70 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | VHDL 2 | ==== 3 | 4 | VHDL samples from school projects. 5 | 6 | 7 | 8bit-calculator 8 | --------------- 9 | 10 | 8-bit calculator controller. 11 | 12 | 13 | Vending Machine (vending-machine) 14 | --------------------------------- 15 | 16 | A vending machine controller with typical vending machine logic (e.g. checking 17 | item cost, giving change, vending selected items). 18 | 19 | 20 | IEEE 754 Multiplier (ieee-754-multiplier) 21 | ----------------------------------------- 22 | 23 | Implements (most of) the logic required to implement a IEEE 754 multiplier 24 | unit. 25 | -------------------------------------------------------------------------------- /ieee-754-multiplier/add_16.vhd: -------------------------------------------------------------------------------- 1 | -- File : add_16.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | library lib438; 7 | use lib438.all; 8 | 9 | entity add_16 is 10 | port ( 11 | A : in std_logic_vector (15 downto 0); 12 | B : in std_logic_vector (15 downto 0); 13 | C : in std_logic; 14 | O : out std_logic_vector (15 downto 0); 15 | G : out std_logic; 16 | P : out std_logic); 17 | end add_16; 18 | 19 | architecture arch of add_16 is 20 | 21 | component CLA is 22 | generic ( 23 | DELAY : time := 6 ns 24 | ); 25 | port ( 26 | A_IN : in std_logic_vector (3 downto 0); 27 | B_IN : in std_logic_vector (3 downto 0); 28 | C_IN : in std_logic; 29 | P : out std_logic; 30 | G : out std_logic; 31 | F_OUT : out std_logic_vector (3 downto 0) 32 | ); 33 | end component CLA; 34 | 35 | component LACG is 36 | generic ( 37 | DELAY : time := 6 ns 38 | ); 39 | port ( 40 | C_IN : in std_logic; 41 | 42 | P0_H : in std_logic; 43 | G0_H : in std_logic; 44 | 45 | CX : out std_logic; 46 | 47 | P1_H : in std_logic; 48 | G1_H : in std_logic; 49 | 50 | CY : out std_logic; 51 | 52 | P2_H : in std_logic; 53 | G2_H : in std_logic; 54 | 55 | CZ : out std_logic; 56 | 57 | P3_H : in std_logic; 58 | G3_H : in std_logic; 59 | 60 | GOUT : out std_logic; 61 | POUT : out std_logic 62 | ); 63 | end component LACG; 64 | 65 | signal G_3 : std_logic; 66 | signal G_2 : std_logic; 67 | signal G_1 : std_logic; 68 | signal G_0 : std_logic; 69 | 70 | signal P_3 : std_logic; 71 | signal P_2 : std_logic; 72 | signal P_1 : std_logic; 73 | signal P_0 : std_logic; 74 | 75 | signal C_3 : std_logic; 76 | signal C_2 : std_logic; 77 | signal C_1 : std_logic; 78 | signal C_0 : std_logic; 79 | 80 | begin -- arch 81 | 82 | GROUP_3 : CLA 83 | port map ( 84 | A_IN => A (15 downto 12), 85 | B_IN => B (15 downto 12), 86 | C_IN => C_3, 87 | P => P_3, 88 | G => G_3, 89 | F_OUT => O (15 downto 12)); 90 | 91 | GROUP_2 : CLA 92 | port map ( 93 | A_IN => A (11 downto 8), 94 | B_IN => B (11 downto 8), 95 | C_IN => C_2, 96 | P => P_2, 97 | G => G_2, 98 | F_OUT => O (11 downto 8)); 99 | 100 | GROUP_1 : CLA 101 | port map ( 102 | A_IN => A (7 downto 4), 103 | B_IN => B (7 downto 4), 104 | C_IN => C_1, 105 | P => P_1, 106 | G => G_1, 107 | F_OUT => O (7 downto 4)); 108 | 109 | GROUP_0 : CLA 110 | port map ( 111 | A_IN => A (3 downto 0), 112 | B_IN => B (3 downto 0), 113 | C_IN => C, 114 | P => P_0, 115 | G => G_0, 116 | F_OUT => O (3 downto 0)); 117 | 118 | LACG_0 : LACG 119 | port map ( 120 | P3_H => P_3, 121 | G3_H => G_3, 122 | P2_H => P_2, 123 | G2_H => G_2, 124 | P1_H => P_1, 125 | G1_H => G_1, 126 | P0_H => P_0, 127 | G0_H => G_0, 128 | C_IN => C, 129 | CZ => C_3, 130 | CY => C_2, 131 | CX => C_1, 132 | GOUT => G, 133 | POUT => P); 134 | 135 | end arch; 136 | -------------------------------------------------------------------------------- /ieee-754-multiplier/add_64.vhd: -------------------------------------------------------------------------------- 1 | -- File : add_64.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | library lib438; 7 | use lib438.all; 8 | 9 | entity add_64 is 10 | port ( 11 | A : in std_logic_vector (63 downto 0); 12 | B : in std_logic_vector (63 downto 0); 13 | C : in std_logic; 14 | G : out std_logic; 15 | P : out std_logic; 16 | O : out std_logic_vector (63 downto 0) 17 | ); 18 | end add_64; 19 | 20 | architecture arch of add_64 is 21 | 22 | component add_16 is 23 | port ( 24 | A : in std_logic_vector (15 downto 0); 25 | B : in std_logic_vector (15 downto 0); 26 | C : in std_logic; 27 | O : out std_logic_vector (15 downto 0); 28 | G : out std_logic; 29 | P : out std_logic 30 | ); 31 | end component add_16; 32 | 33 | component LACG is 34 | generic ( 35 | DELAY : time := 6 ns 36 | ); 37 | port ( 38 | C_IN : in std_logic; 39 | 40 | P0_H : in std_logic; 41 | G0_H : in std_logic; 42 | 43 | CX : out std_logic; 44 | 45 | P1_H : in std_logic; 46 | G1_H : in std_logic; 47 | 48 | CY : out std_logic; 49 | 50 | P2_H : in std_logic; 51 | G2_H : in std_logic; 52 | 53 | CZ : out std_logic; 54 | 55 | P3_H : in std_logic; 56 | G3_H : in std_logic; 57 | 58 | GOUT : out std_logic; 59 | POUT : out std_logic 60 | ); 61 | end component LACG; 62 | 63 | signal G_3 : std_logic; 64 | signal G_2 : std_logic; 65 | signal G_1 : std_logic; 66 | signal G_0 : std_logic; 67 | 68 | signal P_3 : std_logic; 69 | signal P_2 : std_logic; 70 | signal P_1 : std_logic; 71 | signal P_0 : std_logic; 72 | 73 | signal C_3 : std_logic; 74 | signal C_2 : std_logic; 75 | signal C_1 : std_logic; 76 | signal C_0 : std_logic; 77 | 78 | begin -- arch 79 | 80 | GROUP_3 : ADD_16 81 | port map ( 82 | A => A (63 downto 48), 83 | B => B (63 downto 48), 84 | C => C_3, 85 | P => P_3, 86 | G => G_3, 87 | O => O (63 downto 48)); 88 | 89 | GROUP_2 : ADD_16 90 | port map ( 91 | A => A (47 downto 32), 92 | B => B (47 downto 32), 93 | C => C_2, 94 | P => P_2, 95 | G => G_2, 96 | O => O (47 downto 32)); 97 | 98 | GROUP_1 : ADD_16 99 | port map ( 100 | A => A (31 downto 16), 101 | B => B (31 downto 16), 102 | C => C_1, 103 | P => P_1, 104 | G => G_1, 105 | O => O (31 downto 16)); 106 | 107 | GROUP_0 : ADD_16 108 | port map ( 109 | A => A (15 downto 0), 110 | B => B (15 downto 0), 111 | C => C, 112 | P => P_0, 113 | G => G_0, 114 | O => O (15 downto 0)); 115 | 116 | LACG_0 : LACG 117 | port map ( 118 | P3_H => P_3, 119 | G3_H => G_3, 120 | P2_H => P_2, 121 | G2_H => G_2, 122 | P1_H => P_1, 123 | G1_H => G_1, 124 | P0_H => P_0, 125 | G0_H => G_0, 126 | C_IN => C, 127 | CZ => C_3, 128 | CY => C_2, 129 | CX => C_1, 130 | GOUT => G, 131 | POUT => P); 132 | 133 | end arch; 134 | -------------------------------------------------------------------------------- /ieee-754-multiplier/exp_add.vhd: -------------------------------------------------------------------------------- 1 | -- File : exp_add.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity exp_add is 7 | port ( 8 | A_EXP : in std_logic_vector(7 downto 0); 9 | B_EXP : in std_logic_vector(7 downto 0); 10 | ADJ : in std_logic_vector(4 downto 0); -- adjustment needed from 11 | -- right shifting mantissa 12 | O_EXP : out std_logic_vector(7 downto 0) 13 | ); 14 | end exp_add; 15 | 16 | architecture arch of exp_add is 17 | 18 | component sub_8 is 19 | port ( 20 | A : in std_logic_vector(7 downto 0); 21 | B : in std_logic_vector(7 downto 0); 22 | D : out std_logic_vector(7 downto 0) 23 | ); 24 | end component sub_8; 25 | 26 | component add_16 is 27 | port ( 28 | A : in std_logic_vector (15 downto 0); 29 | B : in std_logic_vector (15 downto 0); 30 | C : in std_logic; 31 | O : out std_logic_vector (15 downto 0); 32 | G : out std_logic; 33 | P : out std_logic); 34 | end component add_16; 35 | 36 | signal s_a_b_sum : std_logic_vector(15 downto 0); 37 | signal s_a_b_sum_p : std_logic; 38 | signal s_a_b_sum_g : std_logic; 39 | 40 | signal s_a_b_adj_sum : std_logic_vector(15 downto 0); 41 | signal s_a_b_adj_sum_p : std_logic; 42 | signal s_a_b_adj_sum_g : std_logic; 43 | 44 | signal s_output : std_logic_vector(7 downto 0); 45 | 46 | begin -- arch 47 | 48 | O_EXP <= s_output; 49 | 50 | add_0 : add_16 51 | port map ( 52 | A(15 downto 8) => (others => '0'), 53 | A(7 downto 0) => A_EXP, 54 | B(15 downto 8) => (others => '0'), 55 | B(7 downto 0) => B_EXP, 56 | C => '0', 57 | O => s_a_b_sum, 58 | G => s_a_b_sum_g, 59 | P => s_a_b_sum_p 60 | ); 61 | 62 | add_1 : add_16 63 | port map ( 64 | A => s_a_b_sum, 65 | B(15 downto 5) => (others => '0'), 66 | B(4 downto 0) => ADJ, 67 | C => '0', 68 | O => s_a_b_adj_sum, 69 | G => s_a_b_adj_sum_g, 70 | P => s_a_b_adj_sum_p 71 | ); 72 | 73 | sub_0 : sub_8 74 | port map ( 75 | A => s_a_b_adj_sum(7 downto 0), 76 | B => X"7F", -- substract bias (127) 77 | D => s_output 78 | ); 79 | 80 | end arch; 81 | -------------------------------------------------------------------------------- /ieee-754-multiplier/fp_mult.vhd: -------------------------------------------------------------------------------- 1 | -- File : fp_mult.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity fp_mult is 7 | port ( 8 | A_H : in std_logic_vector (31 downto 0); 9 | B_H : in std_logic_vector (31 downto 0); 10 | O_H : out std_logic_vector (31 downto 0) 11 | ); 12 | end fp_mult; 13 | 14 | architecture arch of fp_mult is 15 | 16 | component mant_mult is 17 | port ( 18 | A_EXP : in std_logic_vector(7 downto 0); 19 | B_EXP : in std_logic_vector(7 downto 0); 20 | A_H : in std_logic_vector(22 downto 0); 21 | B_H : in std_logic_vector(22 downto 0); 22 | C_H : out std_logic; 23 | O_H : out std_logic_vector(47 downto 0)); 24 | end component mant_mult; 25 | 26 | component post_norm is 27 | port ( 28 | N_MANT : in std_logic_vector(47 downto 0); 29 | ADJ : out std_logic_vector(4 downto 0); 30 | O_MANT : out std_logic_vector(22 downto 0) 31 | ); 32 | end component post_norm; 33 | 34 | component exp_add is 35 | port ( 36 | A_EXP : in std_logic_vector(7 downto 0); 37 | B_EXP : in std_logic_vector(7 downto 0); 38 | ADJ : in std_logic_vector(4 downto 0); 39 | O_EXP : out std_logic_vector(7 downto 0) 40 | ); 41 | end component exp_add; 42 | 43 | signal s_mm_c : std_logic; 44 | signal s_mm_o : std_logic_vector(47 downto 0); 45 | 46 | signal s_ea_adj : std_logic_vector(4 downto 0); 47 | 48 | begin -- arch 49 | 50 | O_H(31) <= A_H(31) xor B_H(31); 51 | 52 | MM_0 : MANT_MULT 53 | port map ( 54 | A_EXP => A_H(30 downto 23), 55 | B_EXP => B_H(30 downto 23), 56 | A_H => A_H(22 downto 0), 57 | B_H => B_H(22 downto 0), 58 | C_H => s_mm_c, 59 | O_H => s_mm_o 60 | ); 61 | 62 | EA_0 : EXP_ADD 63 | port map ( 64 | A_EXP => A_H(30 downto 23), 65 | B_EXP => B_H(30 downto 23), 66 | ADJ => s_ea_adj, 67 | O_EXP => O_H(30 downto 23) 68 | ); 69 | 70 | PN_0 : POST_NORM 71 | port map ( 72 | N_MANT => s_mm_o, 73 | ADJ => s_ea_adj, 74 | O_MANT => O_H(22 downto 0) 75 | ); 76 | 77 | end arch; 78 | -------------------------------------------------------------------------------- /ieee-754-multiplier/ieee_754_mult.doc: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/ieee-754-multiplier/ieee_754_mult.doc -------------------------------------------------------------------------------- /ieee-754-multiplier/left_shifter.vhd: -------------------------------------------------------------------------------- 1 | -- File : left_shifter 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity left_shifter is 7 | port ( 8 | A : in std_logic_vector(23 downto 0); 9 | S : in std_logic_vector(4 downto 0); 10 | O : out std_logic_vector(47 downto 0) 11 | ); 12 | end left_shifter; 13 | 14 | architecture arch of left_shifter is 15 | 16 | component x_2_to_1_mux is 17 | port ( 18 | A : in std_logic_vector(47 downto 0); 19 | B : in std_logic_vector(47 downto 0); 20 | S : in std_logic; 21 | O : out std_logic_vector(47 downto 0) 22 | ); 23 | end component x_2_to_1_mux; 24 | 25 | signal s_8_to_16 : std_logic_vector(47 downto 0); 26 | signal s_4_to_8 : std_logic_vector(47 downto 0); 27 | signal s_2_to_4 : std_logic_vector(47 downto 0); 28 | signal s_1_to_2 : std_logic_vector(47 downto 0); 29 | 30 | begin -- arch 31 | 32 | -- 1-bit shift 33 | X21M_1 : x_2_to_1_mux 34 | port map ( 35 | A(47 downto 24) => (others => '0'), 36 | A(23 downto 0) => A, 37 | B(47 downto 25) => (others => '0'), 38 | B(24 downto 1) => A (23 downto 0), 39 | B(0) => '0', 40 | S => S(0), 41 | O => s_1_to_2 42 | ); 43 | 44 | -- 2-bit shift 45 | X21M_2 : x_2_to_1_mux 46 | port map ( 47 | A => s_1_to_2, 48 | B(47 downto 2) => s_1_to_2(45 downto 0), 49 | B(1 downto 0) => (others => '0'), 50 | S => S(1), 51 | O => s_2_to_4 52 | ); 53 | 54 | -- 4-bit shift 55 | X21M_4 : x_2_to_1_mux 56 | port map ( 57 | A => s_2_to_4, 58 | B(47 downto 4) => s_2_to_4(43 downto 0), 59 | B(3 downto 0) => (others => '0'), 60 | S => S(2), 61 | O => s_4_to_8 62 | ); 63 | 64 | -- 8-bit shift 65 | X21M_8 : x_2_to_1_mux 66 | port map ( 67 | A => s_4_to_8, 68 | B(47 downto 8) => s_4_to_8(39 downto 0), 69 | B(7 downto 0) => (others => '0'), 70 | S => S(3), 71 | O => s_8_to_16 72 | ); 73 | 74 | -- 16-bit shift 75 | X21M_16 : x_2_to_1_mux 76 | port map ( 77 | A => s_8_to_16, 78 | B(47 downto 16) => s_8_to_16(31 downto 0), 79 | B(15 downto 0) => (others => '0'), 80 | S => S(4), 81 | O => O 82 | ); 83 | 84 | end arch; 85 | -------------------------------------------------------------------------------- /ieee-754-multiplier/mant_mult.vhd: -------------------------------------------------------------------------------- 1 | -- File : mant_mult.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | library lib438; 7 | use lib438.all; 8 | 9 | entity mant_mult is 10 | port ( 11 | A_EXP : in std_logic_vector(7 downto 0); 12 | B_EXP : in std_logic_vector(7 downto 0); 13 | A_H : in std_logic_vector(22 downto 0); 14 | B_H : in std_logic_vector(22 downto 0); 15 | C_H : out std_logic; 16 | O_H : out std_logic_vector(47 downto 0)); 17 | end mant_mult; 18 | 19 | architecture arch of mant_mult is 20 | 21 | component left_shifter is 22 | port ( 23 | A : in std_logic_vector(23 downto 0); 24 | S : in std_logic_vector(4 downto 0); 25 | O : out std_logic_vector(47 downto 0) 26 | ); 27 | end component left_shifter; 28 | 29 | component adder64 is 30 | port ( 31 | A : in std_logic_vector(63 downto 0); 32 | B : in std_logic_vector(63 downto 0); 33 | C : in std_logic; 34 | G : out std_logic; 35 | P : out std_logic; 36 | O : out std_logic_vector(63 downto 0) 37 | ); 38 | end component adder64; 39 | 40 | component RRU3_2 is 41 | generic (DLY_TIME : time := 2 ns); 42 | port ( 43 | A_VAL : in std_logic_vector(47 downto 0); 44 | B_VAL : in std_logic_vector(47 downto 0); 45 | C_VAL : in std_logic_vector(47 downto 0); 46 | F0_VAL : out std_logic_vector(47 downto 0); 47 | F1_VAL : out std_logic_vector(47 downto 0) 48 | ); 49 | end component RRU3_2; 50 | 51 | component RRU7_3 is 52 | port ( 53 | A_VAL : in std_logic_vector(47 downto 0); 54 | B_VAL : in std_logic_vector(47 downto 0); 55 | C_VAL : in std_logic_vector(47 downto 0); 56 | D_VAL : in std_logic_vector(47 downto 0); 57 | E_VAL : in std_logic_vector(47 downto 0); 58 | F_VAL : in std_logic_vector(47 downto 0); 59 | G_VAL : in std_logic_vector(47 downto 0); 60 | F0_VAL : out std_logic_vector(47 downto 0); 61 | F1_VAL : out std_logic_vector(47 downto 0); 62 | F2_VAL : out std_logic_vector(47 downto 0) 63 | ); 64 | end component RRU7_3; 65 | 66 | signal pp_00 : std_logic_vector(47 downto 0) := (others => '0'); 67 | signal pp_01 : std_logic_vector(47 downto 0) := (others => '0'); 68 | signal pp_02 : std_logic_vector(47 downto 0) := (others => '0'); 69 | signal pp_03 : std_logic_vector(47 downto 0) := (others => '0'); 70 | signal pp_04 : std_logic_vector(47 downto 0) := (others => '0'); 71 | signal pp_05 : std_logic_vector(47 downto 0) := (others => '0'); 72 | signal pp_06 : std_logic_vector(47 downto 0) := (others => '0'); 73 | signal pp_07 : std_logic_vector(47 downto 0) := (others => '0'); 74 | signal pp_08 : std_logic_vector(47 downto 0) := (others => '0'); 75 | signal pp_09 : std_logic_vector(47 downto 0) := (others => '0'); 76 | signal pp_10 : std_logic_vector(47 downto 0) := (others => '0'); 77 | signal pp_11 : std_logic_vector(47 downto 0) := (others => '0'); 78 | signal pp_12 : std_logic_vector(47 downto 0) := (others => '0'); 79 | signal pp_13 : std_logic_vector(47 downto 0) := (others => '0'); 80 | signal pp_14 : std_logic_vector(47 downto 0) := (others => '0'); 81 | signal pp_15 : std_logic_vector(47 downto 0) := (others => '0'); 82 | signal pp_16 : std_logic_vector(47 downto 0) := (others => '0'); 83 | signal pp_17 : std_logic_vector(47 downto 0) := (others => '0'); 84 | signal pp_18 : std_logic_vector(47 downto 0) := (others => '0'); 85 | signal pp_19 : std_logic_vector(47 downto 0) := (others => '0'); 86 | signal pp_20 : std_logic_vector(47 downto 0) := (others => '0'); 87 | signal pp_21 : std_logic_vector(47 downto 0) := (others => '0'); 88 | signal pp_22 : std_logic_vector(47 downto 0) := (others => '0'); 89 | signal pp_23 : std_logic_vector(47 downto 0) := (others => '0'); 90 | 91 | signal s_shift_01 : std_logic_vector(4 downto 0); 92 | signal s_shift_02 : std_logic_vector(4 downto 0); 93 | signal s_shift_03 : std_logic_vector(4 downto 0); 94 | signal s_shift_04 : std_logic_vector(4 downto 0); 95 | signal s_shift_05 : std_logic_vector(4 downto 0); 96 | signal s_shift_06 : std_logic_vector(4 downto 0); 97 | signal s_shift_07 : std_logic_vector(4 downto 0); 98 | signal s_shift_08 : std_logic_vector(4 downto 0); 99 | signal s_shift_09 : std_logic_vector(4 downto 0); 100 | signal s_shift_10 : std_logic_vector(4 downto 0); 101 | signal s_shift_11 : std_logic_vector(4 downto 0); 102 | signal s_shift_12 : std_logic_vector(4 downto 0); 103 | signal s_shift_13 : std_logic_vector(4 downto 0); 104 | signal s_shift_14 : std_logic_vector(4 downto 0); 105 | signal s_shift_15 : std_logic_vector(4 downto 0); 106 | signal s_shift_16 : std_logic_vector(4 downto 0); 107 | signal s_shift_17 : std_logic_vector(4 downto 0); 108 | signal s_shift_18 : std_logic_vector(4 downto 0); 109 | signal s_shift_19 : std_logic_vector(4 downto 0); 110 | signal s_shift_20 : std_logic_vector(4 downto 0); 111 | signal s_shift_21 : std_logic_vector(4 downto 0); 112 | signal s_shift_22 : std_logic_vector(4 downto 0); 113 | signal s_shift_23 : std_logic_vector(4 downto 0); 114 | 115 | signal s_stage0_output00 : std_logic_vector(47 downto 0); 116 | signal s_stage0_output01 : std_logic_vector(47 downto 0); 117 | signal s_stage0_output02 : std_logic_vector(47 downto 0); 118 | signal s_stage0_output03 : std_logic_vector(47 downto 0); 119 | signal s_stage0_output04 : std_logic_vector(47 downto 0); 120 | signal s_stage0_output05 : std_logic_vector(47 downto 0); 121 | signal s_stage0_output06 : std_logic_vector(47 downto 0); 122 | signal s_stage0_output07 : std_logic_vector(47 downto 0); 123 | signal s_stage0_output08 : std_logic_vector(47 downto 0); 124 | signal s_stage0_output09 : std_logic_vector(47 downto 0); 125 | signal s_stage0_output10 : std_logic_vector(47 downto 0); 126 | 127 | signal s_stage1_output00 : std_logic_vector(47 downto 0); 128 | signal s_stage1_output01 : std_logic_vector(47 downto 0); 129 | signal s_stage1_output02 : std_logic_vector(47 downto 0); 130 | signal s_stage1_output03 : std_logic_vector(47 downto 0); 131 | signal s_stage1_output04 : std_logic_vector(47 downto 0); 132 | signal s_stage1_output05 : std_logic_vector(47 downto 0); 133 | 134 | signal s_stage2_output00 : std_logic_vector(47 downto 0); 135 | signal s_stage2_output01 : std_logic_vector(47 downto 0); 136 | signal s_stage2_output02 : std_logic_vector(47 downto 0); 137 | 138 | signal s_stage3_output00 : std_logic_vector(47 downto 0); 139 | signal s_stage3_output01 : std_logic_vector(47 downto 0); 140 | 141 | signal s_pp_sum_p : std_logic; 142 | signal s_pp_sum_g : std_logic; 143 | signal s_pp_sum_o : std_logic_vector(63 downto 0); 144 | 145 | signal s_in_01 : std_logic_vector(23 downto 0); 146 | signal s_in_02 : std_logic_vector(23 downto 0); 147 | signal s_in_03 : std_logic_vector(23 downto 0); 148 | signal s_in_04 : std_logic_vector(23 downto 0); 149 | signal s_in_05 : std_logic_vector(23 downto 0); 150 | signal s_in_06 : std_logic_vector(23 downto 0); 151 | signal s_in_07 : std_logic_vector(23 downto 0); 152 | signal s_in_08 : std_logic_vector(23 downto 0); 153 | signal s_in_09 : std_logic_vector(23 downto 0); 154 | signal s_in_10 : std_logic_vector(23 downto 0); 155 | signal s_in_11 : std_logic_vector(23 downto 0); 156 | signal s_in_12 : std_logic_vector(23 downto 0); 157 | signal s_in_13 : std_logic_vector(23 downto 0); 158 | signal s_in_14 : std_logic_vector(23 downto 0); 159 | signal s_in_15 : std_logic_vector(23 downto 0); 160 | signal s_in_16 : std_logic_vector(23 downto 0); 161 | signal s_in_17 : std_logic_vector(23 downto 0); 162 | signal s_in_18 : std_logic_vector(23 downto 0); 163 | signal s_in_19 : std_logic_vector(23 downto 0); 164 | signal s_in_20 : std_logic_vector(23 downto 0); 165 | signal s_in_21 : std_logic_vector(23 downto 0); 166 | signal s_in_22 : std_logic_vector(23 downto 0); 167 | signal s_in_23 : std_logic_vector(23 downto 0); 168 | 169 | constant zeros : std_logic_vector(24 downto 0) := (others => '0'); 170 | 171 | signal s_fa : std_logic_vector(23 downto 0); 172 | signal s_fb : std_logic_vector(23 downto 0); 173 | 174 | function or_reduce( V: std_logic_vector ) 175 | return std_ulogic is variable result: std_ulogic; 176 | begin 177 | for i in V'range loop 178 | if i = V'left then 179 | result := V(i); 180 | else 181 | result := result OR V(i); 182 | end if; 183 | exit when result = '1'; 184 | end loop; 185 | return result; 186 | end or_reduce; 187 | 188 | begin -- arch 189 | 190 | C_H <= '1' when s_pp_sum_o(48) = '1' else '0'; 191 | 192 | O_H <= zeros & A_H when B_H = zeros(22 downto 0) else 193 | zeros & B_H when A_H = zeros(22 downto 0) else 194 | s_pp_sum_o(47 downto 0) ;-- when s_pp_sum_o(46) = '0' else 195 | --(others => '1'); 196 | 197 | s_fa <= or_reduce(A_EXP) & A_H; 198 | s_fb <= or_reduce(B_EXP) & B_H; 199 | 200 | pp_00(47 downto 24) <= (others => '0'); 201 | pp_00(23 downto 0) <= s_fa when B_H(0) = '1' else (others => '0'); 202 | 203 | s_shift_01 <= "00001" when B_H(1) = '1' else "00000"; 204 | s_shift_02 <= "00010" when B_H(2) = '1' else "00000"; 205 | s_shift_03 <= "00011" when B_H(3) = '1' else "00000"; 206 | s_shift_04 <= "00100" when B_H(4) = '1' else "00000"; 207 | s_shift_05 <= "00101" when B_H(5) = '1' else "00000"; 208 | s_shift_06 <= "00110" when B_H(6) = '1' else "00000"; 209 | s_shift_07 <= "00111" when B_H(7) = '1' else "00000"; 210 | s_shift_08 <= "01000" when B_H(8) = '1' else "00000"; 211 | s_shift_09 <= "01001" when B_H(9) = '1' else "00000"; 212 | s_shift_10 <= "01010" when B_H(10) = '1' else "00000"; 213 | s_shift_11 <= "01011" when B_H(11) = '1' else "00000"; 214 | s_shift_12 <= "01100" when B_H(12) = '1' else "00000"; 215 | s_shift_13 <= "01101" when B_H(13) = '1' else "00000"; 216 | s_shift_14 <= "01110" when B_H(14) = '1' else "00000"; 217 | s_shift_15 <= "01111" when B_H(15) = '1' else "00000"; 218 | s_shift_16 <= "10000" when B_H(16) = '1' else "00000"; 219 | s_shift_17 <= "10001" when B_H(17) = '1' else "00000"; 220 | s_shift_18 <= "10010" when B_H(18) = '1' else "00000"; 221 | s_shift_19 <= "10011" when B_H(19) = '1' else "00000"; 222 | s_shift_20 <= "10100" when B_H(20) = '1' else "00000"; 223 | s_shift_21 <= "10101" when B_H(21) = '1' else "00000"; 224 | s_shift_22 <= "10110" when B_H(22) = '1' else "00000"; 225 | s_shift_23 <= "10111" when s_fb(23) = '1' else "00000"; 226 | 227 | s_in_01 <= s_fa when B_H(1) = '1' else (others => '0'); 228 | s_in_02 <= s_fa when B_H(2) = '1' else (others => '0'); 229 | s_in_03 <= s_fa when B_H(3) = '1' else (others => '0'); 230 | s_in_04 <= s_fa when B_H(4) = '1' else (others => '0'); 231 | s_in_05 <= s_fa when B_H(5) = '1' else (others => '0'); 232 | s_in_06 <= s_fa when B_H(6) = '1' else (others => '0'); 233 | s_in_07 <= s_fa when B_H(7) = '1' else (others => '0'); 234 | s_in_08 <= s_fa when B_H(8) = '1' else (others => '0'); 235 | s_in_09 <= s_fa when B_H(9) = '1' else (others => '0'); 236 | s_in_10 <= s_fa when B_H(10) = '1' else (others => '0'); 237 | s_in_11 <= s_fa when B_H(11) = '1' else (others => '0'); 238 | s_in_12 <= s_fa when B_H(12) = '1' else (others => '0'); 239 | s_in_13 <= s_fa when B_H(13) = '1' else (others => '0'); 240 | s_in_14 <= s_fa when B_H(14) = '1' else (others => '0'); 241 | s_in_15 <= s_fa when B_H(15) = '1' else (others => '0'); 242 | s_in_16 <= s_fa when B_H(16) = '1' else (others => '0'); 243 | s_in_17 <= s_fa when B_H(17) = '1' else (others => '0'); 244 | s_in_18 <= s_fa when B_H(18) = '1' else (others => '0'); 245 | s_in_19 <= s_fa when B_H(19) = '1' else (others => '0'); 246 | s_in_20 <= s_fa when B_H(20) = '1' else (others => '0'); 247 | s_in_21 <= s_fa when B_H(21) = '1' else (others => '0'); 248 | s_in_22 <= s_fa when B_H(22) = '1' else (others => '0'); 249 | s_in_23 <= s_fa when s_fb(23) = '1' else (others => '0'); 250 | 251 | SHIFT_01 : LEFT_SHIFTER 252 | port map ( 253 | A => s_in_01, 254 | S => s_shift_01, 255 | O => pp_01 256 | ); 257 | 258 | SHIFT_02 : LEFT_SHIFTER 259 | port map ( 260 | A => s_in_02, 261 | S => s_shift_02, 262 | O => pp_02 263 | ); 264 | 265 | SHIFT_03 : LEFT_SHIFTER 266 | port map ( 267 | A => s_in_03, 268 | S => s_shift_03, 269 | O => pp_03 270 | ); 271 | 272 | SHIFT_04 : LEFT_SHIFTER 273 | port map ( 274 | A => s_in_04, 275 | S => s_shift_04, 276 | O => pp_04 277 | ); 278 | 279 | SHIFT_05 : LEFT_SHIFTER 280 | port map ( 281 | A => s_in_05, 282 | S => s_shift_05, 283 | O => pp_05 284 | ); 285 | 286 | SHIFT_06 : LEFT_SHIFTER 287 | port map ( 288 | A => s_in_06, 289 | S => s_shift_06, 290 | O => pp_06 291 | ); 292 | 293 | SHIFT_07 : LEFT_SHIFTER 294 | port map ( 295 | A => s_in_07, 296 | S => s_shift_07, 297 | O => pp_07 298 | ); 299 | 300 | SHIFT_08 : LEFT_SHIFTER 301 | port map ( 302 | A => s_in_08, 303 | S => s_shift_08, 304 | O => pp_08 305 | ); 306 | 307 | SHIFT_09 : LEFT_SHIFTER 308 | port map ( 309 | A => s_in_09, 310 | S => s_shift_09, 311 | O => pp_09 312 | ); 313 | 314 | SHIFT_10 : LEFT_SHIFTER 315 | port map ( 316 | A => s_in_10, 317 | S => s_shift_10, 318 | O => pp_10 319 | ); 320 | 321 | SHIFT_11 : LEFT_SHIFTER 322 | port map ( 323 | A => s_in_11, 324 | S => s_shift_11, 325 | O => pp_11 326 | ); 327 | 328 | SHIFT_12 : LEFT_SHIFTER 329 | port map ( 330 | A => s_in_12, 331 | S => s_shift_12, 332 | O => pp_12 333 | ); 334 | 335 | SHIFT_13 : LEFT_SHIFTER 336 | port map ( 337 | A => s_in_13, 338 | S => s_shift_13, 339 | O => pp_13 340 | ); 341 | 342 | SHIFT_14 : LEFT_SHIFTER 343 | port map ( 344 | A => s_in_14, 345 | S => s_shift_14, 346 | O => pp_14 347 | ); 348 | 349 | SHIFT_15 : LEFT_SHIFTER 350 | port map ( 351 | A => s_in_15, 352 | S => s_shift_15, 353 | O => pp_15 354 | ); 355 | 356 | SHIFT_16 : LEFT_SHIFTER 357 | port map ( 358 | A => s_in_16, 359 | S => s_shift_16, 360 | O => pp_16 361 | ); 362 | 363 | SHIFT_17 : LEFT_SHIFTER 364 | port map ( 365 | A => s_in_17, 366 | S => s_shift_17, 367 | O => pp_17 368 | ); 369 | 370 | SHIFT_18 : LEFT_SHIFTER 371 | port map ( 372 | A => s_in_18, 373 | S => s_shift_18, 374 | O => pp_18 375 | ); 376 | 377 | SHIFT_19 : LEFT_SHIFTER 378 | port map ( 379 | A => s_in_19, 380 | S => s_shift_19, 381 | O => pp_19 382 | ); 383 | 384 | SHIFT_20 : LEFT_SHIFTER 385 | port map ( 386 | A => s_in_20, 387 | S => s_shift_20, 388 | O => pp_20 389 | ); 390 | 391 | SHIFT_21 : LEFT_SHIFTER 392 | port map ( 393 | A => s_in_21, 394 | S => s_shift_21, 395 | O => pp_21 396 | ); 397 | 398 | SHIFT_22 : LEFT_SHIFTER 399 | port map ( 400 | A => s_in_22, 401 | S => s_shift_22, 402 | O => pp_22 403 | ); 404 | 405 | SHIFT_23 : LEFT_SHIFTER 406 | port map ( 407 | A => s_in_23, 408 | S => s_shift_23, 409 | O => pp_23 410 | ); 411 | 412 | STAGE0_RRU7TO3_0 : RRU7_3 413 | port map ( 414 | A_VAL => pp_00, 415 | B_VAL => pp_01, 416 | C_VAL => pp_02, 417 | D_VAL => pp_03, 418 | E_VAL => pp_04, 419 | F_VAL => pp_05, 420 | G_VAL => pp_06, 421 | F0_VAL => s_stage0_output00, 422 | F1_VAL => s_stage0_output01, 423 | F2_VAL => s_stage0_output02 424 | ); 425 | 426 | STAGE0_RRU7TO3_1 : RRU7_3 427 | port map ( 428 | A_VAL => pp_07, 429 | B_VAL => pp_08, 430 | C_VAL => pp_09, 431 | D_VAL => pp_10, 432 | E_VAL => pp_11, 433 | F_VAL => pp_12, 434 | G_VAL => pp_13, 435 | F0_VAL => s_stage0_output03, 436 | F1_VAL => s_stage0_output04, 437 | F2_VAL => s_stage0_output05 438 | ); 439 | 440 | STAGE0_RRU7TO3_2 : RRU7_3 441 | port map ( 442 | A_VAL => pp_14, 443 | B_VAL => pp_15, 444 | C_VAL => pp_16, 445 | D_VAL => pp_17, 446 | E_VAL => pp_18, 447 | F_VAL => pp_19, 448 | G_VAL => pp_20, 449 | F0_VAL => s_stage0_output06, 450 | F1_VAL => s_stage0_output07, 451 | F2_VAL => s_stage0_output08 452 | ); 453 | 454 | STAGE0_RRU3TO2_0 : RRU3_2 455 | port map ( 456 | A_VAL => pp_21, 457 | B_VAL => pp_22, 458 | C_VAL => pp_23, 459 | F0_VAL => s_stage0_output09, 460 | F1_VAL => s_stage0_output10 461 | ); 462 | 463 | STAGE1_RRU7TO3_0 : RRU7_3 464 | port map ( 465 | A_VAL => s_stage0_output00, 466 | B_VAL => s_stage0_output01, 467 | C_VAL => s_stage0_output02, 468 | D_VAL => s_stage0_output03, 469 | E_VAL => s_stage0_output04, 470 | F_VAL => s_stage0_output05, 471 | G_VAL => s_stage0_output06, 472 | F0_VAL => s_stage1_output00, 473 | F1_VAL => s_stage1_output01, 474 | F2_VAL => s_stage1_output02 475 | ); 476 | 477 | STAGE1_RRU7TO3_1 : RRU7_3 478 | port map ( 479 | A_VAL => s_stage0_output07, 480 | B_VAL => s_stage0_output08, 481 | C_VAL => s_stage0_output09, 482 | D_VAL => s_stage0_output10, 483 | E_VAL => (others => '0'), 484 | F_VAL => (others => '0'), 485 | G_VAL => (others => '0'), 486 | F0_VAL => s_stage1_output03, 487 | F1_VAL => s_stage1_output04, 488 | F2_VAL => s_stage1_output05 489 | ); 490 | 491 | STAGE2_RRU7TO3_0 : RRU7_3 492 | port map ( 493 | A_VAL => s_stage1_output00, 494 | B_VAL => s_stage1_output01, 495 | C_VAL => s_stage1_output02, 496 | D_VAL => s_stage1_output03, 497 | E_VAL => s_stage1_output04, 498 | F_VAL => s_stage1_output05, 499 | G_VAL => (others => '0'), 500 | F0_VAL => s_stage2_output00, 501 | F1_VAL => s_stage2_output01, 502 | F2_VAL => s_stage2_output02 503 | ); 504 | 505 | STAGE3_RRU3TO2_0 : RRU3_2 506 | port map ( 507 | A_VAL => s_stage2_output00, 508 | B_VAL => s_stage2_output01, 509 | C_VAL => s_stage2_output02, 510 | F0_VAL => s_stage3_output00, 511 | F1_VAL => s_stage3_output01 512 | ); 513 | 514 | ADD_PP_ARRAY : ADDER64 515 | port map ( 516 | A(63 downto 48) => (others => '0'), 517 | A(47 downto 0) => s_stage3_output00, 518 | B(63 downto 48) => (others => '0'), 519 | B(47 downto 0) => s_stage3_output01, 520 | C => '0', 521 | O => s_pp_sum_o, 522 | G => s_pp_sum_g, 523 | P => s_pp_sum_p 524 | ); 525 | 526 | end arch; 527 | -------------------------------------------------------------------------------- /ieee-754-multiplier/post_norm.vhd: -------------------------------------------------------------------------------- 1 | -- File : post_norm.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity post_norm is 7 | port ( 8 | N_MANT : in std_logic_vector(47 downto 0); 9 | ADJ : out std_logic_vector(4 downto 0); 10 | O_MANT : out std_logic_vector(22 downto 0) 11 | ); 12 | end post_norm; 13 | 14 | architecture arch of post_norm is 15 | 16 | signal s_a_shift : std_logic_vector(23 downto 0); 17 | signal s_s_shift : std_logic_vector(4 downto 0); 18 | 19 | begin -- arch 20 | 21 | ADJ <= B"0_0001" when N_MANT(47) = '1' else 22 | B"0_0000"; 23 | 24 | O_MANT <= s_a_shift(22 downto 0); 25 | 26 | s_a_shift <= N_MANT(47 downto 24) when N_MANT(47) = '1' else 27 | N_MANT(46 downto 23) when N_MANT(46) = '1' else 28 | N_MANT(45 downto 22) when N_MANT(45) = '1' else 29 | N_MANT(44 downto 21) when N_MANT(44) = '1' else 30 | N_MANT(43 downto 20) when N_MANT(43) = '1' else 31 | N_MANT(42 downto 19) when N_MANT(42) = '1' else 32 | N_MANT(41 downto 18) when N_MANT(41) = '1' else 33 | N_MANT(40 downto 17) when N_MANT(40) = '1' else 34 | N_MANT(39 downto 16) when N_MANT(39) = '1' else 35 | N_MANT(38 downto 15) when N_MANT(38) = '1' else 36 | N_MANT(37 downto 14) when N_MANT(37) = '1' else 37 | N_MANT(36 downto 13) when N_MANT(36) = '1' else 38 | N_MANT(35 downto 12) when N_MANT(35) = '1' else 39 | N_MANT(34 downto 11) when N_MANT(34) = '1' else 40 | N_MANT(33 downto 10) when N_MANT(33) = '1' else 41 | N_MANT(32 downto 9) when N_MANT(32) = '1' else 42 | N_MANT(31 downto 8) when N_MANT(31) = '1' else 43 | N_MANT(30 downto 7) when N_MANT(30) = '1' else 44 | N_MANT(29 downto 6) when N_MANT(29) = '1' else 45 | N_MANT(28 downto 5) when N_MANT(28) = '1' else 46 | N_MANT(27 downto 4) when N_MANT(27) = '1' else 47 | N_MANT(26 downto 3) when N_MANT(26) = '1' else 48 | N_MANT(25 downto 2) when N_MANT(25) = '1' else 49 | N_MANT(24 downto 1) when N_MANT(24) = '1' else 50 | N_MANT(23 downto 0); 51 | end arch; 52 | -------------------------------------------------------------------------------- /ieee-754-multiplier/right_shifter.vhd: -------------------------------------------------------------------------------- 1 | -- File : right_shifter.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity right_shifter is 7 | port ( 8 | A : in std_logic_vector(22 downto 0); 9 | S : in std_logic_vector(4 downto 0); 10 | O : out std_logic_vector(22 downto 0) 11 | ); 12 | end right_shifter; 13 | 14 | architecture arch of right_shifter is 15 | 16 | component x_2_to_1_mux_46 is 17 | port ( 18 | A : in std_logic_vector(47 downto 0); 19 | B : in std_logic_vector(47 downto 0); 20 | S : in std_logic; 21 | O : out std_logic_vector(47 downto 0) 22 | ); 23 | end component x_2_to_1_mux_46; 24 | 25 | signal s_8_to_16 : std_logic_vector(47 downto 0); 26 | signal s_4_to_8 : std_logic_vector(47 downto 0); 27 | signal s_2_to_4 : std_logic_vector(47 downto 0); 28 | signal s_1_to_2 : std_logic_vector(47 downto 0); 29 | 30 | signal s_dont_care : std_logic_vector(24 downto 0); 31 | 32 | begin -- arch 33 | 34 | -- 1-bit shift 35 | X21M_1 : x_2_to_1_mux_46 36 | port map ( 37 | A(47 downto 23) => (others => '0'), 38 | A(22 downto 0) => A, 39 | B(47 downto 22) => (others => '0'), 40 | B(21 downto 0) => A(22 downto 1), 41 | S => S(0), 42 | O => s_1_to_2 43 | ); 44 | 45 | -- 2-bit shift 46 | X21M_2 : x_2_to_1_mux_46 47 | port map ( 48 | A => s_1_to_2, 49 | B(47 downto 21) => (others => '0'), 50 | B(20 downto 0) => s_1_to_2(22 downto 2), 51 | S => S(1), 52 | O => s_2_to_4 53 | ); 54 | 55 | -- 4-bit shift 56 | X21M_4 : x_2_to_1_mux_46 57 | port map ( 58 | A => s_2_to_4, 59 | B(47 downto 19) => (others => '0'), 60 | B(18 downto 0) => s_2_to_4(22 downto 4), 61 | S => S(2), 62 | O => s_4_to_8 63 | ); 64 | 65 | -- 8-bit shift 66 | X21M_8 : x_2_to_1_mux_46 67 | port map ( 68 | A => s_4_to_8, 69 | B(47 downto 15) => (others => '0'), 70 | B(14 downto 0) => s_4_to_8(22 downto 8), 71 | S => S(3), 72 | O => s_8_to_16 73 | ); 74 | 75 | -- 16-bit shift 76 | X21M_16 : x_2_to_1_mux_46 77 | port map ( 78 | A => s_8_to_16, 79 | B(47 downto 7) => (others => '0'), 80 | B(6 downto 0) => s_8_to_16(22 downto 16), 81 | S => S(4), 82 | O(47 downto 23) => s_dont_care, 83 | O(22 downto 0) => O 84 | ); 85 | 86 | end arch; 87 | -------------------------------------------------------------------------------- /ieee-754-multiplier/sub_8.vhd: -------------------------------------------------------------------------------- 1 | -- File : sub_8.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity sub_8 is 7 | port ( 8 | A : in std_logic_vector(7 downto 0); 9 | B : in std_logic_vector(7 downto 0); 10 | D : out std_logic_vector(7 downto 0) 11 | ); 12 | end sub_8; 13 | 14 | architecture arch of sub_8 is 15 | 16 | signal B_cmpl : std_logic_vector(7 downto 0); 17 | signal P : std_logic_vector(7 downto 0); 18 | signal G : std_logic_vector(7 downto 0); 19 | signal C : std_logic_vector(7 downto 0); 20 | 21 | begin -- arch 22 | 23 | B_cmpl <= not B; 24 | P <= A xor B_cmpl; 25 | G <= A and B_cmpl; 26 | C(0) <= '1'; 27 | 28 | D(7) <= P(7) xor C(7); 29 | D(6) <= P(6) xor C(6); 30 | D(5) <= P(5) xor C(5); 31 | D(4) <= P(4) xor C(4); 32 | D(3) <= P(3) xor C(3); 33 | D(2) <= P(2) xor C(2); 34 | D(1) <= P(1) xor C(1); 35 | D(0) <= P(0) xor C(0); 36 | 37 | C(1) <= G(0) or 38 | (P(0)); 39 | C(2) <= G(1) or 40 | (P(1) and G(0)) or 41 | (P(1) and P(0)); 42 | C(3) <= G(2) or 43 | (P(2) and G(1)) or 44 | (P(2) and P(1) and G(0)) or 45 | (P(2) and P(1) and P(0)); 46 | C(4) <= G(3) or 47 | (P(3) and G(2)) or 48 | (P(3) and P(2) and G(1)) or 49 | (P(3) and P(2) and P(1) and G(0)) or 50 | (P(3) and P(2) and P(1) and P(0)); 51 | C(5) <= G(4) or 52 | (P(4) and G(3)) or 53 | (P(4) and P(3) and G(2)) or 54 | (P(4) and P(3) and P(2) and G(1)) or 55 | (P(4) and P(3) and P(2) and P(1) and G(0)) or 56 | (P(4) and P(3) and P(2) and P(1) and P(0)); 57 | C(6) <= G(5) or 58 | (P(5) and G(4)) or 59 | (P(5) and P(4) and G(3)) or 60 | (P(5) and P(4) and P(3) and G(2)) or 61 | (P(5) and P(4) and P(3) and P(2) and G(1)) or 62 | (P(5) and P(4) and P(3) and P(2) and P(1) and G(0)) or 63 | (P(5) and P(4) and P(3) and P(2) and P(1) and P(0)); 64 | C(7) <= G(6) or 65 | (P(6) and G(5)) or 66 | (P(6) and P(5) and G(4)) or 67 | (P(6) and P(5) and P(4) and G(3)) or 68 | (P(6) and P(5) and P(4) and P(3) and G(2)) or 69 | (P(6) and P(5) and P(4) and P(3) and P(2) and G(1)) or 70 | (P(6) and P(5) and P(4) and P(3) and P(2) and P(1) and G(0)) or 71 | (P(6) and P(5) and P(4) and P(3) and P(2) and P(1) and P(0)); 72 | 73 | end arch; 74 | -------------------------------------------------------------------------------- /ieee-754-multiplier/tb_add_16.vhd: -------------------------------------------------------------------------------- 1 | -- File : tb_add_16.vhd 2 | 3 | library IEEE; 4 | use IEEE.STD_LOGIC_1164.all; 5 | 6 | entity TB_ADDER8 is 7 | end entity TB_ADDER8; 8 | 9 | architecture TB_ADDER8 of TB_ADDER8 is 10 | 11 | component add_16 is 12 | port ( 13 | A : in std_logic_vector (15 downto 0); 14 | B : in std_logic_vector (15 downto 0); 15 | C : in std_logic; 16 | O : out std_logic_vector (15 downto 0); 17 | G : out std_logic; 18 | P : out std_logic); 19 | end component add_16; 20 | 21 | signal X_CIN_H : std_logic; 22 | signal X_A_VAL : std_logic_vector (15 downto 0); 23 | signal X_B_VAL : std_logic_vector (15 downto 0); 24 | signal X_F_OUT : std_logic_vector (15 downto 0); 25 | signal X_G_H : std_logic; 26 | signal X_P_H : std_logic; 27 | 28 | begin 29 | 30 | UUT : ADD_16 31 | port map ( 32 | C => X_CIN_H, 33 | A => X_A_VAL, 34 | B => X_B_VAL, 35 | O => X_F_OUT, 36 | G => X_G_H, 37 | P => X_P_H 38 | ); 39 | 40 | STIMULUS_PROC : 41 | process 42 | begin 43 | X_A_VAL <= X"0000"; X_B_VAL <= X"0000"; X_CIN_H <= '0'; 44 | wait for 100 ns; 45 | X_A_VAL <= X"0000"; X_B_VAL <= X"0000"; X_CIN_H <= '1'; 46 | wait for 100 ns; 47 | X_A_VAL <= X"00FF"; X_B_VAL <= X"00FF"; X_CIN_H <= '0'; 48 | wait for 100 ns; 49 | X_A_VAL <= X"00FF"; X_B_VAL <= X"00FF"; X_CIN_H <= '1'; 50 | wait for 100 ns; 51 | X_A_VAL <= X"0055"; X_B_VAL <= X"00AA"; X_CIN_H <= '0'; 52 | wait for 100 ns; 53 | X_A_VAL <= X"0055"; X_B_VAL <= X"00AA"; X_CIN_H <= '1'; 54 | wait for 100 ns; 55 | X_A_VAL <= X"0355"; X_B_VAL <= X"01AA"; X_CIN_H <= '1'; 56 | wait for 100 ns; 57 | X_A_VAL <= X"FFFF"; X_B_VAL <= X"FFFF"; X_CIN_H <= '0'; 58 | wait for 100 ns; 59 | end process; 60 | 61 | end architecture TB_ADDER8; 62 | -------------------------------------------------------------------------------- /ieee-754-multiplier/tb_mult_32.vhd: -------------------------------------------------------------------------------- 1 | library IEEE; 2 | use IEEE.STD_LOGIC_1164.all; 3 | use IEEE.STD_LOGIC_UNSIGNED.all; 4 | use STD.TEXTIO.all; 5 | use IEEE.STD_LOGIC_TEXTIO.all; 6 | 7 | entity TB_FP_MULT is 8 | end entity TB_FP_MULT; 9 | 10 | use WORK.all; 11 | 12 | architecture TB_FP_MULT of TB_FP_MULT is 13 | 14 | component FP_MULT is 15 | port ( 16 | A_H : in STD_LOGIC_VECTOR ( 31 downto 0 ); 17 | B_H : in STD_LOGIC_VECTOR ( 31 downto 0 ); 18 | O_H : out STD_LOGIC_VECTOR ( 31 downto 0 ) 19 | ); 20 | end component FP_MULT; 21 | 22 | signal A_INPUT : STD_LOGIC_VECTOR ( 31 downto 0 ); 23 | signal B_INPUT : STD_LOGIC_VECTOR ( 31 downto 0 ); 24 | signal F_DETAILED : STD_LOGIC_VECTOR ( 31 downto 0 ); 25 | 26 | alias A_EXP : STD_LOGIC_VECTOR ( 7 downto 0 ) is A_INPUT ( 30 downto 23 ); 27 | alias B_EXP : STD_LOGIC_VECTOR ( 7 downto 0 ) is B_INPUT ( 30 downto 23 ); 28 | 29 | signal A_EXP_INT : INTEGER; 30 | signal B_EXP_INT : INTEGER; 31 | signal R_EXP_INT : INTEGER; 32 | 33 | signal CLOCK : STD_LOGIC; 34 | signal CYCLE : INTEGER := 0; 35 | 36 | begin 37 | UUT_DETAILED: FP_MULT 38 | port map ( 39 | A_H => A_INPUT, 40 | B_H => B_INPUT, 41 | O_H => F_DETAILED 42 | ); 43 | 44 | CYCLE_PROC: 45 | process 46 | begin 47 | CLOCK <= '1'; 48 | wait for 100 ns; 49 | CLOCK <= '0'; 50 | wait for 100 ns; 51 | CYCLE <= CYCLE + 1; 52 | end process; 53 | 54 | A_EXP_INT <= CONV_INTEGER ( A_EXP ) - 127 ; 55 | B_EXP_INT <= CONV_INTEGER ( B_EXP ) - 127 ; 56 | R_EXP_INT <= A_EXP_INT + B_EXP_INT; 57 | 58 | DATA_PROC: 59 | process ( CLOCK ) is 60 | type DATA_STOR is array ( 0 to 31 ) of STD_LOGIC_VECTOR ( 31 downto 0 ); 61 | constant A_VALS : DATA_STOR := ( 62 | X"3D800000", X"3F800000", X"BF800000", X"3F8F0000", -- 0, 1, 2, 3 63 | X"BF800000", X"3F800000", X"3F000000", X"3F890000", -- 4, 5, 6, 7 64 | X"BF000000", X"42C80000", X"42C80000", X"C2C80000", -- 8, 9, 10, 11 65 | X"41D80000", X"C1D80000", X"4620F800", X"4620F800", -- 12, 13, 14, 15 66 | X"49791900", X"49791900", X"42CA0000", X"C1D80000", -- 16, 17, 18, 19 67 | X"C2CE0000", X"42CE0000", X"497E07A0", X"C97E07A0", -- 20, 21, 22, 23 68 | X"1F0AC723", X"269117C6", X"269FF7C6", X"5F0AC723", -- 24, 25, 26, 27 69 | X"733A4000", X"E85B79A2", X"41700000", X"4640E400" -- 28, 29, 30, 31 70 | ); 71 | constant B_VALS : DATA_STOR := ( 72 | X"3D000000", X"3F800000", X"3F800000", X"BF800000", 73 | X"BF800000", X"3F000000", X"3F870000", X"BF00A000", 74 | X"3F800000", X"3F800000", X"BF800000", X"C0400000", 75 | X"43110000", X"43110000", X"3E800000", X"BE800000", 76 | X"42CC0000", X"C2CC0000", X"49791900", X"49FCB8F0", 77 | X"448FC000", X"C481C000", X"497E07B0", X"497E07B0", 78 | X"1E9FF7C6", X"5F0AC723", X"269FF7C6", X"5F0AC723", 79 | X"685B79A2", X"733A4000", X"43988000", X"45D42800" 80 | ); 81 | variable FIRST : BOOLEAN := TRUE; 82 | 83 | variable INDEX : INTEGER := 0; 84 | 85 | begin 86 | if RISING_EDGE ( CLOCK ) or (FIRST = TRUE ) then 87 | INDEX := CYCLE mod 32; 88 | A_INPUT <= A_VALS(INDEX); 89 | B_INPUT <= B_VALS(INDEX); 90 | FIRST := FALSE; 91 | end if; 92 | end process; 93 | 94 | 95 | RECORDING_PROC: 96 | process ( CLOCK ) is 97 | file OUT_FILE: TEXT open WRITE_MODE is "outputvals.txt"; 98 | variable BUF : LINE; -- set BUF up to send line 99 | constant STR : STRING ( 1 to 3 ) := " "; 100 | variable TM : TIME; 101 | begin 102 | if CLOCK'EVENT and CLOCK = '1' and CYCLE > 1 then -- if rising edge 103 | WRITE ( BUF, CYCLE ); 104 | WRITE ( BUF, STR ); 105 | HWRITE ( BUF, A_INPUT ); 106 | WRITE ( BUF, STR); 107 | HWRITE ( BUF, B_INPUT ); 108 | WRITE ( BUF, STR); 109 | WRITE ( BUF, STR); 110 | HWRITE ( BUF, F_DETAILED ); 111 | WRITE ( BUF, STR); 112 | WRITE ( BUF, NOW); 113 | WRITE ( BUF, STR); 114 | TM := F_DETAILED'LAST_EVENT; 115 | WRITE ( BUF, TM ); 116 | WRITELINE (OUT_FILE, BUF); -- and send to file 117 | end if; 118 | end process; 119 | 120 | end TB_FP_MULT; 121 | -------------------------------------------------------------------------------- /ieee-754-multiplier/tb_right_shifter.vhd: -------------------------------------------------------------------------------- 1 | -- File : tb_right_shifter.vhd 2 | 3 | library IEEE; 4 | use IEEE.STD_LOGIC_1164.all; 5 | 6 | entity tb_right_shifter is 7 | end entity tb_right_shifter; 8 | 9 | architecture tb_right_shifter of tb_right_shifter is 10 | 11 | component right_shifter is 12 | port ( 13 | A : in std_logic_vector(22 downto 0); 14 | S : in std_logic_vector(4 downto 0); 15 | O : out std_logic_vector(22 downto 0) 16 | ); 17 | end component right_shifter; 18 | 19 | signal X_A_VAL : std_logic_vector(22 downto 0); 20 | signal X_S_VAL : std_logic_vector(4 downto 0); 21 | signal X_O_OUT : std_logic_vector(22 downto 0); 22 | 23 | begin 24 | UUT : right_shifter 25 | port map ( 26 | A => X_A_VAL, 27 | S => X_S_VAL, 28 | O => X_O_OUT); 29 | 30 | -- 01_0001_1100_1011_0100_1101 31 | -- 11_1110_1111_1111_1110_0100 32 | -- 10_0101_0101_0110_0001_1111 33 | -- 10_1100_0101_1101_0001_0100 34 | 35 | STIMULUS_PROC : 36 | process 37 | begin 38 | X_A_VAL <= B"000_0101_0100_0010_1000_0001"; 39 | X_S_VAL <= B"0_0001"; 40 | wait for 100 ns; 41 | 42 | X_A_VAL <= B"000_0000_0000_0000_0001_0111"; 43 | X_S_VAL <= B"0_0010"; 44 | wait for 100 ns; 45 | 46 | X_A_VAL <= B"000_1000_1000_1000_0001_1010"; 47 | X_S_VAL <= B"0_0100"; 48 | wait for 100 ns; 49 | 50 | X_A_VAL <= B"010_0001_1100_1001_1111_0101"; 51 | X_S_VAL <= B"0_1000"; 52 | wait for 100 ns; 53 | 54 | X_A_VAL <= B"101_1101_1010_1011_1010_0000"; 55 | X_S_VAL <= B"1_0000"; 56 | wait for 100 ns; 57 | 58 | X_A_VAL <= B"010_1100_0001_0101_0101_0001"; 59 | X_S_VAL <= B"0_0011"; 60 | wait for 100 ns; 61 | 62 | X_A_VAL <= B"010_0111_0010_1001_1111_0000"; 63 | X_S_VAL <= B"0_0101"; 64 | wait for 100 ns; 65 | 66 | X_A_VAL <= B"001_0000_0001_0110_0100_1111"; 67 | X_S_VAL <= B"0_0110"; 68 | wait for 100 ns; 69 | end process; 70 | 71 | end architecture tb_right_shifter; 72 | -------------------------------------------------------------------------------- /ieee-754-multiplier/vhd.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/ieee-754-multiplier/vhd.pdf -------------------------------------------------------------------------------- /ieee-754-multiplier/x_2_to_1_mux.vhd: -------------------------------------------------------------------------------- 1 | -- File : x_2_to_1_mux.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity x_2_to_1_mux is 7 | port ( 8 | A : in std_logic_vector(47 downto 0); 9 | B : in std_logic_vector(47 downto 0); 10 | S : in std_logic; 11 | O : out std_logic_vector(47 downto 0) 12 | ); 13 | end x_2_to_1_mux; 14 | 15 | architecture arch of x_2_to_1_mux is 16 | 17 | begin -- arch 18 | 19 | with S select 20 | O <= 21 | A when '0', 22 | B when '1', 23 | (others => 'X') when others; 24 | 25 | end arch; 26 | -------------------------------------------------------------------------------- /ieee-754-multiplier/x_2_to_1_mux_46.vhd: -------------------------------------------------------------------------------- 1 | -- File : x_2_to_1_mux_46.vhd 2 | 3 | library ieee; 4 | use ieee.std_logic_1164.all; 5 | 6 | entity x_2_to_1_mux_46 is 7 | 8 | port ( 9 | A : in std_logic_vector(47 downto 0); 10 | B : in std_logic_vector(47 downto 0); 11 | S : in std_logic; 12 | O : out std_logic_vector(47 downto 0) 13 | ); 14 | 15 | end x_2_to_1_mux_46; 16 | 17 | architecture arch of x_2_to_1_mux_46 is 18 | 19 | begin -- arch 20 | 21 | with S select 22 | O <= 23 | A when '0', 24 | B when '1', 25 | (others => 'X') when others; 26 | 27 | end arch; 28 | -------------------------------------------------------------------------------- /vending-machine/design.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/vending-machine/design.pdf -------------------------------------------------------------------------------- /vending-machine/design.sxw: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/vending-machine/design.sxw -------------------------------------------------------------------------------- /vending-machine/plist.py: -------------------------------------------------------------------------------- 1 | 2 | import random 3 | 4 | prices = xrange(5, 105, 5) 5 | 6 | ls = [] 7 | 8 | for x in xrange(60): 9 | ls.append(random.choice(prices)) 10 | 11 | for x in xrange (6): 12 | for y in xrange(10): 13 | print "%s," % ls.pop(), 14 | print 15 | -------------------------------------------------------------------------------- /vending-machine/state_diagram.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/vending-machine/state_diagram.pdf -------------------------------------------------------------------------------- /vending-machine/state_diagram.scd: -------------------------------------------------------------------------------- 1 | Storage 2 | { 3 | { Format 1.33 } 4 | { GeneratedFrom TSCD-version-2.20 } 5 | { WrittenBy jmob } 6 | { WrittenOn "" } 7 | } 8 | 9 | Document 10 | { 11 | { Type "Statechart Diagram" } 12 | { Name state_diagram.scd } 13 | { Author jmob } 14 | { CreatedOn "" } 15 | { Annotation "" } 16 | { Hierarchy True } 17 | } 18 | 19 | Page 20 | { 21 | { PageOrientation Portrait } 22 | { PageSize A4 } 23 | { ShowHeaders False } 24 | { ShowFooters False } 25 | { ShowNumbers False } 26 | } 27 | 28 | Scale 29 | { 30 | { ScaleValue 1 } 31 | } 32 | 33 | # GRAPH NODES 34 | 35 | SCDOrState 1 36 | { 37 | { Name "dump_everything" } 38 | { Annotation "" } 39 | { Parent 0 } 40 | { Index "" } 41 | } 42 | 43 | SCDOrState 2 44 | { 45 | { Name "reset_stuff" } 46 | { Annotation "" } 47 | { Parent 0 } 48 | { Index "" } 49 | } 50 | 51 | SCDOrState 3 52 | { 53 | { Name "need_letter" } 54 | { Annotation "" } 55 | { Parent 0 } 56 | { Index "" } 57 | } 58 | 59 | SCDOrState 4 60 | { 61 | { Name "need_number" } 62 | { Annotation "" } 63 | { Parent 0 } 64 | { Index "" } 65 | } 66 | 67 | SCDOrState 5 68 | { 69 | { Name "sel_done" } 70 | { Annotation "" } 71 | { Parent 0 } 72 | { Index "" } 73 | } 74 | 75 | SCDOrState 6 76 | { 77 | { Name "need_change" } 78 | { Annotation "" } 79 | { Parent 0 } 80 | { Index "" } 81 | } 82 | 83 | SCDOrState 7 84 | { 85 | { Name "sel_ok" } 86 | { Annotation "" } 87 | { Parent 0 } 88 | { Index "" } 89 | } 90 | 91 | SDCDefaultState 8 92 | { 93 | { Name "" } 94 | { Annotation "" } 95 | { Parent 0 } 96 | { Index "" } 97 | } 98 | 99 | Comment 9 100 | { 101 | { Name "!is_number" } 102 | { Annotation "" } 103 | { Parent 0 } 104 | { Index "" } 105 | } 106 | 107 | Comment 10 108 | { 109 | { Name "is_number" } 110 | { Annotation "" } 111 | { Parent 0 } 112 | { Index "" } 113 | } 114 | 115 | SCDSynchronizationState 11 116 | { 117 | { Name "" } 118 | { Annotation "" } 119 | { Parent 0 } 120 | { Index "" } 121 | } 122 | 123 | Comment 12 124 | { 125 | { Name "previous_state" } 126 | { Annotation "" } 127 | { Parent 0 } 128 | { Index "" } 129 | } 130 | 131 | # GRAPH EDGES 132 | 133 | SCDTransitionEdge 13 134 | { 135 | { Name "" } 136 | { Annotation "" } 137 | { Parent 0 } 138 | { Subject1 8 } 139 | { Subject2 3 } 140 | } 141 | 142 | SCDTransitionEdge 14 143 | { 144 | { Name "" } 145 | { Annotation "" } 146 | { Parent 0 } 147 | { Subject1 4 } 148 | { Subject2 4 } 149 | } 150 | 151 | SCDTransitionEdge 15 152 | { 153 | { Name "" } 154 | { Annotation "" } 155 | { Parent 0 } 156 | { Subject1 3 } 157 | { Subject2 3 } 158 | } 159 | 160 | SCDTransitionEdge 16 161 | { 162 | { Name "!is_number" } 163 | { Annotation "" } 164 | { Parent 0 } 165 | { Subject1 3 } 166 | { Subject2 4 } 167 | } 168 | 169 | SCDTransitionEdge 17 170 | { 171 | { Name "is_number" } 172 | { Annotation "" } 173 | { Parent 0 } 174 | { Subject1 4 } 175 | { Subject2 5 } 176 | } 177 | 178 | SCDTransitionEdge 18 179 | { 180 | { Name "current_payment >= selection_price" } 181 | { Annotation "" } 182 | { Parent 0 } 183 | { Subject1 5 } 184 | { Subject2 6 } 185 | } 186 | 187 | SCDTransitionEdge 19 188 | { 189 | { Name "current_payment < selection_price" } 190 | { Annotation "" } 191 | { Parent 0 } 192 | { Subject1 6 } 193 | { Subject2 5 } 194 | } 195 | 196 | SCDTransitionEdge 20 197 | { 198 | { Name "change_given < change_need" } 199 | { Annotation "" } 200 | { Parent 0 } 201 | { Subject1 6 } 202 | { Subject2 6 } 203 | } 204 | 205 | SCDTransitionEdge 21 206 | { 207 | { Name "change_given > change_need" } 208 | { Annotation "" } 209 | { Parent 0 } 210 | { Subject1 6 } 211 | { Subject2 7 } 212 | } 213 | 214 | SCDTransitionEdge 22 215 | { 216 | { Name "always_true" } 217 | { Annotation "" } 218 | { Parent 0 } 219 | { Subject1 7 } 220 | { Subject2 3 } 221 | } 222 | 223 | SCDTransitionEdge 23 224 | { 225 | { Name "rst" } 226 | { Annotation "" } 227 | { Parent 0 } 228 | { Subject1 8 } 229 | { Subject2 2 } 230 | } 231 | 232 | SCDTransitionEdge 24 233 | { 234 | { Name "!rst" } 235 | { Annotation "" } 236 | { Parent 0 } 237 | { Subject1 8 } 238 | { Subject2 11 } 239 | } 240 | 241 | SCDTransitionEdge 25 242 | { 243 | { Name "coin_return" } 244 | { Annotation "" } 245 | { Parent 0 } 246 | { Subject1 8 } 247 | { Subject2 1 } 248 | } 249 | 250 | SCDTransitionEdge 26 251 | { 252 | { Name "!coin_return" } 253 | { Annotation "" } 254 | { Parent 0 } 255 | { Subject1 8 } 256 | { Subject2 11 } 257 | } 258 | 259 | SCDTransitionEdge 27 260 | { 261 | { Name "always_true" } 262 | { Annotation "" } 263 | { Parent 0 } 264 | { Subject1 2 } 265 | { Subject2 3 } 266 | } 267 | 268 | SCDTransitionEdge 56 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End2 FilledArrow } 883 | { Points 4 } 884 | { Point 364 60 } 885 | { Point 420 140 } 886 | { Point 410 210 } 887 | { Point 363 250 } 888 | { NamePosition 415 175 } 889 | { Color "black" } 890 | { LineWidth 1 } 891 | { LineStyle Solid } 892 | { FixedName False } 893 | { Font "-*-courier-medium-r-normal--10*" } 894 | { TextAlignment Center } 895 | { TextColor "black" } 896 | { NameUnderlined False } 897 | } 898 | 899 | -------------------------------------------------------------------------------- /vending-machine/vmc.do: -------------------------------------------------------------------------------- 1 | # compile and test the vmc project 2 | 3 | vcom -reportprogress 300 -work work vmc.vhd; 4 | vcom -reportprogress 300 -work work vmc_tb.vhd; 5 | quit -sim; 6 | vsim work.vmc_tb; 7 | add wave -r /*; 8 | run 3000ns; 9 | -------------------------------------------------------------------------------- /vending-machine/vmc.vhd: -------------------------------------------------------------------------------- 1 | -- Vending Machine Controller 2 | 3 | library IEEE; 4 | use IEEE.std_logic_1164.all; 5 | use IEEE.numeric_std.all; 6 | --use IEEE.std_logic_arith.all; 7 | 8 | entity vmc is 9 | port( 10 | in_a, in_b, in_c, 11 | in_d, in_e, in_f : in std_logic; 12 | 13 | in_0, in_1, in_2, 14 | in_3, in_4, in_5, 15 | in_6, in_7, in_8, 16 | in_9 : in std_logic; 17 | 18 | clk, rst, 19 | coin_return : in std_logic; 20 | 21 | nickle_in, 22 | dime_in, 23 | quarter_in : in std_logic; 24 | 25 | vend, 26 | nickle_out, 27 | dime_out, 28 | quarter_out : out std_logic; 29 | 30 | selection_out : out std_logic_vector (0 to 5) 31 | ); 32 | end vmc; 33 | 34 | architecture simple of vmc is 35 | 36 | type sel_state is 37 | (dump_everything, 38 | reset_stuff, 39 | need_number, 40 | need_letter, 41 | sel_done, 42 | need_change, 43 | sel_ok); 44 | 45 | type price_mem is array(0 to 59) of integer; 46 | type selection_mem is array(0 to 1) of integer; 47 | 48 | signal sel_st_ns : sel_state := need_letter; 49 | signal sel_st_ps : sel_state := need_letter; 50 | 51 | signal change_need : integer := 0; 52 | signal give_change : std_logic := '0'; 53 | 54 | signal selection : selection_mem := (0, 0); 55 | signal is_number : std_logic := '0'; 56 | signal coin_in : std_logic := '0'; 57 | signal change_given : integer := 0; 58 | signal current_payment : integer := 0; 59 | signal current_coin : integer := 0; 60 | signal selection_price : integer := 0; 61 | signal selection_idx : integer := 0; 62 | 63 | signal return_coin_q : std_logic := '0'; 64 | signal return_coin_d : std_logic := '0'; 65 | signal return_coin_n : std_logic := '0'; 66 | 67 | signal incr_payment : std_logic := '0'; 68 | signal reset_payment : std_logic := '0'; 69 | 70 | signal have_input : std_logic := '0'; 71 | 72 | constant price_list : price_mem := ( 73 | 95, 40, 80, 100, -- AO -- A1 -- A2 -- A3 74 | 90, 100, 45, 50, -- A4 -- A5 -- A6 -- A7 75 | 60, 15, 5, 70, -- A8 -- A9 -- B0 -- B1 76 | 75, 55, 75, 60, -- B2 -- B3 -- B4 -- B5 77 | 90, 40, 40, 90, -- B6 -- B7 -- B8 -- B9 78 | 60, 30, 90, 15, -- C0 -- C1 -- C2 -- C3 79 | 90, 90, 10, 10, -- C4 -- C5 -- C6 -- C7 80 | 45, 10, 70, 95, -- C8 -- C9 -- D0 -- D1 81 | 70, 45, 5, 90, -- D2 -- D3 -- D4 -- D5 82 | 90, 10, 85, 70, -- D6 -- D7 -- D8 -- D9 83 | 30, 65, 90, 15, -- E0 -- E1 -- E2 -- E3 84 | 90, 100, 65, 90, -- E4 -- E5 -- E6 -- E7 85 | 45, 30, 85, 40, -- E8 -- E9 -- F0 -- F1 86 | 40, 10, 20, 35, -- F2 -- F3 -- F4 -- F5 87 | 40, 75, 65, 40 -- F6 -- F7 -- F8 -- F9 88 | ); 89 | 90 | signal rising_clk : std_logic; 91 | 92 | begin 93 | 94 | change_on_rising_edge : process (clk, rst) 95 | begin 96 | --if (rising_edge(clk)) then 97 | if (rising_edge(clk)) then 98 | rising_clk <= '1'; 99 | if (rst = '1') then 100 | sel_st_ps <= reset_stuff; 101 | else 102 | sel_st_ps <= sel_st_ns; 103 | end if; 104 | else 105 | rising_clk <= '0'; 106 | end if; 107 | end process; 108 | 109 | main_state_machine : process (rising_clk, coin_return, is_number, sel_st_ps) 110 | begin 111 | if (rising_clk = '1') then 112 | reset_payment <= '0'; 113 | if (coin_return = '1') then 114 | sel_st_ns <= dump_everything; 115 | change_need <= current_payment; 116 | else 117 | case sel_st_ps is 118 | when dump_everything => 119 | if (change_given < change_need) then 120 | give_change <= '1'; 121 | sel_st_ns <= dump_everything; 122 | else 123 | sel_st_ns <= need_letter; 124 | give_change <= '0'; 125 | reset_payment <= '1'; 126 | end if; 127 | when reset_stuff => 128 | give_change <= '0'; 129 | reset_payment <= '1'; 130 | sel_st_ns <= need_letter; 131 | when need_letter => 132 | if (have_input = '1') then 133 | if (is_number = '1') then 134 | sel_st_ns <= need_letter; 135 | else 136 | sel_st_ns <= need_number; 137 | end if; 138 | else 139 | sel_st_ns <= need_letter; 140 | end if; 141 | when need_number => 142 | if (is_number = '1') then 143 | sel_st_ns <= sel_done; 144 | else 145 | sel_st_ns <= need_number; 146 | end if; 147 | when sel_done => 148 | if ((current_payment > selection_price) or 149 | (current_payment = selection_price)) 150 | then 151 | change_need <= current_payment - selection_price; 152 | sel_st_ns <= need_change; 153 | else 154 | sel_st_ns <= sel_done; 155 | end if; 156 | when need_change => 157 | if (change_given < change_need) then 158 | give_change <= '1'; 159 | else 160 | sel_st_ns <= sel_ok; 161 | give_change <= '0'; 162 | reset_payment <= '1'; 163 | end if; 164 | when others => 165 | sel_st_ns <= need_letter; 166 | end case; 167 | end if; 168 | end if; 169 | end process; 170 | 171 | decode_selection : process 172 | (clk, in_0, in_1, in_2, in_3, in_4, in_5, in_6, in_7, in_8, in_9, 173 | in_a, in_b, in_c, in_d, in_e, in_f) 174 | 175 | variable idx : integer; 176 | 177 | begin 178 | have_input <= '1'; 179 | if (in_0 = '1' or in_1 = '1' or in_2 = '1' or 180 | in_3 = '1' or in_4 = '1' or in_5 = '1' or 181 | in_6 = '1' or in_7 = '1' or in_8 = '1' or 182 | in_9 = '1') 183 | then 184 | is_number <= '1'; 185 | elsif (in_a = '1' or in_b = '1' or in_c = '1' or 186 | in_d = '1' or in_e = '1' or in_f = '1') 187 | then 188 | is_number <= '0'; 189 | else 190 | is_number <= '0'; 191 | end if; 192 | 193 | if (in_0 = '1') then 194 | selection(0) <= 0; 195 | elsif (in_1 = '1') then 196 | selection(0) <= 1; 197 | elsif (in_2= '1') then 198 | selection(0) <= 2; 199 | elsif (in_3 = '1') then 200 | selection(0) <= 3; 201 | elsif (in_4 = '1') then 202 | selection(0) <= 4; 203 | elsif (in_5 = '1') then 204 | selection(0) <= 5; 205 | elsif (in_6 = '1') then 206 | selection(0) <= 6; 207 | elsif (in_7 = '1') then 208 | selection(0) <= 7; 209 | elsif (in_8 = '1') then 210 | selection(0) <= 8; 211 | elsif (in_9 = '1') then 212 | selection(0) <= 9; 213 | elsif (in_a = '1') then 214 | selection(1) <= 0; 215 | elsif (in_b = '1') then 216 | selection(1) <= 1; 217 | elsif (in_c = '1') then 218 | selection(1) <= 2; 219 | elsif (in_d = '1') then 220 | selection(1) <= 3; 221 | elsif (in_e = '1') then 222 | selection(1) <= 4; 223 | elsif (in_f = '1') then 224 | selection(1) <= 5; 225 | else 226 | have_input <= '0'; 227 | --selection(0) <= 0; 228 | --selection(1) <= 0; 229 | end if; 230 | idx := (selection(1) * 10) + selection(0); 231 | selection_idx <= idx; 232 | selection_price <= price_list(idx); 233 | end process; 234 | 235 | handle_payment : process (incr_payment, reset_payment) 236 | begin 237 | if (incr_payment = '1') then 238 | current_payment <= current_payment + current_coin; 239 | elsif (reset_payment = '1') then 240 | current_payment <= 0; 241 | end if; 242 | end process; 243 | 244 | incr_pay_mon : process (rising_clk, coin_in) 245 | begin 246 | if (rising_clk = '1') then 247 | if (coin_in = '1') then 248 | incr_payment <= '1'; 249 | else 250 | incr_payment <= '0'; 251 | end if; 252 | else 253 | incr_payment <= '0'; 254 | end if; 255 | end process; 256 | 257 | decode_coin : process (nickle_in, dime_in, quarter_in) 258 | begin 259 | if (nickle_in = '1' or 260 | dime_in = '1' or 261 | quarter_in = '1') 262 | then 263 | coin_in <= '1'; 264 | else 265 | coin_in <= '0'; 266 | end if; 267 | if (nickle_in = '1') then current_coin <= 5; 268 | elsif (dime_in = '1') then current_coin <= 10; 269 | elsif (quarter_in = '1') then current_coin <= 25; 270 | else 271 | current_coin <= 0; 272 | end if; 273 | if ((current_payment + current_coin) > 100) then 274 | if (nickle_in = '1') then 275 | return_coin_n <= '1'; 276 | else 277 | return_coin_n <= '0'; 278 | end if; 279 | if (dime_in = '1') then 280 | return_coin_d <= '1'; 281 | else 282 | return_coin_d <= '0'; 283 | end if; 284 | if (quarter_in = '1') then 285 | return_coin_q <= '1'; 286 | else 287 | return_coin_q <= '0'; 288 | end if; 289 | end if; 290 | end process; 291 | 292 | vend_product : process (sel_st_ps) 293 | begin 294 | case sel_st_ps is 295 | when sel_ok => 296 | selection_out <= 297 | std_logic_vector(to_unsigned(selection_idx, 6)); 298 | vend <= '1'; 299 | when others => 300 | selection_out <= "000000"; 301 | vend <= '0'; 302 | end case; 303 | end process; 304 | 305 | pulse_change : process (rising_clk, give_change, return_coin_q, return_coin_n, return_coin_d) 306 | begin 307 | if (rising_clk = '1') then 308 | quarter_out <= '0'; 309 | dime_out <= '0'; 310 | nickle_out <= '0'; 311 | if (give_change = '1') then 312 | if ((change_given + 25) <= change_need) then 313 | change_given <= change_given + 25; 314 | quarter_out <= '1'; 315 | elsif ((change_given + 10) <= change_need) then 316 | change_given <= change_given + 10; 317 | dime_out <= '1'; 318 | elsif ((change_given + 5) <= change_need) then 319 | change_given <= change_given + 5; 320 | nickle_out <= '1'; 321 | end if; 322 | elsif (return_coin_d = '1' or return_coin_q = '1' or return_coin_d = '1') then 323 | if (return_coin_q = '1') then 324 | quarter_out <= '1'; 325 | elsif (return_coin_d = '1') then 326 | dime_out <= '1'; 327 | elsif (return_coin_n = '1') then 328 | nickle_out <= '1'; 329 | end if; 330 | elsif (give_change = '0') then 331 | change_given <= 0; 332 | end if; 333 | end if; 334 | end process; 335 | 336 | end simple; 337 | 338 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 339 | -------------------------------------------------------------------------------- /vending-machine/vmc_tb.vhd: -------------------------------------------------------------------------------- 1 | 2 | -- Vending machine controller 3 | 4 | library IEEE; 5 | library work; 6 | 7 | use IEEE.std_logic_1164.all; 8 | use IEEE.numeric_std.all; 9 | use work.all; 10 | 11 | entity vmc_tb is end vmc_tb; 12 | 13 | architecture test of vmc_tb is 14 | 15 | component vmc is 16 | port( 17 | in_a : in std_logic; 18 | in_b : in std_logic; 19 | in_c : in std_logic; 20 | in_d : in std_logic; 21 | in_e : in std_logic; 22 | in_f : in std_logic; 23 | in_0 : in std_logic; 24 | in_1 : in std_logic; 25 | in_2 : in std_logic; 26 | in_3 : in std_logic; 27 | in_4 : in std_logic; 28 | in_5 : in std_logic; 29 | in_6 : in std_logic; 30 | in_7 : in std_logic; 31 | in_8 : in std_logic; 32 | in_9 : in std_logic; 33 | 34 | clk : in std_logic; 35 | rst : in std_logic; 36 | 37 | nickle_in : in std_logic; 38 | dime_in : in std_logic; 39 | quarter_in : in std_logic; 40 | 41 | nickle_out : out std_logic; 42 | dime_out : out std_logic; 43 | quarter_out : out std_logic; 44 | 45 | coin_return : in std_logic; 46 | selection_out : out std_logic_vector (0 to 5); 47 | vend : out std_logic 48 | ); 49 | end component; 50 | 51 | signal in_a : std_logic; 52 | signal in_b : std_logic; 53 | signal in_c : std_logic; 54 | signal in_d : std_logic; 55 | signal in_e : std_logic; 56 | signal in_f : std_logic; 57 | signal in_0 : std_logic; 58 | signal in_1 : std_logic; 59 | signal in_2 : std_logic; 60 | signal in_3 : std_logic; 61 | signal in_4 : std_logic; 62 | signal in_5 : std_logic; 63 | signal in_6 : std_logic; 64 | signal in_7 : std_logic; 65 | signal in_8 : std_logic; 66 | signal in_9 : std_logic; 67 | 68 | signal clk : std_logic; 69 | signal rst : std_logic; 70 | 71 | signal nickle_in : std_logic; 72 | signal dime_in : std_logic; 73 | signal quarter_in : std_logic; 74 | 75 | signal nickle_out : std_logic; 76 | signal dime_out : std_logic; 77 | signal quarter_out : std_logic; 78 | 79 | signal coin_return : std_logic; 80 | signal selection_out : std_logic_vector (0 to 5); 81 | signal vend : std_logic; 82 | 83 | constant clk_period : time := 10 ns; 84 | constant clk_cycle : time := clk_period*2; 85 | constant change : integer := 10; 86 | 87 | begin 88 | 89 | unit : vmc 90 | port map ( 91 | in_0 => in_0, 92 | in_1 => in_1, 93 | in_2 => in_2, 94 | in_3 => in_3, 95 | in_4 => in_4, 96 | in_5 => in_5, 97 | in_6 => in_6, 98 | in_7 => in_7, 99 | in_8 => in_8, 100 | in_9 => in_9, 101 | in_a => in_a, 102 | in_b => in_b, 103 | in_c => in_c, 104 | in_d => in_d, 105 | in_e => in_e, 106 | in_f => in_f, 107 | clk => clk, 108 | rst => rst, 109 | nickle_in => nickle_in, 110 | dime_in => dime_in, 111 | quarter_in => quarter_in, 112 | nickle_out => nickle_out, 113 | dime_out => dime_out, 114 | quarter_out => quarter_out, 115 | coin_return => coin_return, 116 | selection_out => selection_out, 117 | vend => vend 118 | ); 119 | 120 | rest : process begin 121 | wait for clk_period; 122 | rst <= '0'; 123 | wait for 48*clk_cycle; 124 | rst <= '1'; 125 | wait for clk_cycle; 126 | rst <= '0'; 127 | wait; 128 | end process; 129 | 130 | clock : process begin 131 | clk <= '0'; 132 | wait for clk_period; 133 | clk <= '1'; 134 | wait for clk_period; 135 | end process; 136 | 137 | selection : process begin 138 | in_a <= '0'; in_b <= '0'; in_c <= '0'; in_d <= '0'; 139 | in_e <= '0'; in_f <= '0'; in_0 <= '0'; in_1 <= '0'; 140 | in_2 <= '0'; in_3 <= '0'; in_4 <= '0'; in_5 <= '0'; 141 | in_6 <= '0'; in_7 <= '0'; in_8 <= '0'; in_9 <= '0'; 142 | wait for clk_period; 143 | wait for clk_cycle*4; 144 | in_a <= '1'; 145 | wait for clk_cycle; 146 | in_a <= '0'; 147 | in_1 <= '1'; 148 | wait for clk_cycle; 149 | in_1 <= '0'; 150 | wait for clk_cycle*(change+6); 151 | in_a <= '1'; 152 | wait for clk_cycle; 153 | in_a <= '0'; 154 | in_2 <= '1'; 155 | wait for clk_cycle; 156 | in_2 <= '0'; 157 | wait for clk_cycle*(change+10); 158 | in_b <= '1'; 159 | wait for clk_cycle; 160 | in_b <= '0'; 161 | wait; 162 | end process; 163 | 164 | coin_ret : process 165 | begin 166 | coin_return <= '0'; 167 | wait for clk_period; 168 | wait for clk_cycle*36; 169 | coin_return <= '1'; 170 | wait for clk_cycle; 171 | coin_return <= '0'; 172 | wait; 173 | end process; 174 | 175 | money : process 176 | begin 177 | nickle_in <= '0'; 178 | dime_in <= '0'; 179 | quarter_in <= '0'; 180 | wait for clk_period; 181 | quarter_in <= '1'; 182 | wait for clk_cycle*3; 183 | nickle_in <= '1'; 184 | quarter_in <= '0'; 185 | wait for clk_cycle; 186 | nickle_in <= '0'; 187 | wait for clk_cycle*(change+2); 188 | quarter_in <= '1'; 189 | wait for clk_cycle*3; 190 | nickle_in <= '1'; 191 | quarter_in <= '0'; 192 | wait for clk_cycle; 193 | nickle_in <= '0'; 194 | wait for clk_cycle*(change+2); 195 | quarter_in <= '1'; 196 | wait for clk_cycle*3; 197 | nickle_in <= '1'; 198 | quarter_in <= '0'; 199 | wait for clk_cycle; 200 | nickle_in <= '0'; 201 | wait for clk_cycle*(change); 202 | nickle_in <= '1'; 203 | wait for clk_cycle; 204 | nickle_in <= '0'; 205 | wait; 206 | end process; 207 | 208 | end architecture test; 209 | 210 | -- vim: et:ts=4:sw=4:sts=4:ai:hlsearch:nu: 211 | -------------------------------------------------------------------------------- /vending-machine/vmc_tb_2.vhd: -------------------------------------------------------------------------------- 1 | 2 | 3 | selection : process 4 | begin 5 | in_a <= '1'; 6 | in_b <= '0'; 7 | in_c <= '0'; 8 | in_d <= '0'; 9 | in_e <= '0'; 10 | in_f <= '0'; 11 | in_0 <= '0'; 12 | in_1 <= '0'; 13 | in_2 <= '0'; 14 | in_3 <= '0'; 15 | in_4 <= '0'; 16 | in_5 <= '0'; 17 | in_6 <= '0'; 18 | in_7 <= '0'; 19 | in_8 <= '0'; 20 | in_9 <= '0'; 21 | wait for clk_period; 22 | in_a <= '0'; 23 | in_b <= '0'; 24 | in_c <= '0'; 25 | in_d <= '0'; 26 | in_e <= '0'; 27 | in_f <= '0'; 28 | in_0 <= '0'; 29 | in_1 <= '0'; 30 | in_2 <= '1'; 31 | in_3 <= '0'; 32 | in_4 <= '0'; 33 | in_5 <= '0'; 34 | in_6 <= '0'; 35 | in_7 <= '0'; 36 | in_8 <= '0'; 37 | in_9 <= '0'; 38 | wait for clk_period; 39 | end process; 40 | 41 | money : process 42 | begin 43 | nickle_in <= 44 | dime_in 45 | quarter_in 46 | end process; 47 | 48 | -- vim: ts=2:sts=2:sw=2: 49 | -------------------------------------------------------------------------------- /vending-machine/wave_all.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/silverjam/VHDL/2494a4b1218a07a591baa7cf079db319e0cdcca0/vending-machine/wave_all.pdf -------------------------------------------------------------------------------- /vending-machine/wave_change.pdf: -------------------------------------------------------------------------------- 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