├── .cproject ├── .gitignore ├── .project ├── .settings └── language.settings.xml ├── CMSIS ├── core │ ├── arm_common_tables.h │ ├── arm_const_structs.h │ ├── arm_math.h │ ├── core_cm0.h │ ├── core_cm0plus.h │ ├── core_cm3.h │ ├── core_cm4.h │ ├── core_cm4_simd.h │ ├── core_cmFunc.h │ ├── core_cmInstr.h │ ├── core_sc000.h │ └── core_sc300.h └── device │ ├── stm32f0xx.h │ └── system_stm32f0xx.h ├── LinkerScript.ld ├── README.md ├── StdPeriph_Driver ├── Release_Notes.html ├── inc │ ├── stm32f0xx_adc.h │ ├── stm32f0xx_can.h │ ├── stm32f0xx_cec.h │ ├── stm32f0xx_comp.h │ ├── stm32f0xx_conf.h │ ├── stm32f0xx_crc.h │ ├── stm32f0xx_crs.h │ ├── stm32f0xx_dac.h │ ├── stm32f0xx_dbgmcu.h │ ├── stm32f0xx_dma.h │ ├── stm32f0xx_exti.h │ ├── stm32f0xx_flash.h │ ├── stm32f0xx_gpio.h │ ├── stm32f0xx_i2c.h │ ├── stm32f0xx_iwdg.h │ ├── stm32f0xx_misc.h │ ├── stm32f0xx_pwr.h │ ├── stm32f0xx_rcc.h │ ├── stm32f0xx_rtc.h │ ├── stm32f0xx_spi.h │ ├── stm32f0xx_syscfg.h │ ├── stm32f0xx_tim.h │ ├── stm32f0xx_usart.h │ └── stm32f0xx_wwdg.h └── src │ ├── stm32f0xx_adc.c │ ├── stm32f0xx_can.c │ ├── stm32f0xx_cec.c │ ├── stm32f0xx_comp.c │ ├── stm32f0xx_crc.c │ ├── stm32f0xx_crs.c │ ├── stm32f0xx_dac.c │ ├── stm32f0xx_dbgmcu.c │ ├── stm32f0xx_dma.c │ ├── stm32f0xx_exti.c │ ├── stm32f0xx_flash.c │ ├── stm32f0xx_gpio.c │ ├── stm32f0xx_i2c.c │ ├── stm32f0xx_iwdg.c │ ├── stm32f0xx_misc.c │ ├── stm32f0xx_pwr.c │ ├── stm32f0xx_rcc.c │ ├── stm32f0xx_rtc.c │ ├── stm32f0xx_spi.c │ ├── stm32f0xx_syscfg.c │ ├── stm32f0xx_tim.c │ ├── stm32f0xx_usart.c │ └── stm32f0xx_wwdg.c ├── dist └── sensorsRaw.bin ├── hardware ├── neoimage_sensors small.brd ├── neoimage_sensors small.pdf └── neoimage_sensors small.sch ├── inc ├── main.h └── stm32f0xx_it.h ├── sensorsRaw Run.cfg ├── src ├── fix_fft.c ├── libfixmath_sqrt.c ├── main.c ├── output.c ├── syscalls.c └── system_stm32f0xx.c └── startup └── startup_stm32.s /.gitignore: -------------------------------------------------------------------------------- 1 | .DS_Store 2 | /Debug/ 3 | /Release/ 4 | 5 | #eclipse stuff 6 | 7 | 8 | .metadata 9 | bin/ 10 | tmp/ 11 | *.tmp 12 | *.bak 13 | *.swp 14 | *~.nib 15 | local.properties 16 | .loadpath 17 | .recommenders 18 | 19 | # External tool builders 20 | .externalToolBuilders/ 21 | 22 | # Locally stored "Eclipse launch configurations" 23 | *.launch 24 | 25 | # PyDev specific (Python IDE for Eclipse) 26 | *.pydevproject 27 | 28 | 29 | # CDT- autotools 30 | .autotools 31 | 32 | # Java annotation processor (APT) 33 | .factorypath 34 | 35 | # PDT-specific (PHP Development Tools) 36 | .buildpath 37 | 38 | # sbteclipse plugin 39 | .target 40 | 41 | # Tern plugin 42 | .tern-project 43 | 44 | # TeXlipse plugin 45 | .texlipse 46 | 47 | # STS (Spring Tool Suite) 48 | .springBeans 49 | 50 | # Code Recommenders 51 | .recommenders/ 52 | 53 | # Scala IDE specific (Scala & Java development for Eclipse) 54 | .cache-main 55 | .scala_dependencies 56 | .worksheet 57 | 58 | 59 | -------------------------------------------------------------------------------- /.project: -------------------------------------------------------------------------------- 1 | 2 | 3 | sensorsRaw 4 | 5 | 6 | 7 | 8 | 9 | org.eclipse.cdt.managedbuilder.core.genmakebuilder 10 | clean,full,incremental, 11 | 12 | 13 | 14 | 15 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder 16 | full,incremental, 17 | 18 | 19 | 20 | 21 | 22 | org.eclipse.cdt.core.cnature 23 | com.st.stm32cube.ide.mcu.MCUSingleCpuProjectNature 24 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature 25 | com.st.stm32cube.ide.mcu.MCUSW4STM32ConvertedProjectNature 26 | org.eclipse.cdt.managedbuilder.core.managedBuildNature 27 | 28 | 29 | -------------------------------------------------------------------------------- /.settings/language.settings.xml: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | -------------------------------------------------------------------------------- /CMSIS/core/arm_common_tables.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2013 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 17. January 2013 5 | * $Revision: V1.4.1 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_common_tables.h 9 | * 10 | * Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 11 | * 12 | * Target Processor: Cortex-M4/Cortex-M3 13 | * 14 | * Redistribution and use in source and binary forms, with or without 15 | * modification, are permitted provided that the following conditions 16 | * are met: 17 | * - Redistributions of source code must retain the above copyright 18 | * notice, this list of conditions and the following disclaimer. 19 | * - Redistributions in binary form must reproduce the above copyright 20 | * notice, this list of conditions and the following disclaimer in 21 | * the documentation and/or other materials provided with the 22 | * distribution. 23 | * - Neither the name of ARM LIMITED nor the names of its contributors 24 | * may be used to endorse or promote products derived from this 25 | * software without specific prior written permission. 26 | * 27 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 30 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 31 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 32 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 33 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 34 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 35 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 | * POSSIBILITY OF SUCH DAMAGE. 39 | * -------------------------------------------------------------------- */ 40 | 41 | #ifndef _ARM_COMMON_TABLES_H 42 | #define _ARM_COMMON_TABLES_H 43 | 44 | #include "arm_math.h" 45 | 46 | extern const uint16_t armBitRevTable[1024]; 47 | extern const q15_t armRecipTableQ15[64]; 48 | extern const q31_t armRecipTableQ31[64]; 49 | extern const q31_t realCoefAQ31[1024]; 50 | extern const q31_t realCoefBQ31[1024]; 51 | extern const float32_t twiddleCoef_16[32]; 52 | extern const float32_t twiddleCoef_32[64]; 53 | extern const float32_t twiddleCoef_64[128]; 54 | extern const float32_t twiddleCoef_128[256]; 55 | extern const float32_t twiddleCoef_256[512]; 56 | extern const float32_t twiddleCoef_512[1024]; 57 | extern const float32_t twiddleCoef_1024[2048]; 58 | extern const float32_t twiddleCoef_2048[4096]; 59 | extern const float32_t twiddleCoef_4096[8192]; 60 | #define twiddleCoef twiddleCoef_4096 61 | extern const q31_t twiddleCoefQ31[6144]; 62 | extern const q15_t twiddleCoefQ15[6144]; 63 | extern const float32_t twiddleCoef_rfft_32[32]; 64 | extern const float32_t twiddleCoef_rfft_64[64]; 65 | extern const float32_t twiddleCoef_rfft_128[128]; 66 | extern const float32_t twiddleCoef_rfft_256[256]; 67 | extern const float32_t twiddleCoef_rfft_512[512]; 68 | extern const float32_t twiddleCoef_rfft_1024[1024]; 69 | extern const float32_t twiddleCoef_rfft_2048[2048]; 70 | extern const float32_t twiddleCoef_rfft_4096[4096]; 71 | 72 | 73 | #define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 ) 74 | #define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 ) 75 | #define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 ) 76 | #define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 ) 77 | #define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 ) 78 | #define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 ) 79 | #define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) 80 | #define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) 81 | #define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) 82 | 83 | extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; 84 | extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; 85 | extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; 86 | extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; 87 | extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; 88 | extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; 89 | extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; 90 | extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; 91 | extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; 92 | 93 | #endif /* ARM_COMMON_TABLES_H */ 94 | -------------------------------------------------------------------------------- /CMSIS/core/arm_const_structs.h: -------------------------------------------------------------------------------- 1 | /* ---------------------------------------------------------------------- 2 | * Copyright (C) 2010-2013 ARM Limited. All rights reserved. 3 | * 4 | * $Date: 17. January 2013 5 | * $Revision: V1.4.1 6 | * 7 | * Project: CMSIS DSP Library 8 | * Title: arm_const_structs.h 9 | * 10 | * Description: This file has constant structs that are initialized for 11 | * user convenience. For example, some can be given as 12 | * arguments to the arm_cfft_f32() function. 13 | * 14 | * Target Processor: Cortex-M4/Cortex-M3 15 | * 16 | * Redistribution and use in source and binary forms, with or without 17 | * modification, are permitted provided that the following conditions 18 | * are met: 19 | * - Redistributions of source code must retain the above copyright 20 | * notice, this list of conditions and the following disclaimer. 21 | * - Redistributions in binary form must reproduce the above copyright 22 | * notice, this list of conditions and the following disclaimer in 23 | * the documentation and/or other materials provided with the 24 | * distribution. 25 | * - Neither the name of ARM LIMITED nor the names of its contributors 26 | * may be used to endorse or promote products derived from this 27 | * software without specific prior written permission. 28 | * 29 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 32 | * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 33 | * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 34 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 35 | * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 37 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 38 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 39 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 | * POSSIBILITY OF SUCH DAMAGE. 41 | * -------------------------------------------------------------------- */ 42 | 43 | #ifndef _ARM_CONST_STRUCTS_H 44 | #define _ARM_CONST_STRUCTS_H 45 | 46 | #include "arm_math.h" 47 | #include "arm_common_tables.h" 48 | 49 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { 50 | 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH 51 | }; 52 | 53 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { 54 | 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH 55 | }; 56 | 57 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { 58 | 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH 59 | }; 60 | 61 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { 62 | 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH 63 | }; 64 | 65 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { 66 | 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH 67 | }; 68 | 69 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { 70 | 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH 71 | }; 72 | 73 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { 74 | 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH 75 | }; 76 | 77 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { 78 | 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH 79 | }; 80 | 81 | const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { 82 | 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH 83 | }; 84 | 85 | #endif 86 | -------------------------------------------------------------------------------- /CMSIS/device/system_stm32f0xx.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2014 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /** @addtogroup CMSIS 29 | * @{ 30 | */ 31 | 32 | /** @addtogroup stm32f0xx_system 33 | * @{ 34 | */ 35 | 36 | /** 37 | * @brief Define to prevent recursive inclusion 38 | */ 39 | #ifndef __SYSTEM_STM32F0XX_H 40 | #define __SYSTEM_STM32F0XX_H 41 | 42 | #ifdef __cplusplus 43 | extern "C" { 44 | #endif 45 | 46 | /** @addtogroup STM32F0xx_System_Includes 47 | * @{ 48 | */ 49 | 50 | /** 51 | * @} 52 | */ 53 | 54 | 55 | /** @addtogroup STM32F0xx_System_Exported_types 56 | * @{ 57 | */ 58 | 59 | extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ 60 | 61 | /** 62 | * @} 63 | */ 64 | 65 | /** @addtogroup STM32F0xx_System_Exported_Constants 66 | * @{ 67 | */ 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** @addtogroup STM32F0xx_System_Exported_Macros 74 | * @{ 75 | */ 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /** @addtogroup STM32F0xx_System_Exported_Functions 82 | * @{ 83 | */ 84 | 85 | extern void SystemInit(void); 86 | extern void SystemCoreClockUpdate(void); 87 | /** 88 | * @} 89 | */ 90 | 91 | #ifdef __cplusplus 92 | } 93 | #endif 94 | 95 | #endif /*__SYSTEM_STM32F0XX_H */ 96 | 97 | /** 98 | * @} 99 | */ 100 | 101 | /** 102 | * @} 103 | */ 104 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 105 | -------------------------------------------------------------------------------- /LinkerScript.ld: -------------------------------------------------------------------------------- 1 | /* 2 | ****************************************************************************** 3 | ** 4 | ** File : LinkerScript.ld 5 | ** 6 | ** Author : Auto-generated by Ac6 System Workbench 7 | ** 8 | ** Abstract : Linker script for STM32F030F4Px Device from STM32F0 series 9 | ** 4Kbytes RAM 10 | ** 16Kbytes ROM 11 | ** 12 | ** Set heap size, stack size and stack location according 13 | ** to application requirements. 14 | ** 15 | ** Set memory bank area and size if external memory is used. 16 | ** 17 | ** Target : STMicroelectronics STM32 18 | ** 19 | ** Distribution: The file is distributed �as is,� without any warranty 20 | ** of any kind. 21 | ** 22 | ***************************************************************************** 23 | ** @attention 24 | ** 25 | **

© COPYRIGHT(c) 2018 Ac6

26 | ** 27 | ** Redistribution and use in source and binary forms, with or without modification, 28 | ** are permitted provided that the following conditions are met: 29 | ** 1. Redistributions of source code must retain the above copyright notice, 30 | ** this list of conditions and the following disclaimer. 31 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 32 | ** this list of conditions and the following disclaimer in the documentation 33 | ** and/or other materials provided with the distribution. 34 | ** 3. Neither the name of Ac6 nor the names of its contributors 35 | ** may be used to endorse or promote products derived from this software 36 | ** without specific prior written permission. 37 | ** 38 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 39 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 40 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 42 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 43 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 44 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 45 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 46 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 | ** 49 | ***************************************************************************** 50 | */ 51 | 52 | /* Entry Point */ 53 | ENTRY(Reset_Handler) 54 | 55 | /* Highest address of the user mode stack */ 56 | _estack = 0x20001000; /* end of RAM */ 57 | 58 | _Min_Heap_Size = 0; /* required amount of heap */ 59 | _Min_Stack_Size = 0x400; /* required amount of stack */ 60 | 61 | /* Memories definition */ 62 | MEMORY 63 | { 64 | RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 4K 65 | ROM (rx) : ORIGIN = 0x8000000, LENGTH = 16K 66 | } 67 | 68 | /* Sections */ 69 | SECTIONS 70 | { 71 | /* The startup code into ROM memory */ 72 | .isr_vector : 73 | { 74 | . = ALIGN(4); 75 | KEEP(*(.isr_vector)) /* Startup code */ 76 | . = ALIGN(4); 77 | } >ROM 78 | 79 | /* The program code and other data into ROM memory */ 80 | .text : 81 | { 82 | . = ALIGN(4); 83 | *(.text) /* .text sections (code) */ 84 | *(.text*) /* .text* sections (code) */ 85 | *(.glue_7) /* glue arm to thumb code */ 86 | *(.glue_7t) /* glue thumb to arm code */ 87 | *(.eh_frame) 88 | 89 | KEEP (*(.init)) 90 | KEEP (*(.fini)) 91 | 92 | . = ALIGN(4); 93 | _etext = .; /* define a global symbols at end of code */ 94 | } >ROM 95 | 96 | /* Constant data into ROM memory*/ 97 | .rodata : 98 | { 99 | . = ALIGN(4); 100 | *(.rodata) /* .rodata sections (constants, strings, etc.) */ 101 | *(.rodata*) /* .rodata* sections (constants, strings, etc.) */ 102 | . = ALIGN(4); 103 | } >ROM 104 | 105 | .ARM.extab : { 106 | . = ALIGN(4); 107 | *(.ARM.extab* .gnu.linkonce.armextab.*) 108 | . = ALIGN(4); 109 | } >ROM 110 | 111 | .ARM : { 112 | . = ALIGN(4); 113 | __exidx_start = .; 114 | *(.ARM.exidx*) 115 | __exidx_end = .; 116 | . = ALIGN(4); 117 | } >ROM 118 | 119 | .preinit_array : 120 | { 121 | . = ALIGN(4); 122 | PROVIDE_HIDDEN (__preinit_array_start = .); 123 | KEEP (*(.preinit_array*)) 124 | PROVIDE_HIDDEN (__preinit_array_end = .); 125 | . = ALIGN(4); 126 | } >ROM 127 | 128 | .init_array : 129 | { 130 | . = ALIGN(4); 131 | PROVIDE_HIDDEN (__init_array_start = .); 132 | KEEP (*(SORT(.init_array.*))) 133 | KEEP (*(.init_array*)) 134 | PROVIDE_HIDDEN (__init_array_end = .); 135 | . = ALIGN(4); 136 | } >ROM 137 | 138 | .fini_array : 139 | { 140 | . = ALIGN(4); 141 | PROVIDE_HIDDEN (__fini_array_start = .); 142 | KEEP (*(SORT(.fini_array.*))) 143 | KEEP (*(.fini_array*)) 144 | PROVIDE_HIDDEN (__fini_array_end = .); 145 | . = ALIGN(4); 146 | } >ROM 147 | 148 | /* Used by the startup to initialize data */ 149 | _sidata = LOADADDR(.data); 150 | 151 | /* Initialized data sections into RAM memory */ 152 | .data : 153 | { 154 | . = ALIGN(4); 155 | _sdata = .; /* create a global symbol at data start */ 156 | *(.data) /* .data sections */ 157 | *(.data*) /* .data* sections */ 158 | 159 | . = ALIGN(4); 160 | _edata = .; /* define a global symbol at data end */ 161 | } >RAM AT> ROM 162 | 163 | 164 | /* Uninitialized data section into RAM memory */ 165 | . = ALIGN(4); 166 | .bss : 167 | { 168 | /* This is used by the startup in order to initialize the .bss secion */ 169 | _sbss = .; /* define a global symbol at bss start */ 170 | __bss_start__ = _sbss; 171 | *(.bss) 172 | *(.bss*) 173 | *(COMMON) 174 | 175 | . = ALIGN(4); 176 | _ebss = .; /* define a global symbol at bss end */ 177 | __bss_end__ = _ebss; 178 | } >RAM 179 | 180 | /* User_heap_stack section, used to check that there is enough RAM left */ 181 | ._user_heap_stack : 182 | { 183 | . = ALIGN(8); 184 | PROVIDE ( end = . ); 185 | PROVIDE ( _end = . ); 186 | . = . + _Min_Heap_Size; 187 | . = . + _Min_Stack_Size; 188 | . = ALIGN(8); 189 | } >RAM 190 | 191 | 192 | 193 | /* Remove information from the compiler libraries */ 194 | /DISCARD/ : 195 | { 196 | libc.a ( * ) 197 | libm.a ( * ) 198 | libgcc.a ( * ) 199 | } 200 | 201 | .ARM.attributes 0 : { *(.ARM.attributes) } 202 | } 203 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | Pixelblaze Sensor Expansion Board 2 | ------------------- 3 | 4 | ![sensor board](http://app.bhencke.com/pixelblaze/sb10b.jpg) 5 | 6 | * A microphone and signal processing with frequency magnitude data ranging from 37Hz-10KHz designed to work in very loud environments 7 | * A 3-axis 16G accelerometer 8 | * An ambient light sensor 9 | * 5 analog inputs that can be used with potentiometers or other analog inputs 10 | 11 | [For sale on Tindie](https://www.tindie.com/products/12158/)! Pick up this board and/or a Pixelblaze! Make cool sound-reactive LED things, or get one and hack the firmware! 12 | 13 | ![soundmatrix](http://app.bhencke.com/pixelblaze/soundmatrix.gif) 14 | 15 | I hope you find this useful or interesting. Maybe you hack your board? I'd be stoked to hear about it! Roll your own? Great! Turn it into a robot brain? Awesome! 16 | 17 | Shout out to Sparkfun, their boards were used in the initial prototype, and their Eagle files were really helpful! 18 | 19 | Shout out to [https://github.com/pyrohaz/STM32F0-PCD8544GraphicAnalyzer](https://github.com/pyrohaz/STM32F0-PCD8544GraphicAnalyzer) which does similar FFT stuff with a similar processor, even shares the fixed point FFT code in common! 20 | 21 | Non-Pixelblaze Usage 22 | ------------------- 23 | Looking to use this with an Arduino or Teensy or something? You just need a free serial port at 115200 baud. 24 | 25 | The protocol is fairly simple: 26 | 27 | 1. Each frame starts with "SB1.0" including a null character (6 bytes). 28 | 2. The frequency information follows, as 32 x 16-bit unsigned integers. 29 | 3. Then is the audio energy average, max frequency magnitiude, max frequency Hz, all 3 as 16-bit unsigned ints. 30 | 4. Next the accelerometer information as 3 x 16-bit signed integers. 31 | 5. The data from the Light sensor is next, as a single 16-bit unsigned integer. 32 | 6. Followed by the 5 x 16-bit analog inputs (12-bit resolution, shifted up to 16 bits) 33 | 7. Finally "END" including a null character (4 bytes). 34 | 35 | 36 | License Information 37 | ------------------- 38 | The hardware files are released under [Creative Commons ShareAlike 4.0 International](https://creativecommons.org/licenses/by-sa/4.0/) since the PCB is largely based off of Sparkfun boards with this license requirement. 39 | 40 | Distributed as-is; no warranty is given. 41 | 42 | The ElectroMage logo and wizard character is excluded from this license. 43 | 44 | The software is released under The MIT License. 45 | 46 | The MIT License 47 | 48 | Copyright (c) 2018 Ben Hencke 49 | 50 | Permission is hereby granted, free of charge, to any person obtaining a copy 51 | of this software and associated documentation files (the "Software"), to deal 52 | in the Software without restriction, including without limitation the rights 53 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 54 | copies of the Software, and to permit persons to whom the Software is 55 | furnished to do so, subject to the following conditions: 56 | 57 | The above copyright notice and this permission notice shall be included in 58 | all copies or substantial portions of the Software. 59 | 60 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 61 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 62 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 63 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 64 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 65 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 66 | THE SOFTWARE. 67 | -------------------------------------------------------------------------------- /StdPeriph_Driver/Release_Notes.html: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/simap/pixelblaze_sensor_board/15b3d271e0d6535965a68b15f057bac58a3154d7/StdPeriph_Driver/Release_Notes.html -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_cec.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_cec.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the CEC firmware 8 | * library, applicable only for STM32F051, STM32F042 and STM32F072 devices. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_CEC_H 31 | #define __STM32F0XX_CEC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CEC 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief CEC Init structure definition 51 | */ 52 | typedef struct 53 | { 54 | uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration. 55 | This parameter can be a value of @ref CEC_Signal_Free_Time */ 56 | uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance. 57 | This parameter can be a value of @ref CEC_RxTolerance */ 58 | uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception. 59 | This parameter can be a value of @ref CEC_Stop_Reception */ 60 | uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation. 61 | This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */ 62 | uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation. 63 | This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */ 64 | uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation. 65 | This parameter can be a value of @ref CEC_BDR_No_Gen */ 66 | uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option. 67 | This parameter can be a value of @ref CEC_SFT_Option */ 68 | 69 | }CEC_InitTypeDef; 70 | 71 | /* Exported constants --------------------------------------------------------*/ 72 | 73 | /** @defgroup CEC_Exported_Constants 74 | * @{ 75 | */ 76 | 77 | /** @defgroup CEC_Signal_Free_Time 78 | * @{ 79 | */ 80 | #define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */ 81 | #define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */ 82 | #define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */ 83 | #define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */ 84 | #define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */ 85 | #define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */ 86 | #define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */ 87 | #define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */ 88 | 89 | #define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \ 90 | ((TIME) == CEC_SignalFreeTime_1T)|| \ 91 | ((TIME) == CEC_SignalFreeTime_2T)|| \ 92 | ((TIME) == CEC_SignalFreeTime_3T)|| \ 93 | ((TIME) == CEC_SignalFreeTime_4T)|| \ 94 | ((TIME) == CEC_SignalFreeTime_5T)|| \ 95 | ((TIME) == CEC_SignalFreeTime_6T)|| \ 96 | ((TIME) == CEC_SignalFreeTime_7T)) 97 | /** 98 | * @} 99 | */ 100 | 101 | /** @defgroup CEC_RxTolerance 102 | * @{ 103 | */ 104 | #define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */ 105 | #define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */ 106 | 107 | #define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \ 108 | ((TOLERANCE) == CEC_RxTolerance_Extended)) 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @defgroup CEC_Stop_Reception 114 | * @{ 115 | */ 116 | #define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */ 117 | #define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */ 118 | 119 | #define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \ 120 | ((RECEPTION) == CEC_StopReception_Off)) 121 | /** 122 | * @} 123 | */ 124 | 125 | /** @defgroup CEC_Bit_Rising_Error_Generation 126 | * @{ 127 | */ 128 | #define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */ 129 | #define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */ 130 | 131 | #define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \ 132 | ((ERROR) == CEC_BitRisingError_On)) 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup CEC_Long_Bit_Error_Generation 138 | * @{ 139 | */ 140 | #define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */ 141 | #define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */ 142 | 143 | #define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \ 144 | ((ERROR) == CEC_LongBitPeriodError_On)) 145 | /** 146 | * @} 147 | */ 148 | 149 | /** @defgroup CEC_BDR_No_Gen 150 | * @{ 151 | */ 152 | 153 | #define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */ 154 | #define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */ 155 | 156 | #define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \ 157 | ((ERROR) == CEC_BRDNoGen_On)) 158 | /** 159 | * @} 160 | */ 161 | 162 | /** @defgroup CEC_SFT_Option 163 | * @{ 164 | */ 165 | #define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */ 166 | #define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */ 167 | 168 | #define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \ 169 | ((OPTION) == CEC_SFTOption_On)) 170 | /** 171 | * @} 172 | */ 173 | 174 | /** @defgroup CEC_Own_Address 175 | * @{ 176 | */ 177 | #define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10) 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** @defgroup CEC_Interrupt_Configuration_definition 184 | * @{ 185 | */ 186 | #define CEC_IT_TXACKE CEC_IER_TXACKEIE 187 | #define CEC_IT_TXERR CEC_IER_TXERRIE 188 | #define CEC_IT_TXUDR CEC_IER_TXUDRIE 189 | #define CEC_IT_TXEND CEC_IER_TXENDIE 190 | #define CEC_IT_TXBR CEC_IER_TXBRIE 191 | #define CEC_IT_ARBLST CEC_IER_ARBLSTIE 192 | #define CEC_IT_RXACKE CEC_IER_RXACKEIE 193 | #define CEC_IT_LBPE CEC_IER_LBPEIE 194 | #define CEC_IT_SBPE CEC_IER_SBPEIE 195 | #define CEC_IT_BRE CEC_IER_BREIEIE 196 | #define CEC_IT_RXOVR CEC_IER_RXOVRIE 197 | #define CEC_IT_RXEND CEC_IER_RXENDIE 198 | #define CEC_IT_RXBR CEC_IER_RXBRIE 199 | 200 | #define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00)) 201 | 202 | #define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \ 203 | ((IT) == CEC_IT_TXERR)|| \ 204 | ((IT) == CEC_IT_TXUDR)|| \ 205 | ((IT) == CEC_IT_TXEND)|| \ 206 | ((IT) == CEC_IT_TXBR)|| \ 207 | ((IT) == CEC_IT_ARBLST)|| \ 208 | ((IT) == CEC_IT_RXACKE)|| \ 209 | ((IT) == CEC_IT_LBPE)|| \ 210 | ((IT) == CEC_IT_SBPE)|| \ 211 | ((IT) == CEC_IT_BRE)|| \ 212 | ((IT) == CEC_IT_RXOVR)|| \ 213 | ((IT) == CEC_IT_RXEND)|| \ 214 | ((IT) == CEC_IT_RXBR)) 215 | /** 216 | * @} 217 | */ 218 | 219 | /** @defgroup CEC_ISR_register_flags_definition 220 | * @{ 221 | */ 222 | #define CEC_FLAG_TXACKE CEC_ISR_TXACKE 223 | #define CEC_FLAG_TXERR CEC_ISR_TXERR 224 | #define CEC_FLAG_TXUDR CEC_ISR_TXUDR 225 | #define CEC_FLAG_TXEND CEC_ISR_TXEND 226 | #define CEC_FLAG_TXBR CEC_ISR_TXBR 227 | #define CEC_FLAG_ARBLST CEC_ISR_ARBLST 228 | #define CEC_FLAG_RXACKE CEC_ISR_RXACKE 229 | #define CEC_FLAG_LBPE CEC_ISR_LBPE 230 | #define CEC_FLAG_SBPE CEC_ISR_SBPE 231 | #define CEC_FLAG_BRE CEC_ISR_BRE 232 | #define CEC_FLAG_RXOVR CEC_ISR_RXOVR 233 | #define CEC_FLAG_RXEND CEC_ISR_RXEND 234 | #define CEC_FLAG_RXBR CEC_ISR_RXBR 235 | 236 | #define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00)) 237 | 238 | #define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \ 239 | ((FLAG) == CEC_FLAG_TXERR)|| \ 240 | ((FLAG) == CEC_FLAG_TXUDR)|| \ 241 | ((FLAG) == CEC_FLAG_TXEND)|| \ 242 | ((FLAG) == CEC_FLAG_TXBR)|| \ 243 | ((FLAG) == CEC_FLAG_ARBLST)|| \ 244 | ((FLAG) == CEC_FLAG_RXACKE)|| \ 245 | ((FLAG) == CEC_FLAG_LBPE)|| \ 246 | ((FLAG) == CEC_FLAG_SBPE)|| \ 247 | ((FLAG) == CEC_FLAG_BRE)|| \ 248 | ((FLAG) == CEC_FLAG_RXOVR)|| \ 249 | ((FLAG) == CEC_FLAG_RXEND)|| \ 250 | ((FLAG) == CEC_FLAG_RXBR)) 251 | /** 252 | * @} 253 | */ 254 | 255 | /** 256 | * @} 257 | */ 258 | 259 | /* Exported macro ------------------------------------------------------------*/ 260 | /* Exported functions ------------------------------------------------------- */ 261 | 262 | /* Function used to set the CEC configuration to the default reset state *****/ 263 | void CEC_DeInit(void); 264 | 265 | /* CEC_Initialization and Configuration functions *****************************/ 266 | void CEC_Init(CEC_InitTypeDef* CEC_InitStruct); 267 | void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct); 268 | void CEC_Cmd(FunctionalState NewState); 269 | void CEC_ListenModeCmd(FunctionalState NewState); 270 | void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress); 271 | void CEC_OwnAddressClear(void); 272 | 273 | /* CEC_Data transfers functions ***********************************************/ 274 | void CEC_SendData(uint8_t Data); 275 | uint8_t CEC_ReceiveData(void); 276 | void CEC_StartOfMessage(void); 277 | void CEC_EndOfMessage(void); 278 | 279 | /* CEC_Interrupts and flags management functions ******************************/ 280 | void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState); 281 | FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG); 282 | void CEC_ClearFlag(uint32_t CEC_FLAG); 283 | ITStatus CEC_GetITStatus(uint16_t CEC_IT); 284 | void CEC_ClearITPendingBit(uint16_t CEC_IT); 285 | 286 | #ifdef __cplusplus 287 | } 288 | #endif 289 | 290 | #endif /* __STM32F0XX_CEC_H */ 291 | 292 | /** 293 | * @} 294 | */ 295 | 296 | /** 297 | * @} 298 | */ 299 | 300 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 301 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_comp.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_comp.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the COMP firmware 8 | * library, applicable only for STM32F051 and STM32F072 devices. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_COMP_H 31 | #define __STM32F0XX_COMP_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup COMP 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief COMP Init structure definition 52 | */ 53 | 54 | typedef struct 55 | { 56 | 57 | uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator. 58 | This parameter can be a value of @ref COMP_InvertingInput */ 59 | 60 | uint32_t COMP_Output; /*!< Selects the output redirection of the comparator. 61 | This parameter can be a value of @ref COMP_Output */ 62 | 63 | uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator. 64 | This parameter can be a value of @ref COMP_OutputPolarity */ 65 | 66 | uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator. 67 | This parameter can be a value of @ref COMP_Hysteresis */ 68 | 69 | uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator 70 | and allows to adjust the speed/consumption. 71 | This parameter can be a value of @ref COMP_Mode */ 72 | 73 | }COMP_InitTypeDef; 74 | 75 | /* Exported constants --------------------------------------------------------*/ 76 | 77 | /** @defgroup COMP_Exported_Constants 78 | * @{ 79 | */ 80 | 81 | /** @defgroup COMP_Selection 82 | * @{ 83 | */ 84 | 85 | #define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */ 86 | #define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */ 87 | 88 | #define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \ 89 | ((PERIPH) == COMP_Selection_COMP2)) 90 | 91 | /** 92 | * @} 93 | */ 94 | 95 | /** @defgroup COMP_InvertingInput 96 | * @{ 97 | */ 98 | 99 | #define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */ 100 | #define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */ 101 | #define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */ 102 | #define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */ 103 | #define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */ 104 | #define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */ 105 | #define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */ 106 | 107 | #define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ 108 | ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \ 109 | ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \ 110 | ((INPUT) == COMP_InvertingInput_VREFINT) || \ 111 | ((INPUT) == COMP_InvertingInput_DAC1) || \ 112 | ((INPUT) == COMP_InvertingInput_DAC2) || \ 113 | ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \ 114 | ((INPUT) == COMP_InvertingInput_IO)) 115 | /** 116 | * @} 117 | */ 118 | 119 | /** @defgroup COMP_Output 120 | * @{ 121 | */ 122 | 123 | #define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */ 124 | #define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */ 125 | #define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */ 126 | #define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */ 127 | #define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */ 128 | #define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */ 129 | #define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */ 130 | #define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */ 131 | 132 | 133 | #define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \ 134 | ((OUTPUT) == COMP_Output_TIM1BKIN) || \ 135 | ((OUTPUT) == COMP_Output_TIM1IC1) || \ 136 | ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \ 137 | ((OUTPUT) == COMP_Output_TIM2IC4) || \ 138 | ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \ 139 | ((OUTPUT) == COMP_Output_TIM3IC1) || \ 140 | ((OUTPUT) == COMP_Output_TIM3OCREFCLR)) 141 | /** 142 | * @} 143 | */ 144 | 145 | /** @defgroup COMP_OutputPolarity 146 | * @{ 147 | */ 148 | #define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */ 149 | #define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */ 150 | 151 | #define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \ 152 | ((POL) == COMP_OutputPol_Inverted)) 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /** @defgroup COMP_Hysteresis 159 | * @{ 160 | */ 161 | /* Please refer to the electrical characteristics in the device datasheet for 162 | the hysteresis level */ 163 | #define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */ 164 | #define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */ 165 | #define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */ 166 | #define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */ 167 | 168 | #define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \ 169 | ((HYSTERESIS) == COMP_Hysteresis_Low) || \ 170 | ((HYSTERESIS) == COMP_Hysteresis_Medium) || \ 171 | ((HYSTERESIS) == COMP_Hysteresis_High)) 172 | /** 173 | * @} 174 | */ 175 | 176 | /** @defgroup COMP_Mode 177 | * @{ 178 | */ 179 | /* Please refer to the electrical characteristics in the device datasheet for 180 | the power consumption values */ 181 | #define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */ 182 | #define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */ 183 | #define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */ 184 | #define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */ 185 | 186 | #define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \ 187 | ((MODE) == COMP_Mode_LowPower) || \ 188 | ((MODE) == COMP_Mode_MediumSpeed) || \ 189 | ((MODE) == COMP_Mode_HighSpeed)) 190 | /** 191 | * @} 192 | */ 193 | 194 | /** @defgroup COMP_OutputLevel 195 | * @{ 196 | */ 197 | /* When output polarity is not inverted, comparator output is high when 198 | the non-inverting input is at a higher voltage than the inverting input */ 199 | #define COMP_OutputLevel_High COMP_CSR_COMP1OUT 200 | /* When output polarity is not inverted, comparator output is low when 201 | the non-inverting input is at a lower voltage than the inverting input*/ 202 | #define COMP_OutputLevel_Low ((uint32_t)0x00000000) 203 | 204 | /** 205 | * @} 206 | */ 207 | 208 | /** 209 | * @} 210 | */ 211 | 212 | /* Exported macro ------------------------------------------------------------*/ 213 | /* Exported functions ------------------------------------------------------- */ 214 | 215 | /* Function used to set the COMP configuration to the default reset state ****/ 216 | void COMP_DeInit(void); 217 | 218 | /* Initialization and Configuration functions *********************************/ 219 | void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct); 220 | void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct); 221 | void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState); 222 | void COMP_SwitchCmd(FunctionalState NewState); 223 | uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection); 224 | 225 | /* Window mode control function ***********************************************/ 226 | void COMP_WindowCmd(FunctionalState NewState); 227 | 228 | /* COMP configuration locking function ****************************************/ 229 | void COMP_LockConfig(uint32_t COMP_Selection); 230 | 231 | #ifdef __cplusplus 232 | } 233 | #endif 234 | 235 | #endif /*__STM32F0XX_COMP_H */ 236 | 237 | /** 238 | * @} 239 | */ 240 | 241 | /** 242 | * @} 243 | */ 244 | 245 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 246 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_conf.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief Library configuration file. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2014 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F0XX_CONF_H 30 | #define __STM32F0XX_CONF_H 31 | 32 | /* Includes ------------------------------------------------------------------*/ 33 | /* Comment the line below to disable peripheral header file inclusion */ 34 | #include "stm32f0xx_adc.h" 35 | #include "stm32f0xx_can.h" 36 | #include "stm32f0xx_cec.h" 37 | #include "stm32f0xx_crc.h" 38 | #include "stm32f0xx_crs.h" 39 | #include "stm32f0xx_comp.h" 40 | #include "stm32f0xx_dac.h" 41 | #include "stm32f0xx_dbgmcu.h" 42 | #include "stm32f0xx_dma.h" 43 | #include "stm32f0xx_exti.h" 44 | #include "stm32f0xx_flash.h" 45 | #include "stm32f0xx_gpio.h" 46 | #include "stm32f0xx_syscfg.h" 47 | #include "stm32f0xx_i2c.h" 48 | #include "stm32f0xx_iwdg.h" 49 | #include "stm32f0xx_pwr.h" 50 | #include "stm32f0xx_rcc.h" 51 | #include "stm32f0xx_rtc.h" 52 | #include "stm32f0xx_spi.h" 53 | #include "stm32f0xx_tim.h" 54 | #include "stm32f0xx_usart.h" 55 | #include "stm32f0xx_wwdg.h" 56 | #include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ 57 | 58 | /* Exported types ------------------------------------------------------------*/ 59 | /* Exported constants --------------------------------------------------------*/ 60 | /* Uncomment the line below to expanse the "assert_param" macro in the 61 | Standard Peripheral Library drivers code */ 62 | /* #define USE_FULL_ASSERT 1 */ 63 | 64 | /* Exported macro ------------------------------------------------------------*/ 65 | #ifdef USE_FULL_ASSERT 66 | 67 | /** 68 | * @brief The assert_param macro is used for function's parameters check. 69 | * @param expr: If expr is false, it calls assert_failed function which reports 70 | * the name of the source file and the source line number of the call 71 | * that failed. If expr is true, it returns no value. 72 | * @retval None 73 | */ 74 | #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) 75 | /* Exported functions ------------------------------------------------------- */ 76 | void assert_failed(uint8_t* file, uint32_t line); 77 | #else 78 | #define assert_param(expr) ((void)0) 79 | #endif /* USE_FULL_ASSERT */ 80 | 81 | #endif /* __STM32F0XX_CONF_H */ 82 | 83 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 84 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_crc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_crc.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the CRC firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_CRC_H 31 | #define __STM32F0XX_CRC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /*!< Includes ----------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CRC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup CRC_ReverseInputData 52 | * @{ 53 | */ 54 | #define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */ 55 | #define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */ 56 | #define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */ 57 | #define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */ 58 | 59 | #define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \ 60 | ((DATA) == CRC_ReverseInputData_8bits) || \ 61 | ((DATA) == CRC_ReverseInputData_16bits) || \ 62 | ((DATA) == CRC_ReverseInputData_32bits)) 63 | 64 | /** 65 | * @} 66 | */ 67 | 68 | /** @defgroup CRC_PolynomialSize 69 | * @brief Only applicable for STM32F042 and STM32F072 devices 70 | * @{ 71 | */ 72 | #define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */ 73 | #define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */ 74 | #define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */ 75 | #define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */ 76 | 77 | #define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \ 78 | ((SIZE) == CRC_PolSize_8) || \ 79 | ((SIZE) == CRC_PolSize_16) || \ 80 | ((SIZE) == CRC_PolSize_32)) 81 | 82 | /** 83 | * @} 84 | */ 85 | 86 | /* Exported macro ------------------------------------------------------------*/ 87 | /* Exported functions ------------------------------------------------------- */ 88 | /* Configuration of the CRC computation unit **********************************/ 89 | void CRC_DeInit(void); 90 | void CRC_ResetDR(void); 91 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */ 92 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData); 93 | void CRC_ReverseOutputDataCmd(FunctionalState NewState); 94 | void CRC_SetInitRegister(uint32_t CRC_InitValue); 95 | void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */ 96 | 97 | /* CRC computation ************************************************************/ 98 | uint32_t CRC_CalcCRC(uint32_t CRC_Data); 99 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ 100 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */ 101 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); 102 | uint32_t CRC_GetCRC(void); 103 | 104 | /* Independent register (IDR) access (write/read) *****************************/ 105 | void CRC_SetIDRegister(uint8_t CRC_IDValue); 106 | uint8_t CRC_GetIDRegister(void); 107 | 108 | #ifdef __cplusplus 109 | } 110 | #endif 111 | 112 | #endif /* __STM32F0XX_CRC_H */ 113 | 114 | /** 115 | * @} 116 | */ 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 123 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_crs.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_crs.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the CRS firmware 8 | * library, applicable only for STM32F042 and STM32F072 devices. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_CRS_H 31 | #define __STM32F0XX_CRS_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /*!< Includes ----------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup CRS 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup CRS_Interrupt_Sources 52 | * @{ 53 | */ 54 | #define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ 55 | #define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ 56 | #define CRS_IT_ERR CRS_ISR_ERRF /*!< error */ 57 | #define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ 58 | #define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 59 | #define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 60 | #define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 61 | 62 | #define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ 63 | ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC)) 64 | 65 | #define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \ 66 | ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \ 67 | ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \ 68 | ((IT) == CRS_IT_SYNCMISS)) 69 | 70 | #define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00) 71 | 72 | /** 73 | * @} 74 | */ 75 | 76 | /** @defgroup CRS_Flags 77 | * @{ 78 | */ 79 | #define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */ 80 | #define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */ 81 | #define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */ 82 | #define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */ 83 | #define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */ 84 | #define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */ 85 | #define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/ 86 | 87 | #define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \ 88 | ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \ 89 | ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \ 90 | ((FLAG) == CRS_FLAG_SYNCMISS)) 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup CRS_Synchro_Source 97 | * @{ 98 | */ 99 | #define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */ 100 | #define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 101 | #define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */ 102 | 103 | #define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \ 104 | ((SOURCE) == CRS_SYNCSource_LSE) ||\ 105 | ((SOURCE) == CRS_SYNCSource_USB)) 106 | /** 107 | * @} 108 | */ 109 | 110 | /** @defgroup CRS_SynchroDivider 111 | * @{ 112 | */ 113 | #define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */ 114 | #define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 115 | #define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 116 | #define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 117 | #define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 118 | #define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 119 | #define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 120 | #define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 121 | 122 | #define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\ 123 | ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \ 124 | ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \ 125 | ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128)) 126 | /** 127 | * @} 128 | */ 129 | 130 | /** @defgroup CRS_SynchroPolarity 131 | * @{ 132 | */ 133 | #define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */ 134 | #define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 135 | 136 | #define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \ 137 | ((POLARITY) == CRS_SYNCPolarity_Falling)) 138 | /** 139 | * @} 140 | */ 141 | 142 | 143 | 144 | /* Exported macro ------------------------------------------------------------*/ 145 | /* Exported functions ------------------------------------------------------- */ 146 | /* Configuration of the CRS **********************************/ 147 | void CRS_DeInit(void); 148 | void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue); 149 | void CRS_FrequencyErrorCounterCmd(FunctionalState NewState); 150 | void CRS_AutomaticCalibrationCmd(FunctionalState NewState); 151 | void CRS_SoftwareSynchronizationGenerate(void); 152 | void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue); 153 | void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue); 154 | void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler); 155 | void CRS_SynchronizationSourceConfig(uint32_t CRS_Source); 156 | void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity); 157 | uint32_t CRS_GetReloadValue(void); 158 | uint32_t CRS_GetHSI48CalibrationValue(void); 159 | uint32_t CRS_GetFrequencyErrorValue(void); 160 | uint32_t CRS_GetFrequencyErrorDirection(void); 161 | 162 | /* Interrupts and flags management functions **********************************/ 163 | void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState); 164 | FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG); 165 | void CRS_ClearFlag(uint32_t CRS_FLAG); 166 | ITStatus CRS_GetITStatus(uint32_t CRS_IT); 167 | void CRS_ClearITPendingBit(uint32_t CRS_IT); 168 | 169 | #ifdef __cplusplus 170 | } 171 | #endif 172 | 173 | #endif /* __STM32F0XX_CRS_H */ 174 | 175 | /** 176 | * @} 177 | */ 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 184 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_dbgmcu.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the DBGMCU firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_DBGMCU_H 31 | #define __STM32F0XX_DBGMCU_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup DBGMCU 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | /* Exported constants --------------------------------------------------------*/ 49 | 50 | 51 | /** @defgroup DBGMCU_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | #define DBGMCU_STOP DBGMCU_CR_DBG_STOP 56 | #define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY 57 | #define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00)) 58 | 59 | #define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */ 60 | #define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP 61 | #define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP 62 | #define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */ 63 | #define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP 64 | #define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP 65 | #define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP 66 | #define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP 67 | #define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 68 | #define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */ 69 | #define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00)) 70 | 71 | #define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP 72 | #define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP 73 | #define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP 74 | #define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP 75 | #define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00)) 76 | 77 | /** 78 | * @} 79 | */ 80 | 81 | /* Exported macro ------------------------------------------------------------*/ 82 | /* Exported functions ------------------------------------------------------- */ 83 | 84 | /* Device and Revision ID management functions ********************************/ 85 | uint32_t DBGMCU_GetREVID(void); 86 | uint32_t DBGMCU_GetDEVID(void); 87 | 88 | /* Peripherals Configuration functions ****************************************/ 89 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); 90 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); 91 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState); 92 | 93 | #ifdef __cplusplus 94 | } 95 | #endif 96 | 97 | #endif /* __STM32F0XX_DBGMCU_H */ 98 | 99 | /** 100 | * @} 101 | */ 102 | 103 | /** 104 | * @} 105 | */ 106 | 107 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 108 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_exti.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_exti.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the EXTI 8 | * firmware library 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_EXTI_H 31 | #define __STM32F0XX_EXTI_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup EXTI 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | 49 | /** 50 | * @brief EXTI mode enumeration 51 | */ 52 | 53 | typedef enum 54 | { 55 | EXTI_Mode_Interrupt = 0x00, 56 | EXTI_Mode_Event = 0x04 57 | }EXTIMode_TypeDef; 58 | 59 | #define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event)) 60 | 61 | /** 62 | * @brief EXTI Trigger enumeration 63 | */ 64 | 65 | typedef enum 66 | { 67 | EXTI_Trigger_Rising = 0x08, 68 | EXTI_Trigger_Falling = 0x0C, 69 | EXTI_Trigger_Rising_Falling = 0x10 70 | }EXTITrigger_TypeDef; 71 | 72 | #define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \ 73 | ((TRIGGER) == EXTI_Trigger_Falling) || \ 74 | ((TRIGGER) == EXTI_Trigger_Rising_Falling)) 75 | /** 76 | * @brief EXTI Init Structure definition 77 | */ 78 | 79 | typedef struct 80 | { 81 | uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled. 82 | This parameter can be any combination of @ref EXTI_Lines */ 83 | 84 | EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines. 85 | This parameter can be a value of @ref EXTIMode_TypeDef */ 86 | 87 | EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. 88 | This parameter can be a value of @ref EXTIMode_TypeDef */ 89 | 90 | FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines. 91 | This parameter can be set either to ENABLE or DISABLE */ 92 | }EXTI_InitTypeDef; 93 | 94 | /* Exported constants --------------------------------------------------------*/ 95 | 96 | /** @defgroup EXTI_Exported_Constants 97 | * @{ 98 | */ 99 | /** @defgroup EXTI_Lines 100 | * @{ 101 | */ 102 | 103 | #define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */ 104 | #define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */ 105 | #define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */ 106 | #define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */ 107 | #define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */ 108 | #define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */ 109 | #define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */ 110 | #define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */ 111 | #define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */ 112 | #define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */ 113 | #define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */ 114 | #define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */ 115 | #define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */ 116 | #define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */ 117 | #define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */ 118 | #define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */ 119 | #define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16 120 | Connected to the PVD Output, 121 | not applicable for STM32F030 devices */ 122 | #define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17 123 | Connected to the RTC Alarm 124 | event */ 125 | #define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18 126 | Connected to the USB 127 | event, only applicable for 128 | STM32F072 devices */ 129 | #define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19 130 | Connected to the RTC Tamper 131 | and Time Stamp events */ 132 | #define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20 133 | Connected to the RTC wakeup 134 | event, only applicable for 135 | STM32F072 devices */ 136 | #define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21 137 | Connected to the Comparator 1 138 | event, only applicable for STM32F051 139 | ans STM32F072 devices */ 140 | #define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22 141 | Connected to the Comparator 2 142 | event, only applicable for STM32F051 143 | and STM32F072 devices */ 144 | #define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23 145 | Connected to the I2C1 wakeup 146 | event, not applicable for STM32F030 devices */ 147 | #define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25 148 | Connected to the USART1 wakeup 149 | event, not applicable for STM32F030 devices */ 150 | #define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26 151 | Connected to the USART2 wakeup 152 | event, applicable only for 153 | STM32F072 devices */ 154 | #define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27 155 | Connected to the CEC wakeup 156 | event, applicable only for STM32F051 157 | and STM32F072 devices */ 158 | #define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31 159 | Connected to the VDD USB monitor 160 | event, applicable only for 161 | STM32F072 devices */ 162 | #define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00)) 163 | 164 | #define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \ 165 | ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \ 166 | ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \ 167 | ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \ 168 | ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \ 169 | ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \ 170 | ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \ 171 | ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \ 172 | ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \ 173 | ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \ 174 | ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \ 175 | ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \ 176 | ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \ 177 | ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31)) 178 | 179 | /** 180 | * @} 181 | */ 182 | 183 | /** 184 | * @} 185 | */ 186 | 187 | /* Exported macro ------------------------------------------------------------*/ 188 | /* Exported functions ------------------------------------------------------- */ 189 | /* Function used to set the EXTI configuration to the default reset state *****/ 190 | void EXTI_DeInit(void); 191 | 192 | /* Initialization and Configuration functions *********************************/ 193 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); 194 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); 195 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); 196 | 197 | /* Interrupts and flags management functions **********************************/ 198 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); 199 | void EXTI_ClearFlag(uint32_t EXTI_Line); 200 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); 201 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line); 202 | 203 | #ifdef __cplusplus 204 | } 205 | #endif 206 | 207 | #endif /* __STM32F0XX_EXTI_H */ 208 | /** 209 | * @} 210 | */ 211 | 212 | /** 213 | * @} 214 | */ 215 | 216 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 217 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_iwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_iwdg.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the IWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_IWDG_H 31 | #define __STM32F0XX_IWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup IWDG 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | /* Exported constants --------------------------------------------------------*/ 50 | 51 | /** @defgroup IWDG_Exported_Constants 52 | * @{ 53 | */ 54 | 55 | /** @defgroup IWDG_WriteAccess 56 | * @{ 57 | */ 58 | 59 | #define IWDG_WriteAccess_Enable ((uint16_t)0x5555) 60 | #define IWDG_WriteAccess_Disable ((uint16_t)0x0000) 61 | #define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \ 62 | ((ACCESS) == IWDG_WriteAccess_Disable)) 63 | /** 64 | * @} 65 | */ 66 | 67 | /** @defgroup IWDG_prescaler 68 | * @{ 69 | */ 70 | 71 | #define IWDG_Prescaler_4 ((uint8_t)0x00) 72 | #define IWDG_Prescaler_8 ((uint8_t)0x01) 73 | #define IWDG_Prescaler_16 ((uint8_t)0x02) 74 | #define IWDG_Prescaler_32 ((uint8_t)0x03) 75 | #define IWDG_Prescaler_64 ((uint8_t)0x04) 76 | #define IWDG_Prescaler_128 ((uint8_t)0x05) 77 | #define IWDG_Prescaler_256 ((uint8_t)0x06) 78 | #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \ 79 | ((PRESCALER) == IWDG_Prescaler_8) || \ 80 | ((PRESCALER) == IWDG_Prescaler_16) || \ 81 | ((PRESCALER) == IWDG_Prescaler_32) || \ 82 | ((PRESCALER) == IWDG_Prescaler_64) || \ 83 | ((PRESCALER) == IWDG_Prescaler_128)|| \ 84 | ((PRESCALER) == IWDG_Prescaler_256)) 85 | /** 86 | * @} 87 | */ 88 | 89 | /** @defgroup IWDG_Flag 90 | * @{ 91 | */ 92 | 93 | #define IWDG_FLAG_PVU IWDG_SR_PVU 94 | #define IWDG_FLAG_RVU IWDG_SR_RVU 95 | #define IWDG_FLAG_WVU IWDG_SR_WVU 96 | #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \ 97 | ((FLAG) == IWDG_FLAG_WVU)) 98 | 99 | #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF) 100 | 101 | #define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF) 102 | /** 103 | * @} 104 | */ 105 | 106 | /** 107 | * @} 108 | */ 109 | 110 | /* Exported macro ------------------------------------------------------------*/ 111 | /* Exported functions ------------------------------------------------------- */ 112 | 113 | /* Prescaler and Counter configuration functions ******************************/ 114 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); 115 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); 116 | void IWDG_SetReload(uint16_t Reload); 117 | void IWDG_ReloadCounter(void); 118 | void IWDG_SetWindowValue(uint16_t WindowValue); 119 | 120 | /* IWDG activation function ***************************************************/ 121 | void IWDG_Enable(void); 122 | 123 | /* Flag management function ***************************************************/ 124 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); 125 | 126 | #ifdef __cplusplus 127 | } 128 | #endif 129 | 130 | #endif /* __STM32F0XX_IWDG_H */ 131 | 132 | /** 133 | * @} 134 | */ 135 | 136 | /** 137 | * @} 138 | */ 139 | 140 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 141 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_misc.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_misc.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the miscellaneous 8 | * firmware library functions (add-on to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_MISC_H 31 | #define __STM32F0XX_MISC_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup MISC 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /** 51 | * @brief NVIC Init Structure definition 52 | */ 53 | 54 | typedef struct 55 | { 56 | uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. 57 | This parameter can be a value of @ref IRQn_Type 58 | (For the complete STM32 Devices IRQ Channels list, 59 | please refer to stm32f0xx.h file) */ 60 | 61 | uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified 62 | in NVIC_IRQChannel. This parameter can be a value 63 | between 0 and 3. */ 64 | 65 | FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel 66 | will be enabled or disabled. 67 | This parameter can be set either to ENABLE or DISABLE */ 68 | } NVIC_InitTypeDef; 69 | 70 | /** 71 | * 72 | @verbatim 73 | 74 | @endverbatim 75 | */ 76 | 77 | /* Exported constants --------------------------------------------------------*/ 78 | 79 | /** @defgroup MISC_Exported_Constants 80 | * @{ 81 | */ 82 | 83 | /** @defgroup MISC_System_Low_Power 84 | * @{ 85 | */ 86 | 87 | #define NVIC_LP_SEVONPEND ((uint8_t)0x10) 88 | #define NVIC_LP_SLEEPDEEP ((uint8_t)0x04) 89 | #define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02) 90 | #define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \ 91 | ((LP) == NVIC_LP_SLEEPDEEP) || \ 92 | ((LP) == NVIC_LP_SLEEPONEXIT)) 93 | /** 94 | * @} 95 | */ 96 | 97 | /** @defgroup MISC_Preemption_Priority_Group 98 | * @{ 99 | */ 100 | #define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04) 101 | 102 | /** 103 | * @} 104 | */ 105 | 106 | /** @defgroup MISC_SysTick_clock_source 107 | * @{ 108 | */ 109 | 110 | #define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) 111 | #define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) 112 | #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \ 113 | ((SOURCE) == SysTick_CLKSource_HCLK_Div8)) 114 | /** 115 | * @} 116 | */ 117 | 118 | /** 119 | * @} 120 | */ 121 | 122 | /* Exported macro ------------------------------------------------------------*/ 123 | /* Exported functions ------------------------------------------------------- */ 124 | 125 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); 126 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState); 127 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource); 128 | 129 | #ifdef __cplusplus 130 | } 131 | #endif 132 | 133 | #endif /* __STM32F0XX_MISC_H */ 134 | 135 | /** 136 | * @} 137 | */ 138 | 139 | /** 140 | * @} 141 | */ 142 | 143 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 144 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_pwr.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_pwr.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the PWR firmware 8 | * library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_PWR_H 31 | #define __STM32F0XX_PWR_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup PWR 45 | * @{ 46 | */ 47 | 48 | /* Exported types ------------------------------------------------------------*/ 49 | 50 | /* Exported constants --------------------------------------------------------*/ 51 | 52 | /** @defgroup PWR_Exported_Constants 53 | * @{ 54 | */ 55 | 56 | /** @defgroup PWR_PVD_detection_level 57 | * @brief This parameters are only applicable for STM32F051 and STM32F072 devices 58 | * @{ 59 | */ 60 | 61 | #define PWR_PVDLevel_0 PWR_CR_PLS_LEV0 62 | #define PWR_PVDLevel_1 PWR_CR_PLS_LEV1 63 | #define PWR_PVDLevel_2 PWR_CR_PLS_LEV2 64 | #define PWR_PVDLevel_3 PWR_CR_PLS_LEV3 65 | #define PWR_PVDLevel_4 PWR_CR_PLS_LEV4 66 | #define PWR_PVDLevel_5 PWR_CR_PLS_LEV5 67 | #define PWR_PVDLevel_6 PWR_CR_PLS_LEV6 68 | #define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 69 | 70 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \ 71 | ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \ 72 | ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \ 73 | ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7)) 74 | /** 75 | * @} 76 | */ 77 | 78 | /** @defgroup PWR_WakeUp_Pins 79 | * @{ 80 | */ 81 | 82 | #define PWR_WakeUpPin_1 PWR_CSR_EWUP1 83 | #define PWR_WakeUpPin_2 PWR_CSR_EWUP2 84 | #define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */ 85 | #define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */ 86 | #define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */ 87 | #define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */ 88 | #define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */ 89 | #define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */ 90 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \ 91 | ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \ 92 | ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \ 93 | ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8)) 94 | /** 95 | * @} 96 | */ 97 | 98 | 99 | /** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode 100 | * @{ 101 | */ 102 | 103 | #define PWR_Regulator_ON ((uint32_t)0x00000000) 104 | #define PWR_Regulator_LowPower PWR_CR_LPSDSR 105 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \ 106 | ((REGULATOR) == PWR_Regulator_LowPower)) 107 | /** 108 | * @} 109 | */ 110 | 111 | /** @defgroup PWR_SLEEP_mode_entry 112 | * @{ 113 | */ 114 | 115 | #define PWR_SLEEPEntry_WFI ((uint8_t)0x01) 116 | #define PWR_SLEEPEntry_WFE ((uint8_t)0x02) 117 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE)) 118 | 119 | /** 120 | * @} 121 | */ 122 | 123 | /** @defgroup PWR_STOP_mode_entry 124 | * @{ 125 | */ 126 | 127 | #define PWR_STOPEntry_WFI ((uint8_t)0x01) 128 | #define PWR_STOPEntry_WFE ((uint8_t)0x02) 129 | #define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03) 130 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\ 131 | ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT)) 132 | 133 | /** 134 | * @} 135 | */ 136 | 137 | /** @defgroup PWR_Flag 138 | * @{ 139 | */ 140 | 141 | #define PWR_FLAG_WU PWR_CSR_WUF 142 | #define PWR_FLAG_SB PWR_CSR_SBF 143 | #define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */ 144 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF 145 | 146 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ 147 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY)) 148 | 149 | #define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB)) 150 | /** 151 | * @} 152 | */ 153 | 154 | /** 155 | * @} 156 | */ 157 | 158 | /* Exported macro ------------------------------------------------------------*/ 159 | /* Exported functions ------------------------------------------------------- */ 160 | 161 | /* Function used to set the PWR configuration to the default reset state ******/ 162 | void PWR_DeInit(void); 163 | 164 | /* Backup Domain Access function **********************************************/ 165 | void PWR_BackupAccessCmd(FunctionalState NewState); 166 | 167 | /* PVD configuration functions ************************************************/ 168 | void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */ 169 | void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */ 170 | 171 | /* WakeUp pins configuration functions ****************************************/ 172 | void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState); 173 | 174 | /* Low Power modes configuration functions ************************************/ 175 | void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry); 176 | void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); 177 | void PWR_EnterSTANDBYMode(void); 178 | 179 | /* Flags management functions *************************************************/ 180 | FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); 181 | void PWR_ClearFlag(uint32_t PWR_FLAG); 182 | 183 | #ifdef __cplusplus 184 | } 185 | #endif 186 | 187 | #endif /* __STM32F0XX_PWR_H */ 188 | 189 | /** 190 | * @} 191 | */ 192 | 193 | /** 194 | * @} 195 | */ 196 | 197 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 198 | -------------------------------------------------------------------------------- /StdPeriph_Driver/inc/stm32f0xx_wwdg.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_wwdg.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains all the functions prototypes for the WWDG 8 | * firmware library. 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Define to prevent recursive inclusion -------------------------------------*/ 30 | #ifndef __STM32F0XX_WWDG_H 31 | #define __STM32F0XX_WWDG_H 32 | 33 | #ifdef __cplusplus 34 | extern "C" { 35 | #endif 36 | 37 | /* Includes ------------------------------------------------------------------*/ 38 | #include "stm32f0xx.h" 39 | 40 | /** @addtogroup STM32F0xx_StdPeriph_Driver 41 | * @{ 42 | */ 43 | 44 | /** @addtogroup WWDG 45 | * @{ 46 | */ 47 | /* Exported types ------------------------------------------------------------*/ 48 | /* Exported constants --------------------------------------------------------*/ 49 | 50 | /** @defgroup WWDG_Exported_Constants 51 | * @{ 52 | */ 53 | 54 | /** @defgroup WWDG_Prescaler 55 | * @{ 56 | */ 57 | 58 | #define WWDG_Prescaler_1 ((uint32_t)0x00000000) 59 | #define WWDG_Prescaler_2 ((uint32_t)0x00000080) 60 | #define WWDG_Prescaler_4 ((uint32_t)0x00000100) 61 | #define WWDG_Prescaler_8 ((uint32_t)0x00000180) 62 | #define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \ 63 | ((PRESCALER) == WWDG_Prescaler_2) || \ 64 | ((PRESCALER) == WWDG_Prescaler_4) || \ 65 | ((PRESCALER) == WWDG_Prescaler_8)) 66 | #define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F) 67 | #define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F)) 68 | 69 | /** 70 | * @} 71 | */ 72 | 73 | /** 74 | * @} 75 | */ 76 | 77 | /* Exported macro ------------------------------------------------------------*/ 78 | /* Exported functions ------------------------------------------------------- */ 79 | /* Function used to set the WWDG configuration to the default reset state ****/ 80 | void WWDG_DeInit(void); 81 | 82 | /* Prescaler, Refresh window and Counter configuration functions **************/ 83 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); 84 | void WWDG_SetWindowValue(uint8_t WindowValue); 85 | void WWDG_EnableIT(void); 86 | void WWDG_SetCounter(uint8_t Counter); 87 | 88 | /* WWDG activation functions **************************************************/ 89 | void WWDG_Enable(uint8_t Counter); 90 | 91 | /* Interrupts and flags management functions **********************************/ 92 | FlagStatus WWDG_GetFlagStatus(void); 93 | void WWDG_ClearFlag(void); 94 | 95 | #ifdef __cplusplus 96 | } 97 | #endif 98 | 99 | #endif /* __STM32F0XX_WWDG_H */ 100 | 101 | /** 102 | * @} 103 | */ 104 | 105 | /** 106 | * @} 107 | */ 108 | 109 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 110 | -------------------------------------------------------------------------------- /StdPeriph_Driver/src/stm32f0xx_crc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_crc.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of CRC computation unit peripheral: 9 | * + Configuration of the CRC computation unit 10 | * + CRC computation of one/many 32-bit data 11 | * + CRC Independent register (IDR) access 12 | * 13 | * @verbatim 14 | =============================================================================== 15 | ##### How to use this driver ##### 16 | =============================================================================== 17 | [..] 18 | 19 | (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE) 20 | function 21 | (+) If required, select the reverse operation on input data 22 | using CRC_ReverseInputDataSelect() 23 | (+) If required, enable the reverse operation on output data 24 | using CRC_ReverseOutputDataCmd(Enable) 25 | (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data 26 | or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit 27 | data buffer 28 | (@) To compute the CRC of a new data use CRC_ResetDR() to reset 29 | the CRC computation unit before starting the computation 30 | otherwise you can get wrong CRC values. 31 | 32 | @endverbatim 33 | * 34 | ****************************************************************************** 35 | * @attention 36 | * 37 | *

© COPYRIGHT 2014 STMicroelectronics

38 | * 39 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 40 | * You may not use this file except in compliance with the License. 41 | * You may obtain a copy of the License at: 42 | * 43 | * http://www.st.com/software_license_agreement_liberty_v2 44 | * 45 | * Unless required by applicable law or agreed to in writing, software 46 | * distributed under the License is distributed on an "AS IS" BASIS, 47 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 48 | * See the License for the specific language governing permissions and 49 | * limitations under the License. 50 | * 51 | ****************************************************************************** 52 | */ 53 | 54 | /* Includes ------------------------------------------------------------------*/ 55 | #include "stm32f0xx_crc.h" 56 | 57 | /** @addtogroup STM32F0xx_StdPeriph_Driver 58 | * @{ 59 | */ 60 | 61 | /** @defgroup CRC 62 | * @brief CRC driver modules 63 | * @{ 64 | */ 65 | 66 | /* Private typedef -----------------------------------------------------------*/ 67 | /* Private define ------------------------------------------------------------*/ 68 | /* Private macro -------------------------------------------------------------*/ 69 | /* Private variables ---------------------------------------------------------*/ 70 | /* Private function prototypes -----------------------------------------------*/ 71 | /* Private functions ---------------------------------------------------------*/ 72 | 73 | /** @defgroup CRC_Private_Functions 74 | * @{ 75 | */ 76 | 77 | /** @defgroup CRC_Group1 Configuration of the CRC computation unit functions 78 | * @brief Configuration of the CRC computation unit functions 79 | * 80 | @verbatim 81 | =============================================================================== 82 | ##### CRC configuration functions ##### 83 | =============================================================================== 84 | 85 | @endverbatim 86 | * @{ 87 | */ 88 | 89 | /** 90 | * @brief Deinitializes CRC peripheral registers to their default reset values. 91 | * @param None 92 | * @retval None 93 | */ 94 | void CRC_DeInit(void) 95 | { 96 | /* Set DR register to reset value */ 97 | CRC->DR = 0xFFFFFFFF; 98 | 99 | /* Set the POL register to the reset value: 0x04C11DB7 */ 100 | CRC->POL = 0x04C11DB7; 101 | 102 | /* Reset IDR register */ 103 | CRC->IDR = 0x00; 104 | 105 | /* Set INIT register to reset value */ 106 | CRC->INIT = 0xFFFFFFFF; 107 | 108 | /* Reset the CRC calculation unit */ 109 | CRC->CR = CRC_CR_RESET; 110 | } 111 | 112 | /** 113 | * @brief Resets the CRC calculation unit and sets INIT register content in DR register. 114 | * @param None 115 | * @retval None 116 | */ 117 | void CRC_ResetDR(void) 118 | { 119 | /* Reset CRC generator */ 120 | CRC->CR |= CRC_CR_RESET; 121 | } 122 | 123 | /** 124 | * @brief Selects the polynomial size. This function is only applicable for 125 | * STM32F072 devices. 126 | * @param CRC_PolSize: Specifies the polynomial size. 127 | * This parameter can be: 128 | * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation 129 | * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation 130 | * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation 131 | * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation 132 | * @retval None 133 | */ 134 | void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize) 135 | { 136 | uint32_t tmpcr = 0; 137 | 138 | /* Check the parameter */ 139 | assert_param(IS_CRC_POL_SIZE(CRC_PolSize)); 140 | 141 | /* Get CR register value */ 142 | tmpcr = CRC->CR; 143 | 144 | /* Reset POL_SIZE bits */ 145 | tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE); 146 | /* Set the polynomial size */ 147 | tmpcr |= (uint32_t)CRC_PolSize; 148 | 149 | /* Write to CR register */ 150 | CRC->CR = (uint32_t)tmpcr; 151 | } 152 | 153 | /** 154 | * @brief Selects the reverse operation to be performed on input data. 155 | * @param CRC_ReverseInputData: Specifies the reverse operation on input data. 156 | * This parameter can be: 157 | * @arg CRC_ReverseInputData_No: No reverse operation is performed 158 | * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits 159 | * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits 160 | * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits 161 | * @retval None 162 | */ 163 | void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData) 164 | { 165 | uint32_t tmpcr = 0; 166 | 167 | /* Check the parameter */ 168 | assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData)); 169 | 170 | /* Get CR register value */ 171 | tmpcr = CRC->CR; 172 | 173 | /* Reset REV_IN bits */ 174 | tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN); 175 | /* Set the reverse operation */ 176 | tmpcr |= (uint32_t)CRC_ReverseInputData; 177 | 178 | /* Write to CR register */ 179 | CRC->CR = (uint32_t)tmpcr; 180 | } 181 | 182 | /** 183 | * @brief Enables or disable the reverse operation on output data. 184 | * The reverse operation on output data is performed on 32-bit. 185 | * @param NewState: new state of the reverse operation on output data. 186 | * This parameter can be: ENABLE or DISABLE. 187 | * @retval None 188 | */ 189 | void CRC_ReverseOutputDataCmd(FunctionalState NewState) 190 | { 191 | /* Check the parameters */ 192 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 193 | 194 | if (NewState != DISABLE) 195 | { 196 | /* Enable reverse operation on output data */ 197 | CRC->CR |= CRC_CR_REV_OUT; 198 | } 199 | else 200 | { 201 | /* Disable reverse operation on output data */ 202 | CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT); 203 | } 204 | } 205 | 206 | /** 207 | * @brief Initializes the INIT register. 208 | * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register 209 | * @param CRC_InitValue: Programmable initial CRC value 210 | * @retval None 211 | */ 212 | void CRC_SetInitRegister(uint32_t CRC_InitValue) 213 | { 214 | CRC->INIT = CRC_InitValue; 215 | } 216 | 217 | /** 218 | * @brief Initializes the polynomail coefficients. This function is only 219 | * applicable for STM32F072 devices. 220 | * @param CRC_Pol: Polynomial to be used for CRC calculation. 221 | * @retval None 222 | */ 223 | void CRC_SetPolynomial(uint32_t CRC_Pol) 224 | { 225 | CRC->POL = CRC_Pol; 226 | } 227 | 228 | /** 229 | * @} 230 | */ 231 | 232 | /** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions 233 | * @brief CRC computation of one/many 32-bit data functions 234 | * 235 | @verbatim 236 | =============================================================================== 237 | ##### CRC computation functions ##### 238 | =============================================================================== 239 | 240 | @endverbatim 241 | * @{ 242 | */ 243 | 244 | /** 245 | * @brief Computes the 32-bit CRC of a given data word(32-bit). 246 | * @param CRC_Data: data word(32-bit) to compute its CRC 247 | * @retval 32-bit CRC 248 | */ 249 | uint32_t CRC_CalcCRC(uint32_t CRC_Data) 250 | { 251 | CRC->DR = CRC_Data; 252 | 253 | return (CRC->DR); 254 | } 255 | 256 | /** 257 | * @brief Computes the 16-bit CRC of a given 16-bit data. This function is only 258 | * applicable for STM32F072 devices. 259 | * @param CRC_Data: data half-word(16-bit) to compute its CRC 260 | * @retval 16-bit CRC 261 | */ 262 | uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data) 263 | { 264 | *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data; 265 | 266 | return (CRC->DR); 267 | } 268 | 269 | /** 270 | * @brief Computes the 8-bit CRC of a given 8-bit data. This function is only 271 | * applicable for STM32F072 devices. 272 | * @param CRC_Data: 8-bit data to compute its CRC 273 | * @retval 8-bit CRC 274 | */ 275 | uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data) 276 | { 277 | *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data; 278 | 279 | return (CRC->DR); 280 | } 281 | 282 | /** 283 | * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). 284 | * @param pBuffer: pointer to the buffer containing the data to be computed 285 | * @param BufferLength: length of the buffer to be computed 286 | * @retval 32-bit CRC 287 | */ 288 | uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) 289 | { 290 | uint32_t index = 0; 291 | 292 | for(index = 0; index < BufferLength; index++) 293 | { 294 | CRC->DR = pBuffer[index]; 295 | } 296 | return (CRC->DR); 297 | } 298 | 299 | /** 300 | * @brief Returns the current CRC value. 301 | * @param None 302 | * @retval 32-bit CRC 303 | */ 304 | uint32_t CRC_GetCRC(void) 305 | { 306 | return (CRC->DR); 307 | } 308 | 309 | /** 310 | * @} 311 | */ 312 | 313 | /** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions 314 | * @brief CRC Independent Register (IDR) access (write/read) functions 315 | * 316 | @verbatim 317 | =============================================================================== 318 | ##### CRC Independent Register (IDR) access functions ##### 319 | =============================================================================== 320 | 321 | @endverbatim 322 | * @{ 323 | */ 324 | 325 | /** 326 | * @brief Stores an 8-bit data in the Independent Data(ID) register. 327 | * @param CRC_IDValue: 8-bit value to be stored in the ID register 328 | * @retval None 329 | */ 330 | void CRC_SetIDRegister(uint8_t CRC_IDValue) 331 | { 332 | CRC->IDR = CRC_IDValue; 333 | } 334 | 335 | /** 336 | * @brief Returns the 8-bit data stored in the Independent Data(ID) register 337 | * @param None 338 | * @retval 8-bit value of the ID register 339 | */ 340 | uint8_t CRC_GetIDRegister(void) 341 | { 342 | return (CRC->IDR); 343 | } 344 | 345 | /** 346 | * @} 347 | */ 348 | 349 | /** 350 | * @} 351 | */ 352 | 353 | /** 354 | * @} 355 | */ 356 | 357 | /** 358 | * @} 359 | */ 360 | 361 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 362 | -------------------------------------------------------------------------------- /StdPeriph_Driver/src/stm32f0xx_dbgmcu.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_dbgmcu.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the Debug MCU (DBGMCU) peripheral: 9 | * + Device and Revision ID management 10 | * + Peripherals Configuration 11 | * @verbatim 12 | * @endverbatim 13 | * 14 | ****************************************************************************** 15 | * @attention 16 | * 17 | *

© COPYRIGHT 2014 STMicroelectronics

18 | * 19 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 20 | * You may not use this file except in compliance with the License. 21 | * You may obtain a copy of the License at: 22 | * 23 | * http://www.st.com/software_license_agreement_liberty_v2 24 | * 25 | * Unless required by applicable law or agreed to in writing, software 26 | * distributed under the License is distributed on an "AS IS" BASIS, 27 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 28 | * See the License for the specific language governing permissions and 29 | * limitations under the License. 30 | * 31 | ****************************************************************************** 32 | */ 33 | 34 | /* Includes ------------------------------------------------------------------*/ 35 | #include "stm32f0xx_dbgmcu.h" 36 | 37 | /** @addtogroup STM32F0xx_StdPeriph_Driver 38 | * @{ 39 | */ 40 | 41 | /** @defgroup DBGMCU 42 | * @brief DBGMCU driver modules 43 | * @{ 44 | */ 45 | 46 | /* Private typedef -----------------------------------------------------------*/ 47 | /* Private define ------------------------------------------------------------*/ 48 | #define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) 49 | 50 | /* Private macro -------------------------------------------------------------*/ 51 | /* Private variables ---------------------------------------------------------*/ 52 | /* Private function prototypes -----------------------------------------------*/ 53 | /* Private functions ---------------------------------------------------------*/ 54 | 55 | /** @defgroup DBGMCU_Private_Functions 56 | * @{ 57 | */ 58 | 59 | 60 | /** @defgroup DBGMCU_Group1 Device and Revision ID management functions 61 | * @brief Device and Revision ID management functions 62 | * 63 | @verbatim 64 | ============================================================================== 65 | ##### Device and Revision ID management functions ##### 66 | ============================================================================== 67 | 68 | @endverbatim 69 | * @{ 70 | */ 71 | 72 | /** 73 | * @brief Returns the device revision identifier. 74 | * @param None 75 | * @retval Device revision identifier 76 | */ 77 | uint32_t DBGMCU_GetREVID(void) 78 | { 79 | return(DBGMCU->IDCODE >> 16); 80 | } 81 | 82 | /** 83 | * @brief Returns the device identifier. 84 | * @param None 85 | * @retval Device identifier 86 | */ 87 | uint32_t DBGMCU_GetDEVID(void) 88 | { 89 | return(DBGMCU->IDCODE & IDCODE_DEVID_MASK); 90 | } 91 | 92 | /** 93 | * @} 94 | */ 95 | 96 | /** @defgroup DBGMCU_Group2 Peripherals Configuration functions 97 | * @brief Peripherals Configuration 98 | * 99 | @verbatim 100 | ============================================================================== 101 | ##### Peripherals Configuration functions ##### 102 | ============================================================================== 103 | 104 | @endverbatim 105 | * @{ 106 | */ 107 | 108 | /** 109 | * @brief Configures low power mode behavior when the MCU is in Debug mode. 110 | * @param DBGMCU_Periph: specifies the low power mode. 111 | * This parameter can be any combination of the following values: 112 | * @arg DBGMCU_STOP: Keep debugger connection during STOP mode 113 | * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode 114 | * @param NewState: new state of the specified low power mode in Debug mode. 115 | * This parameter can be: ENABLE or DISABLE. 116 | * @retval None 117 | */ 118 | void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) 119 | { 120 | /* Check the parameters */ 121 | assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph)); 122 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 123 | 124 | if (NewState != DISABLE) 125 | { 126 | DBGMCU->CR |= DBGMCU_Periph; 127 | } 128 | else 129 | { 130 | DBGMCU->CR &= ~DBGMCU_Periph; 131 | } 132 | } 133 | 134 | 135 | /** 136 | * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode. 137 | * @param DBGMCU_Periph: specifies the APB1 peripheral. 138 | * This parameter can be any combination of the following values: 139 | * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted, 140 | * not applicable for STM32F030 devices 141 | * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted 142 | * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted 143 | * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted, 144 | * applicable only for STM32F072 devices 145 | * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 146 | * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped 147 | * when Core is halted. 148 | * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted 149 | * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted 150 | * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped 151 | * when Core is halted 152 | * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted, 153 | * applicable only for STM32F042 and STM32F072 devices 154 | * @param NewState: new state of the specified APB1 peripheral in Debug mode. 155 | * This parameter can be: ENABLE or DISABLE. 156 | * @retval None 157 | */ 158 | void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) 159 | { 160 | /* Check the parameters */ 161 | assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph)); 162 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 163 | 164 | if (NewState != DISABLE) 165 | { 166 | DBGMCU->APB1FZ |= DBGMCU_Periph; 167 | } 168 | else 169 | { 170 | DBGMCU->APB1FZ &= ~DBGMCU_Periph; 171 | } 172 | } 173 | 174 | /** 175 | * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode. 176 | * @param DBGMCU_Periph: specifies the APB2 peripheral. 177 | * This parameter can be any combination of the following values: 178 | * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted 179 | * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted 180 | * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted 181 | * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted 182 | * @param NewState: new state of the specified APB2 peripheral in Debug mode. 183 | * This parameter can be: ENABLE or DISABLE. 184 | * @retval None 185 | */ 186 | void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState) 187 | { 188 | /* Check the parameters */ 189 | assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph)); 190 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 191 | 192 | if (NewState != DISABLE) 193 | { 194 | DBGMCU->APB2FZ |= DBGMCU_Periph; 195 | } 196 | else 197 | { 198 | DBGMCU->APB2FZ &= ~DBGMCU_Periph; 199 | } 200 | } 201 | 202 | /** 203 | * @} 204 | */ 205 | 206 | /** 207 | * @} 208 | */ 209 | 210 | /** 211 | * @} 212 | */ 213 | 214 | /** 215 | * @} 216 | */ 217 | 218 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 219 | -------------------------------------------------------------------------------- /StdPeriph_Driver/src/stm32f0xx_exti.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_exti.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the EXTI peripheral: 9 | * + Initialization and Configuration 10 | * + Interrupts and flags management 11 | * 12 | * @verbatim 13 | ============================================================================== 14 | ##### EXTI features ##### 15 | ============================================================================== 16 | [..] External interrupt/event lines are mapped as following: 17 | (#) All available GPIO pins are connected to the 16 external 18 | interrupt/event lines from EXTI0 to EXTI15. 19 | (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices. 20 | (#) EXTI line 17 is connected to the RTC Alarm event. 21 | (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices. 22 | (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events. 23 | (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices. 24 | (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices. 25 | (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices. 26 | (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices. 27 | (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices. 28 | (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices. 29 | (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices. 30 | (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices. 31 | 32 | ##### How to use this driver ##### 33 | ============================================================================== 34 | [..] In order to use an I/O pin as an external interrupt source, follow 35 | steps below: 36 | (#) Configure the I/O in input mode using GPIO_Init() 37 | (#) Select the input source pin for the EXTI line using 38 | SYSCFG_EXTILineConfig(). 39 | (#) Select the mode(interrupt, event) and configure the trigger selection 40 | (Rising, falling or both) using EXTI_Init(). For the internal interrupt, 41 | the trigger selection is not needed( the active edge is always the rising one). 42 | (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init(). 43 | (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt(). 44 | [..] 45 | (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx 46 | registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE); 47 | @endverbatim 48 | * 49 | ****************************************************************************** 50 | * @attention 51 | * 52 | *

© COPYRIGHT 2014 STMicroelectronics

53 | * 54 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 55 | * You may not use this file except in compliance with the License. 56 | * You may obtain a copy of the License at: 57 | * 58 | * http://www.st.com/software_license_agreement_liberty_v2 59 | * 60 | * Unless required by applicable law or agreed to in writing, software 61 | * distributed under the License is distributed on an "AS IS" BASIS, 62 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 63 | * See the License for the specific language governing permissions and 64 | * limitations under the License. 65 | * 66 | ****************************************************************************** 67 | */ 68 | 69 | /* Includes ------------------------------------------------------------------*/ 70 | #include "stm32f0xx_exti.h" 71 | 72 | /** @addtogroup STM32F0xx_StdPeriph_Driver 73 | * @{ 74 | */ 75 | 76 | /** @defgroup EXTI 77 | * @brief EXTI driver modules 78 | * @{ 79 | */ 80 | 81 | /* Private typedef -----------------------------------------------------------*/ 82 | /* Private define ------------------------------------------------------------*/ 83 | #define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ 84 | 85 | /* Private macro -------------------------------------------------------------*/ 86 | /* Private variables ---------------------------------------------------------*/ 87 | /* Private function prototypes -----------------------------------------------*/ 88 | /* Private functions ---------------------------------------------------------*/ 89 | 90 | /** @defgroup EXTI_Private_Functions 91 | * @{ 92 | */ 93 | 94 | /** @defgroup EXTI_Group1 Initialization and Configuration functions 95 | * @brief Initialization and Configuration functions 96 | * 97 | @verbatim 98 | ============================================================================== 99 | ##### Initialization and Configuration functions ##### 100 | ============================================================================== 101 | 102 | @endverbatim 103 | * @{ 104 | */ 105 | 106 | /** 107 | * @brief Deinitializes the EXTI peripheral registers to their default reset 108 | * values. 109 | * @param None 110 | * @retval None 111 | */ 112 | void EXTI_DeInit(void) 113 | { 114 | EXTI->IMR = 0x0F940000; 115 | EXTI->EMR = 0x00000000; 116 | EXTI->RTSR = 0x00000000; 117 | EXTI->FTSR = 0x00000000; 118 | EXTI->PR = 0x006BFFFF; 119 | } 120 | 121 | /** 122 | * @brief Initializes the EXTI peripheral according to the specified 123 | * parameters in the EXTI_InitStruct. 124 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that 125 | * contains the configuration information for the EXTI peripheral. 126 | * @retval None 127 | */ 128 | void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct) 129 | { 130 | uint32_t tmp = 0; 131 | 132 | /* Check the parameters */ 133 | assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode)); 134 | assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger)); 135 | assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line)); 136 | assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd)); 137 | 138 | tmp = (uint32_t)EXTI_BASE; 139 | 140 | if (EXTI_InitStruct->EXTI_LineCmd != DISABLE) 141 | { 142 | /* Clear EXTI line configuration */ 143 | EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line; 144 | EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line; 145 | 146 | tmp += EXTI_InitStruct->EXTI_Mode; 147 | 148 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 149 | 150 | /* Clear Rising Falling edge configuration */ 151 | EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line; 152 | EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line; 153 | 154 | /* Select the trigger for the selected interrupts */ 155 | if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) 156 | { 157 | /* Rising Falling edge */ 158 | EXTI->RTSR |= EXTI_InitStruct->EXTI_Line; 159 | EXTI->FTSR |= EXTI_InitStruct->EXTI_Line; 160 | } 161 | else 162 | { 163 | tmp = (uint32_t)EXTI_BASE; 164 | tmp += EXTI_InitStruct->EXTI_Trigger; 165 | 166 | *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line; 167 | } 168 | } 169 | else 170 | { 171 | tmp += EXTI_InitStruct->EXTI_Mode; 172 | 173 | /* Disable the selected external lines */ 174 | *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line; 175 | } 176 | } 177 | 178 | /** 179 | * @brief Fills each EXTI_InitStruct member with its reset value. 180 | * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will 181 | * be initialized. 182 | * @retval None 183 | */ 184 | void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct) 185 | { 186 | EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; 187 | EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; 188 | EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; 189 | EXTI_InitStruct->EXTI_LineCmd = DISABLE; 190 | } 191 | 192 | /** 193 | * @brief Generates a Software interrupt on selected EXTI line. 194 | * @param EXTI_Line: specifies the EXTI line on which the software interrupt 195 | * will be generated. 196 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 197 | * @retval None 198 | */ 199 | void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) 200 | { 201 | /* Check the parameters */ 202 | assert_param(IS_EXTI_LINE(EXTI_Line)); 203 | 204 | EXTI->SWIER |= EXTI_Line; 205 | } 206 | 207 | /** 208 | * @} 209 | */ 210 | 211 | /** @defgroup EXTI_Group2 Interrupts and flags management functions 212 | * @brief Interrupts and flags management functions 213 | * 214 | @verbatim 215 | ============================================================================== 216 | ##### Interrupts and flags management functions ##### 217 | ============================================================================== 218 | 219 | @endverbatim 220 | * @{ 221 | */ 222 | 223 | /** 224 | * @brief Checks whether the specified EXTI line flag is set or not. 225 | * @param EXTI_Line: specifies the EXTI line flag to check. 226 | * This parameter can be EXTI_Linex where x can be (0..27). 227 | * @retval The new state of EXTI_Line (SET or RESET). 228 | */ 229 | FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) 230 | { 231 | FlagStatus bitstatus = RESET; 232 | /* Check the parameters */ 233 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 234 | 235 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 236 | { 237 | bitstatus = SET; 238 | } 239 | else 240 | { 241 | bitstatus = RESET; 242 | } 243 | return bitstatus; 244 | } 245 | 246 | /** 247 | * @brief Clears the EXTI's line pending flags. 248 | * @param EXTI_Line: specifies the EXTI lines flags to clear. 249 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 250 | * @retval None 251 | */ 252 | void EXTI_ClearFlag(uint32_t EXTI_Line) 253 | { 254 | /* Check the parameters */ 255 | assert_param(IS_EXTI_LINE(EXTI_Line)); 256 | 257 | EXTI->PR = EXTI_Line; 258 | } 259 | 260 | /** 261 | * @brief Checks whether the specified EXTI line is asserted or not. 262 | * @param EXTI_Line: specifies the EXTI line to check. 263 | * This parameter can be EXTI_Linex where x can be (0..27). 264 | * @retval The new state of EXTI_Line (SET or RESET). 265 | */ 266 | ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) 267 | { 268 | ITStatus bitstatus = RESET; 269 | 270 | /* Check the parameters */ 271 | assert_param(IS_GET_EXTI_LINE(EXTI_Line)); 272 | 273 | if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET) 274 | { 275 | bitstatus = SET; 276 | } 277 | else 278 | { 279 | bitstatus = RESET; 280 | } 281 | return bitstatus; 282 | } 283 | 284 | /** 285 | * @brief Clears the EXTI's line pending bits. 286 | * @param EXTI_Line: specifies the EXTI lines to clear. 287 | * This parameter can be any combination of EXTI_Linex where x can be (0..27). 288 | * @retval None 289 | */ 290 | void EXTI_ClearITPendingBit(uint32_t EXTI_Line) 291 | { 292 | /* Check the parameters */ 293 | assert_param(IS_EXTI_LINE(EXTI_Line)); 294 | 295 | EXTI->PR = EXTI_Line; 296 | } 297 | 298 | /** 299 | * @} 300 | */ 301 | 302 | /** 303 | * @} 304 | */ 305 | 306 | /** 307 | * @} 308 | */ 309 | 310 | /** 311 | * @} 312 | */ 313 | 314 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 315 | -------------------------------------------------------------------------------- /StdPeriph_Driver/src/stm32f0xx_iwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_iwdg.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the Independent watchdog (IWDG) peripheral: 9 | * + Prescaler and Counter configuration 10 | * + IWDG activation 11 | * + Flag management 12 | * 13 | * @verbatim 14 | * 15 | ============================================================================== 16 | ##### IWDG features ##### 17 | ============================================================================== 18 | [..] The IWDG can be started by either software or hardware (configurable 19 | through option byte). 20 | 21 | [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and 22 | thus stays active even if the main clock fails. 23 | Once the IWDG is started, the LSI is forced ON and cannot be disabled 24 | (LSI cannot be disabled too), and the counter starts counting down from 25 | the reset value of 0xFFF. When it reaches the end of count value (0x000) 26 | a system reset is generated. 27 | The IWDG counter should be reloaded at regular intervals to prevent 28 | an MCU reset. 29 | 30 | [..] The IWDG is implemented in the VDD voltage domain that is still functional 31 | in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY). 32 | 33 | [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG 34 | reset occurs. 35 | 36 | [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s 37 | The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx 38 | devices provide the capability to measure the LSI frequency (LSI clock 39 | should be seleted as RTC clock which is internally connected to TIM10 CH1 40 | input capture). The measured value can be used to have an IWDG timeout with 41 | an acceptable accuracy. 42 | For more information, please refer to the STM32F0xx Reference manual. 43 | 44 | ##### How to use this driver ##### 45 | ============================================================================== 46 | [..] This driver allows to use IWDG peripheral with either window option enabled 47 | or disabled. To do so follow one of the two procedures below. 48 | (#) Window option is enabled: 49 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used 50 | in software mode (no need to enable the LSI, it will be enabled 51 | by hardware). 52 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using 53 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. 54 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. 55 | (++) Configure the IWDG counter value using IWDG_SetReload() function. 56 | This value will be loaded in the IWDG counter each time the counter 57 | is reloaded, then the IWDG will start counting down from this value. 58 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. 59 | (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function. 60 | 61 | (#) Window option is disabled: 62 | (++) Enable write access to IWDG_PR and IWDG_RLR registers using 63 | IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function. 64 | (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function. 65 | (++) Configure the IWDG counter value using IWDG_SetReload() function. 66 | This value will be loaded in the IWDG counter each time the counter 67 | is reloaded, then the IWDG will start counting down from this value. 68 | (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function. 69 | (++) reload the IWDG counter at regular intervals during normal operation 70 | to prevent an MCU reset, using IWDG_ReloadCounter() function. 71 | (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used 72 | in software mode (no need to enable the LSI, it will be enabled 73 | by hardware). 74 | 75 | @endverbatim 76 | * 77 | ****************************************************************************** 78 | * @attention 79 | * 80 | *

© COPYRIGHT 2014 STMicroelectronics

81 | * 82 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 83 | * You may not use this file except in compliance with the License. 84 | * You may obtain a copy of the License at: 85 | * 86 | * http://www.st.com/software_license_agreement_liberty_v2 87 | * 88 | * Unless required by applicable law or agreed to in writing, software 89 | * distributed under the License is distributed on an "AS IS" BASIS, 90 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 91 | * See the License for the specific language governing permissions and 92 | * limitations under the License. 93 | * 94 | ****************************************************************************** 95 | */ 96 | 97 | /* Includes ------------------------------------------------------------------*/ 98 | #include "stm32f0xx_iwdg.h" 99 | 100 | /** @addtogroup STM32F0xx_StdPeriph_Driver 101 | * @{ 102 | */ 103 | 104 | /** @defgroup IWDG 105 | * @brief IWDG driver modules 106 | * @{ 107 | */ 108 | 109 | /* Private typedef -----------------------------------------------------------*/ 110 | /* Private define ------------------------------------------------------------*/ 111 | /* ---------------------- IWDG registers bit mask ----------------------------*/ 112 | /* KR register bit mask */ 113 | #define KR_KEY_RELOAD ((uint16_t)0xAAAA) 114 | #define KR_KEY_ENABLE ((uint16_t)0xCCCC) 115 | 116 | /* Private macro -------------------------------------------------------------*/ 117 | /* Private variables ---------------------------------------------------------*/ 118 | /* Private function prototypes -----------------------------------------------*/ 119 | /* Private functions ---------------------------------------------------------*/ 120 | 121 | /** @defgroup IWDG_Private_Functions 122 | * @{ 123 | */ 124 | 125 | /** @defgroup IWDG_Group1 Prescaler and Counter configuration functions 126 | * @brief Prescaler and Counter configuration functions 127 | * 128 | @verbatim 129 | ============================================================================== 130 | ##### Prescaler and Counter configuration functions ##### 131 | ============================================================================== 132 | 133 | @endverbatim 134 | * @{ 135 | */ 136 | 137 | /** 138 | * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers. 139 | * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers. 140 | * This parameter can be one of the following values: 141 | * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers 142 | * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers 143 | * @retval None 144 | */ 145 | void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) 146 | { 147 | /* Check the parameters */ 148 | assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess)); 149 | IWDG->KR = IWDG_WriteAccess; 150 | } 151 | 152 | /** 153 | * @brief Sets IWDG Prescaler value. 154 | * @param IWDG_Prescaler: specifies the IWDG Prescaler value. 155 | * This parameter can be one of the following values: 156 | * @arg IWDG_Prescaler_4: IWDG prescaler set to 4 157 | * @arg IWDG_Prescaler_8: IWDG prescaler set to 8 158 | * @arg IWDG_Prescaler_16: IWDG prescaler set to 16 159 | * @arg IWDG_Prescaler_32: IWDG prescaler set to 32 160 | * @arg IWDG_Prescaler_64: IWDG prescaler set to 64 161 | * @arg IWDG_Prescaler_128: IWDG prescaler set to 128 162 | * @arg IWDG_Prescaler_256: IWDG prescaler set to 256 163 | * @retval None 164 | */ 165 | void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) 166 | { 167 | /* Check the parameters */ 168 | assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler)); 169 | IWDG->PR = IWDG_Prescaler; 170 | } 171 | 172 | /** 173 | * @brief Sets IWDG Reload value. 174 | * @param Reload: specifies the IWDG Reload value. 175 | * This parameter must be a number between 0 and 0x0FFF. 176 | * @retval None 177 | */ 178 | void IWDG_SetReload(uint16_t Reload) 179 | { 180 | /* Check the parameters */ 181 | assert_param(IS_IWDG_RELOAD(Reload)); 182 | IWDG->RLR = Reload; 183 | } 184 | 185 | /** 186 | * @brief Reloads IWDG counter with value defined in the reload register 187 | * (write access to IWDG_PR and IWDG_RLR registers disabled). 188 | * @param None 189 | * @retval None 190 | */ 191 | void IWDG_ReloadCounter(void) 192 | { 193 | IWDG->KR = KR_KEY_RELOAD; 194 | } 195 | 196 | 197 | /** 198 | * @brief Sets the IWDG window value. 199 | * @param WindowValue: specifies the window value to be compared to the downcounter. 200 | * @retval None 201 | */ 202 | void IWDG_SetWindowValue(uint16_t WindowValue) 203 | { 204 | /* Check the parameters */ 205 | assert_param(IS_IWDG_WINDOW_VALUE(WindowValue)); 206 | IWDG->WINR = WindowValue; 207 | } 208 | 209 | /** 210 | * @} 211 | */ 212 | 213 | /** @defgroup IWDG_Group2 IWDG activation function 214 | * @brief IWDG activation function 215 | * 216 | @verbatim 217 | ============================================================================== 218 | ##### IWDG activation function ##### 219 | ============================================================================== 220 | 221 | @endverbatim 222 | * @{ 223 | */ 224 | 225 | /** 226 | * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled). 227 | * @param None 228 | * @retval None 229 | */ 230 | void IWDG_Enable(void) 231 | { 232 | IWDG->KR = KR_KEY_ENABLE; 233 | } 234 | 235 | /** 236 | * @} 237 | */ 238 | 239 | /** @defgroup IWDG_Group3 Flag management function 240 | * @brief Flag management function 241 | * 242 | @verbatim 243 | =============================================================================== 244 | ##### Flag management function ##### 245 | =============================================================================== 246 | 247 | @endverbatim 248 | * @{ 249 | */ 250 | 251 | /** 252 | * @brief Checks whether the specified IWDG flag is set or not. 253 | * @param IWDG_FLAG: specifies the flag to check. 254 | * This parameter can be one of the following values: 255 | * @arg IWDG_FLAG_PVU: Prescaler Value Update on going 256 | * @arg IWDG_FLAG_RVU: Reload Value Update on going 257 | * @arg IWDG_FLAG_WVU: Counter Window Value Update on going 258 | * @retval The new state of IWDG_FLAG (SET or RESET). 259 | */ 260 | FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) 261 | { 262 | FlagStatus bitstatus = RESET; 263 | /* Check the parameters */ 264 | assert_param(IS_IWDG_FLAG(IWDG_FLAG)); 265 | if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET) 266 | { 267 | bitstatus = SET; 268 | } 269 | else 270 | { 271 | bitstatus = RESET; 272 | } 273 | /* Return the flag status */ 274 | return bitstatus; 275 | } 276 | 277 | /** 278 | * @} 279 | */ 280 | 281 | /** 282 | * @} 283 | */ 284 | 285 | /** 286 | * @} 287 | */ 288 | 289 | /** 290 | * @} 291 | */ 292 | 293 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 294 | -------------------------------------------------------------------------------- /StdPeriph_Driver/src/stm32f0xx_misc.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_misc.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides all the miscellaneous firmware functions (add-on 8 | * to CMSIS functions). 9 | ****************************************************************************** 10 | * @attention 11 | * 12 | *

© COPYRIGHT 2014 STMicroelectronics

13 | * 14 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 15 | * You may not use this file except in compliance with the License. 16 | * You may obtain a copy of the License at: 17 | * 18 | * http://www.st.com/software_license_agreement_liberty_v2 19 | * 20 | * Unless required by applicable law or agreed to in writing, software 21 | * distributed under the License is distributed on an "AS IS" BASIS, 22 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 | * See the License for the specific language governing permissions and 24 | * limitations under the License. 25 | * 26 | ****************************************************************************** 27 | */ 28 | 29 | /* Includes ------------------------------------------------------------------*/ 30 | #include "stm32f0xx_misc.h" 31 | 32 | /** @addtogroup STM32F0xx_StdPeriph_Driver 33 | * @{ 34 | */ 35 | 36 | /** @defgroup MISC 37 | * @brief MISC driver modules 38 | * @{ 39 | */ 40 | 41 | /* Private typedef -----------------------------------------------------------*/ 42 | /* Private define ------------------------------------------------------------*/ 43 | /* Private macro -------------------------------------------------------------*/ 44 | /* Private variables ---------------------------------------------------------*/ 45 | /* Private function prototypes -----------------------------------------------*/ 46 | /* Private functions ---------------------------------------------------------*/ 47 | 48 | /** @defgroup MISC_Private_Functions 49 | * @{ 50 | */ 51 | /** 52 | * 53 | @verbatim 54 | ******************************************************************************* 55 | ##### Interrupts configuration functions ##### 56 | ******************************************************************************* 57 | [..] This section provide functions allowing to configure the NVIC interrupts 58 | (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions. 59 | (#) Enable and Configure the priority of the selected IRQ Channels. 60 | The priority can be 0..3. 61 | 62 | -@- Lower priority values gives higher priority. 63 | -@- Priority Order: 64 | (#@) Lowest priority. 65 | (#@) Lowest hardware priority (IRQn position). 66 | 67 | @endverbatim 68 | */ 69 | 70 | /** 71 | * @brief Initializes the NVIC peripheral according to the specified 72 | * parameters in the NVIC_InitStruct. 73 | * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains 74 | * the configuration information for the specified NVIC peripheral. 75 | * @retval None 76 | */ 77 | void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct) 78 | { 79 | uint32_t tmppriority = 0x00; 80 | 81 | /* Check the parameters */ 82 | assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd)); 83 | assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority)); 84 | 85 | if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) 86 | { 87 | /* Compute the Corresponding IRQ Priority --------------------------------*/ 88 | tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02]; 89 | tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8))); 90 | tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)); 91 | 92 | NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority; 93 | 94 | /* Enable the Selected IRQ Channels --------------------------------------*/ 95 | NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 96 | } 97 | else 98 | { 99 | /* Disable the Selected IRQ Channels -------------------------------------*/ 100 | NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F); 101 | } 102 | } 103 | 104 | /** 105 | * @brief Selects the condition for the system to enter low power mode. 106 | * @param LowPowerMode: Specifies the new mode for the system to enter low power mode. 107 | * This parameter can be one of the following values: 108 | * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend. 109 | * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request. 110 | * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit. 111 | * @param NewState: new state of LP condition. 112 | * This parameter can be: ENABLE or DISABLE. 113 | * @retval None 114 | */ 115 | void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState) 116 | { 117 | /* Check the parameters */ 118 | assert_param(IS_NVIC_LP(LowPowerMode)); 119 | 120 | assert_param(IS_FUNCTIONAL_STATE(NewState)); 121 | 122 | if (NewState != DISABLE) 123 | { 124 | SCB->SCR |= LowPowerMode; 125 | } 126 | else 127 | { 128 | SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode); 129 | } 130 | } 131 | 132 | /** 133 | * @brief Configures the SysTick clock source. 134 | * @param SysTick_CLKSource: specifies the SysTick clock source. 135 | * This parameter can be one of the following values: 136 | * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source. 137 | * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source. 138 | * @retval None 139 | */ 140 | void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource) 141 | { 142 | /* Check the parameters */ 143 | assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource)); 144 | 145 | if (SysTick_CLKSource == SysTick_CLKSource_HCLK) 146 | { 147 | SysTick->CTRL |= SysTick_CLKSource_HCLK; 148 | } 149 | else 150 | { 151 | SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8; 152 | } 153 | } 154 | 155 | /** 156 | * @} 157 | */ 158 | 159 | /** 160 | * @} 161 | */ 162 | 163 | /** 164 | * @} 165 | */ 166 | 167 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 168 | -------------------------------------------------------------------------------- /StdPeriph_Driver/src/stm32f0xx_wwdg.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file stm32f0xx_wwdg.c 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file provides firmware functions to manage the following 8 | * functionalities of the Window watchdog (WWDG) peripheral: 9 | * + Prescaler, Refresh window and Counter configuration 10 | * + WWDG activation 11 | * + Interrupts and flags management 12 | * 13 | * @verbatim 14 | * 15 | ============================================================================== 16 | ##### WWDG features ##### 17 | ============================================================================== 18 | [..] Once enabled the WWDG generates a system reset on expiry of a programmed 19 | time period, unless the program refreshes the counter (downcounter) 20 | before to reach 0x3F value (i.e. a reset is generated when the counter 21 | value rolls over from 0x40 to 0x3F). 22 | [..] An MCU reset is also generated if the counter value is refreshed 23 | before the counter has reached the refresh window value. This 24 | implies that the counter must be refreshed in a limited window. 25 | 26 | [..] Once enabled the WWDG cannot be disabled except by a system reset. 27 | 28 | [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG 29 | reset occurs. 30 | 31 | [..] The WWDG counter input clock is derived from the APB clock divided 32 | by a programmable prescaler. 33 | 34 | [..] WWDG counter clock = PCLK1 / Prescaler. 35 | [..] WWDG timeout = (WWDG counter clock) * (counter value). 36 | 37 | [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms. 38 | 39 | ##### How to use this driver ##### 40 | ============================================================================== 41 | [..] 42 | (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) 43 | function. 44 | 45 | (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function. 46 | 47 | (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function. 48 | 49 | (#) Set the WWDG counter value and start it using WWDG_Enable() function. 50 | When the WWDG is enabled the counter value should be configured to 51 | a value greater than 0x40 to prevent generating an immediate reset. 52 | 53 | (#) Optionally you can enable the Early wakeup interrupt which is 54 | generated when the counter reach 0x40. 55 | Once enabled this interrupt cannot be disabled except by a system reset. 56 | 57 | (#) Then the application program must refresh the WWDG counter at regular 58 | intervals during normal operation to prevent an MCU reset, using 59 | WWDG_SetCounter() function. This operation must occur only when 60 | the counter value is lower than the refresh window value, 61 | programmed using WWDG_SetWindowValue(). 62 | 63 | * @endverbatim 64 | * 65 | ****************************************************************************** 66 | * @attention 67 | * 68 | *

© COPYRIGHT 2014 STMicroelectronics

69 | * 70 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 71 | * You may not use this file except in compliance with the License. 72 | * You may obtain a copy of the License at: 73 | * 74 | * http://www.st.com/software_license_agreement_liberty_v2 75 | * 76 | * Unless required by applicable law or agreed to in writing, software 77 | * distributed under the License is distributed on an "AS IS" BASIS, 78 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 79 | * See the License for the specific language governing permissions and 80 | * limitations under the License. 81 | * 82 | ****************************************************************************** 83 | */ 84 | 85 | /* Includes ------------------------------------------------------------------*/ 86 | #include "stm32f0xx_wwdg.h" 87 | #include "stm32f0xx_rcc.h" 88 | 89 | /** @addtogroup STM32F0xx_StdPeriph_Driver 90 | * @{ 91 | */ 92 | 93 | /** @defgroup WWDG 94 | * @brief WWDG driver modules 95 | * @{ 96 | */ 97 | 98 | /* Private typedef -----------------------------------------------------------*/ 99 | /* Private define ------------------------------------------------------------*/ 100 | /* --------------------- WWDG registers bit mask ---------------------------- */ 101 | /* CFR register bit mask */ 102 | #define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F) 103 | #define CFR_W_MASK ((uint32_t)0xFFFFFF80) 104 | #define BIT_MASK ((uint8_t)0x7F) 105 | 106 | /* Private macro -------------------------------------------------------------*/ 107 | /* Private variables ---------------------------------------------------------*/ 108 | /* Private function prototypes -----------------------------------------------*/ 109 | /* Private functions ---------------------------------------------------------*/ 110 | 111 | /** @defgroup WWDG_Private_Functions 112 | * @{ 113 | */ 114 | 115 | /** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions 116 | * @brief Prescaler, Refresh window and Counter configuration functions 117 | * 118 | @verbatim 119 | ============================================================================== 120 | ##### Prescaler, Refresh window and Counter configuration functions ##### 121 | ============================================================================== 122 | 123 | @endverbatim 124 | * @{ 125 | */ 126 | 127 | /** 128 | * @brief Deinitializes the WWDG peripheral registers to their default reset values. 129 | * @param None 130 | * @retval None 131 | */ 132 | void WWDG_DeInit(void) 133 | { 134 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); 135 | RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); 136 | } 137 | 138 | /** 139 | * @brief Sets the WWDG Prescaler. 140 | * @param WWDG_Prescaler: specifies the WWDG Prescaler. 141 | * This parameter can be one of the following values: 142 | * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1 143 | * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2 144 | * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4 145 | * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8 146 | * @retval None 147 | */ 148 | void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) 149 | { 150 | uint32_t tmpreg = 0; 151 | /* Check the parameters */ 152 | assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler)); 153 | /* Clear WDGTB[1:0] bits */ 154 | tmpreg = WWDG->CFR & CFR_WDGTB_MASK; 155 | /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */ 156 | tmpreg |= WWDG_Prescaler; 157 | /* Store the new value */ 158 | WWDG->CFR = tmpreg; 159 | } 160 | 161 | /** 162 | * @brief Sets the WWDG window value. 163 | * @param WindowValue: specifies the window value to be compared to the downcounter. 164 | * This parameter value must be lower than 0x80. 165 | * @retval None 166 | */ 167 | void WWDG_SetWindowValue(uint8_t WindowValue) 168 | { 169 | __IO uint32_t tmpreg = 0; 170 | 171 | /* Check the parameters */ 172 | assert_param(IS_WWDG_WINDOW_VALUE(WindowValue)); 173 | /* Clear W[6:0] bits */ 174 | 175 | tmpreg = WWDG->CFR & CFR_W_MASK; 176 | 177 | /* Set W[6:0] bits according to WindowValue value */ 178 | tmpreg |= WindowValue & (uint32_t) BIT_MASK; 179 | 180 | /* Store the new value */ 181 | WWDG->CFR = tmpreg; 182 | } 183 | 184 | /** 185 | * @brief Enables the WWDG Early Wakeup interrupt(EWI). 186 | * @note Once enabled this interrupt cannot be disabled except by a system reset. 187 | * @param None 188 | * @retval None 189 | */ 190 | void WWDG_EnableIT(void) 191 | { 192 | WWDG->CFR |= WWDG_CFR_EWI; 193 | } 194 | 195 | /** 196 | * @brief Sets the WWDG counter value. 197 | * @param Counter: specifies the watchdog counter value. 198 | * This parameter must be a number between 0x40 and 0x7F (to prevent 199 | * generating an immediate reset). 200 | * @retval None 201 | */ 202 | void WWDG_SetCounter(uint8_t Counter) 203 | { 204 | /* Check the parameters */ 205 | assert_param(IS_WWDG_COUNTER(Counter)); 206 | /* Write to T[6:0] bits to configure the counter value, no need to do 207 | a read-modify-write; writing a 0 to WDGA bit does nothing */ 208 | WWDG->CR = Counter & BIT_MASK; 209 | } 210 | 211 | /** 212 | * @} 213 | */ 214 | 215 | /** @defgroup WWDG_Group2 WWDG activation functions 216 | * @brief WWDG activation functions 217 | * 218 | @verbatim 219 | ============================================================================== 220 | ##### WWDG activation function ##### 221 | ============================================================================== 222 | 223 | @endverbatim 224 | * @{ 225 | */ 226 | 227 | /** 228 | * @brief Enables WWDG and load the counter value. 229 | * @param Counter: specifies the watchdog counter value. 230 | * This parameter must be a number between 0x40 and 0x7F (to prevent 231 | * generating an immediate reset). 232 | * @retval None 233 | */ 234 | void WWDG_Enable(uint8_t Counter) 235 | { 236 | /* Check the parameters */ 237 | assert_param(IS_WWDG_COUNTER(Counter)); 238 | WWDG->CR = WWDG_CR_WDGA | Counter; 239 | } 240 | 241 | /** 242 | * @} 243 | */ 244 | 245 | /** @defgroup WWDG_Group3 Interrupts and flags management functions 246 | * @brief Interrupts and flags management functions 247 | * 248 | @verbatim 249 | ============================================================================== 250 | ##### Interrupts and flags management functions ##### 251 | ============================================================================== 252 | 253 | @endverbatim 254 | * @{ 255 | */ 256 | 257 | /** 258 | * @brief Checks whether the Early Wakeup interrupt flag is set or not. 259 | * @param None 260 | * @retval The new state of the Early Wakeup interrupt flag (SET or RESET). 261 | */ 262 | FlagStatus WWDG_GetFlagStatus(void) 263 | { 264 | FlagStatus bitstatus = RESET; 265 | 266 | if ((WWDG->SR) != (uint32_t)RESET) 267 | { 268 | bitstatus = SET; 269 | } 270 | else 271 | { 272 | bitstatus = RESET; 273 | } 274 | return bitstatus; 275 | } 276 | 277 | /** 278 | * @brief Clears Early Wakeup interrupt flag. 279 | * @param None 280 | * @retval None 281 | */ 282 | void WWDG_ClearFlag(void) 283 | { 284 | WWDG->SR = (uint32_t)RESET; 285 | } 286 | 287 | /** 288 | * @} 289 | */ 290 | 291 | /** 292 | * @} 293 | */ 294 | 295 | /** 296 | * @} 297 | */ 298 | 299 | /** 300 | * @} 301 | */ 302 | 303 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 304 | -------------------------------------------------------------------------------- /dist/sensorsRaw.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/simap/pixelblaze_sensor_board/15b3d271e0d6535965a68b15f057bac58a3154d7/dist/sensorsRaw.bin -------------------------------------------------------------------------------- /hardware/neoimage_sensors small.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/simap/pixelblaze_sensor_board/15b3d271e0d6535965a68b15f057bac58a3154d7/hardware/neoimage_sensors small.pdf -------------------------------------------------------------------------------- /inc/main.h: -------------------------------------------------------------------------------- 1 | #ifndef _MAIN_H_ 2 | #define _MAIN_H_ 3 | 4 | #include "stm32f0xx.h" 5 | #include "stdbool.h" 6 | #include "string.h" 7 | #include "stdlib.h" 8 | 9 | #define HIGH_N 512 10 | #define HIGH_NLOG2 9 11 | 12 | #define LOW_N 32 13 | #define LOW_NLOG2 5 14 | 15 | #define LIS3DH_ADDR (0x18<<1) 16 | 17 | 18 | extern const short Sinewave[]; 19 | extern int fix_fft(short fr[], short fi[], short m, short inverse); 20 | extern int32_t fix16_sqrt(int32_t inValue); 21 | 22 | void initRcc(); 23 | void initTim1(); 24 | void initAdc(); 25 | void initGpio(); 26 | void initUart(); 27 | void initDma(); 28 | void initI2C(); 29 | 30 | void writeToUsart(uint8_t * outBuffer, uint32_t len); 31 | void i2cWriteReg(uint8_t addr, uint8_t reg, uint8_t value); 32 | void i2cReadReg(uint8_t addr, uint8_t reg, uint8_t * value, uint8_t len); 33 | void initAccelerometer(); 34 | void startAccelerometerPoll(); 35 | 36 | void processSensorData(int16_t * audioBuffer, int16_t * audio400HzBuffer, volatile uint16_t adcBuffer[7], volatile int16_t accelerometer[3]); 37 | 38 | 39 | #endif 40 | -------------------------------------------------------------------------------- /inc/stm32f0xx_it.h: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_it.h 4 | * @author MCD Application Team 5 | * @version V1.5.0 6 | * @date 05-December-2014 7 | * @brief This file contains the headers of the interrupt handlers. 8 | ****************************************************************************** 9 | * @attention 10 | * 11 | *

© COPYRIGHT 2014 STMicroelectronics

12 | * 13 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 14 | * You may not use this file except in compliance with the License. 15 | * You may obtain a copy of the License at: 16 | * 17 | * http://www.st.com/software_license_agreement_liberty_v2 18 | * 19 | * Unless required by applicable law or agreed to in writing, software 20 | * distributed under the License is distributed on an "AS IS" BASIS, 21 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 22 | * See the License for the specific language governing permissions and 23 | * limitations under the License. 24 | * 25 | ****************************************************************************** 26 | */ 27 | 28 | /* Define to prevent recursive inclusion -------------------------------------*/ 29 | #ifndef __STM32F0XX_IT_H 30 | #define __STM32F0XX_IT_H 31 | 32 | #ifdef __cplusplus 33 | extern "C" { 34 | #endif 35 | 36 | /* Includes ------------------------------------------------------------------*/ 37 | #include "main.h" 38 | 39 | /* Exported types ------------------------------------------------------------*/ 40 | /* Exported constants --------------------------------------------------------*/ 41 | /* Exported macro ------------------------------------------------------------*/ 42 | /* Exported functions ------------------------------------------------------- */ 43 | 44 | void NMI_Handler(void); 45 | void HardFault_Handler(void); 46 | void SVC_Handler(void); 47 | void PendSV_Handler(void); 48 | void SysTick_Handler(void); 49 | 50 | /*void PPP_IRQHandler(void);*/ 51 | 52 | #ifdef __cplusplus 53 | } 54 | #endif 55 | 56 | #endif /* __STM32F0XX_IT_H */ 57 | 58 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 59 | -------------------------------------------------------------------------------- /sensorsRaw Run.cfg: -------------------------------------------------------------------------------- 1 | # This is an genericBoard board with a single STM32F030F4Px chip 2 | # 3 | # Generated by System Workbench for STM32 4 | # Take care that such file, as generated, may be overridden without any early notice. Please have a look to debug launch configuration setup(s) 5 | 6 | source [find interface/stlink.cfg] 7 | 8 | set WORKAREASIZE 0x1000 9 | 10 | transport select "hla_swd" 11 | 12 | set CHIPNAME STM32F030F4Px 13 | 14 | # Enable debug when in low power modes 15 | set ENABLE_LOW_POWER 1 16 | 17 | # Stop Watchdog counters when halt 18 | set STOP_WATCHDOG 1 19 | 20 | # STlink Debug clock frequency 21 | set CLOCK_FREQ 4000 22 | 23 | # use hardware reset, connect under reset 24 | # connect_assert_srst needed if low power mode application running (WFI...) 25 | reset_config srst_only srst_nogate connect_assert_srst 26 | set CONNECT_UNDER_RESET 1 27 | 28 | source [find target/stm32f0x.cfg] 29 | -------------------------------------------------------------------------------- /src/fix_fft.c: -------------------------------------------------------------------------------- 1 | /* fix_fft.c - Fixed-point in-place Fast Fourier Transform */ 2 | /* 3 | All data are fixed-point short integers, in which -32768 4 | to +32768 represent -1.0 to +1.0 respectively. Integer 5 | arithmetic is used for speed, instead of the more natural 6 | floating-point. 7 | 8 | For the forward FFT (time -> freq), fixed scaling is 9 | performed to prevent arithmetic overflow, and to map a 0dB 10 | sine/cosine wave (i.e. amplitude = 32767) to two -6dB freq 11 | coefficients. The return value is always 0. 12 | 13 | For the inverse FFT (freq -> time), fixed scaling cannot be 14 | done, as two 0dB coefficients would sum to a peak amplitude 15 | of 64K, overflowing the 32k range of the fixed-point integers. 16 | Thus, the fix_fft() routine performs variable scaling, and 17 | returns a value which is the number of bits LEFT by which 18 | the output must be shifted to get the actual amplitude 19 | (i.e. if fix_fft() returns 3, each value of fr[] and fi[] 20 | must be multiplied by 8 (2**3) for proper scaling. 21 | Clearly, this cannot be done within fixed-point short 22 | integers. In practice, if the result is to be used as a 23 | filter, the scale_shift can usually be ignored, as the 24 | result will be approximately correctly normalized as is. 25 | 26 | Written by: Tom Roberts 11/8/89 27 | Made portable: Malcolm Slaney 12/15/94 malcolm@interval.com 28 | Enhanced: Dimitrios P. Bouras 14 Jun 2006 dbouras@ieee.org 29 | */ 30 | 31 | #define N_WAVE 1024 /* full length of Sinewave[] */ 32 | #define LOG2_N_WAVE 10 /* log2(N_WAVE) */ 33 | 34 | /* 35 | Henceforth "short" implies 16-bit word. If this is not 36 | the case in your architecture, please replace "short" 37 | with a type definition which *is* a 16-bit word. 38 | */ 39 | 40 | /* 41 | Since we only use 3/4 of N_WAVE, we define only 42 | this many samples, in order to conserve data space. 43 | */ 44 | const short Sinewave[N_WAVE-N_WAVE/4] = { 45 | 0, 201, 402, 603, 804, 1005, 1206, 1406, 46 | 1607, 1808, 2009, 2209, 2410, 2610, 2811, 3011, 47 | 3211, 3411, 3611, 3811, 4011, 4210, 4409, 4608, 48 | 4807, 5006, 5205, 5403, 5601, 5799, 5997, 6195, 49 | 6392, 6589, 6786, 6982, 7179, 7375, 7571, 7766, 50 | 7961, 8156, 8351, 8545, 8739, 8932, 9126, 9319, 51 | 9511, 9703, 9895, 10087, 10278, 10469, 10659, 10849, 52 | 11038, 11227, 11416, 11604, 11792, 11980, 12166, 12353, 53 | 12539, 12724, 12909, 13094, 13278, 13462, 13645, 13827, 54 | 14009, 14191, 14372, 14552, 14732, 14911, 15090, 15268, 55 | 15446, 15623, 15799, 15975, 16150, 16325, 16499, 16672, 56 | 16845, 17017, 17189, 17360, 17530, 17699, 17868, 18036, 57 | 18204, 18371, 18537, 18702, 18867, 19031, 19194, 19357, 58 | 19519, 19680, 19840, 20000, 20159, 20317, 20474, 20631, 59 | 20787, 20942, 21096, 21249, 21402, 21554, 21705, 21855, 60 | 22004, 22153, 22301, 22448, 22594, 22739, 22883, 23027, 61 | 23169, 23311, 23452, 23592, 23731, 23869, 24006, 24143, 62 | 24278, 24413, 24546, 24679, 24811, 24942, 25072, 25201, 63 | 25329, 25456, 25582, 25707, 25831, 25954, 26077, 26198, 64 | 26318, 26437, 26556, 26673, 26789, 26905, 27019, 27132, 65 | 27244, 27355, 27466, 27575, 27683, 27790, 27896, 28001, 66 | 28105, 28208, 28309, 28410, 28510, 28608, 28706, 28802, 67 | 28897, 28992, 29085, 29177, 29268, 29358, 29446, 29534, 68 | 29621, 29706, 29790, 29873, 29955, 30036, 30116, 30195, 69 | 30272, 30349, 30424, 30498, 30571, 30643, 30713, 30783, 70 | 30851, 30918, 30984, 31049, 31113, 31175, 31236, 31297, 71 | 31356, 31413, 31470, 31525, 31580, 31633, 31684, 31735, 72 | 31785, 31833, 31880, 31926, 31970, 32014, 32056, 32097, 73 | 32137, 32176, 32213, 32249, 32284, 32318, 32350, 32382, 74 | 32412, 32441, 32468, 32495, 32520, 32544, 32567, 32588, 75 | 32609, 32628, 32646, 32662, 32678, 32692, 32705, 32717, 76 | 32727, 32736, 32744, 32751, 32757, 32761, 32764, 32766, 77 | 32767, 32766, 32764, 32761, 32757, 32751, 32744, 32736, 78 | 32727, 32717, 32705, 32692, 32678, 32662, 32646, 32628, 79 | 32609, 32588, 32567, 32544, 32520, 32495, 32468, 32441, 80 | 32412, 32382, 32350, 32318, 32284, 32249, 32213, 32176, 81 | 32137, 32097, 32056, 32014, 31970, 31926, 31880, 31833, 82 | 31785, 31735, 31684, 31633, 31580, 31525, 31470, 31413, 83 | 31356, 31297, 31236, 31175, 31113, 31049, 30984, 30918, 84 | 30851, 30783, 30713, 30643, 30571, 30498, 30424, 30349, 85 | 30272, 30195, 30116, 30036, 29955, 29873, 29790, 29706, 86 | 29621, 29534, 29446, 29358, 29268, 29177, 29085, 28992, 87 | 28897, 28802, 28706, 28608, 28510, 28410, 28309, 28208, 88 | 28105, 28001, 27896, 27790, 27683, 27575, 27466, 27355, 89 | 27244, 27132, 27019, 26905, 26789, 26673, 26556, 26437, 90 | 26318, 26198, 26077, 25954, 25831, 25707, 25582, 25456, 91 | 25329, 25201, 25072, 24942, 24811, 24679, 24546, 24413, 92 | 24278, 24143, 24006, 23869, 23731, 23592, 23452, 23311, 93 | 23169, 23027, 22883, 22739, 22594, 22448, 22301, 22153, 94 | 22004, 21855, 21705, 21554, 21402, 21249, 21096, 20942, 95 | 20787, 20631, 20474, 20317, 20159, 20000, 19840, 19680, 96 | 19519, 19357, 19194, 19031, 18867, 18702, 18537, 18371, 97 | 18204, 18036, 17868, 17699, 17530, 17360, 17189, 17017, 98 | 16845, 16672, 16499, 16325, 16150, 15975, 15799, 15623, 99 | 15446, 15268, 15090, 14911, 14732, 14552, 14372, 14191, 100 | 14009, 13827, 13645, 13462, 13278, 13094, 12909, 12724, 101 | 12539, 12353, 12166, 11980, 11792, 11604, 11416, 11227, 102 | 11038, 10849, 10659, 10469, 10278, 10087, 9895, 9703, 103 | 9511, 9319, 9126, 8932, 8739, 8545, 8351, 8156, 104 | 7961, 7766, 7571, 7375, 7179, 6982, 6786, 6589, 105 | 6392, 6195, 5997, 5799, 5601, 5403, 5205, 5006, 106 | 4807, 4608, 4409, 4210, 4011, 3811, 3611, 3411, 107 | 3211, 3011, 2811, 2610, 2410, 2209, 2009, 1808, 108 | 1607, 1406, 1206, 1005, 804, 603, 402, 201, 109 | 0, -201, -402, -603, -804, -1005, -1206, -1406, 110 | -1607, -1808, -2009, -2209, -2410, -2610, -2811, -3011, 111 | -3211, -3411, -3611, -3811, -4011, -4210, -4409, -4608, 112 | -4807, -5006, -5205, -5403, -5601, -5799, -5997, -6195, 113 | -6392, -6589, -6786, -6982, -7179, -7375, -7571, -7766, 114 | -7961, -8156, -8351, -8545, -8739, -8932, -9126, -9319, 115 | -9511, -9703, -9895, -10087, -10278, -10469, -10659, -10849, 116 | -11038, -11227, -11416, -11604, -11792, -11980, -12166, -12353, 117 | -12539, -12724, -12909, -13094, -13278, -13462, -13645, -13827, 118 | -14009, -14191, -14372, -14552, -14732, -14911, -15090, -15268, 119 | -15446, -15623, -15799, -15975, -16150, -16325, -16499, -16672, 120 | -16845, -17017, -17189, -17360, -17530, -17699, -17868, -18036, 121 | -18204, -18371, -18537, -18702, -18867, -19031, -19194, -19357, 122 | -19519, -19680, -19840, -20000, -20159, -20317, -20474, -20631, 123 | -20787, -20942, -21096, -21249, -21402, -21554, -21705, -21855, 124 | -22004, -22153, -22301, -22448, -22594, -22739, -22883, -23027, 125 | -23169, -23311, -23452, -23592, -23731, -23869, -24006, -24143, 126 | -24278, -24413, -24546, -24679, -24811, -24942, -25072, -25201, 127 | -25329, -25456, -25582, -25707, -25831, -25954, -26077, -26198, 128 | -26318, -26437, -26556, -26673, -26789, -26905, -27019, -27132, 129 | -27244, -27355, -27466, -27575, -27683, -27790, -27896, -28001, 130 | -28105, -28208, -28309, -28410, -28510, -28608, -28706, -28802, 131 | -28897, -28992, -29085, -29177, -29268, -29358, -29446, -29534, 132 | -29621, -29706, -29790, -29873, -29955, -30036, -30116, -30195, 133 | -30272, -30349, -30424, -30498, -30571, -30643, -30713, -30783, 134 | -30851, -30918, -30984, -31049, -31113, -31175, -31236, -31297, 135 | -31356, -31413, -31470, -31525, -31580, -31633, -31684, -31735, 136 | -31785, -31833, -31880, -31926, -31970, -32014, -32056, -32097, 137 | -32137, -32176, -32213, -32249, -32284, -32318, -32350, -32382, 138 | -32412, -32441, -32468, -32495, -32520, -32544, -32567, -32588, 139 | -32609, -32628, -32646, -32662, -32678, -32692, -32705, -32717, 140 | -32727, -32736, -32744, -32751, -32757, -32761, -32764, -32766, 141 | }; 142 | 143 | /* 144 | FIX_MPY() - fixed-point multiplication & scaling. 145 | Substitute inline assembly for hardware-specific 146 | optimization suited to a particluar DSP processor. 147 | Scaling ensures that result remains 16-bit. 148 | */ 149 | short FIX_MPY(short a, short b) 150 | { 151 | /* shift right one less bit (i.e. 15-1) */ 152 | int c = ((int)a * (int)b) >> 14; 153 | /* last bit shifted out = rounding-bit */ 154 | b = c & 0x01; 155 | /* last shift + rounding bit */ 156 | a = (c >> 1) + b; 157 | return a; 158 | } 159 | 160 | /* 161 | fix_fft() - perform forward/inverse fast Fourier transform. 162 | fr[n],fi[n] are real and imaginary arrays, both INPUT AND 163 | RESULT (in-place FFT), with 0 <= n < 2**m; set inverse to 164 | 0 for forward transform (FFT), or 1 for iFFT. 165 | */ 166 | int fix_fft(short fr[], short fi[], short m, short inverse) 167 | { 168 | int mr, nn, i, j, l, k, istep, n, scale, shift; 169 | short qr, qi, tr, ti, wr, wi; 170 | 171 | n = 1 << m; 172 | 173 | /* max FFT size = N_WAVE */ 174 | if (n > N_WAVE) 175 | return -1; 176 | 177 | mr = 0; 178 | nn = n - 1; 179 | scale = 0; 180 | 181 | /* decimation in time - re-order data */ 182 | for (m=1; m<=nn; ++m) { 183 | l = n; 184 | do { 185 | l >>= 1; 186 | } while (mr+l > nn); 187 | mr = (mr & (l-1)) + l; 188 | 189 | if (mr <= m) 190 | continue; 191 | tr = fr[m]; 192 | fr[m] = fr[mr]; 193 | fr[mr] = tr; 194 | ti = fi[m]; 195 | fi[m] = fi[mr]; 196 | fi[mr] = ti; 197 | } 198 | 199 | l = 1; 200 | k = LOG2_N_WAVE-1; 201 | while (l < n) { 202 | if (inverse) { 203 | /* variable scaling, depending upon data */ 204 | shift = 0; 205 | for (i=0; i 16383 || m > 16383) { 213 | shift = 1; 214 | break; 215 | } 216 | } 217 | if (shift) 218 | ++scale; 219 | } else { 220 | /* 221 | fixed scaling, for proper normalization -- 222 | there will be log2(n) passes, so this results 223 | in an overall factor of 1/n, distributed to 224 | maximize arithmetic accuracy. 225 | */ 226 | shift = 1; 227 | } 228 | /* 229 | it may not be obvious, but the shift will be 230 | performed on each data point exactly once, 231 | during this pass. 232 | */ 233 | istep = l << 1; 234 | for (m=0; m>= 1; 243 | wi >>= 1; 244 | } 245 | for (i=m; i>= 1; 253 | qi >>= 1; 254 | } 255 | fr[j] = qr - tr; 256 | fi[j] = qi - ti; 257 | fr[i] = qr + tr; 258 | fi[i] = qi + ti; 259 | } 260 | } 261 | --k; 262 | l = istep; 263 | } 264 | return scale; 265 | } 266 | 267 | /* 268 | fix_fftr() - forward/inverse FFT on array of real numbers. 269 | Real FFT/iFFT using half-size complex FFT by distributing 270 | even/odd samples into real/imaginary arrays respectively. 271 | In order to save data space (i.e. to avoid two arrays, one 272 | for real, one for imaginary samples), we proceed in the 273 | following two steps: a) samples are rearranged in the real 274 | array so that all even samples are in places 0-(N/2-1) and 275 | all imaginary samples in places (N/2)-(N-1), and b) fix_fft 276 | is called with fr and fi pointing to index 0 and index N/2 277 | respectively in the original array. The above guarantees 278 | that fix_fft "sees" consecutive real samples as alternating 279 | real and imaginary samples in the complex array. 280 | */ 281 | int fix_fftr(short f[], int m, int inverse) 282 | { 283 | int i, N = 1<<(m-1), scale = 0; 284 | short tt, *fr=f, *fi=&f[N]; 285 | 286 | if (inverse) 287 | scale = fix_fft(fi, fr, m-1, inverse); 288 | for (i=1; i num) bit >>= 2; 26 | 27 | // The main part is executed twice, in order to avoid 28 | // using 64 bit values in computations. 29 | for (n = 0; n < 2; n++) 30 | { 31 | // First we get the top 24 bits of the answer. 32 | while (bit) 33 | { 34 | if (num >= result + bit) 35 | { 36 | num -= result + bit; 37 | result = (result >> 1) + bit; 38 | } 39 | else 40 | { 41 | result = (result >> 1); 42 | } 43 | bit >>= 2; 44 | } 45 | 46 | if (n == 0) 47 | { 48 | // Then process it again to get the lowest 8 bits. 49 | if (num > 65535) 50 | { 51 | // The remainder 'num' is too large to be shifted left 52 | // by 16, so we have to add 1 to result manually and 53 | // adjust 'num' accordingly. 54 | // num = a - (result + 0.5)^2 55 | // = num + result^2 - (result + 0.5)^2 56 | // = num - result - 0.5 57 | num -= result; 58 | num = (num << 16) - 0x8000; 59 | result = (result << 16) + 0x8000; 60 | } 61 | else 62 | { 63 | num <<= 16; 64 | result <<= 16; 65 | } 66 | 67 | bit = 1 << 14; 68 | } 69 | } 70 | 71 | #ifndef FIXMATH_NO_ROUNDING 72 | // Finally, if next bit would have been 1, round the result upwards. 73 | if (num > result) 74 | { 75 | result++; 76 | } 77 | #endif 78 | 79 | return result; 80 | } 81 | -------------------------------------------------------------------------------- /src/output.c: -------------------------------------------------------------------------------- 1 | 2 | #include "main.h" 3 | 4 | //an fft of 512 gives us 256 buckets of frequency info. at 20khz, each has ~38Hz 5 | //we don't really want all 256 buckets of frequency info 6 | //if we compressed this linearly, we'd lose a lot of low/mid tone info 7 | //also, in order to capture low frequency stuff below 38Hz would require a much larger fft 8 | //so we can combine a downsampled 400hz using a smaller fft for low frequency stuff with the 20khz stuff 9 | 10 | //the first 6 buckets are dedicated to low frequency audio from 12.5-162.5 Hz 11 | const uint8_t lowFrequencyMap[6] = { 12 | 3, 4, 6, 8, 10, 13 13 | }; 14 | //the next 26 buckets are dedicated to higher frequency audio from 195Hz to just under the nyquist limit of 10khz 15 | const uint8_t highFrequencyMap[26] = { 16 | 5, 6, 8, 10, 12, 15, 18, 22, 25, 30, 35, 40, 46, 53, 61, 70, 80, 92, 105, 119, 136, 154, 175, 199, 225, 255, 17 | }; 18 | 19 | 20 | char outBuffer[100]; 21 | int outBufferLen; 22 | 23 | #define WRITEOUT(v) {memcpy(out, &v, sizeof(v)); out+= sizeof(v);} 24 | 25 | /* 26 | * Takes a real input, applies Hann window, calculates energyAverage 27 | * out must be the the same size as in as it is used for the imaginary part 28 | * after returning, the first half is filled with bucket magnitudes 29 | * magnitude is multiplied by 16 and saturates at 16 bits 30 | * m = log2(n) 31 | */ 32 | void fftRealWindowedMagnitude(int16_t * in, uint16_t * out, int m, uint16_t * energyAverage) { 33 | int16_t * imag = (int16_t *) out; //borrow out for imaginary part 34 | int n = 1 << m; 35 | 36 | //init with zeros 37 | for (int i = 0; i < n; i++) { 38 | imag[i] = 0; 39 | } 40 | uint32_t energyTotal = 0; 41 | for (int i = 0; i < n; i++) { 42 | energyTotal += abs(in[i]); 43 | 44 | //apply the hann windowing function, borrowing Sinewave LUT from fix_fft 45 | //the positive portion of Sinewave ranges from index 0-512 46 | // (i * 512) / n == (i * 512) >> m 47 | int si = (i * 512) >> m ; 48 | in[i] = (Sinewave[si] * in[i]) >> 16; 49 | } 50 | *energyAverage = energyTotal >> m; 51 | 52 | //run the FFT (runs in place, overwriting both in and imag) 53 | fix_fft(in, imag, m, 0); 54 | 55 | //calculate the magnitude and store in out for only the first half 56 | int halfN = n>>1; 57 | for (int i = 0; i < halfN; i++) { 58 | //using the fix16_sqrt gives us a bit more resolution as we get 59 | //8 bits more using this over an integer sqrt 60 | int32_t t = fix16_sqrt(imag[i] * imag[i] + in[i] * in[i]); 61 | 62 | //we can't keep all those extra bits, but 4 of 8 seems like a good value 63 | //as this only overloads a little and only for REALLY LOUD inputs 64 | t >>= 4; 65 | if (t > 0xffff) 66 | t = 0xffff; 67 | out[i] = t; 68 | } 69 | } 70 | 71 | void processSensorData(int16_t * audioBuffer, int16_t * audio400HzBuffer, volatile uint16_t adcBuffer[7], volatile int16_t accelerometer[3]) { 72 | uint16_t magnitude[HIGH_N]; //temp and output from the fft 73 | uint16_t lowEnergy; 74 | uint16_t energyAverage; 75 | int maxFrequencyIndex = 0; 76 | uint16_t maxFrequencyMagnitude = 0; 77 | uint16_t maxFrequencyHz; 78 | char * out = outBuffer; 79 | 80 | //start making output buffer 81 | WRITEOUT("SB1.0"); 82 | 83 | //do the low frequency stuff 84 | fftRealWindowedMagnitude(audio400HzBuffer, &magnitude[0], LOW_NLOG2, &lowEnergy); 85 | //write out low frequency stuff 86 | for (int i = 0, k = lowFrequencyMap[0]; i < 6; i++) { 87 | int top = lowFrequencyMap[i] + 1; 88 | uint16_t max = 0; 89 | for (; k < top; k++) { 90 | max = magnitude[k] > max ? magnitude[k] : max; 91 | } 92 | WRITEOUT(max); 93 | } 94 | 95 | //do high frequency stuff 96 | fftRealWindowedMagnitude(audioBuffer, &magnitude[0], HIGH_NLOG2, &energyAverage); 97 | 98 | //run through and get maxFrequency info 99 | for (int i = 1; i < HIGH_N/2; i++) { 100 | if (magnitude[i] > maxFrequencyMagnitude) { 101 | maxFrequencyMagnitude = magnitude[i]; 102 | maxFrequencyIndex = i; 103 | } 104 | } 105 | 106 | //write out high frequency stuff 107 | for (int i = 0, k = highFrequencyMap[0]; i < 26; i++) { 108 | int top = highFrequencyMap[i] + 1; 109 | uint16_t max = 0; 110 | for (; k < top; k++) { 111 | max = magnitude[k] > max ? magnitude[k] : max; 112 | } 113 | WRITEOUT(max); 114 | } 115 | 116 | WRITEOUT(energyAverage); 117 | WRITEOUT(maxFrequencyMagnitude); 118 | maxFrequencyHz = (20000 * (int32_t)maxFrequencyIndex) / 512; //or 39.0625 per bin 119 | WRITEOUT(maxFrequencyHz); 120 | 121 | for (int i = 0; i < 3; i++) { 122 | int16_t v = accelerometer[i]; 123 | WRITEOUT(v); 124 | } 125 | 126 | //light 127 | uint16_t v = adcBuffer[1]<<4; 128 | WRITEOUT(v); 129 | 130 | //a0 131 | v = adcBuffer[2]<<4; 132 | WRITEOUT(v); 133 | //a1 134 | v = adcBuffer[6]<<4; 135 | WRITEOUT(v); 136 | //a2 137 | v = adcBuffer[5]<<4; 138 | WRITEOUT(v); 139 | //a3 140 | v = adcBuffer[4]<<4; 141 | WRITEOUT(v); 142 | //a4 143 | v = adcBuffer[3]<<4; 144 | WRITEOUT(v); 145 | 146 | 147 | WRITEOUT("END"); 148 | 149 | outBufferLen = out - outBuffer; 150 | writeToUsart((uint8_t *) outBuffer, outBufferLen); 151 | } 152 | -------------------------------------------------------------------------------- /src/syscalls.c: -------------------------------------------------------------------------------- 1 | /** 2 | ***************************************************************************** 3 | ** 4 | ** File : syscalls.c 5 | ** 6 | ** Abstract : System Workbench Minimal System calls file 7 | ** 8 | ** For more information about which c-functions 9 | ** need which of these lowlevel functions 10 | ** please consult the Newlib libc-manual 11 | ** 12 | ** Environment : System Workbench for MCU 13 | ** 14 | ** Distribution: The file is distributed �as is,� without any warranty 15 | ** of any kind. 16 | ** 17 | ***************************************************************************** 18 | ** 19 | **

© COPYRIGHT(c) 2014 Ac6

20 | ** 21 | ** Redistribution and use in source and binary forms, with or without modification, 22 | ** are permitted provided that the following conditions are met: 23 | ** 1. Redistributions of source code must retain the above copyright notice, 24 | ** this list of conditions and the following disclaimer. 25 | ** 2. Redistributions in binary form must reproduce the above copyright notice, 26 | ** this list of conditions and the following disclaimer in the documentation 27 | ** and/or other materials provided with the distribution. 28 | ** 3. Neither the name of Ac6 nor the names of its contributors 29 | ** may be used to endorse or promote products derived from this software 30 | ** without specific prior written permission. 31 | ** 32 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 33 | ** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 34 | ** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 35 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 36 | ** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 37 | ** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 38 | ** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 39 | ** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 40 | ** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 41 | ** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 42 | ** 43 | ***************************************************************************** 44 | */ 45 | 46 | /* Includes */ 47 | #include 48 | #include 49 | #include 50 | #include 51 | #include 52 | #include 53 | #include 54 | #include 55 | 56 | 57 | /* Variables */ 58 | //#undef errno 59 | extern int errno; 60 | extern int __io_putchar(int ch) __attribute__((weak)); 61 | extern int __io_getchar(void) __attribute__((weak)); 62 | 63 | register char * stack_ptr asm("sp"); 64 | 65 | char *__env[1] = { 0 }; 66 | char **environ = __env; 67 | 68 | 69 | /* Functions */ 70 | void initialise_monitor_handles() 71 | { 72 | } 73 | 74 | int _getpid(void) 75 | { 76 | return 1; 77 | } 78 | 79 | int _kill(int pid, int sig) 80 | { 81 | errno = EINVAL; 82 | return -1; 83 | } 84 | 85 | void _exit (int status) 86 | { 87 | _kill(status, -1); 88 | while (1) {} /* Make sure we hang here */ 89 | } 90 | 91 | int _read (int file, char *ptr, int len) 92 | { 93 | int DataIdx; 94 | 95 | for (DataIdx = 0; DataIdx < len; DataIdx++) 96 | { 97 | *ptr++ = __io_getchar(); 98 | } 99 | 100 | return len; 101 | } 102 | 103 | int _write(int file, char *ptr, int len) 104 | { 105 | int DataIdx; 106 | 107 | for (DataIdx = 0; DataIdx < len; DataIdx++) 108 | { 109 | __io_putchar(*ptr++); 110 | } 111 | return len; 112 | } 113 | 114 | caddr_t _sbrk(int incr) 115 | { 116 | extern char end asm("end"); 117 | static char *heap_end; 118 | char *prev_heap_end; 119 | 120 | if (heap_end == 0) 121 | heap_end = &end; 122 | 123 | prev_heap_end = heap_end; 124 | if (heap_end + incr > stack_ptr) 125 | { 126 | // write(1, "Heap and stack collision\n", 25); 127 | // abort(); 128 | errno = ENOMEM; 129 | return (caddr_t) -1; 130 | } 131 | 132 | heap_end += incr; 133 | 134 | return (caddr_t) prev_heap_end; 135 | } 136 | 137 | int _close(int file) 138 | { 139 | return -1; 140 | } 141 | 142 | 143 | int _fstat(int file, struct stat *st) 144 | { 145 | st->st_mode = S_IFCHR; 146 | return 0; 147 | } 148 | 149 | int _isatty(int file) 150 | { 151 | return 1; 152 | } 153 | 154 | int _lseek(int file, int ptr, int dir) 155 | { 156 | return 0; 157 | } 158 | 159 | int _open(char *path, int flags, ...) 160 | { 161 | /* Pretend like we always fail */ 162 | return -1; 163 | } 164 | 165 | int _wait(int *status) 166 | { 167 | errno = ECHILD; 168 | return -1; 169 | } 170 | 171 | int _unlink(char *name) 172 | { 173 | errno = ENOENT; 174 | return -1; 175 | } 176 | 177 | int _times(struct tms *buf) 178 | { 179 | return -1; 180 | } 181 | 182 | int _stat(char *file, struct stat *st) 183 | { 184 | st->st_mode = S_IFCHR; 185 | return 0; 186 | } 187 | 188 | int _link(char *old, char *new) 189 | { 190 | errno = EMLINK; 191 | return -1; 192 | } 193 | 194 | int _fork(void) 195 | { 196 | errno = EAGAIN; 197 | return -1; 198 | } 199 | 200 | int _execve(char *name, char **argv, char **env) 201 | { 202 | errno = ENOMEM; 203 | return -1; 204 | } 205 | -------------------------------------------------------------------------------- /src/system_stm32f0xx.c: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file system_stm32f0xx.c 4 | * @author MCD Application Team 5 | * @version V1.4.0 6 | * @date 05-December-2014 7 | * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. 8 | * This file contains the system clock configuration for STM32F0xx devices, 9 | * and is generated by the clock configuration tool 10 | * STM32F0xx_Clock_Configuration_V1.0.0.xls 11 | * 12 | * 1. This file provides two functions and one global variable to be called from 13 | * user application: 14 | * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier 15 | * and Divider factors, AHB/APBx prescalers and Flash settings), 16 | * depending on the configuration made in the clock xls tool. 17 | * This function is called at startup just after reset and 18 | * before branch to main program. This call is made inside 19 | * the "startup_stm32f0xx.s" file. 20 | * 21 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used 22 | * by the user application to setup the SysTick 23 | * timer or configure other parameters. 24 | * 25 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must 26 | * be called whenever the core clock is changed 27 | * during program execution. 28 | * 29 | * 2. After each device reset the HSI (8 MHz Range) is used as system clock source. 30 | * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to 31 | * configure the system clock before to branch to main program. 32 | * 33 | * 3. If the system clock source selected by user fails to startup, the SystemInit() 34 | * function will do nothing and HSI still used as system clock source. User can 35 | * add some code to deal with this issue inside the SetSysClock() function. 36 | * 37 | * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define 38 | * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or 39 | * through PLL, and you are using different crystal you have to adapt the HSE 40 | * value to your own configuration. 41 | * 42 | * 5. This file configures the system clock as follows: 43 | *============================================================================= 44 | * System Clock Configuration 45 | *============================================================================= 46 | * System Clock source | PLL(HSE) 47 | *----------------------------------------------------------------------------- 48 | * SYSCLK | 48000000 Hz 49 | *----------------------------------------------------------------------------- 50 | * HCLK | 48000000 Hz 51 | *----------------------------------------------------------------------------- 52 | * AHB Prescaler | 1 53 | *----------------------------------------------------------------------------- 54 | * APB1 Prescaler | 1 55 | *----------------------------------------------------------------------------- 56 | * APB2 Prescaler | 1 57 | *----------------------------------------------------------------------------- 58 | * HSE Frequency | 8000000 Hz 59 | *----------------------------------------------------------------------------- 60 | * PLL MUL | 6 61 | *----------------------------------------------------------------------------- 62 | * VDD | 3.3 V 63 | *----------------------------------------------------------------------------- 64 | * Flash Latency | 1 WS 65 | *----------------------------------------------------------------------------- 66 | *============================================================================= 67 | ****************************************************************************** 68 | * @attention 69 | * 70 | *

© COPYRIGHT 2014 STMicroelectronics

71 | * 72 | * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); 73 | * You may not use this file except in compliance with the License. 74 | * You may obtain a copy of the License at: 75 | * 76 | * http://www.st.com/software_license_agreement_liberty_v2 77 | * 78 | * Unless required by applicable law or agreed to in writing, software 79 | * distributed under the License is distributed on an "AS IS" BASIS, 80 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 81 | * See the License for the specific language governing permissions and 82 | * limitations under the License. 83 | * 84 | ****************************************************************************** 85 | */ 86 | 87 | /** @addtogroup CMSIS 88 | * @{ 89 | */ 90 | 91 | /** @addtogroup stm32f0xx_system 92 | * @{ 93 | */ 94 | 95 | /** @addtogroup STM32F0xx_System_Private_Includes 96 | * @{ 97 | */ 98 | 99 | #include "stm32f0xx.h" 100 | 101 | /** 102 | * @} 103 | */ 104 | 105 | /** @addtogroup STM32F0xx_System_Private_TypesDefinitions 106 | * @{ 107 | */ 108 | 109 | /** 110 | * @} 111 | */ 112 | 113 | /** @addtogroup STM32F0xx_System_Private_Defines 114 | * @{ 115 | */ 116 | /** 117 | * @} 118 | */ 119 | 120 | /** @addtogroup STM32F0xx_System_Private_Macros 121 | * @{ 122 | */ 123 | 124 | /** 125 | * @} 126 | */ 127 | 128 | /** @addtogroup STM32F0xx_System_Private_Variables 129 | * @{ 130 | */ 131 | uint32_t SystemCoreClock = 48000000; 132 | __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; 133 | 134 | /** 135 | * @} 136 | */ 137 | 138 | /** @addtogroup STM32F0xx_System_Private_FunctionPrototypes 139 | * @{ 140 | */ 141 | 142 | static void SetSysClock(void); 143 | 144 | /** 145 | * @} 146 | */ 147 | 148 | /** @addtogroup STM32F0xx_System_Private_Functions 149 | * @{ 150 | */ 151 | 152 | /** 153 | * @brief Setup the microcontroller system. 154 | * Initialize the Embedded Flash Interface, the PLL and update the 155 | * SystemCoreClock variable. 156 | * @param None 157 | * @retval None 158 | */ 159 | void SystemInit (void) 160 | { 161 | RCC->CFGR = RCC->CFGR & (~RCC_CFGR_PLLMUL) | (RCC_CFGR_PLLMUL12); 162 | RCC->CR |= RCC_CR_PLLON; 163 | while ((RCC->CR & RCC_CR_PLLRDY) == 0) 164 | ; 165 | RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); 166 | while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) 167 | ; 168 | 169 | /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ 170 | SetSysClock(); 171 | } 172 | 173 | /** 174 | * @brief Update SystemCoreClock according to Clock Register Values 175 | * The SystemCoreClock variable contains the core clock (HCLK), it can 176 | * be used by the user application to setup the SysTick timer or configure 177 | * other parameters. 178 | * 179 | * @note Each time the core clock (HCLK) changes, this function must be called 180 | * to update SystemCoreClock variable value. Otherwise, any configuration 181 | * based on this variable will be incorrect. 182 | * 183 | * @note - The system frequency computed by this function is not the real 184 | * frequency in the chip. It is calculated based on the predefined 185 | * constant and the selected clock source: 186 | * 187 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) 188 | * 189 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) 190 | * 191 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 192 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. 193 | * 194 | * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value 195 | * 8 MHz) but the real value may vary depending on the variations 196 | * in voltage and temperature. 197 | * 198 | * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value 199 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real 200 | * frequency of the crystal used. Otherwise, this function may 201 | * have wrong result. 202 | * 203 | * - The result of this function could be not correct when using fractional 204 | * value for HSE crystal. 205 | * @param None 206 | * @retval None 207 | */ 208 | void SystemCoreClockUpdate (void) 209 | { 210 | uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0; 211 | 212 | /* Get SYSCLK source -------------------------------------------------------*/ 213 | tmp = RCC->CFGR & RCC_CFGR_SWS; 214 | 215 | switch (tmp) 216 | { 217 | case 0x00: /* HSI used as system clock */ 218 | SystemCoreClock = HSI_VALUE; 219 | break; 220 | case 0x04: /* HSE used as system clock */ 221 | SystemCoreClock = HSE_VALUE; 222 | break; 223 | case 0x08: /* PLL used as system clock */ 224 | /* Get PLL clock source and multiplication factor ----------------------*/ 225 | pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; 226 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; 227 | pllmull = ( pllmull >> 18) + 2; 228 | 229 | if (pllsource == 0x00) 230 | { 231 | /* HSI oscillator clock divided by 2 selected as PLL clock entry */ 232 | SystemCoreClock = (HSI_VALUE >> 1) * pllmull; 233 | } 234 | else 235 | { 236 | prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; 237 | /* HSE oscillator clock selected as PREDIV1 clock entry */ 238 | SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; 239 | } 240 | break; 241 | default: /* HSI used as system clock */ 242 | SystemCoreClock = HSI_VALUE; 243 | break; 244 | } 245 | /* Compute HCLK clock frequency ----------------*/ 246 | /* Get HCLK prescaler */ 247 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; 248 | /* HCLK clock frequency */ 249 | SystemCoreClock >>= tmp; 250 | } 251 | 252 | /** 253 | * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash 254 | * settings. 255 | * @note This function should be called only once the RCC clock configuration 256 | * is reset to the default reset state (done in SystemInit() function). 257 | * @param None 258 | * @retval None 259 | */ 260 | static void SetSysClock(void) 261 | { 262 | __IO uint32_t StartUpCounter = 0, HSEStatus = 0; 263 | 264 | /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/ 265 | /* Enable HSE */ 266 | RCC->CR |= ((uint32_t)RCC_CR_HSEON); 267 | 268 | /* Wait till HSE is ready and if Time out is reached exit */ 269 | do 270 | { 271 | HSEStatus = RCC->CR & RCC_CR_HSERDY; 272 | StartUpCounter++; 273 | } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); 274 | 275 | if ((RCC->CR & RCC_CR_HSERDY) != RESET) 276 | { 277 | HSEStatus = (uint32_t)0x01; 278 | } 279 | else 280 | { 281 | HSEStatus = (uint32_t)0x00; 282 | } 283 | 284 | if (HSEStatus == (uint32_t)0x01) 285 | { 286 | /* Enable Prefetch Buffer and set Flash Latency */ 287 | FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY; 288 | 289 | /* HCLK = SYSCLK */ 290 | RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; 291 | 292 | /* PCLK = HCLK */ 293 | RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1; 294 | 295 | /* PLL configuration = HSE * 6 = 48 MHz */ 296 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); 297 | RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6); 298 | 299 | /* Enable PLL */ 300 | RCC->CR |= RCC_CR_PLLON; 301 | 302 | /* Wait till PLL is ready */ 303 | while((RCC->CR & RCC_CR_PLLRDY) == 0) 304 | { 305 | } 306 | 307 | /* Select PLL as system clock source */ 308 | RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); 309 | RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; 310 | 311 | /* Wait till PLL is used as system clock source */ 312 | while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) 313 | { 314 | } 315 | } 316 | else 317 | { /* If HSE fails to start-up, the application will have wrong clock 318 | configuration. User can add here some code to deal with this error */ 319 | } 320 | } 321 | 322 | /** 323 | * @} 324 | */ 325 | 326 | /** 327 | * @} 328 | */ 329 | 330 | /** 331 | * @} 332 | */ 333 | 334 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 335 | -------------------------------------------------------------------------------- /startup/startup_stm32.s: -------------------------------------------------------------------------------- 1 | /** 2 | ****************************************************************************** 3 | * @file startup_stm32.s dedicated to STM32F030F4Px device 4 | * @author Ac6 5 | * @version V1.0.0 6 | * @date 2018-02-23 7 | ****************************************************************************** 8 | */ 9 | 10 | .syntax unified 11 | .cpu cortex-m0 12 | .fpu softvfp 13 | .thumb 14 | 15 | .global g_pfnVectors 16 | .global Default_Handler 17 | 18 | /* start address for the initialization values of the .data section. 19 | defined in linker script */ 20 | .word _sidata 21 | /* start address for the .data section. defined in linker script */ 22 | .word _sdata 23 | /* end address for the .data section. defined in linker script */ 24 | .word _edata 25 | /* start address for the .bss section. defined in linker script */ 26 | .word _sbss 27 | /* end address for the .bss section. defined in linker script */ 28 | .word _ebss 29 | 30 | /** 31 | * @brief This is the code that gets called when the processor first 32 | * starts execution following a reset event. Only the absolutely 33 | * necessary set is performed, after which the application 34 | * supplied main() routine is called. 35 | * @param None 36 | * @retval : None 37 | */ 38 | 39 | .section .text.Reset_Handler 40 | .weak Reset_Handler 41 | .type Reset_Handler, %function 42 | Reset_Handler: 43 | ldr r0, =_estack 44 | mov sp, r0 /* set stack pointer */ 45 | 46 | /* Copy the data segment initializers from flash to SRAM */ 47 | ldr r0, =_sdata 48 | ldr r1, =_edata 49 | ldr r2, =_sidata 50 | movs r3, #0 51 | b LoopCopyDataInit 52 | 53 | CopyDataInit: 54 | ldr r4, [r2, r3] 55 | str r4, [r0, r3] 56 | adds r3, r3, #4 57 | 58 | LoopCopyDataInit: 59 | adds r4, r0, r3 60 | cmp r4, r1 61 | bcc CopyDataInit 62 | 63 | /* Zero fill the bss segment. */ 64 | ldr r2, =_sbss 65 | ldr r4, =_ebss 66 | movs r3, #0 67 | b LoopFillZerobss 68 | 69 | FillZerobss: 70 | str r3, [r2] 71 | adds r2, r2, #4 72 | 73 | LoopFillZerobss: 74 | cmp r2, r4 75 | bcc FillZerobss 76 | 77 | /* Call the clock system intitialization function.*/ 78 | bl SystemInit 79 | /* Call static constructors */ 80 | /* bl __libc_init_array */ 81 | /* Call the application's entry point.*/ 82 | bl main 83 | 84 | LoopForever: 85 | b LoopForever 86 | 87 | 88 | .size Reset_Handler, .-Reset_Handler 89 | 90 | /** 91 | * @brief This is the code that gets called when the processor receives an 92 | * unexpected interrupt. This simply enters an infinite loop, preserving 93 | * the system state for examination by a debugger. 94 | * 95 | * @param None 96 | * @retval : None 97 | */ 98 | .section .text.Default_Handler,"ax",%progbits 99 | Default_Handler: 100 | Infinite_Loop: 101 | b Infinite_Loop 102 | .size Default_Handler, .-Default_Handler 103 | /****************************************************************************** 104 | * 105 | * The STM32F030F4Px vector table. Note that the proper constructs 106 | * must be placed on this to ensure that it ends up at physical address 107 | * 0x0000.0000. 108 | * 109 | ******************************************************************************/ 110 | .section .isr_vector,"a",%progbits 111 | .type g_pfnVectors, %object 112 | .size g_pfnVectors, .-g_pfnVectors 113 | 114 | 115 | g_pfnVectors: 116 | .word _estack 117 | .word Reset_Handler 118 | .word NMI_Handler 119 | .word HardFault_Handler 120 | .word 0 121 | .word 0 122 | .word 0 123 | .word 0 124 | .word 0 125 | .word 0 126 | .word 0 127 | .word SVC_Handler 128 | .word 0 129 | .word 0 130 | .word PendSV_Handler 131 | .word SysTick_Handler 132 | .word WWDG_IRQHandler /* Window Watchdog interrupt */ 133 | .word PVD_IRQHandler /* PVD and VDDIO2 supply comparator interrupt */ 134 | .word RTC_IRQHandler /* RTC interrupts */ 135 | .word FLASH_IRQHandler /* Flash global interrupt */ 136 | .word RCC_IRQHandler /* RCC global interruptr */ 137 | .word EXTI0_1_IRQHandler /* EXTI Line[1:0] interrupts */ 138 | .word EXTI2_3_IRQHandler /* EXTI Line[3:2] interrupts */ 139 | .word EXTI4_15_IRQHandler /* EXTI Line15 and EXTI4 interrupts */ 140 | .word 0 /* Reserved */ 141 | .word DMA1_CH1_IRQHandler /* DMA1 channel 1 interrupt */ 142 | .word DMA1_CH2_3_IRQHandler /* DMA1 channel 2 and 3 interrupt */ 143 | .word DMA1_CH4_5_IRQHandler /* DMA1 channel 4 and 5 interrupt */ 144 | .word ADC_IRQHandler /* ADC interrupt */ 145 | .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 break, update, trigger and commutation interrupt */ 146 | .word TIM1_CC_IRQHandler /* TIM1 Capture Compare interrupt */ 147 | .word 0 /* Reserved */ 148 | .word TIM3_IRQHandler /* TIM3 global interrupt */ 149 | .word TIM6_IRQHandler /* TIM6 global interrupt */ 150 | .word 0 /* Reserved */ 151 | .word TIM14_IRQHandler /* TIM14 global interrupt */ 152 | .word TIM15_IRQHandler /* TIM15 global interrupt */ 153 | .word TIM16_IRQHandler /* TIM16 global interrupt */ 154 | .word TIM17_IRQHandler /* TIM17 global interrupt */ 155 | .word I2C1_IRQHandler /* I2C1 global interrupt */ 156 | .word I2C2_IRQHandler /* I2C2 global interrupt */ 157 | .word SPI1_IRQHandler /* SPI1_global_interrupt */ 158 | .word SPI2_IRQHandler /* SPI2 global interrupt */ 159 | .word USART1_IRQHandler /* USART1 global interrupt */ 160 | .word USART2_IRQHandler /* USART2 global interrupt */ 161 | .word USART3_4_5_6_IRQHandler /* USART3, USART4, USART5, USART6 global interrupt */ 162 | .word 0 /* Reserved */ 163 | .word USB_IRQHandler /* USB global interrupt */ 164 | 165 | /******************************************************************************* 166 | * 167 | * Provide weak aliases for each Exception handler to the Default_Handler. 168 | * As they are weak aliases, any function with the same name will override 169 | * this definition. 170 | * 171 | *******************************************************************************/ 172 | 173 | .weak NMI_Handler 174 | .thumb_set NMI_Handler,Default_Handler 175 | 176 | .weak HardFault_Handler 177 | .thumb_set HardFault_Handler,Default_Handler 178 | 179 | .weak SVC_Handler 180 | .thumb_set SVC_Handler,Default_Handler 181 | 182 | .weak PendSV_Handler 183 | .thumb_set PendSV_Handler,Default_Handler 184 | 185 | .weak SysTick_Handler 186 | .thumb_set SysTick_Handler,Default_Handler 187 | 188 | .weak WWDG_IRQHandler 189 | .thumb_set WWDG_IRQHandler,Default_Handler 190 | 191 | .weak PVD_IRQHandler 192 | .thumb_set PVD_IRQHandler,Default_Handler 193 | 194 | .weak RTC_IRQHandler 195 | .thumb_set RTC_IRQHandler,Default_Handler 196 | 197 | .weak FLASH_IRQHandler 198 | .thumb_set FLASH_IRQHandler,Default_Handler 199 | 200 | .weak RCC_IRQHandler 201 | .thumb_set RCC_IRQHandler,Default_Handler 202 | 203 | .weak EXTI0_1_IRQHandler 204 | .thumb_set EXTI0_1_IRQHandler,Default_Handler 205 | 206 | .weak EXTI2_3_IRQHandler 207 | .thumb_set EXTI2_3_IRQHandler,Default_Handler 208 | 209 | .weak EXTI4_15_IRQHandler 210 | .thumb_set EXTI4_15_IRQHandler,Default_Handler 211 | 212 | .weak DMA1_CH1_IRQHandler 213 | .thumb_set DMA1_CH1_IRQHandler,Default_Handler 214 | 215 | .weak DMA1_CH2_3_IRQHandler 216 | .thumb_set DMA1_CH2_3_IRQHandler,Default_Handler 217 | 218 | .weak DMA1_CH4_5_IRQHandler 219 | .thumb_set DMA1_CH4_5_IRQHandler,Default_Handler 220 | 221 | .weak ADC_IRQHandler 222 | .thumb_set ADC_IRQHandler,Default_Handler 223 | 224 | .weak TIM1_BRK_UP_TRG_COM_IRQHandler 225 | .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler 226 | 227 | .weak TIM1_CC_IRQHandler 228 | .thumb_set TIM1_CC_IRQHandler,Default_Handler 229 | 230 | .weak TIM3_IRQHandler 231 | .thumb_set TIM3_IRQHandler,Default_Handler 232 | 233 | .weak TIM6_IRQHandler 234 | .thumb_set TIM6_IRQHandler,Default_Handler 235 | 236 | .weak TIM14_IRQHandler 237 | .thumb_set TIM14_IRQHandler,Default_Handler 238 | 239 | .weak TIM15_IRQHandler 240 | .thumb_set TIM15_IRQHandler,Default_Handler 241 | 242 | .weak TIM16_IRQHandler 243 | .thumb_set TIM16_IRQHandler,Default_Handler 244 | 245 | .weak TIM17_IRQHandler 246 | .thumb_set TIM17_IRQHandler,Default_Handler 247 | 248 | .weak I2C1_IRQHandler 249 | .thumb_set I2C1_IRQHandler,Default_Handler 250 | 251 | .weak I2C2_IRQHandler 252 | .thumb_set I2C2_IRQHandler,Default_Handler 253 | 254 | .weak SPI1_IRQHandler 255 | .thumb_set SPI1_IRQHandler,Default_Handler 256 | 257 | .weak SPI2_IRQHandler 258 | .thumb_set SPI2_IRQHandler,Default_Handler 259 | 260 | .weak USART1_IRQHandler 261 | .thumb_set USART1_IRQHandler,Default_Handler 262 | 263 | .weak USART2_IRQHandler 264 | .thumb_set USART2_IRQHandler,Default_Handler 265 | 266 | .weak USART3_4_5_6_IRQHandler 267 | .thumb_set USART3_4_5_6_IRQHandler,Default_Handler 268 | 269 | .weak USB_IRQHandler 270 | .thumb_set USB_IRQHandler,Default_Handler 271 | 272 | .weak SystemInit 273 | 274 | /************************ (C) COPYRIGHT Ac6 *****END OF FILE****/ 275 | --------------------------------------------------------------------------------