├── .designinit ├── .gitattributes ├── .gitignore ├── README.md ├── clean_all.sh ├── doc ├── AMS_simulation.pdf ├── Docker-Tutorial.pdf └── scripts_overview.svg ├── gds └── TBD_copy_gds.txt ├── orfs ├── env.sh ├── flow │ ├── Makefile │ ├── designs │ │ ├── ihp-sg13g2 │ │ │ └── counter_board │ │ │ │ ├── autotuner.json │ │ │ │ ├── config.mk │ │ │ │ ├── constraint.sdc │ │ │ │ └── io.tcl │ │ └── src │ │ │ └── see_verilog_rtl_folder.txt │ ├── logs │ │ └── ihp-sg13g2 │ │ │ └── counter_board │ │ │ └── base │ │ │ ├── 2_1_floorplan.json │ │ │ ├── 2_2_floorplan_macro.json │ │ │ ├── 2_3_floorplan_tapcell.json │ │ │ ├── 2_4_floorplan_pdn.json │ │ │ ├── 3_1_place_gp_skip_io.json │ │ │ ├── 3_2_place_iop.json │ │ │ ├── 3_3_place_gp.json │ │ │ ├── 3_4_place_resized.json │ │ │ ├── 3_5_place_dp.json │ │ │ ├── 4_1_cts.json │ │ │ ├── 5_1_grt.json │ │ │ ├── 5_2_route.json │ │ │ ├── 5_3_fillcell.json │ │ │ ├── 6_1_fill.json │ │ │ └── 6_report.json │ ├── objects │ │ └── ihp-sg13g2 │ │ │ └── counter_board │ │ │ └── base │ │ │ ├── abc.constr │ │ │ ├── copyright.txt │ │ │ ├── klayout.lyt │ │ │ ├── klayout_tech.lef │ │ │ └── lib │ │ │ └── sg13g2_stdcell_typ_1p20V_25C.lib │ ├── platforms │ │ ├── common │ │ │ └── lcu_kogge_stone.v │ │ └── ihp-sg13g2 │ │ │ ├── IHP_rcx_patterns.rules │ │ │ ├── Readme.md │ │ │ ├── cdl │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist.cdl │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist.cdl │ │ │ ├── sg13g2_io.cdl │ │ │ ├── sg13g2_iocell.cdl │ │ │ └── sg13g2_stdcell.cdl │ │ │ ├── cells_clkgate.v │ │ │ ├── cells_latch.v │ │ │ ├── config.mk │ │ │ ├── drc │ │ │ ├── sg13g2_maximal.lydrc │ │ │ └── sg13g2_minimal.lydrc │ │ │ ├── fastroute.tcl │ │ │ ├── fill.json │ │ │ ├── gds │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist.gds │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist.gds │ │ │ ├── bondpad_70x70.gds │ │ │ ├── sg13g2_io.gds │ │ │ └── sg13g2_stdcell.gds │ │ │ ├── lef │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist.lef │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist.lef │ │ │ ├── bondpad_70x70.lef │ │ │ ├── sg13g2_io.lef │ │ │ ├── sg13g2_stdcell.lef │ │ │ └── sg13g2_tech.lef │ │ │ ├── lib │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist_fast_1p32V_m55C.lib │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist_slow_1p08V_125C.lib │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist_typ_1p20V_25C.lib │ │ │ ├── sg13g2_io_dummy.lib │ │ │ ├── sg13g2_io_fast_1p32V_3p6V_m40C.lib │ │ │ ├── sg13g2_io_fast_1p65V_3p6V_m40C.lib │ │ │ ├── sg13g2_io_slow_1p08V_3p0V_125C.lib │ │ │ ├── sg13g2_io_slow_1p35V_3p0V_125C.lib │ │ │ ├── sg13g2_io_typ_1p2V_3p3V_25C.lib │ │ │ ├── sg13g2_io_typ_1p5V_3p3V_25C.lib │ │ │ ├── sg13g2_stdcell_fast_1p32V_m40C.lib │ │ │ ├── sg13g2_stdcell_fast_1p65V_m40C.lib │ │ │ ├── sg13g2_stdcell_slow_1p08V_125C.lib │ │ │ ├── sg13g2_stdcell_slow_1p35V_125C.lib │ │ │ ├── sg13g2_stdcell_typ_1p20V_25C.lib │ │ │ └── sg13g2_stdcell_typ_1p50V_25C.lib │ │ │ ├── lvs │ │ │ ├── rule_decks │ │ │ │ ├── bjt_connections.lvs │ │ │ │ ├── bjt_derivations.lvs │ │ │ │ ├── bjt_extraction.lvs │ │ │ │ ├── cap_connections.lvs │ │ │ │ ├── cap_derivations.lvs │ │ │ │ ├── cap_extraction.lvs │ │ │ │ ├── custom_classes.lvs │ │ │ │ ├── custom_combiner.lvs │ │ │ │ ├── custom_devices.lvs │ │ │ │ ├── custom_extractor.lvs │ │ │ │ ├── custom_mim_extractor.lvs │ │ │ │ ├── custom_reader.lvs │ │ │ │ ├── custom_writer.lvs │ │ │ │ ├── devices_connections.lvs │ │ │ │ ├── diode_connections.lvs │ │ │ │ ├── diode_derivations.lvs │ │ │ │ ├── diode_extraction.lvs │ │ │ │ ├── esd_connections.lvs │ │ │ │ ├── esd_derivations.lvs │ │ │ │ ├── esd_extraction.lvs │ │ │ │ ├── general_connections.lvs │ │ │ │ ├── general_derivations.lvs │ │ │ │ ├── globals.lvs │ │ │ │ ├── ind_connections.lvs │ │ │ │ ├── ind_derivations.lvs │ │ │ │ ├── ind_extraction.lvs │ │ │ │ ├── layers_definitions.lvs │ │ │ │ ├── mos_connections.lvs │ │ │ │ ├── mos_derivations.lvs │ │ │ │ ├── mos_extraction.lvs │ │ │ │ ├── res_connections.lvs │ │ │ │ ├── res_derivations.lvs │ │ │ │ ├── res_extraction.lvs │ │ │ │ ├── rfmos_connections.lvs │ │ │ │ ├── rfmos_derivations.lvs │ │ │ │ ├── rfmos_extraction.lvs │ │ │ │ ├── tap_connections.lvs │ │ │ │ ├── tap_derivations.lvs │ │ │ │ └── tap_extraction.lvs │ │ │ ├── run_lvs.py │ │ │ └── sg13g2.lvs │ │ │ ├── make_tracks.tcl │ │ │ ├── pdn.tcl │ │ │ ├── rcx_patterns.rules │ │ │ ├── setRC.tcl │ │ │ ├── sg13g2.lyp │ │ │ ├── sg13g2.lyt │ │ │ ├── sg13g2.map │ │ │ ├── sg13g2_update.py │ │ │ ├── tapcell.tcl │ │ │ └── verilog │ │ │ ├── RM_IHPSG13_1P_1024x16_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_1024x64_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_1024x8_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_2048x64_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_256x48_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_256x64_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_4096x16_c3_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_4096x8_c3_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_512x64_c2_bm_bist.v │ │ │ ├── RM_IHPSG13_1P_64x64_c2_bm_bist.v │ │ │ ├── sg13g2_io.v │ │ │ └── sg13g2_stdcell.v │ ├── report_area.tcl │ ├── report_power.tcl │ ├── reports │ │ └── ihp-sg13g2 │ │ │ └── counter_board │ │ │ └── base │ │ │ ├── 2_floorplan_final.rpt │ │ │ ├── 3_detailed_place.rpt │ │ │ ├── 3_global_place.rpt │ │ │ ├── 3_resizer.rpt │ │ │ ├── 4_cts_final.rpt │ │ │ ├── 5_global_route.rpt │ │ │ ├── 5_route_drc.rpt │ │ │ ├── 6_finish.rpt │ │ │ ├── cts_clock_i.webp │ │ │ ├── cts_clock_i_layout.webp │ │ │ ├── final_all.webp │ │ │ ├── final_clocks.webp │ │ │ ├── final_congestion.webp │ │ │ ├── final_ir_drop.webp │ │ │ ├── final_placement.webp │ │ │ ├── final_resizer.webp │ │ │ ├── final_routing.webp │ │ │ ├── synth_check.txt │ │ │ └── synth_stat.txt │ ├── results │ │ └── ihp-sg13g2 │ │ │ └── counter_board │ │ │ └── base │ │ │ ├── 1_1_yosys_canonicalize.rtlil │ │ │ ├── 1_2_yosys.v │ │ │ ├── 1_synth.sdc │ │ │ ├── 1_synth.v │ │ │ ├── 2_1_floorplan.odb │ │ │ ├── 2_1_floorplan.sdc │ │ │ ├── 2_2_floorplan_macro.odb │ │ │ ├── 2_2_floorplan_macro.tcl │ │ │ ├── 2_3_floorplan_tapcell.odb │ │ │ ├── 2_4_floorplan_pdn.odb │ │ │ ├── 2_floorplan.odb │ │ │ ├── 2_floorplan.sdc │ │ │ ├── 3_1_place_gp_skip_io.odb │ │ │ ├── 3_2_place_iop.odb │ │ │ ├── 3_2_place_iop.tcl │ │ │ ├── 3_3_place_gp.odb │ │ │ ├── 3_4_place_resized.odb │ │ │ ├── 3_5_place_dp.odb │ │ │ ├── 3_place.odb │ │ │ ├── 3_place.sdc │ │ │ ├── 4_1_cts.odb │ │ │ ├── 4_cts.odb │ │ │ ├── 4_cts.sdc │ │ │ ├── 5_1_grt.odb │ │ │ ├── 5_1_grt.sdc │ │ │ ├── 5_2_route.odb │ │ │ ├── 5_3_fillcell.odb │ │ │ ├── 5_route.odb │ │ │ ├── 5_route.sdc │ │ │ ├── 6_1_fill.odb │ │ │ ├── 6_1_fill.sdc │ │ │ ├── 6_1_fill.v │ │ │ ├── 6_1_merged.gds │ │ │ ├── 6_final.def │ │ │ ├── 6_final.gds │ │ │ ├── 6_final.odb │ │ │ ├── 6_final.sdc │ │ │ ├── 6_final.spef │ │ │ ├── 6_final.v │ │ │ ├── clock_period.txt │ │ │ ├── mem.json │ │ │ ├── route.guide │ │ │ └── updated_clks.sdc │ ├── scripts │ │ ├── README.md │ │ ├── abc_area.script │ │ ├── abc_speed.script │ │ ├── abc_speed_gia_only.script │ │ ├── add_routing_blk.tcl │ │ ├── cdl.tcl │ │ ├── cts.tcl │ │ ├── defaults.py │ │ ├── deleteNonClkNets.tcl │ │ ├── deletePowerNets.tcl │ │ ├── deleteRoutingObstructions.tcl │ │ ├── density_fill.tcl │ │ ├── detail_place.tcl │ │ ├── detail_route.tcl │ │ ├── escape.sh │ │ ├── fillcell.tcl │ │ ├── final_report.tcl │ │ ├── floorplan.tcl │ │ ├── flow.sh │ │ ├── generate-variables-docs.py │ │ ├── generate_abstract.tcl │ │ ├── global_place.tcl │ │ ├── global_place_skip_io.tcl │ │ ├── global_route.tcl │ │ ├── io_placement.tcl │ │ ├── klayout.tcl │ │ ├── klayout │ │ │ ├── README.md │ │ │ ├── src │ │ │ │ ├── GenericLayerNameMapper.rb │ │ │ │ ├── KLayoutLayerMapGenerator.rb │ │ │ │ ├── KLayoutLayerPropertiesFileGenerator.rb │ │ │ │ ├── KLayoutTechFileGenerator.rb │ │ │ │ ├── LEFLayer.rb │ │ │ │ ├── LEFNamedObject.rb │ │ │ │ ├── LEFVia.rb │ │ │ │ ├── LEFViaData.rb │ │ │ │ └── gen_klayout_files.sh │ │ │ └── test │ │ │ │ ├── GenericLayerNameMapperTest.rb │ │ │ │ ├── KLayoutLayerMapGeneratorTest.rb │ │ │ │ ├── LEFLayerTest.rb │ │ │ │ ├── LEFNamedObjectTest.rb │ │ │ │ ├── LEFViaDataTest.rb │ │ │ │ └── LEFViaTest.rb │ │ ├── load.tcl │ │ ├── macro_place.tcl │ │ ├── macro_place_util.tcl │ │ ├── mem_dump.py │ │ ├── non_stage_variables.py │ │ ├── noop.tcl │ │ ├── open.tcl │ │ ├── pdn.tcl │ │ ├── placement_blockages.tcl │ │ ├── read_liberty.tcl │ │ ├── read_macro_placement.tcl │ │ ├── report_metrics.tcl │ │ ├── resize.tcl │ │ ├── save_images.tcl │ │ ├── sta-synth.tcl │ │ ├── synth.sh │ │ ├── synth.tcl │ │ ├── synth_canonicalize.tcl │ │ ├── synth_metrics.tcl │ │ ├── synth_preamble.tcl │ │ ├── synth_stdcells.tcl │ │ ├── synth_wrap_operators-booth.v │ │ ├── synth_wrap_operators.tcl │ │ ├── tapcell.tcl │ │ ├── util.tcl │ │ ├── variables.mk │ │ ├── variables.yaml │ │ ├── view_cells.tcl │ │ ├── write_def.tcl │ │ ├── write_ref_sdc.tcl │ │ ├── write_verilog.tcl │ │ ├── yosys.tcl │ │ ├── yosys_keep.tcl │ │ └── yosys_load.tcl │ ├── test │ │ ├── .gitignore │ │ ├── openroad.sh │ │ ├── test-do-stage.sh │ │ ├── test_autotuner.sh │ │ ├── test_delta_debug.sh │ │ ├── test_genElapsedTime.py │ │ ├── test_helper.sh │ │ ├── test_make_issue.sh │ │ └── test_outoftree.sh │ └── util │ │ ├── BUILD.bazel │ │ ├── addDummyToLef.py │ │ ├── appendStatsToDb.py │ │ ├── calBuffer.py │ │ ├── calPath.py │ │ ├── cell-veneer │ │ ├── README.md │ │ ├── lefdef.tcl │ │ ├── pkgIndex.tcl │ │ ├── wrap.tcl │ │ └── wrap_stdcells.tcl │ │ ├── checkMetadata.py │ │ ├── convertDrc.py │ │ ├── correlateRC.py │ │ ├── createGallery.py │ │ ├── cred_helper.py │ │ ├── def2stream.py │ │ ├── docker_shell │ │ ├── gallery.json │ │ ├── genAllRuleFiles.sh │ │ ├── genElapsedTime.py │ │ ├── genMassive.py │ │ ├── genMetrics.py │ │ ├── genReport.py │ │ ├── genReportTable.py │ │ ├── genRuleFile.py │ │ ├── generate-vars.sh │ │ ├── makeIssue.sh │ │ ├── merge_lib.py │ │ ├── open_plots.sh │ │ ├── plot_congestion.bzl │ │ ├── plot_congestion.py │ │ ├── plot_floorplan.py │ │ ├── preprocessLib.py │ │ ├── requirements.in │ │ ├── requirements_lock.txt │ │ ├── uploadMetadata.py │ │ ├── utils.mk │ │ ├── viewDrc.py │ │ ├── viewGuide.py │ │ ├── write_net_rc.tcl │ │ └── write_net_rc_script.tcl └── run_orfs.sh ├── python └── plot_simulations │ ├── __pycache__ │ └── ngspice2python.cpython-311.pyc │ ├── figures │ ├── counter_board_simulation.csv │ ├── counter_board_simulation.eps │ └── counter_board_simulation.svg │ ├── ngspice2python.py │ └── plot_counter_board_tb_tran.py ├── run_all.sh ├── spice ├── TBD_copy_spice.txt └── ToDo_verilog2spice.sh ├── verilog ├── gl │ └── TBD_synth_verilog_v_vp.txt ├── rtl │ ├── build │ │ ├── constants_p.o │ │ ├── counter-obj93.cf │ │ ├── counter_board.o │ │ └── counter_ea.o │ ├── counter_board │ ├── counter_board.v │ ├── counter_board_self.v │ ├── e~counter_board.o │ ├── vhdl2verilog.sh │ └── yosys_stats.sh └── sim │ ├── counter_tb.gtkw │ ├── counter_tb.v │ ├── counter_tb.vhd │ ├── sim_verilog_tb.do │ ├── sim_vhdl_tb.do │ ├── simulate_verilog.sh │ ├── wave_verilog.do │ └── wave_vhdl.do ├── vhdl ├── rtl │ ├── constants_p.vhd │ ├── counter_board.vhd │ └── counter_ea.vhd └── sim │ ├── counter_tb.gtkw │ ├── counter_tb.vhd │ ├── sim.do │ ├── simulate_vhdl.sh │ └── wave.do ├── xschem ├── counter_board.sym ├── counter_board_bus.sym ├── testbenches │ └── counter_board_tb_tran.sch └── xschemrc └── xspice ├── counter_board ├── counter_board.spice ├── counter_board.vp ├── counter_board.xspice └── counter_board_bus.xspice ├── post_layout └── TBD_xspice_files.txt ├── spi2xspice.py ├── synth └── TBD_xspice_files.txt └── verilog2xspice.sh /.designinit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/simi1505/SG13G2_ASIC-Design-Template/HEAD/.designinit -------------------------------------------------------------------------------- /.gitattributes: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/simi1505/SG13G2_ASIC-Design-Template/HEAD/.gitattributes -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/simi1505/SG13G2_ASIC-Design-Template/HEAD/.gitignore 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