├── .gitmodules
├── LICENSE
├── README.md
├── bench
├── avalon_mm_manager_tb.sv
├── avl_mm_mgr_tb
│ ├── .gitignore
│ └── work
│ │ └── .gitignore
├── core_tb
│ ├── .gitignore
│ └── work
│ │ └── .gitignore
├── dsi_core_tb.sv
├── dsi_lane_controller_tb.sv
├── dsi_tx_testbench.sv
├── fifo
│ ├── .gitignore
│ └── fifo_1024_32.v
├── lanes_ctrl_tb
│ ├── .gitignore
│ └── work
│ │ └── .gitignore
├── pixel_uploder_tb.sv
├── repacker_4_to_4_tb.sv
├── repacker_tb.sv
├── repacker_tb
│ ├── .gitignore
│ └── work
│ │ └── .gitignore
├── tb_prj
│ ├── .gitignore
│ └── work
│ │ └── .gitignore
├── test_tasks.vh
└── uplader_tb
│ ├── .gitignore
│ └── work
│ └── .gitignore
├── doc
├── DSI struct.graphml
├── TX_timings_regs.png
├── dsi display controller.graphml
└── sctruct.graphml
├── quartus_project
└── dsi_controller_test
│ ├── .gitignore
│ ├── .qsys_edit
│ ├── filters.xml
│ ├── preferences.xml
│ ├── top_level_system.xml
│ └── top_level_system_schematic.nlv
│ ├── avl_st_vid_2_st_hw.tcl
│ ├── avl_st_vid_2_st_hw.tcl~
│ ├── dsi_controller_test.qpf
│ ├── dsi_controller_test.qsf
│ ├── dsi_controller_test.qws
│ ├── dsi_tx_controller_hw.tcl
│ ├── dsi_tx_controller_hw.tcl~
│ ├── output_files
│ ├── dsi_controller_test.asm.rpt
│ ├── dsi_controller_test.done
│ ├── dsi_controller_test.eda.rpt
│ ├── dsi_controller_test.fit.rpt
│ ├── dsi_controller_test.fit.smsg
│ ├── dsi_controller_test.fit.summary
│ ├── dsi_controller_test.flow.rpt
│ ├── dsi_controller_test.jdi
│ ├── dsi_controller_test.map.rpt
│ ├── dsi_controller_test.map.smsg
│ ├── dsi_controller_test.map.summary
│ ├── dsi_controller_test.sld
│ ├── dsi_controller_test.sta.rpt
│ ├── dsi_controller_test.sta.summary
│ └── dsi_controller_test_time_limited.sof
│ ├── software
│ └── dsi_soft_test
│ │ ├── .cproject
│ │ ├── .project
│ │ ├── .settings
│ │ └── language.settings.xml
│ │ ├── Makefile
│ │ ├── create-this-app
│ │ ├── custom_periph.h
│ │ ├── dsi_soft_test.elf
│ │ ├── dsi_soft_test.map
│ │ ├── dsi_soft_test.objdump
│ │ ├── hello_world.c
│ │ ├── mem_init
│ │ ├── hdl_sim
│ │ │ ├── onchip_mem.dat
│ │ │ └── onchip_mem.sym
│ │ ├── meminit.qip
│ │ ├── meminit.spd
│ │ └── onchip_mem.hex
│ │ └── readme.txt
│ ├── test.bsf
│ ├── test.cmp
│ ├── test.qip
│ ├── test.sip
│ ├── test.spd
│ ├── test.v
│ ├── test
│ └── altera_gpio_lite.sv
│ ├── test_sim.f
│ ├── test_sim
│ ├── aldec
│ │ └── rivierapro_setup.tcl
│ ├── altera_gpio_lite
│ │ └── altera_gpio_lite.sv
│ ├── cadence
│ │ ├── cds.lib
│ │ ├── cds_libs
│ │ │ └── test.cds.lib
│ │ ├── hdl.var
│ │ └── ncsim_setup.sh
│ ├── mentor
│ │ └── msim_setup.tcl
│ ├── synopsys
│ │ ├── vcs
│ │ │ └── vcs_setup.sh
│ │ └── vcsmx
│ │ │ ├── synopsys_sim.setup
│ │ │ └── vcsmx_setup.sh
│ └── test.v
│ ├── top_level_system.qsys
│ ├── top_level_system.sopcinfo
│ ├── top_level_system
│ ├── testbench
│ │ ├── aldec
│ │ │ └── rivierapro_setup.tcl
│ │ ├── mentor
│ │ │ └── msim_setup.tcl
│ │ ├── synopsys
│ │ │ ├── vcs
│ │ │ │ └── vcs_setup.sh
│ │ │ └── vcsmx
│ │ │ │ ├── synopsys_sim.setup
│ │ │ │ └── vcsmx_setup.sh
│ │ ├── top_level_system.html
│ │ ├── top_level_system.ipx
│ │ ├── top_level_system_generation.rpt
│ │ ├── top_level_system_generation_previous.rpt
│ │ ├── top_level_system_tb.html
│ │ ├── top_level_system_tb.qsys
│ │ └── top_level_system_tb
│ │ │ └── simulation
│ │ │ └── top_level_system_tb.v
│ ├── top_level_system.bsf
│ ├── top_level_system.cmp
│ ├── top_level_system.html
│ ├── top_level_system.xml
│ ├── top_level_system_bb.v
│ ├── top_level_system_generation.rpt
│ ├── top_level_system_generation_previous.rpt
│ ├── top_level_system_inst.v
│ └── top_level_system_inst.vhd
│ ├── top_level_system_tb.csv
│ └── top_level_system_tb.spd
└── rtl
└── mipi_dsi
├── altera_specific
├── altera_generic_fifo.v
├── altera_gpio_lite.sv
├── avalon_mm_manager.v
├── bidir.v
├── gpio.v
├── lvds_soft.v
└── lvds_soft_0002.v
├── avalon_st_video_2_avalon_st.v
├── compile_module.tcl
├── crc_modules.v
├── dphy_tx_hs_lane.v
├── dphy_tx_lane_full.v
├── dphy_tx_lanes_controller.v
├── dsi_tx_packets_assembler.v
├── dsi_tx_packets_assembler_standard.v
├── dsi_tx_pixel_buffer.v
├── dsi_tx_regs.v
├── dsi_tx_top.v
├── dsi_tx_top.v.bak
├── fifo_to_lane_bridge.v
├── packets_assembler.v
├── pixel_uploader.v
├── sync_2ff.v
└── xilinx_specific
├── fifo_32x1024.v
├── fifo_8x32.v
├── fifo_9x32.v
├── fifo_generator_v9_3.v
├── lvds_soft_x.v
├── lvds_soft_x.v.bak
└── scfifo_34.v
/.gitmodules:
--------------------------------------------------------------------------------
1 | [submodule "rtl/processor_core/picorv32"]
2 | path = rtl/processor_core/picorv32
3 | url = https://github.com/cliffordwolf/picorv32.git
4 | [submodule "rtl/i2c_ip/verilog-i2c"]
5 | path = rtl/i2c_ip/verilog-i2c
6 | url = https://github.com/alexforencich/verilog-i2c.git
7 | [submodule "rtl/uart_ip/verilog-uart"]
8 | path = rtl/uart_ip/verilog-uart
9 | url = https://github.com/alexforencich/verilog-uart.git
10 |
--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # dsi_controller
2 | MIPI DSI controller
3 |
4 | This project implements a MIPI DSI (MIPI Display Serial Interface) Verilog core.
5 | Since the DSI specification is non-public and requires an NDA, the core was built
6 | using bits and pieces available throughout the Web: presentations, display controller/SOC
7 | datasheets, various application notes and Android kernel drivers. The author is not
8 | associated in any way with the MIPI Alliance.
9 |
--------------------------------------------------------------------------------
/bench/avalon_mm_manager_tb.sv:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ps
2 |
3 | module avalon_mm_manager_tb();
4 |
5 | bit clk;
6 | bit rst_n;
7 |
8 | logic [3:0] avl_mm_addr;
9 | logic avl_mm_read;
10 | logic avl_mm_readdatavalid;
11 | logic [31:0] avl_mm_readdata;
12 | logic [1:0] avl_mm_response;
13 | logic avl_mm_write;
14 | logic [31:0] avl_mm_writedata;
15 | logic [3:0] avl_mm_byteenable;
16 | logic avl_mm_waitrequest;
17 | logic [4 - 1 : 0] sys_read_req;
18 | logic sys_read_ready;
19 | logic [31:0] sys_read_data;
20 | logic [1:0] sys_read_resp;
21 | logic sys_write_ready;
22 | logic [4 - 1 : 0] sys_write_req;
23 | logic [31:0] sys_write_data;
24 | logic [3:0] sys_write_strb;
25 |
26 | avalon_mm_manager
27 | #(
28 | .REGISTERS_NUMBER(4),
29 | .ADDR_WIDTH (4),
30 | .MEMORY_MAP ({4'hc, 4'h8, 4'h4, 4'h0})
31 | )
32 | avalon_mm_manager_0 (
33 |
34 | .clk (clk ),
35 | .rst_n (rst_n ),
36 |
37 |
38 | .avl_mm_addr (avl_mm_addr ),
39 |
40 | .avl_mm_read (avl_mm_read ),
41 | .avl_mm_readdatavalid (avl_mm_readdatavalid ),
42 | .avl_mm_readdata (avl_mm_readdata ),
43 | .avl_mm_response (avl_mm_response ),
44 |
45 | .avl_mm_write (avl_mm_write ),
46 | .avl_mm_writedata (avl_mm_writedata ),
47 | .avl_mm_byteenable (avl_mm_byteenable ),
48 |
49 | .avl_mm_waitrequest (avl_mm_waitrequest ),
50 |
51 |
52 | .sys_read_req (sys_read_req ),
53 | .sys_read_ready (sys_read_ready ),
54 | .sys_read_data (sys_read_data ),
55 | .sys_read_resp (sys_read_resp ),
56 |
57 | .sys_write_ready (sys_write_ready ),
58 | .sys_write_req (sys_write_req ),
59 | .sys_write_strb (sys_write_strb ),
60 | .sys_write_data (sys_write_data )
61 |
62 | );
63 |
64 |
65 | logic [3:0] task_addr;
66 | logic [31:0] task_data_write;
67 | logic [31:0] task_data_read;
68 |
69 | initial
70 | begin
71 | clk = 0;
72 | forever
73 | #5 clk = ! clk;
74 | end
75 |
76 | initial
77 | begin
78 | rst_n = 0;
79 | repeat(5) @(posedge clk);
80 | rst_n = 1;
81 | end
82 |
83 | initial begin
84 | avl_mm_addr = 0;
85 | avl_mm_read = 0;
86 | avl_mm_write = 0;
87 | avl_mm_writedata = 0;
88 | avl_mm_byteenable = 0;
89 | sys_read_resp = 0;
90 | sys_write_ready = 1;
91 | sys_write_strb = 0;
92 | task_addr = 0;
93 | task_data_write = 0;
94 | task_data_read = 0;
95 |
96 |
97 | repeat(10) @(posedge clk);
98 |
99 | task_addr = $urandom_range(0,4'hffff_ffff) << 2;
100 | task_data_write = $urandom_range(0,32'hffff_ffff);
101 |
102 | avalon_write(task_addr, task_data_write);
103 |
104 | repeat(1) @(posedge clk);
105 |
106 | task_addr = $urandom_range(0,5'hffff_ffff);
107 |
108 | avalon_read(task_addr, task_data_read);
109 |
110 | end // initial
111 |
112 | always_ff @(posedge clk or negedge rst_n) begin
113 | if(~rst_n) begin
114 | sys_read_data <= 0;
115 | sys_read_ready <= 1'b0;
116 | end
117 | else if(sys_read_ready)
118 | begin
119 | sys_read_ready <= 0;
120 | sys_read_data <= 0;
121 | end
122 | else if(|sys_read_req) begin
123 | sys_read_ready <= 1'b1;
124 | sys_read_data = $urandom_range(0,32'hffff_ffff);
125 | end
126 | else
127 | sys_read_ready <= 1'b0;
128 | sys_read_data <= 0;
129 | end
130 |
131 |
132 | task avalon_write;
133 | input [31:0] addr;
134 | input [31:0] data;
135 |
136 | #0.01 avl_mm_addr = addr;
137 | avl_mm_write = 1'b1;
138 | avl_mm_writedata = data;
139 | avl_mm_byteenable = 4'hf;
140 |
141 | $display($time()," Current waitrequest %h", avl_mm_waitrequest);
142 | do
143 | repeat(1) @(posedge clk);
144 | while(avl_mm_waitrequest);
145 |
146 | avl_mm_addr = 'b0;
147 | avl_mm_write = 1'b0;
148 | avl_mm_writedata = 0;
149 | avl_mm_byteenable = 0;
150 |
151 | endtask : avalon_write
152 |
153 | task avalon_read;
154 | input [31:0] addr;
155 | output [31:0] data;
156 |
157 | #0.01 avl_mm_addr = addr;
158 | avl_mm_read = 1'b1;
159 |
160 | do
161 | repeat(1) @(posedge clk);
162 | while(avl_mm_waitrequest);
163 |
164 | avl_mm_addr = 'b0;
165 | avl_mm_read = 1'b0;
166 |
167 | if(avl_mm_readdatavalid && (avl_mm_response == 2'b00))
168 | data = avl_mm_readdata;
169 | else
170 | data = 0;
171 |
172 | endtask : avalon_read
173 |
174 | endmodule
--------------------------------------------------------------------------------
/bench/avl_mm_mgr_tb/.gitignore:
--------------------------------------------------------------------------------
1 | /avl_mm_mgr_tb.cr.mti
2 | /avl_mm_mgr_tb.mpf
3 | /vsim.wlf
4 |
--------------------------------------------------------------------------------
/bench/avl_mm_mgr_tb/work/.gitignore:
--------------------------------------------------------------------------------
1 | /_info
2 | /_lib.qdb
3 | /_lib1_8.qdb
4 | /_lib1_8.qpg
5 | /_lib1_8.qtl
6 | /_vmake
7 |
--------------------------------------------------------------------------------
/bench/core_tb/.gitignore:
--------------------------------------------------------------------------------
1 | /core_tb.cr.mti
2 | /core_tb.mpf
3 | /vsim.wlf
4 | /wlftj344xi
5 | /wlftkvi7qr
6 | /wlfti1eqqd
7 |
--------------------------------------------------------------------------------
/bench/core_tb/work/.gitignore:
--------------------------------------------------------------------------------
1 | /_info
2 | /_lib.qdb
3 | /_lib1_28.qdb
4 | /_lib1_28.qpg
5 | /_lib1_28.qtl
6 | /_vmake
7 | /_lib1_53.qdb
8 | /_lib1_53.qpg
9 | /_lib1_53.qtl
10 | /_lib1_67.qdb
11 | /_lib1_67.qpg
12 | /_lib1_67.qtl
13 | /_lib1_141.qdb
14 | /_lib1_141.qpg
15 | /_lib1_141.qtl
16 | /_lib1_144.qdb
17 | /_lib1_144.qpg
18 | /_lib1_144.qtl
19 |
--------------------------------------------------------------------------------
/bench/dsi_lane_controller_tb.sv:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ps
2 | module dsi_lane_controller_tb();
3 |
4 | bit clk_sys;
5 | bit clk_serdes;
6 | bit clk_serdes_clk;
7 | bit clk_latch;
8 | bit rst_n;
9 | logic [31:0] iface_write_data;
10 | logic [3:0] iface_write_strb;
11 | logic iface_write_rqst;
12 | logic iface_last_word;
13 | logic iface_data_rqst;
14 | logic [1:0] reg_lanes_number = 3;
15 | logic lines_enable;
16 | logic clock_enable;
17 | logic lines_ready;
18 | logic clock_ready;
19 | logic [31:0] hs_lane_output;
20 | logic [3:0] LP_p_output;
21 | logic [3:0] LP_n_output;
22 | logic [3:0] hs_lane_enable;
23 | logic [3:0] LP_enable;
24 | logic clock_LP_p_output;
25 | logic clock_LP_n_output;
26 | logic clock_hs_output;
27 |
28 | dsi_lanes_controller dsi_lanes_controller_0(
29 | .clk_sys (clk_sys ),
30 | .rst_n (rst_n ),
31 | .iface_write_data (iface_write_data ),
32 | .iface_write_strb (iface_write_strb ),
33 | .iface_write_rqst (iface_write_rqst ),
34 | .iface_last_word (iface_last_word ),
35 | .iface_data_rqst (iface_data_rqst ),
36 | .iface_lpm_en (1'b0 ),
37 | .reg_lanes_number (reg_lanes_number ),
38 | .lines_enable (lines_enable ),
39 | .clock_enable (clock_enable ),
40 | .lines_ready (lines_ready ),
41 | .clock_ready (clock_ready ),
42 | .hs_lane_output (hs_lane_output ),
43 | .LP_p_output (LP_p_output ),
44 | .LP_n_output (LP_n_output ),
45 | .clock_LP_p_output (clock_LP_p_output ),
46 | .clock_LP_n_output (clock_LP_n_output ),
47 | .hs_lane_enable (hs_lane_enable ),
48 | .LP_enable (LP_enable ),
49 | .clock_hs_output (clock_hs_output )
50 | );
51 |
52 | initial begin
53 | rst_n = 0;
54 | #100
55 | wait(10) @(posedge clk_sys)
56 | rst_n = 1;
57 | end
58 |
59 | initial
60 | begin
61 | #1.25;
62 | clk_sys = 1;
63 | forever #10 clk_sys = ~clk_sys;
64 | end
65 |
66 |
67 | /********************************************************************
68 | Generate data array
69 | ********************************************************************/
70 | integer data_size = 0;
71 | bit [31:0] data_array [0:64];
72 |
73 |
74 | initial begin
75 | iface_write_rqst = 0;
76 | iface_write_data = 0;
77 | iface_write_strb = 0;
78 | iface_last_word = 0;
79 | lines_enable = 0;
80 | clock_enable = 0;
81 |
82 | wait(rst_n);
83 | repeat(10) @(posedge clk_sys);
84 | lines_enable = 1;
85 | wait(lines_ready);
86 | repeat(10) @(posedge clk_sys);
87 |
88 | clock_enable = 1;
89 |
90 | wait(clock_ready);
91 |
92 | repeat(40) @(posedge clk_sys);
93 |
94 | write_data();
95 |
96 | repeat(2000) @(posedge clk_sys);
97 | clock_enable = 0;
98 | repeat(1000) @(posedge clk_sys);
99 | lines_enable = 0;
100 |
101 |
102 | end // initial
103 |
104 |
105 | task write_data;
106 |
107 | integer data_size;
108 | bit [31:0] data_array [0:64];
109 | integer total_cycles;
110 | integer data_left;
111 | integer i;
112 |
113 | data_size = 8;
114 | $display("Data size %d", data_size);
115 |
116 |
117 | for (i = 0; i < data_size; i++) begin
118 | data_array[i] = $urandom_range(0,32'hffff_ffff);
119 | end
120 |
121 | total_cycles = data_size/4 + (data_size%4 ? 1 : 0);
122 |
123 | $display("Total cycles %d", total_cycles);
124 |
125 | data_left = data_size;
126 | i = 0;
127 | #0.01 iface_write_data = data_array[i];
128 | iface_write_strb = 4'hf;
129 | iface_write_rqst = 1;
130 | if(i == total_cycles - 1)
131 | iface_last_word = 1;
132 | data_left = data_left >= 4 ? data_left - 4 : 0;
133 | i = i + 1;
134 |
135 | while(i < total_cycles) begin
136 | repeat(1) @(posedge clk_sys);
137 | iface_write_rqst = 0;
138 | if(iface_data_rqst)
139 | begin
140 | $display($time()," Current data %h", data_array[i]);
141 | $display($time()," Index %h", i);
142 | #0.01 iface_write_data = data_array[i];
143 | iface_write_strb = data_left >= 4 ? 4'hf : (4'hf >> (4 - data_left));
144 |
145 | if(i == total_cycles - 1)
146 | iface_last_word = 1;
147 | else
148 | iface_last_word = 0;
149 |
150 | i = i + 1;
151 | data_left = data_left >= 4 ? data_left - 4 : 0;
152 | $display($time()," Data left %h", data_left);
153 | end
154 | end
155 | repeat(1) @(posedge clk_sys);
156 |
157 | iface_write_rqst = 0;
158 | iface_last_word = 0;
159 | iface_write_strb = 0;
160 |
161 | endtask
162 |
163 | endmodule
164 |
165 |
--------------------------------------------------------------------------------
/bench/fifo/.gitignore:
--------------------------------------------------------------------------------
1 | /fifo_1024_32.qip
2 | /fifo_1024_32_bb.v
3 | /fifo_1024_32_inst.v
4 |
--------------------------------------------------------------------------------
/bench/fifo/fifo_1024_32.v:
--------------------------------------------------------------------------------
1 | // megafunction wizard: %FIFO%
2 | // GENERATION: STANDARD
3 | // VERSION: WM1.0
4 | // MODULE: dcfifo
5 |
6 | // ============================================================
7 | // File Name: fifo_1024_32.v
8 | // Megafunction Name(s):
9 | // dcfifo
10 | //
11 | // Simulation Library Files(s):
12 | // altera_mf
13 | // ============================================================
14 | // ************************************************************
15 | // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
16 | //
17 | // 18.0.0 Build 614 04/24/2018 SJ Lite Edition
18 | // ************************************************************
19 |
20 |
21 | //Copyright (C) 2018 Intel Corporation. All rights reserved.
22 | //Your use of Intel Corporation's design tools, logic functions
23 | //and other software and tools, and its AMPP partner logic
24 | //functions, and any output files from any of the foregoing
25 | //(including device programming or simulation files), and any
26 | //associated documentation or information are expressly subject
27 | //to the terms and conditions of the Intel Program License
28 | //Subscription Agreement, the Intel Quartus Prime License Agreement,
29 | //the Intel FPGA IP License Agreement, or other applicable license
30 | //agreement, including, without limitation, that your use is for
31 | //the sole purpose of programming logic devices manufactured by
32 | //Intel and sold by Intel or its authorized distributors. Please
33 | //refer to the applicable agreement for further details.
34 |
35 |
36 | // synopsys translate_off
37 | `timescale 1 ps / 1 ps
38 | // synopsys translate_on
39 | module fifo_1024_32 (
40 | data,
41 | rdclk,
42 | rdreq,
43 | wrclk,
44 | wrreq,
45 | q,
46 | rdempty,
47 | wrfull,
48 | wrusedw);
49 |
50 | input [31:0] data;
51 | input rdclk;
52 | input rdreq;
53 | input wrclk;
54 | input wrreq;
55 | output [31:0] q;
56 | output rdempty;
57 | output wrfull;
58 | output [9:0] wrusedw;
59 |
60 | wire [31:0] sub_wire0;
61 | wire sub_wire1;
62 | wire sub_wire2;
63 | wire [9:0] sub_wire3;
64 | wire [31:0] q = sub_wire0[31:0];
65 | wire rdempty = sub_wire1;
66 | wire wrfull = sub_wire2;
67 | wire [9:0] wrusedw = sub_wire3[9:0];
68 |
69 | dcfifo dcfifo_component (
70 | .data (data),
71 | .rdclk (rdclk),
72 | .rdreq (rdreq),
73 | .wrclk (wrclk),
74 | .wrreq (wrreq),
75 | .q (sub_wire0),
76 | .rdempty (sub_wire1),
77 | .wrfull (sub_wire2),
78 | .wrusedw (sub_wire3),
79 | .aclr (),
80 | .eccstatus (),
81 | .rdfull (),
82 | .rdusedw (),
83 | .wrempty ());
84 | defparam
85 | dcfifo_component.intended_device_family = "Cyclone V",
86 | dcfifo_component.lpm_numwords = 1024,
87 | dcfifo_component.lpm_showahead = "OFF",
88 | dcfifo_component.lpm_type = "dcfifo",
89 | dcfifo_component.lpm_width = 32,
90 | dcfifo_component.lpm_widthu = 10,
91 | dcfifo_component.overflow_checking = "ON",
92 | dcfifo_component.rdsync_delaypipe = 4,
93 | dcfifo_component.underflow_checking = "ON",
94 | dcfifo_component.use_eab = "ON",
95 | dcfifo_component.wrsync_delaypipe = 4;
96 |
97 |
98 | endmodule
99 |
100 | // ============================================================
101 | // CNX file retrieval info
102 | // ============================================================
103 | // Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
104 | // Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
105 | // Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
106 | // Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
107 | // Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
108 | // Retrieval info: PRIVATE: Clock NUMERIC "4"
109 | // Retrieval info: PRIVATE: Depth NUMERIC "1024"
110 | // Retrieval info: PRIVATE: Empty NUMERIC "1"
111 | // Retrieval info: PRIVATE: Full NUMERIC "1"
112 | // Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
113 | // Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
114 | // Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
115 | // Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
116 | // Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
117 | // Retrieval info: PRIVATE: Optimize NUMERIC "2"
118 | // Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
119 | // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
120 | // Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
121 | // Retrieval info: PRIVATE: UsedW NUMERIC "1"
122 | // Retrieval info: PRIVATE: Width NUMERIC "32"
123 | // Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
124 | // Retrieval info: PRIVATE: diff_widths NUMERIC "0"
125 | // Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
126 | // Retrieval info: PRIVATE: output_width NUMERIC "32"
127 | // Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
128 | // Retrieval info: PRIVATE: rsFull NUMERIC "0"
129 | // Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
130 | // Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
131 | // Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
132 | // Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
133 | // Retrieval info: PRIVATE: wsFull NUMERIC "1"
134 | // Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
135 | // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
136 | // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
137 | // Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
138 | // Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
139 | // Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
140 | // Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
141 | // Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
142 | // Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
143 | // Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
144 | // Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
145 | // Retrieval info: CONSTANT: USE_EAB STRING "ON"
146 | // Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
147 | // Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL "data[31..0]"
148 | // Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
149 | // Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
150 | // Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL "rdempty"
151 | // Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
152 | // Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
153 | // Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL "wrfull"
154 | // Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
155 | // Retrieval info: USED_PORT: wrusedw 0 0 10 0 OUTPUT NODEFVAL "wrusedw[9..0]"
156 | // Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
157 | // Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
158 | // Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
159 | // Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
160 | // Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
161 | // Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
162 | // Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
163 | // Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
164 | // Retrieval info: CONNECT: wrusedw 0 0 10 0 @wrusedw 0 0 10 0
165 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1024_32.v TRUE
166 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1024_32.inc FALSE
167 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1024_32.cmp FALSE
168 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1024_32.bsf FALSE
169 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1024_32_inst.v TRUE
170 | // Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1024_32_bb.v TRUE
171 | // Retrieval info: LIB_FILE: altera_mf
172 |
--------------------------------------------------------------------------------
/bench/lanes_ctrl_tb/.gitignore:
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1 | /lanes_controller_tb.cr.mti
2 | /lanes_controller_tb.mpf
3 | /vsim.wlf
4 | /wlfte7y0e3
5 |
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/bench/lanes_ctrl_tb/work/.gitignore:
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1 | /_info
2 | /_lib.qdb
3 | /_lib1_2.qdb
4 | /_lib1_2.qpg
5 | /_lib1_2.qtl
6 | /_vmake
7 | /_lib1_4.qdb
8 | /_lib1_4.qpg
9 | /_lib1_4.qtl
10 |
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/bench/pixel_uploder_tb.sv:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ps
2 | module pixel_uploader_tb();
3 |
4 | localparam DATA_SIZE = 27264;
5 |
6 | bit [31:0] memory_data [0:36352 - 1];
7 | bit [31:0] memory_data_remapped [0:DATA_SIZE-1];
8 |
9 | bit clk;
10 | bit clk_slow;
11 | bit rst_n;
12 | bit rst_n_slow;
13 |
14 | logic [255:0] alv_dataread;
15 | logic avl_read;
16 | logic avl_waitrequest;
17 | logic avl_datavalid;
18 | logic [31:0] avl_address;
19 |
20 | logic [31:0] fifo_data;
21 | logic fifo_read;
22 | logic fifo_empty;
23 | logic upl_enable;
24 |
25 | initial
26 | begin
27 | rst_n = 0;
28 | clk = 0;
29 | upl_enable = 0;
30 | repeat(30) @(posedge clk);
31 | rst_n = 1;
32 | repeat(30) @(posedge clk);
33 | upl_enable = 1;
34 |
35 | end
36 |
37 | initial
38 | begin
39 | clk_slow = 0;
40 | rst_n_slow = 0;
41 | repeat(30) @(posedge clk_slow);
42 | rst_n_slow = 1;
43 | end
44 |
45 | initial
46 | begin
47 | alv_dataread = 0;
48 | avl_waitrequest = 0;
49 | avl_datavalid = 0;
50 | fifo_read = 0;
51 |
52 | end
53 |
54 | initial
55 | begin
56 | for(int i = 0; i < 10000; i = i + 1)
57 | #1000000;
58 |
59 | $display("Test Done");
60 | $finish;
61 | end
62 |
63 | always
64 | #10 clk = !clk;
65 |
66 | always
67 | #17 clk_slow = !clk_slow;
68 |
69 | semaphore mem_read_sem = new(1);
70 | semaphore fifo_read_sem = new(1);
71 |
72 | int j;
73 | int k;
74 |
75 | initial
76 | begin
77 |
78 | for(int i = 0; i < 36352; i = i + 1)
79 | memory_data[i] = $urandom_range(0,32'hffffffff);
80 | j = 0;
81 | k = 0;
82 | for(int i = 0; i < 36352; i = i + 1)
83 | for(int h = 0; h < 3; h = h + 1)
84 | begin
85 | memory_data_remapped[j][k*8+:8] = memory_data[i][8*h+:8];
86 | k = k + 1;
87 | if(k == 4)
88 | begin
89 | k = 0;
90 | j = j + 1;
91 | end
92 | end
93 |
94 | $display("mm_rem size %d",j);
95 |
96 | end
97 |
98 | task automatic memory_read;
99 | logic data_ready;
100 |
101 | mem_read_sem.get(1);
102 |
103 | data_ready = $urandom_range(0,1);
104 |
105 | wait(avl_read);
106 |
107 | avl_waitrequest = avl_read & !data_ready;
108 | @(posedge clk);
109 | if(!data_ready)
110 | begin
111 | repeat($urandom_range(4,0)) @(posedge clk);
112 | #0.1 avl_waitrequest = 0;
113 | @(posedge clk);
114 | end
115 |
116 | #0.1 avl_datavalid = 1;
117 |
118 | for(int i = 0 ; i < 8; i = i + 1)
119 | alv_dataread[i*32+:32] = memory_data[avl_address + i];
120 |
121 | @(posedge clk);
122 |
123 | #0.1 avl_datavalid = 0;
124 | alv_dataread = 0;
125 |
126 | mem_read_sem.put(1);
127 |
128 | endtask : memory_read
129 |
130 | task fifo_read_task;
131 |
132 | logic [31:0] data_pointer;
133 | fifo_read_sem.get(1);
134 | data_pointer = 0;
135 |
136 | repeat(100) @(posedge clk_slow);
137 |
138 | for(int i = 0; i < 1136; i = i + 1)
139 | begin
140 | for(int j = 0; j < 24; j = j + 1)
141 | begin
142 | fifo_read = 1;
143 | if(fifo_empty)
144 | begin
145 | $display("FIFO empty!");
146 | $finish;
147 | end
148 |
149 | @(posedge clk_slow);
150 | wait(!clk_slow);
151 | if(memory_data_remapped[data_pointer] != fifo_data)
152 | begin
153 | $display("Wrong data at index %d", data_pointer);
154 | $display("Data read = %h, data should be = %h", fifo_data , memory_data_remapped[data_pointer]);
155 | $finish;
156 | end
157 | data_pointer = data_pointer + 1;
158 | end
159 |
160 | fifo_read = 0;
161 | repeat($urandom_range(20,10)) @(posedge clk_slow);
162 | end
163 | repeat(200) @(posedge clk_slow);
164 | fifo_read_sem.put(1);
165 |
166 | endtask : fifo_read_task
167 |
168 | initial
169 | begin
170 |
171 | wait(rst_n);
172 | forever
173 | begin
174 | fork
175 | memory_read;
176 | fifo_read_task;
177 | join_any
178 | end
179 | end
180 |
181 | logic pix_fifo_write;
182 | logic [31:0] pix_fifo_data;
183 | logic pix_fifo_full;
184 | logic [9:0] pix_fifo_usedw;
185 |
186 | pixel_uploader pixel_uploader_0(
187 |
188 | .clk (clk ),
189 | .rst_n (rst_n ),
190 |
191 | .avl_mm_addr (avl_address ),
192 | .avl_mm_read (avl_read ),
193 |
194 | .avl_mm_readdata (alv_dataread ),
195 | .avl_mm_readdatavalid (avl_datavalid ),
196 | .avl_mm_response (2'b0),
197 | .avl_mm_waitrequest (avl_waitrequest ),
198 |
199 | .pix_fifo_write (pix_fifo_write ),
200 | .pix_fifo_data (pix_fifo_data ),
201 |
202 | .pix_fifo_full (pix_fifo_full ),
203 | .pix_fifo_usedw (pix_fifo_usedw ),
204 |
205 | .enable (upl_enable ),
206 | .word_mode (1'b1 ), // 1 - word addressing, 0 - byte addressing
207 | .base_address (32'b0 ),
208 | .total_size (36352 ),
209 | .pix_fifo_threshold (1000 ),
210 | .transform_data (1 ), // 0 - write data from memory directly to fifo, 1 - transform 4 bytes to 4, removing empty 3rd byte in memory data
211 |
212 | .read_error_w (),
213 | .active ()
214 |
215 | );
216 |
217 | fifo_1024_32 fifo_1024_32_inst (
218 | .data ( pix_fifo_data ),
219 | .rdclk ( clk_slow ),
220 | .rdreq ( fifo_read ),
221 | .wrclk ( clk ),
222 | .wrreq ( pix_fifo_write ),
223 | .q ( fifo_data ),
224 | .rdempty ( fifo_empty ),
225 | .wrfull ( pix_fifo_full ),
226 | .wrusedw ( pix_fifo_usedw )
227 | );
228 |
229 | endmodule
230 |
--------------------------------------------------------------------------------
/bench/repacker_4_to_4_tb.sv:
--------------------------------------------------------------------------------
1 | module repacker_4_to_4_tb();
2 |
3 | bit clk;
4 | bit rst_n;
5 |
6 | logic [31:0] data_inp;
7 | logic [31:0] data_out;
8 |
9 | logic [3:0] input_strb;
10 | logic [3:0] last_data_strb;
11 |
12 | logic dchange_req;
13 | logic data_req;
14 |
15 | logic enable;
16 |
17 | repacker_4_to_4 inst0(
18 | .clk (clk ),
19 | .rst_n (rst_n ),
20 |
21 | .data_req (data_req ), // data request signal. Need to get new data on the next clock.
22 | .data_out (data_out ), // output data
23 | .last_data_strb (last_data_strb ), // strobes indicate last data bytes on each line
24 |
25 | .data_change_req (dchange_req ), // request data changing. new data on the next clock is needed
26 | .input_data (data_inp ), // input data
27 | .input_strb (input_strb ), // input strobes
28 |
29 | .enable (enable ) // enable repacker signal
30 | );
31 |
32 | initial
33 | begin
34 | clk = 0;
35 | rst_n = 0;
36 |
37 | repeat(10) @(posedge clk);
38 |
39 | rst_n = 1;
40 |
41 | end
42 |
43 | always
44 | #10 clk = ~clk;
45 |
46 | initial
47 | begin
48 | data_inp = 0;
49 | input_strb = 0;
50 | enable = 0;
51 | wait(rst_n);
52 |
53 | repeat(10) @(posedge clk);
54 |
55 | write_data();
56 |
57 | end
58 |
59 | initial
60 | begin
61 | data_req = 0;
62 |
63 | wait(rst_n);
64 | repeat(12) @(posedge clk);
65 |
66 | #0.01 data_req = 1;
67 | end
68 |
69 | task write_data;
70 |
71 | integer data_size = $urandom_range(0, 64);
72 | bit [31:0] data_array [15:0];
73 | integer i = 0;
74 |
75 | for (int i = 0; i < 16; i = i + 1) begin
76 | data_array[i] = $urandom_range(0, 32'hffff_ffff);
77 | end
78 |
79 | enable = 1;
80 | input_strb = 4'hf;
81 | data_inp = data_array[i];
82 | i = i + 1;
83 |
84 | while(i <= data_size / 4) begin
85 | repeat(1) @(posedge clk);
86 | if(dchange_req)
87 | begin
88 |
89 | #0.01 data_inp = data_array[i];
90 |
91 | if(data_size/4 == i)
92 | input_strb = 4'b1100;
93 | else if(data_size/4 - 1 == i)
94 | input_strb = 4'b0011;
95 | else input_strb = 4'hf;
96 | end
97 | i = i + 1;
98 | end
99 | repeat(1) @(posedge clk);
100 |
101 | #0.001 enable = 0;
102 | endtask : write_data
103 |
104 |
105 |
106 | endmodule // repacker_4_to_4
--------------------------------------------------------------------------------
/bench/repacker_tb.sv:
--------------------------------------------------------------------------------
1 | `timescale 1ns/1ps
2 |
3 | `define CLK_RST(clk, rst_n) posedge clk, negedge rst_n
4 | `define RST(rst_n) !rst_n
5 |
6 | module repacker_tb();
7 |
8 | bit clk;
9 | bit reset_n;
10 |
11 | logic [31:0] output_data;
12 | logic [31:0] input_data_1; // main data
13 | logic [31:0] input_data_2; // aditional data
14 | logic [31:0] temp_buffer;
15 | logic [2:0] offset_value;
16 | logic [5:0] data_size_left;
17 | logic ask_for_extra_data;
18 | logic read_data;
19 |
20 | assign ask_for_extra_data = (data_size_left + offset_value) < 4 ;
21 |
22 | always @(`CLK_RST(clk, reset_n))
23 | if(`RST(reset_n)) output_data <= 32'b0;
24 | else if(read_data)
25 | if(ask_for_extra_data) output_data <= (input_data_1 << (offset_value * 8)) | temp_buffer | (input_data_2 << ((data_size_left + offset_value) * 8));
26 | else output_data <= (input_data_1 << (offset_value * 8)) | temp_buffer;
27 |
28 | always @(`CLK_RST(clk, reset_n))
29 | if(`RST(reset_n)) temp_buffer <= 32'b0;
30 | else if(read_data)
31 | if(ask_for_extra_data) temp_buffer <= 32'b0 | (input_data_2 >> ((4 - data_size_left - offset_value) * 8));
32 | else temp_buffer <= (input_data_1 >> ((4 - offset_value) * 8));
33 |
34 | always @(`CLK_RST(clk, reset_n))
35 | if(`RST(reset_n)) offset_value <= 3'b0;
36 | else if(read_data)
37 | if(ask_for_extra_data) offset_value <= (data_size_left + offset_value);
38 | else if(data_size_left < 4) offset_value <= data_size_left + offset_value - 4;
39 |
40 | always
41 | #10 clk = !clk;
42 |
43 | initial
44 | begin
45 | reset_n = 0;
46 | repeat(10) @(posedge clk);
47 | reset_n = 1;
48 | end
49 |
50 | logic [31:0] temp_data;
51 | logic [31:0] mask;
52 |
53 | integer cnt;
54 |
55 | bit [31:0] memory_array [0:4095];
56 |
57 | initial
58 | begin
59 | for(int i = 0; i < 4096; i = i + 1)
60 | memory_array[i] = $urandom_range(0,32'hffff_ffff);
61 |
62 | cnt = 0;
63 | input_data_1 = memory_array[cnt];
64 | input_data_2 = memory_array[cnt];
65 | data_size_left = $urandom_range(4,5'h1f) + 4;
66 | temp_data = 0;
67 |
68 | wait(reset_n);
69 |
70 | forever
71 | begin
72 | repeat(1) @(posedge clk);
73 | if(read_data)
74 | begin
75 | cnt = cnt + 1;
76 |
77 | if(data_size_left < 4)
78 | data_size_left = $urandom_range(4,5'h1f);
79 | else
80 | data_size_left = (data_size_left - 4 == 0) ? $urandom_range(4,5'h1f) : data_size_left - 4;
81 |
82 | temp_data = $urandom_range(0,32'hffff_ffff); //memory_array[cnt];
83 | mask = 32'hffff_ffff >> (((data_size_left >= 4) ? 0 : (4 - data_size_left % 4) * 8) );
84 | input_data_1 = temp_data & mask;
85 | $display("Data %h", temp_data);
86 | $display("mask %h", mask);
87 | $display("Data left %d", data_size_left);
88 | $display("------------------");
89 |
90 | if(ask_for_extra_data)
91 | begin
92 | input_data_2 = $urandom_range(0,32'hffff_ffff); //memory_array[cnt];
93 | // cnt = cnt + 1;
94 | end
95 |
96 | end
97 |
98 |
99 | end
100 |
101 | end
102 |
103 | initial
104 | begin
105 | read_data = 0;
106 |
107 | wait (reset_n);
108 | repeat(10) @(posedge clk);
109 |
110 | forever
111 | begin
112 | repeat($urandom_range(1,3)) @(posedge clk);
113 | #0.1 read_data = !read_data;
114 | end
115 |
116 | end
117 |
118 |
119 | endmodule
120 |
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/bench/repacker_tb/.gitignore:
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1 | /repacker_tb.cr.mti
2 | /repacker_tb.mpf
3 | /vsim.wlf
4 |
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/bench/repacker_tb/work/.gitignore:
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1 | /_info
2 | /_lib.qdb
3 | /_lib1_1.qdb
4 | /_lib1_1.qpg
5 | /_lib1_1.qtl
6 | /_vmake
7 |
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/bench/tb_prj/.gitignore:
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1 | /altlvds.v
2 | /dsi_ctrl_tb.cr.mti
3 | /dsi_ctrl_tb.mpf
4 | /hs_buff.v
5 | /vsim.wlf
6 |
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/bench/tb_prj/work/.gitignore:
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1 | /_info
2 | /_lib.qdb
3 | /_lib1_3.qdb
4 | /_lib1_3.qpg
5 | /_lib1_3.qtl
6 | /_vmake
7 | /_lib1_107.qdb
8 | /_lib1_107.qpg
9 | /_lib1_107.qtl
10 | /_lib1_22.qdb
11 | /_lib1_22.qpg
12 | /_lib1_22.qtl
13 |
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/bench/uplader_tb/.gitignore:
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1 | /pixel_uploader_tb.cr.mti
2 | /pixel_uploader_tb.mpf
3 | /vsim.wlf
4 |
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/bench/uplader_tb/work/.gitignore:
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1 | /_info
2 | /_lib.qdb
3 | /_lib1_17.qdb
4 | /_lib1_17.qpg
5 | /_lib1_17.qtl
6 | /_vmake
7 |
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/doc/TX_timings_regs.png:
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https://raw.githubusercontent.com/skatanik/dsi_controller/d22ef722f3963aa4a4a88bfb10bca2e4d17ac13a/doc/TX_timings_regs.png
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/quartus_project/dsi_controller_test/.gitignore:
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1 | db/
2 | incremental_db/
3 | software/dsi_soft_test/obj/
4 | software/dsi_soft_test_bsp/
5 | top_level_system/testbench/cadence
6 | top_level_system/testbench/top_level_system_tb/simulation/submodules
7 | top_level_system/synthesis/
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/quartus_project/dsi_controller_test/.qsys_edit/filters.xml:
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/quartus_project/dsi_controller_test/.qsys_edit/preferences.xml:
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6 |
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10 |
12 |
13 |
14 |
15 |
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/quartus_project/dsi_controller_test/.qsys_edit/top_level_system_schematic.nlv:
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https://raw.githubusercontent.com/skatanik/dsi_controller/d22ef722f3963aa4a4a88bfb10bca2e4d17ac13a/quartus_project/dsi_controller_test/.qsys_edit/top_level_system_schematic.nlv
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/quartus_project/dsi_controller_test/avl_st_vid_2_st_hw.tcl:
--------------------------------------------------------------------------------
1 | # TCL File Generated by Component Editor 18.0
2 | # Sun Mar 24 21:16:52 MSK 2019
3 | # DO NOT MODIFY
4 |
5 |
6 | #
7 | # avl_st_vid_2_st "Avalon ST Video To Avalon ST" v1.0
8 | # 2019.03.24.21:16:52
9 | #
10 | #
11 |
12 | #
13 | # request TCL package from ACDS 16.1
14 | #
15 | package require -exact qsys 16.1
16 |
17 |
18 | #
19 | # module avl_st_vid_2_st
20 | #
21 | set_module_property DESCRIPTION ""
22 | set_module_property NAME avl_st_vid_2_st
23 | set_module_property VERSION 1.0
24 | set_module_property INTERNAL false
25 | set_module_property OPAQUE_ADDRESS_MAP true
26 | set_module_property AUTHOR ""
27 | set_module_property DISPLAY_NAME "Avalon ST Video To Avalon ST"
28 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
29 | set_module_property EDITABLE true
30 | set_module_property REPORT_TO_TALKBACK false
31 | set_module_property ALLOW_GREYBOX_GENERATION false
32 | set_module_property REPORT_HIERARCHY false
33 |
34 |
35 | #
36 | # file sets
37 | #
38 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
39 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL avl_st_video_2_avl_st_top
40 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
41 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
42 | add_fileset_file avalon_st_video_2_avalon_st.v VERILOG PATH ../../rtl/avalon_st_video_2_avalon_st.v TOP_LEVEL_FILE
43 |
44 | add_fileset SIM_VERILOG SIM_VERILOG "" ""
45 | set_fileset_property SIM_VERILOG TOP_LEVEL avl_st_video_2_avl_st_top
46 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
47 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
48 | add_fileset_file avalon_st_video_2_avalon_st.v VERILOG PATH ../../rtl/avalon_st_video_2_avalon_st.v
49 |
50 |
51 | #
52 | # parameters
53 | #
54 |
55 |
56 | #
57 | # display items
58 | #
59 |
60 |
61 | #
62 | # connection point clock
63 | #
64 | add_interface clock clock end
65 | set_interface_property clock clockRate 0
66 | set_interface_property clock ENABLED true
67 | set_interface_property clock EXPORT_OF ""
68 | set_interface_property clock PORT_NAME_MAP ""
69 | set_interface_property clock CMSIS_SVD_VARIABLES ""
70 | set_interface_property clock SVD_ADDRESS_GROUP ""
71 |
72 | add_interface_port clock clk clk Input 1
73 |
74 |
75 | #
76 | # connection point out_avl_st
77 | #
78 | add_interface out_avl_st avalon_streaming start
79 | set_interface_property out_avl_st associatedClock clock
80 | set_interface_property out_avl_st associatedReset reset_n
81 | set_interface_property out_avl_st dataBitsPerSymbol 8
82 | set_interface_property out_avl_st errorDescriptor ""
83 | set_interface_property out_avl_st firstSymbolInHighOrderBits true
84 | set_interface_property out_avl_st maxChannel 0
85 | set_interface_property out_avl_st readyLatency 0
86 | set_interface_property out_avl_st ENABLED true
87 | set_interface_property out_avl_st EXPORT_OF ""
88 | set_interface_property out_avl_st PORT_NAME_MAP ""
89 | set_interface_property out_avl_st CMSIS_SVD_VARIABLES ""
90 | set_interface_property out_avl_st SVD_ADDRESS_GROUP ""
91 |
92 | add_interface_port out_avl_st out_avl_st_endofpacket endofpacket Output 1
93 | add_interface_port out_avl_st out_avl_st_data data Output 32
94 | add_interface_port out_avl_st out_avl_st_ready ready Input 1
95 | add_interface_port out_avl_st out_avl_st_startofpacket startofpacket Output 1
96 | add_interface_port out_avl_st out_avl_st_valid valid Output 1
97 |
98 |
99 | #
100 | # connection point reset_n
101 | #
102 | add_interface reset_n reset end
103 | set_interface_property reset_n associatedClock clock
104 | set_interface_property reset_n synchronousEdges DEASSERT
105 | set_interface_property reset_n ENABLED true
106 | set_interface_property reset_n EXPORT_OF ""
107 | set_interface_property reset_n PORT_NAME_MAP ""
108 | set_interface_property reset_n CMSIS_SVD_VARIABLES ""
109 | set_interface_property reset_n SVD_ADDRESS_GROUP ""
110 |
111 | add_interface_port reset_n rst_n reset_n Input 1
112 |
113 |
114 | #
115 | # connection point in_avl_st
116 | #
117 | add_interface in_avl_st avalon_streaming end
118 | set_interface_property in_avl_st associatedClock clock
119 | set_interface_property in_avl_st associatedReset reset_n
120 | set_interface_property in_avl_st dataBitsPerSymbol 8
121 | set_interface_property in_avl_st errorDescriptor ""
122 | set_interface_property in_avl_st firstSymbolInHighOrderBits true
123 | set_interface_property in_avl_st maxChannel 0
124 | set_interface_property in_avl_st readyLatency 0
125 | set_interface_property in_avl_st ENABLED true
126 | set_interface_property in_avl_st EXPORT_OF ""
127 | set_interface_property in_avl_st PORT_NAME_MAP ""
128 | set_interface_property in_avl_st CMSIS_SVD_VARIABLES ""
129 | set_interface_property in_avl_st SVD_ADDRESS_GROUP ""
130 |
131 | add_interface_port in_avl_st in_avl_st_data data Input 24
132 | add_interface_port in_avl_st in_avl_st_valid valid Input 1
133 | add_interface_port in_avl_st in_avl_st_endofpacket endofpacket Input 1
134 | add_interface_port in_avl_st in_avl_st_startofpacket startofpacket Input 1
135 | add_interface_port in_avl_st in_avl_st_ready ready Output 1
136 |
137 |
--------------------------------------------------------------------------------
/quartus_project/dsi_controller_test/avl_st_vid_2_st_hw.tcl~:
--------------------------------------------------------------------------------
1 | # TCL File Generated by Component Editor 18.0
2 | # Sun Mar 24 21:09:46 MSK 2019
3 | # DO NOT MODIFY
4 |
5 |
6 | #
7 | # avl_st_vid_2_st "Avalon ST Video To Avalon ST" v1.0
8 | # 2019.03.24.21:09:46
9 | #
10 | #
11 |
12 | #
13 | # request TCL package from ACDS 16.1
14 | #
15 | package require -exact qsys 16.1
16 |
17 |
18 | #
19 | # module avl_st_vid_2_st
20 | #
21 | set_module_property DESCRIPTION ""
22 | set_module_property NAME avl_st_vid_2_st
23 | set_module_property VERSION 1.0
24 | set_module_property INTERNAL false
25 | set_module_property OPAQUE_ADDRESS_MAP true
26 | set_module_property AUTHOR ""
27 | set_module_property DISPLAY_NAME "Avalon ST Video To Avalon ST"
28 | set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
29 | set_module_property EDITABLE true
30 | set_module_property REPORT_TO_TALKBACK false
31 | set_module_property ALLOW_GREYBOX_GENERATION false
32 | set_module_property REPORT_HIERARCHY false
33 |
34 |
35 | #
36 | # file sets
37 | #
38 | add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
39 | set_fileset_property QUARTUS_SYNTH TOP_LEVEL avalon_st_video_2_avalon_st
40 | set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
41 | set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
42 | add_fileset_file avalon_st_video_2_avalon_st.v VERILOG PATH ../../rtl/avalon_st_video_2_avalon_st.v TOP_LEVEL_FILE
43 |
44 | add_fileset SIM_VERILOG SIM_VERILOG "" ""
45 | set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
46 | set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
47 | add_fileset_file avalon_st_video_2_avalon_st.v VERILOG PATH ../../rtl/avalon_st_video_2_avalon_st.v
48 |
49 |
50 | #
51 | # parameters
52 | #
53 |
54 |
55 | #
56 | # display items
57 | #
58 |
59 |
60 | #
61 | # connection point clock
62 | #
63 | add_interface clock clock end
64 | set_interface_property clock clockRate 0
65 | set_interface_property clock ENABLED true
66 | set_interface_property clock EXPORT_OF ""
67 | set_interface_property clock PORT_NAME_MAP ""
68 | set_interface_property clock CMSIS_SVD_VARIABLES ""
69 | set_interface_property clock SVD_ADDRESS_GROUP ""
70 |
71 | add_interface_port clock clk clk Input 1
72 |
73 |
74 | #
75 | # connection point out_avl_st
76 | #
77 | add_interface out_avl_st avalon_streaming start
78 | set_interface_property out_avl_st associatedClock clock
79 | set_interface_property out_avl_st associatedReset reset_n
80 | set_interface_property out_avl_st dataBitsPerSymbol 8
81 | set_interface_property out_avl_st errorDescriptor ""
82 | set_interface_property out_avl_st firstSymbolInHighOrderBits true
83 | set_interface_property out_avl_st maxChannel 0
84 | set_interface_property out_avl_st readyLatency 0
85 | set_interface_property out_avl_st ENABLED true
86 | set_interface_property out_avl_st EXPORT_OF ""
87 | set_interface_property out_avl_st PORT_NAME_MAP ""
88 | set_interface_property out_avl_st CMSIS_SVD_VARIABLES ""
89 | set_interface_property out_avl_st SVD_ADDRESS_GROUP ""
90 |
91 | add_interface_port out_avl_st out_avl_st_endofpacket endofpacket Output 1
92 | add_interface_port out_avl_st out_avl_st_data data Output 32
93 | add_interface_port out_avl_st out_avl_st_ready ready Input 1
94 | add_interface_port out_avl_st out_avl_st_startofpacket startofpacket Output 1
95 | add_interface_port out_avl_st out_avl_st_valid valid Output 1
96 |
97 |
98 | #
99 | # connection point reset_n
100 | #
101 | add_interface reset_n reset end
102 | set_interface_property reset_n associatedClock clock
103 | set_interface_property reset_n synchronousEdges DEASSERT
104 | set_interface_property reset_n ENABLED true
105 | set_interface_property reset_n EXPORT_OF ""
106 | set_interface_property reset_n PORT_NAME_MAP ""
107 | set_interface_property reset_n CMSIS_SVD_VARIABLES ""
108 | set_interface_property reset_n SVD_ADDRESS_GROUP ""
109 |
110 | add_interface_port reset_n rst_n reset_n Input 1
111 |
112 |
113 | #
114 | # connection point in_avl_st
115 | #
116 | add_interface in_avl_st avalon_streaming end
117 | set_interface_property in_avl_st associatedClock clock
118 | set_interface_property in_avl_st associatedReset reset_n
119 | set_interface_property in_avl_st dataBitsPerSymbol 8
120 | set_interface_property in_avl_st errorDescriptor ""
121 | set_interface_property in_avl_st firstSymbolInHighOrderBits true
122 | set_interface_property in_avl_st maxChannel 0
123 | set_interface_property in_avl_st readyLatency 0
124 | set_interface_property in_avl_st ENABLED true
125 | set_interface_property in_avl_st EXPORT_OF ""
126 | set_interface_property in_avl_st PORT_NAME_MAP ""
127 | set_interface_property in_avl_st CMSIS_SVD_VARIABLES ""
128 | set_interface_property in_avl_st SVD_ADDRESS_GROUP ""
129 |
130 | add_interface_port in_avl_st in_avl_st_data data Input 24
131 | add_interface_port in_avl_st in_avl_st_valid valid Input 1
132 | add_interface_port in_avl_st in_avl_st_endofpacket endofpacket Input 1
133 | add_interface_port in_avl_st in_avl_st_startofpacket startofpacket Input 1
134 | add_interface_port in_avl_st in_avl_st_ready ready Output 1
135 |
136 |
--------------------------------------------------------------------------------
/quartus_project/dsi_controller_test/dsi_controller_test.qpf:
--------------------------------------------------------------------------------
1 | # -------------------------------------------------------------------------- #
2 | #
3 | # Copyright (C) 2018 Intel Corporation. All rights reserved.
4 | # Your use of Intel Corporation's design tools, logic functions
5 | # and other software and tools, and its AMPP partner logic
6 | # functions, and any output files from any of the foregoing
7 | # (including device programming or simulation files), and any
8 | # associated documentation or information are expressly subject
9 | # to the terms and conditions of the Intel Program License
10 | # Subscription Agreement, the Intel Quartus Prime License Agreement,
11 | # the Intel FPGA IP License Agreement, or other applicable license
12 | # agreement, including, without limitation, that your use is for
13 | # the sole purpose of programming logic devices manufactured by
14 | # Intel and sold by Intel or its authorized distributors. Please
15 | # refer to the applicable agreement for further details.
16 | #
17 | # -------------------------------------------------------------------------- #
18 | #
19 | # Quartus Prime
20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
21 | # Date created = 18:38:56 March 24, 2019
22 | #
23 | # -------------------------------------------------------------------------- #
24 |
25 | QUARTUS_VERSION = "18.0"
26 | DATE = "18:38:56 March 24, 2019"
27 |
28 | # Revisions
29 |
30 | PROJECT_REVISION = "dsi_controller_test"
31 |
--------------------------------------------------------------------------------
/quartus_project/dsi_controller_test/dsi_controller_test.qsf:
--------------------------------------------------------------------------------
1 | # -------------------------------------------------------------------------- #
2 | #
3 | # Copyright (C) 2018 Intel Corporation. All rights reserved.
4 | # Your use of Intel Corporation's design tools, logic functions
5 | # and other software and tools, and its AMPP partner logic
6 | # functions, and any output files from any of the foregoing
7 | # (including device programming or simulation files), and any
8 | # associated documentation or information are expressly subject
9 | # to the terms and conditions of the Intel Program License
10 | # Subscription Agreement, the Intel Quartus Prime License Agreement,
11 | # the Intel FPGA IP License Agreement, or other applicable license
12 | # agreement, including, without limitation, that your use is for
13 | # the sole purpose of programming logic devices manufactured by
14 | # Intel and sold by Intel or its authorized distributors. Please
15 | # refer to the applicable agreement for further details.
16 | #
17 | # -------------------------------------------------------------------------- #
18 | #
19 | # Quartus Prime
20 | # Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
21 | # Date created = 18:38:56 March 24, 2019
22 | #
23 | # -------------------------------------------------------------------------- #
24 | #
25 | # Notes:
26 | #
27 | # 1) The default values for assignments are stored in the file:
28 | # dsi_controller_test_assignment_defaults.qdf
29 | # If this file doesn't exist, see file:
30 | # assignment_defaults.qdf
31 | #
32 | # 2) Altera recommends that you do not modify this file. This
33 | # file is updated automatically by the Quartus Prime software
34 | # and any changes you make may be lost or overwritten.
35 | #
36 | # -------------------------------------------------------------------------- #
37 |
38 |
39 | set_global_assignment -name FAMILY "MAX 10"
40 | set_global_assignment -name DEVICE 10M50DAF484C6GES
41 | set_global_assignment -name TOP_LEVEL_ENTITY top_level_system
42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.0.0
43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:38:56 MARCH 24, 2019"
44 | set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition"
45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
48 | set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
49 | set_global_assignment -name DEVICE_FILTER_PIN_COUNT 484
50 | set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
51 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
52 | set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Precision Synthesis"
53 | set_global_assignment -name EDA_LMF_FILE mentor.lmf -section_id eda_design_synthesis
54 | set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis
55 | set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
56 | set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
57 | set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
58 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
59 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
60 | set_global_assignment -name QIP_FILE top_level_system/synthesis/top_level_system.qip
61 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
62 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
63 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
64 | set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
65 | set_global_assignment -name VERILOG_MACRO "MIPI_TX_TRI_STATED_HS_OUTPUTS="
66 | set_global_assignment -name VERILOG_MACRO "MAX_10="
67 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_clk_hs_out_n
68 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_clk_hs_out_p
69 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[0]
70 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[1]
71 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[2]
72 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[3]
73 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[0]
74 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[1]
75 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[2]
76 | set_instance_assignment -name IO_STANDARD "DIFFERENTIAL 1.8-V HSTL CLASS I" -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[3]
77 | set_location_assignment PIN_N1 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[0]
78 | set_location_assignment PIN_T2 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[1]
79 | set_location_assignment PIN_V1 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[2]
80 | set_location_assignment PIN_W2 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_p[3]
81 | set_location_assignment PIN_R2 -to dsi_tx_controller_0_dsi_interface_dphy_clk_hs_out_p
82 | set_location_assignment PIN_P1 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[0]
83 | set_location_assignment PIN_T1 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[1]
84 | set_location_assignment PIN_U1 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[2]
85 | set_location_assignment PIN_W1 -to dsi_tx_controller_0_dsi_interface_dphy_data_hs_out_n[3]
86 | set_location_assignment PIN_R1 -to dsi_tx_controller_0_dsi_interface_dphy_clk_hs_out_n
87 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
--------------------------------------------------------------------------------
/quartus_project/dsi_controller_test/dsi_controller_test.qws:
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https://raw.githubusercontent.com/skatanik/dsi_controller/d22ef722f3963aa4a4a88bfb10bca2e4d17ac13a/quartus_project/dsi_controller_test/dsi_controller_test.qws
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.asm.rpt:
--------------------------------------------------------------------------------
1 | Assembler report for dsi_controller_test
2 | Sun Mar 31 21:20:26 2019
3 | Quartus Prime Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
4 |
5 |
6 | ---------------------
7 | ; Table of Contents ;
8 | ---------------------
9 | 1. Legal Notice
10 | 2. Assembler Summary
11 | 3. Assembler Settings
12 | 4. Assembler Encrypted IP Cores Summary
13 | 5. Assembler Generated Files
14 | 6. Assembler Device Options: D:/git/dsi_controller/quartus_project/dsi_controller_test/output_files/dsi_controller_test_time_limited.sof
15 | 7. Assembler Messages
16 |
17 |
18 |
19 | ----------------
20 | ; Legal Notice ;
21 | ----------------
22 | Copyright (C) 2018 Intel Corporation. All rights reserved.
23 | Your use of Intel Corporation's design tools, logic functions
24 | and other software and tools, and its AMPP partner logic
25 | functions, and any output files from any of the foregoing
26 | (including device programming or simulation files), and any
27 | associated documentation or information are expressly subject
28 | to the terms and conditions of the Intel Program License
29 | Subscription Agreement, the Intel Quartus Prime License Agreement,
30 | the Intel FPGA IP License Agreement, or other applicable license
31 | agreement, including, without limitation, that your use is for
32 | the sole purpose of programming logic devices manufactured by
33 | Intel and sold by Intel or its authorized distributors. Please
34 | refer to the applicable agreement for further details.
35 |
36 |
37 |
38 | +---------------------------------------------------------------+
39 | ; Assembler Summary ;
40 | +-----------------------+---------------------------------------+
41 | ; Assembler Status ; Successful - Sun Mar 31 21:20:26 2019 ;
42 | ; Revision Name ; dsi_controller_test ;
43 | ; Top-level Entity Name ; top_level_system ;
44 | ; Family ; MAX 10 ;
45 | ; Device ; 10M50DAF484C6GES ;
46 | +-----------------------+---------------------------------------+
47 |
48 |
49 | +----------------------------------+
50 | ; Assembler Settings ;
51 | +--------+---------+---------------+
52 | ; Option ; Setting ; Default Value ;
53 | +--------+---------+---------------+
54 |
55 |
56 | +-----------------------------------------------------------------------+
57 | ; Assembler Encrypted IP Cores Summary ;
58 | +--------+----------------------------------------------+---------------+
59 | ; Vendor ; IP Core Name ; License Type ;
60 | +--------+----------------------------------------------+---------------+
61 | ; Altera ; Nios II Processor (6AF7 00A2) ; OpenCore Plus ;
62 | ; Altera ; Video and Image Processing Suite (6AF7 00EE) ; OpenCore Plus ;
63 | ; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ;
64 | ; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ;
65 | ; Altera ; Unknown (6AF7 FFFF) ; Licensed ;
66 | +--------+----------------------------------------------+---------------+
67 |
68 |
69 | +-------------------------------------------------------------------------------------------------------------+
70 | ; Assembler Generated Files ;
71 | +-------------------------------------------------------------------------------------------------------------+
72 | ; File Name ;
73 | +-------------------------------------------------------------------------------------------------------------+
74 | ; D:/git/dsi_controller/quartus_project/dsi_controller_test/output_files/dsi_controller_test_time_limited.sof ;
75 | +-------------------------------------------------------------------------------------------------------------+
76 |
77 |
78 | +---------------------------------------------------------------------------------------------------------------------------------------+
79 | ; Assembler Device Options: D:/git/dsi_controller/quartus_project/dsi_controller_test/output_files/dsi_controller_test_time_limited.sof ;
80 | +----------------+----------------------------------------------------------------------------------------------------------------------+
81 | ; Option ; Setting ;
82 | +----------------+----------------------------------------------------------------------------------------------------------------------+
83 | ; JTAG usercode ; 0x007295E5 ;
84 | ; Checksum ; 0x007295E5 ;
85 | +----------------+----------------------------------------------------------------------------------------------------------------------+
86 |
87 |
88 | +--------------------+
89 | ; Assembler Messages ;
90 | +--------------------+
91 | Info: *******************************************************************
92 | Info: Running Quartus Prime Assembler
93 | Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition
94 | Info: Processing started: Sun Mar 31 21:20:22 2019
95 | Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off dsi_controller_test -c dsi_controller_test
96 | Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
97 | Info (115031): Writing out detailed assembly data for power analysis
98 | Info (115030): Assembler is generating device programming files
99 | Info (115017): Design contains a time-limited core -- only a single, time-limited programming file can be generated
100 | Info: Quartus Prime Assembler was successful. 0 errors, 1 warning
101 | Info: Peak virtual memory: 4722 megabytes
102 | Info: Processing ended: Sun Mar 31 21:20:26 2019
103 | Info: Elapsed time: 00:00:04
104 | Info: Total CPU time (on all processors): 00:00:04
105 |
106 |
107 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.done:
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1 | Sun Mar 31 21:17:57 2019
2 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.fit.rpt:
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https://raw.githubusercontent.com/skatanik/dsi_controller/d22ef722f3963aa4a4a88bfb10bca2e4d17ac13a/quartus_project/dsi_controller_test/output_files/dsi_controller_test.fit.rpt
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.fit.smsg:
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1 | Extra Info (176273): Performing register packing on registers with non-logic cell location assignments
2 | Extra Info (176274): Completed register packing on registers with non-logic cell location assignments
3 | Extra Info (176236): Started Fast Input/Output/OE register processing
4 | Extra Info (176237): Finished Fast Input/Output/OE register processing
5 | Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density
6 | Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks
7 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.fit.summary:
--------------------------------------------------------------------------------
1 | Fitter Status : Failed - Sun Mar 31 22:49:49 2019
2 | Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Lite Edition
3 | Revision Name : dsi_controller_test
4 | Top-level Entity Name : top_level_system
5 | Family : MAX 10
6 | Device : 10M50DAF484C6GES
7 | Timing Models : Preliminary
8 | Total logic elements : 7,633 / 49,760 ( 15 % )
9 | Total combinational functions : 5,973 / 49,760 ( 12 % )
10 | Dedicated logic registers : 4,270 / 49,760 ( 9 % )
11 | Total registers : 4280
12 | Total pins : 23 / 360 ( 6 % )
13 | Total virtual pins : 0
14 | Total memory bits : 1,146,408 / 1,677,312 ( 68 % )
15 | Embedded Multiplier 9-bit elements : 6 / 288 ( 2 % )
16 | Total PLLs : 1 / 4 ( 25 % )
17 | UFM blocks : 0 / 1 ( 0 % )
18 | ADC blocks : 0 / 2 ( 0 % )
19 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.map.smsg:
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1 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router_006.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router_006.sv Line: 48
2 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router_006.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router_006.sv Line: 49
3 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router_002.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router_002.sv Line: 48
4 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router_002.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router_002.sv Line: 49
5 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router_001.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router_001.sv Line: 48
6 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router_001.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router_001.sv Line: 49
7 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router.sv(48): object "DEFAULT_WR_CHANNEL" differs only in case from object "default_wr_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router.sv Line: 48
8 | Info (10281): Verilog HDL Declaration information at top_level_system_mm_interconnect_0_router.sv(49): object "DEFAULT_RD_CHANNEL" differs only in case from object "default_rd_channel" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/top_level_system_mm_interconnect_0_router.sv Line: 49
9 | Warning (10268): Verilog HDL information at dphy_tx_lanes_controller.sv(210): always construct contains both blocking and non-blocking assignments File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dphy_tx_lanes_controller.sv Line: 210
10 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(70): object "STATE_SEND_LP_CMD" differs only in case from object "state_send_lp_cmd" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 70
11 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(71): object "STATE_SEND_VSS_VSA" differs only in case from object "state_send_vss_vsa" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 71
12 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(72): object "STATE_WAIT_H_BLANK_VSS_VSA" differs only in case from object "state_wait_h_blank_vss_vsa" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 72
13 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(73): object "STATE_SEND_HSS_VSA" differs only in case from object "state_send_hss_vsa" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 73
14 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(74): object "STATE_WAIT_H_BLANK_VSA" differs only in case from object "state_wait_h_blank_vsa" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 74
15 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(75): object "STATE_SEND_HSS_VBP" differs only in case from object "state_send_hss_vbp" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 75
16 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(76): object "STATE_WAIT_H_BLANK_VBP" differs only in case from object "state_wait_h_blank_vbp" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 76
17 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(77): object "STATE_SEND_HSS_ACT" differs only in case from object "state_send_hss_act" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 77
18 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(78): object "STATE_WAIT_H_BLANK_ACT_HBP" differs only in case from object "state_wait_h_blank_act_hbp" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 78
19 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(79): object "STATE_SEND_DATA_HEADER" differs only in case from object "state_send_data_header" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 79
20 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(80): object "STATE_SEND_DATA" differs only in case from object "state_send_data" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 80
21 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(81): object "STATE_SEND_DATA_CRC" differs only in case from object "state_send_data_crc" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 81
22 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(82): object "STATE_WAIT_H_BLANK_ACT_HFP" differs only in case from object "state_wait_h_blank_act_hfp" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 82
23 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(83): object "STATE_SEND_HSS_VFP" differs only in case from object "state_send_hss_vfp" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 83
24 | Info (10281): Verilog HDL Declaration information at dsi_tx_packets_assembler.v(84): object "STATE_WAIT_H_BLANK_VFP" differs only in case from object "state_wait_h_blank_vfp" in the same scope File: D:/git/dsi_controller/quartus_project/dsi_controller_test/top_level_system/synthesis/submodules/dsi_tx_packets_assembler.v Line: 84
25 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.map.summary:
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1 | Analysis & Synthesis Status : Successful - Sun Mar 31 22:49:39 2019
2 | Quartus Prime Version : 18.0.0 Build 614 04/24/2018 SJ Lite Edition
3 | Revision Name : dsi_controller_test
4 | Top-level Entity Name : top_level_system
5 | Family : MAX 10
6 | Total logic elements : 7,633
7 | Total combinational functions : 5,973
8 | Dedicated logic registers : 4,270
9 | Total registers : 4280
10 | Total pins : 23
11 | Total virtual pins : 0
12 | Total memory bits : 1,146,408
13 | Embedded Multiplier 9-bit elements : 6
14 | Total PLLs : 1
15 | UFM blocks : 0
16 | ADC blocks : 0
17 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.sld:
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test.sta.summary:
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1 | ------------------------------------------------------------
2 | Timing Analyzer Summary
3 | ------------------------------------------------------------
4 |
5 | Type : Slow 1200mV 85C Model Setup 'altera_reserved_tck'
6 | Slack : 45.147
7 | TNS : 0.000
8 |
9 | Type : Slow 1200mV 85C Model Hold 'altera_reserved_tck'
10 | Slack : 0.323
11 | TNS : 0.000
12 |
13 | Type : Slow 1200mV 85C Model Recovery 'altera_reserved_tck'
14 | Slack : 48.151
15 | TNS : 0.000
16 |
17 | Type : Slow 1200mV 85C Model Removal 'altera_reserved_tck'
18 | Slack : 1.058
19 | TNS : 0.000
20 |
21 | Type : Slow 1200mV 85C Model Minimum Pulse Width 'altera_reserved_tck'
22 | Slack : 49.577
23 | TNS : 0.000
24 |
25 | Type : Slow 1200mV 0C Model Setup 'altera_reserved_tck'
26 | Slack : 45.620
27 | TNS : 0.000
28 |
29 | Type : Slow 1200mV 0C Model Hold 'altera_reserved_tck'
30 | Slack : 0.294
31 | TNS : 0.000
32 |
33 | Type : Slow 1200mV 0C Model Recovery 'altera_reserved_tck'
34 | Slack : 48.310
35 | TNS : 0.000
36 |
37 | Type : Slow 1200mV 0C Model Removal 'altera_reserved_tck'
38 | Slack : 0.986
39 | TNS : 0.000
40 |
41 | Type : Slow 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
42 | Slack : 49.604
43 | TNS : 0.000
44 |
45 | Type : Fast 1200mV 0C Model Setup 'altera_reserved_tck'
46 | Slack : 47.892
47 | TNS : 0.000
48 |
49 | Type : Fast 1200mV 0C Model Hold 'altera_reserved_tck'
50 | Slack : 0.147
51 | TNS : 0.000
52 |
53 | Type : Fast 1200mV 0C Model Recovery 'altera_reserved_tck'
54 | Slack : 49.333
55 | TNS : 0.000
56 |
57 | Type : Fast 1200mV 0C Model Removal 'altera_reserved_tck'
58 | Slack : 0.482
59 | TNS : 0.000
60 |
61 | Type : Fast 1200mV 0C Model Minimum Pulse Width 'altera_reserved_tck'
62 | Slack : 49.425
63 | TNS : 0.000
64 |
65 | ------------------------------------------------------------
66 |
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/quartus_project/dsi_controller_test/output_files/dsi_controller_test_time_limited.sof:
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https://raw.githubusercontent.com/skatanik/dsi_controller/d22ef722f3963aa4a4a88bfb10bca2e4d17ac13a/quartus_project/dsi_controller_test/output_files/dsi_controller_test_time_limited.sof
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/quartus_project/dsi_controller_test/software/dsi_soft_test/.cproject:
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56 |
57 |
58 | make
59 |
60 | mem_init_install
61 | true
62 | false
63 | false
64 |
65 |
66 | make
67 |
68 | mem_init_generate
69 | true
70 | false
71 | false
72 |
73 |
74 | make
75 |
76 | help
77 | true
78 | false
79 | false
80 |
81 |
82 |
83 |
84 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/.project:
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2 |
3 | dsi_soft_test
4 |
5 |
6 |
7 |
8 |
9 | com.altera.sbtgui.project.makefileBuilder
10 |
11 |
12 |
13 |
14 | com.altera.sbtgui.project.makefileBuilder
15 |
16 |
17 |
18 |
19 | org.eclipse.cdt.managedbuilder.core.genmakebuilder
20 | clean,full,incremental,
21 |
22 |
23 |
24 |
25 | org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder
26 | full,incremental,
27 |
28 |
29 |
30 |
31 |
32 | org.eclipse.cdt.core.cnature
33 | org.eclipse.cdt.managedbuilder.core.managedBuildNature
34 | org.eclipse.cdt.managedbuilder.core.ScannerConfigNature
35 | org.eclipse.cdt.core.ccnature
36 | com.altera.sbtgui.project.SBTGUINature
37 | com.altera.sbtgui.project.SBTGUIAppNature
38 | com.altera.sbtgui.project.SBTGUIManagedNature
39 |
40 |
41 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/.settings/language.settings.xml:
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/quartus_project/dsi_controller_test/software/dsi_soft_test/create-this-app:
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1 | #!/bin/bash
2 | #
3 | # This script creates the hello_world application in this directory.
4 |
5 |
6 | BSP_DIR=../dsi_soft_test_bsp
7 | QUARTUS_PROJECT_DIR=../../
8 | NIOS2_APP_GEN_ARGS="--elf-name dsi_soft_test.elf --set OBJDUMP_INCLUDE_SOURCE 1 --src-files hello_world.c"
9 |
10 |
11 | # First, check to see if $SOPC_KIT_NIOS2 environmental variable is set.
12 | # This variable is required for the command line tools to execute correctly.
13 | if [ -z "${SOPC_KIT_NIOS2}" ]
14 | then
15 | echo Required \$SOPC_KIT_NIOS2 Environmental Variable is not set!
16 | exit 1
17 | fi
18 |
19 |
20 | # Also make sure that the APP has not been created already. Check for
21 | # existence of Makefile in the app directory
22 | if [ -f ./Makefile ]
23 | then
24 | echo Application has already been created! Delete Makefile if you want to create a new application makefile
25 | exit 1
26 | fi
27 |
28 |
29 | # We are selecting hal_default bsp because it supports this application.
30 | # Check to see if the hal_default has already been generated by checking for
31 | # existence of the public.mk file. If not, we need to run
32 | # create-this-bsp file to generate the bsp.
33 | if [ ! -f ${BSP_DIR}/public.mk ]; then
34 | # Since BSP doesn't exist, create the BSP
35 | # Pass any command line arguments passed to this script to the BSP.
36 | pushd ${BSP_DIR} >> /dev/null
37 | ./create-this-bsp "$@" || {
38 | echo "create-this-bsp failed"
39 | exit 1
40 | }
41 | popd >> /dev/null
42 | fi
43 |
44 |
45 | # Don't run make if create-this-app script is called with --no-make arg
46 | SKIP_MAKE=
47 | while [ $# -gt 0 ]
48 | do
49 | case "$1" in
50 | --no-make)
51 | SKIP_MAKE=1
52 | ;;
53 | esac
54 | shift
55 | done
56 |
57 |
58 | # Now we also need to go copy the sources for this application to the
59 | # local directory.
60 | find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name '*.c' -or -name '*.h' -or -name 'hostfs*' | xargs -i cp -L {} ./ || {
61 | echo "failed during copying example source files"
62 | exit 1
63 | }
64 |
65 | find "${SOPC_KIT_NIOS2}/examples/software/hello_world/" -name 'readme.txt' -or -name 'Readme.txt' | xargs -i cp -L {} ./ || {
66 | echo "failed copying readme file"
67 | }
68 |
69 | if [ -d "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" ]
70 | then
71 | cp -RL "${SOPC_KIT_NIOS2}/examples/software/hello_world/system" . || {
72 | echo "failed during copying project support files"
73 | exit 1
74 | }
75 | fi
76 |
77 | chmod -R +w . || {
78 | echo "failed during changing file permissions"
79 | exit 1
80 | }
81 |
82 | cmd="nios2-app-generate-makefile --bsp-dir ${BSP_DIR} --set QUARTUS_PROJECT_DIR=${QUARTUS_PROJECT_DIR} ${NIOS2_APP_GEN_ARGS}"
83 |
84 | echo "create-this-app: Running \"${cmd}\""
85 | $cmd || {
86 | echo "nios2-app-generate-makefile failed"
87 | exit 1
88 | }
89 |
90 | if [ -z "$SKIP_MAKE" ]; then
91 | cmd="make"
92 |
93 | echo "create-this-app: Running \"$cmd\""
94 | $cmd || {
95 | echo "make failed"
96 | exit 1
97 | }
98 |
99 | echo
100 | echo "To download and run the application:"
101 | echo " 1. Make sure the board is connected to the system."
102 | echo " 2. Run 'nios2-configure-sof ' to configure the FPGA with the hardware design."
103 | echo " 3. If you have a stdio device, run 'nios2-terminal' in a different shell."
104 | echo " 4. Run 'make download-elf' from the application directory."
105 | echo
106 | echo "To debug the application:"
107 | echo " Import the project into Nios II Software Build Tools for Eclipse."
108 | echo " Refer to Nios II Software Build Tools for Eclipse Documentation for more information."
109 | echo
110 | echo -e ""
111 | fi
112 |
113 |
114 | exit 0
115 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/custom_periph.h:
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1 | #ifndef PERIPH_INC_CUSTOM_PERIPH_H_
2 | #define PERIPH_INC_CUSTOM_PERIPH_H_
3 |
4 | #include
5 | /* MIPI DSI TX controller regs */
6 |
7 | #define MIPI_DSI_TX_CTRL_BASE 0
8 | #define MIPI_DSI_TX_CTRL_ASSEMBLER_ENABLE_OFST (0)
9 | #define MIPI_DSI_TX_CTRL_ASSEMBLER_ENABLE_MASK ((1) << MIPI_DSI_TX_CTRL_ASSEMBLER_ENABLE_OFST)
10 | #define MIPI_DSI_TX_CTRL_LANES_ENABLE_OFST (1)
11 | #define MIPI_DSI_TX_CTRL_LANES_ENABLE_MASK ((1) << MIPI_DSI_TX_CTRL_LANES_ENABLE_OFST)
12 | #define MIPI_DSI_TX_CTRL_CLK_ENABLE_OFST (2)
13 | #define MIPI_DSI_TX_CTRL_CLK_ENABLE_MASK ((1) << MIPI_DSI_TX_CTRL_CLK_ENABLE_OFST)
14 | #define MIPI_DSI_TX_CTRL_SEND_CMD_OFST (3)
15 | #define MIPI_DSI_TX_CTRL_SEND_CMD_MASK ((1) << MIPI_DSI_TX_CTRL_SEND_CMD_OFST)
16 | #define MIPI_DSI_TX_CTRL_LANES_NUMBER_OFST (8)
17 | #define MIPI_DSI_TX_CTRL_LANES_NUMBER_MASK ((3) << MIPI_DSI_TX_CTRL_LANES_NUMBER_OFST)
18 | #define MIPI_DSI_TX_CTRL_LANES_NUMBER_MASK_0 ((0) << MIPI_DSI_TX_CTRL_LANES_NUMBER_OFST)
19 | #define MIPI_DSI_TX_CTRL_LANES_NUMBER_MASK_1 ((1) << MIPI_DSI_TX_CTRL_LANES_NUMBER_OFST)
20 | #define MIPI_DSI_TX_CTRL_LANES_NUMBER_MASK_2 ((2) << MIPI_DSI_TX_CTRL_LANES_NUMBER_OFST)
21 | #define MIPI_DSI_TX_CTRL_LANES_NUMBER_MASK_3 ((3) << MIPI_DSI_TX_CTRL_LANES_NUMBER_OFST)
22 |
23 | #define MIPI_DSI_TX_ISR_BASE 4
24 | #define MIPI_DSI_TX_ISR_PIX_BUFF_UNDERFLOW_OFST (0)
25 | #define MIPI_DSI_TX_ISR_PIX_BUFF_UNDERFLOW_MASK ((1) << MIPI_DSI_TX_ISR_PIX_BUFF_UNDERFLOW_OFST)
26 | #define MIPI_DSI_TX_ISR_LANES_READY_OFST (1)
27 | #define MIPI_DSI_TX_ISR_LANES_READY_MASK ((1) << MIPI_DSI_TX_ISR_LANES_READY_OFST)
28 | #define MIPI_DSI_TX_ISR_CLK_READY_OFST (2)
29 | #define MIPI_DSI_TX_ISR_CLK_READY_MASK ((1) << MIPI_DSI_TX_ISR_CLK_READY_OFST)
30 | #define MIPI_DSI_TX_ISR_LANES_ACTINE_OFST (3)
31 | #define MIPI_DSI_TX_ISR_LANES_ACTINE_MASK ((1) << MIPI_DSI_TX_ISR_LANES_ACTINE_OFST)
32 | #define MIPI_DSI_TX_ISR_LANES_UNACTINE_OFST (4)
33 | #define MIPI_DSI_TX_ISR_LANES_UNACTINE_MASK ((1) << MIPI_DSI_TX_ISR_LANES_UNACTINE_OFST)
34 |
35 | #define MIPI_DSI_TX_IER_BASE 8
36 | #define MIPI_DSI_TX_IER_PIX_BUFF_UNDERFLOW_OFST (0)
37 | #define MIPI_DSI_TX_IER_PIX_BUFF_UNDERFLOW_MASK ((1) << MIPI_DSI_TX_IER_PIX_BUFF_UNDERFLOW_OFST)
38 | #define MIPI_DSI_TX_IER_LANES_READY_OFST (1)
39 | #define MIPI_DSI_TX_IER_LANES_READY_MASK ((1) << MIPI_DSI_TX_IER_LANES_READY_OFST)
40 | #define MIPI_DSI_TX_IER_CLK_READY_OFST (2)
41 | #define MIPI_DSI_TX_IER_CLK_READY_MASK ((1) << MIPI_DSI_TX_IER_CLK_READY_OFST)
42 |
43 | #define MIPI_DSI_TX_TR1_BASE 12
44 | #define MIPI_DSI_TX_TR1_TLPX_TIMEOUT_OFST (16)
45 | #define MIPI_DSI_TX_TR1_TLPX_TIMEOUT_MASK ((0xff) << MIPI_DSI_TX_TR1_TLPX_TIMEOUT_OFST)
46 | #define MIPI_DSI_TX_TR1_HS_PREPARE_TIMEOUT_OFST (8)
47 | #define MIPI_DSI_TX_TR1_HS_PREPARE_TIMEOUT_MASK ((0xff) << MIPI_DSI_TX_TR1_HS_PREPARE_TIMEOUT_OFST)
48 | #define MIPI_DSI_TX_TR1_HS_EXIT_TIMEOUT_OFST (0)
49 | #define MIPI_DSI_TX_TR1_HS_EXIT_TIMEOUT_MASK ((0xff) << MIPI_DSI_TX_TR1_HS_EXIT_TIMEOUT_OFST)
50 |
51 | #define MIPI_DSI_TX_TR2_BASE 16
52 | #define MIPI_DSI_TX_TR2_HS_GO_TIMEOUT_OFST (8)
53 | #define MIPI_DSI_TX_TR2_HS_GO_TIMEOUT_MASK ((0xff) << MIPI_DSI_TX_TR2_HS_GO_TIMEOUT_OFST)
54 | #define MIPI_DSI_TX_TR2_HS_TRAIL_TIMEOUT_OFST (0)
55 | #define MIPI_DSI_TX_TR2_HS_TRAIL_TIMEOUT_MASK ((0xff) << MIPI_DSI_TX_TR2_HS_TRAIL_TIMEOUT_OFST)
56 |
57 | #define MIPI_DSI_TX_CMD_BASE 20
58 | #define MIPI_DSI_TX_CMD_REG_OFST (0)
59 | #define MIPI_DSI_TX_CMD_REG_MASK ((0xff) << MIPI_DSI_TX_CMD_REG_OFST)
60 |
61 | #endif
62 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/dsi_soft_test.elf:
--------------------------------------------------------------------------------
https://raw.githubusercontent.com/skatanik/dsi_controller/d22ef722f3963aa4a4a88bfb10bca2e4d17ac13a/quartus_project/dsi_controller_test/software/dsi_soft_test/dsi_soft_test.elf
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/quartus_project/dsi_controller_test/software/dsi_soft_test/hello_world.c:
--------------------------------------------------------------------------------
1 | /*
2 | * "Hello World" example.
3 | *
4 | * This example prints 'Hello from Nios II' to the STDOUT stream. It runs on
5 | * the Nios II 'standard', 'full_featured', 'fast', and 'low_cost' example
6 | * designs. It runs with or without the MicroC/OS-II RTOS and requires a STDOUT
7 | * device in your system's hardware.
8 | * The memory footprint of this hosted application is ~69 kbytes by default
9 | * using the standard reference design.
10 | *
11 | * For a reduced footprint version of this template, and an explanation of how
12 | * to reduce the memory footprint for a given application, see the
13 | * "small_hello_world" template.
14 | *
15 | */
16 |
17 | #include
18 | #include
19 | #include "system.h"
20 | #include
21 | #include "custom_periph.h"
22 |
23 | int main()
24 | {
25 | // MIPI DSI TX INIT
26 | // disable packet dropping
27 | printf("\n[Soft init] TX init\n\n");
28 | uint32_t settings_word = MIPI_DSI_TX_CTRL_LANES_ENABLE_MASK | MIPI_DSI_TX_CTRL_LANES_NUMBER_MASK_3;
29 |
30 | // enable lanes
31 | IOWR(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_CTRL_BASE, settings_word);
32 |
33 | while(!(IORD(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_ISR_BASE) & MIPI_DSI_TX_ISR_LANES_READY_MASK))
34 | {}
35 | printf("\n[Soft init] Lanes ready!\n\n");
36 |
37 | settings_word |= MIPI_DSI_TX_CTRL_CLK_ENABLE_MASK;
38 |
39 | // enable lck lanes
40 | IOWR(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_CTRL_BASE, settings_word);
41 |
42 | while(!(IORD(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_ISR_BASE) & MIPI_DSI_TX_ISR_CLK_READY_MASK))
43 | {}
44 |
45 | printf("\n[Soft init] Clock ready!\n\n");
46 |
47 | settings_word = IORD(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_CTRL_BASE);
48 |
49 | IOWR(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_CMD_BASE, 0x551234);
50 |
51 | settings_word |= MIPI_DSI_TX_CTRL_SEND_CMD_MASK;
52 |
53 | IOWR(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_CTRL_BASE, settings_word);
54 |
55 | while(!(IORD(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_ISR_BASE) & MIPI_DSI_TX_ISR_LANES_UNACTINE_MASK))
56 | {}
57 |
58 | IOWR(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_ISR_BASE, 0);
59 |
60 | printf("\n[Soft init] CMD sent!\n\n");
61 |
62 | // enable controller
63 | settings_word |= MIPI_DSI_TX_CTRL_ASSEMBLER_ENABLE_MASK;
64 | settings_word &= ~MIPI_DSI_TX_CTRL_SEND_CMD_MASK;
65 |
66 | IOWR(DSI_TX_CONTROLLER_0_BASE, MIPI_DSI_TX_CTRL_BASE, settings_word);
67 |
68 | printf("\n[Soft init] Controller enabled!\n\n");
69 |
70 | for(int i = 0; i < 200; i++){}
71 |
72 | IOWR(ALT_VIP_CL_TPG_0_BASE, 0, 0x1);
73 |
74 | printf("\n[Soft init] TPG enabled;\n\n");
75 |
76 | return 0;
77 | }
78 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/mem_init/hdl_sim/onchip_mem.sym:
--------------------------------------------------------------------------------
1 | 00020000 A __alt_mem_onchip_memory2_0
2 | 00020000 T __reset
3 | 00020020 A __flash_exceptions_start
4 | 00020020 A __ram_exceptions_start
5 | 00020020 T alt_exception
6 | 00020020 T alt_irq_entry
7 | 000200fc T alt_irq_handler
8 | 000201d0 T alt_instruction_exception_entry
9 | 00020244 A __ram_exceptions_end
10 | 00020244 T _start
11 | 0002028c t alt_after_alt_main
12 | 00020290 T main
13 | 00020428 T _puts_r
14 | 000204e8 T puts
15 | 000204fc T strlen
16 | 00020594 t __fp_unlock
17 | 0002059c T _cleanup_r
18 | 000205a8 t __sinit.part.1
19 | 00020744 t __fp_lock
20 | 0002074c T __sfmoreglue
21 | 000207b4 T __sfp
22 | 000208cc T _cleanup
23 | 000208e4 T __sinit
24 | 000208f4 T __sfp_lock_acquire
25 | 000208f8 T __sfp_lock_release
26 | 000208fc T __sinit_lock_acquire
27 | 00020900 T __sinit_lock_release
28 | 00020904 T __fp_lock_all
29 | 0002091c T __fp_unlock_all
30 | 00020934 T __sfvwrite_r
31 | 00020df0 T _fwalk
32 | 00020eb4 T _fwalk_reent
33 | 00020f78 T _malloc_r
34 | 00021784 T memchr
35 | 00021868 T memcpy
36 | 000219b0 T memmove
37 | 00021b0c T memset
38 | 00021c34 T _realloc_r
39 | 00022198 T _sbrk_r
40 | 000221ec T __sread
41 | 00022240 T __seofread
42 | 00022248 T __swrite
43 | 000222c4 T __sseek
44 | 00022320 T __sclose
45 | 00022328 T _write_r
46 | 00022388 T __swsetup_r
47 | 000224dc T _close_r
48 | 00022530 T _fclose_r
49 | 00022620 T fclose
50 | 00022634 T __sflush_r
51 | 00022850 T _fflush_r
52 | 000228ac T fflush
53 | 000228dc T _malloc_trim_r
54 | 00022a00 T _free_r
55 | 00022d10 T _lseek_r
56 | 00022d70 T __smakebuf_r
57 | 00022f2c T _read_r
58 | 00022f8c T _fstat_r
59 | 00022fe8 T _isatty_r
60 | 0002303c T __divsi3
61 | 000230c0 T __modsi3
62 | 00023134 T __udivsi3
63 | 00023198 T __umodsi3
64 | 000231f0 t alt_get_errno
65 | 0002322c T close
66 | 000232fc t alt_dev_null_write
67 | 00023328 t alt_get_errno
68 | 00023364 T fstat
69 | 00023414 t alt_get_errno
70 | 00023450 T isatty
71 | 000234f4 t alt_load_section
72 | 0002355c T alt_load
73 | 000235e0 t alt_get_errno
74 | 0002361c T lseek
75 | 000236f0 T alt_main
76 | 0002376c T __malloc_lock
77 | 00023790 T __malloc_unlock
78 | 000237b4 t alt_get_errno
79 | 000237f0 T read
80 | 000238ec T alt_release_fd
81 | 00023950 T sbrk
82 | 00023a00 t alt_get_errno
83 | 00023a3c T write
84 | 00023b34 t alt_dev_reg
85 | 00023b68 T alt_irq_init
86 | 00023ba0 T alt_sys_init
87 | 00023bec T altera_avalon_jtag_uart_read_fd
88 | 00023c4c T altera_avalon_jtag_uart_write_fd
89 | 00023cac T altera_avalon_jtag_uart_close_fd
90 | 00023cfc T altera_avalon_jtag_uart_ioctl_fd
91 | 00023d50 T altera_avalon_jtag_uart_init
92 | 00023e10 t altera_avalon_jtag_uart_irq
93 | 0002401c t altera_avalon_jtag_uart_timeout
94 | 000240bc T altera_avalon_jtag_uart_close
95 | 00024124 T altera_avalon_jtag_uart_ioctl
96 | 00024214 T altera_avalon_jtag_uart_read
97 | 00024430 T altera_avalon_jtag_uart_write
98 | 00024654 T alt_alarm_start
99 | 00024780 T alt_dcache_flush_all
100 | 000247c8 t alt_get_errno
101 | 00024804 T alt_dev_llist_insert
102 | 000248a8 T _do_ctors
103 | 00024908 T _do_dtors
104 | 00024968 T alt_icache_flush_all
105 | 0002499c T alt_ic_isr_register
106 | 000249ec T alt_ic_irq_enable
107 | 00024a74 T alt_ic_irq_disable
108 | 00024b00 T alt_ic_irq_enabled
109 | 00024b4c T alt_iic_isr_register
110 | 00024c3c t alt_open_fd
111 | 00024d00 T alt_io_redirect
112 | 00024d7c t alt_get_errno
113 | 00024db8 t alt_file_locked
114 | 00024e7c T open
115 | 00024fd0 T alt_alarm_stop
116 | 0002506c T alt_tick
117 | 00025174 T altera_nios2_gen2_irq_init
118 | 00025198 T alt_find_dev
119 | 00025228 T alt_find_file
120 | 00025330 T alt_get_fd
121 | 000253d4 T alt_icache_flush
122 | 00025464 T alt_exception_cause_generated_bad_addr
123 | 00025500 T atexit
124 | 00025514 T exit
125 | 0002554c T memcmp
126 | 000255c8 T __register_exitproc
127 | 000256e0 T __call_exitprocs
128 | 00025860 T _exit
129 | 00025894 A __CTOR_END__
130 | 00025894 A __CTOR_LIST__
131 | 00025894 A __DTOR_END__
132 | 00025894 A __DTOR_LIST__
133 | 00025894 A __flash_rodata_start
134 | 00025894 A __ram_rodata_start
135 | 00025978 A __ram_rodata_end
136 | 00025978 A __ram_rwdata_start
137 | 00025978 g impure_data
138 | 00025d9c G __malloc_av_
139 | 000261a4 G alt_dev_null
140 | 000261cc G alt_fd_list
141 | 0002634c g jtag_uart_0
142 | 000273ac G _global_impure_ptr
143 | 000273b0 G _impure_ptr
144 | 000273b4 G __malloc_sbrk_base
145 | 000273b8 G __malloc_trim_threshold
146 | 000273bc G alt_fs_list
147 | 000273c4 G alt_dev_list
148 | 000273cc G alt_max_fd
149 | 000273d0 G alt_errno
150 | 000273d4 g heap_end
151 | 000273d8 G alt_priority_mask
152 | 000273dc G alt_alarm_list
153 | 000273e4 A __flash_rwdata_start
154 | 000273e4 A __ram_rwdata_end
155 | 000273e4 A _edata
156 | 00028e50 A __bss_start
157 | 00028e50 B __malloc_max_total_mem
158 | 00028e54 B __malloc_max_sbrked_mem
159 | 00028e58 B __malloc_top_pad
160 | 00028e5c B errno
161 | 00028e60 B alt_argc
162 | 00028e64 B alt_argv
163 | 00028e68 B alt_envp
164 | 00028e6c B alt_irq_active
165 | 00028e70 B _alt_tick_rate
166 | 00028e74 B _alt_nticks
167 | 00028e78 B alt_instruction_exception_handler
168 | 00028e7c B __malloc_current_mallinfo
169 | 00028ea4 B alt_irq
170 | 00028fa4 A __alt_heap_start
171 | 00028fa4 A __alt_stack_base
172 | 00028fa4 A __bss_end
173 | 00028fa4 A _end
174 | 00028fa4 A end
175 | 0002f3ac A _gp
176 | 00040000 A __alt_data_end
177 | 00040000 A __alt_heap_limit
178 | 00040000 A __alt_stack_pointer
179 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/mem_init/meminit.qip:
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1 | set_global_assignment -name SEARCH_PATH $::quartus(qip_path)
2 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/mem_init/meminit.spd:
--------------------------------------------------------------------------------
1 |
2 |
3 |
4 |
5 |
6 |
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/quartus_project/dsi_controller_test/software/dsi_soft_test/readme.txt:
--------------------------------------------------------------------------------
1 | Readme - Hello World Software Example
2 |
3 | DESCRIPTION:
4 | Simple program that prints "Hello from Nios II"
5 |
6 | The memory footprint of this hosted application is intended to be small (under 100 kbytes) by default
7 | using a standard reference deisgn.
8 |
9 | For an even smaller, reduced footprint version of this template, and an explanation of how
10 | to reduce the memory footprint for a given application, see the
11 | "small_hello_world" template.
12 |
13 |
14 | PERIPHERALS USED:
15 | This example exercises the following peripherals:
16 | - STDOUT device (UART or JTAG UART)
17 |
18 | SOFTWARE SOURCE FILES:
19 | This example includes the following software source files:
20 | - hello_world.c: Everyone needs a Hello World program, right?
21 |
22 | BOARD/HOST REQUIREMENTS:
23 | This example requires only a JTAG connection with a Nios Development board. If
24 | the host communication settings are changed from JTAG UART (default) to use a
25 | conventional UART, a serial cable between board DB-9 connector and the host is
26 | required.
27 |
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/quartus_project/dsi_controller_test/test.bsf:
--------------------------------------------------------------------------------
1 | /*
2 | WARNING: Do NOT edit the input and output ports in this file in a text
3 | editor if you plan to continue editing the block that represents it in
4 | the Block Editor! File corruption is VERY likely to occur.
5 | */
6 | /*
7 | Copyright (C) 2018 Intel Corporation. All rights reserved.
8 | Your use of Intel Corporation's design tools, logic functions
9 | and other software and tools, and its AMPP partner logic
10 | functions, and any output files from any of the foregoing
11 | (including device programming or simulation files), and any
12 | associated documentation or information are expressly subject
13 | to the terms and conditions of the Intel Program License
14 | Subscription Agreement, the Intel Quartus Prime License Agreement,
15 | the Intel FPGA IP License Agreement, or other applicable license
16 | agreement, including, without limitation, that your use is for
17 | the sole purpose of programming logic devices manufactured by
18 | Intel and sold by Intel or its authorized distributors. Please
19 | refer to the applicable agreement for further details.
20 | */
21 | (header "symbol" (version "1.1"))
22 | (symbol
23 | (rect 0 0 208 144)
24 | (text "test" (rect 94 -1 108 11)(font "Arial" (font_size 10)))
25 | (text "inst" (rect 8 128 20 140)(font "Arial" ))
26 | (port
27 | (pt 0 72)
28 | (input)
29 | (text "din[3..0]" (rect 0 0 30 12)(font "Arial" (font_size 8)))
30 | (text "din[3..0]" (rect 4 61 58 72)(font "Arial" (font_size 8)))
31 | (line (pt 0 72)(pt 48 72)(line_width 3))
32 | )
33 | (port
34 | (pt 0 112)
35 | (input)
36 | (text "oe[3..0]" (rect 0 0 29 12)(font "Arial" (font_size 8)))
37 | (text "oe[3..0]" (rect 4 101 52 112)(font "Arial" (font_size 8)))
38 | (line (pt 0 112)(pt 48 112)(line_width 3))
39 | )
40 | (port
41 | (pt 208 72)
42 | (output)
43 | (text "pad_out[3..0]" (rect 0 0 51 12)(font "Arial" (font_size 8)))
44 | (text "pad_out[3..0]" (rect 142 61 220 72)(font "Arial" (font_size 8)))
45 | (line (pt 208 72)(pt 128 72)(line_width 3))
46 | )
47 | (drawing
48 | (text "din" (rect 32 43 82 99)(font "Arial" (color 128 0 0)(font_size 9)))
49 | (text "export" (rect 53 67 142 144)(font "Arial" (color 0 0 0)))
50 | (text "pad_out" (rect 129 43 300 99)(font "Arial" (color 128 0 0)(font_size 9)))
51 | (text "export" (rect 98 67 232 144)(font "Arial" (color 0 0 0)))
52 | (text "oe" (rect 35 83 82 179)(font "Arial" (color 128 0 0)(font_size 9)))
53 | (text "export" (rect 53 107 142 224)(font "Arial" (color 0 0 0)))
54 | (text " altera_gpio_lite " (rect 140 128 388 266)(font "Arial" ))
55 | (line (pt 48 32)(pt 128 32)(line_width 1))
56 | (line (pt 128 32)(pt 128 128)(line_width 1))
57 | (line (pt 48 128)(pt 128 128)(line_width 1))
58 | (line (pt 48 32)(pt 48 128)(line_width 1))
59 | (line (pt 49 52)(pt 49 76)(line_width 1))
60 | (line (pt 50 52)(pt 50 76)(line_width 1))
61 | (line (pt 127 52)(pt 127 76)(line_width 1))
62 | (line (pt 126 52)(pt 126 76)(line_width 1))
63 | (line (pt 49 92)(pt 49 116)(line_width 1))
64 | (line (pt 50 92)(pt 50 116)(line_width 1))
65 | (line (pt 0 0)(pt 208 0)(line_width 1))
66 | (line (pt 208 0)(pt 208 144)(line_width 1))
67 | (line (pt 0 144)(pt 208 144)(line_width 1))
68 | (line (pt 0 0)(pt 0 144)(line_width 1))
69 | )
70 | )
71 |
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/quartus_project/dsi_controller_test/test.cmp:
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1 | component test is
2 | port (
3 | din : in std_logic_vector(3 downto 0) := (others => 'X'); -- export
4 | pad_out : out std_logic_vector(3 downto 0); -- export
5 | oe : in std_logic_vector(3 downto 0) := (others => 'X') -- export
6 | );
7 | end component test;
8 |
9 |
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/quartus_project/dsi_controller_test/test.sip:
--------------------------------------------------------------------------------
1 | set_global_assignment -entity "test" -library "lib_test" -name IP_TOOL_NAME "altera_gpio_lite"
2 | set_global_assignment -entity "test" -library "lib_test" -name IP_TOOL_VERSION "18.0"
3 | set_global_assignment -entity "test" -library "lib_test" -name IP_TOOL_ENV "mwpim"
4 | set_global_assignment -library "lib_test" -name SPD_FILE [file join $::quartus(sip_path) "test.spd"]
5 |
6 | set_global_assignment -library "lib_test" -name MISC_FILE [file join $::quartus(sip_path) "test_sim/test.v"]
7 | set_global_assignment -library "lib_test" -name MISC_FILE [file join $::quartus(sip_path) "test_sim/altera_gpio_lite/altera_gpio_lite.sv"]
8 |
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/quartus_project/dsi_controller_test/test.spd:
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1 |
2 |
3 |
7 |
8 |
9 |
10 |
11 |
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/quartus_project/dsi_controller_test/test.v:
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1 | // megafunction wizard: %GPIO Lite Intel FPGA IP v18.0%
2 | // GENERATION: XML
3 | // test.v
4 |
5 | // Generated using ACDS version 18.0 614
6 |
7 | `timescale 1 ps / 1 ps
8 | module test (
9 | input wire [3:0] din, // din.export
10 | output wire [3:0] pad_out, // pad_out.export
11 | input wire [3:0] oe // oe.export
12 | );
13 |
14 | altera_gpio_lite #(
15 | .PIN_TYPE ("output"),
16 | .SIZE (4),
17 | .REGISTER_MODE ("bypass"),
18 | .BUFFER_TYPE ("single-ended"),
19 | .ASYNC_MODE ("none"),
20 | .SYNC_MODE ("none"),
21 | .BUS_HOLD ("false"),
22 | .OPEN_DRAIN_OUTPUT ("false"),
23 | .ENABLE_OE_PORT ("true"),
24 | .ENABLE_NSLEEP_PORT ("false"),
25 | .ENABLE_CLOCK_ENA_PORT ("false"),
26 | .SET_REGISTER_OUTPUTS_HIGH ("false"),
27 | .INVERT_OUTPUT ("false"),
28 | .INVERT_INPUT_CLOCK ("false"),
29 | .USE_ONE_REG_TO_DRIVE_OE ("false"),
30 | .USE_DDIO_REG_TO_DRIVE_OE ("false"),
31 | .USE_ADVANCED_DDR_FEATURES ("false"),
32 | .USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ("false"),
33 | .ENABLE_OE_HALF_CYCLE_DELAY ("true"),
34 | .INVERT_CLKDIV_INPUT_CLOCK ("false"),
35 | .ENABLE_PHASE_INVERT_CTRL_PORT ("false"),
36 | .ENABLE_HR_CLOCK ("false"),
37 | .INVERT_OUTPUT_CLOCK ("false"),
38 | .INVERT_OE_INCLOCK ("false"),
39 | .ENABLE_PHASE_DETECTOR_FOR_CK ("false")
40 | ) test_inst (
41 | .din (din), // din.export
42 | .pad_out (pad_out), // pad_out.export
43 | .oe (oe), // oe.export
44 | .outclocken (1'b1), // (terminated)
45 | .inclock (1'b0), // (terminated)
46 | .inclocken (1'b0), // (terminated)
47 | .fr_clock (), // (terminated)
48 | .hr_clock (), // (terminated)
49 | .invert_hr_clock (1'b0), // (terminated)
50 | .outclock (1'b0), // (terminated)
51 | .phy_mem_clock (1'b0), // (terminated)
52 | .mimic_clock (), // (terminated)
53 | .dout (), // (terminated)
54 | .pad_io (), // (terminated)
55 | .pad_io_b (), // (terminated)
56 | .pad_in (4'b0000), // (terminated)
57 | .pad_in_b (4'b0000), // (terminated)
58 | .pad_out_b (), // (terminated)
59 | .aset (1'b0), // (terminated)
60 | .aclr (1'b0), // (terminated)
61 | .sclr (1'b0), // (terminated)
62 | .nsleep (4'b0000) // (terminated)
63 | );
64 |
65 | endmodule
66 | // Retrieval info:
67 | //
92 | // Retrieval info:
93 | // Retrieval info:
94 | // Retrieval info:
95 | // Retrieval info:
96 | // Retrieval info:
97 | // Retrieval info:
98 | // Retrieval info:
99 | // Retrieval info:
100 | // Retrieval info:
101 | // Retrieval info:
102 | // Retrieval info:
103 | // Retrieval info:
104 | // Retrieval info:
105 | // Retrieval info:
106 | // Retrieval info:
107 | // Retrieval info:
108 | // Retrieval info:
109 | // Retrieval info:
110 | // Retrieval info:
111 | // Retrieval info:
112 | // Retrieval info:
113 | // Retrieval info:
114 | // Retrieval info:
115 | // Retrieval info:
116 | // Retrieval info:
117 | // Retrieval info:
118 | // Retrieval info:
119 | // Retrieval info:
120 | // Retrieval info:
121 | // Retrieval info:
122 | // IPFS_FILES : test.vo
123 | // RELATED_FILES: test.v, altera_gpio_lite.sv
124 |
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/quartus_project/dsi_controller_test/test_sim.f:
--------------------------------------------------------------------------------
1 | test_sim/test.v
2 | test_sim/altera_gpio_lite/altera_gpio_lite.sv
3 |
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/quartus_project/dsi_controller_test/test_sim/cadence/cds.lib:
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1 |
2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/
3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
11 | DEFINE work ./libraries/work/
12 | DEFINE test ./libraries/test/
13 | DEFINE altera_ver ./libraries/altera_ver/
14 | DEFINE lpm_ver ./libraries/lpm_ver/
15 | DEFINE sgate_ver ./libraries/sgate_ver/
16 | DEFINE altera_mf_ver ./libraries/altera_mf_ver/
17 | DEFINE altera_lnsim_ver ./libraries/altera_lnsim_ver/
18 | DEFINE fiftyfivenm_ver ./libraries/fiftyfivenm_ver/
19 |
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/quartus_project/dsi_controller_test/test_sim/cadence/cds_libs/test.cds.lib:
--------------------------------------------------------------------------------
1 |
2 | DEFINE std $CDS_ROOT/tools/inca/files/STD/
3 | DEFINE synopsys $CDS_ROOT/tools/inca/files/SYNOPSYS/
4 | DEFINE ieee $CDS_ROOT/tools/inca/files/IEEE/
5 | DEFINE ambit $CDS_ROOT/tools/inca/files/AMBIT/
6 | DEFINE vital_memory $CDS_ROOT/tools/inca/files/VITAL_MEMORY/
7 | DEFINE ncutils $CDS_ROOT/tools/inca/files/NCUTILS/
8 | DEFINE ncinternal $CDS_ROOT/tools/inca/files/NCINTERNAL/
9 | DEFINE ncmodels $CDS_ROOT/tools/inca/files/NCMODELS/
10 | DEFINE cds_assertions $CDS_ROOT/tools/inca/files/CDS_ASSERTIONS/
11 | DEFINE work ./../libraries/work/
12 | DEFINE altera_ver ./../libraries/altera_ver/
13 | DEFINE lpm_ver ./../libraries/lpm_ver/
14 | DEFINE sgate_ver ./../libraries/sgate_ver/
15 | DEFINE altera_mf_ver ./../libraries/altera_mf_ver/
16 | DEFINE altera_lnsim_ver ./../libraries/altera_lnsim_ver/
17 | DEFINE fiftyfivenm_ver ./../libraries/fiftyfivenm_ver/
18 | DEFINE test ./../libraries/test/
19 |
--------------------------------------------------------------------------------
/quartus_project/dsi_controller_test/test_sim/cadence/hdl.var:
--------------------------------------------------------------------------------
1 |
2 | DEFINE WORK work
3 |
--------------------------------------------------------------------------------
/quartus_project/dsi_controller_test/test_sim/synopsys/vcs/vcs_setup.sh:
--------------------------------------------------------------------------------
1 |
2 | # (C) 2001-2019 Altera Corporation. All rights reserved.
3 | # Your use of Altera Corporation's design tools, logic functions and
4 | # other software and tools, and its AMPP partner logic functions, and
5 | # any output files any of the foregoing (including device programming
6 | # or simulation files), and any associated documentation or information
7 | # are expressly subject to the terms and conditions of the Altera
8 | # Program License Subscription Agreement, Altera MegaCore Function
9 | # License Agreement, or other applicable license agreement, including,
10 | # without limitation, that your use is for the sole purpose of
11 | # programming logic devices manufactured by Altera and sold by Altera
12 | # or its authorized distributors. Please refer to the applicable
13 | # agreement for further details.
14 |
15 | # ACDS 18.0 614 win32 2019.03.31.23:26:19
16 |
17 | # ----------------------------------------
18 | # vcs - auto-generated simulation script
19 |
20 | # ----------------------------------------
21 | # This script provides commands to simulate the following IP detected in
22 | # your Quartus project:
23 | # test
24 | #
25 | # Altera recommends that you source this Quartus-generated IP simulation
26 | # script from your own customized top-level script, and avoid editing this
27 | # generated script.
28 | #
29 | # To write a top-level shell script that compiles Altera simulation libraries
30 | # and the Quartus-generated IP in your project, along with your design and
31 | # testbench files, follow the guidelines below.
32 | #
33 | # 1) Copy the shell script text from the TOP-LEVEL TEMPLATE section
34 | # below into a new file, e.g. named "vcs_sim.sh".
35 | #
36 | # 2) Copy the text from the DESIGN FILE LIST & OPTIONS TEMPLATE section into
37 | # a separate file, e.g. named "filelist.f".
38 | #
39 | # ----------------------------------------
40 | # # TOP-LEVEL TEMPLATE - BEGIN
41 | # #
42 | # # TOP_LEVEL_NAME is used in the Quartus-generated IP simulation script to
43 | # # set the top-level simulation or testbench module/entity name.
44 | # #
45 | # # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to
46 | # # construct paths to the files required to simulate the IP in your Quartus
47 | # # project. By default, the IP script assumes that you are launching the
48 | # # simulator from the IP script location. If launching from another
49 | # # location, set QSYS_SIMDIR to the output directory you specified when you
50 | # # generated the IP script, relative to the directory from which you launch
51 | # # the simulator.
52 | # #
53 | # # Source the Quartus-generated IP simulation script and do the following:
54 | # # - Compile the Quartus EDA simulation library and IP simulation files.
55 | # # - Specify TOP_LEVEL_NAME and QSYS_SIMDIR.
56 | # # - Compile the design and top-level simulation module/entity using
57 | # # information specified in "filelist.f".
58 | # # - Override the default USER_DEFINED_SIM_OPTIONS. For example, to run
59 | # # until $finish(), set to an empty string: USER_DEFINED_SIM_OPTIONS="".
60 | # # - Run the simulation.
61 | # #
62 | # source