├── .gitignore ├── Makefile ├── README ├── ar100-boot ├── Makefile ├── ar100-boot.ld ├── main.c └── start.S ├── ar100-info.ld ├── clock.h ├── cpu.h ├── dram.h ├── dram_sun6i.c ├── gpio.c ├── gpio.h ├── instruction_tests.h ├── io.h ├── main.c ├── platform.h ├── spr-defs.h ├── spr.h ├── start.S ├── timer.h ├── type.h ├── uart.c └── uart.h /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | *.o 3 | *.bin 4 | *.code 5 | ar100-boot 6 | ar100-info -------------------------------------------------------------------------------- /Makefile: -------------------------------------------------------------------------------- 1 | # Commands 2 | CROSS_COMPILE ?= or1k-elf- 3 | CC = $(CROSS_COMPILE)gcc 4 | CPP = $(CROSS_COMPILE)g++ 5 | LD = $(CROSS_COMPILE)ld 6 | OBJCOPY = $(CROSS_COMPILE)objcopy 7 | OBJDUMP = $(CROSS_COMPILE)objdump 8 | REMOVE = rm -rf 9 | FEL ?= sunxi-fel 10 | 11 | # Compiler flags 12 | CFLAGS = -O2 -fno-common -fno-builtin -ffreestanding 13 | 14 | # Linker flags 15 | LDFLAGS = -static -nostartfiles -lgcc 16 | 17 | # Sources 18 | TARGET = main.c 19 | SRC = $(TARGET) 20 | SRC += uart.c 21 | SRC += gpio.c 22 | SRC += dram_sun6i.c 23 | 24 | SSRC = start.S 25 | 26 | # Output filename 27 | OUT = ar100-info 28 | 29 | # Object defines 30 | COBJ = $(SRC:.c=.o) 31 | SOBJ = $(SSRC:.S=.o) 32 | 33 | all: $(SRC) $(OUT) $(OUT).bin $(OUT).code 34 | 35 | $(OUT).code: $(OUT).bin 36 | srec_cat $< -Binary -Byte_Swap 4 -Output $@ -Binary 37 | 38 | $(OUT).bin: $(OUT) 39 | $(OBJCOPY) -O binary $< $@ 40 | 41 | $(OUT): $(COBJ) $(SOBJ) 42 | $(CC) $(LDFLAGS) -T$@.ld $(SOBJ) $(COBJ) -o $@ 43 | 44 | $(COBJ) : %.o : %.c 45 | $(CC) $(CFLAGS) -c $< -o $@ 46 | 47 | $(SOBJ) : %.o : %.S 48 | $(CC) $(CFLAGS) -c $< -o $@ 49 | 50 | load: $(OUT).code 51 | $(FEL) write 0x40000 $< 52 | $(FEL) exe 0x44000 53 | 54 | clean: 55 | $(REMOVE) *~ $(COBJ) $(SOBJ) $(OUT) $(OUT).bin $(OUT).code 56 | -------------------------------------------------------------------------------- /README: -------------------------------------------------------------------------------- 1 | Introduction 2 | ============ 3 | A small OpenRISC 1000 baremetal application to be run on the Allwinner A31 4 | and Allwinner H3 SoCs to gain some information about the AR100 core (an or1k 5 | implementation) present in that SoCs. 6 | 7 | Usage 8 | ===== 9 | The application is intended to be loaded into SRAM from the FEL mode with the 10 | 'sunxi-fel' tool available from https://github.com/linux-sunxi/sunxi-tools. 11 | 12 | Embedded in the OpenRISC 1000 binary is a small ARM "boot loader", 13 | which is intended to be run first, it's sole purpose is to deassert the 14 | reset line to the AR100 core. 15 | 16 | To build the ARM "boot loader": 17 | $ make -C ar100-boot/ 18 | 19 | To build, load and run the OpenRISC baremetal application: 20 | $ make load 21 | 22 | A note about the SRAM and exception vectors 23 | =========================================== 24 | AR100 uses an SRAM located at addresses 0x40000 - 0x54000 25 | (as seen from the ARM cores) as instruction and data memory. 26 | The OpenRISC 1000 architecture defines a generous space (0x100 bytes) for each 27 | exception vector i.e. 28 | 29 | 0x100 vector0 30 | ... 31 | 0x200 vector1 32 | ... 33 | 0x300 vector3 34 | ... 35 | etc 36 | 37 | This is rather memory consuming, especially if you are using an internal 38 | SRAM as the main memory. 39 | To avoid this, the Allwinner engineers have added address decode logic to 40 | the lower addresses of the SRAM, so that only the first word of each 0x100 41 | multiple is actually routed to the memory. 42 | The second word of each 0x100 multiple reads out as 0x15000000 = l.nop and the 43 | rest as 0x00000000. 44 | i.e. all exception vectors have to be implemented like this: 45 | 46 | l.j exception_handler 47 | l.nop 48 | 49 | The actual contiguous SRAM memory starts at address 0x44000. The size of this 50 | contiguous SRAM memory is 64 KiB in Allwinner A31 and 32 KiB in Allwinner H3. 51 | 52 | Results (application output) 53 | ============================ 54 | OpenRISC-1200 (rev 1) 55 | D-Cache: no 56 | I-Cache: 4096 bytes, 16 bytes/line, 1 way(s) 57 | DMMU: no 58 | IMMU: no 59 | MAC unit: yes 60 | Debug unit: yes 61 | Performance counters: no 62 | Power management: yes 63 | Interrupt controller: yes 64 | Timer: yes 65 | Custom unit(s): no 66 | ORBIS32: yes 67 | ORBIS64: no 68 | ORFPX32: no 69 | ORFPX64: no 70 | Test support for l.addc...yes 71 | Test support for l.cmov...yes 72 | Test support for l.cust1...no 73 | Test support for l.cust2...no 74 | Test support for l.cust3...no 75 | Test support for l.cust4...no 76 | Test support for l.cust5...no 77 | Test support for l.cust6...no 78 | Test support for l.cust7...no 79 | Test support for l.cust8...no 80 | Test support for l.div...yes 81 | Test support for l.divu...yes 82 | Test support for l.extbs...yes 83 | Test support for l.extbz...yes 84 | Test support for l.exths...yes 85 | Test support for l.exthz...yes 86 | Test support for l.extws...yes 87 | Test support for l.extwz...yes 88 | Test support for l.ff1...yes 89 | Test support for l.fl1...yes 90 | Test support for l.lws...no 91 | Test support for l.mac...yes 92 | Test support for l.maci...yes 93 | Test support for l.macrc...yes 94 | Test support for l.mul...yes 95 | Test support for l.muli...yes 96 | Test support for l.mulu...yes 97 | Test support for l.ror...yes 98 | Test support for l.rori...yes 99 | Init DRAM...done 100 | Test DRAM read/write...OK 101 | Test timer functionality...OK 102 | Set clock source to LOSC...done 103 | Test CLK freq...33 KHz 104 | Set clock source to HOSC (POSTDIV=0, DIV=0)...done 105 | Test CLK freq...24 MHz 106 | Set clock source to HOSC (POSTDIV=0, DIV=1)...done 107 | Test CLK freq...12 MHz 108 | Set clock source to HOSC (POSTDIV=1, DIV=1)...done 109 | Test CLK freq...12 MHz 110 | Setup PLL6 (M=1, K=1, N=24)...done 111 | Set clock source to PLL6 (POSTDIV=1, DIV=0)...done 112 | Test CLK freq...300 MHz 113 | Set clock source to PLL6 (POSTDIV=2, DIV=0)...done 114 | Test CLK freq...200 MHz 115 | Set clock source to PLL6 (POSTDIV=2, DIV=1)...done 116 | Test CLK freq...100 MHz 117 | Setup PLL6 (M=2, K=1, N=24)...done 118 | Test CLK freq...100 MHz 119 | Setup PLL6 (M=1, K=2, N=24)...done 120 | Test CLK freq...150 MHz 121 | Setup PLL6 (M=1, K=1, N=12)...done 122 | Test CLK freq...52 MHz 123 | Restore clock config to original state...done 124 | All tests completed! 125 | -------------------------------------------------------------------------------- /ar100-boot/Makefile: -------------------------------------------------------------------------------- 1 | # Commands 2 | CROSS_COMPILE ?= arm-linux-gnueabi- 3 | CC = $(CROSS_COMPILE)gcc 4 | CPP = $(CROSS_COMPILE)g++ 5 | OBJCOPY = $(CROSS_COMPILE)objcopy 6 | OBJDUMP = $(CROSS_COMPILE)objdump 7 | REMOVE = rm -rf 8 | 9 | # Compiler flags 10 | CFLAGS = -marm -mno-thumb-interwork -mabi=aapcs-linux -march=armv7-a \ 11 | -fno-common -fno-builtin -ffreestanding -msoft-float 12 | 13 | # Linker flags 14 | LDFLAGS = $(CFLAGS) --gc-sections -static -nostartfiles 15 | 16 | # Sources 17 | TARGET = main.c 18 | SRC = $(TARGET) 19 | 20 | SSRC = start.S 21 | 22 | # Output filename 23 | OUT = ar100-boot 24 | 25 | # Object defines 26 | COBJ = $(SRC:.c=.o) 27 | SOBJ = $(SSRC:.S=.o) 28 | 29 | all: $(SRC) $(OUT) $(OUT).bin $(OUT).code 30 | 31 | $(OUT).code: $(OUT).bin 32 | srec_cat $< -Binary -Byte_Swap 4 -Output $@ -Binary 33 | 34 | $(OUT).bin: $(OUT) 35 | $(OBJCOPY) -O binary $< $@ 36 | 37 | $(OUT): $(COBJ) $(SOBJ) 38 | $(CC) $(LDFLAGS) -T$@.ld $(SOBJ) $(COBJ) -o $@ 39 | 40 | $(COBJ) : %.o : %.c 41 | $(CC) $(CFLAGS) -c $< -o $@ 42 | 43 | $(SOBJ) : %.o : %.S 44 | $(CC) $(CFLAGS) -c $< -o $@ 45 | 46 | clean: 47 | $(REMOVE) *~ $(COBJ) $(SOBJ) $(OUT) $(OUT).bin $(OUT).code 48 | -------------------------------------------------------------------------------- /ar100-boot/ar100-boot.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") 2 | OUTPUT_ARCH(arm) 3 | ENTRY(_start) 4 | SECTIONS 5 | { 6 | . = 0x00044000; 7 | . = ALIGN(4); 8 | .text : 9 | { 10 | start.o (.text.start) 11 | *(.text*) 12 | } 13 | . = ALIGN(4); 14 | .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } 15 | . = ALIGN(4); 16 | .data : { 17 | *(.data*) 18 | } 19 | . = ALIGN(4); 20 | . = .; 21 | . = ALIGN(4); 22 | .rel.dyn : { 23 | __rel_dyn_start = .; 24 | *(.rel*) 25 | __rel_dyn_end = .; 26 | } 27 | .dynsym : { 28 | __dynsym_start = .; 29 | *(.dynsym) 30 | } 31 | . = ALIGN(4); 32 | .note.gnu.build-id : 33 | { 34 | *(.note.gnu.build-id) 35 | } 36 | _end = .; 37 | . = ALIGN(4096); 38 | .mmutable : { 39 | *(.mmutable) 40 | } 41 | .bss_start __rel_dyn_start (OVERLAY) : { 42 | KEEP(*(.__bss_start)); 43 | __bss_base = .; 44 | } 45 | .bss __bss_base (OVERLAY) : { 46 | *(.bss*) 47 | . = ALIGN(4); 48 | __bss_limit = .; 49 | } 50 | .bss_end __bss_limit (OVERLAY) : { 51 | KEEP(*(.__bss_end)); 52 | } 53 | /DISCARD/ : { *(.dynstr*) } 54 | /DISCARD/ : { *(.dynamic*) } 55 | /DISCARD/ : { *(.plt*) } 56 | /DISCARD/ : { *(.interp*) } 57 | /DISCARD/ : { *(.gnu*) } 58 | /DISCARD/ : { *(.note*) } 59 | } 60 | -------------------------------------------------------------------------------- /ar100-boot/main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Stefan Kristiansson 3 | * 4 | * This program is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU General Public License as 6 | * published by the Free Software Foundation; either version 2 of 7 | * the License, or (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 | * MA 02111-1307 USA 18 | */ 19 | #define CPUCFG_BASE 0x01f01c00 20 | 21 | #define readl(addr) (*((volatile unsigned long *)(addr))) 22 | #define writel(v, addr) (*((volatile unsigned long *)(addr)) = (unsigned long)(v)) 23 | 24 | /* 25 | * from U-Boot arch/arm/cpu/armv7/syslib 26 | * (C) Copyright 2008 27 | * Texas Instruments, 28 | * 29 | * Richard Woodruff 30 | * Syed Mohammed Khasim 31 | */ 32 | void delay(unsigned long loops) 33 | { 34 | __asm__ volatile ("1:\n" "subs %0, %1, #1\n" 35 | "bne 1b":"=r" (loops):"0"(loops)); 36 | } 37 | 38 | int main(void) 39 | { 40 | volatile unsigned long cpu_cfg; 41 | 42 | /* assert reset to ar100 */ 43 | cpu_cfg = readl(CPUCFG_BASE); 44 | cpu_cfg &= ~(1uL); 45 | writel(cpu_cfg, CPUCFG_BASE); 46 | delay(1000); 47 | /* deassert reset to ar100 */ 48 | cpu_cfg |= 1; 49 | writel(cpu_cfg, CPUCFG_BASE); 50 | 51 | return 0; 52 | } 53 | -------------------------------------------------------------------------------- /ar100-boot/start.S: -------------------------------------------------------------------------------- 1 | .globl _start 2 | _start: 3 | b main 4 | -------------------------------------------------------------------------------- /ar100-info.ld: -------------------------------------------------------------------------------- 1 | OUTPUT_FORMAT("elf32-or1k") 2 | OUTPUT_ARCH(or1k) 3 | ENTRY(_start) 4 | SECTIONS 5 | { 6 | . = 0x00000000; 7 | . = ALIGN(4); 8 | .text : 9 | { 10 | start.o (.text.start) 11 | *(.text*) 12 | } 13 | . = ALIGN(4); 14 | .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } 15 | . = ALIGN(4); 16 | .data : { 17 | *(.data*) 18 | } 19 | . = ALIGN(4); 20 | . = .; 21 | . = ALIGN(4); 22 | .rel.dyn : { 23 | __rel_dyn_start = .; 24 | *(.rel*) 25 | __rel_dyn_end = .; 26 | } 27 | .dynsym : { 28 | __dynsym_start = .; 29 | *(.dynsym) 30 | } 31 | . = ALIGN(4); 32 | .note.gnu.build-id : 33 | { 34 | *(.note.gnu.build-id) 35 | } 36 | _end = .; 37 | . = ALIGN(4096); 38 | .mmutable : { 39 | *(.mmutable) 40 | } 41 | .bss_start __rel_dyn_start (OVERLAY) : { 42 | KEEP(*(.__bss_start)); 43 | __bss_base = .; 44 | } 45 | .bss __bss_base (OVERLAY) : { 46 | *(.bss*) 47 | . = ALIGN(4); 48 | __bss_limit = .; 49 | } 50 | .bss_end __bss_limit (OVERLAY) : { 51 | KEEP(*(.__bss_end)); 52 | } 53 | /DISCARD/ : { *(.dynstr*) } 54 | /DISCARD/ : { *(.dynamic*) } 55 | /DISCARD/ : { *(.plt*) } 56 | /DISCARD/ : { *(.interp*) } 57 | /DISCARD/ : { *(.gnu*) } 58 | /DISCARD/ : { *(.note*) } 59 | } 60 | -------------------------------------------------------------------------------- /clock.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Stefan Kristiansson 3 | * 4 | * This program is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU General Public License as 6 | * published by the Free Software Foundation; either version 2 of 7 | * the License, or (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 | * MA 02111-1307 USA 18 | */ 19 | #ifndef _CLOCK_H 20 | #define _CLOCK_H 21 | #include "platform.h" 22 | 23 | /* 24 | * PLL6 control register: 25 | * [31] Enable 26 | * [30:29] Reserved 27 | * [28] Lock flag 28 | * [27:26] Reserved 29 | * [25] Output bypass enable 30 | * [24] Clock output enable 31 | * [23:19] Reserved 32 | * [18] 24 MHz clock output enable 33 | * [17:16] 24 MHz output clock post divider 34 | * [15:13] Reserved 35 | * [12:8] Factor N 36 | * [7:6] Reserved 37 | * [5:4] Factor K 38 | * [3:2] Reserved 39 | * [1:0] Factor M 40 | */ 41 | #define PLL6_CTRL_REG (AW_CCM_BASE + 0x0028) 42 | #define PLL6_CTRL_ENABLE (1 << 31) 43 | #define PLL6_CTRL_LOCK (1 << 28) 44 | #define PLL6_CTRL_BYPASS (1 << 25) 45 | #define PLL6_CTRL_CLK_OUTEN (1 << 24) 46 | #define PLL6_CTRL_24M_OUTEN (1 << 18) 47 | #define PLL6_CTRL_24M_POSTDIV(x) (((x) & 0x3) << 16) 48 | #define PLL6_CTRL_24M_POSTDIV_MASK (0x3 << 16) 49 | #define PLL6_CTRL_N(x) (((x) & 0x1f) << 8) 50 | #define PLL6_CTRL_N_MASK (0x1f << 8) 51 | #define PLL6_CTRL_K(x) (((x) & 0x3) << 4) 52 | #define PLL6_CTRL_K_MASK (0x3 << 4) 53 | #define PLL6_CTRL_M(x) (((x) & 0x3) << 0) 54 | #define PLL6_CTRL_M_MASK (0x3 << 0) 55 | 56 | /* apb2 bit field */ 57 | #define APB2_CLK_SRC_LOSC (0x0 << 24) 58 | #define APB2_CLK_SRC_OSC24M (0x1 << 24) 59 | #define APB2_CLK_SRC_PLL6 (0x2 << 24) 60 | #define APB2_CLK_SRC_MASK (0x3 << 24) 61 | #define APB2_CLK_RATE_N_1 (0x0 << 16) 62 | #define APB2_CLK_RATE_N_2 (0x1 << 16) 63 | #define APB2_CLK_RATE_N_4 (0x2 << 16) 64 | #define APB2_CLK_RATE_N_8 (0x3 << 16) 65 | #define APB2_CLK_RATE_N_MASK (3 << 16) 66 | #define APB2_CLK_RATE_M(m) (((m)-1) << 0) 67 | #define APB2_CLK_RATE_M_MASK (0x1f << 0) 68 | 69 | /* apb2 gate field */ 70 | #define APB2_GATE_UART_SHIFT (16) 71 | #define APB2_GATE_UART_MASK (0xff << APB2_GATE_UART_SHIFT) 72 | #define APB2_GATE_TWI_SHIFT (0) 73 | #define APB2_GATE_TWI_MASK (0xf << APB2_GATE_TWI_SHIFT) 74 | 75 | /* apb2 reset */ 76 | #define APB2_RESET_UART_SHIFT (16) 77 | #define APB2_RESET_UART_MASK (0xff << APB2_RESET_UART_SHIFT) 78 | #define APB2_RESET_TWI_SHIFT (0) 79 | #define APB2_RESET_TWI_MASK (0xf << APB2_RESET_TWI_SHIFT) 80 | 81 | /* 82 | * AR100 clock configuration register: 83 | * [31:18] Reserved 84 | * [17:16] Clock source (00: LOSC, 01: HOSC, 10/11: PLL6/PDIV) 85 | * [15:13] Reserved 86 | * [12:8] Post divide (00000: 1 - 11111: 32) 87 | * [7:6] Reserved 88 | * [5:4] Clock divide ratio (00: 1, 01: 2, 10: 4, 11: 8) 89 | * [3:0] Reserved 90 | */ 91 | #define AR100_CLKCFG_REG (AW_R_PRCM_BASE + 0x000) 92 | #define AR100_CLKCFG_SRC_LOSC (0 << 16) 93 | #define AR100_CLKCFG_SRC_HOSC (1 << 16) 94 | #define AR100_CLKCFG_SRC_PLL6 (2 << 16) 95 | #define AR100_CLKCFG_SRC_MASK (0x3 << 16) 96 | #define AR100_CLKCFG_POSTDIV(x) (((x) & 0x1f) << 8) 97 | #define AR100_CLKCFG_POSTDIV_MASK (0x1f << 8) 98 | #define AR100_CLKCFG_DIV(x) (((x) & 0x3) << 4) 99 | #define AR100_CLKCFG_DIV_MASK (0x3 << 4) 100 | 101 | #endif 102 | -------------------------------------------------------------------------------- /cpu.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2007-2011 3 | * Allwinner Technology Co., Ltd. 4 | * Tom Cubie 5 | * 6 | * See file CREDITS for list of people who contributed to this 7 | * project. 8 | * 9 | * This program is free software; you can redistribute it and/or 10 | * modify it under the terms of the GNU General Public License as 11 | * published by the Free Software Foundation; either version 2 of 12 | * the License, or (at your option) any later version. 13 | * 14 | * This program is distributed in the hope that it will be useful, 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | * GNU General Public License for more details. 18 | * 19 | * You should have received a copy of the GNU General Public License 20 | * along with this program; if not, write to the Free Software 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 | * MA 02111-1307 USA 23 | */ 24 | 25 | #ifndef _SUNXI_CPU_H 26 | #define _SUNXI_CPU_H 27 | 28 | 29 | #define SUNXI_SRAM_A1_BASE 0X00000000 30 | #define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16k */ 31 | 32 | #define SUNXI_SRAM_A2_BASE 0X00004000 /* 16k */ 33 | #define SUNXI_SRAM_A3_BASE 0X00008000 /* 13k */ 34 | #define SUNXI_SRAM_A4_BASE 0X0000B400 /* 3k */ 35 | #if 0 36 | #define SUNXI_SRAM_NAND_BASE 0Xdeaddead /* 2k(address not available on spec) */ 37 | #endif 38 | #define SUNXI_SRAM_D_BASE 0X01C00000 39 | #define SUNXI_SRAM_B_BASE 0X01C00000 /* 64k(secure) */ 40 | 41 | #define SUNXI_SRAMC_BASE 0X01C00000 42 | #define SUNXI_DRAMC_BASE 0X01C01000 43 | #define SUNXI_DMA_BASE 0X01C02000 44 | #define SUNXI_NFC_BASE 0X01C03000 45 | #define SUNXI_TS_BASE 0X01C04000 46 | #define SUNXI_SPI0_BASE 0X01C05000 47 | #define SUNXI_SPI1_BASE 0X01C06000 48 | #define SUNXI_MS_BASE 0X01C07000 49 | #define SUNXI_TVD_BASE 0X01C08000 50 | #define SUNXI_CSI0_BASE 0X01C09000 51 | #define SUNXI_TVE0_BASE 0X01C0A000 52 | #define SUNXI_EMAC_BASE 0X01C0B000 53 | #define SUNXI_LCD0_BASE 0X01C0C000 54 | #define SUNXI_LCD1_BASE 0X01C0D000 55 | #define SUNXI_VE_BASE 0X01C0E000 56 | #define SUNXI_MMC0_BASE 0X01C0F000 57 | #define SUNXI_MMC1_BASE 0X01C10000 58 | #define SUNXI_MMC2_BASE 0X01C11000 59 | #define SUNXI_MMC3_BASE 0X01C12000 60 | #define SUNXI_USB0_BASE 0X01C13000 61 | #define SUNXI_USB1_BASE 0X01C14000 62 | #define SUNXI_SS_BASE 0X01C15000 63 | #define SUNXI_HDMI_BASE 0X01C16000 64 | #define SUNXI_SPI2_BASE 0X01C17000 65 | #define SUNXI_SATA_BASE 0X01C18000 66 | #define SUNXI_PATA_BASE 0X01C19000 67 | #define SUNXI_ACE_BASE 0X01C1A000 68 | #define SUNXI_TVE1_BASE 0X01C1B000 69 | #define SUNXI_USB2_BASE 0X01C1C000 70 | #define SUNXI_CSI1_BASE 0X01C1D000 71 | #define SUNXI_TZASC_BASE 0X01C1E000 72 | #define SUNXI_SPI3_BASE 0X01C1F000 73 | 74 | #define SUNXI_CCM_BASE 0X01C20000 75 | #define SUNXI_INTC_BASE 0X01C20400 76 | #define SUNXI_PIO_BASE 0X01C20800 77 | #define SUNXI_TIMER_BASE 0X01C20C00 78 | #define SUNXI_SPDIF_BASE 0X01C21000 79 | #define SUNXI_AC97_BASE 0X01C21400 80 | #define SUNXI_IR0_BASE 0X01C21800 81 | #define SUNXI_IR1_BASE 0X01C21C00 82 | 83 | #define SUNXI_IIS_BASE 0X01C22400 84 | #define SUNXI_LRADC_BASE 0X01C22800 85 | #define SUNXI_AD_DA_BASE 0X01C22C00 86 | #define SUNXI_KEYPAD_BASE 0X01C23000 87 | #define SUNXI_TZPC_BASE 0X01C23400 88 | #define SUNXI_SID_BASE 0X01C23800 89 | #define SUNXI_SJTAG_BASE 0X01C23C00 90 | 91 | #define SUNXI_TP_BASE 0X01C25000 92 | #define SUNXI_PMU_BASE 0X01C25400 93 | 94 | #define SUNXI_UART0_BASE 0X01C28000 95 | #define SUNXI_UART1_BASE 0X01C28400 96 | #define SUNXI_UART2_BASE 0X01C28800 97 | #define SUNXI_UART3_BASE 0X01C28C00 98 | #define SUNXI_UART4_BASE 0X01C29000 99 | #define SUNXI_UART5_BASE 0X01C29400 100 | #define SUNXI_UART6_BASE 0X01C29800 101 | #define SUNXI_UART7_BASE 0X01C29C00 102 | #define SUNXI_PS2_0_BASE 0X01C2A000 103 | #define SUNXI_PS2_1_BASE 0X01C2A400 104 | 105 | #define SUNXI_TWI0_BASE 0X01C2AC00 106 | #define SUNXI_TWI1_BASE 0X01C2B000 107 | #define SUNXI_TWI2_BASE 0X01C2B400 108 | 109 | #define SUNXI_CAN_BASE 0X01C2BC00 110 | 111 | #define SUNXI_SCR_BASE 0X01C2C400 112 | 113 | #define SUNXI_GPS_BASE 0X01C30000 114 | #define SUNXI_MALI400_BASE 0X01C40000 115 | 116 | #define SUNXI_SRAM_C_BASE 0X01D00000 /* module sram */ 117 | 118 | #define SUNXI_DE_FE0_BASE 0X01E00000 119 | #define SUNXI_DE_FE1_BASE 0X01E20000 120 | #define SUNXI_DE_BE0_BASE 0X01E60000 121 | #define SUNXI_DE_BE1_BASE 0X01E40000 122 | #define SUNXI_MP_BASE 0X01E80000 123 | #define SUNXI_AVG_BASE 0X01EA0000 124 | 125 | #define SUNXI_CSDM_BASE 0X3F500000 /* CoreSight Debug Module*/ 126 | 127 | #define SUNXI_DDRII_DDRIII_BASE 0X40000000 /* 2G */ 128 | 129 | #define SUNXI_BROM_BASE 0XFFFF0000 /* 32K */ 130 | 131 | #define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) 132 | 133 | #ifndef __ASSEMBLY__ 134 | /* boot type */ 135 | typedef enum { 136 | SUNXI_BOOT_TYPE_NULL = -1, 137 | SUNXI_BOOT_TYPE_NAND = 0, 138 | SUNXI_BOOT_TYPE_MMC0 = 1, 139 | SUNXI_BOOT_TYPE_MMC2 = 2, 140 | SUNXI_BOOT_TYPE_SPI = 3 141 | } sunxi_boot_type_t; 142 | 143 | sunxi_boot_type_t get_boot_type(void); 144 | #endif /* __ASSEMBLY__ */ 145 | 146 | #define SUNXI_GET_BITS(value, start_bit, bits_num) ( (value >> start_bit) & \ 147 | ((1 << bits_num) - 1) ) 148 | 149 | #endif /* _CPU_H */ 150 | -------------------------------------------------------------------------------- /dram.h: -------------------------------------------------------------------------------- 1 | #ifndef _SUNXI_DRAM_H 2 | #define _SUNXI_DRAM_H 3 | #define PLL5_DDR_CLK (24000000) 4 | #define uint32 unsigned 5 | #define DRAM_MEM_BASE (0x40000000) 6 | #define HEAP_MEM_START (0x48000000) //heap start offset: 128MB 7 | #define HEAP_MEM_SIZE (0x18000000) //384MB 8 | #define DRAM_FREE_MEM_BASE (0x40100000) //free memory for test, size 7M 9 | 10 | #ifdef CONFIG_SUN6I_FPGA 11 | //#define DDR2_32B 12 | //#define DDR3_32B 13 | //#define DDR2_FPGA_BJ530 //DDR2_32B 14 | #define DDR2_FPGA_S2C 15 | //#define LPDDR2_FPGA_S2C_2CS_2CH 16 | #define MCTL_CLK PLL5_DDR_CLK 17 | #define MCTL_ACCESS_MODE 1 //0: sequence mode, 1: interleave mode 18 | #define MCTL_CHANNEL_NUM 1 19 | #ifdef DDR2_FPGA_S2C 20 | #define MCTL_CS_NUM 2 21 | #else 22 | #define MCTL_CS_NUM 2 23 | #endif 24 | #else 25 | //#define DDR2_32B 26 | #define DDR3_32B 27 | //#define LPDDR2_32B 28 | #define MCTL_CLK PLL5_DDR_CLK 29 | #define MCTL_ACCESS_MODE 1 //0: sequence mode, 1: interleave mode 30 | #define MCTL_CHANNEL_NUM 2 31 | #define MCTL_CS_NUM 1 32 | #endif 33 | extern uint32 mctl_init(void); 34 | extern uint32 mctl_set_emrs(uint32 emrs_id, uint32 emrs_val); 35 | extern uint32 mctl_scan_readpipe(uint32 clk); 36 | 37 | extern void mctl_self_refresh_entry(uint32 channel_num); 38 | extern void mctl_self_refresh_exit(uint32 channel_num); 39 | extern void mctl_power_down_entry(void); 40 | extern void mctl_power_down_exit(void); 41 | extern void mctl_precharge_all(void); 42 | 43 | extern void mctl_setup_ar_interval(uint32 clk); 44 | extern void mctl_DLL_reset(void); 45 | extern void mctl_DLL_enable(void); 46 | extern void mctl_DLL_disable(void); 47 | extern void mctl_hostport_control(uint32 enable); 48 | extern uint32 mctl_init_dram(void); 49 | 50 | 51 | extern void mctl_host_port_cfg(uint32 port_no, uint32 cfg); 52 | extern void mctl_power_save_process(void); 53 | extern uint32 mctl_power_up_process(void); 54 | extern uint32 mctl_ahb_reset(void); 55 | 56 | 57 | 58 | //DDR2_32B DDR2_32B_128Mx8x4 59 | //DDR3_32B DDR3_32B_256Mx8x4 60 | 61 | 62 | 63 | //***************************************************************************** 64 | //DDR2 SDRAM(x32) 65 | //***************************************************************************** 66 | #ifdef DDR2_FPGA_S2C 67 | //DDR2 128Mx8 (128M Byte), total 1GB 68 | #define MCTL_DDR_TYPE 2 //1: DDR, 2: DDR2, 3: DDR3 69 | #define MCTL_BANK_SIZE 8 70 | #define MCTL_ROW_WIDTH 14 71 | #define MCTL_BUS_WIDTH 32 72 | #define MCTL_PAGE_SIZE 4 //unit in KByte for one rank 73 | #endif 74 | 75 | #ifdef DDR2_FPGA_S2C_2C 76 | //DDR2 128Mx8 (128M Byte), total 512MB 77 | #define MCTL_DDR_TYPE 2 //1: DDR, 2: DDR2, 3: DDR3 78 | #define MCTL_BANK_SIZE 8 79 | #define MCTL_ROW_WIDTH 14 80 | #define MCTL_BUS_WIDTH 16 81 | #define MCTL_PAGE_SIZE 2 //unit in KByte for one rank 82 | #endif 83 | 84 | #ifdef DDR2_32B 85 | //DDR2 128Mx8 (128M Byte) 86 | #define MCTL_DDR_TYPE 2 //1: DDR, 2: DDR2, 3: DDR3 87 | #define MCTL_BANK_SIZE 8 88 | #define MCTL_ROW_WIDTH 14 89 | #define MCTL_BUS_WIDTH 32 90 | #define MCTL_PAGE_SIZE 4 //unit in KByte for one rank 91 | #endif 92 | 93 | //***************************************************************************** 94 | //DDR3 SDRAM(x32) 95 | //***************************************************************************** 96 | #ifdef DDR3_32B 97 | //DDR3 256Mx8 (256M Byte) 98 | #define MCTL_DDR_TYPE 3 //1: DDR, 2: DDR2, 3: DDR3 99 | #define MCTL_BANK_SIZE 8 100 | #define MCTL_ROW_WIDTH 15 101 | #define MCTL_BUS_WIDTH 32 102 | #define MCTL_PAGE_SIZE 4 //unit in KByte for one rank 103 | #endif 104 | 105 | 106 | //***************************************************************************** 107 | //LPDDR2 SDRAM(x32) 108 | //***************************************************************************** 109 | #ifdef LPDDR2_FPGA_S2C_2CS_2CH 110 | //LPDDR2 128Mx32 (512M Byte), total 2GB 111 | #define MCTL_DDR_TYPE 6 //1: DDR, 2: DDR2, 3: DDR3 112 | #define MCTL_BANK_SIZE 8 113 | #define MCTL_ROW_WIDTH 14 114 | #define MCTL_BUS_WIDTH 32 115 | #define MCTL_PAGE_SIZE 4 //unit in KByte for one rank 116 | #endif 117 | 118 | #ifdef LPDDR2_32B 119 | //LPDDR2 128Mx32 120 | #define MCTL_DDR_TYPE 6 //1: DDR, 2: DDR2, 3: DDR3 121 | #define MCTL_BANK_SIZE 8 122 | #define MCTL_ROW_WIDTH 14 123 | #define MCTL_BUS_WIDTH 32 124 | #define MCTL_PAGE_SIZE 4 //unit in KByte for one rank 125 | #endif 126 | 127 | 128 | 129 | 130 | #if (MCTL_DDR_TYPE==2) //DDR2-800 131 | 132 | #define MCTL_TREFI 78 133 | #define MCTL_TMRD 2 134 | #define MCTL_TRFC 52 135 | #define MCTL_TRP 6 136 | #define MCTL_TPREA 1 137 | #define MCTL_TRTW 2 138 | #define MCTL_TAL 0 139 | #define MCTL_TCL 6 140 | #define MCTL_TCWL 5 141 | #define MCTL_TRAS 18 142 | #define MCTL_TRC 24 143 | #define MCTL_TRCD 6 144 | #define MCTL_TRRD 4 145 | #define MCTL_TRTP 3 146 | #define MCTL_TWR 6 147 | #define MCTL_TWTR 4 148 | #define MCTL_TEXSR 200 149 | #define MCTL_TXP 2 150 | #define MCTL_TXPDLL 6 151 | #define MCTL_TZQCS 0 152 | #define MCTL_TZQCSI 0 153 | #define MCTL_TDQS 1 154 | #define MCTL_TCKSRE 0 155 | #define MCTL_TCKSRX 0 156 | #define MCTL_TCKE 3 157 | #define MCTL_TMOD 0 158 | #define MCTL_TRSTL 0 159 | #define MCTL_TZQCL 0 160 | #define MCTL_TMRR 2 161 | #define MCTL_TCKESR 2 162 | #define MCTL_TDPD 0 163 | 164 | #define MCTL_MR0 0xa62 165 | #define MCTL_MR1 0x0 166 | #define MCTL_MR2 0x0 167 | #define MCTL_MR3 0x0 168 | 169 | 170 | #elif(MCTL_DDR_TYPE==3) //DDR3-1333 171 | #define MCTL_TREFI 78 172 | #define MCTL_TMRD 4 173 | #define MCTL_TRFC 107 174 | #define MCTL_TRP 9 175 | #define MCTL_TPREA 0 176 | #define MCTL_TRTW 2 177 | #define MCTL_TAL 0 178 | #define MCTL_TCL 9 179 | #define MCTL_TCWL 8 180 | #define MCTL_TRAS 24 181 | #define MCTL_TRC 33 182 | #define MCTL_TRCD 9 183 | #define MCTL_TRRD 4 184 | #define MCTL_TRTP 5 185 | #define MCTL_TWR 10 186 | #define MCTL_TWTR 5 187 | #define MCTL_TEXSR 512 188 | #define MCTL_TXP 5 189 | #define MCTL_TXPDLL 16 190 | #define MCTL_TZQCS 64 191 | #define MCTL_TZQCSI 0 192 | #define MCTL_TDQS 1 193 | #define MCTL_TCKSRE 7 194 | #define MCTL_TCKSRX 7 195 | #define MCTL_TCKE 4 196 | #define MCTL_TMOD 12 197 | #define MCTL_TRSTL 80 198 | #define MCTL_TZQCL 512 199 | #define MCTL_TMRR 2 200 | #define MCTL_TCKESR 5 201 | #define MCTL_TDPD 0 202 | 203 | #define MCTL_MR0 0x1a50 204 | #define MCTL_MR1 0x0 205 | #define MCTL_MR2 0x18 206 | #define MCTL_MR3 0x0 207 | 208 | #elif(MCTL_DDR_TYPE==5) //LPDDR 209 | #else //LPDDR2-800 210 | #define MCTL_TREFI 78 211 | #define MCTL_TMRD 2 212 | #define MCTL_TRFC 52 213 | #define MCTL_TRP 8 214 | #define MCTL_TPREA 0 215 | #define MCTL_TRTW 2 216 | #define MCTL_TAL 0 217 | #define MCTL_TCL 6 218 | #define MCTL_TCWL 4 219 | #define MCTL_TRAS 18 220 | #define MCTL_TRC 27 221 | #define MCTL_TRCD 8 222 | #define MCTL_TRRD 4 223 | #define MCTL_TRTP 3 224 | #define MCTL_TWR 6 225 | #define MCTL_TWTR 3 226 | #define MCTL_TEXSR 200 227 | #define MCTL_TXP 3 228 | #define MCTL_TXPDLL 6 229 | #define MCTL_TZQCS 0 230 | #define MCTL_TZQCSI 0 231 | #define MCTL_TDQS 1 232 | #define MCTL_TCKSRE 5 233 | #define MCTL_TCKSRX 5 234 | #define MCTL_TCKE 3 235 | #define MCTL_TMOD 0 236 | #define MCTL_TRSTL 0 237 | #define MCTL_TZQCL 0 238 | #define MCTL_TMRR 2 239 | #define MCTL_TCKESR 6 240 | #define MCTL_TDPD 0 241 | 242 | #define MCTL_MR0 0x0 243 | #define MCTL_MR1 0x92 244 | #define MCTL_MR2 0x4 245 | #define MCTL_MR3 0x2 246 | 247 | 248 | #endif 249 | 250 | 251 | 252 | #define MCTL_COM_BASE 0x01c62000 253 | #define MCTL_CTL0 0x01c63000 254 | #define MCTL_CTL1 0x01c64000 255 | #define MCTL_PHY0 0x01c65000 256 | #define MCTL_PHY1 0x01c66000 257 | 258 | #define MCTL_CTL_BASE 0x01c63000 259 | #define MCTL_PHY_BASE 0x01c65000 260 | #define MCTL_CCU_BASE 0x01c20000 261 | 262 | 263 | #define SDR_COM_CR (MCTL_COM_BASE + 0x00) 264 | #define SDR_COM_CCR (MCTL_COM_BASE + 0x04) 265 | #define SDR_COM_MFACR (MCTL_COM_BASE + 0x10) 266 | #define SDR_COM_MSACR (MCTL_COM_BASE + 0x30) 267 | #define SDR_COM_MBACR (MCTL_COM_BASE + 0x50) 268 | 269 | #define SDR_SCTL (MCTL_CTL_BASE + 0x04) 270 | #define SDR_SSTAT (MCTL_CTL_BASE + 0x08) 271 | #define SDR_MCMD (MCTL_CTL_BASE + 0x40) 272 | #define SDR_CMDSTAT (MCTL_CTL_BASE + 0x4c) 273 | #define SDR_CMDSTATEN (MCTL_CTL_BASE + 0x50) 274 | #define SDR_MRRCFG0 (MCTL_CTL_BASE + 0x60) 275 | #define SDR_MRRSTAT0 (MCTL_CTL_BASE + 0x64) 276 | #define SDR_MRRSTAT1 (MCTL_CTL_BASE + 0x68) 277 | #define SDR_MCFG1 (MCTL_CTL_BASE + 0x7c) 278 | #define SDR_MCFG (MCTL_CTL_BASE + 0x80) 279 | #define SDR_PPCFG (MCTL_CTL_BASE + 0x84) 280 | #define SDR_MSTAT (MCTL_CTL_BASE + 0x88) 281 | #define SDR_LP2ZQCFG (MCTL_CTL_BASE + 0x8c) 282 | #define SDR_DTUSTAT (MCTL_CTL_BASE + 0x94) 283 | #define SDR_DTUNA (MCTL_CTL_BASE + 0x98) 284 | #define SDR_DTUNE (MCTL_CTL_BASE + 0x9c) 285 | #define SDR_DTUPRD0 (MCTL_CTL_BASE + 0xa0) 286 | #define SDR_DTUPRD1 (MCTL_CTL_BASE + 0xa4) 287 | #define SDR_DTUPRD2 (MCTL_CTL_BASE + 0xa8) 288 | #define SDR_DTUPRD3 (MCTL_CTL_BASE + 0xac) 289 | #define SDR_DTUAWDT (MCTL_CTL_BASE + 0xb0) 290 | #define SDR_TOGCNT1U (MCTL_CTL_BASE + 0xc0) 291 | #define SDR_TOGCNT100N (MCTL_CTL_BASE + 0xcc) 292 | #define SDR_TREFI (MCTL_CTL_BASE + 0xd0) 293 | #define SDR_TMRD (MCTL_CTL_BASE + 0xd4) 294 | #define SDR_TRFC (MCTL_CTL_BASE + 0xd8) 295 | #define SDR_TRP (MCTL_CTL_BASE + 0xdc) 296 | #define SDR_TRTW (MCTL_CTL_BASE + 0xe0) 297 | #define SDR_TAL (MCTL_CTL_BASE + 0xe4) 298 | #define SDR_TCL (MCTL_CTL_BASE + 0xe8) 299 | #define SDR_TCWL (MCTL_CTL_BASE + 0xec) 300 | #define SDR_TRAS (MCTL_CTL_BASE + 0xf0) 301 | #define SDR_TRC (MCTL_CTL_BASE + 0xf4) 302 | #define SDR_TRCD (MCTL_CTL_BASE + 0xf8) 303 | #define SDR_TRRD (MCTL_CTL_BASE + 0xfc) 304 | #define SDR_TRTP (MCTL_CTL_BASE + 0x100) 305 | #define SDR_TWR (MCTL_CTL_BASE + 0x104) 306 | #define SDR_TWTR (MCTL_CTL_BASE + 0x108) 307 | #define SDR_TEXSR (MCTL_CTL_BASE + 0x10c) 308 | #define SDR_TXP (MCTL_CTL_BASE + 0x110) 309 | #define SDR_TXPDLL (MCTL_CTL_BASE + 0x114) 310 | #define SDR_TZQCS (MCTL_CTL_BASE + 0x118) 311 | #define SDR_TZQCSI (MCTL_CTL_BASE + 0x11c) 312 | #define SDR_TDQS (MCTL_CTL_BASE + 0x120) 313 | #define SDR_TCKSRE (MCTL_CTL_BASE + 0x124) 314 | #define SDR_TCKSRX (MCTL_CTL_BASE + 0x128) 315 | #define SDR_TCKE (MCTL_CTL_BASE + 0x12c) 316 | #define SDR_TMOD (MCTL_CTL_BASE + 0x130) 317 | #define SDR_TRSTL (MCTL_CTL_BASE + 0x134) 318 | #define SDR_TZQCL (MCTL_CTL_BASE + 0x138) 319 | #define SDR_TMRR (MCTL_CTL_BASE + 0x13c) 320 | #define SDR_TCKESR (MCTL_CTL_BASE + 0x140) 321 | #define SDR_TDPD (MCTL_CTL_BASE + 0x144) 322 | #define SDR_DTUWACTL (MCTL_CTL_BASE + 0x200) 323 | #define SDR_DTURACTL (MCTL_CTL_BASE + 0x204) 324 | #define SDR_DTUCFG (MCTL_CTL_BASE + 0x208) 325 | #define SDR_DTUECTL (MCTL_CTL_BASE + 0x20c) 326 | #define SDR_DTUWD0 (MCTL_CTL_BASE + 0x210) 327 | #define SDR_DTUWD1 (MCTL_CTL_BASE + 0x214) 328 | #define SDR_DTUWD2 (MCTL_CTL_BASE + 0x218) 329 | #define SDR_DTUWD3 (MCTL_CTL_BASE + 0x21c) 330 | #define SDR_DTUWDM (MCTL_CTL_BASE + 0x220) 331 | #define SDR_DTURD0 (MCTL_CTL_BASE + 0x224) 332 | #define SDR_DTURD1 (MCTL_CTL_BASE + 0x224) 333 | #define SDR_DTURD2 (MCTL_CTL_BASE + 0x22c) 334 | #define SDR_DTURD3 (MCTL_CTL_BASE + 0x230) 335 | #define SDR_DTULFSRWD (MCTL_CTL_BASE + 0x234) 336 | #define SDR_DTULFSRRD (MCTL_CTL_BASE + 0x238) 337 | #define SDR_DTUEAF (MCTL_CTL_BASE + 0x23c) 338 | #define SDR_DFITCTLDLY (MCTL_CTL_BASE + 0x240) 339 | #define SDR_DFIODTCFG (MCTL_CTL_BASE + 0x244) 340 | #define SDR_DFIODTCFG1 (MCTL_CTL_BASE + 0x248) 341 | #define SDR_DFIODTRMAP (MCTL_CTL_BASE + 0x24c) 342 | #define SDR_DFITPHYWRD (MCTL_CTL_BASE + 0x250) 343 | #define SDR_DFITPHYWRL (MCTL_CTL_BASE + 0x254) 344 | #define SDR_DFITRDDEN (MCTL_CTL_BASE + 0x260) 345 | #define SDR_DFITPHYRDL (MCTL_CTL_BASE + 0x264) 346 | #define SDR_DFITPHYUPDTYPE0 (MCTL_CTL_BASE + 0x270) 347 | #define SDR_DFITPHYUPDTYPE1 (MCTL_CTL_BASE + 0x274) 348 | #define SDR_DFITPHYUPDTYPE2 (MCTL_CTL_BASE + 0x278) 349 | #define SDR_DFITPHYUPDTYPE3 (MCTL_CTL_BASE + 0x27c) 350 | 351 | #define SDR_DFITCTRLUPDMIN (MCTL_CTL_BASE + 0x280) 352 | #define SDR_DFITCTRLUPDMAX (MCTL_CTL_BASE + 0x284) 353 | #define SDR_DFITCTRLUPDDLY (MCTL_CTL_BASE + 0x288) 354 | #define SDR_DFIUPDCFG (MCTL_CTL_BASE + 0x290) 355 | #define SDR_DFITREFMSKI (MCTL_CTL_BASE + 0x294) 356 | #define SDR_DFITCRLUPDI (MCTL_CTL_BASE + 0x298) 357 | #define SDR_DFITRCFG0 (MCTL_CTL_BASE + 0x2ac) 358 | #define SDR_DFITRSTAT0 (MCTL_CTL_BASE + 0x2b0) 359 | #define SDR_DFITRWRLVLEN (MCTL_CTL_BASE + 0x2b4) 360 | #define SDR_DFITRRDLVLEN (MCTL_CTL_BASE + 0x2b8) 361 | #define SDR_DFITRRDLVLGATEEN (MCTL_CTL_BASE + 0x2bc) 362 | 363 | #define SDR_DFISTCFG0 (MCTL_CTL_BASE + 0x2c4) 364 | #define SDR_DFISTCFG1 (MCTL_CTL_BASE + 0x2c8) 365 | #define SDR_DFITDRAMCLKEN (MCTL_CTL_BASE + 0x2d0) 366 | #define SDR_DFITDRAMCLKDIS (MCTL_CTL_BASE + 0x2d4) 367 | #define SDR_DFILPCFG0 (MCTL_CTL_BASE + 0x2f0) 368 | 369 | #define SDR_PIR (MCTL_PHY_BASE + 0x04) 370 | #define SDR_PGCR (MCTL_PHY_BASE + 0x08) 371 | #define SDR_PGSR (MCTL_PHY_BASE + 0x0c) 372 | #define SDR_DLLGCR (MCTL_PHY_BASE + 0x10) 373 | #define SDR_ACDLLCR (MCTL_PHY_BASE + 0x14) 374 | #define SDR_PTR0 (MCTL_PHY_BASE + 0x18) 375 | #define SDR_PTR1 (MCTL_PHY_BASE + 0x1c) 376 | #define SDR_PTR2 (MCTL_PHY_BASE + 0x20) 377 | #define SDR_ACIOCR (MCTL_PHY_BASE + 0x24) 378 | #define SDR_DXCCR (MCTL_PHY_BASE + 0x28) 379 | #define SDR_DSGCR (MCTL_PHY_BASE + 0x2c) 380 | #define SDR_DCR (MCTL_PHY_BASE + 0x30) 381 | #define SDR_DTPR0 (MCTL_PHY_BASE + 0x34) 382 | #define SDR_DTPR1 (MCTL_PHY_BASE + 0x38) 383 | #define SDR_DTPR2 (MCTL_PHY_BASE + 0x3c) 384 | #define SDR_MR0 (MCTL_PHY_BASE + 0x40) 385 | #define SDR_MR1 (MCTL_PHY_BASE + 0x44) 386 | #define SDR_MR2 (MCTL_PHY_BASE + 0x48) 387 | #define SDR_MR3 (MCTL_PHY_BASE + 0x4c) 388 | #define SDR_ODTCR (MCTL_PHY_BASE + 0x50) 389 | #define SDR_DTAR (MCTL_PHY_BASE + 0x54) 390 | #define SDR_DTDT0 (MCTL_PHY_BASE + 0x58) 391 | #define SDR_DTDT1 (MCTL_PHY_BASE + 0x5c) 392 | #define SDR_DCUAR (MCTL_PHY_BASE + 0xc0) 393 | #define SDR_DCUDR (MCTL_PHY_BASE + 0xc4) 394 | #define SDR_DCURR (MCTL_PHY_BASE + 0xc8) 395 | #define SDR_DCULR (MCTL_PHY_BASE + 0xcc) 396 | #define SDR_DCUGCR (MCTL_PHY_BASE + 0xd0) 397 | #define SDR_DCUTPR (MCTL_PHY_BASE + 0xd4) 398 | #define SDR_DCUSR0 (MCTL_PHY_BASE + 0xd8) 399 | #define SDR_DCUSR1 (MCTL_PHY_BASE + 0xdc) 400 | #define SDR_BISTRR (MCTL_PHY_BASE + 0x100) 401 | #define SDR_BISTMSKR0 (MCTL_PHY_BASE + 0x104) 402 | #define SDR_BISTMSKR1 (MCTL_PHY_BASE + 0x108) 403 | #define SDR_BISTWCR (MCTL_PHY_BASE + 0x10c) 404 | #define SDR_BISTLSR (MCTL_PHY_BASE + 0x110) 405 | #define SDR_BISTAR0 (MCTL_PHY_BASE + 0x114) 406 | #define SDR_BISTAR1 (MCTL_PHY_BASE + 0x118) 407 | #define SDR_BISTAR2 (MCTL_PHY_BASE + 0x11c) 408 | #define SDR_BISTUDPR (MCTL_PHY_BASE + 0x120) 409 | #define SDR_BISTGSR (MCTL_PHY_BASE + 0x124) 410 | #define SDR_BISTWER (MCTL_PHY_BASE + 0x128) 411 | #define SDR_BISTBER0 (MCTL_PHY_BASE + 0x12c) 412 | #define SDR_BISTBER1 (MCTL_PHY_BASE + 0x130) 413 | #define SDR_BISTBER2 (MCTL_PHY_BASE + 0x134) 414 | #define SDR_BISTWCSR (MCTL_PHY_BASE + 0x138) 415 | #define SDR_BISTFWR0 (MCTL_PHY_BASE + 0x13c) 416 | #define SDR_BISTFWR1 (MCTL_PHY_BASE + 0x140) 417 | #define SDR_ZQ0CR0 (MCTL_PHY_BASE + 0x180) 418 | #define SDR_ZQ0CR1 (MCTL_PHY_BASE + 0x184) 419 | #define SDR_ZQ0SR0 (MCTL_PHY_BASE + 0x188) 420 | #define SDR_ZQ0SR1 (MCTL_PHY_BASE + 0x18c) 421 | #define SDR_DX0GCR (MCTL_PHY_BASE + 0x1c0) 422 | #define SDR_DX0GSR0 (MCTL_PHY_BASE + 0x1c4) 423 | #define SDR_DX0GSR1 (MCTL_PHY_BASE + 0x1c8) 424 | #define SDR_DX0DLLCR (MCTL_PHY_BASE + 0x1cc) 425 | #define SDR_DX0DQTR (MCTL_PHY_BASE + 0x1d0) 426 | #define SDR_DX0DQSTR (MCTL_PHY_BASE + 0x1d4) 427 | #define SDR_DX1GCR (MCTL_PHY_BASE + 0x200) 428 | #define SDR_DX1GSR0 (MCTL_PHY_BASE + 0x204) 429 | #define SDR_DX1GSR1 (MCTL_PHY_BASE + 0x208) 430 | #define SDR_DX1DLLCR (MCTL_PHY_BASE + 0x20c) 431 | #define SDR_DX1DQTR (MCTL_PHY_BASE + 0x210) 432 | #define SDR_DX1DQSTR (MCTL_PHY_BASE + 0x214) 433 | #define SDR_DX2GCR (MCTL_PHY_BASE + 0x240) 434 | #define SDR_DX2GSR0 (MCTL_PHY_BASE + 0x244) 435 | #define SDR_DX2GSR1 (MCTL_PHY_BASE + 0x248) 436 | #define SDR_DX2DLLCR (MCTL_PHY_BASE + 0x24c) 437 | #define SDR_DX2DQTR (MCTL_PHY_BASE + 0x250) 438 | #define SDR_DX2DQSTR (MCTL_PHY_BASE + 0x254) 439 | #define SDR_DX3GCR (MCTL_PHY_BASE + 0x280) 440 | #define SDR_DX3GSR0 (MCTL_PHY_BASE + 0x284) 441 | #define SDR_DX3GSR1 (MCTL_PHY_BASE + 0x288) 442 | #define SDR_DX3DLLCR (MCTL_PHY_BASE + 0x28c) 443 | #define SDR_DX3DQTR (MCTL_PHY_BASE + 0x290) 444 | #define SDR_DX3DQSTR (MCTL_PHY_BASE + 0x294) 445 | 446 | 447 | #define CCU_PLL5CFG (MCTL_CCU_BASE + 0x20) 448 | #define CCU_AXIGATE (MCTL_CCU_BASE + 0x5c) 449 | #define CCU_AHBGATE0 (MCTL_CCU_BASE + 0x60) 450 | #define CCU_AHBGATE1 (MCTL_CCU_BASE + 0x64) 451 | #define CCU_MDFS_CLK (MCTL_CCU_BASE + 0xf0) 452 | #define CCU_MDFS_CFG (MCTL_CCU_BASE + 0xf4) 453 | #define CCU_AHB1_RST (MCTL_CCU_BASE + 0x2c0) 454 | 455 | #define mctl_read_w(n) (*((volatile uint32 *)(n))) 456 | #define mctl_write_w(n,c) (*((volatile uint32 *)(n)) = (c)) 457 | 458 | extern uint32 mctl_sys_init(void); 459 | extern uint32 mctl_reset_release(void); 460 | 461 | #endif /*SUNXI_DRAM_H*/ 462 | 463 | 464 | 465 | -------------------------------------------------------------------------------- /dram_sun6i.c: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2007-2012 3 | * Allwinner Technology Co., Ltd. 4 | * Berg Xing 5 | * Tom Cubie 6 | * 7 | * Sunxi platform dram controller init. 8 | * 9 | * See file CREDITS for list of people who contributed to this 10 | * project. 11 | * 12 | * This program is free software; you can redistribute it and/or 13 | * modify it under the terms of the GNU General Public License as 14 | * published by the Free Software Foundation; either version 2 of 15 | * the License, or (at your option) any later version. 16 | * 17 | * This program is distributed in the hope that it will be useful, 18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 | * GNU General Public License for more details. 21 | * 22 | * You should have received a copy of the GNU General Public License 23 | * along with this program; if not, write to the Free Software 24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 | * MA 02111-1307 USA 26 | */ 27 | #include "io.h" 28 | #include "dram.h" 29 | 30 | extern void puts(char *s); 31 | 32 | 33 | //***************************************************************************** 34 | // Allwinner Technology, All Right Reserved. 2006-2010 Copyright (c) 35 | // 36 | // File: mctl_hal.c 37 | // 38 | // Description: This file implements basic functions for AW1633 DRAM controller 39 | // 40 | // History: 41 | // 2012/02/06 Berg Xing 0.10 Initial version 42 | // 2012/02/24 Berg Xing 0.20 Supprot 2 channel 43 | // 2012/02/27 Berg Xing 0.30 modify mode register access 44 | // 2012/03/01 Berg Xing 0.40 add LPDDR2 45 | // 2012/03/10 Berg Xing 0.50 add mctl_dll_init() function 46 | //***************************************************************************** 47 | void aw_delay (u32 n) 48 | { 49 | while(n--); 50 | } 51 | uint32 mctl_sys_init(void) 52 | { 53 | uint32 reg_val; 54 | 55 | //PLL5 enable 56 | reg_val = mctl_read_w(CCU_PLL5CFG); 57 | reg_val |= 0x1U<<31; 58 | reg_val |= 0x1U<<20; 59 | mctl_write_w(CCU_PLL5CFG, reg_val); 60 | #ifndef SYSTEM_SIMULATION 61 | aw_delay(0x20); 62 | #endif 63 | 64 | //MDFS clock enable 65 | reg_val = mctl_read_w(CCU_MDFS_CLK); 66 | reg_val |= 0x1U<<31; 67 | mctl_write_w(CCU_MDFS_CLK, reg_val); 68 | 69 | //select DRAM clock 70 | reg_val = mctl_read_w(CCU_MDFS_CFG); 71 | reg_val |= 0x1U<<16; 72 | mctl_write_w(CCU_MDFS_CFG, reg_val); 73 | 74 | //release DRAMC register reset 75 | reg_val = mctl_read_w(CCU_AHB1_RST); 76 | reg_val |= 0x1<<14; 77 | mctl_write_w(CCU_AHB1_RST, reg_val); 78 | 79 | //DRAMC AHB clok on 80 | reg_val = mctl_read_w(CCU_AHBGATE0); 81 | reg_val |= 0x1<<14; 82 | mctl_write_w(CCU_AHBGATE0, reg_val); 83 | 84 | return (1); 85 | } 86 | 87 | uint32 mctl_reset_release(void) 88 | { 89 | uint32 reg_val; 90 | 91 | reg_val = mctl_read_w(CCU_MDFS_CFG); 92 | reg_val |= 0x1U<<31; 93 | mctl_write_w(CCU_MDFS_CFG, reg_val); 94 | #ifndef SYSTEM_SIMULATION 95 | aw_delay(0x20); 96 | #endif 97 | 98 | return (1); 99 | } 100 | 101 | uint32 mctl_dll_init(uint32 ch_index) 102 | { 103 | uint32 ch_id; 104 | 105 | if(ch_index == 1) 106 | ch_id = 0x1000; 107 | else 108 | ch_id = 0x0; 109 | 110 | //*********************************************** 111 | // set dram PHY register 112 | //*********************************************** 113 | //reset dll 114 | mctl_write_w(ch_id + SDR_ACDLLCR,0x80000000); 115 | mctl_write_w(ch_id + SDR_DX0DLLCR,0x80000000); 116 | mctl_write_w(ch_id + SDR_DX1DLLCR,0x80000000); 117 | mctl_write_w(ch_id + SDR_DX2DLLCR,0x80000000); 118 | mctl_write_w(ch_id + SDR_DX3DLLCR,0x80000000); 119 | #ifndef SYSTEM_SIMULATION 120 | aw_delay(0x10); 121 | #endif 122 | //enable dll 123 | mctl_write_w(ch_id + SDR_ACDLLCR,0x0); 124 | mctl_write_w(ch_id + SDR_DX0DLLCR,0x0); 125 | mctl_write_w(ch_id + SDR_DX1DLLCR,0x0); 126 | mctl_write_w(ch_id + SDR_DX2DLLCR,0x0); 127 | mctl_write_w(ch_id + SDR_DX3DLLCR,0x0); 128 | #ifndef SYSTEM_SIMULATION 129 | aw_delay(0x10); 130 | #endif 131 | //release reset dll 132 | mctl_write_w(ch_id + SDR_ACDLLCR,0x40000000); 133 | mctl_write_w(ch_id + SDR_DX0DLLCR,0x40000000); 134 | mctl_write_w(ch_id + SDR_DX1DLLCR,0x40000000); 135 | mctl_write_w(ch_id + SDR_DX2DLLCR,0x40000000); 136 | mctl_write_w(ch_id + SDR_DX3DLLCR,0x40000000); 137 | #ifndef SYSTEM_SIMULATION 138 | aw_delay(0x10); 139 | #endif 140 | 141 | return (1); 142 | } 143 | 144 | uint32 mctl_channel_init(uint32 ch_index) 145 | { 146 | uint32 reg_val; 147 | uint32 clkmhz; 148 | uint32 ch_id; 149 | 150 | if(ch_index == 1) 151 | ch_id = 0x1000; 152 | else 153 | ch_id = 0x0; 154 | 155 | //set PHY genereral configuration register 156 | reg_val = 0x01042202; 157 | mctl_write_w(ch_id + SDR_PGCR, reg_val); 158 | 159 | //set mode register 160 | mctl_write_w(ch_id + SDR_MR0, MCTL_MR0); 161 | mctl_write_w(ch_id + SDR_MR1, MCTL_MR1); 162 | mctl_write_w(ch_id + SDR_MR2, MCTL_MR2); 163 | mctl_write_w(ch_id + SDR_MR3, MCTL_MR3); 164 | 165 | //set PHY DDR mode 166 | if(MCTL_DDR_TYPE==2) //DDR2 167 | reg_val = 0xa; 168 | else if(MCTL_DDR_TYPE==3) //DDR3 169 | reg_val = 0xb; 170 | else if(MCTL_DDR_TYPE==5) //LPDDR 171 | reg_val = 0x8; 172 | else //LPDDR2 173 | reg_val = 0xc; 174 | mctl_write_w(ch_id + SDR_DCR, reg_val); 175 | 176 | #ifndef FPGA_PLATFORM 177 | //set DDR system general configuration register 178 | reg_val = 0xd200013b; 179 | mctl_write_w(ch_id + SDR_DSGCR, reg_val); 180 | 181 | //set DATX8 common configuration register 182 | reg_val = 0x910; 183 | mctl_write_w(ch_id + SDR_DXCCR, reg_val); 184 | #endif 185 | 186 | //set COM sclk enable register 187 | reg_val = mctl_read_w(SDR_COM_CCR); 188 | reg_val |= (0x4 | (0x1< 4 | * Tom Cubie 5 | * 6 | * See file CREDITS for list of people who contributed to this 7 | * project. 8 | * 9 | * This program is free software; you can redistribute it and/or 10 | * modify it under the terms of the GNU General Public License as 11 | * published by the Free Software Foundation; either version 2 of 12 | * the License, or (at your option) any later version. 13 | * 14 | * This program is distributed in the hope that it will be useful, 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | * GNU General Public License for more details. 18 | * 19 | * You should have received a copy of the GNU General Public License 20 | * along with this program; if not, write to the Free Software 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 | * MA 02111-1307 USA 23 | */ 24 | 25 | #include "cpu.h" 26 | #include "io.h" 27 | #include "gpio.h" 28 | 29 | int sunxi_gpio_set_cfgpin(u32 pin, u32 val) { 30 | 31 | u32 cfg; 32 | u32 bank = GPIO_BANK(pin); 33 | u32 index = GPIO_CFG_INDEX(pin); 34 | u32 offset = GPIO_CFG_OFFSET(pin); 35 | 36 | struct sunxi_gpio *pio = 37 | &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; 38 | 39 | cfg = readl(&pio->cfg[0] + index); 40 | cfg &= ~(0xf << offset); 41 | cfg |= val << offset; 42 | 43 | writel(cfg, &pio->cfg[0] + index); 44 | 45 | return 0; 46 | } 47 | 48 | int sunxi_gpio_get_cfgpin(u32 pin) { 49 | 50 | u32 cfg; 51 | u32 bank = GPIO_BANK(pin); 52 | u32 index = GPIO_CFG_INDEX(pin); 53 | u32 offset = GPIO_CFG_OFFSET(pin); 54 | 55 | struct sunxi_gpio *pio = 56 | &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; 57 | 58 | cfg = readl(&pio->cfg[0] + index); 59 | cfg >>= offset; 60 | 61 | return (cfg & 0xf); 62 | } 63 | 64 | int sunxi_gpio_output(u32 pin, u32 val) { 65 | 66 | u32 dat; 67 | u32 bank = GPIO_BANK(pin); 68 | u32 num = GPIO_NUM(pin); 69 | 70 | struct sunxi_gpio *pio = 71 | &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; 72 | 73 | dat = readl(&pio->dat); 74 | if(val) 75 | dat |= 1 << num; 76 | else 77 | dat &= ~(1 << num); 78 | 79 | writel(dat, &pio->dat); 80 | 81 | return 0; 82 | } 83 | 84 | int sunxi_gpio_input(u32 pin) { 85 | 86 | u32 dat; 87 | u32 bank = GPIO_BANK(pin); 88 | u32 num = GPIO_NUM(pin); 89 | 90 | struct sunxi_gpio *pio = 91 | &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank]; 92 | 93 | dat = readl(&pio->dat); 94 | dat >>= num; 95 | 96 | return (dat & 0x1); 97 | } 98 | 99 | int gpio_request(unsigned gpio, const char *label) { 100 | 101 | return 0; 102 | } 103 | 104 | int gpio_free(unsigned gpio) { 105 | 106 | return 0; 107 | } 108 | 109 | int gpio_direction_input(unsigned gpio) { 110 | 111 | sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_INPUT); 112 | return sunxi_gpio_input(gpio); 113 | } 114 | 115 | int gpio_direction_output(unsigned gpio, int value) { 116 | 117 | sunxi_gpio_set_cfgpin(gpio, SUNXI_GPIO_OUTPUT); 118 | return sunxi_gpio_output(gpio, value); 119 | } 120 | 121 | int gpio_get_value(unsigned gpio) { 122 | 123 | return sunxi_gpio_input(gpio); 124 | } 125 | 126 | int gpio_set_value(unsigned gpio, int value) { 127 | 128 | return sunxi_gpio_output(gpio, value); 129 | } 130 | -------------------------------------------------------------------------------- /gpio.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2007-2012 3 | * Allwinner Technology Co., Ltd. 4 | * Tom Cubie 5 | * 6 | * See file CREDITS for list of people who contributed to this 7 | * project. 8 | * 9 | * This program is free software; you can redistribute it and/or 10 | * modify it under the terms of the GNU General Public License as 11 | * published by the Free Software Foundation; either version 2 of 12 | * the License, or (at your option) any later version. 13 | * 14 | * This program is distributed in the hope that it will be useful, 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 | * GNU General Public License for more details. 18 | * 19 | * You should have received a copy of the GNU General Public License 20 | * along with this program; if not, write to the Free Software 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 | * MA 02111-1307 USA 23 | */ 24 | 25 | #ifndef _SUNXI_GPIO_H 26 | #define _SUNXI_GPIO_H 27 | 28 | #include "type.h" 29 | 30 | /* 31 | * sun6i has 10 banks of gpio, they are: 32 | * PA0 - PA27 | PB0 - PB7 | PC0 - PC27 33 | * PD0 - PD27 | PE0 - PE16 | PF0 - PF5 34 | * PG0 - PG18 | PH0 - PH30 | PL0 - PL8 35 | * PM0 - PM7 36 | */ 37 | 38 | #define SUNXI_GPIO_A 0 39 | #define SUNXI_GPIO_B 1 40 | #define SUNXI_GPIO_C 2 41 | #define SUNXI_GPIO_D 3 42 | #define SUNXI_GPIO_E 4 43 | #define SUNXI_GPIO_F 5 44 | #define SUNXI_GPIO_G 6 45 | #define SUNXI_GPIO_H 7 46 | #define SUNXI_GPIO_I 8 47 | 48 | struct sunxi_gpio { 49 | u32 cfg[4]; 50 | u32 dat; 51 | u32 drv[2]; 52 | u32 pull[2]; 53 | }; 54 | 55 | /* gpio interrupt control */ 56 | struct sunxi_gpio_int { 57 | u32 cfg[3]; 58 | u32 ctl; 59 | u32 sta; 60 | u32 deb; /* interrupt debounce */ 61 | }; 62 | 63 | struct sunxi_gpio_reg { 64 | struct sunxi_gpio gpio_bank[10]; 65 | u8 res[0xbc]; 66 | struct sunxi_gpio_int gpio_int; 67 | }; 68 | 69 | #define GPIO_BANK(pin) ((pin) >> 5) 70 | #define GPIO_NUM(pin) ((pin) & 0x1F) 71 | 72 | #define GPIO_CFG_INDEX(pin) (((pin) & 0x1F) >> 3) 73 | #define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1F) & 0x7) << 2) 74 | 75 | /* GPIO bank sizes */ 76 | #define SUNXI_GPIO_A_NR (32) 77 | #define SUNXI_GPIO_B_NR (32) 78 | #define SUNXI_GPIO_C_NR (32) 79 | #define SUNXI_GPIO_D_NR (32) 80 | #define SUNXI_GPIO_E_NR (32) 81 | #define SUNXI_GPIO_F_NR (32) 82 | #define SUNXI_GPIO_G_NR (32) 83 | #define SUNXI_GPIO_H_NR (32) 84 | #define SUNXI_GPIO_I_NR (32) 85 | 86 | #define SUNXI_GPIO_NEXT(__gpio) \ 87 | ((__gpio##_START) + (__gpio##_NR) + 0) 88 | 89 | enum sunxi_gpio_number { 90 | SUNXI_GPIO_A_START = 0, 91 | SUNXI_GPIO_B_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_A), 92 | SUNXI_GPIO_C_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_B), 93 | SUNXI_GPIO_D_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_C), 94 | SUNXI_GPIO_E_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_D), 95 | SUNXI_GPIO_F_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_E), 96 | SUNXI_GPIO_G_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_F), 97 | SUNXI_GPIO_H_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_G), 98 | SUNXI_GPIO_I_START = SUNXI_GPIO_NEXT(SUNXI_GPIO_H), 99 | }; 100 | 101 | /* SUNXI GPIO number definitions */ 102 | #define SUNXI_GPA(_nr) (SUNXI_GPIO_A_START + (_nr)) 103 | #define SUNXI_GPB(_nr) (SUNXI_GPIO_B_START + (_nr)) 104 | #define SUNXI_GPC(_nr) (SUNXI_GPIO_C_START + (_nr)) 105 | #define SUNXI_GPD(_nr) (SUNXI_GPIO_D_START + (_nr)) 106 | #define SUNXI_GPE(_nr) (SUNXI_GPIO_E_START + (_nr)) 107 | #define SUNXI_GPF(_nr) (SUNXI_GPIO_F_START + (_nr)) 108 | #define SUNXI_GPG(_nr) (SUNXI_GPIO_G_START + (_nr)) 109 | #define SUNXI_GPH(_nr) (SUNXI_GPIO_H_START + (_nr)) 110 | #define SUNXI_GPI(_nr) (SUNXI_GPIO_I_START + (_nr)) 111 | 112 | /* GPIO pin function config */ 113 | #define SUNXI_GPIO_INPUT (0) 114 | #define SUNXI_GPIO_OUTPUT (1) 115 | 116 | #define SUNXI_GPA0_ERXD3 (2) 117 | #define SUNXI_GPA0_SPI1_CS0 (3) 118 | #define SUNXI_GPA0_UART2_RTS (4) 119 | 120 | #define SUNXI_GPA1_ERXD2 (2) 121 | #define SUNXI_GPA1_SPI1_CLK (3) 122 | #define SUNXI_GPA1_UART2_CTS (4) 123 | 124 | #define SUNXI_GPA2_ERXD1 (2) 125 | #define SUNXI_GPA2_SPI1_MOSI (3) 126 | #define SUNXI_GPA2_UART2_TX (4) 127 | 128 | #define SUNXI_GPA10_UART1_TX (4) 129 | #define SUNXI_GPA11_UART1_RX (4) 130 | 131 | #define SUN4I_GPB22_UART0_TX (2) 132 | #define SUN4I_GPB23_UART0_RX (2) 133 | 134 | #define SUN5I_GPG3_UART0_TX (4) 135 | #define SUN5I_GPG4_UART0_RX (4) 136 | 137 | #define SUNXI_GPC2_NCLE (2) 138 | #define SUNXI_GPC2_SPI0_CLK (3) 139 | 140 | #define SUNXI_GPC6_NRB0 (2) 141 | #define SUNXI_GPC6_SDC2_CMD (3) 142 | 143 | #define SUNXI_GPC7_NRB1 (2) 144 | #define SUNXI_GPC7_SDC2_CLK (3) 145 | 146 | #define SUNXI_GPC8_NDQ0 (2) 147 | #define SUNXI_GPC8_SDC2_D0 (3) 148 | 149 | #define SUNXI_GPC9_NDQ1 (2) 150 | #define SUNXI_GPC9_SDC2_D1 (3) 151 | 152 | #define SUNXI_GPC10_NDQ2 (2) 153 | #define SUNXI_GPC10_SDC2_D2 (3) 154 | 155 | #define SUNXI_GPC11_NDQ3 (2) 156 | #define SUNXI_GPC11_SDC2_D3 (3) 157 | 158 | #define SUNXI_GPF2_SDC0_CLK (2) 159 | #define SUNXI_GPF2_UART0_TX (4) 160 | 161 | #define SUNXI_GPF4_SDC0_D3 (2) 162 | #define SUNXI_GPF4_UART0_RX (4) 163 | 164 | #define SUN8I_H3_GPA_UART0 2 165 | 166 | int sunxi_gpio_set_cfgpin(u32 pin, u32 val); 167 | int sunxi_gpio_get_cfgpin(u32 pin); 168 | int sunxi_gpio_output(u32 pin, u32 val); 169 | int sunxi_gpio_input(u32 pin); 170 | 171 | #endif /* _SUNXI_GPIO_H */ 172 | -------------------------------------------------------------------------------- /instruction_tests.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Stefan Kristiansson 3 | * 4 | * This program is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU General Public License as 6 | * published by the Free Software Foundation; either version 2 of 7 | * the License, or (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 | * MA 02111-1307 USA 18 | */ 19 | #ifndef _INSTRUCTION_TESTS_H 20 | #define _INSTRUCTION_TESTS_H 21 | extern volatile unsigned int illegal_instruction; 22 | 23 | static int test_addc(void) 24 | { 25 | volatile unsigned int ra = 1, rb = 1, rd; 26 | 27 | illegal_instruction = 0; 28 | asm volatile("l.addc %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 29 | 30 | return !illegal_instruction; 31 | } 32 | 33 | static int test_cmov(void) 34 | { 35 | volatile unsigned int ra = 1, rb = 1, rd; 36 | 37 | illegal_instruction = 0; 38 | asm volatile("l.cmov %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 39 | 40 | return !illegal_instruction; 41 | } 42 | 43 | static int test_cust1(void) 44 | { 45 | illegal_instruction = 0; 46 | asm volatile("l.cust1"); 47 | } 48 | 49 | static int test_cust2(void) 50 | { 51 | illegal_instruction = 0; 52 | asm volatile("l.cust2"); 53 | } 54 | 55 | static int test_cust3(void) 56 | { 57 | illegal_instruction = 0; 58 | asm volatile("l.cust3"); 59 | } 60 | 61 | static int test_cust4(void) 62 | { 63 | illegal_instruction = 0; 64 | asm volatile("l.cust4"); 65 | } 66 | 67 | static int test_cust5(void) 68 | { 69 | illegal_instruction = 0; 70 | asm volatile("l.cust5"); 71 | } 72 | 73 | static int test_cust6(void) 74 | { 75 | illegal_instruction = 0; 76 | asm volatile("l.cust6"); 77 | } 78 | 79 | static int test_cust7(void) 80 | { 81 | illegal_instruction = 0; 82 | asm volatile("l.cust7"); 83 | } 84 | 85 | static int test_cust8(void) 86 | { 87 | illegal_instruction = 0; 88 | asm volatile("l.cust8"); 89 | } 90 | 91 | static int test_div(void) 92 | { 93 | volatile unsigned int ra = 1, rb = 1, rd; 94 | 95 | illegal_instruction = 0; 96 | asm volatile("l.div %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 97 | 98 | return !illegal_instruction; 99 | } 100 | 101 | static int test_divu(void) 102 | { 103 | volatile unsigned int ra = 1, rb = 1, rd; 104 | 105 | illegal_instruction = 0; 106 | asm volatile("l.divu %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 107 | 108 | return !illegal_instruction; 109 | } 110 | 111 | static int test_extbs(void) 112 | { 113 | volatile unsigned int ra = 1, rd; 114 | 115 | illegal_instruction = 0; 116 | asm volatile("l.extbs %0,%1" : "=r" (rd) : "r" (ra)); 117 | 118 | return !illegal_instruction; 119 | } 120 | 121 | static int test_extbz(void) 122 | { 123 | volatile unsigned int ra = 1, rd; 124 | 125 | illegal_instruction = 0; 126 | asm volatile("l.extbz %0,%1" : "=r" (rd) : "r" (ra)); 127 | 128 | return !illegal_instruction; 129 | } 130 | 131 | static int test_exths(void) 132 | { 133 | volatile unsigned int ra = 1, rd; 134 | 135 | illegal_instruction = 0; 136 | asm volatile("l.exths %0,%1" : "=r" (rd) : "r" (ra)); 137 | 138 | return !illegal_instruction; 139 | } 140 | 141 | static int test_exthz(void) 142 | { 143 | volatile unsigned int ra = 1, rd; 144 | 145 | illegal_instruction = 0; 146 | asm volatile("l.exthz %0,%1" : "=r" (rd) : "r" (ra)); 147 | 148 | return !illegal_instruction; 149 | } 150 | 151 | static int test_extws(void) 152 | { 153 | volatile unsigned int ra = 1, rd; 154 | 155 | illegal_instruction = 0; 156 | asm volatile("l.exths %0,%1" : "=r" (rd) : "r" (ra)); 157 | 158 | return !illegal_instruction; 159 | } 160 | 161 | static int test_extwz(void) 162 | { 163 | volatile unsigned int ra = 1, rd; 164 | 165 | illegal_instruction = 0; 166 | asm volatile("l.exthz %0,%1" : "=r" (rd) : "r" (ra)); 167 | 168 | return !illegal_instruction; 169 | } 170 | 171 | static int test_ff1(void) 172 | { 173 | volatile unsigned int ra = 1, rd; 174 | 175 | illegal_instruction = 0; 176 | asm volatile("l.ff1 %0,%1" : "=r" (rd) : "r" (ra)); 177 | 178 | return !illegal_instruction; 179 | } 180 | 181 | static int test_fl1(void) 182 | { 183 | volatile unsigned int ra = 1, rd; 184 | 185 | illegal_instruction = 0; 186 | asm volatile("l.fl1 %0,%1" : "=r" (rd) : "r" (ra)); 187 | 188 | return !illegal_instruction; 189 | } 190 | 191 | static int test_lws(void) 192 | { 193 | volatile unsigned int ra = 0, rd; 194 | 195 | illegal_instruction = 0; 196 | asm volatile("l.lws %0,0(%1)" : "=r" (rd) : "r" (ra)); 197 | 198 | return !illegal_instruction; 199 | } 200 | 201 | static int test_mac(void) 202 | { 203 | volatile unsigned int ra = 1, rb = 1; 204 | 205 | illegal_instruction = 0; 206 | asm volatile("l.mac %0,%1" : : "r" (ra), "r" (rb)); 207 | 208 | return !illegal_instruction; 209 | } 210 | 211 | static int test_maci(void) 212 | { 213 | volatile unsigned int rd; 214 | 215 | illegal_instruction = 0; 216 | asm volatile("l.maci %0,1" : "=r" (rd)); 217 | 218 | return !illegal_instruction; 219 | } 220 | 221 | static int test_macrc(void) 222 | { 223 | volatile unsigned int rd; 224 | 225 | illegal_instruction = 0; 226 | asm volatile("l.macrc %0" : "=r" (rd)); 227 | 228 | return !illegal_instruction; 229 | } 230 | 231 | static int test_macu(void) 232 | { 233 | volatile unsigned int ra = 1, rb = 1; 234 | 235 | illegal_instruction = 0; 236 | asm volatile("l.macu %0,%1" : : "r" (ra), "r" (rb)); 237 | 238 | return !illegal_instruction; 239 | } 240 | 241 | 242 | static int test_mul(void) 243 | { 244 | volatile unsigned int ra = 1, rb = 1, rd; 245 | 246 | illegal_instruction = 0; 247 | asm volatile("l.mul %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 248 | 249 | return !illegal_instruction; 250 | } 251 | 252 | static int test_muli(void) 253 | { 254 | volatile unsigned int ra = 1, rd; 255 | 256 | illegal_instruction = 0; 257 | asm volatile("l.muli %0,%1,1" : "=r" (rd) : "r" (ra)); 258 | 259 | return !illegal_instruction; 260 | } 261 | 262 | static int test_mulu(void) 263 | { 264 | volatile unsigned int ra = 1, rb = 1, rd; 265 | 266 | illegal_instruction = 0; 267 | asm volatile("l.mulu %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 268 | 269 | return !illegal_instruction; 270 | } 271 | 272 | static int test_ror(void) 273 | { 274 | volatile unsigned int ra = 1, rb = 1, rd; 275 | 276 | illegal_instruction = 0; 277 | asm volatile("l.ror %0,%1,%2" : "=r" (rd) : "r" (ra), "r" (rb)); 278 | 279 | return !illegal_instruction; 280 | } 281 | 282 | static int test_rori(void) 283 | { 284 | volatile unsigned int ra = 1, rd; 285 | 286 | illegal_instruction = 0; 287 | asm volatile("l.rori %0,%1,1" : "=r" (rd) : "r" (ra)); 288 | 289 | return !illegal_instruction; 290 | } 291 | #endif 292 | -------------------------------------------------------------------------------- /io.h: -------------------------------------------------------------------------------- 1 | /** 2 | * io.h - definition for registers of ccmu controller 3 | * date: 2012-2-13 8:42:56 4 | * author: Aaron 5 | * history: V0.1 6 | */ 7 | #ifndef __IO_H 8 | #define __IO_H 9 | #include "type.h" 10 | 11 | #define get_bvalue(addr) (*((volatile unsigned char *)(addr))) 12 | #define put_bvalue(addr, v) (*((volatile unsigned char *)(addr)) = (unsigned char)(v)) 13 | #define get_hvalue(addr) (*((volatile unsigned short *)(addr))) 14 | #define put_hvalue(addr, v) (*((volatile unsigned short *)(addr)) = (unsigned short)(v)) 15 | #define get_wvalue(addr) (*((volatile unsigned long *)(addr))) 16 | #define put_wvalue(addr, v) (*((volatile unsigned long *)(addr)) = (unsigned long)(v)) 17 | 18 | #define set_bit(addr, v) (*((volatile unsigned char *)(addr)) |= (unsigned char)(v)) 19 | #define clr_bit(addr, v) (*((volatile unsigned char *)(addr)) &= ~(unsigned char)(v)) 20 | #define set_bbit(addr, v) (*((volatile unsigned char *)(addr)) |= (unsigned char)(v)) 21 | #define clr_bbit(addr, v) (*((volatile unsigned char *)(addr)) &= ~(unsigned char)(v)) 22 | #define set_hbit(addr, v) (*((volatile unsigned short *)(addr)) |= (unsigned short)(v)) 23 | #define clr_hbit(addr, v) (*((volatile unsigned short *)(addr)) &= ~(unsigned short)(v)) 24 | #define set_wbit(addr, v) (*((volatile unsigned long *)(addr)) |= (unsigned long)(v)) 25 | #define clr_wbit(addr, v) (*((volatile unsigned long *)(addr)) &= ~(unsigned long)(v)) 26 | 27 | #define cmp_wvalue(addr, v) (v == (*((volatile unsigned long *) (addr)))) 28 | 29 | #define readb(addr) (*((volatile unsigned char *)(addr))) 30 | #define readw(addr) (*((volatile unsigned short *)(addr))) 31 | #define readl(addr) (*((volatile unsigned long *)(addr))) 32 | #define writeb(v, addr) (*((volatile unsigned char *)(addr)) = (unsigned char)(v)) 33 | #define writew(v, addr) (*((volatile unsigned short *)(addr)) = (unsigned short)(v)) 34 | #define writel(v, addr) (*((volatile unsigned long *)(addr)) = (unsigned long)(v)) 35 | 36 | /** 37 | * sr32 - clear & set a value in a bit range for a 32 bit address 38 | */ 39 | static __inline void sr32_aw(u32 addr, u32 start_bit, u32 num_bits, u32 value) 40 | { 41 | uint32_t tmp, msk = (1 << num_bits) - 1; 42 | tmp = readl(addr) & ~(msk << start_bit); 43 | tmp |= value << start_bit; 44 | writel(tmp, addr); 45 | } 46 | 47 | /***************************************************************** 48 | * sr32 - clear & set a value in a bit range for a 32 bit address 49 | *****************************************************************/ 50 | static __inline void sr32(void *addr, u32 start_bit, u32 num_bits, u32 value) 51 | { 52 | u32 tmp, msk = 0; 53 | msk = 1 << num_bits; 54 | --msk; 55 | tmp = readl((u32)addr) & ~(msk << start_bit); 56 | tmp |= value << start_bit; 57 | writel(tmp, (u32)addr); 58 | } 59 | 60 | #endif 61 | -------------------------------------------------------------------------------- /main.c: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Stefan Kristiansson 3 | * 4 | * This program is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU General Public License as 6 | * published by the Free Software Foundation; either version 2 of 7 | * the License, or (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 | * MA 02111-1307 USA 18 | */ 19 | 20 | #include 21 | #include "cpu.h" 22 | #include "io.h" 23 | #include "gpio.h" 24 | #include "uart.h" 25 | #include "timer.h" 26 | #include "dram.h" 27 | #include "clock.h" 28 | #include "spr.h" 29 | #include "instruction_tests.h" 30 | 31 | #define print_spr(spr) \ 32 | puts(#spr); \ 33 | puts(" = 0x"); \ 34 | put_hex(mfspr(spr)); \ 35 | puts("\n"); 36 | 37 | void putchar(char c) 38 | { 39 | uart0_putc(c); 40 | } 41 | 42 | void puts(char *str) 43 | { 44 | uart0_puts(str); 45 | } 46 | 47 | static char nibble_to_hex(unsigned char byte) 48 | { 49 | switch (byte) { 50 | default: 51 | case 0x0: 52 | return '0'; 53 | case 0x1: 54 | return '1'; 55 | case 0x2: 56 | return '2'; 57 | case 0x3: 58 | return '3'; 59 | case 0x4: 60 | return '4'; 61 | case 0x5: 62 | return '5'; 63 | case 0x6: 64 | return '6'; 65 | case 0x7: 66 | return '7'; 67 | case 0x8: 68 | return '8'; 69 | case 0x9: 70 | return '9'; 71 | case 0xa: 72 | return 'a'; 73 | case 0xb: 74 | return 'b'; 75 | case 0xc: 76 | return 'c'; 77 | case 0xd: 78 | return 'd'; 79 | case 0xe: 80 | return 'e'; 81 | case 0xf: 82 | return 'f'; 83 | } 84 | } 85 | 86 | static void put_hex(unsigned int hex) 87 | { 88 | int i; 89 | 90 | for (i = 0; i < 8; i++) { 91 | uart0_putc(nibble_to_hex((hex & 0xf0000000)>>28)); 92 | hex <<= 4; 93 | } 94 | } 95 | 96 | #define BUF_LEN 12 97 | static void put_uint(unsigned int value) 98 | { 99 | char buf[BUF_LEN]; 100 | char *p = &buf[BUF_LEN-1]; 101 | 102 | *p = '\0'; 103 | 104 | if (!value) 105 | *--p = '0'; 106 | 107 | while (value) { 108 | *--p = '0' + value%10; 109 | value /= 10; 110 | } 111 | 112 | puts(p); 113 | } 114 | 115 | /* Present as floating point with one decimal digit in the fractional part */ 116 | static void put_uint_div_by_10(unsigned int value) 117 | { 118 | if (value >= 10) 119 | put_uint(value / 10); 120 | else 121 | puts("0"); 122 | puts("."); 123 | put_uint(value % 10); 124 | } 125 | 126 | #define SRAM_VER_REG (AW_SRAMCTRL_BASE + 0x24) 127 | 128 | void soc_detection_init(void) 129 | { 130 | set_wbit(SRAM_VER_REG, 1 << 15); 131 | } 132 | 133 | int soc_is_a31(void) 134 | { 135 | return (readl(SRAM_VER_REG) >> 16) == 0x1633; 136 | } 137 | 138 | int soc_is_h3(void) 139 | { 140 | return (readl(SRAM_VER_REG) >> 16) == 0x1680; 141 | } 142 | 143 | int dram_is_clocked(void) 144 | { 145 | return readl(CCU_PLL5CFG) & (1 << 31); 146 | } 147 | 148 | void gpio_init() 149 | { 150 | if (soc_is_h3()) { 151 | sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0); 152 | sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0); 153 | } else { 154 | /* setup UART0 to PORTF */ 155 | /* disable GPH20,21 as uart0 tx,rx to avoid conflict */ 156 | gpio_direction_input(SUNXI_GPH(20)); 157 | gpio_direction_input(SUNXI_GPH(21)); 158 | /* Setup GPF2,4 as uart0 tx,rx */ 159 | sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF2_UART0_TX); 160 | sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF4_UART0_RX); 161 | } 162 | } 163 | 164 | /* Write a couple of words into the DRAM and read them back */ 165 | void test_dram(void) 166 | { 167 | int i; 168 | volatile unsigned int *dram = (volatile unsigned int *)0x40000000; 169 | 170 | for (i = 0; i < 1024; i++) 171 | dram[i] = i; 172 | 173 | for (i = 0; i < 1024; i++) { 174 | if (dram[i] != i) { 175 | puts("FAIL\n"); 176 | return; 177 | } 178 | 179 | } 180 | 181 | puts("OK\n"); 182 | } 183 | 184 | void test_timer(void) 185 | { 186 | unsigned int time0, time1; 187 | timer_enable(); 188 | timer_reset_ticks(); 189 | time0 = timer_get_ticks(); 190 | time1 = timer_get_ticks(); 191 | 192 | /* Check that the tick value has changed */ 193 | if (time0 != time1) 194 | puts("OK\n"); 195 | else 196 | puts("FAIL\n"); 197 | } 198 | 199 | /* 200 | * Clock frequency detection routine. 201 | * Compares the internal AR100 timer with the AVS0 timer. 202 | */ 203 | #define TMR_AVS0_VAL (AW_TIMER_BASE + 0x0084) 204 | #define TMR_AVS_DIV (AW_TIMER_BASE + 0x008C) 205 | #define AVS_CLK (AW_CCM_BASE + 0x0144) 206 | #define AVS_CNT_CTL (AW_TIMER_BASE + 0x0080) 207 | void test_clk_freq(void) 208 | { 209 | int i; 210 | unsigned int tmr_avs0_val0, tmr_avs0_val1; 211 | unsigned int tmr_avs0_div; 212 | unsigned int time0, time1; 213 | unsigned int delta; 214 | unsigned int clk_freq; 215 | 216 | puts("Test CLK freq..."); 217 | timer_enable(); 218 | timer_reset_ticks(); 219 | 220 | set_wbit(AVS_CLK, 1 << 31); 221 | set_wbit(AVS_CNT_CTL, 1); 222 | 223 | tmr_avs0_div = (readl(TMR_AVS_DIV) & 0x7ff) + 1; 224 | 225 | /* 226 | * AVS0 reads high 32 bits of a 33-bit counter, so effectively we are 227 | * dealing with a counter, which runs at (12 MHz / div) clock speed. 228 | */ 229 | tmr_avs0_val0 = readl(TMR_AVS0_VAL); 230 | time0 = timer_get_ticks(); 231 | do { 232 | tmr_avs0_val1 = readl(TMR_AVS0_VAL); 233 | if (tmr_avs0_val1 >= tmr_avs0_val0) 234 | delta = tmr_avs0_val1 - tmr_avs0_val0; 235 | else 236 | delta = 0xffffffff - (tmr_avs0_val0 - tmr_avs0_val1); 237 | } while (delta < 1000); 238 | 239 | time1 = timer_get_ticks(); 240 | delta = time1 - time0; 241 | 242 | clk_freq = (uint64_t)delta * 12000 / tmr_avs0_div; 243 | clk_freq = (clk_freq + 500) / 1000; 244 | 245 | if (clk_freq < 1000) { 246 | put_uint(clk_freq); 247 | puts(" KHz\n"); 248 | } else { 249 | clk_freq = (clk_freq + 500) / 1000; 250 | put_uint(clk_freq); 251 | puts(" MHz\n"); 252 | } 253 | } 254 | 255 | void pointer_chasing(int count, void **addr) 256 | { 257 | void *old = *addr; 258 | *addr = addr; 259 | count = (count + 25) / 50; 260 | while (count--) { 261 | asm volatile(".rept 50\n" 262 | " l.lwz %0, 0(%0)\n" 263 | ".endr\n" 264 | : "+r" (addr)); 265 | } 266 | *addr = old; 267 | } 268 | 269 | void pointer_chasing_plus_nop(int count, void **addr) 270 | { 271 | void *old = *addr; 272 | *addr = addr; 273 | count = (count + 25) / 50; 274 | while (count--) { 275 | asm volatile(".rept 50\n" 276 | " l.lwz %0, 0(%0)\n" 277 | " l.nop\n" 278 | ".endr\n" 279 | : "+r" (addr)); 280 | } 281 | *addr = old; 282 | } 283 | 284 | void unrolled_nops(int count) 285 | { 286 | count = (count + 25) / 50; 287 | while (count--) { 288 | asm volatile(".rept 50\n" 289 | " l.nop\n" 290 | ".endr\n"); 291 | } 292 | } 293 | 294 | void empty_loop(int count) 295 | { 296 | count = (count + 25) / 50; 297 | while (count--) { 298 | asm volatile(""); 299 | } 300 | } 301 | 302 | void enable_caches(void) 303 | { 304 | unsigned addr; 305 | /* Flush I-cache for the whole SRAM A2 (cargo cult?) */ 306 | for (addr = 0; addr < 16 * 1024 + 32 * 1024; addr += 16) 307 | or1k_icache_flush(addr); 308 | or1k_icache_enable(); 309 | } 310 | 311 | void disable_caches(void) 312 | { 313 | or1k_icache_disable(); 314 | } 315 | 316 | void test_mem_latency(char *label, void **addr) 317 | { 318 | int count = 1000000; 319 | unsigned t1, t2, t3, t4; 320 | unsigned loop_overhead; 321 | 322 | timer_enable(); 323 | timer_reset_ticks(); 324 | 325 | t1 = timer_get_ticks(); 326 | pointer_chasing(count, addr); 327 | t2 = timer_get_ticks(); 328 | pointer_chasing_plus_nop(count, addr); 329 | t3 = timer_get_ticks(); 330 | unrolled_nops(count); 331 | t4 = timer_get_ticks(); 332 | empty_loop(count); 333 | loop_overhead = timer_get_ticks() - t4; 334 | 335 | puts(label); 336 | 337 | puts("\n"); 338 | puts(" Instructions fetch : "); 339 | put_uint_div_by_10((t4 - t3 - loop_overhead) * 10 / count); 340 | puts(" cycles per instruction\n"); 341 | 342 | puts(" Back-to-back L.LWZ : "); 343 | put_uint_div_by_10((t2 - t1 - loop_overhead) * 10 / count); 344 | puts(" cycles per 32-bit read\n"); 345 | 346 | puts(" L.LWZ + L.NOP : "); 347 | put_uint_div_by_10((t3 - t2 - loop_overhead) * 10 / count); 348 | puts(" cycles per 32-bit read\n"); 349 | } 350 | 351 | void benchmark(void) 352 | { 353 | void *dummy; 354 | 355 | enable_caches(); 356 | puts("\n == Benchmark ==\n"); 357 | test_mem_latency(" == Code in SRAM A2 (I-cache ON), data in SRAM A2 ==", 358 | &dummy); 359 | test_mem_latency(" == Code in SRAM A2 (I-cache ON), data in SRAM A1 ==", 360 | (void *)0x40000); 361 | if (dram_is_clocked()) { 362 | test_mem_latency( 363 | " == Code in SRAM A2 (I-cache ON), data in DRAM ==", 364 | (void *)0x40000000); 365 | } 366 | 367 | disable_caches(); 368 | puts("\n"); 369 | test_mem_latency(" == Code in SRAM A2 (I-cache OFF), data in SRAM A2 ==", 370 | &dummy); 371 | test_mem_latency(" == Code in SRAM A2 (I-cache OFF), data in SRAM A1 ==", 372 | (void *)0x40000); 373 | if (dram_is_clocked()) { 374 | test_mem_latency( 375 | " == Code in SRAM A2 (I-cache OFF), data in DRAM ==", 376 | (void *)0x40000000); 377 | } 378 | 379 | puts("\n"); 380 | } 381 | 382 | 383 | void test_clk_config(void) 384 | { 385 | unsigned int ar100_clkcfg_reg; 386 | unsigned int old_ar100_clkcfg_reg; 387 | unsigned int pll6_ctrl_reg; 388 | unsigned int old_pll6_ctrl_reg; 389 | 390 | puts("Set clock source to LOSC..."); 391 | old_ar100_clkcfg_reg = ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 392 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 393 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_LOSC; 394 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 395 | puts("done\n"); 396 | 397 | test_clk_freq(); 398 | 399 | puts("Set clock source to HOSC (POSTDIV=0, DIV=0)..."); 400 | ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 401 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 402 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_HOSC; 403 | ar100_clkcfg_reg &= ~AR100_CLKCFG_POSTDIV_MASK; 404 | ar100_clkcfg_reg |= AR100_CLKCFG_POSTDIV(0); 405 | ar100_clkcfg_reg &= ~AR100_CLKCFG_DIV_MASK; 406 | ar100_clkcfg_reg |= AR100_CLKCFG_DIV(0); 407 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 408 | puts("done\n"); 409 | 410 | test_clk_freq(); 411 | 412 | puts("Set clock source to HOSC (POSTDIV=0, DIV=1)..."); 413 | ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 414 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 415 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_HOSC; 416 | ar100_clkcfg_reg &= ~AR100_CLKCFG_POSTDIV_MASK; 417 | ar100_clkcfg_reg |= AR100_CLKCFG_POSTDIV(0); 418 | ar100_clkcfg_reg &= ~AR100_CLKCFG_DIV_MASK; 419 | ar100_clkcfg_reg |= AR100_CLKCFG_DIV(1); 420 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 421 | puts("done\n"); 422 | 423 | test_clk_freq(); 424 | 425 | puts("Set clock source to HOSC (POSTDIV=1, DIV=1)..."); 426 | ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 427 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 428 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_HOSC; 429 | ar100_clkcfg_reg &= ~AR100_CLKCFG_POSTDIV_MASK; 430 | ar100_clkcfg_reg |= AR100_CLKCFG_POSTDIV(1); 431 | ar100_clkcfg_reg &= ~AR100_CLKCFG_DIV_MASK; 432 | ar100_clkcfg_reg |= AR100_CLKCFG_DIV(1); 433 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 434 | puts("done\n"); 435 | 436 | test_clk_freq(); 437 | 438 | puts("Setup PLL6 (M=1, K=1, N=24)..."); 439 | old_pll6_ctrl_reg = pll6_ctrl_reg = readl(PLL6_CTRL_REG); 440 | pll6_ctrl_reg &= ~PLL6_CTRL_M_MASK; 441 | pll6_ctrl_reg |= PLL6_CTRL_M(1); 442 | pll6_ctrl_reg &= ~PLL6_CTRL_K_MASK; 443 | pll6_ctrl_reg |= PLL6_CTRL_K(1); 444 | pll6_ctrl_reg &= ~PLL6_CTRL_N_MASK; 445 | pll6_ctrl_reg |= PLL6_CTRL_N(24); 446 | pll6_ctrl_reg |= (PLL6_CTRL_ENABLE | PLL6_CTRL_CLK_OUTEN); 447 | writel(pll6_ctrl_reg, PLL6_CTRL_REG); 448 | puts("done\n"); 449 | 450 | puts("Set clock source to PLL6 (POSTDIV=1, DIV=0)..."); 451 | ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 452 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 453 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_PLL6; 454 | ar100_clkcfg_reg &= ~AR100_CLKCFG_POSTDIV_MASK; 455 | ar100_clkcfg_reg |= AR100_CLKCFG_POSTDIV(1); 456 | ar100_clkcfg_reg &= ~AR100_CLKCFG_DIV_MASK; 457 | ar100_clkcfg_reg |= AR100_CLKCFG_DIV(0); 458 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 459 | puts("done\n"); 460 | 461 | test_clk_freq(); 462 | benchmark(); 463 | 464 | puts("Set clock source to PLL6 (POSTDIV=2, DIV=0)..."); 465 | ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 466 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 467 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_PLL6; 468 | ar100_clkcfg_reg &= ~AR100_CLKCFG_POSTDIV_MASK; 469 | ar100_clkcfg_reg |= AR100_CLKCFG_POSTDIV(2); 470 | ar100_clkcfg_reg &= ~AR100_CLKCFG_DIV_MASK; 471 | ar100_clkcfg_reg |= AR100_CLKCFG_DIV(0); 472 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 473 | puts("done\n"); 474 | 475 | test_clk_freq(); 476 | 477 | puts("Set clock source to PLL6 (POSTDIV=2, DIV=1)..."); 478 | ar100_clkcfg_reg = readl(AR100_CLKCFG_REG); 479 | ar100_clkcfg_reg &= ~AR100_CLKCFG_SRC_MASK; 480 | ar100_clkcfg_reg |= AR100_CLKCFG_SRC_PLL6; 481 | ar100_clkcfg_reg &= ~AR100_CLKCFG_POSTDIV_MASK; 482 | ar100_clkcfg_reg |= AR100_CLKCFG_POSTDIV(2); 483 | ar100_clkcfg_reg &= ~AR100_CLKCFG_DIV_MASK; 484 | ar100_clkcfg_reg |= AR100_CLKCFG_DIV(1); 485 | writel(ar100_clkcfg_reg, AR100_CLKCFG_REG); 486 | puts("done\n"); 487 | 488 | test_clk_freq(); 489 | 490 | puts("Setup PLL6 (M=2, K=1, N=24)..."); 491 | pll6_ctrl_reg &= ~PLL6_CTRL_M_MASK; 492 | pll6_ctrl_reg |= PLL6_CTRL_M(2); 493 | pll6_ctrl_reg &= ~PLL6_CTRL_K_MASK; 494 | pll6_ctrl_reg |= PLL6_CTRL_K(1); 495 | pll6_ctrl_reg &= ~PLL6_CTRL_N_MASK; 496 | pll6_ctrl_reg |= PLL6_CTRL_N(24); 497 | writel(pll6_ctrl_reg, PLL6_CTRL_REG); 498 | puts("done\n"); 499 | 500 | test_clk_freq(); 501 | 502 | puts("Setup PLL6 (M=1, K=2, N=24)..."); 503 | pll6_ctrl_reg &= ~PLL6_CTRL_M_MASK; 504 | pll6_ctrl_reg |= PLL6_CTRL_M(1); 505 | pll6_ctrl_reg &= ~PLL6_CTRL_K_MASK; 506 | pll6_ctrl_reg |= PLL6_CTRL_K(2); 507 | pll6_ctrl_reg &= ~PLL6_CTRL_N_MASK; 508 | pll6_ctrl_reg |= PLL6_CTRL_N(24); 509 | writel(pll6_ctrl_reg, PLL6_CTRL_REG); 510 | puts("done\n"); 511 | 512 | test_clk_freq(); 513 | 514 | puts("Setup PLL6 (M=1, K=1, N=12)..."); 515 | pll6_ctrl_reg &= ~PLL6_CTRL_M_MASK; 516 | pll6_ctrl_reg |= PLL6_CTRL_M(1); 517 | pll6_ctrl_reg &= ~PLL6_CTRL_K_MASK; 518 | pll6_ctrl_reg |= PLL6_CTRL_K(1); 519 | pll6_ctrl_reg &= ~PLL6_CTRL_N_MASK; 520 | pll6_ctrl_reg |= PLL6_CTRL_N(12); 521 | writel(pll6_ctrl_reg, PLL6_CTRL_REG); 522 | puts("done\n"); 523 | 524 | test_clk_freq(); 525 | 526 | /* restore regs */ 527 | puts("Restore clock config to original state..."); 528 | writel(old_ar100_clkcfg_reg, AR100_CLKCFG_REG); 529 | writel(old_pll6_ctrl_reg, PLL6_CTRL_REG); 530 | puts("done\n"); 531 | } 532 | 533 | int main(void) 534 | { 535 | unsigned int upr = mfspr(SPR_UPR); 536 | unsigned int vr = mfspr(SPR_VR); 537 | unsigned int iccfgr = mfspr(SPR_ICCFGR); 538 | unsigned int dccfgr = mfspr(SPR_DCCFGR); 539 | unsigned int immucfgr = mfspr(SPR_IMMUCFGR); 540 | unsigned int dmmucfgr = mfspr(SPR_DMMUCFGR); 541 | unsigned int cpucfgr = mfspr(SPR_CPUCFGR); 542 | unsigned int ver = (vr & SPR_VR_VER) >> 24; 543 | unsigned int rev = vr & SPR_VR_REV; 544 | unsigned int block_size; 545 | unsigned int set_size; 546 | unsigned int ways; 547 | 548 | soc_detection_init(); 549 | gpio_init(); 550 | uart0_init(); 551 | 552 | puts("\n"); 553 | 554 | puts("OpenRISC-"); 555 | putchar(nibble_to_hex((char)(ver >> 4))); 556 | putchar(nibble_to_hex((char)ver & 0xf)); 557 | puts("00 (rev "); 558 | put_uint(rev); 559 | puts(")\n"); 560 | 561 | if (upr & SPR_UPR_DCP) { 562 | block_size = (dccfgr & SPR_DCCFGR_CBS) ? 32 : 16; 563 | ways = 1 << (dccfgr & SPR_DCCFGR_NCW); 564 | set_size = 1 << ((dccfgr & SPR_DCCFGR_NCS) >> 3); 565 | puts("D-Cache: "); 566 | put_uint(block_size*set_size*ways); 567 | puts(" bytes, "); 568 | put_uint(block_size); 569 | puts(" bytes/line, "); 570 | put_uint(ways); 571 | puts(" way(s)\n"); 572 | } else { 573 | puts("D-Cache: no\n"); 574 | } 575 | 576 | if (upr & SPR_UPR_ICP) { 577 | block_size = (iccfgr & SPR_ICCFGR_CBS) ? 32 : 16; 578 | ways = 1 << (iccfgr & SPR_ICCFGR_NCW); 579 | set_size = 1 << ((iccfgr & SPR_ICCFGR_NCS) >> 3); 580 | puts("I-Cache: "); 581 | put_uint(block_size*set_size*ways); 582 | puts(" bytes, "); 583 | put_uint(block_size); 584 | puts(" bytes/line, "); 585 | put_uint(ways); 586 | puts(" way(s)\n"); 587 | } else { 588 | puts("I-Cache: no\n"); 589 | } 590 | 591 | if (upr & SPR_UPR_DMP) { 592 | set_size = 1 << ((dmmucfgr & SPR_DMMUCFGR_NTS) >> 2); 593 | ways = (dmmucfgr & SPR_DMMUCFGR_NTW) + 1; 594 | puts("DMMU: "); 595 | put_uint(set_size); 596 | puts(" sets, "); 597 | put_uint(ways); 598 | puts(" way(s)\n"); 599 | } else { 600 | puts("DMMU: no\n"); 601 | } 602 | 603 | if (upr & SPR_UPR_IMP) { 604 | set_size = 1 << ((immucfgr & SPR_IMMUCFGR_NTS) >> 2); 605 | ways = (immucfgr & SPR_IMMUCFGR_NTW) + 1; 606 | puts("IMMU: "); 607 | put_uint(set_size); 608 | puts(" sets, "); 609 | put_uint(ways); 610 | puts(" way(s)\n"); 611 | } else { 612 | puts("IMMU: no\n"); 613 | } 614 | 615 | puts("MAC unit: "); 616 | (upr & SPR_UPR_MP) ? puts("yes\n") : puts("no\n"); 617 | puts("Debug unit: "); 618 | (upr & SPR_UPR_DUP) ? puts("yes\n") : puts("no\n"); 619 | puts("Performance counters: "); 620 | (upr & SPR_UPR_PCUP) ? puts("yes\n") : puts("no\n"); 621 | puts("Power management: "); 622 | (upr & SPR_UPR_PMP) ? puts("yes\n") : puts("no\n"); 623 | puts("Interrupt controller: "); 624 | (upr & SPR_UPR_PICP) ? puts("yes\n") : puts("no\n"); 625 | puts("Timer: "); 626 | (upr & SPR_UPR_TTP) ? puts("yes\n") : puts("no\n"); 627 | puts("Custom unit(s): "); 628 | (upr & SPR_UPR_CUP) ? puts("yes\n") : puts("no\n"); 629 | 630 | puts("ORBIS32: "); 631 | (cpucfgr & SPR_CPUCFGR_OB32S) ? puts("yes\n") : puts("no\n"); 632 | puts("ORBIS64: "); 633 | (cpucfgr & SPR_CPUCFGR_OB64S) ? puts("yes\n") : puts("no\n"); 634 | puts("ORFPX32: "); 635 | (cpucfgr & SPR_CPUCFGR_OF32S) ? puts("yes\n") : puts("no\n"); 636 | puts("ORFPX64: "); 637 | (cpucfgr & SPR_CPUCFGR_OF64S) ? puts("yes\n") : puts("no\n"); 638 | 639 | puts("Test support for l.addc..."); 640 | test_addc() ? puts("yes\n") : puts("no\n"); 641 | puts("Test support for l.cmov..."); 642 | test_cmov() ? puts("yes\n") : puts("no\n"); 643 | puts("Test support for l.cust1..."); 644 | test_cust1() ? puts("yes\n") : puts("no\n"); 645 | puts("Test support for l.cust2..."); 646 | test_cust2() ? puts("yes\n") : puts("no\n"); 647 | puts("Test support for l.cust3..."); 648 | test_cust3() ? puts("yes\n") : puts("no\n"); 649 | puts("Test support for l.cust4..."); 650 | test_cust4() ? puts("yes\n") : puts("no\n"); 651 | puts("Test support for l.cust5..."); 652 | test_cust5() ? puts("yes\n") : puts("no\n"); 653 | puts("Test support for l.cust6..."); 654 | test_cust6() ? puts("yes\n") : puts("no\n"); 655 | puts("Test support for l.cust7..."); 656 | test_cust7() ? puts("yes\n") : puts("no\n"); 657 | puts("Test support for l.cust8..."); 658 | test_cust8() ? puts("yes\n") : puts("no\n"); 659 | puts("Test support for l.div..."); 660 | test_div() ? puts("yes\n") : puts("no\n"); 661 | puts("Test support for l.divu..."); 662 | test_divu() ? puts("yes\n") : puts("no\n"); 663 | puts("Test support for l.extbs..."); 664 | test_extbs() ? puts("yes\n") : puts("no\n"); 665 | puts("Test support for l.extbz..."); 666 | test_extbz() ? puts("yes\n") : puts("no\n"); 667 | puts("Test support for l.exths..."); 668 | test_exths() ? puts("yes\n") : puts("no\n"); 669 | puts("Test support for l.exthz..."); 670 | test_exthz() ? puts("yes\n") : puts("no\n"); 671 | puts("Test support for l.extws..."); 672 | test_extws() ? puts("yes\n") : puts("no\n"); 673 | puts("Test support for l.extwz..."); 674 | test_extwz() ? puts("yes\n") : puts("no\n"); 675 | puts("Test support for l.ff1..."); 676 | test_ff1() ? puts("yes\n") : puts("no\n"); 677 | puts("Test support for l.fl1..."); 678 | test_fl1() ? puts("yes\n") : puts("no\n"); 679 | puts("Test support for l.lws..."); 680 | test_lws() ? puts("yes\n") : puts("no\n"); 681 | puts("Test support for l.mac..."); 682 | test_mac() ? puts("yes\n") : puts("no\n"); 683 | puts("Test support for l.maci..."); 684 | test_maci() ? puts("yes\n") : puts("no\n"); 685 | puts("Test support for l.macrc..."); 686 | test_macrc() ? puts("yes\n") : puts("no\n"); 687 | /* 688 | puts("Test support for l.macu..."); 689 | test_macu() ? puts("yes\n") : puts("no\n"); 690 | */ 691 | puts("Test support for l.mul..."); 692 | test_mul() ? puts("yes\n") : puts("no\n"); 693 | puts("Test support for l.muli..."); 694 | test_muli() ? puts("yes\n") : puts("no\n"); 695 | puts("Test support for l.mulu..."); 696 | test_mulu() ? puts("yes\n") : puts("no\n"); 697 | puts("Test support for l.ror..."); 698 | test_ror() ? puts("yes\n") : puts("no\n"); 699 | puts("Test support for l.rori..."); 700 | test_rori() ? puts("yes\n") : puts("no\n"); 701 | 702 | if (soc_is_a31() && !dram_is_clocked()) { 703 | puts("Init DRAM..."); 704 | mctl_init(); 705 | puts("done\n"); 706 | } 707 | 708 | if (dram_is_clocked()) { 709 | puts("Test DRAM read/write..."); 710 | test_dram(); 711 | } 712 | 713 | puts("Test timer functionality..."); 714 | test_timer(); 715 | 716 | test_clk_config(); 717 | 718 | puts("All tests completed!\n"); 719 | for (;;); 720 | } 721 | -------------------------------------------------------------------------------- /platform.h: -------------------------------------------------------------------------------- 1 | /* 2 | * arch/arm/mach-sun6i/include/mach/platform.h 3 | * 4 | * Copyright (c) Allwinner. All rights reserved. 5 | * Benn Huang (benn@allwinnertech.com) 6 | * 7 | * This program is free software; you can redistribute it and/or modify 8 | * it under the terms of the GNU General Public License as published by 9 | * the Free Software Foundation; either version 2 of the License, or 10 | * (at your option) any later version. 11 | * 12 | * This program is distributed in the hope that it will be useful, 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 | * GNU General Public License for more details. 16 | * 17 | * You should have received a copy of the GNU General Public License 18 | * along with this program; if not, write to the Free Software 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 20 | */ 21 | 22 | #ifndef __ASM_ARCH_PLATFORM_H 23 | #define __ASM_ARCH_PLATFORM_H 24 | 25 | /* 26 | * Memory definitions 27 | */ 28 | #define AW_IO_PHYS_BASE 0x01c00000 29 | #define AW_IO_SIZE 0x00400000 /* 4MB(Max) */ 30 | #define AW_SRAM_A1_BASE 0x00000000 31 | #define AW_SRAM_A1_SIZE 0x00008000 32 | #define AW_SRAM_A2_BASE 0x00040000 33 | #define AW_SRAM_A2_SIZE 0x00014000 34 | #define AW_SRAM_D_BASE 0x00010000 35 | #define AW_SRAM_D_SIZE 0x00001000 36 | #define AW_SRAM_B_BASE 0x00020000 /* Secure, 64KB */ 37 | #define AW_SRAM_B_SIZE 0x00010000 38 | #define AW_SDRAM_BASE 0x40000000 39 | #define AW_BROM_BASE 0xffff0000 40 | #define AW_BROM_SIZE 0x00008000 /* 32KB*/ 41 | #define AW_MTC_ACC 0x00080000 42 | 43 | /* 44 | * device physical addresses 45 | */ 46 | #define AW_SRAMCTRL_BASE 0x01c00000 47 | #define AW_DMA_BASE 0x01c02000 48 | #define AW_NANDFLASHC0_BASE 0x01c03000 49 | #define AW_TS_BASE 0x01c04000 50 | #define AW_NANDFLASHC1_BASE 0x01c05000 51 | #define AW_LCD0_BASE 0x01c0c000 52 | #define AW_LCD1_BASE 0x01c0d000 53 | #define AW_VE_BASE 0x01c0e000 54 | #define AW_SDMMC0_BASE 0x01c0f000 55 | #define AW_SDMMC1_BASE 0x01c10000 56 | #define AW_SDMMC2_BASE 0x01c11000 57 | #define AW_SDMMC3_BASE 0x01c12000 58 | #define AW_SS_BASE 0x01c15000 59 | #define AW_HDMI_BASE 0x01c16000 60 | #define AW_MSGBOX_BASE 0x01c17000 61 | #define AW_SPINLOCK_BASE 0x01c18000 62 | #define AW_USB_OTG_BASE 0x01c19000 63 | #define AW_USB_EHCI0_BASE 0x01c1a000 64 | #define AW_USB_OHCI0_BASE 0x01c1a000 65 | #define AW_USB_EHCI1_BASE 0x01c1b000 66 | #define AW_USB_OHCI1_BASE 0x01c1b000 67 | #define AW_USB_OHCI2_BASE 0x01c1c000 68 | #define AW_TZASC_BASE 0x01c1e000 69 | #define AW_CCM_BASE 0x01c20000 70 | #define AW_PIO_BASE 0x01c20800 71 | #define AW_TIMER_BASE 0x01c20c00 72 | #define AW_SPDIF_BASE 0x01c21000 73 | #define AW_PWM_BASE 0x01c21400 74 | #define AW_DAUDIO0_BASE 0x01c22000 75 | #define AW_DAUDIO1_BASE 0x01c22400 76 | #define AW_LRADC01_BASE 0x01c22800 77 | #define AW_AUDIOCODEC_BASE 0x01c22C00 78 | #define AW_TZPC_BASE 0x01c23400 79 | #define AW_SID_BASE 0x01c23800 80 | #define AW_SJTAG_BASE 0x01c23c00 81 | #define AW_TP_BASE 0x01c25000 82 | #define AW_DMIC_BASE 0x01c25400 83 | #define AW_UART0_BASE 0x01c28000 /* UART 0 */ 84 | #define AW_UART1_BASE 0x01c28400 /* UART 1 */ 85 | #define AW_UART2_BASE 0x01c28800 /* UART 2 */ 86 | #define AW_UART3_BASE 0x01c28c00 /* UART 3 */ 87 | #define AW_UART4_BASE 0x01c29000 /* UART 4 */ 88 | #define AW_UART5_BASE 0x01c29400 /* UART 5 */ 89 | #define AW_TWI0_BASE 0x01c2ac00 90 | #define AW_TWI1_BASE 0x01c2b000 91 | #define AW_TWI2_BASE 0x01c2b400 92 | #define AW_TWI3_BASE 0x01c2b800 93 | #define AW_GMAC_BASE 0x01c30000 94 | #define AW_GPU_BASE 0x01c40000 95 | #define AW_HSTMR_BASE 0x01c60000 96 | #define AW_DRAMCOM_BASE 0x01c62000 97 | #define AW_DRAMCTL0_BASE 0x01c63000 98 | #define AW_DRAMCTL1_BASE 0x01c64000 99 | #define AW_DRAMPHY0_BASE 0x01c65000 100 | #define AW_DRAMPHY1_BASE 0x01c66000 101 | #define AW_SPI0_BASE 0x01c68000 102 | #define AW_SPI1_BASE 0x01c69000 103 | #define AW_SPI2_BASE 0x01c6a000 104 | #define AW_SPI3_BASE 0x01c6b000 105 | #define AW_SCU_BASE 0x01c80000 106 | #define AW_MIPI_DSI0_BASE 0x01ca0000 107 | #define AW_MIPI_DSI0_PHY_BASE 0x01ca1000 108 | #define AW_CSI0_BASE 0x01cb0000 109 | #define AW_MIPI_CSI0_BASE 0x01cb1000 110 | #define AW_MIPI_CSI0_PHY_BASE 0x01cb2000 111 | #define AW_CSI1_BASE 0x01cb3000 112 | #define AW_ISP_BASE 0x01cb8000 113 | #define AW_ISP_MEM_BASE 0x01cc0000 114 | #define AW_SRAM_C_BASE 0x01d00000 115 | #define AW_DE_FE0_BASE 0x01e00000 116 | #define AW_DE_FE1_BASE 0x01e20000 117 | #define AW_DE_BE1_BASE 0x01e40000 118 | #define AW_DRC1_BASE 0x01e50000 119 | #define AW_DE_BE0_BASE 0x01e60000 120 | #define AW_DRC0_BASE 0x01e70000 121 | #define AW_MP_BASE 0x01e80000 122 | #define AW_DEU1_BASE 0x01ea0000 123 | #define AW_DEU0_BASE 0x01eb0000 124 | #define AW_PS_BASE 0x01ef0000 125 | #define AW_RTC_BASE 0x01f00000 126 | #define AW_R_TIMER_BASE 0x01f00800 127 | #define AW_R_INTC_BASE 0x01f00c00 128 | #define AW_R_WDOG_BASE 0x01f01000 129 | #define AW_R_PRCM_BASE 0x01f01400 130 | #define AW_R_CPUCFG_BASE 0x01f01c00 131 | #define AW_R_CIR_BASE 0x01f02000 132 | #define AW_R_TWI_BASE 0x01f02400 133 | #define AW_R_UART_BASE 0x01f02800 /* R_UART */ 134 | #define AW_R_PIO_BASE 0x01f02c00 /* for r-pio */ 135 | #define AW_R_ONE_WIRE_BASE 0x01f03000 136 | #define AW_R_P2WI_BASE 0x01f03400 137 | #define AW_CDM_BASE 0x3f500000/*coresight debug module*/ 138 | #define AW_TSGEN_RO_BASE 0x3f506000 139 | #define AW_TSGEN_CTRL_BASE 0x3f507000 140 | 141 | 142 | 143 | 144 | #define AW_GIC_DIST_BASE 0x01c81000 145 | #define AW_GIC_CPU_BASE 0x01c82000 146 | #define AW_TIMER_G_BASE 0x01c80200 /* CPU global timer, not used */ 147 | #define AW_TIMER_P_BASE 0x01c80600 /* CPU private timer, not used */ 148 | 149 | 150 | /* 151 | * Peripheral addresses 152 | */ 153 | #define AW_RTC_REG AW_RTC_BASE 154 | #define AW_RPIO_BASE AW_R_PIO_BASE 155 | 156 | 157 | 158 | 159 | 160 | 161 | 162 | 163 | 164 | 165 | /* 166 | * device virtual addresses 167 | */ 168 | #define AW_VIR_SRAMCTRL_BASE 0xf1c00000 169 | #define AW_VIR_DMA_BASE 0xf1c02000 170 | #define AW_VIR_NANDFLASHC0_BASE 0xf1c03000 171 | #define AW_VIR_TS_BASE 0xf1c04000 172 | #define AW_VIR_NANDFLASHC1_BASE 0xf1c05000 173 | #define AW_VIR_LCD0_BASE 0xf1c0c000 174 | #define AW_VIR_LCD1_BASE 0xf1c0d000 175 | #define AW_VIR_VE_BASE 0xf1c0e000 176 | #define AW_VIR_SDMMC0_BASE 0xf1c0f000 177 | #define AW_VIR_SDMMC1_BASE 0xf1c10000 178 | #define AW_VIR_SDMMC2_BASE 0xf1c11000 179 | #define AW_VIR_SDMMC3_BASE 0xf1c12000 180 | #define AW_VIR_SS_BASE 0xf1c15000 181 | #define AW_VIR_HDMI_BASE 0xf1c16000 182 | #define AW_VIR_MSGBOX_BASE 0xf1c17000 183 | #define AW_VIR_SPINLOCK_BASE 0xf1c18000 184 | #define AW_VIR_USB_OTG_BASE 0xf1c19000 185 | #define AW_VIR_USB_EHCI0_BASE 0xf1c1a000 186 | #define AW_VIR_USB_OHCI0_BASE 0xf1c1a000 187 | #define AW_VIR_USB_EHCI1_BASE 0xf1c1b000 188 | #define AW_VIR_USB_OHCI1_BASE 0xf1c1b000 189 | #define AW_VIR_USB_OHCI2_BASE 0xf1c1c000 190 | #define AW_VIR_TZASC_BASE 0xf1c1e000 191 | #define AW_VIR_CCM_BASE 0xf1c20000 192 | #define AW_VIR_PIO_BASE 0xf1c20800 193 | #define AW_VIR_TIMER_BASE 0xf1c20c00 194 | #define AW_VIR_SPDIF_BASE 0xf1c21000 195 | #define AW_VIR_PWM_BASE 0xf1c21400 196 | #define AW_VIR_DAUDIO0_BASE 0xf1c22000 197 | #define AW_VIR_DAUDIO1_BASE 0xf1c22400 198 | #define AW_VIR_LRADC01_BASE 0xf1c22800 199 | #define AW_VIR_AUDIOCODEC_BASE 0xf1c22C00 200 | #define AW_VIR_TZPC_BASE 0xf1c23400 201 | #define AW_VIR_SID_BASE 0xf1c23800 202 | #define AW_VIR_SJTAG_BASE 0xf1c23c00 203 | #define AW_VIR_TP_BASE 0xf1c25000 204 | #define AW_VIR_DMIC_BASE 0xf1c25400 205 | #define AW_VIR_UART0_BASE 0xf1c28000 /* UART 0 */ 206 | #define AW_VIR_UART1_BASE 0xf1c28400 /* UART 1 */ 207 | #define AW_VIR_UART2_BASE 0xf1c28800 /* UART 2 */ 208 | #define AW_VIR_UART3_BASE 0xf1c28c00 /* UART 3 */ 209 | #define AW_VIR_UART4_BASE 0xf1c29000 /* UART 4 */ 210 | #define AW_VIR_UART5_BASE 0xf1c29400 /* UART 5 */ 211 | #define AW_VIR_TWI0_BASE 0xf1c2ac00 212 | #define AW_VIR_TWI1_BASE 0xf1c2b000 213 | #define AW_VIR_TWI2_BASE 0xf1c2b400 214 | #define AW_VIR_TWI3_BASE 0xf1c2b800 215 | #define AW_VIR_GMAC_BASE 0xf1c30000 216 | #define AW_VIR_GPU_BASE 0xf1c40000 217 | #define AW_VIR_HSTMR_BASE 0xf1c60000 218 | #define AW_VIR_DRAMCOM_BASE 0xf1c62000 219 | #define AW_VIR_DRAMCTL0_BASE 0xf1c63000 220 | #define AW_VIR_DRAMCTL1_BASE 0xf1c64000 221 | #define AW_VIR_DRAMPHY0_BASE 0xf1c65000 222 | #define AW_VIR_DRAMPHY1_BASE 0xf1c66000 223 | #define AW_VIR_SPI0_BASE 0xf1c68000 224 | #define AW_VIR_SPI1_BASE 0xf1c69000 225 | #define AW_VIR_SPI2_BASE 0xf1c6a000 226 | #define AW_VIR_SPI3_BASE 0xf1c6b000 227 | #define AW_VIR_SCU_BASE 0xf1c80000 228 | #define AW_VIR_MIPI_DSI0_BASE 0xf1ca0000 229 | #define AW_VIR_MIPI_DSI0_PHY_BASE 0xf1ca1000 230 | #define AW_VIR_CSI0_BASE 0xf1cb0000 231 | #define AW_VIR_MIPI_CSI0_BASE 0xf1cb1000 232 | #define AW_VIR_MIPI_CSI0_PHY_BASE 0xf1cb2000 233 | #define AW_VIR_CSI1_BASE 0xf1cb3000 234 | #define AW_VIR_ISP_BASE 0xf1cb8000 235 | #define AW_VIR_ISP_MEM_BASE 0xf1cc0000 236 | #define AW_VIR_SRAM_C_BASE 0xf1d00000 237 | #define AW_VIR_DE_FE0_BASE 0xf1e00000 238 | #define AW_VIR_DE_FE1_BASE 0xf1e20000 239 | #define AW_VIR_DE_BE1_BASE 0xf1e40000 240 | #define AW_VIR_DRC1_BASE 0xf1e50000 241 | #define AW_VIR_DE_BE0_BASE 0xf1e60000 242 | #define AW_VIR_DRC0_BASE 0xf1e70000 243 | #define AW_VIR_MP_BASE 0xf1e80000 244 | #define AW_VIR_DEU1_BASE 0xf1ea0000 245 | #define AW_VIR_DEU0_BASE 0xf1eb0000 246 | #define AW_VIR_PS_BASE 0xf1ef0000 247 | #define AW_VIR_RTC_BASE 0xf1f00000 248 | #define AW_VIR_R_TIMER_BASE 0xf1f00800 249 | #define AW_VIR_R_INTC_BASE 0xf1f00c00 250 | #define AW_VIR_R_WDOG_BASE 0xf1f01000 251 | #define AW_VIR_R_PRCM_BASE 0xf1f01400 252 | #define AW_VIR_R_CPUCFG_BASE 0xf1f01c00 253 | #define AW_VIR_R_CIR_BASE 0xf1f02000 254 | #define AW_VIR_R_TWI_BASE 0xf1f02400 255 | #define AW_VIR_R_UART_BASE 0xf1f02800 /* R_UART */ 256 | #define AW_VIR_R_PIO_BASE 0xf1f02c00 /* for r-pio */ 257 | #define AW_VIR_R_ONE_WIRE_BASE 0xf1f03000 258 | #define AW_VIR_R_P2WI_BASE 0xf1f03400 259 | 260 | 261 | 262 | 263 | /* 264 | * Timer registers 265 | */ 266 | #define AW_TMR_IRQ_EN_REG 0x0000 267 | #define AW_TMR_IRQ_STA_REG 0x0004 268 | #define AW_TMR0_CTRL_REG 0x0010 269 | #define AW_TMR0_INTV_VALUE_REG 0x0014 270 | #define AW_TMR0_CUR_VALUE_REG 0x0018 271 | 272 | #define AW_AVS_CNT_CTL_REG 0x0080 273 | #define AW_AVS_CNT0_REG 0x0084 274 | #define AW_AVS_CNT1_REG 0x0088 275 | #define AW_AVS_CNT_DIV_REG 0x008c 276 | 277 | #define AW_WDOG1_IRQ_EN_REG 0xa0 278 | #define AW_WDOG1_IRQ_STA_REG 0xa4 279 | #define AW_WDOG1_CTRL_REG 0xb0 280 | #define AW_WDOG1_CFG_REG 0xb4 281 | #define AW_WDOG1_MODE_REG 0xb8 282 | 283 | /* r-watchdog0 reg offset define */ 284 | #define AW_WDOG0_IRQ_EN_REG 0x0 285 | #define AW_WDOG0_IRQ_STA_REG 0x4 286 | #define AW_WDOG0_CTRL_REG 0x10 287 | #define AW_WDOG0_CFG_REG 0x14 288 | #define AW_WDOG0_MODE_REG 0x18 289 | 290 | /* 291 | * CPUCFG 292 | */ 293 | #define AW_CPUCFG_P_REG0 0x01a4 294 | #define AW_CPUCFG_P_REG1 0x01a8 295 | #define CPUX_RESET_CTL(x) (0x40 + (x)*0x40) 296 | #define CPUX_CONTROL(x) (0x44 + (x)*0x40) 297 | #define CPUX_STATUS(x) (0x48 + (x)*0x40) 298 | #define AW_CPUCFG_GENCTL 0x0184 299 | #define AW_CPUCFG_DBGCTL0 0x01e0 300 | #define AW_CPUCFG_DBGCTL1 0x01e4 301 | 302 | 303 | /* 304 | * PRCM 305 | */ 306 | #define AW_CPU_PWROFF_REG 0x100 307 | /* cpu0 has no clmap register! */ 308 | #define AW_CPUX_PWR_CLAMP(x) (0x140 + (x)*0x04) 309 | #define AW_CPUX_PWR_CLAMP_STATUS(x) (0x64 + (x)*0x40) 310 | 311 | /* 312 | * UART 313 | */ 314 | #define AW_UART_RBR 0x00 /* Receive Buffer Register */ 315 | #define AW_UART_THR 0x00 /* Transmit Holding Register */ 316 | #define AW_UART_DLL 0x00 /* Divisor Latch Low Register */ 317 | #define AW_UART_DLH 0x04 /* Diviso Latch High Register */ 318 | #define AW_UART_IER 0x04 /* Interrupt Enable Register */ 319 | #define AW_UART_IIR 0x08 /* Interrrupt Identity Register */ 320 | #define AW_UART_FCR 0x08 /* FIFO Control Register */ 321 | #define AW_UART_LCR 0x0c /* Line Control Register */ 322 | #define AW_UART_MCR 0x10 /* Modem Control Register */ 323 | #define AW_UART_LSR 0x14 /* Line Status Register */ 324 | #define AW_UART_MSR 0x18 /* Modem Status Register */ 325 | #define AW_UART_SCH 0x1c /* Scratch Register */ 326 | #define AW_UART_USR 0x7c /* Status Register */ 327 | #define AW_UART_TFL 0x80 /* Transmit FIFO Level */ 328 | #define AW_UART_RFL 0x84 /* RFL */ 329 | #define AW_UART_HALT 0xa4 /* Halt TX Register */ 330 | 331 | #define UART_USR (AW_UART_USR >> 2) 332 | #define UART_HALT (AW_UART_HALT >> 2) 333 | #define UART_SCH (AW_UART_SCH >> 2) 334 | #define UART_FORCE_CFG (1 << 1) 335 | #define UART_FORCE_UPDATE (1 << 2) 336 | 337 | #define AW_UART_LOG(fmt, args...) do {} while(0) 338 | #if 0 339 | #define AW_UART_LOG(fmt, args...) \ 340 | do { \ 341 | aw_printk((u32)AW_UART0_BASE, "[%s]"fmt"\n", __FUNCTION__, ##args); \ 342 | } while (0) 343 | #endif 344 | 345 | #define AW_R_UART_LOG(fmt, args...) \ 346 | do { \ 347 | aw_printk((u32)AW_R_UART_BASE, "[%s]"fmt"\n", __FUNCTION__, ##args); \ 348 | } while (0) 349 | 350 | 351 | #endif /* __ASM_ARCH_PLATFORM_H */ 352 | -------------------------------------------------------------------------------- /spr-defs.h: -------------------------------------------------------------------------------- 1 | /* 2 | * SPR Definitions 3 | * 4 | * Copyright (C) 2000 Damjan Lampret 5 | * Copyright (C) 2003 Matjaz Breskvar 6 | * Copyright (C) 2008, 2010 Embecosm Limited 7 | * Copyright (C) 2010-2011 Jonas Bonn 8 | * et al. 9 | * 10 | * This program is free software; you can redistribute it and/or modify 11 | * it under the terms of the GNU General Public License as published by 12 | * the Free Software Foundation; either version 2 of the License, or 13 | * (at your option) any later version. 14 | * 15 | * This file is part of OpenRISC 1000 Architectural Simulator. 16 | */ 17 | 18 | #ifndef SPR_DEFS__H 19 | #define SPR_DEFS__H 20 | 21 | /* Definition of special-purpose registers (SPRs) */ 22 | 23 | #define MAX_GRPS (32) 24 | #define MAX_SPRS_PER_GRP_BITS (11) 25 | #define MAX_SPRS_PER_GRP (1 << MAX_SPRS_PER_GRP_BITS) 26 | #define MAX_SPRS (0x10000) 27 | 28 | /* Base addresses for the groups */ 29 | #define SPRGROUP_SYS (0 << MAX_SPRS_PER_GRP_BITS) 30 | #define SPRGROUP_DMMU (1 << MAX_SPRS_PER_GRP_BITS) 31 | #define SPRGROUP_IMMU (2 << MAX_SPRS_PER_GRP_BITS) 32 | #define SPRGROUP_DC (3 << MAX_SPRS_PER_GRP_BITS) 33 | #define SPRGROUP_IC (4 << MAX_SPRS_PER_GRP_BITS) 34 | #define SPRGROUP_MAC (5 << MAX_SPRS_PER_GRP_BITS) 35 | #define SPRGROUP_D (6 << MAX_SPRS_PER_GRP_BITS) 36 | #define SPRGROUP_PC (7 << MAX_SPRS_PER_GRP_BITS) 37 | #define SPRGROUP_PM (8 << MAX_SPRS_PER_GRP_BITS) 38 | #define SPRGROUP_PIC (9 << MAX_SPRS_PER_GRP_BITS) 39 | #define SPRGROUP_TT (10 << MAX_SPRS_PER_GRP_BITS) 40 | #define SPRGROUP_FP (11 << MAX_SPRS_PER_GRP_BITS) 41 | 42 | /* System control and status group */ 43 | #define SPR_VR (SPRGROUP_SYS + 0) 44 | #define SPR_UPR (SPRGROUP_SYS + 1) 45 | #define SPR_CPUCFGR (SPRGROUP_SYS + 2) 46 | #define SPR_DMMUCFGR (SPRGROUP_SYS + 3) 47 | #define SPR_IMMUCFGR (SPRGROUP_SYS + 4) 48 | #define SPR_DCCFGR (SPRGROUP_SYS + 5) 49 | #define SPR_ICCFGR (SPRGROUP_SYS + 6) 50 | #define SPR_DCFGR (SPRGROUP_SYS + 7) 51 | #define SPR_PCCFGR (SPRGROUP_SYS + 8) 52 | #define SPR_NPC (SPRGROUP_SYS + 16) 53 | #define SPR_SR (SPRGROUP_SYS + 17) 54 | #define SPR_PPC (SPRGROUP_SYS + 18) 55 | #define SPR_FPCSR (SPRGROUP_SYS + 20) 56 | #define SPR_EPCR_BASE (SPRGROUP_SYS + 32) 57 | #define SPR_EPCR_LAST (SPRGROUP_SYS + 47) 58 | #define SPR_EEAR_BASE (SPRGROUP_SYS + 48) 59 | #define SPR_EEAR_LAST (SPRGROUP_SYS + 63) 60 | #define SPR_ESR_BASE (SPRGROUP_SYS + 64) 61 | #define SPR_ESR_LAST (SPRGROUP_SYS + 79) 62 | #define SPR_GPR_BASE (SPRGROUP_SYS + 1024) 63 | 64 | /* Data MMU group */ 65 | #define SPR_DMMUCR (SPRGROUP_DMMU + 0) 66 | #define SPR_DTLBEIR (SPRGROUP_DMMU + 2) 67 | #define SPR_DTLBMR_BASE(WAY) (SPRGROUP_DMMU + 0x200 + (WAY) * 0x100) 68 | #define SPR_DTLBMR_LAST(WAY) (SPRGROUP_DMMU + 0x27f + (WAY) * 0x100) 69 | #define SPR_DTLBTR_BASE(WAY) (SPRGROUP_DMMU + 0x280 + (WAY) * 0x100) 70 | #define SPR_DTLBTR_LAST(WAY) (SPRGROUP_DMMU + 0x2ff + (WAY) * 0x100) 71 | 72 | /* Instruction MMU group */ 73 | #define SPR_IMMUCR (SPRGROUP_IMMU + 0) 74 | #define SPR_ITLBEIR (SPRGROUP_IMMU + 2) 75 | #define SPR_ITLBMR_BASE(WAY) (SPRGROUP_IMMU + 0x200 + (WAY) * 0x100) 76 | #define SPR_ITLBMR_LAST(WAY) (SPRGROUP_IMMU + 0x27f + (WAY) * 0x100) 77 | #define SPR_ITLBTR_BASE(WAY) (SPRGROUP_IMMU + 0x280 + (WAY) * 0x100) 78 | #define SPR_ITLBTR_LAST(WAY) (SPRGROUP_IMMU + 0x2ff + (WAY) * 0x100) 79 | 80 | /* Data cache group */ 81 | #define SPR_DCCR (SPRGROUP_DC + 0) 82 | #define SPR_DCBPR (SPRGROUP_DC + 1) 83 | #define SPR_DCBFR (SPRGROUP_DC + 2) 84 | #define SPR_DCBIR (SPRGROUP_DC + 3) 85 | #define SPR_DCBWR (SPRGROUP_DC + 4) 86 | #define SPR_DCBLR (SPRGROUP_DC + 5) 87 | #define SPR_DCR_BASE(WAY) (SPRGROUP_DC + 0x200 + (WAY) * 0x200) 88 | #define SPR_DCR_LAST(WAY) (SPRGROUP_DC + 0x3ff + (WAY) * 0x200) 89 | 90 | /* Instruction cache group */ 91 | #define SPR_ICCR (SPRGROUP_IC + 0) 92 | #define SPR_ICBPR (SPRGROUP_IC + 1) 93 | #define SPR_ICBIR (SPRGROUP_IC + 2) 94 | #define SPR_ICBLR (SPRGROUP_IC + 3) 95 | #define SPR_ICR_BASE(WAY) (SPRGROUP_IC + 0x200 + (WAY) * 0x200) 96 | #define SPR_ICR_LAST(WAY) (SPRGROUP_IC + 0x3ff + (WAY) * 0x200) 97 | 98 | /* MAC group */ 99 | #define SPR_MACLO (SPRGROUP_MAC + 1) 100 | #define SPR_MACHI (SPRGROUP_MAC + 2) 101 | 102 | /* Debug group */ 103 | #define SPR_DVR(N) (SPRGROUP_D + (N)) 104 | #define SPR_DCR(N) (SPRGROUP_D + 8 + (N)) 105 | #define SPR_DMR1 (SPRGROUP_D + 16) 106 | #define SPR_DMR2 (SPRGROUP_D + 17) 107 | #define SPR_DWCR0 (SPRGROUP_D + 18) 108 | #define SPR_DWCR1 (SPRGROUP_D + 19) 109 | #define SPR_DSR (SPRGROUP_D + 20) 110 | #define SPR_DRR (SPRGROUP_D + 21) 111 | 112 | /* Performance counters group */ 113 | #define SPR_PCCR(N) (SPRGROUP_PC + (N)) 114 | #define SPR_PCMR(N) (SPRGROUP_PC + 8 + (N)) 115 | 116 | /* Power management group */ 117 | #define SPR_PMR (SPRGROUP_PM + 0) 118 | 119 | /* PIC group */ 120 | #define SPR_PICMR (SPRGROUP_PIC + 0) 121 | #define SPR_PICPR (SPRGROUP_PIC + 1) 122 | #define SPR_PICSR (SPRGROUP_PIC + 2) 123 | 124 | /* Tick Timer group */ 125 | #define SPR_TTMR (SPRGROUP_TT + 0) 126 | #define SPR_TTCR (SPRGROUP_TT + 1) 127 | 128 | /* 129 | * Bit definitions for the Version Register 130 | */ 131 | #define SPR_VR_VER 0xff000000 /* Processor version */ 132 | #define SPR_VR_CFG 0x00ff0000 /* Processor configuration */ 133 | #define SPR_VR_RES 0x0000ffc0 /* Reserved */ 134 | #define SPR_VR_REV 0x0000003f /* Processor revision */ 135 | 136 | #define SPR_VR_VER_OFF 24 137 | #define SPR_VR_CFG_OFF 16 138 | #define SPR_VR_REV_OFF 0 139 | 140 | /* 141 | * Bit definitions for the Unit Present Register 142 | */ 143 | #define SPR_UPR_UP 0x00000001 /* UPR present */ 144 | #define SPR_UPR_DCP 0x00000002 /* Data cache present */ 145 | #define SPR_UPR_ICP 0x00000004 /* Instruction cache present */ 146 | #define SPR_UPR_DMP 0x00000008 /* Data MMU present */ 147 | #define SPR_UPR_IMP 0x00000010 /* Instruction MMU present */ 148 | #define SPR_UPR_MP 0x00000020 /* MAC present */ 149 | #define SPR_UPR_DUP 0x00000040 /* Debug unit present */ 150 | #define SPR_UPR_PCUP 0x00000080 /* Performance counters unit present */ 151 | #define SPR_UPR_PMP 0x00000100 /* Power management present */ 152 | #define SPR_UPR_PICP 0x00000200 /* PIC present */ 153 | #define SPR_UPR_TTP 0x00000400 /* Tick timer present */ 154 | #define SPR_UPR_RES 0x00fe0000 /* Reserved */ 155 | #define SPR_UPR_CUP 0xff000000 /* Context units present */ 156 | 157 | /* 158 | * Bit definitions for the CPU configuration register 159 | */ 160 | #define SPR_CPUCFGR_NSGF 0x0000000f /* Number of shadow GPR files */ 161 | #define SPR_CPUCFGR_CGF 0x00000010 /* Custom GPR file */ 162 | #define SPR_CPUCFGR_OB32S 0x00000020 /* ORBIS32 supported */ 163 | #define SPR_CPUCFGR_OB64S 0x00000040 /* ORBIS64 supported */ 164 | #define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */ 165 | #define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */ 166 | #define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */ 167 | #define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */ 168 | 169 | /* 170 | * Bit definitions for the Debug configuration register and other 171 | * constants. 172 | */ 173 | 174 | #define SPR_DCFGR_NDP 0x00000007 /* Number of matchpoints mask */ 175 | #define SPR_DCFGR_NDP1 0x00000000 /* One matchpoint supported */ 176 | #define SPR_DCFGR_NDP2 0x00000001 /* Two matchpoints supported */ 177 | #define SPR_DCFGR_NDP3 0x00000002 /* Three matchpoints supported */ 178 | #define SPR_DCFGR_NDP4 0x00000003 /* Four matchpoints supported */ 179 | #define SPR_DCFGR_NDP5 0x00000004 /* Five matchpoints supported */ 180 | #define SPR_DCFGR_NDP6 0x00000005 /* Six matchpoints supported */ 181 | #define SPR_DCFGR_NDP7 0x00000006 /* Seven matchpoints supported */ 182 | #define SPR_DCFGR_NDP8 0x00000007 /* Eight matchpoints supported */ 183 | #define SPR_DCFGR_WPCI 0x00000008 /* Watchpoint counters implemented */ 184 | 185 | #define MATCHPOINTS_TO_NDP(n) (1 == n ? SPR_DCFGR_NDP1 : \ 186 | 2 == n ? SPR_DCFGR_NDP2 : \ 187 | 3 == n ? SPR_DCFGR_NDP3 : \ 188 | 4 == n ? SPR_DCFGR_NDP4 : \ 189 | 5 == n ? SPR_DCFGR_NDP5 : \ 190 | 6 == n ? SPR_DCFGR_NDP6 : \ 191 | 7 == n ? SPR_DCFGR_NDP7 : SPR_DCFGR_NDP8) 192 | #define MAX_MATCHPOINTS 8 193 | #define MAX_WATCHPOINTS (MAX_MATCHPOINTS + 2) 194 | 195 | /* 196 | * Bit definitions for the Supervision Register 197 | */ 198 | #define SPR_SR_SM 0x00000001 /* Supervisor Mode */ 199 | #define SPR_SR_TEE 0x00000002 /* Tick timer Exception Enable */ 200 | #define SPR_SR_IEE 0x00000004 /* Interrupt Exception Enable */ 201 | #define SPR_SR_DCE 0x00000008 /* Data Cache Enable */ 202 | #define SPR_SR_ICE 0x00000010 /* Instruction Cache Enable */ 203 | #define SPR_SR_DME 0x00000020 /* Data MMU Enable */ 204 | #define SPR_SR_IME 0x00000040 /* Instruction MMU Enable */ 205 | #define SPR_SR_LEE 0x00000080 /* Little Endian Enable */ 206 | #define SPR_SR_CE 0x00000100 /* CID Enable */ 207 | #define SPR_SR_F 0x00000200 /* Condition Flag */ 208 | #define SPR_SR_CY 0x00000400 /* Carry flag */ 209 | #define SPR_SR_OV 0x00000800 /* Overflow flag */ 210 | #define SPR_SR_OVE 0x00001000 /* Overflow flag Exception */ 211 | #define SPR_SR_DSX 0x00002000 /* Delay Slot Exception */ 212 | #define SPR_SR_EPH 0x00004000 /* Exception Prefix High */ 213 | #define SPR_SR_FO 0x00008000 /* Fixed one */ 214 | #define SPR_SR_SUMRA 0x00010000 /* Supervisor SPR read access */ 215 | #define SPR_SR_RES 0x0ffe0000 /* Reserved */ 216 | #define SPR_SR_CID 0xf0000000 /* Context ID */ 217 | 218 | /* 219 | * Bit definitions for the Data MMU Control Register 220 | */ 221 | #define SPR_DMMUCR_P2S 0x0000003e /* Level 2 Page Size */ 222 | #define SPR_DMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ 223 | #define SPR_DMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ 224 | #define SPR_DMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ 225 | 226 | /* 227 | * Bit definitions for the Instruction MMU Control Register 228 | */ 229 | #define SPR_IMMUCR_P2S 0x0000003e /* Level 2 Page Size */ 230 | #define SPR_IMMUCR_P1S 0x000007c0 /* Level 1 Page Size */ 231 | #define SPR_IMMUCR_VADDR_WIDTH 0x0000f800 /* Virtual ADDR Width */ 232 | #define SPR_IMMUCR_PADDR_WIDTH 0x000f0000 /* Physical ADDR Width */ 233 | 234 | /* 235 | * Bit definitions for the Data TLB Match Register 236 | */ 237 | #define SPR_DTLBMR_V 0x00000001 /* Valid */ 238 | #define SPR_DTLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ 239 | #define SPR_DTLBMR_CID 0x0000003c /* Context ID */ 240 | #define SPR_DTLBMR_LRU 0x000000c0 /* Least Recently Used */ 241 | #define SPR_DTLBMR_VPN 0xfffff000 /* Virtual Page Number */ 242 | 243 | /* 244 | * Bit definitions for the Data TLB Translate Register 245 | */ 246 | #define SPR_DTLBTR_CC 0x00000001 /* Cache Coherency */ 247 | #define SPR_DTLBTR_CI 0x00000002 /* Cache Inhibit */ 248 | #define SPR_DTLBTR_WBC 0x00000004 /* Write-Back Cache */ 249 | #define SPR_DTLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ 250 | #define SPR_DTLBTR_A 0x00000010 /* Accessed */ 251 | #define SPR_DTLBTR_D 0x00000020 /* Dirty */ 252 | #define SPR_DTLBTR_URE 0x00000040 /* User Read Enable */ 253 | #define SPR_DTLBTR_UWE 0x00000080 /* User Write Enable */ 254 | #define SPR_DTLBTR_SRE 0x00000100 /* Supervisor Read Enable */ 255 | #define SPR_DTLBTR_SWE 0x00000200 /* Supervisor Write Enable */ 256 | #define SPR_DTLBTR_PPN 0xfffff000 /* Physical Page Number */ 257 | 258 | /* 259 | * Bit definitions for the Instruction TLB Match Register 260 | */ 261 | #define SPR_ITLBMR_V 0x00000001 /* Valid */ 262 | #define SPR_ITLBMR_PL1 0x00000002 /* Page Level 1 (if 0 then PL2) */ 263 | #define SPR_ITLBMR_CID 0x0000003c /* Context ID */ 264 | #define SPR_ITLBMR_LRU 0x000000c0 /* Least Recently Used */ 265 | #define SPR_ITLBMR_VPN 0xfffff000 /* Virtual Page Number */ 266 | 267 | /* 268 | * Bit definitions for the Instruction TLB Translate Register 269 | */ 270 | #define SPR_ITLBTR_CC 0x00000001 /* Cache Coherency */ 271 | #define SPR_ITLBTR_CI 0x00000002 /* Cache Inhibit */ 272 | #define SPR_ITLBTR_WBC 0x00000004 /* Write-Back Cache */ 273 | #define SPR_ITLBTR_WOM 0x00000008 /* Weakly-Ordered Memory */ 274 | #define SPR_ITLBTR_A 0x00000010 /* Accessed */ 275 | #define SPR_ITLBTR_D 0x00000020 /* Dirty */ 276 | #define SPR_ITLBTR_SXE 0x00000040 /* User Read Enable */ 277 | #define SPR_ITLBTR_UXE 0x00000080 /* User Write Enable */ 278 | #define SPR_ITLBTR_PPN 0xfffff000 /* Physical Page Number */ 279 | 280 | /* 281 | * Bit definitions for Data Cache Control register 282 | */ 283 | #define SPR_DCCR_EW 0x000000ff /* Enable ways */ 284 | 285 | /* 286 | * Bit definitions for Insn Cache Control register 287 | */ 288 | #define SPR_ICCR_EW 0x000000ff /* Enable ways */ 289 | 290 | /* 291 | * Bit definitions for Data Cache Configuration Register 292 | */ 293 | 294 | #define SPR_DCCFGR_NCW 0x00000007 295 | #define SPR_DCCFGR_NCS 0x00000078 296 | #define SPR_DCCFGR_CBS 0x00000080 297 | #define SPR_DCCFGR_CWS 0x00000100 298 | #define SPR_DCCFGR_CCRI 0x00000200 299 | #define SPR_DCCFGR_CBIRI 0x00000400 300 | #define SPR_DCCFGR_CBPRI 0x00000800 301 | #define SPR_DCCFGR_CBLRI 0x00001000 302 | #define SPR_DCCFGR_CBFRI 0x00002000 303 | #define SPR_DCCFGR_CBWBRI 0x00004000 304 | 305 | #define SPR_DCCFGR_NCW_OFF 0 306 | #define SPR_DCCFGR_NCS_OFF 3 307 | #define SPR_DCCFGR_CBS_OFF 7 308 | 309 | /* 310 | * Bit definitions for Instruction Cache Configuration Register 311 | */ 312 | #define SPR_ICCFGR_NCW 0x00000007 313 | #define SPR_ICCFGR_NCS 0x00000078 314 | #define SPR_ICCFGR_CBS 0x00000080 315 | #define SPR_ICCFGR_CCRI 0x00000200 316 | #define SPR_ICCFGR_CBIRI 0x00000400 317 | #define SPR_ICCFGR_CBPRI 0x00000800 318 | #define SPR_ICCFGR_CBLRI 0x00001000 319 | 320 | #define SPR_ICCFGR_NCW_OFF 0 321 | #define SPR_ICCFGR_NCS_OFF 3 322 | #define SPR_ICCFGR_CBS_OFF 7 323 | 324 | /* 325 | * Bit definitions for Data MMU Configuration Register 326 | */ 327 | #define SPR_DMMUCFGR_NTW 0x00000003 328 | #define SPR_DMMUCFGR_NTS 0x0000001C 329 | #define SPR_DMMUCFGR_NAE 0x000000E0 330 | #define SPR_DMMUCFGR_CRI 0x00000100 331 | #define SPR_DMMUCFGR_PRI 0x00000200 332 | #define SPR_DMMUCFGR_TEIRI 0x00000400 333 | #define SPR_DMMUCFGR_HTR 0x00000800 334 | 335 | #define SPR_DMMUCFGR_NTW_OFF 0 336 | #define SPR_DMMUCFGR_NTS_OFF 2 337 | 338 | /* 339 | * Bit definitions for Instruction MMU Configuration Register 340 | */ 341 | #define SPR_IMMUCFGR_NTW 0x00000003 342 | #define SPR_IMMUCFGR_NTS 0x0000001C 343 | #define SPR_IMMUCFGR_NAE 0x000000E0 344 | #define SPR_IMMUCFGR_CRI 0x00000100 345 | #define SPR_IMMUCFGR_PRI 0x00000200 346 | #define SPR_IMMUCFGR_TEIRI 0x00000400 347 | #define SPR_IMMUCFGR_HTR 0x00000800 348 | 349 | #define SPR_IMMUCFGR_NTW_OFF 0 350 | #define SPR_IMMUCFGR_NTS_OFF 2 351 | 352 | /* 353 | * Bit definitions for Debug Control registers 354 | */ 355 | #define SPR_DCR_DP 0x00000001 /* DVR/DCR present */ 356 | #define SPR_DCR_CC 0x0000000e /* Compare condition */ 357 | #define SPR_DCR_SC 0x00000010 /* Signed compare */ 358 | #define SPR_DCR_CT 0x000000e0 /* Compare to */ 359 | 360 | /* Bit results with SPR_DCR_CC mask */ 361 | #define SPR_DCR_CC_MASKED 0x00000000 362 | #define SPR_DCR_CC_EQUAL 0x00000002 363 | #define SPR_DCR_CC_LESS 0x00000004 364 | #define SPR_DCR_CC_LESSE 0x00000006 365 | #define SPR_DCR_CC_GREAT 0x00000008 366 | #define SPR_DCR_CC_GREATE 0x0000000a 367 | #define SPR_DCR_CC_NEQUAL 0x0000000c 368 | 369 | /* Bit results with SPR_DCR_CT mask */ 370 | #define SPR_DCR_CT_DISABLED 0x00000000 371 | #define SPR_DCR_CT_IFEA 0x00000020 372 | #define SPR_DCR_CT_LEA 0x00000040 373 | #define SPR_DCR_CT_SEA 0x00000060 374 | #define SPR_DCR_CT_LD 0x00000080 375 | #define SPR_DCR_CT_SD 0x000000a0 376 | #define SPR_DCR_CT_LSEA 0x000000c0 377 | #define SPR_DCR_CT_LSD 0x000000e0 378 | 379 | /* 380 | * Bit definitions for Debug Mode 1 register 381 | */ 382 | #define SPR_DMR1_CW 0x000fffff /* Chain register pair data */ 383 | #define SPR_DMR1_CW0_AND 0x00000001 384 | #define SPR_DMR1_CW0_OR 0x00000002 385 | #define SPR_DMR1_CW0 (SPR_DMR1_CW0_AND | SPR_DMR1_CW0_OR) 386 | #define SPR_DMR1_CW1_AND 0x00000004 387 | #define SPR_DMR1_CW1_OR 0x00000008 388 | #define SPR_DMR1_CW1 (SPR_DMR1_CW1_AND | SPR_DMR1_CW1_OR) 389 | #define SPR_DMR1_CW2_AND 0x00000010 390 | #define SPR_DMR1_CW2_OR 0x00000020 391 | #define SPR_DMR1_CW2 (SPR_DMR1_CW2_AND | SPR_DMR1_CW2_OR) 392 | #define SPR_DMR1_CW3_AND 0x00000040 393 | #define SPR_DMR1_CW3_OR 0x00000080 394 | #define SPR_DMR1_CW3 (SPR_DMR1_CW3_AND | SPR_DMR1_CW3_OR) 395 | #define SPR_DMR1_CW4_AND 0x00000100 396 | #define SPR_DMR1_CW4_OR 0x00000200 397 | #define SPR_DMR1_CW4 (SPR_DMR1_CW4_AND | SPR_DMR1_CW4_OR) 398 | #define SPR_DMR1_CW5_AND 0x00000400 399 | #define SPR_DMR1_CW5_OR 0x00000800 400 | #define SPR_DMR1_CW5 (SPR_DMR1_CW5_AND | SPR_DMR1_CW5_OR) 401 | #define SPR_DMR1_CW6_AND 0x00001000 402 | #define SPR_DMR1_CW6_OR 0x00002000 403 | #define SPR_DMR1_CW6 (SPR_DMR1_CW6_AND | SPR_DMR1_CW6_OR) 404 | #define SPR_DMR1_CW7_AND 0x00004000 405 | #define SPR_DMR1_CW7_OR 0x00008000 406 | #define SPR_DMR1_CW7 (SPR_DMR1_CW7_AND | SPR_DMR1_CW7_OR) 407 | #define SPR_DMR1_CW8_AND 0x00010000 408 | #define SPR_DMR1_CW8_OR 0x00020000 409 | #define SPR_DMR1_CW8 (SPR_DMR1_CW8_AND | SPR_DMR1_CW8_OR) 410 | #define SPR_DMR1_CW9_AND 0x00040000 411 | #define SPR_DMR1_CW9_OR 0x00080000 412 | #define SPR_DMR1_CW9 (SPR_DMR1_CW9_AND | SPR_DMR1_CW9_OR) 413 | #define SPR_DMR1_RES1 0x00300000 /* Reserved */ 414 | #define SPR_DMR1_ST 0x00400000 /* Single-step trace*/ 415 | #define SPR_DMR1_BT 0x00800000 /* Branch trace */ 416 | #define SPR_DMR1_RES2 0xff000000 /* Reserved */ 417 | 418 | /* 419 | * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB 420 | */ 421 | #define SPR_DMR2_WCE0 0x00000001 /* Watchpoint counter 0 enable */ 422 | #define SPR_DMR2_WCE1 0x00000002 /* Watchpoint counter 0 enable */ 423 | #define SPR_DMR2_AWTC 0x00000ffc /* Assign watchpoints to counters */ 424 | #define SPR_DMR2_AWTC_OFF 2 /* Bit offset to AWTC field */ 425 | #define SPR_DMR2_WGB 0x003ff000 /* Watch generating breakpoint */ 426 | #define SPR_DMR2_WGB_OFF 12 /* Bit offset to WGB field */ 427 | #define SPR_DMR2_WBS 0xffc00000 /* Watchpoint status */ 428 | #define SPR_DMR2_WBS_OFF 22 /* Bit offset to WBS field */ 429 | 430 | /* 431 | * Bit definitions for Debug watchpoint counter registers 432 | */ 433 | #define SPR_DWCR_COUNT 0x0000ffff /* Count */ 434 | #define SPR_DWCR_MATCH 0xffff0000 /* Match */ 435 | #define SPR_DWCR_MATCH_OFF 16 /* Match bit offset */ 436 | 437 | /* 438 | * Bit definitions for Debug stop register 439 | * 440 | */ 441 | #define SPR_DSR_RSTE 0x00000001 /* Reset exception */ 442 | #define SPR_DSR_BUSEE 0x00000002 /* Bus error exception */ 443 | #define SPR_DSR_DPFE 0x00000004 /* Data Page Fault exception */ 444 | #define SPR_DSR_IPFE 0x00000008 /* Insn Page Fault exception */ 445 | #define SPR_DSR_TTE 0x00000010 /* Tick Timer exception */ 446 | #define SPR_DSR_AE 0x00000020 /* Alignment exception */ 447 | #define SPR_DSR_IIE 0x00000040 /* Illegal Instruction exception */ 448 | #define SPR_DSR_IE 0x00000080 /* Interrupt exception */ 449 | #define SPR_DSR_DME 0x00000100 /* DTLB miss exception */ 450 | #define SPR_DSR_IME 0x00000200 /* ITLB miss exception */ 451 | #define SPR_DSR_RE 0x00000400 /* Range exception */ 452 | #define SPR_DSR_SCE 0x00000800 /* System call exception */ 453 | #define SPR_DSR_FPE 0x00001000 /* Floating Point Exception */ 454 | #define SPR_DSR_TE 0x00002000 /* Trap exception */ 455 | 456 | /* 457 | * Bit definitions for Debug reason register 458 | */ 459 | #define SPR_DRR_RSTE 0x00000001 /* Reset exception */ 460 | #define SPR_DRR_BUSEE 0x00000002 /* Bus error exception */ 461 | #define SPR_DRR_DPFE 0x00000004 /* Data Page Fault exception */ 462 | #define SPR_DRR_IPFE 0x00000008 /* Insn Page Fault exception */ 463 | #define SPR_DRR_TTE 0x00000010 /* Tick Timer exception */ 464 | #define SPR_DRR_AE 0x00000020 /* Alignment exception */ 465 | #define SPR_DRR_IIE 0x00000040 /* Illegal Instruction exception */ 466 | #define SPR_DRR_IE 0x00000080 /* Interrupt exception */ 467 | #define SPR_DRR_DME 0x00000100 /* DTLB miss exception */ 468 | #define SPR_DRR_IME 0x00000200 /* ITLB miss exception */ 469 | #define SPR_DRR_RE 0x00000400 /* Range exception */ 470 | #define SPR_DRR_SCE 0x00000800 /* System call exception */ 471 | #define SPR_DRR_FPE 0x00001000 /* Floating Point Exception */ 472 | #define SPR_DRR_TE 0x00002000 /* Trap exception */ 473 | 474 | /* 475 | * Bit definitions for Performance counters mode registers 476 | */ 477 | #define SPR_PCMR_CP 0x00000001 /* Counter present */ 478 | #define SPR_PCMR_UMRA 0x00000002 /* User mode read access */ 479 | #define SPR_PCMR_CISM 0x00000004 /* Count in supervisor mode */ 480 | #define SPR_PCMR_CIUM 0x00000008 /* Count in user mode */ 481 | #define SPR_PCMR_LA 0x00000010 /* Load access event */ 482 | #define SPR_PCMR_SA 0x00000020 /* Store access event */ 483 | #define SPR_PCMR_IF 0x00000040 /* Instruction fetch event*/ 484 | #define SPR_PCMR_DCM 0x00000080 /* Data cache miss event */ 485 | #define SPR_PCMR_ICM 0x00000100 /* Insn cache miss event */ 486 | #define SPR_PCMR_IFS 0x00000200 /* Insn fetch stall event */ 487 | #define SPR_PCMR_LSUS 0x00000400 /* LSU stall event */ 488 | #define SPR_PCMR_BS 0x00000800 /* Branch stall event */ 489 | #define SPR_PCMR_DTLBM 0x00001000 /* DTLB miss event */ 490 | #define SPR_PCMR_ITLBM 0x00002000 /* ITLB miss event */ 491 | #define SPR_PCMR_DDS 0x00004000 /* Data dependency stall event */ 492 | #define SPR_PCMR_WPE 0x03ff8000 /* Watchpoint events */ 493 | 494 | /* 495 | * Bit definitions for the Power management register 496 | */ 497 | #define SPR_PMR_SDF 0x0000000f /* Slow down factor */ 498 | #define SPR_PMR_DME 0x00000010 /* Doze mode enable */ 499 | #define SPR_PMR_SME 0x00000020 /* Sleep mode enable */ 500 | #define SPR_PMR_DCGE 0x00000040 /* Dynamic clock gating enable */ 501 | #define SPR_PMR_SUME 0x00000080 /* Suspend mode enable */ 502 | 503 | /* 504 | * Bit definitions for PICMR 505 | */ 506 | #define SPR_PICMR_IUM 0xfffffffc /* Interrupt unmask */ 507 | 508 | /* 509 | * Bit definitions for PICPR 510 | */ 511 | #define SPR_PICPR_IPRIO 0xfffffffc /* Interrupt priority */ 512 | 513 | /* 514 | * Bit definitions for PICSR 515 | */ 516 | #define SPR_PICSR_IS 0xffffffff /* Interrupt status */ 517 | 518 | /* 519 | * Bit definitions for Tick Timer Control Register 520 | */ 521 | #define SPR_TTCR_CNT 0xffffffff /* Count, time period */ 522 | #define SPR_TTMR_TP 0x0fffffff /* Time period */ 523 | #define SPR_TTMR_IP 0x10000000 /* Interrupt Pending */ 524 | #define SPR_TTMR_IE 0x20000000 /* Interrupt Enable */ 525 | #define SPR_TTMR_DI 0x00000000 /* Disabled */ 526 | #define SPR_TTMR_RT 0x40000000 /* Restart tick */ 527 | #define SPR_TTMR_SR 0x80000000 /* Single run */ 528 | #define SPR_TTMR_CR 0xc0000000 /* Continuous run */ 529 | #define SPR_TTMR_M 0xc0000000 /* Tick mode */ 530 | 531 | /* 532 | * Bit definitions for the FP Control Status Register 533 | */ 534 | #define SPR_FPCSR_FPEE 0x00000001 /* Floating Point Exception Enable */ 535 | #define SPR_FPCSR_RM 0x00000006 /* Rounding Mode */ 536 | #define SPR_FPCSR_OVF 0x00000008 /* Overflow Flag */ 537 | #define SPR_FPCSR_UNF 0x00000010 /* Underflow Flag */ 538 | #define SPR_FPCSR_SNF 0x00000020 /* SNAN Flag */ 539 | #define SPR_FPCSR_QNF 0x00000040 /* QNAN Flag */ 540 | #define SPR_FPCSR_ZF 0x00000080 /* Zero Flag */ 541 | #define SPR_FPCSR_IXF 0x00000100 /* Inexact Flag */ 542 | #define SPR_FPCSR_IVF 0x00000200 /* Invalid Flag */ 543 | #define SPR_FPCSR_INF 0x00000400 /* Infinity Flag */ 544 | #define SPR_FPCSR_DZF 0x00000800 /* Divide By Zero Flag */ 545 | #define SPR_FPCSR_ALLF (SPR_FPCSR_OVF | SPR_FPCSR_UNF | SPR_FPCSR_SNF | \ 546 | SPR_FPCSR_QNF | SPR_FPCSR_ZF | SPR_FPCSR_IXF | \ 547 | SPR_FPCSR_IVF | SPR_FPCSR_INF | SPR_FPCSR_DZF) 548 | 549 | #define FPCSR_RM_RN (0<<1) 550 | #define FPCSR_RM_RZ (1<<1) 551 | #define FPCSR_RM_RIP (2<<1) 552 | #define FPCSR_RM_RIN (3<<1) 553 | 554 | /* 555 | * l.nop constants 556 | */ 557 | #define NOP_NOP 0x0000 /* Normal nop instruction */ 558 | #define NOP_EXIT 0x0001 /* End of simulation */ 559 | #define NOP_REPORT 0x0002 /* Simple report */ 560 | #define NOP_PUTC 0x0004 /* Simputc instruction */ 561 | #define NOP_CNT_RESET 0x0005 /* Reset statistics counters */ 562 | #define NOP_GET_TICKS 0x0006 /* Get # ticks running */ 563 | #define NOP_GET_PS 0x0007 /* Get picosecs/cycle */ 564 | #define NOP_REPORT_FIRST 0x0400 /* Report with number */ 565 | #define NOP_REPORT_LAST 0x03ff /* Report with number */ 566 | 567 | #endif /* SPR_DEFS__H */ 568 | -------------------------------------------------------------------------------- /spr.h: -------------------------------------------------------------------------------- 1 | #ifndef _SPR_H 2 | #define _SPR_H 3 | #include "spr-defs.h" 4 | 5 | static inline unsigned long mfspr(unsigned long add) 6 | { 7 | unsigned long ret; 8 | 9 | __asm__ __volatile__ ("l.mfspr %0,r0,%1" : "=r" (ret) : "K" (add)); 10 | 11 | return ret; 12 | } 13 | 14 | static inline void mtspr(unsigned long add, unsigned long val) 15 | { 16 | __asm__ __volatile__ ("l.mtspr r0,%1,%0" : : "K" (add), "r" (val)); 17 | } 18 | #endif 19 | -------------------------------------------------------------------------------- /start.S: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Stefan Kristiansson 3 | * 4 | * This program is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU General Public License as 6 | * published by the Free Software Foundation; either version 2 of 7 | * the License, or (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 | * MA 02111-1307 USA 18 | */ 19 | #include "spr-defs.h" 20 | 21 | /* 22 | * The A31 SoC have address decode logic for the exception vectors, 23 | * leaving only room for a jump instruction at each exception vector, 24 | * so we can't do the setup here but have to jump into the actual 25 | * SRAM at 0x4000 26 | * 27 | * NOTE: we are missing vectors here, but since the l.nop actually is 28 | * hardwired, the "0" instruction data will turn into an infinite loop 29 | * (l.j 0) at the unhandled exceptions. 30 | */ 31 | .org 0x100 32 | .global _start 33 | _start: 34 | l.j reset 35 | l.nop 36 | 37 | .org 0x700 38 | l.j illegal_instruction_handler 39 | l.nop 40 | 41 | .org 0x4000 42 | /* include the arm "boot loader" binary at a fixed address */ 43 | .global ar100_boot_start 44 | ar100_boot: 45 | .incbin "ar100-boot/ar100-boot.code" 46 | .align 4 47 | 48 | reset: 49 | l.movhi r0,0 50 | l.ori r1, r0, 0xbffc 51 | l.j main 52 | l.nop 53 | 54 | .global illegal_instruction 55 | illegal_instruction: .long 0x0 56 | 57 | illegal_instruction_handler: 58 | /* Step over red zone */ 59 | l.addi r1, r1, -128 60 | l.sw -4(r1), r3 61 | l.sw -8(r1), r4 62 | 63 | /* Set illegal_instruction to 1 */ 64 | l.movhi r3, hi(illegal_instruction) 65 | l.ori r3, r3, lo(illegal_instruction) 66 | l.ori r4, r0, 1 67 | l.sw 0(r3), r4 68 | /* Step over the illegal instruction */ 69 | l.mfspr r3, r0, SPR_EPCR_BASE 70 | l.addi r3, r3, 4 71 | l.mtspr r0, r3, SPR_EPCR_BASE 72 | 73 | /* Restore */ 74 | l.lwz r3, -4(r1) 75 | l.lwz r4, -8(r1) 76 | l.addi r1, r1, 128 77 | 78 | 79 | l.rfe 80 | l.nop 81 | -------------------------------------------------------------------------------- /timer.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2013 Stefan Kristiansson 3 | * 4 | * This program is free software; you can redistribute it and/or 5 | * modify it under the terms of the GNU General Public License as 6 | * published by the Free Software Foundation; either version 2 of 7 | * the License, or (at your option) any later version. 8 | * 9 | * This program is distributed in the hope that it will be useful, 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 | * GNU General Public License for more details. 13 | * 14 | * You should have received a copy of the GNU General Public License 15 | * along with this program; if not, write to the Free Software 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 17 | * MA 02111-1307 USA 18 | */ 19 | #ifndef _TIMER_H 20 | #define _TIMER_H 21 | #include "spr.h" 22 | 23 | static inline void timer_enable(void) 24 | { 25 | mtspr(SPR_TTMR, SPR_TTMR_CR); 26 | } 27 | 28 | static inline void timer_disable(void) 29 | { 30 | mtspr(SPR_TTMR, 0); 31 | } 32 | 33 | static inline void timer_reset_ticks(void) 34 | { 35 | mtspr(SPR_TTCR, 0); 36 | } 37 | 38 | static inline unsigned timer_get_ticks(void) 39 | { 40 | return mfspr(SPR_TTCR); 41 | } 42 | #endif 43 | -------------------------------------------------------------------------------- /type.h: -------------------------------------------------------------------------------- 1 | #include 2 | 3 | typedef uint64_t u64; 4 | typedef uint32_t u32; 5 | typedef uint16_t u16; 6 | typedef uint8_t u8; 7 | 8 | typedef int64_t s64; 9 | typedef int32_t s32; 10 | typedef int16_t s16; 11 | typedef int8_t s8; 12 | -------------------------------------------------------------------------------- /uart.c: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2007-2012 3 | * Allwinner Technology Co., Ltd. 4 | * Tom Cubie 5 | * 6 | * Early uart print for debugging. 7 | * 8 | * See file CREDITS for list of people who contributed to this 9 | * project. 10 | * 11 | * This program is free software; you can redistribute it and/or 12 | * modify it under the terms of the GNU General Public License as 13 | * published by the Free Software Foundation; either version 2 of 14 | * the License, or (at your option) any later version. 15 | * 16 | * This program is distributed in the hope that it will be useful, 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | * GNU General Public License for more details. 20 | * 21 | * You should have received a copy of the GNU General Public License 22 | * along with this program; if not, write to the Free Software 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 | * MA 02111-1307 USA 25 | */ 26 | 27 | #include "io.h" 28 | #include "uart.h" 29 | #include "clock.h" 30 | 31 | #define CONFIG_CONS_INDEX 1 32 | 33 | #define APB2_DIV (AW_CCM_BASE + 0x058) 34 | #define APB2_GATE (AW_CCM_BASE + 0x06C) 35 | #define APB2_RESET (AW_CCM_BASE + 0x2D8) 36 | 37 | void clock_init_uart(void) 38 | { 39 | /* uart clock source is apb2 */ 40 | writel(APB2_CLK_SRC_OSC24M| 41 | APB2_CLK_RATE_N_1| 42 | APB2_CLK_RATE_M(1), 43 | APB2_GATE); 44 | 45 | /* open the clock for uart */ 46 | set_wbit(APB2_GATE, 1 << (APB2_GATE_UART_SHIFT + 47 | CONFIG_CONS_INDEX - 1)); 48 | 49 | /* deassert uart reset */ 50 | set_wbit(APB2_RESET, 1 << (APB2_RESET_UART_SHIFT + 51 | CONFIG_CONS_INDEX - 1)); 52 | } 53 | 54 | void uart0_init(void) 55 | { 56 | clock_init_uart(); 57 | 58 | /* select dll dlh */ 59 | writel(0x80, UART0_LCR); 60 | /* set baudrate */ 61 | writel(0, UART0_DLH); 62 | writel(BAUD_115200, UART0_DLL); 63 | /* set line control */ 64 | writel(LC_8_N_1, UART0_LCR); 65 | } 66 | 67 | #define TX_READY (readl(UART0_LSR) & (1 << 6)) 68 | void uart0_putc(char c) 69 | { 70 | while(!TX_READY) 71 | ; 72 | writel(c, UART0_THR); 73 | } 74 | 75 | void uart0_puts(const char *s) 76 | { 77 | while(*s) { 78 | if (*s == '\n') 79 | uart0_putc('\r'); 80 | uart0_putc(*s++); 81 | } 82 | } 83 | -------------------------------------------------------------------------------- /uart.h: -------------------------------------------------------------------------------- 1 | /* 2 | * (C) Copyright 2007-2012 3 | * Allwinner Technology Co., Ltd. 4 | * Tom Cubie 5 | * 6 | * Early uart print for debugging. 7 | * 8 | * See file CREDITS for list of people who contributed to this 9 | * project. 10 | * 11 | * This program is free software; you can redistribute it and/or 12 | * modify it under the terms of the GNU General Public License as 13 | * published by the Free Software Foundation; either version 2 of 14 | * the License, or (at your option) any later version. 15 | * 16 | * This program is distributed in the hope that it will be useful, 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 | * GNU General Public License for more details. 20 | * 21 | * You should have received a copy of the GNU General Public License 22 | * along with this program; if not, write to the Free Software 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 | * MA 02111-1307 USA 25 | */ 26 | 27 | #ifndef _UART_H 28 | #define _UART_H 29 | 30 | #include "cpu.h" 31 | 32 | #define UART0_RBR (SUNXI_UART0_BASE + 0x0) /* receive buffer register */ 33 | #define UART0_THR (SUNXI_UART0_BASE + 0x0) /* transmit holding register */ 34 | #define UART0_DLL (SUNXI_UART0_BASE + 0x0) /* divisor latch low register */ 35 | 36 | #define UART0_DLH (SUNXI_UART0_BASE + 0x4) /* divisor latch high register */ 37 | #define UART0_IER (SUNXI_UART0_BASE + 0x4) /* interrupt enable reigster */ 38 | 39 | #define UART0_IIR (SUNXI_UART0_BASE + 0x8) /* interrupt identity register */ 40 | #define UART0_FCR (SUNXI_UART0_BASE + 0x8) /* fifo control register */ 41 | 42 | #define UART0_LCR (SUNXI_UART0_BASE + 0xc) /* line control register */ 43 | 44 | #define UART0_LSR (SUNXI_UART0_BASE + 0x14) /* line status register */ 45 | 46 | #define BAUD_115200 (0xD) /* 24 * 1000 * 1000 / 16 / 115200 = 13 */ 47 | #define NO_PARITY (0) 48 | #define ONE_STOP_BIT (0) 49 | #define DAT_LEN_8_BITS (3) 50 | #define LC_8_N_1 (NO_PARITY << 3 | ONE_STOP_BIT << 2 | DAT_LEN_8_BITS) 51 | 52 | void uart0_init(void); 53 | void uart0_putc(char c); 54 | void uart0_puts(const char *s); 55 | 56 | #endif 57 | --------------------------------------------------------------------------------