├── .gitignore ├── .travis.yml ├── bench └── i2s_tb.v ├── i2s.core └── rtl └── verilog ├── i2s_rx.v ├── i2s_tx.v └── i2s_wb_if.v /.gitignore: -------------------------------------------------------------------------------- 1 | *~ -------------------------------------------------------------------------------- /.travis.yml: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/skristiansson/i2s/HEAD/.travis.yml -------------------------------------------------------------------------------- /bench/i2s_tb.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/skristiansson/i2s/HEAD/bench/i2s_tb.v -------------------------------------------------------------------------------- /i2s.core: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/skristiansson/i2s/HEAD/i2s.core -------------------------------------------------------------------------------- /rtl/verilog/i2s_rx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/skristiansson/i2s/HEAD/rtl/verilog/i2s_rx.v -------------------------------------------------------------------------------- /rtl/verilog/i2s_tx.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/skristiansson/i2s/HEAD/rtl/verilog/i2s_tx.v -------------------------------------------------------------------------------- /rtl/verilog/i2s_wb_if.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/skristiansson/i2s/HEAD/rtl/verilog/i2s_wb_if.v --------------------------------------------------------------------------------