├── .flake8 ├── .gitattributes ├── .github └── workflows │ └── axi_ci.yml ├── .gitignore ├── LICENSE.txt ├── README.md ├── conda-recipe ├── README.md ├── build.sh └── meta.yaml ├── hardware ├── AbacoPc821 │ ├── pcie │ │ ├── XCKU085 │ │ │ ├── AbacoPc821PciePhy.dcp │ │ │ ├── AbacoPc821PciePhy.xci │ │ │ └── AbacoPc821PciePhy.xdc │ │ ├── XCKU115 │ │ │ ├── AbacoPc821PciePhy.dcp │ │ │ ├── AbacoPc821PciePhy.xci │ │ │ └── AbacoPc821PciePhy.xdc │ │ ├── rtl │ │ │ └── AbacoPc821PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── rtl │ │ ├── AbacoPc821Core.vhd │ │ ├── KU085 │ │ │ └── AxiPciePkg.vhd │ │ └── KU115 │ │ │ └── AxiPciePkg.vhd │ ├── ruckus.tcl │ └── xdc │ │ ├── AbacoPc821App.xdc │ │ └── AbacoPc821Core.xdc ├── AlphaDataKu3 │ ├── pcie │ │ ├── ip │ │ │ ├── AlphaDataKu3PciePhy.dcp │ │ │ ├── AlphaDataKu3PciePhy.xci │ │ │ └── AlphaDataKu3PciePhy.xdc │ │ ├── rtl │ │ │ └── AlphaDataKu3PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── rtl │ │ ├── AlphaDataKu3Core.vhd │ │ ├── AxiPciePkg.vhd │ │ └── TerminateQsfp.vhd │ ├── ruckus.tcl │ └── xdc │ │ ├── AlphaDataKu3App.xdc │ │ └── AlphaDataKu3Core.xdc ├── BittWareXupVv8 │ ├── core │ │ ├── BittWareXupVv8Core.vhd │ │ ├── TerminateQsfp.vhd │ │ ├── VU13P │ │ │ └── AxiPciePkg.vhd │ │ └── VU9P │ │ │ └── AxiPciePkg.vhd │ ├── ddr │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── 1600-MTPS │ │ │ │ ├── BittWareXupVv8MigCore.xci │ │ │ │ └── MTA18ADF2G72PZ-2G3.csv │ │ │ ├── 2400-MTPS │ │ │ │ ├── BittWareXupVv8MigCore.xci │ │ │ │ └── MTA18ADF2G72PZ-2G3.csv │ │ │ └── BittWareXupVv8MigCore.xdc │ │ ├── rtl │ │ │ ├── Mig.vhd │ │ │ ├── MigAll.vhd │ │ │ └── MigPkg.vhd │ │ ├── ruckus.tcl │ │ ├── tb │ │ │ ├── Ddr4ModelWrapper.sv │ │ │ ├── ddr4_bi_delay.sv │ │ │ ├── ddr4_db_delay_model.sv │ │ │ ├── ddr4_db_dly_dir.sv │ │ │ ├── ddr4_dimm.sv │ │ │ ├── ddr4_dir_detect.sv │ │ │ ├── ddr4_rank.sv │ │ │ ├── ddr4_rcd_model.sv │ │ │ └── ddr4_sdram_model_wrapper.sv │ │ ├── vivado │ │ │ ├── pthread_post.tcl │ │ │ └── pthread_pre.tcl │ │ └── xdc │ │ │ └── BittWareXupVv8MigTiming.xdc │ ├── pcie │ │ ├── rtl │ │ │ └── BittWareXupVv8PciePhyWrapper.vhd │ │ ├── ruckus.tcl │ │ ├── xcvu13p │ │ │ ├── BittWareXupVv8PciePhy.dcp │ │ │ ├── BittWareXupVv8PciePhy.xci │ │ │ ├── BittWareXupVv8PciePhy_pcie4_ip_gt.xdc │ │ │ ├── BittWareXupVv8PciePhy_pcie4_ip_late.xdc │ │ │ └── ip_pcie4_uscale_plus_x0y1.xdc │ │ └── xcvu9p │ │ │ ├── BittWareXupVv8PciePhy.dcp │ │ │ ├── BittWareXupVv8PciePhy.xci │ │ │ ├── BittWareXupVv8PciePhy_pcie4_ip_gt.xdc │ │ │ ├── BittWareXupVv8PciePhy_pcie4_ip_late.xdc │ │ │ └── ip_pcie4_uscale_plus_x0y1.xdc │ ├── ruckus.tcl │ └── xdc │ │ ├── BittWareXupVv8App.xdc │ │ ├── BittWareXupVv8Core.xdc │ │ ├── BittWareXupVv8Vu13p.xdc │ │ └── BittWareXupVv8Vu9p.xdc ├── SlacPgpCardG4 │ ├── .gitignore │ ├── pcie │ │ ├── ip │ │ │ └── XCKU040 │ │ │ │ ├── SlacPgpCardG4PciePhy.dcp │ │ │ │ ├── SlacPgpCardG4PciePhy.xci │ │ │ │ └── SlacPgpCardG4PciePhy.xdc │ │ ├── rtl │ │ │ └── SlacPgpCardG4PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── rtl │ │ ├── AxiPciePkg.vhd │ │ └── SlacPgpCardG4Core.vhd │ ├── ruckus.tcl │ └── xdc │ │ ├── SlacPgpCardGen4App.xdc │ │ └── SlacPgpCardGen4Core.xdc ├── XilinxAlveoU200 │ ├── .gitignore │ ├── core │ │ ├── AxiPciePkg.vhd │ │ ├── TerminateQsfp.vhd │ │ └── XilinxAlveoU200Core.vhd │ ├── ddr │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── MigClkConvt.xci │ │ │ ├── XilinxAlveoU200Mig0Core.xci │ │ │ ├── XilinxAlveoU200Mig1Core.xci │ │ │ ├── XilinxAlveoU200Mig2Core.xci │ │ │ ├── XilinxAlveoU200Mig3Core.xci │ │ │ └── axi_infrastructure_v1_1_0.vh │ │ ├── rtl │ │ │ ├── Mig0.vhd │ │ │ ├── Mig1.vhd │ │ │ ├── Mig2.vhd │ │ │ ├── Mig3.vhd │ │ │ ├── MigAll.vhd │ │ │ ├── MigClkConvtWrapper.vhd │ │ │ ├── MigDmaBuffer.vhd │ │ │ └── MigPkg.vhd │ │ ├── ruckus.tcl │ │ ├── tb │ │ │ ├── Ddr4ModelWrapper.sv │ │ │ ├── ddr4_bi_delay.sv │ │ │ ├── ddr4_db_delay_model.sv │ │ │ ├── ddr4_db_dly_dir.sv │ │ │ ├── ddr4_dimm.sv │ │ │ ├── ddr4_dir_detect.sv │ │ │ ├── ddr4_rank.sv │ │ │ ├── ddr4_rcd_model.sv │ │ │ └── ddr4_sdram_model_wrapper.sv │ │ └── xdc │ │ │ ├── XilinxAlveoU200Mig0_user.xdc │ │ │ ├── XilinxAlveoU200Mig0_user_mapping.xdc │ │ │ ├── XilinxAlveoU200Mig1_user.xdc │ │ │ ├── XilinxAlveoU200Mig1_user_mapping.xdc │ │ │ ├── XilinxAlveoU200Mig2_user.xdc │ │ │ ├── XilinxAlveoU200Mig2_user_mapping.xdc │ │ │ ├── XilinxAlveoU200Mig3_user.xdc │ │ │ ├── XilinxAlveoU200Mig3_user_mapping.xdc │ │ │ └── XilinxAlveoU200MigTiming.xdc │ ├── pcie │ │ ├── ip │ │ │ ├── XilinxAlveoU200PciePhy.dcp │ │ │ ├── XilinxAlveoU200PciePhy.xci │ │ │ ├── XilinxAlveoU200PciePhy_pcie4_ip_gt.xdc │ │ │ ├── XilinxAlveoU200PciePhy_pcie4_ip_late.xdc │ │ │ └── ip_pcie4_uscale_plus_x1y2.xdc │ │ ├── rtl │ │ │ └── XilinxAlveoU200PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── revert_to_golden.mcs │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxAlveoU200App.xdc │ │ └── XilinxAlveoU200Core.xdc ├── XilinxAlveoU250 │ ├── .gitignore │ ├── core │ │ ├── AxiPciePkg.vhd │ │ ├── TerminateQsfp.vhd │ │ └── XilinxAlveoU250Core.vhd │ ├── ddr │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── XilinxAlveoU250Mig0Core.xci │ │ │ ├── XilinxAlveoU250Mig1Core.xci │ │ │ ├── XilinxAlveoU250Mig2Core.xci │ │ │ └── XilinxAlveoU250Mig3Core.xci │ │ ├── rtl │ │ │ ├── Mig0.vhd │ │ │ ├── Mig1.vhd │ │ │ ├── Mig2.vhd │ │ │ ├── Mig3.vhd │ │ │ ├── MigAll.vhd │ │ │ └── MigPkg.vhd │ │ ├── ruckus.tcl │ │ ├── tb │ │ │ ├── Ddr4ModelWrapper.sv │ │ │ ├── ddr4_bi_delay.sv │ │ │ ├── ddr4_db_delay_model.sv │ │ │ ├── ddr4_db_dly_dir.sv │ │ │ ├── ddr4_dimm.sv │ │ │ ├── ddr4_dir_detect.sv │ │ │ ├── ddr4_rank.sv │ │ │ ├── ddr4_rcd_model.sv │ │ │ └── ddr4_sdram_model_wrapper.sv │ │ └── xdc │ │ │ ├── XilinxAlveoU250Mig0_user.xdc │ │ │ ├── XilinxAlveoU250Mig0_user_mapping.xdc │ │ │ ├── XilinxAlveoU250Mig1_user.xdc │ │ │ ├── XilinxAlveoU250Mig1_user_mapping.xdc │ │ │ ├── XilinxAlveoU250Mig2_user.xdc │ │ │ ├── XilinxAlveoU250Mig2_user_mapping.xdc │ │ │ ├── XilinxAlveoU250Mig3_user.xdc │ │ │ ├── XilinxAlveoU250Mig3_user_mapping.xdc │ │ │ └── XilinxAlveoU250MigTiming.xdc │ ├── pcie │ │ ├── ip │ │ │ ├── XilinxAlveoU250PciePhy.dcp │ │ │ ├── XilinxAlveoU250PciePhy.xci │ │ │ ├── XilinxAlveoU250PciePhy_pcie4_ip_gt.xdc │ │ │ ├── XilinxAlveoU250PciePhy_pcie4_ip_late.xdc │ │ │ └── ip_pcie4_uscale_plus_x0y1.xdc │ │ ├── rtl │ │ │ └── XilinxAlveoU250PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxAlveoU250App.xdc │ │ └── XilinxAlveoU250Core.xdc ├── XilinxAlveoU280 │ ├── .gitignore │ ├── ddr │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── XilinxAlveoU280Mig0Core.xci │ │ │ └── XilinxAlveoU280Mig1Core.xci │ │ ├── rtl │ │ │ ├── Mig0.vhd │ │ │ ├── Mig1.vhd │ │ │ ├── MigAll.vhd │ │ │ └── MigPkg.vhd │ │ ├── ruckus.tcl │ │ ├── tb │ │ │ ├── Ddr4ModelWrapper.sv │ │ │ ├── ddr4_bi_delay.sv │ │ │ ├── ddr4_db_delay_model.sv │ │ │ ├── ddr4_db_dly_dir.sv │ │ │ ├── ddr4_dimm.sv │ │ │ ├── ddr4_dir_detect.sv │ │ │ ├── ddr4_rank.sv │ │ │ ├── ddr4_rcd_model.sv │ │ │ └── ddr4_sdram_model_wrapper.sv │ │ └── xdc │ │ │ ├── XilinxAlveoU280Mig0_user.xdc │ │ │ ├── XilinxAlveoU280Mig0_user_mapping.xdc │ │ │ ├── XilinxAlveoU280Mig1_user.xdc │ │ │ ├── XilinxAlveoU280Mig1_user_mapping.xdc │ │ │ └── XilinxAlveoU280MigTiming.xdc │ ├── misc │ │ ├── AxiPciePkg.vhd │ │ └── TerminateQsfp.vhd │ ├── pcie-3x16 │ │ ├── ip │ │ │ ├── XilinxAlveoU280PciePhyGen3x16.dcp │ │ │ ├── XilinxAlveoU280PciePhyGen3x16.xci │ │ │ ├── XilinxAlveoU280PciePhyGen3x16_pcie4c_ip_gt.xdc │ │ │ ├── XilinxAlveoU280PciePhyGen3x16_pcie4c_ip_late.xdc │ │ │ └── ip_pcie4_uscale_plus_x1y0.xdc │ │ ├── rtl │ │ │ ├── XilinxAlveoU280Core.vhd │ │ │ └── XilinxAlveoU280PciePhyWrapper.vhd │ │ ├── ruckus.tcl │ │ └── xdc │ │ │ └── XilinxAlveoU280Timing.xdc │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxAlveoU280App.xdc │ │ └── XilinxAlveoU280Core.xdc ├── XilinxAlveoU50 │ ├── .gitignore │ ├── misc │ │ ├── AxiPciePkg.vhd │ │ └── TerminateQsfp.vhd │ ├── pcie-3x16 │ │ ├── ip │ │ │ ├── XilinxAlveoU50PciePhyGen3x16.dcp │ │ │ ├── XilinxAlveoU50PciePhyGen3x16.xci │ │ │ ├── XilinxAlveoU50PciePhyGen3x16_pcie4c_ip_gt.xdc │ │ │ ├── XilinxAlveoU50PciePhyGen3x16_pcie4c_ip_late.xdc │ │ │ └── ip_pcie4c_uscale_plus_x1y0.xdc │ │ ├── rtl │ │ │ ├── XilinxAlveoU50Core.vhd │ │ │ └── XilinxAlveoU50PciePhyWrapper.vhd │ │ ├── ruckus.tcl │ │ └── xdc │ │ │ └── XilinxAlveoU50Timing.xdc │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxAlveoU50App.xdc │ │ └── XilinxAlveoU50Core.xdc ├── XilinxAlveoU55c │ ├── .gitignore │ ├── bd │ │ ├── 2024.2 │ │ │ ├── CmsBlockDesign.bd │ │ │ └── CmsBlockDesign.tcl │ │ ├── rtl │ │ │ └── CmsBlockDesignWrapper.vhd │ │ └── ruckus.tcl │ ├── misc │ │ ├── AxiPciePkg.vhd │ │ ├── CmsQsfpCdrDisable.vhd │ │ └── TerminateQsfp.vhd │ ├── pcie-4x8 │ │ ├── ip │ │ │ ├── XilinxAlveoU55cPciePhyGen4x8.dcp │ │ │ ├── XilinxAlveoU55cPciePhyGen4x8.xci │ │ │ ├── XilinxAlveoU55cPciePhyGen4x8_pcie4c_ip_gt.xdc │ │ │ ├── XilinxAlveoU55cPciePhyGen4x8_pcie4c_ip_late.xdc │ │ │ ├── ip_pcie4c_uscale_plus_impl_x1y1.xdc │ │ │ └── ip_pcie4c_uscale_plus_x1y1.xdc │ │ ├── rtl │ │ │ ├── XilinxAlveoU55cCore.vhd │ │ │ └── XilinxAlveoU55cPciePhyWrapper.vhd │ │ ├── ruckus.tcl │ │ └── xdc │ │ │ └── XilinxAlveoU55cTiming.xdc │ ├── pll-config │ │ ├── Si5394A_GT_REFCLK_156MHz.csv │ │ ├── Si5394A_GT_REFCLK_156MHz.mem │ │ ├── Si5394A_GT_REFCLK_161MHz.csv │ │ └── Si5394A_GT_REFCLK_161MHz.mem │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxAlveoU55cApp.xdc │ │ └── XilinxAlveoU55cCore.xdc ├── XilinxKcu105 │ ├── pcie │ │ ├── ip │ │ │ ├── XilinxKcu105PciePhy.dcp │ │ │ ├── XilinxKcu105PciePhy.xci │ │ │ └── XilinxKcu105PciePhy.xdc │ │ ├── rtl │ │ │ └── XilinxKcu105PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── rtl │ │ ├── AxiPciePkg.vhd │ │ └── XilinxKcu105Core.vhd │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxKcu105App.xdc │ │ └── XilinxKcu105Core.xdc ├── XilinxKcu116 │ ├── pcie │ │ ├── ip │ │ │ ├── XilinxKcu116PciePhy.dcp │ │ │ ├── XilinxKcu116PciePhy.xci │ │ │ ├── XilinxKcu116PciePhy.xdc │ │ │ └── XilinxKcu116PciePhyGt.xdc │ │ ├── rtl │ │ │ └── XilinxKcu116PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── rtl │ │ ├── AxiPciePkg.vhd │ │ └── XilinxKcu116Core.vhd │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxKcu116App.xdc │ │ └── XilinxKcu116Core.xdc ├── XilinxKcu1500 │ ├── .gitignore │ ├── ddr │ │ ├── ip │ │ │ ├── .gitignore │ │ │ ├── 2018.3 │ │ │ │ ├── XilinxKcu1500Mig0Core.xci │ │ │ │ ├── XilinxKcu1500Mig1Core.xci │ │ │ │ ├── XilinxKcu1500Mig2Core.xci │ │ │ │ └── XilinxKcu1500Mig3Core.xci │ │ │ ├── 2019.1 │ │ │ │ ├── XilinxKcu1500Mig0Core.xci │ │ │ │ ├── XilinxKcu1500Mig1Core.xci │ │ │ │ ├── XilinxKcu1500Mig2Core.xci │ │ │ │ └── XilinxKcu1500Mig3Core.xci │ │ │ ├── 2022.2 │ │ │ │ ├── XilinxKcu1500Mig0Core.xci │ │ │ │ ├── XilinxKcu1500Mig1Core.xci │ │ │ │ ├── XilinxKcu1500Mig2Core.xci │ │ │ │ └── XilinxKcu1500Mig3Core.xci │ │ │ ├── MigClkConvt.xci │ │ │ └── axi_infrastructure_v1_1_0.vh │ │ ├── rtl │ │ │ ├── Mig0.vhd │ │ │ ├── Mig1.vhd │ │ │ ├── Mig2.vhd │ │ │ ├── Mig3.vhd │ │ │ ├── MigAll.vhd │ │ │ ├── MigClkConvtWrapper.vhd │ │ │ ├── MigDmaBuffer.vhd │ │ │ └── MigPkg.vhd │ │ ├── ruckus.tcl │ │ ├── tb │ │ │ ├── Ddr4ModelWrapper.sv │ │ │ └── ddr4_sdram_model_wrapper.sv │ │ ├── vivado │ │ │ ├── pthread_post.tcl │ │ │ └── pthread_pre.tcl │ │ └── xdc │ │ │ ├── XilinxKcu1500Mig0_user.xdc │ │ │ ├── XilinxKcu1500Mig0_user_mapping.xdc │ │ │ ├── XilinxKcu1500Mig1_user.xdc │ │ │ ├── XilinxKcu1500Mig1_user_mapping.xdc │ │ │ ├── XilinxKcu1500Mig2_user.xdc │ │ │ ├── XilinxKcu1500Mig2_user_mapping.xdc │ │ │ ├── XilinxKcu1500Mig3_user.xdc │ │ │ ├── XilinxKcu1500Mig3_user_mapping.xdc │ │ │ └── XilinxKcu1500MigTiming.xdc │ ├── pcie-extended │ │ ├── ip │ │ │ ├── XilinxKcu1500ExtendedPciePhy.dcp │ │ │ ├── XilinxKcu1500ExtendedPciePhy.xci │ │ │ └── XilinxKcu1500ExtendedPciePhy.xdc │ │ ├── rtl │ │ │ ├── XilinxKcu1500ExtendedPciePhyWrapper.vhd │ │ │ └── XilinxKcu1500PcieExtendedCore.vhd │ │ ├── ruckus.tcl │ │ └── xdc │ │ │ └── XilinxKcu1500PcieExtendedCore.xdc │ ├── pcie │ │ ├── ip │ │ │ ├── XilinxKcu1500PciePhy.dcp │ │ │ ├── XilinxKcu1500PciePhy.xci │ │ │ └── XilinxKcu1500PciePhy.xdc │ │ ├── rtl │ │ │ └── XilinxKcu1500PciePhyWrapper.vhd │ │ └── ruckus.tcl │ ├── rtl │ │ ├── AxiPciePkg.vhd │ │ ├── TerminateQsfp.vhd │ │ └── XilinxKcu1500Core.vhd │ ├── ruckus.tcl │ └── xdc │ │ ├── XilinxKcu1500App.xdc │ │ └── XilinxKcu1500Core.xdc ├── XilinxVariumC1100 │ ├── .gitignore │ ├── hbm │ │ ├── HbmDmaBuffer.vhd │ │ ├── HbmDmaBufferFifo.dcp │ │ ├── HbmDmaBufferFifo.xci │ │ ├── HbmDmaBufferIpCore.xci │ │ ├── HbmDmaBufferV2.vhd │ │ ├── HbmDmaBufferV2Fifo.dcp │ │ ├── HbmDmaBufferV2Fifo.xci │ │ └── HbmDmaBufferV2IpCore.xci │ ├── pcie-4x8 │ │ ├── ip │ │ │ ├── XilinxVariumC1100PciePhyGen4x8.dcp │ │ │ ├── XilinxVariumC1100PciePhyGen4x8.xci │ │ │ ├── XilinxVariumC1100PciePhyGen4x8_pcie4c_ip_gt.xdc │ │ │ ├── XilinxVariumC1100PciePhyGen4x8_pcie4c_ip_late.xdc │ │ │ ├── ip_pcie4c_uscale_plus_impl_x1y1.xdc │ │ │ └── ip_pcie4c_uscale_plus_x1y1.xdc │ │ ├── rtl │ │ │ ├── XilinxVariumC1100Core.vhd │ │ │ └── XilinxVariumC1100PciePhyWrapper.vhd │ │ ├── ruckus.tcl │ │ └── xdc │ │ │ └── XilinxVariumC1100Timing.xdc │ ├── pcie-extended │ │ ├── ip │ │ │ ├── XilinxVariumC1100ExtendedPciePhy.dcp │ │ │ ├── XilinxVariumC1100ExtendedPciePhy.xci │ │ │ ├── XilinxVariumC1100ExtendedPciePhy_pcie4c_ip_gt.xdc │ │ │ ├── XilinxVariumC1100ExtendedPciePhy_pcie4c_ip_late.xdc │ │ │ ├── ip_pcie4c_uscale_plus_impl_x1y0.xdc │ │ │ └── ip_pcie4c_uscale_plus_x1y0.xdc │ │ ├── rtl │ │ │ ├── XilinxVariumC1100ExtendedPciePhyWrapper.vhd │ │ │ └── XilinxVariumC1100PcieExtendedCore.vhd │ │ └── ruckus.tcl │ ├── ruckus.tcl │ └── tb │ │ └── HbmDmaBufferV2Tb.vhd └── XilinxVcu128 │ ├── .gitignore │ ├── misc │ ├── AxiPciePkg.vhd │ └── TerminateQsfp.vhd │ ├── pcie-3x16 │ ├── ip │ │ ├── XilinxVcu128PciePhyGen3x16.dcp │ │ ├── XilinxVcu128PciePhyGen3x16.xci │ │ ├── XilinxVcu128PciePhyGen3x16_pcie4c_ip_gt.xdc │ │ ├── XilinxVcu128PciePhyGen3x16_pcie4c_ip_late.xdc │ │ └── ip_pcie4_uscale_plus_x1y0.xdc │ ├── rtl │ │ ├── XilinxVcu128Core.vhd │ │ └── XilinxVcu128PciePhyWrapper.vhd │ ├── ruckus.tcl │ └── xdc │ │ └── XilinxVcu128Timing.xdc │ ├── ruckus.tcl │ └── xdc │ ├── XilinxVcu128App.xdc │ └── XilinxVcu128Core.xdc ├── protocol ├── gpuAsync │ ├── rtl │ │ ├── AxiPcieGpuAsyncControl.vhd │ │ └── AxiPcieGpuAsyncCore.vhd │ └── ruckus.tcl └── pip │ ├── rtl │ ├── AxiPciePipCore.vhd │ ├── AxiPciePipReg.vhd │ ├── AxiPciePipRx.vhd │ └── AxiPciePipTx.vhd │ ├── ruckus.tcl │ └── tb │ └── AxiPciePipCoreTb.vhd ├── python └── axipcie │ ├── _AxiGpuAsyncCore.py │ ├── _AxiPcieCore.py │ ├── _AxiPcieDma.py │ ├── _AxiPcieRoot.py │ ├── _AxiPipCore.py │ ├── _BittWareXupVv8QsfpGpio.py │ ├── _CmsProxy.py │ ├── _PcieAxiVersion.py │ ├── _TerminateQsfp.py │ └── __init__.py ├── scripts ├── rescanPcieFpga.sh └── updatePcieFpga ├── setup.py └── shared ├── ip ├── AxiPcie16BCrossbarIpCore │ ├── AxiPcie16BCrossbarIpCore10Ports.dcp │ ├── AxiPcie16BCrossbarIpCore10Ports.xci │ ├── AxiPcie16BCrossbarIpCore3Ports.dcp │ ├── AxiPcie16BCrossbarIpCore3Ports.xci │ ├── AxiPcie16BCrossbarIpCore4Ports.dcp │ ├── AxiPcie16BCrossbarIpCore4Ports.xci │ ├── AxiPcie16BCrossbarIpCore5Ports.dcp │ ├── AxiPcie16BCrossbarIpCore5Ports.xci │ ├── AxiPcie16BCrossbarIpCore6Ports.dcp │ ├── AxiPcie16BCrossbarIpCore6Ports.xci │ ├── AxiPcie16BCrossbarIpCore7Ports.dcp │ ├── AxiPcie16BCrossbarIpCore7Ports.xci │ ├── AxiPcie16BCrossbarIpCore8Ports.dcp │ ├── AxiPcie16BCrossbarIpCore8Ports.xci │ ├── AxiPcie16BCrossbarIpCore9Ports.dcp │ └── AxiPcie16BCrossbarIpCore9Ports.xci ├── AxiPcie16BCrossbarIpCoreWrapper.vhd ├── AxiPcie16BResize.vhd ├── AxiPcie32BCrossbarIpCore │ ├── AxiPcie32BCrossbarIpCore10Ports.dcp │ ├── AxiPcie32BCrossbarIpCore10Ports.xci │ ├── AxiPcie32BCrossbarIpCore3Ports.dcp │ ├── AxiPcie32BCrossbarIpCore3Ports.xci │ ├── AxiPcie32BCrossbarIpCore4Ports.dcp │ ├── AxiPcie32BCrossbarIpCore4Ports.xci │ ├── AxiPcie32BCrossbarIpCore5Ports.dcp │ ├── AxiPcie32BCrossbarIpCore5Ports.xci │ ├── AxiPcie32BCrossbarIpCore6Ports.dcp │ ├── AxiPcie32BCrossbarIpCore6Ports.xci │ ├── AxiPcie32BCrossbarIpCore7Ports.dcp │ ├── AxiPcie32BCrossbarIpCore7Ports.xci │ ├── AxiPcie32BCrossbarIpCore8Ports.dcp │ ├── AxiPcie32BCrossbarIpCore8Ports.xci │ ├── AxiPcie32BCrossbarIpCore9Ports.dcp │ └── AxiPcie32BCrossbarIpCore9Ports.xci ├── AxiPcie32BCrossbarIpCoreWrapper.vhd ├── AxiPcie32BResize.vhd ├── AxiPcie64BCrossbarIpCore │ ├── AxiPcie64BCrossbarIpCore10Ports.dcp │ ├── AxiPcie64BCrossbarIpCore10Ports.xci │ ├── AxiPcie64BCrossbarIpCore3Ports.dcp │ ├── AxiPcie64BCrossbarIpCore3Ports.xci │ ├── AxiPcie64BCrossbarIpCore4Ports.dcp │ ├── AxiPcie64BCrossbarIpCore4Ports.xci │ ├── AxiPcie64BCrossbarIpCore5Ports.dcp │ ├── AxiPcie64BCrossbarIpCore5Ports.xci │ ├── AxiPcie64BCrossbarIpCore6Ports.dcp │ ├── AxiPcie64BCrossbarIpCore6Ports.xci │ ├── AxiPcie64BCrossbarIpCore7Ports.dcp │ ├── AxiPcie64BCrossbarIpCore7Ports.xci │ ├── AxiPcie64BCrossbarIpCore8Ports.dcp │ ├── AxiPcie64BCrossbarIpCore8Ports.xci │ ├── AxiPcie64BCrossbarIpCore9Ports.dcp │ └── AxiPcie64BCrossbarIpCore9Ports.xci ├── AxiPcie64BCrossbarIpCoreWrapper.vhd ├── AxiPcie64BResize.vhd ├── AxiPcieCrossbarIpCoreWrapper.vhd ├── AxiPcieResize │ ├── AxiPcie16BResize8BCore.dcp │ ├── AxiPcie16BResize8BCore.xci │ ├── AxiPcie32BResize16BCore.dcp │ ├── AxiPcie32BResize16BCore.xci │ ├── AxiPcie32BResize8BCore.dcp │ ├── AxiPcie32BResize8BCore.xci │ ├── AxiPcie64BResize16BCore.dcp │ ├── AxiPcie64BResize16BCore.xci │ ├── AxiPcie64BResize32BCore.dcp │ ├── AxiPcie64BResize32BCore.xci │ ├── AxiPcie64BResize8BCore.dcp │ └── AxiPcie64BResize8BCore.xci ├── AxiPcieResizer.vhd ├── Sysmon.vhd └── SystemManagementCore │ ├── SystemManagementCore.dcp │ └── SystemManagementCore.xci ├── rtl ├── AxiPcieCommonPkg.vhd ├── AxiPcieCrossbar.vhd ├── AxiPcieDma.vhd ├── AxiPcieReg.vhd ├── AxiPcieRegWriteDeMux.vhd ├── AxiPcieSharedPkg.vhd └── AxiPcieUltrascalePlusIrqFsm.vhd └── ruckus.tcl /.flake8: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/slaclab/axi-pcie-core/HEAD/.flake8 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