├── README.md ├── LICENSE └── rtl ├── AXADRCHSM.sv ├── AXRDCH.sv ├── AXI4LITE_GPIO.sv ├── AXWRCH.sv ├── GPCORE.sv └── AXI4LITEIF.sv /README.md: -------------------------------------------------------------------------------- 1 | # axi4lite_gpio 2 | General purpose IO port with AXI4-Lite interface 3 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | MIT License 2 | 3 | Copyright (c) 2025 Smartfox Data Solutions Inc. 4 | 5 | Permission is hereby granted, free of charge, to any person obtaining a copy 6 | of this software and associated documentation files (the "Software"), to deal 7 | in the Software without restriction, including without limitation the rights 8 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 9 | copies of the Software, and to permit persons to whom the Software is 10 | furnished to do so, subject to the following conditions: 11 | 12 | The above copyright notice and this permission notice shall be included in all 13 | copies or substantial portions of the Software. 14 | 15 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 18 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 20 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 21 | SOFTWARE. 22 | -------------------------------------------------------------------------------- /rtl/AXADRCHSM.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // MIT License 4 | // 5 | // Copyright (c) 2025 Smartfox Data Solutions Inc. 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in 15 | // all copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | module AXADRCHSM ( 28 | input iCLK, 29 | input iRSTN, 30 | 31 | input [31:0] iADDR, 32 | input [2:0] iPROT, 33 | input iVALID, 34 | output oREADY, 35 | 36 | input iBUSY 37 | ); 38 | 39 | reg rdy; 40 | 41 | assign oREADY = rdy; 42 | 43 | always @(posedge iCLK or negedge iRSTN) begin 44 | if (~iRSTN) begin 45 | rdy <= 1'b1; 46 | end 47 | else begin 48 | rdy <= ~iBUSY; 49 | end 50 | end 51 | 52 | endmodule -------------------------------------------------------------------------------- /rtl/AXRDCH.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // MIT License 4 | // 5 | // Copyright (c) 2025 Smartfox Data Solutions Inc. 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in 15 | // all copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | module AXRDCH ( 28 | input iCLK, 29 | input iRSTN, 30 | 31 | input [31:0] iARADDR, 32 | input iARVALID, 33 | 34 | output[31:0] oRDATA, 35 | output[1:0] oRRESP, 36 | output oRVALID, 37 | input iRREADY, 38 | 39 | output[7:0] oPRADR, 40 | input[31:0] iPRDAT, 41 | input iPERR 42 | ); 43 | 44 | reg [7:0] rAddr; 45 | reg [31:0] rData; 46 | 47 | reg rdAct; 48 | reg [1:0] rResp, rRespQ; 49 | reg rValid; 50 | 51 | parameter[1:0] OKAY = 2'b00, 52 | SLVERR = 2'b10; 53 | 54 | parameter SET = 1'b1, 55 | RESET = 1'b0; 56 | 57 | // to AXI 58 | assign oRDATA = iPRDAT; //rData; 59 | assign oRRESP = (iPERR & rdAct) ? SLVERR : rRespQ; 60 | assign oRVALID = rValid; 61 | 62 | // to register block 63 | assign oPRADR = rAddr; 64 | 65 | // signals to register block 66 | always @(posedge iCLK or negedge iRSTN) begin 67 | if (~iRSTN) begin 68 | rAddr <= 8'h0; 69 | end 70 | else begin 71 | rAddr <= iARVALID ? iARADDR[7:0] : 8'h0; 72 | end 73 | end 74 | 75 | // signals to AXI 76 | always @(posedge iCLK or negedge iRSTN) begin 77 | if (~iRSTN) begin 78 | rdAct <= RESET; 79 | rData <= 32'h0; 80 | rRespQ <= OKAY; 81 | rValid <= RESET; 82 | end 83 | else begin 84 | if (~rdAct) begin 85 | rdAct <= iARVALID; 86 | end 87 | else begin 88 | if (iRREADY & rValid) begin 89 | rData <= 32'h0; 90 | rRespQ <= OKAY; 91 | rValid <= RESET; 92 | rdAct <= RESET; 93 | end 94 | else begin 95 | rData <= iPRDAT; 96 | rRespQ <= iPERR ? SLVERR : OKAY; 97 | rValid <= SET; 98 | rdAct <= SET; 99 | end 100 | end 101 | end 102 | end 103 | 104 | endmodule -------------------------------------------------------------------------------- /rtl/AXI4LITE_GPIO.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // MIT License 4 | // 5 | // Copyright (c) 2025 Smartfox Data Solutions Inc. 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in 15 | // all copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | module AXI4LITE_GPIO ( 28 | input CLK, 29 | input RSTN, 30 | input [31:0] GPIN, 31 | output[31:0] GPOUT, 32 | output INT, 33 | 34 | // write address channel 35 | input [31:0] AWADDR, 36 | input [2:0] AWPROT, 37 | input AWVALID, 38 | output AWREADY, 39 | 40 | // write data channel 41 | input [31:0] WDATA, 42 | input [3:0] WSTRB, 43 | input WVALID, 44 | output WREADY, 45 | 46 | // write response channel 47 | output[1:0] BRESP, 48 | output BVALID, 49 | input BREADY, 50 | 51 | // read address channel 52 | input [31:0] ARADDR, 53 | input [2:0] ARPROT, 54 | input ARVALID, 55 | output ARREADY, 56 | 57 | // read data channel 58 | output[31:0] RDATA, 59 | output[1:0] RRESP, 60 | output RVALID, 61 | input RREADY 62 | ); 63 | 64 | wire[7:0] PWADR; 65 | wire[31:0] PWDAT; 66 | wire PWRTE; 67 | wire[7:0] PRADR; 68 | wire[31:0] PRDAT; 69 | wire PERR; 70 | 71 | 72 | AXI4LITEIF AXI4LITEIF ( 73 | .iCLK (CLK), 74 | .iRSTN (RSTN), 75 | 76 | .iAWADDR (AWADDR), 77 | .iAWPROT (AWPROT), 78 | .iAWVALID (AWVALID), 79 | .oAWREADY (AWREADY), 80 | .iWDATA (WDATA), 81 | .iWSTRB (WSTRB), 82 | .iWVALID (WVALID), 83 | .oWREADY (WREADY), 84 | .oBRESP (BRESP), 85 | .oBVALID (BVALID), 86 | .iBREADY (BREADY), 87 | .iARADDR (ARADDR), 88 | .iARPROT (ARPROT), 89 | .iARVALID (ARVALID), 90 | .oARREADY (ARREADY), 91 | .oRDATA (RDATA), 92 | .oRRESP (RRESP), 93 | .oRVALID (RVALID), 94 | .iRREADY (RREADY), 95 | 96 | .oPWADR (PWADR), 97 | .oPWDAT (PWDAT), 98 | .oPWRTE (PWRTE), 99 | .oPRADR (PRADR), 100 | .iPRDAT (PRDAT), 101 | .iPERR (PERR) 102 | ); 103 | 104 | GPCORE GPCORE ( 105 | .iCLK (CLK), 106 | .iRSTN (RSTN), 107 | 108 | .iWADR (PWADR), 109 | .iWR (PWRTE), 110 | .iWDAT (PWDAT), 111 | .iRADR (PRADR), 112 | .oRDAT (PRDAT), 113 | .oERR (PERR), 114 | 115 | .iGPIN (GPIN), 116 | .oGPOUT (GPOUT), 117 | .oINT (INT) 118 | ); 119 | 120 | endmodule 121 | -------------------------------------------------------------------------------- /rtl/AXWRCH.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // MIT License 4 | // 5 | // Copyright (c) 2025 Smartfox Data Solutions Inc. 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in 15 | // all copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | module AXWRCH ( 28 | input iCLK, 29 | input iRSTN, 30 | 31 | input [31:0] iAWADDR, 32 | input [31:0] iWDATA, 33 | input [3:0] iWSTRB, 34 | input iWVALID, 35 | output oWREADY, 36 | 37 | input iARVALID, 38 | 39 | output[1:0] oBRESP, 40 | output oBVALID, 41 | input iBREADY, 42 | 43 | output[7:0] oPWADR, 44 | output[31:0] oPWDAT, 45 | output oPWRTE, 46 | input iPERR 47 | ); 48 | 49 | reg [7:0] wAddr; 50 | reg [31:0] wData; 51 | reg wEna; 52 | 53 | reg wrAct; 54 | reg wReady; 55 | reg [1:0] bResp, bRespQ; 56 | reg bValid; 57 | 58 | parameter[1:0] OKAY = 2'b00, 59 | SLVERR = 2'b10; 60 | 61 | parameter SET = 1'b1, 62 | RESET = 1'b0; 63 | 64 | // to AXI 65 | assign oWREADY = wReady; 66 | assign oBRESP = iPERR ? SLVERR : bRespQ; 67 | assign oBVALID = bValid; 68 | 69 | // to register block 70 | assign oPWADR = wAddr; 71 | assign oPWDAT = wData; 72 | assign oPWRTE = wEna; 73 | 74 | // signals to register block 75 | always @(posedge iCLK or negedge iRSTN) begin 76 | if (~iRSTN) begin 77 | wAddr <= 8'h0; 78 | wData <= 32'h0; 79 | wEna <= RESET; 80 | end 81 | else begin 82 | if (iWVALID & ~wrAct) begin 83 | wAddr <= iAWADDR[7:0]; 84 | wData <= iWDATA; 85 | wEna <= &iWSTRB; 86 | end 87 | else begin 88 | wAddr <= 8'h0; 89 | wData <= 32'h0; 90 | wEna <= RESET; 91 | end 92 | end 93 | end 94 | 95 | // signals to AXI 96 | always @(posedge iCLK or negedge iRSTN) begin 97 | if (~iRSTN) begin 98 | wReady <= SET; 99 | wrAct <= RESET; 100 | bResp <= OKAY; 101 | bRespQ <= OKAY; 102 | bValid <= RESET; 103 | end 104 | else begin 105 | // reset write active if read valid is received 106 | wReady <= iARVALID ? RESET : SET; 107 | 108 | // register resp to make timing as iPERR 109 | bRespQ <= bResp; 110 | 111 | if (~wrAct) begin 112 | wrAct <= iWVALID; 113 | end 114 | else begin 115 | if (~bValid) begin 116 | bValid <= SET; 117 | bResp <= &iWSTRB ? OKAY : SLVERR; 118 | end 119 | else begin 120 | if (iBREADY) begin 121 | bValid <= RESET; 122 | bResp <= OKAY; 123 | wrAct <= RESET; 124 | end 125 | end 126 | end 127 | end 128 | end 129 | 130 | endmodule -------------------------------------------------------------------------------- /rtl/GPCORE.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // MIT License 4 | // 5 | // Copyright (c) 2025 Smartfox Data Solutions Inc. 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in 15 | // all copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | module GPCORE ( 28 | input iCLK, 29 | input iRSTN, 30 | input [7:0] iWADR, 31 | input iWR, 32 | input [31:0] iWDAT, 33 | input [7:0] iRADR, 34 | output[31:0] oRDAT, 35 | 36 | input [31:0] iGPIN, 37 | output[31:0] oGPOUT, 38 | output oINT, 39 | 40 | output oERR 41 | ); 42 | 43 | reg[31:0] rGpDat; 44 | reg[31:0] rGpDir; 45 | reg rGpIen; 46 | reg rGpInt; 47 | reg rGpClr; 48 | 49 | reg[7:0] regAdr; 50 | reg[31:0] regDat, regDatQ; 51 | reg isErr, isErrQ; 52 | 53 | wire[31:0] gpInDir; 54 | reg gpInt; 55 | 56 | parameter[7:0] GPDAT = 8'h0, 57 | GPDIR = 8'h1, 58 | GPIEN = 8'h2, 59 | GPINT = 8'h3; 60 | 61 | assign oRDAT = regDatQ; 62 | assign oERR = isErrQ; 63 | assign oINT = rGpInt; 64 | assign oGPOUT = rGpDat & ~rGpDir; 65 | 66 | // interrupt logic 67 | assign gpInDir = rGpDir & iGPIN; 68 | always @* gpInt = (rGpIen & |gpInDir); 69 | always @(posedge iCLK or negedge iRSTN) begin 70 | if (~iRSTN) begin 71 | rGpInt <= 1'b0; 72 | end 73 | else begin 74 | if (~rGpInt) begin 75 | rGpInt <= gpInt; 76 | end 77 | else begin 78 | rGpInt <= ~rGpClr; 79 | end 80 | end 81 | end 82 | 83 | // select address 84 | always @* regAdr = iWR ? iWADR : iRADR; 85 | 86 | // write to register 87 | always @(posedge iCLK or negedge iRSTN) begin 88 | if (~iRSTN) begin 89 | rGpDat <= 32'h0; 90 | rGpDir <= 32'h0; 91 | rGpIen <= 1'b0; 92 | rGpInt <= 1'b0; 93 | rGpClr <= 1'b0; 94 | end 95 | else begin 96 | case (regAdr) 97 | GPDAT: begin 98 | if (iWR) rGpDat <= iWDAT & ~rGpDir; 99 | end 100 | GPDIR: begin 101 | if (iWR) rGpDir <= iWDAT; 102 | end 103 | GPIEN: begin 104 | if (iWR) rGpIen <= iWDAT[0]; 105 | end 106 | GPINT: begin 107 | if (iWR) rGpClr <= iWDAT[0] & rGpInt; 108 | end 109 | default: begin 110 | end 111 | endcase 112 | end 113 | end 114 | 115 | // register access status 116 | always @* begin 117 | isErr = 1'b0; 118 | case (regAdr) 119 | GPDAT, 120 | GPDIR, 121 | GPIEN, 122 | GPINT: isErr = 1'b0; 123 | default: isErr = iWR; 124 | endcase 125 | end 126 | 127 | // read from register 128 | always @* begin 129 | regDat = 32'h0; 130 | case (regAdr) 131 | GPDAT: regDat = rGpDat; 132 | GPDIR: regDat = rGpDir; 133 | GPIEN: regDat = {31'h0, rGpIen}; 134 | GPINT: regDat = {31'h0, rGpInt}; 135 | default: regDat = 32'h0; 136 | endcase 137 | end 138 | 139 | // register outputs 140 | always @(posedge iCLK or negedge iRSTN) begin 141 | if (~iRSTN) begin 142 | isErrQ <= 1'b0; 143 | regDatQ <= 32'h0; 144 | end 145 | else begin 146 | isErrQ <= isErr; 147 | regDatQ <= regDat; 148 | end 149 | end 150 | 151 | endmodule -------------------------------------------------------------------------------- /rtl/AXI4LITEIF.sv: -------------------------------------------------------------------------------- 1 | //////////////////////////////////////////////////////////////////////////////// 2 | // 3 | // MIT License 4 | // 5 | // Copyright (c) 2025 Smartfox Data Solutions Inc. 6 | // 7 | // Permission is hereby granted, free of charge, to any person obtaining a copy 8 | // of this software and associated documentation files (the "Software"), to deal 9 | // in the Software without restriction, including without limitation the rights 10 | // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 | // copies of the Software, and to permit persons to whom the Software is 12 | // furnished to do so, subject to the following conditions: 13 | // 14 | // The above copyright notice and this permission notice shall be included in 15 | // all copies or substantial portions of the Software. 16 | // 17 | // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 | // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 | // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 20 | // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 | // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 | // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 23 | // SOFTWARE. 24 | // 25 | //////////////////////////////////////////////////////////////////////////////// 26 | 27 | module AXI4LITEIF ( 28 | input iCLK, 29 | input iRSTN, 30 | 31 | // write address channel 32 | input [3:0] iAWID, 33 | input [31:0] iAWADDR, //AXI4-Lite 34 | input [3:0] iAWLEN, 35 | input [2:0] iAWSIZE, 36 | input [1:0] iAWBURST, 37 | input [1:0] iAWLOCK, 38 | input [3:0] iAWCACHE, 39 | input [2:0] iAWPROT, //AXI4-Lite 40 | input iAWQOS, 41 | input iAWREGION, 42 | input iAWVALID, //AXI4-Lite 43 | output oAWREADY, //AXI4-Lite 44 | 45 | // write data channel 46 | input [3:0] iWID, 47 | input [31:0] iWDATA, //AXI4-Lite 48 | input [3:0] iWSTRB, //AXI4-Lite 49 | input iWLAST, 50 | input iWVALID, //AXI4-Lite 51 | output oWREADY, //AXI4-Lite 52 | 53 | // write response channel 54 | output[3:0] oBID, 55 | output[1:0] oBRESP, //AXI4-Lite 56 | output oBVALID, //AXI4-Lite 57 | input iBREADY, //AXI4-Lite 58 | 59 | // read address channel 60 | input [3:0] iARID, 61 | input [31:0] iARADDR, //AXI4-Lite 62 | input [3:0] iARLEN, 63 | input [2:0] iARSIZE, 64 | input [1:0] iARBURST, 65 | input [1:0] iARLOCK, 66 | input [3:0] iARCACHE, 67 | input [2:0] iARPROT, //AXI4-Lite 68 | input iARQOS, 69 | input iARREGION, 70 | input iARVALID, //AXI4-Lite 71 | output oARREADY, //AXI4-Lite 72 | 73 | // read data channel 74 | output[3:0] oRID, 75 | output[31:0] oRDATA, //AXI4-Lite 76 | output[1:0] oRRESP, //AXI4-Lite 77 | output oRLAST, 78 | output oRVALID, //AXI4-Lite 79 | input iRREADY, //AXI4-Lite 80 | 81 | // interface to register block 82 | output[7:0] oPWADR, 83 | output[31:0] oPWDAT, 84 | output oPWRTE, 85 | output[7:0] oPRADR, 86 | input[31:0] iPRDAT, 87 | input iPERR 88 | ); 89 | 90 | //AXI4-Lite 91 | // - all transactions are of burst lenght 1 92 | // - all data accesses use the full width of the data bus (32bit or 64bit) 93 | // - all accesses are non-modifiable, non-bufferable 94 | // - exclusive accesses are not supported 95 | AXADRCHSM WRADRCH ( 96 | .iCLK (iCLK), 97 | .iRSTN (iRSTN), 98 | 99 | .iADDR (iAWADDR), 100 | .iPROT (iAWPROT), 101 | .iVALID (iAWVALID), 102 | .oREADY (oAWREADY), 103 | 104 | .iBUSY (iARVALID & ~iAWVALID) 105 | ); 106 | 107 | AXWRCH WRDATCH ( 108 | .iCLK (iCLK), 109 | .iRSTN (iRSTN), 110 | 111 | .iAWADDR (iAWADDR), 112 | .iWDATA (iWDATA), 113 | .iWSTRB (iWSTRB), 114 | .iWVALID (iWVALID), 115 | .oWREADY (oWREADY), 116 | 117 | .iARVALID (iARVALID), 118 | 119 | .oBRESP (oBRESP), 120 | .oBVALID (oBVALID), 121 | .iBREADY (iBREADY), 122 | 123 | .oPWADR (oPWADR), 124 | .oPWDAT (oPWDAT), 125 | .oPWRTE (oPWRTE), 126 | .iPERR (iPERR) 127 | ); 128 | 129 | AXADRCHSM RDADRCH ( 130 | .iCLK (iCLK), 131 | .iRSTN (iRSTN), 132 | 133 | .iADDR (iARADDR), 134 | .iPROT (iARPROT), 135 | .iVALID (iARVALID), 136 | .oREADY (oARREADY), 137 | 138 | .iBUSY (iAWVALID) 139 | ); 140 | 141 | AXRDCH RDDATCH ( 142 | .iCLK (iCLK), 143 | .iRSTN (iRSTN), 144 | 145 | .iARADDR (iARADDR), 146 | .iARVALID (iARVALID), 147 | 148 | .oRDATA (oRDATA), 149 | .oRRESP (oRRESP), 150 | .oRVALID (oRVALID), 151 | .iRREADY (iRREADY), 152 | 153 | .oPRADR (oPRADR), 154 | .iPRDAT (iPRDAT), 155 | .iPERR (iPERR) 156 | ); 157 | 158 | endmodule 159 | --------------------------------------------------------------------------------