├── .gitignore ├── LICENSE.NVDLA ├── LICENSE.soDLA ├── Makefile ├── README.md ├── docs ├── cacc.md ├── cmac.md ├── configuration_calculations.md ├── imgs │ ├── arb_test0.jpg │ ├── axi4.png │ ├── cmac_floorplan.png │ ├── cmac_hierarchy.png │ ├── fig42.PNG │ ├── verif0.PNG │ ├── verif1.png │ ├── verif2.PNG │ ├── verif3.png │ └── weight0.PNG ├── mcif.md ├── rdma.md ├── register_configurations.md └── verification_environment.md ├── project └── build.properties ├── sodla-wrapper-chipyard1.6+vcs2018 ├── .gitignore ├── .gitmodules └── src │ └── main │ └── scala │ ├── ConfigFragments.scala │ ├── devices │ └── sodla │ │ ├── Periphery.scala │ │ └── SODLA.scala │ └── ip │ └── sodla.scala ├── sodla-wrapper ├── .gitignore ├── .gitmodules └── src │ └── main │ ├── resources │ └── SO_small.v │ └── scala │ ├── ConfigFragments.scala │ ├── devices │ └── sodla │ │ ├── Periphery.scala │ │ └── SODLA.scala │ └── ip │ └── sodla.scala ├── sodla.v ├── src ├── main │ └── scala │ │ ├── nvdla │ │ ├── apb2csb │ │ │ └── NV_NVDLA_apb2csb.scala │ │ ├── cacc │ │ │ ├── NV_NVDLA_CACC_CALC_int8.scala │ │ │ ├── NV_NVDLA_CACC_assembly_buffer.scala │ │ │ ├── NV_NVDLA_CACC_assembly_ctrl.scala │ │ │ ├── NV_NVDLA_CACC_calculator.scala │ │ │ ├── NV_NVDLA_CACC_config.scala │ │ │ ├── NV_NVDLA_CACC_delivery_buffer.scala │ │ │ ├── NV_NVDLA_CACC_delivery_ctrl.scala │ │ │ ├── NV_NVDLA_CACC_dual_reg.scala │ │ │ ├── NV_NVDLA_CACC_regfile.scala │ │ │ └── NV_NVDLA_cacc.scala │ │ ├── car │ │ │ ├── NV_NVDLA_core_reset.scala │ │ │ ├── NV_NVDLA_reset.scala │ │ │ ├── NV_NVDLA_sync3d.scala │ │ │ └── NV_NVDLA_sync3d_s.scala │ │ ├── cbuf │ │ │ ├── NV_NVDLA_CBUF_config.scala │ │ │ └── NV_NVDLA_cbuf.scala │ │ ├── cdma │ │ │ ├── NV_NVDLA_CDMA_CVT_cell.scala │ │ │ ├── NV_NVDLA_CDMA_IMG_ctrl.scala │ │ │ ├── NV_NVDLA_CDMA_IMG_pack.scala │ │ │ ├── NV_NVDLA_CDMA_IMG_sg.scala │ │ │ ├── NV_NVDLA_CDMA_WT_sp_arb.scala │ │ │ ├── NV_NVDLA_CDMA_config.scala │ │ │ ├── NV_NVDLA_CDMA_cvt.scala │ │ │ ├── NV_NVDLA_CDMA_dc.scala │ │ │ ├── NV_NVDLA_CDMA_dma_mux.scala │ │ │ ├── NV_NVDLA_CDMA_dual_reg.scala │ │ │ ├── NV_NVDLA_CDMA_img.scala │ │ │ ├── NV_NVDLA_CDMA_regfile.scala │ │ │ ├── NV_NVDLA_CDMA_shared_buffer.scala │ │ │ ├── NV_NVDLA_CDMA_single_reg.scala │ │ │ ├── NV_NVDLA_CDMA_status.scala │ │ │ ├── NV_NVDLA_CDMA_wt.scala │ │ │ └── NV_NVDLA_cdma.scala │ │ ├── cdp │ │ │ ├── NV_NVDLA_CDP_DP_BUFFERIN_helper.scala │ │ │ ├── NV_NVDLA_CDP_DP_INTP_unit.scala │ │ │ ├── NV_NVDLA_CDP_DP_LUT_CTRL_unit.scala │ │ │ ├── NV_NVDLA_CDP_DP_LUT_ctrl.scala │ │ │ ├── NV_NVDLA_CDP_DP_bufferin.scala │ │ │ ├── NV_NVDLA_CDP_DP_bufferin_tp1.scala │ │ │ ├── NV_NVDLA_CDP_DP_cvtin.scala │ │ │ ├── NV_NVDLA_CDP_DP_cvtout.scala │ │ │ ├── NV_NVDLA_CDP_DP_intp.scala │ │ │ ├── NV_NVDLA_CDP_DP_lut.scala │ │ │ ├── NV_NVDLA_CDP_DP_mul.scala │ │ │ ├── NV_NVDLA_CDP_DP_nan.scala │ │ │ ├── NV_NVDLA_CDP_DP_sum.scala │ │ │ ├── NV_NVDLA_CDP_DP_syncfifo.scala │ │ │ ├── NV_NVDLA_CDP_RDMA_REG_dual.scala │ │ │ ├── NV_NVDLA_CDP_RDMA_eg.scala │ │ │ ├── NV_NVDLA_CDP_RDMA_ig.scala │ │ │ ├── NV_NVDLA_CDP_RDMA_reg.scala │ │ │ ├── NV_NVDLA_CDP_REG_dual.scala │ │ │ ├── NV_NVDLA_CDP_REG_single.scala │ │ │ ├── NV_NVDLA_CDP_config.scala │ │ │ ├── NV_NVDLA_CDP_dp.scala │ │ │ ├── NV_NVDLA_CDP_rdma.scala │ │ │ ├── NV_NVDLA_CDP_reg.scala │ │ │ ├── NV_NVDLA_CDP_wdma.scala │ │ │ ├── NV_NVDLA_cdp.scala │ │ │ ├── int_sum_block.scala │ │ │ └── int_sum_block_tp1.scala │ │ ├── cfgrom │ │ │ ├── NV_NVDLA_CFGROM_rom.scala │ │ │ └── NV_NVDLA_cfgrom.scala │ │ ├── cmac │ │ │ ├── NV_NVDLA_CMAC_CORE_active.scala │ │ │ ├── NV_NVDLA_CMAC_CORE_mac.scala │ │ │ ├── NV_NVDLA_CMAC_CORE_rt_in.scala │ │ │ ├── NV_NVDLA_CMAC_CORE_rt_out.scala │ │ │ ├── NV_NVDLA_CMAC_REG_dual.scala │ │ │ ├── NV_NVDLA_CMAC_config.scala │ │ │ ├── NV_NVDLA_CMAC_core.scala │ │ │ ├── NV_NVDLA_CMAC_reg.scala │ │ │ └── NV_NVDLA_cmac.scala │ │ ├── csb_master │ │ │ ├── NV_NVDLA_CSB_MASTER_csb2falcon_fifo.scala │ │ │ ├── NV_NVDLA_CSB_MASTER_falcon2csb_fifo.scala │ │ │ ├── NV_NVDLA_CSB_MASTER_helper.scala │ │ │ └── NV_NVDLA_csb_master.scala │ │ ├── csc │ │ │ ├── NV_NVDLA_CSC_WL_dec.scala │ │ │ ├── NV_NVDLA_CSC_config.scala │ │ │ ├── NV_NVDLA_CSC_dl.scala │ │ │ ├── NV_NVDLA_CSC_dual_reg.scala │ │ │ ├── NV_NVDLA_CSC_regfile.scala │ │ │ ├── NV_NVDLA_CSC_sg.scala │ │ │ ├── NV_NVDLA_CSC_wl.scala │ │ │ └── NV_NVDLA_csc.scala │ │ ├── glb │ │ │ ├── NV_NVDLA_GLB_CSB_reg.scala │ │ │ ├── NV_NVDLA_GLB_csb.scala │ │ │ ├── NV_NVDLA_GLB_fc.scala │ │ │ ├── NV_NVDLA_GLB_ic.scala │ │ │ └── NV_NVDLA_glb.scala │ │ ├── nocif │ │ │ ├── NV_NVDLA_DMAIF_rdreq.scala │ │ │ ├── NV_NVDLA_DMAIF_rdrsp.scala │ │ │ ├── NV_NVDLA_DMAIF_wr.scala │ │ │ ├── NV_NVDLA_MCIF_CSB_reg.scala │ │ │ ├── NV_NVDLA_MCIF_READ_IG_arb.scala │ │ │ ├── NV_NVDLA_MCIF_READ_IG_bpt.scala │ │ │ ├── NV_NVDLA_MCIF_READ_eg.scala │ │ │ ├── NV_NVDLA_MCIF_READ_ig.scala │ │ │ ├── NV_NVDLA_MCIF_WRITE_IG_arb.scala │ │ │ ├── NV_NVDLA_MCIF_WRITE_IG_bpt.scala │ │ │ ├── NV_NVDLA_MCIF_WRITE_IG_cvt.scala │ │ │ ├── NV_NVDLA_MCIF_WRITE_eg.scala │ │ │ ├── NV_NVDLA_MCIF_WRITE_ig.scala │ │ │ ├── NV_NVDLA_MCIF_csb.scala │ │ │ ├── NV_NVDLA_MCIF_read.scala │ │ │ ├── NV_NVDLA_MCIF_write.scala │ │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.scala │ │ │ ├── NV_NVDLA_XXIF_READ_IG_cvt.scala │ │ │ ├── NV_NVDLA_XXIF_WRITE_cq.scala │ │ │ ├── NV_NVDLA_XXIF_config.scala │ │ │ ├── NV_NVDLA_mcif.scala │ │ │ └── NV_NVDLA_nocif.scala │ │ ├── pdp │ │ │ ├── NV_NVDLA_PDP_CORE_cal1d.scala │ │ │ ├── NV_NVDLA_PDP_CORE_cal2d.scala │ │ │ ├── NV_NVDLA_PDP_CORE_preproc.scala │ │ │ ├── NV_NVDLA_PDP_CORE_unit1d.scala │ │ │ ├── NV_NVDLA_PDP_CORE_unit2d_part1.scala │ │ │ ├── NV_NVDLA_PDP_CORE_unit2d_part2.scala │ │ │ ├── NV_NVDLA_PDP_RDMA_REG_dual.scala │ │ │ ├── NV_NVDLA_PDP_RDMA_eg.scala │ │ │ ├── NV_NVDLA_PDP_RDMA_ig.scala │ │ │ ├── NV_NVDLA_PDP_RDMA_reg.scala │ │ │ ├── NV_NVDLA_PDP_REG_dual.scala │ │ │ ├── NV_NVDLA_PDP_WDMA_cmd.scala │ │ │ ├── NV_NVDLA_PDP_WDMA_dat.scala │ │ │ ├── NV_NVDLA_PDP_config.scala │ │ │ ├── NV_NVDLA_PDP_core.scala │ │ │ ├── NV_NVDLA_PDP_nan.scala │ │ │ ├── NV_NVDLA_PDP_rdma.scala │ │ │ ├── NV_NVDLA_PDP_reg.scala │ │ │ ├── NV_NVDLA_PDP_wdma.scala │ │ │ └── NV_NVDLA_pdp.scala │ │ ├── rams │ │ │ ├── nv_flopram.scala │ │ │ ├── nv_ram_rws.scala │ │ │ ├── nv_ram_rwsp.scala │ │ │ └── nv_ram_rwsthp.scala │ │ ├── retiming │ │ │ ├── NV_NVDLA_RT_cacc2glb.scala │ │ │ ├── NV_NVDLA_RT_cmac2cacc.scala │ │ │ ├── NV_NVDLA_RT_csb2dp.scala │ │ │ └── retiming.scala │ │ ├── sdp │ │ │ ├── NV_NVDLA_SDP_CORE_Y_lut.scala │ │ │ ├── NV_NVDLA_SDP_CORE_pack.scala │ │ │ ├── NV_NVDLA_SDP_CORE_unpack.scala │ │ │ ├── NV_NVDLA_SDP_CORE_y.scala │ │ │ ├── NV_NVDLA_SDP_HLS_C_int.scala │ │ │ ├── NV_NVDLA_SDP_HLS_X_int_alu.scala │ │ │ ├── NV_NVDLA_SDP_HLS_X_int_mul.scala │ │ │ ├── NV_NVDLA_SDP_HLS_X_int_relu.scala │ │ │ ├── NV_NVDLA_SDP_HLS_X_int_trt.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_cvt_top.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_idx_top.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_inp_top.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_int_alu.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_int_core.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_int_cvt.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_int_idx.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_int_inp.scala │ │ │ ├── NV_NVDLA_SDP_HLS_Y_int_mul.scala │ │ │ ├── NV_NVDLA_SDP_HLS_c.scala │ │ │ ├── NV_NVDLA_SDP_HLS_lut_expn.scala │ │ │ ├── NV_NVDLA_SDP_HLS_lut_line.scala │ │ │ ├── NV_NVDLA_SDP_HLS_x_int.scala │ │ │ ├── NV_NVDLA_SDP_MRDMA_EG_cmd.scala │ │ │ ├── NV_NVDLA_SDP_MRDMA_EG_din.scala │ │ │ ├── NV_NVDLA_SDP_MRDMA_EG_dout.scala │ │ │ ├── NV_NVDLA_SDP_MRDMA_eg.scala │ │ │ ├── NV_NVDLA_SDP_MRDMA_ig.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_EG_ro.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_REG_dual.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_dmaif.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_eg.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_ig.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_pack.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_reg.scala │ │ │ ├── NV_NVDLA_SDP_RDMA_unpack.scala │ │ │ ├── NV_NVDLA_SDP_REG_dual.scala │ │ │ ├── NV_NVDLA_SDP_REG_single.scala │ │ │ ├── NV_NVDLA_SDP_WDMA_DAT_in.scala │ │ │ ├── NV_NVDLA_SDP_WDMA_DAT_out.scala │ │ │ ├── NV_NVDLA_SDP_WDMA_cmd.scala │ │ │ ├── NV_NVDLA_SDP_WDMA_dat.scala │ │ │ ├── NV_NVDLA_SDP_WDMA_intr.scala │ │ │ ├── NV_NVDLA_SDP_WDMA_unpack.scala │ │ │ ├── NV_NVDLA_SDP_brdma.scala │ │ │ ├── NV_NVDLA_SDP_cmux.scala │ │ │ ├── NV_NVDLA_SDP_config.scala │ │ │ ├── NV_NVDLA_SDP_core.scala │ │ │ ├── NV_NVDLA_SDP_erdma.scala │ │ │ ├── NV_NVDLA_SDP_mrdma.scala │ │ │ ├── NV_NVDLA_SDP_nrdma.scala │ │ │ ├── NV_NVDLA_SDP_rdma.scala │ │ │ ├── NV_NVDLA_SDP_reg.scala │ │ │ ├── NV_NVDLA_SDP_wdma.scala │ │ │ └── NV_NVDLA_sdp.scala │ │ ├── slibs │ │ │ ├── AN2D4PO4.scala │ │ │ ├── BC_IS_pipe.scala │ │ │ ├── BC_OS_pipe.scala │ │ │ ├── BC_pipe.scala │ │ │ ├── CKLNQD12.scala │ │ │ ├── CKLNQD12PO4.scala │ │ │ ├── FIFO.scala │ │ │ ├── FIFO_new.scala │ │ │ ├── HLS_cdp_icvt.scala │ │ │ ├── HLS_cdp_ocvt.scala │ │ │ ├── IS_pipe.scala │ │ │ ├── LNQD1PO4.scala │ │ │ ├── MUX2D4.scala │ │ │ ├── MUX2HDD2.scala │ │ │ ├── NV_BLKBOX_BUFFER.scala │ │ │ ├── NV_BLKBOX_SINK.scala │ │ │ ├── NV_BLKBOX_SRC0.scala │ │ │ ├── NV_BLKBOX_SRC0_X.scala │ │ │ ├── NV_CLK_gate_power.scala │ │ │ ├── NV_DW_lsd.scala │ │ │ ├── NV_NVDLA_BASIC_REG_single.scala │ │ │ ├── NV_NVDLA_CSB_LOGIC.scala │ │ │ ├── NV_NVDLA_HLS_prelu.scala │ │ │ ├── NV_NVDLA_HLS_relu.scala │ │ │ ├── NV_NVDLA_HLS_saturate.scala │ │ │ ├── NV_NVDLA_HLS_shiftleftsu.scala │ │ │ ├── NV_NVDLA_HLS_shiftrightsatsu.scala │ │ │ ├── NV_NVDLA_HLS_shiftrightss.scala │ │ │ ├── NV_NVDLA_HLS_shiftrightsu.scala │ │ │ ├── NV_NVDLA_HLS_shiftrightusz.scala │ │ │ ├── NV_NVDLA_HLS_sync2data.scala │ │ │ ├── NV_NVDLA_MUL_unit.scala │ │ │ ├── NV_NVDLA_VEC_div_kernel.scala │ │ │ ├── NV_NVDLA_VEC_padder.scala │ │ │ ├── NV_NVDLA_arb.scala │ │ │ ├── OR2D1.scala │ │ │ ├── PGAOPV_INVD2PO4.scala │ │ │ ├── Perf_Counter.scala │ │ │ ├── SDFCNQD1.scala │ │ │ ├── SDFQD1.scala │ │ │ ├── SDFSNQD1.scala │ │ │ ├── oneHotClk_async_read_clock.scala │ │ │ ├── oneHotClk_async_write_clock.scala │ │ │ ├── p_SDFCNQD1PO4.scala │ │ │ ├── p_SSYNC2DO_C_PP.scala │ │ │ ├── p_SSYNC3DO.scala │ │ │ ├── p_SSYNC3DO_C_PPP.scala │ │ │ ├── p_SSYNC3DO_S_PPP.scala │ │ │ ├── p_STRICTSYNC3DOTM_C_PPP.scala │ │ │ ├── slcg.scala │ │ │ ├── sync2d_c_pp.scala │ │ │ ├── sync3d.scala │ │ │ ├── sync3d_c_ppp.scala │ │ │ ├── sync3d_s_ppp.scala │ │ │ └── sync_reset.scala │ │ ├── spec │ │ │ ├── configurations.scala │ │ │ ├── nv_large_config.scala │ │ │ ├── nv_small_config.scala │ │ │ ├── odif.scala │ │ │ └── projects.scala │ │ └── top │ │ │ ├── NV_NVDLA_partition_a.scala │ │ │ ├── NV_NVDLA_partition_c.scala │ │ │ ├── NV_NVDLA_partition_m.scala │ │ │ ├── NV_NVDLA_partition_o.scala │ │ │ ├── NV_NVDLA_partition_p.scala │ │ │ └── NV_nvdla.scala │ │ └── sodla.scala └── test │ ├── resources │ ├── in.im24 │ └── in.wav │ └── scala │ ├── nvdla │ ├── cmac │ │ ├── Launcher.scala │ │ ├── NV_NVDLA_CMAC_CORE_activateTests.scala │ │ ├── NV_NVDLA_CMAC_CORE_activeTests.scala │ │ ├── NV_NVDLA_CMAC_CORE_macTests.scala │ │ ├── NV_NVDLA_CMAC_CORE_rt_inTests.scala │ │ ├── NV_NVDLA_CMAC_CORE_rt_outTests.scala │ │ ├── NV_NVDLA_CMAC_REG_dualTests.scala │ │ ├── NV_NVDLA_CMAC_REG_single_Tests.scala │ │ ├── NV_NVDLA_CMAC_regTests.scala │ │ └── NV_NVDLA_CMAC_reg_vmod.scala │ └── nocif │ │ ├── NV_NVDLA_MCIF_READ_IG_arbTests.scala │ │ └── read_ig_arbTests.scala │ ├── ram │ ├── Launcher.scala │ ├── nv_ram_rwsTests.scala │ └── nv_ram_rwspTests.scala │ ├── slibs │ ├── AN2D4PO4Tests.scala │ ├── BC_IS_pipeTests.scala │ ├── BC_pipeTests.scala │ ├── CKLNQD12Tests.scala │ ├── FIFOTests.scala │ ├── IS_pipeTests.scala │ ├── Launcher.scala │ ├── MUX2D4Tests.scala │ ├── MUX2HDD2Tests.scala │ ├── OR2D1Tests.scala │ └── PGAOPV_INVD2PO4.scala │ └── utils │ ├── TutorialRunner.scala │ └── diff.scala ├── test ├── ape_lenet_small_9jpg_conv3_sdp4 │ ├── Makefile │ ├── ape_single_conv3_sdp4_revise.riscv │ ├── include │ │ ├── ape_get_ali.h │ │ └── ape_small_single.h │ ├── libgloss.mk │ ├── lite.dump │ ├── right_value.c │ ├── src │ │ ├── ape_get_ali1_data.c │ │ ├── ape_get_ali3_data.c │ │ └── ape_single.c │ └── ucli.key └── dc_1x1x8_1x1x8x1_int8_0 │ ├── Makefile │ ├── dc_1x1x8_1x1x8x1_int8_0.riscv │ ├── include │ ├── ape_get_ali.h │ └── ape_small_single.h │ ├── libgloss.mk │ ├── lite.dump │ ├── right_value.c │ └── src │ ├── ape_get_ali1_data.c │ ├── ape_get_ali3_data.c │ └── ape_single.c └── verif ├── seq ├── apb2csb │ ├── Makefile │ └── NV_NVDLA_apb2csb.tcl ├── csb_master │ ├── Makefile │ └── NV_NVDLA_csb_master.tcl ├── csc │ ├── Makefile │ ├── NV_NVDLA_CSC_dl.tcl │ └── NV_NVDLA_CSC_sg.tcl ├── fifo │ ├── Makefile │ ├── NV_NVDLA_MCIF_READ_eg_fifo.tcl │ └── NV_NVDLA_csb_master.tcl ├── glb │ ├── Makefile │ └── NV_NVDLA_glb.tcl └── nocif │ ├── Makefile │ ├── NV_NVDLA_DMAIF_rdreq.tcl │ ├── NV_NVDLA_DMAIF_rdrsp.tcl │ ├── NV_NVDLA_DMAIF_wr.tcl │ ├── NV_NVDLA_MCIF_READ_IG_bpt.tcl │ ├── NV_NVDLA_MCIF_READ_IG_cvt.tcl │ ├── NV_NVDLA_MCIF_READ_eg.tcl │ ├── NV_NVDLA_MCIF_WRITE_IG_bpt.tcl │ ├── NV_NVDLA_MCIF_WRITE_IG_cvt.tcl │ ├── NV_NVDLA_MCIF_WRITE_eg.tcl │ ├── NV_NVDLA_MCIF_csb.tcl │ ├── NV_NVDLA_MCIF_define.vh │ └── NV_NVDLA_XXIF_READ_IG_cvt.tcl ├── small_gate └── vmod │ └── nvdla │ ├── apb2csb │ ├── NV_NVDLA_apb2csb.v │ └── NV_NVDLA_apb2csb_wrapper.v │ ├── csb_master │ ├── NV_NVDLA_csb_master.v │ └── NV_NVDLA_csb_master_wrapper.v │ ├── csc │ ├── NV_NVDLA_CSC_dl.v │ ├── NV_NVDLA_CSC_dl_wrapper.v │ ├── NV_NVDLA_CSC_sg.v │ └── NV_NVDLA_CSC_sg_wrapper.v │ ├── fifo │ ├── NV_NVDLA_MCIF_READ_eg_fifo.v │ └── NV_NVDLA_MCIF_READ_eg_fifo_wrapper.v │ ├── glb │ ├── NV_NVDLA_glb.v │ └── NV_NVDLA_glb_wrapper.v │ └── nocif │ ├── NV_NVDLA_DMAIF_rdreq.v │ ├── NV_NVDLA_DMAIF_rdreq_wrapper.v │ ├── NV_NVDLA_DMAIF_rdrsp.v │ ├── NV_NVDLA_DMAIF_rdrsp_wrapper.v │ ├── NV_NVDLA_DMAIF_wr.v │ ├── NV_NVDLA_DMAIF_wr_wrapper.v │ ├── NV_NVDLA_MCIF_READ_IG_bpt.v │ ├── NV_NVDLA_MCIF_READ_IG_bpt_wrapper.v │ ├── NV_NVDLA_MCIF_READ_IG_cvt_wrapper.v │ ├── NV_NVDLA_MCIF_READ_eg.v │ ├── NV_NVDLA_MCIF_READ_eg_wrapper.v │ ├── NV_NVDLA_MCIF_READ_ig.v │ ├── NV_NVDLA_MCIF_READ_ig_wrapper.v │ ├── NV_NVDLA_MCIF_WRITE_IG_arb.v │ ├── NV_NVDLA_MCIF_WRITE_IG_arb_wrapper.v │ ├── NV_NVDLA_MCIF_WRITE_IG_bpt.v │ ├── NV_NVDLA_MCIF_WRITE_IG_bpt_wrapper.v │ ├── NV_NVDLA_MCIF_WRITE_IG_cvt.v │ ├── NV_NVDLA_MCIF_WRITE_IG_cvt_wrapper.v │ ├── NV_NVDLA_MCIF_WRITE_eg.v │ ├── NV_NVDLA_MCIF_WRITE_eg_wrapper.v │ ├── NV_NVDLA_MCIF_csb.v │ ├── NV_NVDLA_MCIF_csb_wrapper.v │ └── NV_NVDLA_XXIF_READ_IG_cvt.v └── small_gold ├── Makefile ├── defines ├── defs.v └── undefs.v ├── insert-includes.py ├── nvdla_small.preprocessed.v ├── nvdla_small.v ├── vmod ├── fifos │ ├── NV_NVDLA_CDMA_WT_8ATMM_fifo.v │ ├── NV_NVDLA_CDP_DP_data_fifo.v │ ├── NV_NVDLA_CDP_DP_intpinfo_fifo.v │ ├── NV_NVDLA_CDP_DP_sumpd_fifo.v │ ├── NV_NVDLA_CDP_RDMA_lat_fifo.v │ ├── NV_NVDLA_CDP_RDMA_ro_fifo.v │ ├── NV_NVDLA_CDP_WDMA_dat_fifo.v │ ├── NV_NVDLA_PDP_RDMA_lat_fifo.v │ ├── NV_NVDLA_PDP_RDMA_ro_fifo.v │ ├── NV_NVDLA_PDP_SDPIN_ro_fifo.v │ ├── NV_NVDLA_PDP_WDMA_DAT_fifo.v │ ├── NV_NVDLA_SDP_BRDMA_cq_lib.v │ ├── NV_NVDLA_SDP_BRDMA_lat_fifo_lib.v │ ├── NV_NVDLA_SDP_ERDMA_cq_lib.v │ ├── NV_NVDLA_SDP_ERDMA_lat_fifo_lib.v │ ├── NV_NVDLA_SDP_MRDMA_EG_lat_fifo_lib.v │ ├── NV_NVDLA_SDP_MRDMA_cq_lib.v │ ├── NV_NVDLA_SDP_NRDMA_cq_lib.v │ └── NV_NVDLA_SDP_NRDMA_lat_fifo_lib.v ├── include │ ├── NV_HWACC_NVDLA_tick_defines.vh │ ├── NV_NVDLA_MCIF_define.vh │ └── simulate_x_tick.vh ├── nvdla │ ├── apb2csb │ │ └── NV_NVDLA_apb2csb.v │ ├── bdma │ │ ├── NV_NVDLA_BDMA_cq.v │ │ ├── NV_NVDLA_BDMA_csb.v │ │ ├── NV_NVDLA_BDMA_gate.v │ │ ├── NV_NVDLA_BDMA_load.v │ │ ├── NV_NVDLA_BDMA_reg.v │ │ ├── NV_NVDLA_BDMA_store.v │ │ └── NV_NVDLA_bdma.v │ ├── cacc │ │ ├── NV_NVDLA_CACC_CALC_int8.v │ │ ├── NV_NVDLA_CACC_assembly_buffer.v │ │ ├── NV_NVDLA_CACC_assembly_ctrl.v │ │ ├── NV_NVDLA_CACC_calculator.v │ │ ├── NV_NVDLA_CACC_delivery_buffer.v │ │ ├── NV_NVDLA_CACC_delivery_ctrl.v │ │ ├── NV_NVDLA_CACC_dual_reg.v │ │ ├── NV_NVDLA_CACC_regfile.v │ │ ├── NV_NVDLA_CACC_single_reg.v │ │ ├── NV_NVDLA_CACC_slcg.v │ │ └── NV_NVDLA_cacc.v │ ├── car │ │ ├── NV_NVDLA_core_reset.v │ │ ├── NV_NVDLA_reset.v │ │ ├── NV_NVDLA_ssync3d.v │ │ ├── NV_NVDLA_ssync3d_c.v │ │ ├── NV_NVDLA_sync3d.v │ │ ├── NV_NVDLA_sync3d_c.v │ │ └── NV_NVDLA_sync3d_s.v │ ├── cbuf │ │ └── NV_NVDLA_cbuf.v │ ├── cdma │ │ ├── NV_NVDLA_CDMA_CVT_cell.v │ │ ├── NV_NVDLA_CDMA_DC_fifo.v │ │ ├── NV_NVDLA_CDMA_IMG_ctrl.v │ │ ├── NV_NVDLA_CDMA_IMG_fifo.v │ │ ├── NV_NVDLA_CDMA_IMG_pack.v │ │ ├── NV_NVDLA_CDMA_IMG_sg.v │ │ ├── NV_NVDLA_CDMA_IMG_sg2pack_fifo.v │ │ ├── NV_NVDLA_CDMA_WG_fifo.v │ │ ├── NV_NVDLA_CDMA_WT_fifo.v │ │ ├── NV_NVDLA_CDMA_WT_sp_arb.v │ │ ├── NV_NVDLA_CDMA_WT_wgs_fifo.v │ │ ├── NV_NVDLA_CDMA_WT_wrr_arb.v │ │ ├── NV_NVDLA_CDMA_cvt.v │ │ ├── NV_NVDLA_CDMA_dc.v │ │ ├── NV_NVDLA_CDMA_dma_mux.v │ │ ├── NV_NVDLA_CDMA_dual_reg.v │ │ ├── NV_NVDLA_CDMA_img.v │ │ ├── NV_NVDLA_CDMA_regfile.v │ │ ├── NV_NVDLA_CDMA_shared_buffer.v │ │ ├── NV_NVDLA_CDMA_single_reg.v │ │ ├── NV_NVDLA_CDMA_slcg.v │ │ ├── NV_NVDLA_CDMA_status.v │ │ ├── NV_NVDLA_CDMA_wg.v │ │ ├── NV_NVDLA_CDMA_wt.v │ │ ├── NV_NVDLA_cdma.swl │ │ └── NV_NVDLA_cdma.v │ ├── cdp │ │ ├── NV_NVDLA_CDP_DP_INTP_unit.v │ │ ├── NV_NVDLA_CDP_DP_LUT_CTRL_unit.v │ │ ├── NV_NVDLA_CDP_DP_LUT_ctrl.v │ │ ├── NV_NVDLA_CDP_DP_MUL_unit.v │ │ ├── NV_NVDLA_CDP_DP_bufferin.v │ │ ├── NV_NVDLA_CDP_DP_bufferin_tp1.v │ │ ├── NV_NVDLA_CDP_DP_cvtin.v │ │ ├── NV_NVDLA_CDP_DP_cvtout.v │ │ ├── NV_NVDLA_CDP_DP_intp.v │ │ ├── NV_NVDLA_CDP_DP_lut.v │ │ ├── NV_NVDLA_CDP_DP_mul.v │ │ ├── NV_NVDLA_CDP_DP_nan.v │ │ ├── NV_NVDLA_CDP_DP_sum.v │ │ ├── NV_NVDLA_CDP_DP_syncfifo.v │ │ ├── NV_NVDLA_CDP_RDMA_REG_dual.v │ │ ├── NV_NVDLA_CDP_RDMA_REG_single.v │ │ ├── NV_NVDLA_CDP_RDMA_cq.v │ │ ├── NV_NVDLA_CDP_RDMA_eg.v │ │ ├── NV_NVDLA_CDP_RDMA_ig.v │ │ ├── NV_NVDLA_CDP_RDMA_reg.v │ │ ├── NV_NVDLA_CDP_REG_dual.v │ │ ├── NV_NVDLA_CDP_REG_single.v │ │ ├── NV_NVDLA_CDP_dp.v │ │ ├── NV_NVDLA_CDP_rdma.v │ │ ├── NV_NVDLA_CDP_reg.v │ │ ├── NV_NVDLA_CDP_slcg.v │ │ ├── NV_NVDLA_CDP_wdma.v │ │ ├── NV_NVDLA_cdp.v │ │ ├── fp_format_cvt.v │ │ ├── fp_sum_block.v │ │ ├── int_sum_block.v │ │ └── int_sum_block_tp1.v │ ├── cfgrom │ │ ├── NV_NVDLA_CFGROM_rom.v │ │ └── NV_NVDLA_cfgrom.v │ ├── cmac │ │ ├── NV_NVDLA_CMAC_CORE_active.v │ │ ├── NV_NVDLA_CMAC_CORE_cfg.v │ │ ├── NV_NVDLA_CMAC_CORE_mac.v │ │ ├── NV_NVDLA_CMAC_CORE_rt_in.v │ │ ├── NV_NVDLA_CMAC_CORE_rt_out.v │ │ ├── NV_NVDLA_CMAC_CORE_slcg.v │ │ ├── NV_NVDLA_CMAC_REG_dual.v │ │ ├── NV_NVDLA_CMAC_REG_single.v │ │ ├── NV_NVDLA_CMAC_core.v │ │ ├── NV_NVDLA_CMAC_reg.v │ │ └── NV_NVDLA_cmac.v │ ├── csb_master │ │ ├── NV_NVDLA_CSB_MASTER_csb2falcon_fifo.v │ │ ├── NV_NVDLA_CSB_MASTER_falcon2csb_fifo.v │ │ ├── NV_NVDLA_csb_master.v │ │ └── NV_NVDLA_csb_master_golden_wrapper.v │ ├── csc │ │ ├── NV_NVDLA_CSC_SG_dat_fifo.v │ │ ├── NV_NVDLA_CSC_SG_wt_fifo.v │ │ ├── NV_NVDLA_CSC_WL_dec.v │ │ ├── NV_NVDLA_CSC_dl.v │ │ ├── NV_NVDLA_CSC_dl_golden_wrapper.v │ │ ├── NV_NVDLA_CSC_dual_reg.v │ │ ├── NV_NVDLA_CSC_pra_cell.v │ │ ├── NV_NVDLA_CSC_regfile.v │ │ ├── NV_NVDLA_CSC_sg.v │ │ ├── NV_NVDLA_CSC_sg_golden_wrapper.v │ │ ├── NV_NVDLA_CSC_single_reg.v │ │ ├── NV_NVDLA_CSC_slcg.v │ │ ├── NV_NVDLA_CSC_wl.v │ │ ├── NV_NVDLA_csc.swl │ │ ├── NV_NVDLA_csc.v │ │ └── tmp │ ├── glb │ │ ├── NV_NVDLA_GLB_CSB_reg.v │ │ ├── NV_NVDLA_GLB_csb.v │ │ ├── NV_NVDLA_GLB_fc.v │ │ ├── NV_NVDLA_GLB_ic.v │ │ ├── NV_NVDLA_glb.v │ │ └── NV_NVDLA_glb_golden_wrapper.v │ ├── nocif │ │ ├── NV_NVDLA_DMAIF_rdreq.v │ │ ├── NV_NVDLA_DMAIF_rdrsp.v │ │ ├── NV_NVDLA_DMAIF_wr.v │ │ ├── NV_NVDLA_MCIF_CSB_reg.v │ │ ├── NV_NVDLA_MCIF_READ_IG_arb.v │ │ ├── NV_NVDLA_MCIF_READ_IG_bpt.v │ │ ├── NV_NVDLA_MCIF_READ_IG_cvt.v │ │ ├── NV_NVDLA_MCIF_READ_eg.v │ │ ├── NV_NVDLA_MCIF_READ_ig.v │ │ ├── NV_NVDLA_MCIF_WRITE_IG_arb.v │ │ ├── NV_NVDLA_MCIF_WRITE_IG_bpt.v │ │ ├── NV_NVDLA_MCIF_WRITE_IG_cvt.v │ │ ├── NV_NVDLA_MCIF_WRITE_cq.v │ │ ├── NV_NVDLA_MCIF_WRITE_eg.v │ │ ├── NV_NVDLA_MCIF_WRITE_ig.v │ │ ├── NV_NVDLA_MCIF_csb.v │ │ ├── NV_NVDLA_MCIF_read.v │ │ ├── NV_NVDLA_MCIF_write.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_IG_arb.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_IG_bpt.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_IG_cvt.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_IG_spt.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_cq.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_eg.v │ │ ├── NV_NVDLA_NOCIF_DRAM_READ_ig.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_IG_arb.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_IG_bpt.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_IG_cvt.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_IG_spt.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_cq.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_eg.v │ │ ├── NV_NVDLA_NOCIF_DRAM_WRITE_ig.v │ │ ├── NV_NVDLA_NOCIF_DRAM_read.v │ │ ├── NV_NVDLA_NOCIF_DRAM_write.v │ │ ├── NV_NVDLA_NOCIF_dram.v │ │ ├── NV_NVDLA_XXIF_libs.v │ │ ├── NV_NVDLA_mcif.v │ │ ├── NV_NVDLA_nocif.swl │ │ └── NV_NVDLA_nocif.v │ ├── pdp │ │ ├── NV_NVDLA_PDP_CORE_cal1d.v │ │ ├── NV_NVDLA_PDP_CORE_cal2d.v │ │ ├── NV_NVDLA_PDP_CORE_preproc.v │ │ ├── NV_NVDLA_PDP_CORE_unit1d.v │ │ ├── NV_NVDLA_PDP_RDMA_REG_dual.v │ │ ├── NV_NVDLA_PDP_RDMA_REG_single.v │ │ ├── NV_NVDLA_PDP_RDMA_cq.v │ │ ├── NV_NVDLA_PDP_RDMA_eg.v │ │ ├── NV_NVDLA_PDP_RDMA_ig.v │ │ ├── NV_NVDLA_PDP_RDMA_reg.v │ │ ├── NV_NVDLA_PDP_REG_dual.v │ │ ├── NV_NVDLA_PDP_REG_single.v │ │ ├── NV_NVDLA_PDP_WDMA_cmd.v │ │ ├── NV_NVDLA_PDP_WDMA_dat.v │ │ ├── NV_NVDLA_PDP_core.v │ │ ├── NV_NVDLA_PDP_nan.v │ │ ├── NV_NVDLA_PDP_rdma.v │ │ ├── NV_NVDLA_PDP_reg.v │ │ ├── NV_NVDLA_PDP_slcg.v │ │ ├── NV_NVDLA_PDP_wdma.v │ │ ├── NV_NVDLA_pdp.v │ │ ├── cal1d_fp16_pool_sum.v │ │ └── fp16_4add.v │ ├── retiming │ │ ├── NV_NVDLA_RT_cacc2glb.v │ │ ├── NV_NVDLA_RT_cmac_a2cacc.v │ │ ├── NV_NVDLA_RT_cmac_b2cacc.v │ │ ├── NV_NVDLA_RT_csb2cacc.v │ │ ├── NV_NVDLA_RT_csb2cmac.v │ │ ├── NV_NVDLA_RT_csc2cmac_a.v │ │ ├── NV_NVDLA_RT_csc2cmac_b.v │ │ └── NV_NVDLA_RT_sdp2nocif.v │ ├── rubik │ │ ├── NV_NVDLA_RUBIK_dma.v │ │ ├── NV_NVDLA_RUBIK_dr2drc.v │ │ ├── NV_NVDLA_RUBIK_dual_reg.v │ │ ├── NV_NVDLA_RUBIK_fifo.v │ │ ├── NV_NVDLA_RUBIK_intr.v │ │ ├── NV_NVDLA_RUBIK_regfile.v │ │ ├── NV_NVDLA_RUBIK_rf_core.v │ │ ├── NV_NVDLA_RUBIK_rf_ctrl.v │ │ ├── NV_NVDLA_RUBIK_rf_rcmd.v │ │ ├── NV_NVDLA_RUBIK_rf_wcmd.v │ │ ├── NV_NVDLA_RUBIK_seq_gen.v │ │ ├── NV_NVDLA_RUBIK_single_reg.v │ │ ├── NV_NVDLA_RUBIK_slcg.v │ │ ├── NV_NVDLA_RUBIK_wr_req.v │ │ ├── NV_NVDLA_RUBIK_wrdma_cmd.v │ │ ├── NV_NVDLA_RUBIK_wrdma_data.v │ │ └── NV_NVDLA_rubik.v │ ├── sdp │ │ ├── NV_NVDLA_SDP_BRDMA_gate.v │ │ ├── NV_NVDLA_SDP_CORE_Y_lut.v │ │ ├── NV_NVDLA_SDP_CORE_gate.v │ │ ├── NV_NVDLA_SDP_CORE_pack.v │ │ ├── NV_NVDLA_SDP_CORE_unpack.v │ │ ├── NV_NVDLA_SDP_CORE_y.v │ │ ├── NV_NVDLA_SDP_ERDMA_gate.v │ │ ├── NV_NVDLA_SDP_HLS_C_int.v │ │ ├── NV_NVDLA_SDP_HLS_X_int_alu.v │ │ ├── NV_NVDLA_SDP_HLS_X_int_mul.v │ │ ├── NV_NVDLA_SDP_HLS_X_int_relu.v │ │ ├── NV_NVDLA_SDP_HLS_X_int_trt.v │ │ ├── NV_NVDLA_SDP_HLS_Y_cvt_top.v │ │ ├── NV_NVDLA_SDP_HLS_Y_idx_top.v │ │ ├── NV_NVDLA_SDP_HLS_Y_inp_top.v │ │ ├── NV_NVDLA_SDP_HLS_Y_int_alu.v │ │ ├── NV_NVDLA_SDP_HLS_Y_int_core.v │ │ ├── NV_NVDLA_SDP_HLS_Y_int_cvt.v │ │ ├── NV_NVDLA_SDP_HLS_Y_int_idx.v │ │ ├── NV_NVDLA_SDP_HLS_Y_int_inp.v │ │ ├── NV_NVDLA_SDP_HLS_Y_int_mul.v │ │ ├── NV_NVDLA_SDP_HLS_c.v │ │ ├── NV_NVDLA_SDP_HLS_lut_expn.v │ │ ├── NV_NVDLA_SDP_HLS_lut_line.v │ │ ├── NV_NVDLA_SDP_HLS_prelu.v │ │ ├── NV_NVDLA_SDP_HLS_relu.v │ │ ├── NV_NVDLA_SDP_HLS_sync2data.v │ │ ├── NV_NVDLA_SDP_HLS_x1_int.v │ │ ├── NV_NVDLA_SDP_HLS_x2_int.v │ │ ├── NV_NVDLA_SDP_MRDMA_EG_cmd.v │ │ ├── NV_NVDLA_SDP_MRDMA_EG_din.v │ │ ├── NV_NVDLA_SDP_MRDMA_EG_dout.v │ │ ├── NV_NVDLA_SDP_MRDMA_eg.v │ │ ├── NV_NVDLA_SDP_MRDMA_gate.v │ │ ├── NV_NVDLA_SDP_MRDMA_ig.v │ │ ├── NV_NVDLA_SDP_NRDMA_gate.v │ │ ├── NV_NVDLA_SDP_RDMA_EG_ro.v │ │ ├── NV_NVDLA_SDP_RDMA_REG_dual.v │ │ ├── NV_NVDLA_SDP_RDMA_REG_single.v │ │ ├── NV_NVDLA_SDP_RDMA_dmaif.v │ │ ├── NV_NVDLA_SDP_RDMA_eg.v │ │ ├── NV_NVDLA_SDP_RDMA_ig.v │ │ ├── NV_NVDLA_SDP_RDMA_pack.v │ │ ├── NV_NVDLA_SDP_RDMA_reg.v │ │ ├── NV_NVDLA_SDP_RDMA_unpack.v │ │ ├── NV_NVDLA_SDP_REG_dual.v │ │ ├── NV_NVDLA_SDP_REG_single.v │ │ ├── NV_NVDLA_SDP_WDMA_DAT_in.v │ │ ├── NV_NVDLA_SDP_WDMA_DAT_out.v │ │ ├── NV_NVDLA_SDP_WDMA_cmd.v │ │ ├── NV_NVDLA_SDP_WDMA_dat.v │ │ ├── NV_NVDLA_SDP_WDMA_gate.v │ │ ├── NV_NVDLA_SDP_WDMA_intr.v │ │ ├── NV_NVDLA_SDP_WDMA_unpack.v │ │ ├── NV_NVDLA_SDP_brdma.v │ │ ├── NV_NVDLA_SDP_cmux.v │ │ ├── NV_NVDLA_SDP_core.v │ │ ├── NV_NVDLA_SDP_erdma.v │ │ ├── NV_NVDLA_SDP_mrdma.v │ │ ├── NV_NVDLA_SDP_nrdma.v │ │ ├── NV_NVDLA_SDP_rdma.v │ │ ├── NV_NVDLA_SDP_reg.v │ │ ├── NV_NVDLA_SDP_wdma.v │ │ ├── NV_NVDLA_sdp.swl │ │ └── NV_NVDLA_sdp.v │ └── top │ │ ├── NV_NVDLA_partition_a.v │ │ ├── NV_NVDLA_partition_c.v │ │ ├── NV_NVDLA_partition_m.v │ │ ├── NV_NVDLA_partition_o.v │ │ ├── NV_NVDLA_partition_p.v │ │ └── NV_nvdla.v ├── rams │ ├── fpga │ │ └── model │ │ │ ├── nv_ram_rws_128x128.v │ │ │ ├── nv_ram_rws_128x18.v │ │ │ ├── nv_ram_rws_128x256.v │ │ │ ├── nv_ram_rws_128x32.v │ │ │ ├── nv_ram_rws_128x512.v │ │ │ ├── nv_ram_rws_128x60.v │ │ │ ├── nv_ram_rws_128x64.v │ │ │ ├── nv_ram_rws_16x128.v │ │ │ ├── nv_ram_rws_16x256.v │ │ │ ├── nv_ram_rws_16x272.v │ │ │ ├── nv_ram_rws_16x64.v │ │ │ ├── nv_ram_rws_256x128.v │ │ │ ├── nv_ram_rws_256x256.v │ │ │ ├── nv_ram_rws_256x3.v │ │ │ ├── nv_ram_rws_256x512.v │ │ │ ├── nv_ram_rws_256x64.v │ │ │ ├── nv_ram_rws_256x7.v │ │ │ ├── nv_ram_rws_32x128.v │ │ │ ├── nv_ram_rws_32x16.v │ │ │ ├── nv_ram_rws_32x256.v │ │ │ ├── nv_ram_rws_32x272.v │ │ │ ├── nv_ram_rws_32x32.v │ │ │ ├── nv_ram_rws_32x512.v │ │ │ ├── nv_ram_rws_32x544.v │ │ │ ├── nv_ram_rws_32x64.v │ │ │ ├── nv_ram_rws_32x768.v │ │ │ ├── nv_ram_rws_512x128.v │ │ │ ├── nv_ram_rws_512x256.v │ │ │ ├── nv_ram_rws_512x512.v │ │ │ ├── nv_ram_rws_512x64.v │ │ │ ├── nv_ram_rws_64x10.v │ │ │ ├── nv_ram_rws_64x1024.v │ │ │ ├── nv_ram_rws_64x1088.v │ │ │ ├── nv_ram_rws_64x116.v │ │ │ ├── nv_ram_rws_64x128.v │ │ │ ├── nv_ram_rws_64x18.v │ │ │ ├── nv_ram_rws_64x256.v │ │ │ ├── nv_ram_rws_64x32.v │ │ │ ├── nv_ram_rws_64x512.v │ │ │ ├── nv_ram_rws_64x64.v │ │ │ ├── nv_ram_rwsp_128x11.v │ │ │ ├── nv_ram_rwsp_128x257.v │ │ │ ├── nv_ram_rwsp_128x6.v │ │ │ ├── nv_ram_rwsp_160x16.v │ │ │ ├── nv_ram_rwsp_160x514.v │ │ │ ├── nv_ram_rwsp_160x65.v │ │ │ ├── nv_ram_rwsp_16x14.v │ │ │ ├── nv_ram_rwsp_16x16.v │ │ │ ├── nv_ram_rwsp_16x256.v │ │ │ ├── nv_ram_rwsp_16x65.v │ │ │ ├── nv_ram_rwsp_20x289.v │ │ │ ├── nv_ram_rwsp_245x514.v │ │ │ ├── nv_ram_rwsp_256x11.v │ │ │ ├── nv_ram_rwsp_256x14.v │ │ │ ├── nv_ram_rwsp_256x16.v │ │ │ ├── nv_ram_rwsp_256x257.v │ │ │ ├── nv_ram_rwsp_32x129.v │ │ │ ├── nv_ram_rwsp_32x256.v │ │ │ ├── nv_ram_rwsp_32x32.v │ │ │ ├── nv_ram_rwsp_4x128.v │ │ │ ├── nv_ram_rwsp_4x64.v │ │ │ ├── nv_ram_rwsp_61x514.v │ │ │ ├── nv_ram_rwsp_61x64.v │ │ │ ├── nv_ram_rwsp_61x65.v │ │ │ ├── nv_ram_rwsp_64x129.v │ │ │ ├── nv_ram_rwsp_64x14.v │ │ │ ├── nv_ram_rwsp_64x16.v │ │ │ ├── nv_ram_rwsp_80x14.v │ │ │ ├── nv_ram_rwsp_80x16.v │ │ │ ├── nv_ram_rwsp_80x256.v │ │ │ ├── nv_ram_rwsp_80x514.v │ │ │ ├── nv_ram_rwsp_80x65.v │ │ │ ├── nv_ram_rwsp_8x129.v │ │ │ ├── nv_ram_rwsp_8x257.v │ │ │ ├── nv_ram_rwsp_8x65.v │ │ │ ├── nv_ram_rwst_256x8.v │ │ │ ├── nv_ram_rwsthp_19x32.v │ │ │ ├── nv_ram_rwsthp_19x4.v │ │ │ ├── nv_ram_rwsthp_19x80.v │ │ │ ├── nv_ram_rwsthp_20x16.v │ │ │ ├── nv_ram_rwsthp_20x32.v │ │ │ ├── nv_ram_rwsthp_20x4.v │ │ │ ├── nv_ram_rwsthp_20x8.v │ │ │ ├── nv_ram_rwsthp_60x168.v │ │ │ ├── nv_ram_rwsthp_60x21.v │ │ │ ├── nv_ram_rwsthp_60x42.v │ │ │ ├── nv_ram_rwsthp_60x84.v │ │ │ ├── nv_ram_rwsthp_80x15.v │ │ │ ├── nv_ram_rwsthp_80x17.v │ │ │ ├── nv_ram_rwsthp_80x18.v │ │ │ ├── nv_ram_rwsthp_80x36.v │ │ │ ├── nv_ram_rwsthp_80x72.v │ │ │ └── nv_ram_rwsthp_80x9.v │ ├── model │ │ ├── RAMDP_128X11_GL_M2_E2.v │ │ ├── RAMDP_128X6_GL_M2_E2.v │ │ ├── RAMDP_16X128_GL_M1_E2.v │ │ ├── RAMDP_16X14_GL_M1_E2.v │ │ ├── RAMDP_16X16_GL_M1_E2.v │ │ ├── RAMDP_16X256_GL_M1_E2.v │ │ ├── RAMDP_16X272_GL_M1_E2.v │ │ ├── RAMDP_16X64_GL_M1_E2.v │ │ ├── RAMDP_16X66_GL_M1_E2.v │ │ ├── RAMDP_20X16_GL_M1_E2.v │ │ ├── RAMDP_20X288_GL_M1_E2.v │ │ ├── RAMDP_20X32_GL_M1_E2.v │ │ ├── RAMDP_20X80_GL_M1_E2.v │ │ ├── RAMDP_20X8_GL_M1_E2.v │ │ ├── RAMDP_256X4_GL_M2_E2.v │ │ ├── RAMDP_256X7_GL_M2_E2.v │ │ ├── RAMDP_256X8_GL_M2_E2.v │ │ ├── RAMDP_32X16_GL_M1_E2.v │ │ ├── RAMDP_32X32_GL_M1_E2.v │ │ ├── RAMDP_32X64_GL_M1_E2.v │ │ ├── RAMDP_60X22_GL_M1_E2.v │ │ ├── RAMDP_64X10_GL_M2_E2.v │ │ ├── RAMDP_64X14_GL_M2_E2.v │ │ ├── RAMDP_64X16_GL_M2_E2.v │ │ ├── RAMDP_64X18_GL_M2_E2.v │ │ ├── RAMDP_64X32_GL_M1_E2.v │ │ ├── RAMDP_80X14_GL_M2_E2.v │ │ ├── RAMDP_80X15_GL_M2_E2.v │ │ ├── RAMDP_80X18_GL_M1_E2.v │ │ ├── RAMDP_80X9_GL_M2_E2.v │ │ ├── RAMDP_8X130_GL_M1_E2.v │ │ ├── RAMDP_8X258_GL_M1_E2.v │ │ ├── RAMDP_8X66_GL_M1_E2.v │ │ ├── RAMPDP_128X128_GL_M1_D2.v │ │ ├── RAMPDP_128X18_GL_M2_D2.v │ │ ├── RAMPDP_128X224_GL_M1_D2.v │ │ ├── RAMPDP_128X256_GL_M1_D2.v │ │ ├── RAMPDP_128X258_GL_M1_D2.v │ │ ├── RAMPDP_128X288_GL_M1_D2.v │ │ ├── RAMPDP_128X32_GL_M2_D2.v │ │ ├── RAMPDP_128X60_GL_M1_D2.v │ │ ├── RAMPDP_128X64_GL_M1_D2.v │ │ ├── RAMPDP_160X144_GL_M2_D2.v │ │ ├── RAMPDP_160X16_GL_M2_D2.v │ │ ├── RAMPDP_160X65_GL_M2_D2.v │ │ ├── RAMPDP_160X82_GL_M2_D2.v │ │ ├── RAMPDP_160X93_GL_M2_D2.v │ │ ├── RAMPDP_248X144_GL_M2_D2.v │ │ ├── RAMPDP_248X82_GL_M2_D2.v │ │ ├── RAMPDP_256X112_GL_M2_D2.v │ │ ├── RAMPDP_256X113_GL_M2_D2.v │ │ ├── RAMPDP_256X11_GL_M4_D2.v │ │ ├── RAMPDP_256X128_GL_M2_D2.v │ │ ├── RAMPDP_256X144_GL_M2_D2.v │ │ ├── RAMPDP_256X14_GL_M4_D2.v │ │ ├── RAMPDP_256X16_GL_M2_D2.v │ │ ├── RAMPDP_256X64_GL_M2_D2.v │ │ ├── RAMPDP_256X80_GL_M2_D2.v │ │ ├── RAMPDP_32X128_GL_M1_D2.v │ │ ├── RAMPDP_32X130_GL_M1_D2.v │ │ ├── RAMPDP_32X192_GL_M1_D2.v │ │ ├── RAMPDP_32X224_GL_M1_D2.v │ │ ├── RAMPDP_32X256_GL_M1_D2.v │ │ ├── RAMPDP_32X272_GL_M1_D2.v │ │ ├── RAMPDP_32X288_GL_M1_D2.v │ │ ├── RAMPDP_512X40_GL_M4_D2.v │ │ ├── RAMPDP_512X56_GL_M4_D2.v │ │ ├── RAMPDP_512X64_GL_M4_D2.v │ │ ├── RAMPDP_512X72_GL_M4_D2.v │ │ ├── RAMPDP_512X8_GL_M4_D2.v │ │ ├── RAMPDP_60X168_GL_M1_D2.v │ │ ├── RAMPDP_60X42_GL_M1_D2.v │ │ ├── RAMPDP_60X84_GL_M1_D2.v │ │ ├── RAMPDP_64X116_GL_M1_D2.v │ │ ├── RAMPDP_64X128_GL_M1_D2.v │ │ ├── RAMPDP_64X130_GL_M1_D2.v │ │ ├── RAMPDP_64X160_GL_M1_D2.v │ │ ├── RAMPDP_64X224_GL_M1_D2.v │ │ ├── RAMPDP_64X226_GL_M1_D2.v │ │ ├── RAMPDP_64X256_GL_M1_D2.v │ │ ├── RAMPDP_64X288_GL_M1_D2.v │ │ ├── RAMPDP_64X64_GL_M1_D2.v │ │ ├── RAMPDP_64X66_GL_M1_D2.v │ │ ├── RAMPDP_80X16_GL_M2_D2.v │ │ ├── RAMPDP_80X17_GL_M2_D2.v │ │ ├── RAMPDP_80X226_GL_M1_D2.v │ │ ├── RAMPDP_80X238_GL_M1_D2.v │ │ ├── RAMPDP_80X256_GL_M1_D2.v │ │ ├── RAMPDP_80X288_GL_M1_D2.v │ │ ├── RAMPDP_80X36_GL_M1_D2.v │ │ ├── RAMPDP_80X66_GL_M1_D2.v │ │ └── RAMPDP_80X72_GL_M1_D2.v │ └── synth │ │ ├── nv_ram_rws_128x128.v │ │ ├── nv_ram_rws_128x128_logic.v │ │ ├── nv_ram_rws_128x18.v │ │ ├── nv_ram_rws_128x18_logic.v │ │ ├── nv_ram_rws_128x256.v │ │ ├── nv_ram_rws_128x256_logic.v │ │ ├── nv_ram_rws_128x32.v │ │ ├── nv_ram_rws_128x32_logic.v │ │ ├── nv_ram_rws_128x512.v │ │ ├── nv_ram_rws_128x512_logic.v │ │ ├── nv_ram_rws_128x60.v │ │ ├── nv_ram_rws_128x60_logic.v │ │ ├── nv_ram_rws_128x64.v │ │ ├── nv_ram_rws_128x64_logic.v │ │ ├── nv_ram_rws_16x128.v │ │ ├── nv_ram_rws_16x128_logic.v │ │ ├── nv_ram_rws_16x256.v │ │ ├── nv_ram_rws_16x256_logic.v │ │ ├── nv_ram_rws_16x272.v │ │ ├── nv_ram_rws_16x272_logic.v │ │ ├── nv_ram_rws_16x64.v │ │ ├── nv_ram_rws_16x64_logic.v │ │ ├── nv_ram_rws_256x128.v │ │ ├── nv_ram_rws_256x128_logic.v │ │ ├── nv_ram_rws_256x256.v │ │ ├── nv_ram_rws_256x256_logic.v │ │ ├── nv_ram_rws_256x3.v │ │ ├── nv_ram_rws_256x3_logic.v │ │ ├── nv_ram_rws_256x512.v │ │ ├── nv_ram_rws_256x512_logic.v │ │ ├── nv_ram_rws_256x64.v │ │ ├── nv_ram_rws_256x64_logic.v │ │ ├── nv_ram_rws_256x7.v │ │ ├── nv_ram_rws_256x7_logic.v │ │ ├── nv_ram_rws_32x128.v │ │ ├── nv_ram_rws_32x128_logic.v │ │ ├── nv_ram_rws_32x16.v │ │ ├── nv_ram_rws_32x16_logic.v │ │ ├── nv_ram_rws_32x256.v │ │ ├── nv_ram_rws_32x256_logic.v │ │ ├── nv_ram_rws_32x272.v │ │ ├── nv_ram_rws_32x272_logic.v │ │ ├── nv_ram_rws_32x32.v │ │ ├── nv_ram_rws_32x32_logic.v │ │ ├── nv_ram_rws_32x512.v │ │ ├── nv_ram_rws_32x512_logic.v │ │ ├── nv_ram_rws_32x544.v │ │ ├── nv_ram_rws_32x544_logic.v │ │ ├── nv_ram_rws_32x64.v │ │ ├── nv_ram_rws_32x64_logic.v │ │ ├── nv_ram_rws_32x768.v │ │ ├── nv_ram_rws_32x768_logic.v │ │ ├── nv_ram_rws_512x128.v │ │ ├── nv_ram_rws_512x128_logic.v │ │ ├── nv_ram_rws_512x256.v │ │ ├── nv_ram_rws_512x256_logic.v │ │ ├── nv_ram_rws_512x512.v │ │ ├── nv_ram_rws_512x512_logic.v │ │ ├── nv_ram_rws_512x64.v │ │ ├── nv_ram_rws_512x64_logic.v │ │ ├── nv_ram_rws_64x10.v │ │ ├── nv_ram_rws_64x1024.v │ │ ├── nv_ram_rws_64x1024_logic.v │ │ ├── nv_ram_rws_64x1088.v │ │ ├── nv_ram_rws_64x1088_logic.v │ │ ├── nv_ram_rws_64x10_logic.v │ │ ├── nv_ram_rws_64x116.v │ │ ├── nv_ram_rws_64x116_logic.v │ │ ├── nv_ram_rws_64x128.v │ │ ├── nv_ram_rws_64x128_logic.v │ │ ├── nv_ram_rws_64x18.v │ │ ├── nv_ram_rws_64x18_logic.v │ │ ├── nv_ram_rws_64x256.v │ │ ├── nv_ram_rws_64x256_logic.v │ │ ├── nv_ram_rws_64x32.v │ │ ├── nv_ram_rws_64x32_logic.v │ │ ├── nv_ram_rws_64x512.v │ │ ├── nv_ram_rws_64x512_logic.v │ │ ├── nv_ram_rws_64x64.v │ │ ├── nv_ram_rws_64x64_logic.v │ │ ├── nv_ram_rwsp_128x11.v │ │ ├── nv_ram_rwsp_128x11_logic.v │ │ ├── nv_ram_rwsp_128x257.v │ │ ├── nv_ram_rwsp_128x257_logic.v │ │ ├── nv_ram_rwsp_128x6.v │ │ ├── nv_ram_rwsp_128x6_logic.v │ │ ├── nv_ram_rwsp_160x16.v │ │ ├── nv_ram_rwsp_160x16_logic.v │ │ ├── nv_ram_rwsp_160x514.v │ │ ├── nv_ram_rwsp_160x514_logic.v │ │ ├── nv_ram_rwsp_160x65.v │ │ ├── nv_ram_rwsp_160x65_logic.v │ │ ├── nv_ram_rwsp_16x14.v │ │ ├── nv_ram_rwsp_16x14_logic.v │ │ ├── nv_ram_rwsp_16x16.v │ │ ├── nv_ram_rwsp_16x16_logic.v │ │ ├── nv_ram_rwsp_16x256.v │ │ ├── nv_ram_rwsp_16x256_logic.v │ │ ├── nv_ram_rwsp_16x65.v │ │ ├── nv_ram_rwsp_16x65_logic.v │ │ ├── nv_ram_rwsp_20x289.v │ │ ├── nv_ram_rwsp_20x289_logic.v │ │ ├── nv_ram_rwsp_245x514.v │ │ ├── nv_ram_rwsp_245x514_logic.v │ │ ├── nv_ram_rwsp_256x11.v │ │ ├── nv_ram_rwsp_256x11_logic.v │ │ ├── nv_ram_rwsp_256x14.v │ │ ├── nv_ram_rwsp_256x14_logic.v │ │ ├── nv_ram_rwsp_256x16.v │ │ ├── nv_ram_rwsp_256x16_logic.v │ │ ├── nv_ram_rwsp_256x257.v │ │ ├── nv_ram_rwsp_256x257_logic.v │ │ ├── nv_ram_rwsp_32x129.v │ │ ├── nv_ram_rwsp_32x129_logic.v │ │ ├── nv_ram_rwsp_32x256.v │ │ ├── nv_ram_rwsp_32x256_logic.v │ │ ├── nv_ram_rwsp_32x32.v │ │ ├── nv_ram_rwsp_32x32_logic.v │ │ ├── nv_ram_rwsp_4x128.v │ │ ├── nv_ram_rwsp_4x128_logic.v │ │ ├── nv_ram_rwsp_4x64.v │ │ ├── nv_ram_rwsp_4x64_logic.v │ │ ├── nv_ram_rwsp_61x514.v │ │ ├── nv_ram_rwsp_61x514_logic.v │ │ ├── nv_ram_rwsp_61x64.v │ │ ├── nv_ram_rwsp_61x64_logic.v │ │ ├── nv_ram_rwsp_61x65.v │ │ ├── nv_ram_rwsp_61x65_logic.v │ │ ├── nv_ram_rwsp_64x129.v │ │ ├── nv_ram_rwsp_64x129_logic.v │ │ ├── nv_ram_rwsp_64x14.v │ │ ├── nv_ram_rwsp_64x14_logic.v │ │ ├── nv_ram_rwsp_64x16.v │ │ ├── nv_ram_rwsp_64x16_logic.v │ │ ├── nv_ram_rwsp_80x14.v │ │ ├── nv_ram_rwsp_80x14_logic.v │ │ ├── nv_ram_rwsp_80x16.v │ │ ├── nv_ram_rwsp_80x16_logic.v │ │ ├── nv_ram_rwsp_80x256.v │ │ ├── nv_ram_rwsp_80x256_logic.v │ │ ├── nv_ram_rwsp_80x514.v │ │ ├── nv_ram_rwsp_80x514_logic.v │ │ ├── nv_ram_rwsp_80x65.v │ │ ├── nv_ram_rwsp_80x65_logic.v │ │ ├── nv_ram_rwsp_8x129.v │ │ ├── nv_ram_rwsp_8x129_logic.v │ │ ├── nv_ram_rwsp_8x257.v │ │ ├── nv_ram_rwsp_8x257_logic.v │ │ ├── nv_ram_rwsp_8x65.v │ │ ├── nv_ram_rwsp_8x65_logic.v │ │ ├── nv_ram_rwst_256x8.v │ │ ├── nv_ram_rwst_256x8_logic.v │ │ ├── nv_ram_rwsthp_19x32.v │ │ ├── nv_ram_rwsthp_19x4.v │ │ ├── nv_ram_rwsthp_19x80.v │ │ ├── nv_ram_rwsthp_19x80_logic.v │ │ ├── nv_ram_rwsthp_20x16.v │ │ ├── nv_ram_rwsthp_20x16_logic.v │ │ ├── nv_ram_rwsthp_20x32.v │ │ ├── nv_ram_rwsthp_20x32_logic.v │ │ ├── nv_ram_rwsthp_20x4.v │ │ ├── nv_ram_rwsthp_20x4_logic.v │ │ ├── nv_ram_rwsthp_20x8.v │ │ ├── nv_ram_rwsthp_20x8_logic.v │ │ ├── nv_ram_rwsthp_60x168.v │ │ ├── nv_ram_rwsthp_60x168_logic.v │ │ ├── nv_ram_rwsthp_60x21.v │ │ ├── nv_ram_rwsthp_60x21_logic.v │ │ ├── nv_ram_rwsthp_60x42.v │ │ ├── nv_ram_rwsthp_60x42_logic.v │ │ ├── nv_ram_rwsthp_60x84.v │ │ ├── nv_ram_rwsthp_60x84_logic.v │ │ ├── nv_ram_rwsthp_80x15.v │ │ ├── nv_ram_rwsthp_80x15_logic.v │ │ ├── nv_ram_rwsthp_80x17.v │ │ ├── nv_ram_rwsthp_80x17_logic.v │ │ ├── nv_ram_rwsthp_80x18.v │ │ ├── nv_ram_rwsthp_80x18_logic.v │ │ ├── nv_ram_rwsthp_80x36.v │ │ ├── nv_ram_rwsthp_80x36_logic.v │ │ ├── nv_ram_rwsthp_80x72.v │ │ ├── nv_ram_rwsthp_80x72_logic.v │ │ ├── nv_ram_rwsthp_80x9.v │ │ └── nv_ram_rwsthp_80x9_logic.v └── vlibs │ ├── AN2D4PO4.v │ ├── CKLNQD12.v │ ├── CKLNQD12PO4.v │ ├── HLS_cdp_icvt.v │ ├── HLS_cdp_ocvt.v │ ├── HLS_fp16_to_fp17.v │ ├── HLS_fp16_to_fp32.v │ ├── HLS_fp17_add.v │ ├── HLS_fp17_mul.v │ ├── HLS_fp17_sub.v │ ├── HLS_fp17_to_fp16.v │ ├── HLS_fp17_to_fp32.v │ ├── HLS_fp32_add.v │ ├── HLS_fp32_mul.v │ ├── HLS_fp32_sub.v │ ├── HLS_fp32_to_fp16.v │ ├── HLS_fp32_to_fp17.v │ ├── HLS_uint16_to_fp17.v │ ├── LNQD1PO4.v │ ├── MUX2D4.v │ ├── MUX2HDD2.v │ ├── NV_BLKBOX_BUFFER.v │ ├── NV_BLKBOX_SINK.v │ ├── NV_BLKBOX_SRC0.v │ ├── NV_BLKBOX_SRC0_X.v │ ├── NV_CLK_gate_power.v │ ├── NV_DW02_tree.v │ ├── NV_DW_lsd.v │ ├── NV_DW_minmax.v │ ├── NV_NVDLA_CDP_HLS_icvt.v │ ├── NV_NVDLA_CDP_HLS_ocvt.v │ ├── NV_NVDLA_HLS_saturate.v │ ├── NV_NVDLA_HLS_shiftleftsu.v │ ├── NV_NVDLA_HLS_shiftrightsatsu.v │ ├── NV_NVDLA_HLS_shiftrightss.v │ ├── NV_NVDLA_HLS_shiftrightsu.v │ ├── NV_NVDLA_HLS_shiftrightusz.v │ ├── OR2D1.v │ ├── PGAOPV_AN2D2PO4.v │ ├── PGAOPV_DFCNQD2PO4.v │ ├── PGAOPV_INVD2PO4.v │ ├── RANDFUNC.vlib │ ├── SDFCNQD1.v │ ├── SDFQD1.v │ ├── SDFSNQD1.v │ ├── ScanShareSel_JTAG_reg_ext_cg.v │ ├── assertion_header.vh │ ├── assertion_task.vh │ ├── no_lib_cells.vlib │ ├── nv_assert_always.vlib │ ├── nv_assert_at_time_interval.vlib │ ├── nv_assert_fifo.vlib │ ├── nv_assert_hold_throughout_event_interval.vlib │ ├── nv_assert_never.vlib │ ├── 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