├── .github └── workflows │ └── action.yml ├── .gitignore ├── LICENSE ├── README.md ├── SConscript ├── demo ├── SConscript └── demo.c ├── docs ├── NRF24L01_en.pdf ├── api.md ├── features.md └── user_guide.md └── src ├── SConscript ├── nrf24l01.c ├── nrf24l01.h ├── nrf24l01_port.c └── nrf24l01_port.h /.github/workflows/action.yml: -------------------------------------------------------------------------------- 1 | name: RT-Thread_Packages_Test 2 | 3 | on: 4 | [push, pull_request] 5 | 6 | jobs: 7 | pkgs-test: 8 | uses: RT-Thread/pkgs-test/.github/workflows/pkgs-action.yml@main 9 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | .vscode/ -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # nRF24L01 2 | 3 | ## 1、介绍 4 | 5 | 这是一个 RT-Thread 的软件包，该软件包提供了 nRF24L01 模块的驱动。 6 | 7 | nRF24L01 是由 NORDIC 生产的工作在 2.4GHz~2.5GHz 的 ISM 频段的单片无线收发器芯片。 8 | 9 | > 更多关于 nRF24L01 的信息请参阅 [_features.md_](/docs/features.md) 或 _数据手册_ 10 | 11 | ### 1.1 目录结构 12 | 13 | | 名称 | 说明 | 14 | | ---- | ---- | 15 | | docs | 文档 | 16 | | demo | 有关使用该驱动的样例代码 | 17 | | src | 源代码目录 | 18 | 19 | ### 1.2 许可证 20 | 21 | nRF24L01 package 遵循 Apache license v2.0 许可，详见 `LICENSE` 文件。 22 | 23 | ### 1.3 依赖 24 | 25 | - RT-Thread PIN 设备 26 | - RT-Thread SPI 设备 27 | - RT-Thread IPC (SEM) 28 | 29 | ## 2、获取软件包 30 | 31 | 使用 nRF24L01 package 需要在 RT-Thread 的包管理器中选择它，具体路径如下： 32 | 33 | ``` 34 | RT-Thread online packages 35 | peripheral libraries and drivers ---> 36 | [*] nRF24L01: Single-chip 2.4GHz wireless transceiver. 37 | ``` 38 | 39 | 选中后让 RT-Thread 的包管理器自动更新，或者使用 `pkgs --update` 命令更新包到 BSP 中。 40 | 41 | ## 3、使用 nRF24L01 42 | 43 | _**用户指南 --> [user_guide.md](./docs/user_guide.md)**_ 44 | 45 | _**具体用例, 参见 demo --> [demo.c](./demo/demo.c)**_ 46 | 47 | ## 4、注意事项 48 | 49 | 无 50 | 51 | ## 5、联系方式 52 | 53 | - 维护：sogwyms@gmail.com 54 | - 主页：https://github.com/sogwms/nrf24l01 55 | -------------------------------------------------------------------------------- /SConscript: -------------------------------------------------------------------------------- 1 | # RT-Thread building script for bridge 2 | 3 | import os 4 | from building import * 5 | 6 | cwd = GetCurrentDir() 7 | objs = [] 8 | list = os.listdir(cwd) 9 | 10 | if GetDepend('PKG_USING_NRF24L01'): 11 | for d in list: 12 | path = os.path.join(cwd, d) 13 | if os.path.isfile(os.path.join(path, 'SConscript')): 14 | objs = objs + SConscript(os.path.join(d, 'SConscript')) 15 | 16 | Return('objs') -------------------------------------------------------------------------------- /demo/SConscript: -------------------------------------------------------------------------------- 1 | from building import * 2 | Import('rtconfig') 3 | 4 | cwd = GetCurrentDir() 5 | src = Glob('*.c') 6 | path = [cwd] 7 | 8 | group = DefineGroup('nRF24L01', src, depend = ['PKG_USING_NRF24L01_DEMO'], CPPPATH = path) 9 | 10 | Return('group') -------------------------------------------------------------------------------- /demo/demo.c: -------------------------------------------------------------------------------- 1 | #include 2 | #include 3 | 4 | #if (PKG_NRF24L01_DEMO_CE_PIN < 0) 5 | #error Please specify a valid pin 6 | #endif 7 | 8 | #ifdef PKG_NRF24L01_DEMO_ROLE_PTX 9 | #define NRF24_DEMO_ROLE ROLE_PTX 10 | #define NRF24_DEMO_SEND_INTERVAL PKG_NRF24L01_DEMO_INTERVAL_SEND 11 | #else 12 | #define NRF24_DEMO_ROLE ROLE_PRX 13 | #endif 14 | 15 | #define NRF24_DEMO_SPI_DEV_NAME PKG_NRF24L01_DEMO_SPI_DEV_NAME 16 | #define NRF24_DEMO_CE_PIN PKG_NRF24L01_DEMO_CE_PIN 17 | #define NRF24_DEMO_IRQ_PIN PKG_NRF24L01_DEMO_IRQ_PIN 18 | 19 | const static char *ROLE_TABLE[] = {"PTX", "PRX"}; 20 | 21 | static void rx_ind(nrf24_t nrf24, uint8_t *data, uint8_t len, int pipe) 22 | { 23 | /*! Don't need to care the pipe if the role is ROLE_PTX */ 24 | rt_kprintf("(p%d): ", pipe); 25 | rt_kprintf((char *)data); 26 | } 27 | 28 | static void tx_done(nrf24_t nrf24, int pipe) 29 | { 30 | static int cnt = 0; 31 | static char tbuf[32]; 32 | 33 | cnt++; 34 | 35 | /*! Here just want to tell the user when the role is ROLE_PTX 36 | the pipe have no special meaning except indicating (send) FAILED or OK 37 | However, it will matter when the role is ROLE_PRX*/ 38 | if (nrf24->cfg.role == ROLE_PTX) 39 | { 40 | if (pipe == NRF24_PIPE_NONE) 41 | rt_kprintf("tx_done failed"); 42 | else 43 | rt_kprintf("tx_done ok"); 44 | } 45 | else 46 | { 47 | rt_kprintf("tx_done ok"); 48 | } 49 | 50 | rt_kprintf(" (pipe%d)\n", pipe); 51 | 52 | rt_sprintf(tbuf, "My role is %s [%dth]\n", ROLE_TABLE[nrf24->cfg.role], cnt); 53 | nrf24_send_data(nrf24, (uint8_t *)tbuf, rt_strlen(tbuf), pipe); 54 | #ifdef PKG_NRF24L01_DEMO_ROLE_PTX 55 | rt_thread_mdelay(NRF24_DEMO_SEND_INTERVAL); 56 | #endif 57 | } 58 | 59 | const static struct nrf24_callback _cb = { 60 | .rx_ind = rx_ind, 61 | .tx_done = tx_done, 62 | }; 63 | 64 | static void thread_entry(void *param) 65 | { 66 | nrf24_t nrf24; 67 | 68 | rt_kprintf("[nrf24/demo] Version:%s\n", PKG_NRF24L01_VERSION); 69 | 70 | nrf24 = nrf24_default_create(NRF24_DEMO_SPI_DEV_NAME, NRF24_DEMO_CE_PIN, NRF24_DEMO_IRQ_PIN, &_cb, NRF24_DEMO_ROLE); 71 | 72 | if (nrf24 == RT_NULL) 73 | { 74 | rt_kprintf("\n[nrf24/demo] Failed to create nrf24. stop!\n"); 75 | for(;;) rt_thread_mdelay(10000); 76 | } 77 | else 78 | { 79 | rt_kprintf("[nrf24/demo] running."); 80 | } 81 | 82 | nrf24_send_data(nrf24, (uint8_t *)"Hi\n", 3, NRF24_DEFAULT_PIPE); 83 | 84 | while (1) 85 | { 86 | nrf24_run(nrf24); 87 | 88 | if(!nrf24->flags.using_irq) 89 | rt_thread_mdelay(10); 90 | } 91 | 92 | } 93 | 94 | static int nrf24l01_sample_init(void) 95 | { 96 | rt_thread_t thread; 97 | 98 | thread = rt_thread_create("nrfDemo", thread_entry, RT_NULL, 1024, RT_THREAD_PRIORITY_MAX/2, 20); 99 | rt_thread_startup(thread); 100 | 101 | return RT_EOK; 102 | } 103 | 104 | INIT_APP_EXPORT(nrf24l01_sample_init); 105 | -------------------------------------------------------------------------------- /docs/NRF24L01_en.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sogwms/nrf24l01/aca3686048eaca66aeb47aca1a1f23139bc973b4/docs/NRF24L01_en.pdf -------------------------------------------------------------------------------- /docs/api.md: -------------------------------------------------------------------------------- 1 | # API 手册 2 | 3 | ## 重要结构体说明 4 | 5 | *** 6 | 7 | ```c 8 | struct nrf24_callback 9 | { 10 | void (*rx_ind)(nrf24_t nrf24, uint8_t *data, uint8_t len, int pipe); 11 | void (*tx_done)(nrf24_t nrf24, int pipe); 12 | }; 13 | ``` 14 | 15 | 作用: 配置回调函数 16 | 17 | 详细: 18 | 19 | - rx_ind: 接收回调函数，当 run 检测并接收到数据时会调用。参数 len 指示 data 的长度，pipe 参数指示从哪个通道接收到的数据（仅针对 ROLE_PRX 有意义） 20 | 21 | - tx_done: 发送回调函数，当 run 检测到发送结果时调用。对于 ROLE_PTX, pipe 参数指示发送失败(NRF24_PIPE_NONE)或成功(非NRF24_PIPE_NONE) 22 | 23 | *** 24 | 25 | ```c 26 | struct nrf24_cfg 27 | { 28 | nrf24_role_et role; 29 | nrf24_power_et power; 30 | nrf24_crc_et crc; 31 | nrf24_adr_et adr; 32 | uint8_t channel :7; //range: 0 ~ 127 (frequency:) 33 | 34 | int _irq_pin; 35 | 36 | uint8_t txaddr[5]; 37 | 38 | struct { 39 | uint8_t bl_enabled; 40 | uint8_t addr[5]; 41 | } rxpipe0; 42 | struct { 43 | uint8_t bl_enabled; 44 | uint8_t addr[5]; 45 | } rxpipe1; 46 | 47 | struct { 48 | uint8_t bl_enabled; 49 | uint8_t addr; 50 | } rxpipe2; 51 | struct { 52 | uint8_t bl_enabled; 53 | uint8_t addr; 54 | } rxpipe3; 55 | struct { 56 | uint8_t bl_enabled; 57 | uint8_t addr; 58 | } rxpipe4; 59 | struct { 60 | uint8_t bl_enabled; 61 | uint8_t addr; 62 | } rxpipe5; 63 | 64 | }; 65 | ``` 66 | 67 | 作用: 配置 nrf24l01 68 | 69 | 详细: 70 | 71 | - role: 角色选择 (选项参见相应 enum) 72 | 73 | - power: 功率 (选项参见相应 enum) 74 | 75 | - crc：CRC (选项参见相应 enum) 76 | 77 | - adr：空中速率 (选项参见相应 enum) 78 | 79 | - channel: 频率 (范围：0～127) 80 | 81 | - txaddr: 发送地址 82 | 83 | - rxpipex: bl_enabled 视为布尔值，决定是否启用该 pipe。addr 为pipe接收地址 84 | 85 | ## 重要函数说明 86 | 87 | *** 88 | 89 | ```c 90 | int nrf24_init(nrf24_t nrf24, char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, const nrf24_cfg_t cfg); 91 | ``` 92 | 93 | 功能：初始化 nrf24 对象 94 | 95 | 参数： 96 | 97 | - spi_dev_name: spi 设备名 98 | - ce_pin: nrf24l01 的 ce 引脚 99 | - irq_pin: nrf24l01 的 中断 引脚。 若配置为 NRF24_PIN_NONE 表示不使用中断 100 | - cb：回调函数 101 | - cfg: 配置 102 | 103 | *** 104 | 105 | ```c 106 | nrf24_t nrf24_create(char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, const nrf24_cfg_t cfg); 107 | ``` 108 | 109 | 功能：创建 nrf24 对象并初始化 110 | 111 | 参数：同上 112 | 113 | *** 114 | 115 | ```c 116 | int nrf24_fill_default_config_on(nrf24_cfg_t cfg); 117 | ``` 118 | 119 | 功能：将 cfg 设置为默认值（配置） 120 | 121 | *** 122 | 123 | ```c 124 | int nrf24_default_init(nrf24_t nrf24, char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, nrf24_role_et role); 125 | ``` 126 | 127 | 功能：将配置尽量采取默认值，简化版初始化 128 | 129 | 参数：基本同上 130 | 131 | *** 132 | 133 | ```c 134 | nrf24_t nrf24_default_create(char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, nrf24_role_et role); 135 | ``` 136 | 137 | nrf24_default_init 的 create 版本 138 | 139 | *** 140 | 141 | ```c 142 | int nrf24_send_data(nrf24_t nrf24, uint8_t *data, uint8_t len, uint8_t pipe); 143 | ``` 144 | 145 | 功能：发送数据 146 | 147 | 参数： 148 | 149 | - pipe 为 枚举类型 (NRF24_PIPE_X) 150 | 151 | 注意：该函数返回时并不意味着发送完成，发送的结果（失败或成功）是通过回调函数通知的。 152 | 153 | 154 | *** 155 | 156 | ```c 157 | int nrf24_run(nrf24_t nrf24); 158 | ``` 159 | 160 | 功能：运行 nrf24 对象 161 | 162 | 注意： 163 | 164 | - 对于使用中断的 nrf24，run会阻塞。非中断则不会 165 | 166 | ```c 167 | void nrf24_enter_power_up_mode(nrf24_t nrf24); 168 | ``` 169 | 170 | 功能：进入上电模式，以便正常工作 171 | 172 | *** 173 | 174 | ```c 175 | void nrf24_enter_power_down_mode(nrf24_t nrf24); 176 | ``` 177 | 178 | 功能：进入掉电模式，进入最低功耗模式（无法通信） 179 | 180 | _*更详细的信息，参见源码*_ 181 | -------------------------------------------------------------------------------- /docs/features.md: -------------------------------------------------------------------------------- 1 | # nRF24L01 参数 2 | 3 | ## 应用领域 4 | 5 | - 无线 PC 外围设备 6 | - 无线鼠标 键盘 游戏机操纵杆 7 | - 高级媒体中心遥控器 8 | - 超低功耗传感器网络 9 | - 无线数据通讯 10 | - 有源电子标签 11 | - 安防系统 12 | - 遥控装置 13 | - 遥感勘测 14 | - 智能运动设备 15 | - 工业传感器 16 | - 玩具 17 | 18 | ## 主要特点 19 | 20 | - 小体积，QFN20 4x4mm封装 21 | - 宽电压工作范围，1.9V~3.6V，输入引脚可承受5V电压输入 22 | - 工作温度范围，-40℃～+80℃ 23 | - 工作频率范围，2.400GHz～2.525GHz 24 | - 发射功率可选择为0dBm、-6dBm、-12dBm和-18dBm 25 | - 数据传输速率支持1Mbps、2Mbps 26 | - 低功耗设计，接收时工作电流12.3mA，0dBm功率发射时11.3mA，掉电模式时仅为900nA 27 | - 126个通讯通道，6个数据通道，满足多点通讯和调频需要 28 | - 增强型“ShockBurst”工作模式，硬件的CRC校验和点对多点的地址控制 29 | - 数据包每次可传输1～32Byte的数据 30 | - 4线SPI通讯端口，通讯速率最高可达8Mbps，适合与各种MCU连接，编程简单 31 | - 可通过软件设置工作频率、通讯地址、传输速率和数据包长度 32 | - MCU可通过IRQ引脚块判断是否完成数据接收和数据发送 33 | 34 | ## 兼容性 35 | 36 | nRF24L01 可以兼容nRF2401A、nRF24L01+、nRF24LE1、nRF24LU1等无线模块。 37 | 38 | ### nrf24l01+ 39 | 40 | nRF24L01+（或称nRF24L01P）是nRF24L01的低功耗优化版，同时增加了250Kbps通讯速率的支持。nRF24L01与nRF24L01+之间可互用代码（除极少部分需要修改外）和互相通讯 41 | 42 | ### nRF2401A 43 | 44 | nRF2401A与nRF24L01和nRF24L01+之间可完成相互通讯，前提是它们之间必须工作在相同的工作模式下。比如工作频率、传输速率、地址、数据包长度和CRC校验方式。 45 | 46 | ### nRF24LE1 47 | 48 | nRF24LE1、nRF24LU1也可以同nRF24L01之间完成通讯。通讯建立条件同nRF2401A 49 | -------------------------------------------------------------------------------- /docs/user_guide.md: -------------------------------------------------------------------------------- 1 | # 使用前必读 2 | 3 | ## I. 必要了解（关于 nRF24L01） 4 | 5 | ### 1. nRF24L01 特点 6 | 7 | - nRF24L01 是一个无线通信模块，其通信方式属于**半双工** 8 | 9 | - nRF24L01 通信以包为单位，一个包最多携带 32 字节的数据 10 | 11 | - nRF24L01 中有增强性突发模式，该模式可实现自动应答、重传等机制而无需 MCU 的干预. 在该模式下有两个角色：Primary Transmitter（PTX）和 Primary Receiver（PRX）. _（本驱动向上层提供的API即基于此模式）_ 12 | 13 | - 要使 nRF24L01 模块间通信必须匹配关键设置：速率、地址、频率(频道)、CRC 等 14 | 15 | ### 2. PTX、PRX 通信过程**简要说明** 16 | 17 | 1. PTX 方发送数据 18 | 2. PRX 方接收到数据 19 | 3. PRX 方回应一个 ACK，该 ACK 可以携带数据（发送给 PTX 方的） 20 | 4. PTX 方接收到 ACK (可能包含 PRX 发送来的数据) 21 | 22 | 从上述通信过程可以看出：_PTX 属于主动方，PRX 属于被动方。如果 PTX 方不发送数据则也无法接收数据，同时 PRX 方即不能发送也无法接收到数据。_ 23 | 24 | ### 3. 当前驱动特点 25 | 26 | - 默认项（不可配置） 27 | - 5-byte 地址宽度 28 | 29 | - 支持多实例 30 | - 支持中断方式 31 | - 支持一对多通信 32 | 33 | ## II. 使用流程 34 | 35 | 用户首先进行配置和初始化，以获得一个完整的 nrf24 对象， 然后在线程中使用函数 "int nrf24_run(nrf24_t nrf24)" 运行该对象即可。对象会在运行期间调用用户的回调函数 36 | 37 | ### 1 配置和初始化 38 | 39 | 为了便利使用，提供了两类初始化， 一类是默认的和非默认的，另一类是动态的和静态的。 默认和非默认的区别在于用户需要进行的配置工作的多少。 动态和静态是指 nrf24 对象的创建方式。 40 | 41 | 此处以最简便的方式(动态，默认)为例： 42 | 43 | ```c 44 | 45 | static void rx_ind(nrf24_t nrf24, uint8_t *data, uint8_t len, int pipe) 46 | { 47 | // TODO 48 | } 49 | 50 | static void tx_done(nrf24_t nrf24, int pipe) 51 | { 52 | // TODO 53 | } 54 | 55 | const static struct nrf24_callback _cb = { 56 | .rx_ind = rx_ind, 57 | .tx_done = tx_done, 58 | }; 59 | 60 | /* 不使用 IRQ */ 61 | nrf24_t nrf24 = nrf24_default_create("spi10", 36, NRF24_PIN_NONE, _cb, ROLE_PTX); 62 | 63 | /* 使用 IRQ */ 64 | nrf24_t nrf24 = nrf24_default_create("spi10", 36, 37, _cb, ROLE_PTX); 65 | 66 | ``` 67 | 68 | - 配置项的详细说明及更灵活的配置和初始化参见 [api.md](./api.md) 69 | 70 | 显然最简方式关于 nrf24 射频相关的仅需配置一项 ROLE 即可。同样是否使用中断模式配置也很简单仅需配置中断引脚为有效或无效(NRF24_PIN_NONE)即可 71 | 72 | ps：对于两端的通信，使用以上方式，仅两端配置成不同角色（一端 ROLE_PTX, 一端 ROLE_PRX）即可 73 | 74 | ### 2 运行对象 75 | 76 | 直接调用即可，需要注意的是若配置为中断模式（即中断引脚有效）。run 会阻塞线程。 轮询时(无效中断引脚)则不会。 77 | 78 | ```c 79 | ... 80 | nrf24_run(nrf24); 81 | ... 82 | ``` 83 | 84 | ### 3 数据发送和接收 85 | 86 | 不论是哪种 role 发送数据都是调用函数 'nrf24_send_data'，但请一定要认识到 role 的特性和所带来的影响（简单来说 ROLE_PTX 是主动方，ROLE_PRX 是被动的）。xx_run 在检测到在发送完成后（注意：失败也算发送完成）会调用回调函数 tx_done 进行通知。同样 xx_run 在检测并接收到数据后也会调用 rx_ind 进行通知。 87 | 88 | ## III. 其它 89 | 90 | ### 1. 驱动提供有 demo 可用，默认关闭，可在通过 `menuconfig` 中打开 91 | 92 | ```shell 93 | [*] nRF24L01: Single-chip 2.4GHz wireless transceiver. ---> 94 | [*] Ese demo 95 | Role (PTX) ---> 96 | (spi10) The spi device name for nrf24l01 97 | (-1) The ce pin of nrf24l01 98 | (-1) The irq pin of nrf24l01 99 | (100) The interval of sending data (for PTX_ROLE) 100 | ``` 101 | 102 | 必须指定 spi device name 和 ce pin 为有效值 103 | 104 | - -1 为无效 pin。 105 | - irq 为无效 pin 表示不使用中断 106 | 107 | ### 2. 驱动提供了辅助调试的功能，默认关闭，可在 `menuconfig` 中打开 108 | 109 | ```shell 110 | [*] nRF24L01: Single-chip 2.4GHz wireless transceiver. ---> 111 | [*] Enable debug 112 | [*] Use info report 113 | [*] Use shell cmd 114 | ``` 115 | 116 | - Use info report 117 | 118 | 选中该选项会启用 void nrf24_report(void); 该函数的功能是读取 nRF24L01 几乎所有的寄存器，然后进行解读并输出解读信息 119 | 120 | - Use shell cmd 121 | 122 | 选中该选项会添加一 msh 命令 nrf24，使用该命令可以对 nRF24L01 进行初始化、读写寄存器等 123 | -------------------------------------------------------------------------------- /src/SConscript: -------------------------------------------------------------------------------- 1 | from building import * 2 | Import('rtconfig') 3 | 4 | cwd = GetCurrentDir() 5 | src = Glob('*.c') 6 | path = [cwd] 7 | 8 | group = DefineGroup('nRF24L01', src, depend = ['PKG_USING_NRF24L01'], CPPPATH = path) 9 | 10 | Return('group') -------------------------------------------------------------------------------- /src/nrf24l01.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019, sogwyms@gmail.com 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Change Logs: 7 | * Date Author Notes 8 | * 2019-05-23 sogwms the first version 9 | * 2020-02-02 sogwms refactor to object-oriented and make simplification and ... 10 | */ 11 | 12 | // note: 地址宽度:5 13 | 14 | /* Includes --------------------------------------------------------------------------------*/ 15 | #include 16 | #include "nrf24l01.h" 17 | 18 | #define DBG_SECTION_NAME "nrf24l01" 19 | #define DBG_LEVEL DBG_LOG 20 | #include 21 | 22 | #ifdef PKG_NRF24L01_ENABLING_DEBUG 23 | #ifdef PKG_NRF24L01_USING_INFO_REPORT 24 | #define NRF24_USING_INFO_REPORT 25 | #endif 26 | #ifdef PKG_NRF24L01_USING_SHELL_CMD 27 | #define NRF24_USING_SHELL_CMD 28 | #endif 29 | #endif 30 | 31 | ///<命令映射 32 | #define NRF24CMD_R_REG 0x00 // 读寄存器 33 | #define NRF24CMD_W_REG 0x20 // 写寄存器 34 | #define NRF24CMD_R_RX_PAYLOAD 0x61 // 读接收缓冲区 35 | #define NRF24CMD_W_TX_PAYLOAD 0xA0 // 写发送缓冲区 36 | #define NRF24CMD_FLUSH_TX 0xE1 // 清空发送FIFO 37 | #define NRF24CMD_FLUSH_RX 0xE2 // 清空接收FIFO 38 | #define NRF24CMD_REUSE_TX_PL 0xE3 // PTX模式下使用，重装载发送缓冲区 39 | #define NRF24CMD_ACTIVATE 0x50 // 使能命令，后接数据 0x73 40 | #define NRF24CMD_R_RX_PL_WID 0x60 // 读顶层接收FIFO大小 41 | #define NRF24CMD_W_ACK_PAYLOAD 0xA8 // RX模式下使用，写应答发送缓冲区 42 | ///<寄存器映射 43 | #define NRF24REG_CONFIG 0x00 // 配置收发状态，CRC校验模式以及收发状态响应方式 44 | #define NRF24REG_EN_AA 0x01 // 自动应答功能设置 45 | #define NRF24REG_EN_RXADDR 0x02 // 可用信道设置 46 | #define NRF24REG_SETUP_AW 0x03 // 收发地址宽度设置 47 | #define NRF24REG_SETUP_RETR 0x04 // 自动重发功能设置 48 | #define NRF24REG_RF_CH 0x05 // 工作频率设置 49 | #define NRF24REG_RF_SETUP 0x06 // 发射速率、功耗功能设置 50 | #define NRF24REG_STATUS 0x07 // 状态寄存器 51 | #define NRF24REG_OBSERVE_TX 0x08 // 发送监测功能 52 | #define NRF24REG_RPD 0x09 // 接收功率检测 53 | #define NRF24REG_RX_ADDR_P0 0x0A // 频道0接收数据地址 54 | #define NRF24REG_RX_ADDR_P1 0x0B // 频道1接收数据地址 55 | #define NRF24REG_RX_ADDR_P2 0x0C // 频道2接收数据地址 56 | #define NRF24REG_RX_ADDR_P3 0x0D // 频道3接收数据地址 57 | #define NRF24REG_RX_ADDR_P4 0x0E // 频道4接收数据地址 58 | #define NRF24REG_RX_ADDR_P5 0x0F // 频道5接收数据地址 59 | #define NRF24REG_TX_ADDR 0x10 // 发送地址寄存器 60 | #define NRF24REG_RX_PW_P0 0x11 // 接收频道0接收数据长度 61 | #define NRF24REG_RX_PW_P1 0x12 // 接收频道1接收数据长度 62 | #define NRF24REG_RX_PW_P2 0x13 // 接收频道2接收数据长度 63 | #define NRF24REG_RX_PW_P3 0x14 // 接收频道3接收数据长度 64 | #define NRF24REG_RX_PW_P4 0x15 // 接收频道4接收数据长度 65 | #define NRF24REG_RX_PW_P5 0x16 // 接收频道5接收数据长度 66 | #define NRF24REG_FIFO_STATUS 0x17 // FIFO栈入栈出状态寄存器设置 67 | #define NRF24REG_DYNPD 0x1C // 动态数据包长度 68 | #define NRF24REG_FEATURE 0x1D // 特点寄存器 69 | ///<寄存器功能位掩码部分映射 70 | //CONFIG 71 | #define NRF24BITMASK_RX_DR ((uint8_t)(1<<6)) // 接收完成中断使能位 72 | #define NRF24BITMASK_TX_DS ((uint8_t)(1<<5)) // 发送完成中断使能位 73 | #define NRF24BITMASK_MAX_RT ((uint8_t)(1<<4)) // 达最大重发次数中断使能位 74 | #define NRF24BITMASK_EN_CRC ((uint8_t)(1<<3)) // CRC使能位 75 | #define NRF24BITMASK_CRCO ((uint8_t)(1<<2)) // CRC编码方式 （1B or 2B） 76 | #define NRF24BITMASK_PWR_UP ((uint8_t)(1<<1)) // 上（掉）电 77 | #define NRF24BITMASK_PRIM_RX ((uint8_t)(1)) // PR（T）X 78 | //SETUP_AW 79 | #define NRF24BITMASK_AW ((uint8_t)(0x03)) // RX/TX地址宽度 80 | //SETUP_RETR 81 | #define NRF24BITMASK_ARD ((uint8_t)(0xF0)) // 重发延时 82 | #define NRF24BITMASK_ARC ((uint8_t)(0x0F)) // 重发最大次数 83 | //RF_CH 84 | #define NRF24BITMASK_RF_CH ((uint8_t)(0x7F)) // 射频频道 85 | //RF_SETUP 86 | #define NRF24BITMASK_RF_DR ((uint8_t)(1<<3)) // 空中速率 87 | #define NRF24BITMASK_RF_PWR ((uint8_t)(0x06)) // 发射功率 88 | //STATUS 89 | #define NRF24BITMASK_RX_DR ((uint8_t)(1<<6)) // 接收完成标志位 90 | #define NRF24BITMASK_TX_DS ((uint8_t)(1<<5)) // 发送完成标志位 91 | #define NRF24BITMASK_MAX_RT ((uint8_t)(1<<4)) // 最大重发次数标志位 92 | #define NRF24BITMASK_RX_P_NO ((uint8_t)(0x0E)) // RX_FIFO状态标志区位 93 | #define NRF24BITMASK_TX_FULL ((uint8_t)(1)) // TX_FIFO满标志位 94 | //OBSERVE_TX 95 | #define NRF24BITMASK_PLOS_CNT ((uint8_t)(0xF0)) // 丢包计数 96 | #define NRF24BITMASK_ARC_CNT ((uint8_t)(0x0F)) // 重发计数 97 | //CD 98 | #define NRF24BITMASK_CD ((uint8_t)(1)) // 载波检测标志位 99 | //通用掩码，RX_PW_P[0::5] 掩码相同 100 | #define NRF24BITMASK_RX_PW_P_ ((uint8_t)(0x3F)) // 数据管道RX-Payload中的字节数 101 | //FIFO_STATUS 102 | #define NRF24BITMASK_TX_REUSE ((uint8_t)(1<<6)) // 103 | #define NRF24BITMASK_TX_FULL2 ((uint8_t)(1<<5)) // 104 | #define NRF24BITMASK_TX_EMPTY ((uint8_t)(1<<4)) // 105 | #define NRF24BITMASK_RX_RXFULL ((uint8_t)(1<<1)) // 106 | #define NRF24BITMASK_RX_EMPTY ((uint8_t)(1)) // 107 | //FEATURE 108 | #define NRF24BITMASK_EN_DPL ((uint8_t)(1<<2)) // 动态长度使能位 109 | #define NRF24BITMASK_EN_ACK_PAY ((uint8_t)(1<<1)) // Payload with ACK 使能位 110 | #define NRF24BITMASK_EN_DYN_ACK ((uint8_t)(1)) // W_TX_PAYLOAD_NOACK 命令使能位 111 | //通用掩码，适用于多个寄存器： EN_AA, EN_RXADDR, DYNPD 112 | #define NRF24BITMASK_PIPE_0 ((uint8_t)(1)) // 113 | #define NRF24BITMASK_PIPE_1 ((uint8_t)(1<<1)) // 114 | #define NRF24BITMASK_PIPE_2 ((uint8_t)(1<<2)) // 115 | #define NRF24BITMASK_PIPE_3 ((uint8_t)(1<<3)) // 116 | #define NRF24BITMASK_PIPE_4 ((uint8_t)(1<<4)) // 117 | #define NRF24BITMASK_PIPE_5 ((uint8_t)(1<<5)) // 118 | 119 | struct nrf24_onchip_cfg 120 | { 121 | struct { 122 | uint8_t prim_rx :1; 123 | uint8_t pwr_up :1; 124 | uint8_t crco :1; 125 | uint8_t en_crc :1; 126 | uint8_t mask_max_rt :1; 127 | uint8_t mask_tx_ds :1; 128 | uint8_t mask_rx_dr :1; 129 | } config; 130 | 131 | struct { 132 | uint8_t p0 :1; 133 | uint8_t p1 :1; 134 | uint8_t p2 :1; 135 | uint8_t p3 :1; 136 | uint8_t p4 :1; 137 | uint8_t p5 :1; 138 | } en_aa; 139 | 140 | struct { 141 | uint8_t p0 :1; 142 | uint8_t p1 :1; 143 | uint8_t p2 :1; 144 | uint8_t p3 :1; 145 | uint8_t p4 :1; 146 | uint8_t p5 :1; 147 | } en_rxaddr; 148 | 149 | struct { 150 | uint8_t aw :2; 151 | } setup_aw; 152 | 153 | struct { 154 | uint8_t arc :4; 155 | uint8_t ard :4; 156 | } setup_retr; 157 | 158 | struct { 159 | uint8_t rf_ch :7; 160 | } rf_ch; 161 | 162 | struct { 163 | uint8_t lna_hcurr :1; 164 | uint8_t rf_pwr :2; 165 | uint8_t rf_dr :1; 166 | uint8_t pll_lock :1; 167 | } rf_setup; 168 | 169 | struct { 170 | uint8_t p0 :1; 171 | uint8_t p1 :1; 172 | uint8_t p2 :1; 173 | uint8_t p3 :1; 174 | uint8_t p4 :1; 175 | uint8_t p5 :1; 176 | } dynpd; 177 | 178 | struct { 179 | uint8_t en_dyn_ack :1; 180 | uint8_t en_ack_pay :1; 181 | uint8_t en_dpl :1; 182 | } feature; 183 | 184 | uint8_t rx_addr_p0[5]; 185 | uint8_t rx_addr_p1[5]; 186 | uint8_t rx_addr_p2; 187 | uint8_t rx_addr_p3; 188 | uint8_t rx_addr_p4; 189 | uint8_t rx_addr_p5; 190 | 191 | uint8_t tx_addr[5]; 192 | 193 | }ALIGN(1); 194 | 195 | #ifdef NRF24_USING_SHELL_CMD 196 | nrf24_t g_debug_nrf24 = RT_NULL; 197 | #endif 198 | 199 | /** S PORT-ORIENTED */ 200 | /** |||||| **/ 201 | 202 | static uint8_t __read_reg(nrf24_t nrf24, uint8_t reg) 203 | { 204 | uint8_t tmp, rtmp = 0; 205 | 206 | tmp = NRF24CMD_R_REG | reg; 207 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, &rtmp, 1); 208 | return rtmp; 209 | } 210 | 211 | static void __write_reg(nrf24_t nrf24, uint8_t reg, uint8_t data) 212 | { 213 | uint8_t tmp[2]; 214 | 215 | tmp[0] = NRF24CMD_W_REG | reg; 216 | tmp[1] = data; 217 | NRF24_HALPORT_WRITE(&tmp[0], 2); 218 | } 219 | 220 | // /** 221 | // * @brief Set bit(s) to 1 based on bit-mask 222 | // * @param[in] mask: bit mask. e.g 0x81 stands for bit7 and bit0 223 | // */ 224 | // static void __set_reg_bits(nrf24_t nrf24, uint8_t reg, uint8_t mask) 225 | // { 226 | // uint8_t tmp; 227 | 228 | // tmp = __read_reg(nrf24, reg); 229 | // tmp |= mask; 230 | // __write_reg(nrf24, reg, tmp); 231 | // } 232 | 233 | // static void __reset_reg_bits(nrf24_t nrf24, uint8_t reg, uint8_t mask) 234 | // { 235 | // uint8_t tmp; 236 | 237 | // tmp = __read_reg(nrf24, reg); 238 | // tmp &= ~mask; 239 | // __write_reg(nrf24, reg, tmp); 240 | // } 241 | 242 | /** 243 | * @brief Treat the specified continuous bit as a whole and then set its value 244 | */ 245 | static void __write_reg_bits(nrf24_t nrf24, uint8_t reg, uint8_t mask, uint8_t value) 246 | { 247 | uint8_t tmp, tidx; 248 | 249 | for (tidx = 0; tidx < 8; tidx++) 250 | { 251 | if (mask & (1 << tidx)) 252 | break; 253 | } 254 | tmp = ~mask & __read_reg(nrf24, reg); 255 | tmp |= mask & (value << tidx); 256 | __write_reg(nrf24, reg, tmp); 257 | } 258 | 259 | /** E PORT-ORIENTED*/ 260 | 261 | /** S SCALPEL */ 262 | /** |||||| **/ 263 | 264 | static uint8_t read_status(nrf24_t nrf24) 265 | { 266 | return __read_reg(nrf24, NRF24REG_STATUS); 267 | } 268 | 269 | // bit: RX_DR, TX_DS, MAX_RT 270 | static void clear_status(nrf24_t nrf24, uint8_t bitmask) 271 | { 272 | __write_reg(nrf24, NRF24REG_STATUS, bitmask); 273 | } 274 | 275 | static void clear_observe_tx(nrf24_t nrf24) 276 | { 277 | __write_reg(nrf24, NRF24REG_OBSERVE_TX, 0); 278 | } 279 | 280 | static uint8_t read_top_rxfifo_width(nrf24_t nrf24) 281 | { 282 | uint8_t tmp = NRF24CMD_R_RX_PL_WID; 283 | 284 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, &tmp, 1); 285 | return tmp; 286 | } 287 | 288 | void nrf24_enter_power_down_mode(nrf24_t nrf24) 289 | { 290 | __write_reg_bits(nrf24, NRF24REG_CONFIG, NRF24BITMASK_PWR_UP, 0); 291 | } 292 | 293 | void nrf24_enter_power_up_mode(nrf24_t nrf24) 294 | { 295 | __write_reg_bits(nrf24, NRF24REG_CONFIG, NRF24BITMASK_PWR_UP, 1); 296 | } 297 | 298 | // static void enabled_irq(nrf24_t nrf24, uint8_t bitmask) 299 | // { 300 | // if (!((bitmask == NRF24BITMASK_RX_DR) || (bitmask == NRF24BITMASK_TX_DS) || (bitmask == NRF24BITMASK_MAX_RT))) 301 | // return; 302 | 303 | // __reset_reg_bits(nrf24, NRF24REG_CONFIG, bitmask); 304 | // } 305 | 306 | // static void disable_irq(nrf24_t nrf24, uint8_t bitmask) 307 | // { 308 | // if (!((bitmask == NRF24BITMASK_RX_DR) || (bitmask == NRF24BITMASK_TX_DS) || (bitmask == NRF24BITMASK_MAX_RT))) 309 | // return; 310 | 311 | // __set_reg_bits(nrf24, NRF24REG_CONFIG, bitmask); 312 | // } 313 | 314 | 315 | static void write_tx_payload(nrf24_t nrf24, const uint8_t *buf, uint8_t len) 316 | { 317 | uint8_t tmp = NRF24CMD_W_TX_PAYLOAD; 318 | 319 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, buf, len); 320 | } 321 | 322 | static void write_ack_payload(nrf24_t nrf24, uint8_t pipe, const uint8_t *buf, uint8_t len) 323 | { 324 | uint8_t tmp; 325 | 326 | if (pipe > 5) 327 | return; 328 | 329 | tmp = NRF24CMD_W_ACK_PAYLOAD | pipe; 330 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, buf, len); 331 | } 332 | 333 | // static int read_rx_payload_width(nrf24_t nrf24, uint8_t pipe) 334 | // { 335 | // if (pipe > 5) 336 | // return 0; 337 | 338 | // uint8_t len = __read_reg(nrf24, NRF24REG_RX_PW_P0+pipe); 339 | 340 | // return len; 341 | // } 342 | 343 | static void read_rx_payload(nrf24_t nrf24, uint8_t *buf, uint8_t len) 344 | { 345 | uint8_t tcmd; 346 | 347 | if ((len > 32) || (len == 0)) 348 | return; 349 | 350 | tcmd = NRF24CMD_R_RX_PAYLOAD; 351 | NRF24_HALPORT_SEND_THEN_RECV(&tcmd, 1, buf, len); 352 | } 353 | 354 | static void flush_tx_fifo(nrf24_t nrf24) 355 | { 356 | uint8_t tmp = NRF24CMD_FLUSH_TX; 357 | 358 | NRF24_HALPORT_WRITE(&tmp, 1); 359 | } 360 | 361 | static void flush_rx_fifo(nrf24_t nrf24) 362 | { 363 | uint8_t tmp = NRF24CMD_FLUSH_RX; 364 | 365 | NRF24_HALPORT_WRITE(&tmp, 1); 366 | } 367 | 368 | /** E SCALPEL */ 369 | 370 | static void ensure_rww_features_activated(nrf24_t nrf24) 371 | { 372 | if (!nrf24->flags.activated_features) 373 | { 374 | uint8_t tmp[2] = {NRF24CMD_ACTIVATE, 0x73}; 375 | NRF24_HALPORT_WRITE(tmp, 2); 376 | nrf24->flags.activated_features = RT_TRUE; 377 | } 378 | } 379 | 380 | static int update_onchip_config(nrf24_t nrf24, const struct nrf24_onchip_cfg *ccfg) 381 | { 382 | uint8_t tmp; 383 | 384 | nrf24_enter_power_down_mode(nrf24); 385 | ensure_rww_features_activated(nrf24); 386 | 387 | __write_reg(nrf24, NRF24REG_EN_AA, *((uint8_t *)&ccfg->en_aa)); 388 | __write_reg(nrf24, NRF24REG_EN_RXADDR, *((uint8_t *)&ccfg->en_rxaddr)); 389 | __write_reg(nrf24, NRF24REG_SETUP_AW, *((uint8_t *)&ccfg->setup_aw)); 390 | __write_reg(nrf24, NRF24REG_SETUP_RETR, *((uint8_t *)&ccfg->setup_retr)); 391 | __write_reg(nrf24, NRF24REG_RF_CH, *((uint8_t *)&ccfg->rf_ch)); 392 | __write_reg(nrf24, NRF24REG_RF_SETUP, *((uint8_t *)&ccfg->rf_setup)); 393 | __write_reg(nrf24, NRF24REG_DYNPD, *((uint8_t *)&ccfg->dynpd)); 394 | __write_reg(nrf24, NRF24REG_FEATURE, *((uint8_t *)&ccfg->feature)); 395 | 396 | tmp = NRF24CMD_W_REG | NRF24REG_TX_ADDR; 397 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, ccfg->tx_addr, 5); 398 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P0; 399 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, ccfg->rx_addr_p0, 5); 400 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P1; 401 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, ccfg->rx_addr_p1, 5); 402 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P2; 403 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, &ccfg->rx_addr_p2, 1); 404 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P3; 405 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, &ccfg->rx_addr_p3, 1); 406 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P4; 407 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, &ccfg->rx_addr_p4, 1); 408 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P5; 409 | NRF24_HALPORT_SEND_THEN_SEND(&tmp, 1, &ccfg->rx_addr_p5, 1); 410 | 411 | __write_reg(nrf24, NRF24REG_CONFIG, *((uint8_t *)&ccfg->config)); 412 | 413 | return RT_EOK; 414 | } 415 | 416 | static int read_onchip_config(nrf24_t nrf24, struct nrf24_onchip_cfg *ccfg) 417 | { 418 | struct nrf24_onchip_cfg real_cfg; 419 | uint8_t tmp; 420 | 421 | *((uint8_t *)&real_cfg.en_aa) = __read_reg(nrf24, NRF24REG_EN_AA); 422 | *((uint8_t *)&real_cfg.en_rxaddr) = __read_reg(nrf24, NRF24REG_EN_RXADDR); 423 | *((uint8_t *)&real_cfg.setup_aw) = __read_reg(nrf24, NRF24REG_SETUP_AW); 424 | *((uint8_t *)&real_cfg.setup_retr) = __read_reg(nrf24, NRF24REG_SETUP_RETR); 425 | *((uint8_t *)&real_cfg.rf_ch) = __read_reg(nrf24, NRF24REG_RF_CH); 426 | *((uint8_t *)&real_cfg.rf_setup) = __read_reg(nrf24, NRF24REG_RF_SETUP); 427 | *((uint8_t *)&real_cfg.dynpd) = __read_reg(nrf24, NRF24REG_DYNPD); 428 | *((uint8_t *)&real_cfg.feature) = __read_reg(nrf24, NRF24REG_FEATURE); 429 | *((uint8_t *)&real_cfg.config) = __read_reg(nrf24, NRF24REG_CONFIG); 430 | 431 | tmp = NRF24CMD_R_REG | NRF24REG_TX_ADDR; 432 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.tx_addr, 5); 433 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P0; 434 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.rx_addr_p0, 5); 435 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P1; 436 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.rx_addr_p1, 5); 437 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P2; 438 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.rx_addr_p2, 1); 439 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P3; 440 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.rx_addr_p3, 1); 441 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P4; 442 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.rx_addr_p4, 1); 443 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P5; 444 | NRF24_HALPORT_SEND_THEN_RECV(&tmp, 1, (uint8_t *)&real_cfg.rx_addr_p5, 1); 445 | 446 | rt_memcpy(ccfg, &real_cfg, sizeof(struct nrf24_onchip_cfg)); 447 | 448 | return RT_EOK; 449 | } 450 | 451 | static int check_onchip_config(nrf24_t nrf24, const struct nrf24_onchip_cfg *ccfg) 452 | { 453 | struct nrf24_onchip_cfg real_cfg; 454 | 455 | read_onchip_config(nrf24, &real_cfg); 456 | 457 | if (rt_memcmp(&real_cfg, ccfg, sizeof(struct nrf24_onchip_cfg)) == 0) 458 | return RT_EOK; 459 | else 460 | return RT_ERROR; 461 | } 462 | 463 | static int build_onchip_config(struct nrf24_onchip_cfg *ccfg, const struct nrf24_cfg *ucfg) 464 | { 465 | rt_memset(ccfg, 0, sizeof(struct nrf24_onchip_cfg)); 466 | 467 | /* Default config */ 468 | ccfg->setup_retr.ard = 1; // 500us 469 | ccfg->setup_retr.arc = 11; // 11 times 470 | ccfg->setup_aw.aw = 3; // 5-byte address width 471 | 472 | ccfg->rf_setup.pll_lock = 0; 473 | ccfg->rf_setup.lna_hcurr = 1; 474 | 475 | ccfg->en_aa.p0 = 1; 476 | ccfg->en_aa.p1 = 1; 477 | ccfg->en_aa.p2 = 1; 478 | ccfg->en_aa.p3 = 1; 479 | ccfg->en_aa.p4 = 1; 480 | ccfg->en_aa.p5 = 1; 481 | 482 | ccfg->dynpd.p0 = 1; 483 | ccfg->dynpd.p1 = 1; 484 | ccfg->dynpd.p2 = 1; 485 | ccfg->dynpd.p3 = 1; 486 | ccfg->dynpd.p4 = 1; 487 | ccfg->dynpd.p5 = 1; 488 | 489 | ccfg->feature.en_dyn_ack = 1; 490 | ccfg->feature.en_ack_pay = 1; 491 | ccfg->feature.en_dpl = 1; 492 | /* END Default config*/ 493 | 494 | /**/ 495 | if (ucfg->_irq_pin == NRF24_PIN_NONE) 496 | { 497 | ccfg->config.mask_rx_dr = 1; 498 | ccfg->config.mask_tx_ds = 1; 499 | ccfg->config.mask_max_rt = 1; 500 | } 501 | 502 | ccfg->config.pwr_up = 1; 503 | ccfg->config.prim_rx = ucfg->role; 504 | ccfg->config.en_crc = 1; 505 | ccfg->config.crco = ucfg->crc; 506 | 507 | ccfg->rf_setup.rf_pwr = ucfg->power; 508 | ccfg->rf_setup.rf_dr = ucfg->adr; 509 | ccfg->rf_ch.rf_ch = ucfg->channel; 510 | 511 | rt_memcpy(ccfg->tx_addr, ucfg->txaddr, sizeof(ucfg->txaddr)); 512 | 513 | ccfg->en_rxaddr.p0 = ucfg->rxpipe0.bl_enabled; 514 | ccfg->en_rxaddr.p1 = ucfg->rxpipe1.bl_enabled; 515 | ccfg->en_rxaddr.p2 = ucfg->rxpipe2.bl_enabled; 516 | ccfg->en_rxaddr.p3 = ucfg->rxpipe3.bl_enabled; 517 | ccfg->en_rxaddr.p4 = ucfg->rxpipe4.bl_enabled; 518 | ccfg->en_rxaddr.p5 = ucfg->rxpipe5.bl_enabled; 519 | 520 | rt_memcpy(ccfg->rx_addr_p0, ucfg->rxpipe0.addr, sizeof(ucfg->rxpipe0.addr)); 521 | rt_memcpy(ccfg->rx_addr_p1, ucfg->rxpipe1.addr, sizeof(ucfg->rxpipe1.addr)); 522 | ccfg->rx_addr_p2 = ucfg->rxpipe2.addr; 523 | ccfg->rx_addr_p3 = ucfg->rxpipe3.addr; 524 | ccfg->rx_addr_p4 = ucfg->rxpipe4.addr; 525 | ccfg->rx_addr_p5 = ucfg->rxpipe5.addr; 526 | 527 | return RT_EOK; 528 | } 529 | 530 | /** 531 | * Test the connection with NRF24 532 | */ 533 | static int check_halport(hal_nrf24_port_t halport) 534 | { 535 | uint8_t addr[5] = {1,2,3,4,5}, backup_addr[5]; 536 | uint8_t tmp; 537 | 538 | RT_ASSERT(halport != RT_NULL); 539 | RT_ASSERT(halport->ops != RT_NULL); 540 | 541 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P1; 542 | halport->ops->send_then_recv(halport, &tmp, 1, backup_addr, 5); 543 | 544 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P1; 545 | halport->ops->send_then_send(halport, &tmp, 1, addr, 5); 546 | 547 | rt_memset(addr, 0, 5); 548 | 549 | tmp = NRF24CMD_R_REG | NRF24REG_RX_ADDR_P1; 550 | halport->ops->send_then_recv(halport, &tmp, 1, addr, 5); 551 | 552 | for (int i = 0; i < 5; i++) 553 | { 554 | if (addr[i] != i+1) 555 | return RT_ERROR; 556 | } 557 | 558 | tmp = NRF24CMD_W_REG | NRF24REG_RX_ADDR_P1; 559 | halport->ops->send_then_send(halport, &tmp, 1, backup_addr, 5); 560 | 561 | return RT_EOK; 562 | } 563 | 564 | /** 565 | * Set the user-oriented configuration as the default 566 | */ 567 | int nrf24_fill_default_config_on(nrf24_cfg_t cfg) 568 | { 569 | RT_ASSERT(cfg != RT_NULL); 570 | 571 | rt_memset(cfg, 0, sizeof(struct nrf24_cfg)); 572 | 573 | cfg->power = RF_POWER_0dBm; 574 | cfg->crc = CRC_2_BYTE; 575 | cfg->adr = ADR_2Mbps; 576 | cfg->channel = 100; 577 | cfg->role = ROLE_NONE; 578 | 579 | for (int i = 0; i < 5; i++) 580 | { 581 | cfg->txaddr[i] = i; 582 | cfg->rxpipe0.addr[i] = i; 583 | cfg->rxpipe1.addr[i] = i+1; 584 | } 585 | cfg->rxpipe2.addr = 2; 586 | cfg->rxpipe3.addr = 3; 587 | cfg->rxpipe4.addr = 4; 588 | cfg->rxpipe5.addr = 5; 589 | 590 | cfg->rxpipe0.bl_enabled = RT_TRUE; 591 | cfg->rxpipe1.bl_enabled = RT_TRUE; 592 | 593 | cfg->rxpipe2.bl_enabled = RT_FALSE; 594 | cfg->rxpipe3.bl_enabled = RT_FALSE; 595 | cfg->rxpipe4.bl_enabled = RT_FALSE; 596 | cfg->rxpipe5.bl_enabled = RT_FALSE; 597 | 598 | return RT_EOK; 599 | } 600 | 601 | int nrf24_send_data(nrf24_t nrf24, uint8_t *data, uint8_t len, uint8_t pipe) 602 | { 603 | if (len > 32) 604 | return RT_ERROR; 605 | 606 | if (nrf24->cfg.role == ROLE_PTX) 607 | { 608 | write_tx_payload(nrf24, data, len); 609 | } 610 | else 611 | { 612 | write_ack_payload(nrf24, pipe, data, len); 613 | rt_sem_release(nrf24->send_sem); 614 | } 615 | 616 | return RT_EOK; 617 | } 618 | 619 | void __irq_handler(hal_nrf24_port_t halport) 620 | { 621 | nrf24_t nrf24 = (nrf24_t)halport; 622 | 623 | rt_sem_release(nrf24->sem); 624 | } 625 | 626 | /** 627 | * ? if try to create sem with the existing name, what will happen 628 | */ 629 | int nrf24_init(nrf24_t nrf24, char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, const nrf24_cfg_t cfg) 630 | { 631 | struct nrf24_onchip_cfg onchip_cfg; 632 | 633 | RT_ASSERT(nrf24 != RT_NULL); 634 | RT_ASSERT(cfg != RT_NULL); 635 | 636 | RT_ASSERT(cb != RT_NULL); 637 | 638 | rt_memset(nrf24, 0, sizeof(struct nrf24)); 639 | 640 | nrf24->send_sem = rt_sem_create("nrfsend", 0, RT_IPC_FLAG_FIFO); 641 | if (nrf24->send_sem == RT_NULL) 642 | { 643 | LOG_E("Failed to create sem"); 644 | return RT_ERROR; 645 | } 646 | 647 | if (irq_pin != NRF24_PIN_NONE) 648 | { 649 | nrf24->sem = rt_sem_create("nrfirq", 0, RT_IPC_FLAG_FIFO); 650 | if (nrf24->sem == RT_NULL) 651 | { 652 | LOG_E("Failed to create sem"); 653 | return RT_ERROR; 654 | } 655 | 656 | nrf24->flags.using_irq = RT_TRUE; 657 | } 658 | else 659 | { 660 | nrf24->flags.using_irq = RT_FALSE; 661 | } 662 | 663 | rt_memcpy(&nrf24->cb, cb, sizeof(struct nrf24_callback)); 664 | rt_memcpy(&nrf24->cfg, cfg, sizeof(struct nrf24_cfg)); 665 | nrf24->cfg._irq_pin = irq_pin; 666 | 667 | if (hal_nrf24_port_init(&nrf24->halport, spi_dev_name, ce_pin, irq_pin, __irq_handler) != RT_EOK) 668 | return RT_ERROR; 669 | 670 | if (check_halport(&nrf24->halport) != RT_EOK) 671 | return RT_ERROR; 672 | 673 | if (build_onchip_config(&onchip_cfg, &nrf24->cfg) != RT_EOK) 674 | return RT_ERROR; 675 | 676 | if (update_onchip_config(nrf24, &onchip_cfg) != RT_EOK) 677 | return RT_ERROR; 678 | 679 | if (check_onchip_config(nrf24, &onchip_cfg) != RT_EOK) 680 | return RT_ERROR; 681 | 682 | flush_tx_fifo(nrf24); 683 | flush_rx_fifo(nrf24); 684 | clear_status(nrf24, NRF24BITMASK_RX_DR | NRF24BITMASK_TX_DS | NRF24BITMASK_MAX_RT); 685 | clear_observe_tx(nrf24); 686 | 687 | nrf24_enter_power_up_mode(nrf24); 688 | nrf24->halport.ops->set_ce(&nrf24->halport); 689 | 690 | LOG_I("Successfully initialized"); 691 | 692 | #ifdef NRF24_USING_SHELL_CMD 693 | g_debug_nrf24 = nrf24; 694 | #endif 695 | 696 | return RT_EOK; 697 | } 698 | 699 | nrf24_t nrf24_create(char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, const nrf24_cfg_t cfg) 700 | { 701 | RT_ASSERT(cfg != RT_NULL); 702 | 703 | nrf24_t new_nrf24 = (nrf24_t)rt_malloc(sizeof(struct nrf24)); 704 | if (new_nrf24 == RT_NULL) 705 | { 706 | rt_free(new_nrf24); 707 | LOG_E("Failed to allocate memory!"); 708 | } 709 | else 710 | { 711 | if (nrf24_init(new_nrf24, spi_dev_name, ce_pin, irq_pin, cb, cfg) != RT_EOK) 712 | { 713 | rt_free(new_nrf24); 714 | new_nrf24 = RT_NULL; 715 | } 716 | } 717 | 718 | if (new_nrf24 == RT_NULL) 719 | LOG_E("Failed to create nrf24 instance"); 720 | 721 | return new_nrf24; 722 | } 723 | 724 | int nrf24_default_init(nrf24_t nrf24, char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, nrf24_role_et role) 725 | { 726 | struct nrf24_cfg cfg; 727 | 728 | nrf24_fill_default_config_on(&cfg); 729 | cfg.role = role; 730 | return nrf24_init(nrf24, spi_dev_name, ce_pin, irq_pin, cb, &cfg); 731 | } 732 | 733 | nrf24_t nrf24_default_create(char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, nrf24_role_et role) 734 | { 735 | nrf24_t new_nrf24 = (nrf24_t)rt_malloc(sizeof(struct nrf24)); 736 | if (new_nrf24 == RT_NULL) 737 | { 738 | rt_free(new_nrf24); 739 | LOG_E("Failed to allocate memory!"); 740 | } 741 | else 742 | { 743 | if (nrf24_default_init(new_nrf24, spi_dev_name, ce_pin, irq_pin, cb, role) != RT_EOK) 744 | { 745 | rt_free(new_nrf24); 746 | new_nrf24 = RT_NULL; 747 | } 748 | } 749 | 750 | if (new_nrf24 == RT_NULL) 751 | LOG_E("Failed to create nrf24 instance"); 752 | 753 | return new_nrf24; 754 | } 755 | 756 | /** 757 | * check status and inform 758 | * @param nrf24 pointer of nrf24 instance 759 | * @return -x:error 0:nothing 1:tx_done 2:rx_done 3:tx_rx_done 760 | */ 761 | int nrf24_run(nrf24_t nrf24) 762 | { 763 | int rvl = 0; 764 | 765 | if (nrf24->flags.using_irq) 766 | { 767 | rt_sem_take(nrf24->sem, RT_WAITING_FOREVER); 768 | } 769 | 770 | nrf24->status = read_status(nrf24); 771 | clear_status(nrf24, NRF24BITMASK_RX_DR | NRF24BITMASK_TX_DS); 772 | 773 | uint8_t pipe = (nrf24->status & NRF24BITMASK_RX_P_NO) >> 1; 774 | 775 | if (nrf24->cfg.role == ROLE_PTX) 776 | { 777 | if (nrf24->status & NRF24BITMASK_MAX_RT) 778 | { 779 | flush_tx_fifo(nrf24); 780 | clear_status(nrf24, NRF24BITMASK_MAX_RT); 781 | if(nrf24->cb.tx_done) nrf24->cb.tx_done(nrf24, NRF24_PIPE_NONE); 782 | return -1; 783 | } 784 | 785 | if (nrf24->status & NRF24BITMASK_RX_DR) 786 | { 787 | uint8_t data[32]; 788 | uint8_t len = read_top_rxfifo_width(nrf24); 789 | 790 | read_rx_payload(nrf24, data, len); 791 | if (nrf24->cb.rx_ind) nrf24->cb.rx_ind(nrf24, data, len, pipe); 792 | 793 | rvl |= 2; 794 | } 795 | 796 | if (nrf24->status & NRF24BITMASK_TX_DS) 797 | { 798 | if (nrf24->cb.tx_done) nrf24->cb.tx_done(nrf24, pipe); 799 | 800 | rvl |= 1; 801 | } 802 | } 803 | else 804 | { 805 | if (pipe <= 5) 806 | { 807 | uint8_t data[32]; 808 | uint8_t len = read_top_rxfifo_width(nrf24); 809 | 810 | read_rx_payload(nrf24, data, len); 811 | if (nrf24->cb.rx_ind) nrf24->cb.rx_ind(nrf24, data, len, pipe); 812 | 813 | rvl |= 2; 814 | 815 | if (rt_sem_trytake(nrf24->send_sem) == RT_EOK) 816 | { 817 | if (nrf24->cb.tx_done) nrf24->cb.tx_done(nrf24, pipe); 818 | rvl |= 1; 819 | } 820 | } 821 | } 822 | 823 | return rvl; 824 | } 825 | 826 | /** S DEBUG */ 827 | /** |||||| **/ 828 | 829 | #if defined(NRF24_USING_INFO_REPORT) 830 | 831 | void __nrf24_report_config_reg(uint8_t data) 832 | { 833 | if (data & NRF24BITMASK_PRIM_RX) 834 | rt_kprintf("PRX mode\r\n"); 835 | else 836 | rt_kprintf("PTX mode\r\n"); 837 | if (data & NRF24BITMASK_EN_CRC) 838 | { 839 | rt_kprintf("crc opened. FCS: "); 840 | if (data & NRF24BITMASK_CRCO) 841 | rt_kprintf("2bytes\r\n"); 842 | else 843 | rt_kprintf("1byte\r\n"); 844 | } 845 | else 846 | rt_kprintf("crc closed\r\n"); 847 | if (!(data & (NRF24BITMASK_RX_DR | NRF24BITMASK_TX_DS | NRF24BITMASK_MAX_RT))) 848 | { 849 | if (!(data & NRF24BITMASK_RX_DR)) 850 | rt_kprintf("RX irq; "); 851 | if (!(data & NRF24BITMASK_TX_DS)) 852 | rt_kprintf("TX irq; "); 853 | if (!(data & NRF24BITMASK_MAX_RT)) 854 | rt_kprintf("MAX_RT irq; "); 855 | rt_kprintf("opened\r\n"); 856 | } 857 | else 858 | { 859 | rt_kprintf("all irq closed\r\n"); 860 | } 861 | if (data & NRF24BITMASK_PWR_UP) 862 | rt_kprintf("power up now\r\n"); 863 | else 864 | rt_kprintf("power down now\r\n"); 865 | } 866 | 867 | void __nrf24_report_enaa_reg(uint8_t data) 868 | { 869 | if (!(data & 0x3F)) 870 | { 871 | rt_kprintf("all pipe AA closed"); 872 | return; 873 | } 874 | 875 | if (data & NRF24BITMASK_PIPE_0) 876 | rt_kprintf("pipe0 "); 877 | if (data & NRF24BITMASK_PIPE_1) 878 | rt_kprintf("pipe1 "); 879 | if (data & NRF24BITMASK_PIPE_2) 880 | rt_kprintf("pipe2 "); 881 | if (data & NRF24BITMASK_PIPE_3) 882 | rt_kprintf("pipe3 "); 883 | if (data & NRF24BITMASK_PIPE_4) 884 | rt_kprintf("pipe4 "); 885 | if (data & NRF24BITMASK_PIPE_5) 886 | rt_kprintf("pipe5 "); 887 | rt_kprintf("AA opened\r\n"); 888 | } 889 | void __nrf24_report_enrxaddr_reg(uint8_t data) 890 | { 891 | if (!(data & 0x3F)) 892 | { 893 | rt_kprintf("all rx-pipe closed"); 894 | return; 895 | } 896 | 897 | if (data & NRF24BITMASK_PIPE_0) 898 | rt_kprintf("rx-pipe0 "); 899 | if (data & NRF24BITMASK_PIPE_1) 900 | rt_kprintf("rx-pipe1 "); 901 | if (data & NRF24BITMASK_PIPE_2) 902 | rt_kprintf("rx-pipe2 "); 903 | if (data & NRF24BITMASK_PIPE_3) 904 | rt_kprintf("rx-pipe3 "); 905 | if (data & NRF24BITMASK_PIPE_4) 906 | rt_kprintf("rx-pipe4 "); 907 | if (data & NRF24BITMASK_PIPE_5) 908 | rt_kprintf("rx-pipe5 "); 909 | rt_kprintf(" opened\r\n"); 910 | } 911 | void __nrf24_report_setupaw_reg(uint8_t data) 912 | { 913 | rt_kprintf("rx/tx address field width: "); 914 | switch (data & 0x3) 915 | { 916 | case 0: 917 | rt_kprintf("illegal\r\n"); 918 | break; 919 | case 1: 920 | rt_kprintf("3bytes\r\n"); 921 | break; 922 | case 2: 923 | rt_kprintf("4bytes\r\n"); 924 | break; 925 | case 3: 926 | rt_kprintf("5bytes\r\n"); 927 | break; 928 | } 929 | } 930 | void __nrf24_report_setupretr_reg(uint8_t data) 931 | { 932 | rt_kprintf("auto retransmit delay: %dus\r\n", (((data & 0xF0) >> 4) + 1) * 250); 933 | rt_kprintf("auto retransmit count: up to %d\r\n", (data & 0x0F)); 934 | } 935 | void __nrf24_report_rfch_reg(uint8_t data) 936 | { 937 | rt_kprintf("rf channel: %d\r\n", data & 0x7F); 938 | } 939 | void __nrf24_report_rfsetup_reg(uint8_t data) 940 | { 941 | rt_kprintf("air data rate: "); 942 | if (data & NRF24BITMASK_RF_DR) 943 | rt_kprintf("2Mbps\r\n"); 944 | else 945 | rt_kprintf("1Mbsp\r\n"); 946 | 947 | rt_kprintf("rf power: "); 948 | switch ((data & NRF24BITMASK_RF_PWR) >> 1) 949 | { 950 | case 0: 951 | rt_kprintf("-18dBm\r\n"); 952 | break; 953 | case 1: 954 | rt_kprintf("-12dBm\r\n"); 955 | break; 956 | case 2: 957 | rt_kprintf("-6dBm\r\n"); 958 | break; 959 | case 3: 960 | rt_kprintf("0dBm\r\n"); 961 | break; 962 | } 963 | } 964 | void __nrf24_report_status_reg(uint8_t data) 965 | { 966 | rt_kprintf("status: "); 967 | if (data & NRF24BITMASK_RX_DR) 968 | rt_kprintf("new rx data; "); 969 | if (data & NRF24BITMASK_TX_DS) 970 | rt_kprintf("last tx ok; "); 971 | if (data & NRF24BITMASK_MAX_RT) 972 | rt_kprintf("max-rt error exist; "); 973 | 974 | if (data & NRF24BITMASK_TX_FULL) 975 | rt_kprintf("tx-fifo is full; "); 976 | else 977 | rt_kprintf("tx-fifo is not full; "); 978 | 979 | data = (data & NRF24BITMASK_RX_P_NO) >> 1; 980 | if (data > 5) 981 | { 982 | if (data == 7) 983 | rt_kprintf("rx-fifo empty; "); 984 | else 985 | rt_kprintf("rx-fifo not used?; "); 986 | } 987 | else 988 | { 989 | rt_kprintf("rx-fifo pipe: %d; ", data); 990 | } 991 | 992 | rt_kprintf("\r\n"); 993 | } 994 | void __nrf24_report_observetx_reg(uint8_t data) 995 | { 996 | rt_kprintf("lost packets count: %d\r\n", (data & NRF24BITMASK_PLOS_CNT) >> 4); 997 | rt_kprintf("retransmitted packets count: %d\r\n", data & NRF24BITMASK_ARC_CNT); 998 | } 999 | 1000 | void __nrf24_report_fifostatus_reg(uint8_t data) 1001 | { 1002 | if (data & NRF24BITMASK_TX_REUSE) 1003 | rt_kprintf("tx-reuse opened\r\n"); 1004 | 1005 | if (data & NRF24BITMASK_TX_FULL2) 1006 | rt_kprintf("tx-fifo full\r\n"); 1007 | else if (data & NRF24BITMASK_TX_EMPTY) 1008 | rt_kprintf("tx-fifo empty\r\n"); 1009 | else 1010 | rt_kprintf("tx-fifo has some data\r\n"); 1011 | 1012 | if (data & NRF24BITMASK_RX_RXFULL) 1013 | rt_kprintf("rx-fifo full\r\n"); 1014 | else if (data & NRF24BITMASK_RX_EMPTY) 1015 | rt_kprintf("rx-fifo empty\r\n"); 1016 | else 1017 | rt_kprintf("rx-fifo has some data\r\n"); 1018 | } 1019 | void __nrf24_report_dynpd_reg(uint8_t data) 1020 | { 1021 | rt_kprintf("dynamic payload length enabled (pipe): "); 1022 | if (!(data & 0x3F)) 1023 | { 1024 | rt_kprintf("none\r\n"); 1025 | return; 1026 | } 1027 | 1028 | if (data & NRF24BITMASK_PIPE_0) 1029 | rt_kprintf("pipe0; "); 1030 | if (data & NRF24BITMASK_PIPE_1) 1031 | rt_kprintf("pipe1; "); 1032 | if (data & NRF24BITMASK_PIPE_2) 1033 | rt_kprintf("pipe2; "); 1034 | if (data & NRF24BITMASK_PIPE_3) 1035 | rt_kprintf("pipe3; "); 1036 | if (data & NRF24BITMASK_PIPE_4) 1037 | rt_kprintf("pipe4; "); 1038 | if (data & NRF24BITMASK_PIPE_5) 1039 | rt_kprintf("pipe5; "); 1040 | rt_kprintf("\r\n"); 1041 | } 1042 | void __nrf24_report_feature_reg(uint8_t data) 1043 | { 1044 | rt_kprintf("feature enabled conditions: "); 1045 | if (data & NRF24BITMASK_EN_DPL) 1046 | rt_kprintf("dynamic payload length; "); 1047 | if (data & NRF24BITMASK_EN_ACK_PAY) 1048 | rt_kprintf("payload with ack; "); 1049 | if (data & NRF24BITMASK_EN_DYN_ACK) 1050 | rt_kprintf("W_TX_PAYLOAD_NOACK command; "); 1051 | 1052 | rt_kprintf("\r\n"); 1053 | } 1054 | 1055 | void __nrf24_report_addr(nrf24_t nrf24) 1056 | { 1057 | struct nrf24_onchip_cfg ccfg; 1058 | read_onchip_config(nrf24, &ccfg); 1059 | rt_kprintf("tx-addr:0x%02x%02x%02x%02x%02x\n", 1060 | ccfg.tx_addr[4], 1061 | ccfg.tx_addr[3], 1062 | ccfg.tx_addr[2], 1063 | ccfg.tx_addr[1], 1064 | ccfg.tx_addr[0]); 1065 | 1066 | rt_kprintf("rx-addr-p0:0x%02x%02x%02x%02x%02x\n", 1067 | ccfg.rx_addr_p0[4], 1068 | ccfg.rx_addr_p0[3], 1069 | ccfg.rx_addr_p0[2], 1070 | ccfg.rx_addr_p0[1], 1071 | ccfg.rx_addr_p0[0]); 1072 | 1073 | rt_kprintf("rx-addr-p1:0x%02x%02x%02x%02x%02x\n", 1074 | ccfg.rx_addr_p1[4], 1075 | ccfg.rx_addr_p1[3], 1076 | ccfg.rx_addr_p1[2], 1077 | ccfg.rx_addr_p1[1], 1078 | ccfg.rx_addr_p1[0]); 1079 | 1080 | rt_kprintf("rx-addr-p2:0x%02x\n", ccfg.rx_addr_p2); 1081 | rt_kprintf("rx-addr-p3:0x%02x\n", ccfg.rx_addr_p3); 1082 | rt_kprintf("rx-addr-p4:0x%02x\n", ccfg.rx_addr_p4); 1083 | rt_kprintf("rx-addr-p5:0x%02x\n", ccfg.rx_addr_p5); 1084 | } 1085 | 1086 | void nrf24_report(nrf24_t nrf24) 1087 | { 1088 | __nrf24_report_config_reg(__read_reg(nrf24, NRF24REG_CONFIG)); 1089 | __nrf24_report_enaa_reg(__read_reg(nrf24, NRF24REG_EN_AA)); 1090 | __nrf24_report_enrxaddr_reg(__read_reg(nrf24, NRF24REG_EN_RXADDR)); 1091 | __nrf24_report_setupaw_reg(__read_reg(nrf24, NRF24REG_SETUP_AW)); 1092 | __nrf24_report_setupretr_reg(__read_reg(nrf24, NRF24REG_SETUP_RETR)); 1093 | __nrf24_report_rfch_reg(__read_reg(nrf24, NRF24REG_RF_CH)); 1094 | __nrf24_report_rfsetup_reg(__read_reg(nrf24, NRF24REG_RF_SETUP)); 1095 | __nrf24_report_status_reg(__read_reg(nrf24, NRF24REG_STATUS)); 1096 | __nrf24_report_observetx_reg(__read_reg(nrf24, NRF24REG_OBSERVE_TX)); 1097 | 1098 | __nrf24_report_fifostatus_reg(__read_reg(nrf24, NRF24REG_FIFO_STATUS)); 1099 | __nrf24_report_dynpd_reg(__read_reg(nrf24, NRF24REG_DYNPD)); 1100 | __nrf24_report_feature_reg(__read_reg(nrf24, NRF24REG_FEATURE)); 1101 | __nrf24_report_addr(nrf24); 1102 | } 1103 | 1104 | #endif // NRF24_USING_INFO_REPORT 1105 | 1106 | #ifdef NRF24_USING_SHELL_CMD 1107 | #include 1108 | 1109 | static void nrf24(int argc, char **argv) 1110 | { 1111 | static nrf24_t instance = RT_NULL; 1112 | 1113 | if (argc < 2) 1114 | { 1115 | rt_kprintf("Usage: nrf24 [OPTION]\n"); 1116 | rt_kprintf("Options:\n"); 1117 | rt_kprintf(" init \n"); 1118 | rt_kprintf(" probe\n"); 1119 | rt_kprintf(" check_halport\n"); 1120 | rt_kprintf(" read \n"); 1121 | rt_kprintf(" write \n"); 1122 | #ifdef NRF24_USING_INFO_REPORT 1123 | rt_kprintf(" report\n"); 1124 | #endif // NRF24_USING_INFO_REPORT 1125 | 1126 | return; 1127 | } 1128 | 1129 | #ifdef NRF24_USING_INFO_REPORT 1130 | if (!rt_strcmp(argv[1], "report")) 1131 | { 1132 | nrf24_report(instance); 1133 | } 1134 | #endif // NRF24_USING_INFO_REPORT 1135 | 1136 | if (!rt_strcmp(argv[1], "check_halport")) 1137 | { 1138 | if (check_halport(&instance->halport) == RT_EOK) 1139 | rt_kprintf("OK\n"); 1140 | else 1141 | rt_kprintf("ERROR\n"); 1142 | } 1143 | else if (!rt_strcmp(argv[1], "probe")) 1144 | { 1145 | if (g_debug_nrf24 != RT_NULL) 1146 | { 1147 | instance = g_debug_nrf24; 1148 | rt_kprintf("OK\n"); 1149 | } 1150 | else 1151 | rt_kprintf("ERROR\n"); 1152 | } 1153 | 1154 | if (argc < 3) 1155 | { 1156 | return; 1157 | } 1158 | if (!rt_strcmp(argv[1], "read")) 1159 | { 1160 | uint8_t reg = atoi(argv[2]); 1161 | rt_kprintf("reg:0x%x val: 0x%x\n", reg, __read_reg(instance, reg)); 1162 | } 1163 | 1164 | if (argc < 4) 1165 | { 1166 | return; 1167 | } 1168 | if (!rt_strcmp(argv[1], "write")) 1169 | { 1170 | uint8_t reg = atoi(argv[2]); 1171 | uint8_t data = atoi(argv[3]); 1172 | __write_reg(instance, reg, data); 1173 | } 1174 | else if (!rt_strcmp(argv[1], "init")) 1175 | { 1176 | char *name = argv[2]; 1177 | int pin = atoi(argv[3]); 1178 | struct nrf24_callback cb = {0}; 1179 | 1180 | if (instance != RT_NULL) 1181 | return; 1182 | 1183 | instance = nrf24_default_create(name, pin, NRF24_PIN_NONE, &cb, ROLE_PTX); 1184 | 1185 | if (instance) 1186 | rt_kprintf("OK\n"); 1187 | else 1188 | rt_kprintf("\nFAILED!\n"); 1189 | } 1190 | } 1191 | MSH_CMD_EXPORT(nrf24, nrf24l01); 1192 | 1193 | #endif // NRF24_USING_SHELL_CMD 1194 | 1195 | /** E DEBUG */ 1196 | -------------------------------------------------------------------------------- /src/nrf24l01.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019, sogwyms@gmail.com 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Change Logs: 7 | * Date Author Notes 8 | * 2019-05-23 sogwms the first version 9 | * 2020-02-02 sogwms refactor to object-oriented and make simplification and ... 10 | */ 11 | #ifndef __NRF24L01_H__ 12 | #define __NRF24L01_H__ 13 | 14 | #include "nrf24l01_port.h" 15 | 16 | #define NRF24_DEFAULT_PIPE NRF24_PIPE_0 17 | 18 | enum 19 | { 20 | NRF24_PIPE_NONE = 8, 21 | NRF24_PIPE_0 = 0, 22 | NRF24_PIPE_1, 23 | NRF24_PIPE_2, 24 | NRF24_PIPE_3, 25 | NRF24_PIPE_4, 26 | NRF24_PIPE_5, 27 | }; 28 | 29 | typedef enum 30 | { 31 | ROLE_NONE = 2, 32 | ROLE_PTX = 0, 33 | ROLE_PRX = 1, 34 | } nrf24_role_et; 35 | 36 | typedef enum 37 | { 38 | MODE_POWER_DOWN, 39 | MODE_STANDBY, 40 | MODE_TX, 41 | MODE_RX, 42 | } nrf24_mode_et; 43 | 44 | typedef enum 45 | { 46 | // CRC_NONE = 2, 47 | CRC_1_BYTE = 0, 48 | CRC_2_BYTE = 1, 49 | } nrf24_crc_et; 50 | 51 | typedef enum 52 | { 53 | RF_POWER_N18dBm = 0, 54 | RF_POWER_N12dBm = 0x1, 55 | RF_POWER_N6dBm = 0x2, 56 | RF_POWER_0dBm = 0x3, 57 | } nrf24_power_et; 58 | 59 | typedef enum 60 | { 61 | ADR_1Mbps = 0, 62 | ADR_2Mbps = 1, 63 | } nrf24_adr_et; 64 | 65 | /* User-oriented configuration */ 66 | struct nrf24_cfg 67 | { 68 | nrf24_role_et role; 69 | nrf24_power_et power; 70 | nrf24_crc_et crc; 71 | nrf24_adr_et adr; 72 | uint8_t channel :7; //range: 0 ~ 127 (frequency:) 73 | 74 | int _irq_pin; 75 | 76 | uint8_t txaddr[5]; 77 | 78 | struct { 79 | uint8_t bl_enabled; 80 | uint8_t addr[5]; 81 | } rxpipe0; 82 | 83 | struct { 84 | uint8_t bl_enabled; 85 | uint8_t addr[5]; 86 | } rxpipe1; 87 | 88 | struct { 89 | uint8_t bl_enabled; 90 | uint8_t addr; 91 | } rxpipe2; 92 | 93 | struct { 94 | uint8_t bl_enabled; 95 | uint8_t addr; 96 | } rxpipe3; 97 | 98 | struct { 99 | uint8_t bl_enabled; 100 | uint8_t addr; 101 | } rxpipe4; 102 | 103 | struct { 104 | uint8_t bl_enabled; 105 | uint8_t addr; 106 | } rxpipe5; 107 | }; 108 | 109 | typedef struct nrf24_cfg *nrf24_cfg_t; 110 | 111 | typedef struct nrf24 *nrf24_t; 112 | 113 | struct nrf24_callback 114 | { 115 | void (*rx_ind)(nrf24_t nrf24, uint8_t *data, uint8_t len, int pipe); 116 | void (*tx_done)(nrf24_t nrf24, int pipe); 117 | }; 118 | 119 | struct nrf24 120 | { 121 | struct hal_nrf24_port halport; 122 | struct nrf24_cfg cfg; 123 | struct nrf24_callback cb; 124 | 125 | struct { 126 | uint8_t activated_features :1; 127 | uint8_t using_irq :1; 128 | } flags; 129 | 130 | uint8_t status; 131 | 132 | rt_sem_t sem; // irq 133 | rt_sem_t send_sem; 134 | }; 135 | 136 | // int nrf24_update_txaddr(nrf24_t nrf24, uint8_t addr[5]); 137 | // int nrf24_update_rxaddr(nrf24_t nrf24, int pipe, uint8_t addr[5]); 138 | 139 | int nrf24_init(nrf24_t nrf24, char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, const nrf24_cfg_t cfg); 140 | nrf24_t nrf24_create(char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, const nrf24_cfg_t cfg); 141 | 142 | int nrf24_default_init(nrf24_t nrf24, char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, nrf24_role_et role); 143 | nrf24_t nrf24_default_create(char *spi_dev_name, int ce_pin, int irq_pin, const struct nrf24_callback *cb, nrf24_role_et role); 144 | 145 | void nrf24_enter_power_down_mode(nrf24_t nrf24); 146 | void nrf24_enter_power_up_mode(nrf24_t nrf24); 147 | 148 | int nrf24_fill_default_config_on(nrf24_cfg_t cfg); 149 | int nrf24_send_data(nrf24_t nrf24, uint8_t *data, uint8_t len, uint8_t pipe); 150 | int nrf24_run(nrf24_t nrf24); 151 | 152 | #endif // __NRF24L01_H__ 153 | -------------------------------------------------------------------------------- /src/nrf24l01_port.c: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019, sogwyms@gmail.com 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Change Logs: 7 | * Date Author Notes 8 | * 2019-05-23 sogwms the first version 9 | * 2020-02-02 sogwms refactor to object-oriented and add irq support 10 | */ 11 | 12 | #include 13 | 14 | #if defined(RTTHREAD_VERSION) && (RTTHREAD_VERSION >= RT_VERSION_CHECK(5, 0, 0)) 15 | #else 16 | #include "drv_gpio.h" 17 | #include "drv_spi.h" 18 | #endif 19 | 20 | #include "nrf24l01_port.h" 21 | 22 | #define DBG_SECTION_NAME "nrf24l01_port" 23 | #define DBG_LEVEL DBG_LOG 24 | #include 25 | 26 | static int send_then_recv(hal_nrf24_port_t halport, const uint8_t *tbuf, uint8_t tlen, uint8_t *rbuf, uint8_t rlen) 27 | { 28 | return rt_spi_send_then_recv(halport->dev, tbuf, tlen, rbuf, rlen); 29 | } 30 | 31 | static int send_then_send(hal_nrf24_port_t halport, const uint8_t *buf1, uint8_t len1, const uint8_t *buf2, uint8_t len2) 32 | { 33 | return rt_spi_send_then_send(halport->dev, buf1, len1, buf2, len2); 34 | } 35 | 36 | static int write(hal_nrf24_port_t halport, const uint8_t *buf, uint8_t len) 37 | { 38 | return rt_spi_send(halport->dev, buf, len); 39 | } 40 | 41 | static void set_ce(hal_nrf24_port_t halport) 42 | { 43 | rt_pin_write(halport->ce_pin, PIN_HIGH); 44 | } 45 | 46 | static void reset_ce(hal_nrf24_port_t halport) 47 | { 48 | rt_pin_write(halport->ce_pin, PIN_LOW); 49 | } 50 | 51 | static int read_irq_pin(hal_nrf24_port_t halport) 52 | { 53 | return rt_pin_read(halport->irq_pin); 54 | } 55 | 56 | static void hdr(void *args) 57 | { 58 | hal_nrf24_port_t halport = (hal_nrf24_port_t)args; 59 | halport->_irq_cb(halport); 60 | } 61 | 62 | const static struct hal_nrf24_port_ops g_hal_port_ops = { 63 | .send_then_recv = send_then_recv, 64 | .send_then_send = send_then_send, 65 | .write = write, 66 | .set_ce = set_ce, 67 | .reset_ce = reset_ce, 68 | .read_irq_pin = read_irq_pin, 69 | }; 70 | 71 | int hal_nrf24_port_init(hal_nrf24_port_t halport, char *spi_dev_name, int ce_pin, int irq_pin, void(*irq_callback)(hal_nrf24_port_t halport)) 72 | { 73 | struct rt_spi_device *dev; 74 | struct rt_spi_configuration cfg; 75 | 76 | RT_ASSERT(halport != RT_NULL); 77 | 78 | dev = (struct rt_spi_device *)rt_device_find(spi_dev_name); 79 | if (!dev) { 80 | LOG_E("Can't find device on %s\n", spi_dev_name); 81 | return RT_ERROR; 82 | } 83 | 84 | halport->dev = dev; 85 | halport->ce_pin = ce_pin; 86 | halport->irq_pin = irq_pin; 87 | halport->_irq_cb = irq_callback; 88 | halport->ops = &g_hal_port_ops; 89 | 90 | cfg.data_width = 8; 91 | cfg.max_hz = 8 * 1000 * 1000; 92 | cfg.mode = RT_SPI_MASTER | RT_SPI_MSB | RT_SPI_MODE_0; 93 | rt_spi_configure(dev, &cfg); 94 | 95 | rt_pin_mode(ce_pin, PIN_MODE_OUTPUT); 96 | reset_ce(halport); 97 | 98 | if(irq_pin != NRF24_PIN_NONE && irq_callback != RT_NULL) 99 | { 100 | rt_pin_mode(irq_pin, PIN_MODE_INPUT_PULLUP); 101 | rt_pin_attach_irq(irq_pin, PIN_IRQ_MODE_FALLING, hdr, halport); 102 | rt_pin_irq_enable(irq_pin, PIN_IRQ_ENABLE); 103 | } 104 | 105 | return RT_EOK; 106 | } 107 | 108 | hal_nrf24_port_t hal_nrf24_port_create(char *spi_dev_name, int ce_pin, int irq_pin, void(*irq_callback)(hal_nrf24_port_t halport)) 109 | { 110 | struct hal_nrf24_port *halport; 111 | 112 | halport = (struct hal_nrf24_port *)rt_malloc(sizeof(struct hal_nrf24_port)); 113 | if (halport == RT_NULL) 114 | { 115 | LOG_E("Failed to allocate memory!"); 116 | } 117 | else 118 | { 119 | if (hal_nrf24_port_init(halport, spi_dev_name, ce_pin, irq_pin, irq_callback) != RT_EOK) 120 | { 121 | rt_free(halport); 122 | halport = RT_NULL; 123 | } 124 | } 125 | 126 | return halport; 127 | } 128 | -------------------------------------------------------------------------------- /src/nrf24l01_port.h: -------------------------------------------------------------------------------- 1 | /* 2 | * Copyright (c) 2019, sogwyms@gmail.com 3 | * 4 | * SPDX-License-Identifier: Apache-2.0 5 | * 6 | * Change Logs: 7 | * Date Author Notes 8 | * 2019-05-23 sogwms the first version 9 | * 2020-02-02 sogwms refactor to object-oriented and add irq support 10 | */ 11 | #ifndef __NRF24L01_PORT_H__ 12 | #define __NRF24L01_PORT_H__ 13 | 14 | #include 15 | #include 16 | 17 | #define NRF24_PIN_NONE -1 18 | 19 | #define SUB_HALPORT_WIRTE(_nrf24, buf, len) _nrf24->halport.ops->write(&_nrf24->halport, buf, len) 20 | #define SUB_HALPORT_SEND_THEN_RECV(_nrf24, tbuf, tlen, rbuf, rlen) _nrf24->halport.ops->send_then_recv(&_nrf24->halport, tbuf, tlen, rbuf, rlen) 21 | #define SUB_HALPORT_SEND_THEN_SEND(_nrf24, buf1, len1, buf2, len2) _nrf24->halport.ops->send_then_send(&_nrf24->halport, buf1, len1, buf2, len2) 22 | #define SUB_HALPORT_RESET_CE(_nrf24) _nrf24->halport.ops->reset_ce(&_nrf24->halport) 23 | #define SUB_HALPORT_SET_CE(_nrf24) _nrf24->halport.ops->set_ce(&_nrf24->halport) 24 | 25 | #define NRF24_HALPORT_WRITE(buf, len) SUB_HALPORT_WIRTE(nrf24, buf, len) 26 | #define NRF24_HALPORT_SEND_THEN_RECV(tbuf, tlen, rbuf, rlen) SUB_HALPORT_SEND_THEN_RECV(nrf24, tbuf, tlen, rbuf, rlen) 27 | #define NRF24_HALPORT_SEND_THEN_SEND(buf1, len1, buf2, len2) SUB_HALPORT_SEND_THEN_SEND(nrf24, buf1, len1, buf2, len2) 28 | #define NRF24_HALPORT_RESET_CE() SUB_HALPORT_RESET_CE(nrf24) 29 | #define NRF24_HALPORT_SET_CE() SUB_HALPORT_SET_CE(nrf24) 30 | 31 | typedef struct hal_nrf24_port *hal_nrf24_port_t; 32 | 33 | struct hal_nrf24_port 34 | { 35 | const struct hal_nrf24_port_ops *ops; 36 | 37 | int ce_pin; 38 | int irq_pin; 39 | void(*_irq_cb)(struct hal_nrf24_port *halport); 40 | struct rt_spi_device *dev; 41 | }; 42 | 43 | struct hal_nrf24_port_ops 44 | { 45 | int (*send_then_recv)(struct hal_nrf24_port *halport, const uint8_t *tbuf, uint8_t tlen, uint8_t *rbuf, uint8_t rlen); 46 | int (*send_then_send)(struct hal_nrf24_port *halport, const uint8_t *buf1, uint8_t len1, const uint8_t *buf2, uint8_t len2); 47 | int (*write)(struct hal_nrf24_port *halport, const uint8_t *buf, uint8_t len); 48 | void (*set_ce)(struct hal_nrf24_port *halport); 49 | void (*reset_ce)(struct hal_nrf24_port *halport); 50 | 51 | int (*read_irq_pin)(struct hal_nrf24_port *halport); 52 | }; 53 | 54 | int hal_nrf24_port_init(hal_nrf24_port_t halport, char *spi_dev_name, int ce_pin, int irq_pin, void(*irq_callback)(hal_nrf24_port_t halport)); 55 | hal_nrf24_port_t hal_nrf24_port_create(char *spi_dev_name, int ce_pin, int irq_pin, void(*irq_callback)(hal_nrf24_port_t halport)); 56 | 57 | #endif // __NRF24L01_PORT_H__ 58 | --------------------------------------------------------------------------------