├── .github └── workflows │ └── trm.yml ├── .gitignore ├── Benchmark ├── Makefile ├── backup.rst ├── make.bat ├── source │ ├── 0_testbench.rst │ ├── 10_stress_ng.rst │ ├── 11_fio.rst │ ├── 12_redis.rst │ ├── 13_memoryreadlatency.rst │ ├── 14_dhrystone.rst │ ├── 1_spec.rst │ ├── 2_unixbench.rst │ ├── 3_coremark.rst │ ├── 4_stream.rst │ ├── 5_cache.rst │ ├── 6_core_core_latency.rst │ ├── 7_litmus.rst │ ├── 8_sysbench.rst │ ├── 9_ltp.rst │ ├── LMBench.png │ ├── SPEC.png │ ├── SPEC_CPU.png │ ├── SPECmetrics.png │ ├── Untitled Diagram.drawio │ ├── _static │ │ └── riscv.cfg │ ├── cache_bench.png │ ├── conf.py │ ├── core_core_latency.png │ ├── coremark.png │ ├── dhystone.png │ ├── index.rst │ ├── litmus.png │ ├── litmus_1.png │ ├── litmus_2.png │ ├── redis_benchmark.png │ ├── spec2006-install.png │ ├── stream.png │ ├── stream_alg.png │ ├── sysbench.png │ ├── test.css │ ├── test.md │ ├── testbenchmark.md │ └── unix_benchmark.png └── test.rst ├── LICENSE ├── README.md ├── README_cn.md ├── SG200X ├── 8051 │ ├── 8051_Core_Quick_Start_Guide_cn.md │ ├── 8051_Core_Quick_Start_Guide_en.md │ ├── d8051_db.pdf │ ├── imgs │ │ ├── 8051interrupt.jpeg │ │ ├── 8051interrupt_en.jpeg │ │ ├── 8051memIO.jpeg │ │ ├── 8051memmap.jpeg │ │ ├── memmap_modify.jpeg │ │ ├── rtc_domain_phi.jpeg │ │ ├── rtc_domain_phi_en.jpeg │ │ ├── rtc_int.jpeg │ │ └── sophpi_sfr.jpeg │ └── sg200x_interrupt.xlsx ├── .gitignore ├── Software_Developers_Manual │ ├── SG200x_Software_Developer's_Manual_cn.md │ └── SG200x_Software_Developer's_Manual_en.md └── TRM │ ├── build.sh │ ├── conf.py │ ├── contents │ ├── cn │ │ ├── audio │ │ │ ├── 0.index.rst │ │ │ ├── aiao.rst │ │ │ ├── aiao_registers_overview.table.rst │ │ │ ├── aiao_subsystem_registers_description.table.rst │ │ │ ├── audio_adc_registers_description.table.rst │ │ │ ├── audio_codec.rst │ │ │ ├── audio_dac_adc_registers_overview.table.rst │ │ │ ├── audio_dac_registers_description.table.rst │ │ │ ├── i2s_tdb_registers_overview.table.rst │ │ │ └── i2s_tdm_module_registers_description.table.rst │ │ ├── clock │ │ │ ├── 0.index.rst │ │ │ ├── clksource_preset_freq_div_param.table.rst │ │ │ ├── clock_tree.rst │ │ │ ├── div_configure.rst │ │ │ ├── div_crg_registers_description.table.rst │ │ │ ├── div_crg_registers_overview.table.rst │ │ │ ├── div_reg_description.rst │ │ │ ├── div_reg_overview.rst │ │ │ ├── function_block.rst │ │ │ ├── overview.rst │ │ │ ├── pll_configure.rst │ │ │ ├── pll_configure_fractional_params.table.rst │ │ │ ├── pll_configure_integer_params.table.rst │ │ │ ├── pll_configure_params.table.rst │ │ │ ├── pll_crg_registers_overview.table.rst │ │ │ ├── pll_g2_registers_description.table.rst │ │ │ ├── pll_g6_registers_description.table.rst │ │ │ ├── pll_reg_description.rst │ │ │ └── pll_reg_overview.rst │ │ ├── ddr │ │ │ ├── 0.index.rst │ │ │ ├── axi_registers.rst │ │ │ ├── axi_registers_description_0x0800_4000.table.rst │ │ │ ├── axi_registers_description_0x0800_8000.table.rst │ │ │ ├── axi_registers_overview.table.rst │ │ │ ├── ddr2_vs_ddr3.table.rst │ │ │ ├── ddr_command_truth_table.table.rst │ │ │ ├── ddrc_registers.rst │ │ │ ├── ddrc_registers_description.table.rst │ │ │ ├── ddrc_registers_overview.table.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ └── working_method.rst │ │ ├── disclaimer.rst │ │ ├── dma │ │ │ ├── 0.index.rst │ │ │ ├── dmac_access_space_type.table.rst │ │ │ ├── dmac_registers.table.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ ├── registers.rst │ │ │ └── working_method.rst │ │ ├── initialization │ │ │ └── 0.index.rst │ │ ├── mcu │ │ │ ├── 0.index.rst │ │ │ ├── 8051_interrupts.table.rst │ │ │ ├── features.rst │ │ │ ├── overview.rst │ │ │ ├── registers_description.rst │ │ │ ├── registers_overview.rst │ │ │ └── working_method.rst │ │ ├── network │ │ │ ├── 0.index.rst │ │ │ ├── eth_mac.rst │ │ │ ├── eth_phy.rst │ │ │ ├── gmac_registers_description.table.rst │ │ │ └── gmac_registers_overview.table.rst │ │ ├── peripherals │ │ │ ├── 0.index.rst │ │ │ ├── gpio.rst │ │ │ ├── gpio_registers_description.table.rst │ │ │ ├── i2c.rst │ │ │ ├── i2c_registers_description.table.rst │ │ │ ├── i2c_registers_overview.table.rst │ │ │ ├── irrx.rst │ │ │ ├── irrx_registers_description.table.rst │ │ │ ├── keyscan.rst │ │ │ ├── keyscan_registers_description.table.rst │ │ │ ├── pwm.rst │ │ │ ├── pwm_registers_overview.table.rst │ │ │ ├── pwn_registers_description.table.rst │ │ │ ├── saradc.rst │ │ │ ├── saradc_registers_description.table.rst │ │ │ ├── sdmmc.rst │ │ │ ├── sdmmc_register_description.table.rst │ │ │ ├── sdmmc_register_overview.table.rst │ │ │ ├── spi.rst │ │ │ ├── spi_registers_description.table.rst │ │ │ ├── spi_registers_overview.table.rst │ │ │ ├── temperature.rst │ │ │ ├── temperature_interrupt_description.table.rst │ │ │ ├── temperature_registers_description.table.rst │ │ │ ├── temperature_registers_overview.table.rst │ │ │ ├── uart.rst │ │ │ ├── uart_registers_description.table.rst │ │ │ ├── uart_registers_overview.table.rst │ │ │ ├── usb.rst │ │ │ ├── usb_device_registers_description.table.rst │ │ │ ├── usb_host_registers_description.table.rst │ │ │ ├── usb_usbc_registers_description.table.rst │ │ │ ├── wiegand.rst │ │ │ └── wiegand_registers_description.table.rst │ │ ├── pinmux-pinctrl │ │ │ └── 0.index.rst │ │ ├── power │ │ │ ├── 0.index.rst │ │ │ ├── clock_control.rst │ │ │ ├── ddr_powerctrl.rst │ │ │ ├── overview.rst │ │ │ └── voltage_adjustment.rst │ │ ├── reset │ │ │ ├── 0.index.rst │ │ │ ├── overview.rst │ │ │ ├── reset_control.rst │ │ │ ├── reset_registers.rst │ │ │ ├── reset_registers_describe.table.rst │ │ │ └── reset_registers_overview.table.rst │ │ ├── rtc │ │ │ ├── 0.index.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ ├── registers_description.rst │ │ │ ├── registers_overview.rst │ │ │ ├── rtc_core_reg_overview.table.rst │ │ │ ├── rtc_ctrl_reg_overview.table.rst │ │ │ ├── rtc_macro_reg_overview.table.rst │ │ │ ├── rtc_registers_description.table.rst │ │ │ └── working_method.rst │ │ ├── security │ │ │ ├── 0.index.rst │ │ │ ├── cryptodma.rst │ │ │ ├── cryptodma_registers_description.table.rst │ │ │ ├── cryptodma_registers_overview.table.rst │ │ │ ├── efuse.rst │ │ │ ├── firewall.rst │ │ │ ├── firewall_i2c_query_interface.table.rst │ │ │ ├── trng.rst │ │ │ ├── trng_registers_description.table.rst │ │ │ └── trng_registers_overview.table.rst │ │ ├── spi_nandflash │ │ │ ├── 0.index.rst │ │ │ ├── data_structure.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ ├── registers_descriptions.rst │ │ │ ├── registers_overview.rst │ │ │ ├── spi_nandflash_registers_description.table.rst │ │ │ ├── spi_nandflash_registers_overview.table.rst │ │ │ └── working_method.rst │ │ ├── spi_norflash │ │ │ ├── 0.index.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ ├── registers_descriptions.rst │ │ │ ├── registers_overview.rst │ │ │ ├── spi_norflash_registers_description.table.rst │ │ │ ├── spi_norflash_registers_overview.table.rst │ │ │ └── working_method.rst │ │ ├── system-architecture │ │ │ ├── 0.index.rst │ │ │ ├── interrupts.rst │ │ │ ├── interrupts.table.rst │ │ │ ├── memorymap.rst │ │ │ ├── memorymap_sg2000.table.rst │ │ │ ├── memorymap_sg2002.table.rst │ │ │ ├── package_pin.rst │ │ │ ├── package_pin_sg2000.table.rst │ │ │ ├── package_pin_sg2002.table.rst │ │ │ └── processors.rst │ │ ├── system-control │ │ │ ├── 0.index.rst │ │ │ ├── function_description.rst │ │ │ ├── overview.rst │ │ │ ├── registers.rst │ │ │ ├── system_control_registers_description.table.rst │ │ │ ├── system_control_registers_overview.table.rst │ │ │ └── system_dma_channel_mapping.table.rst │ │ ├── system-overview │ │ │ ├── 0.index.rst │ │ │ ├── features.rst │ │ │ ├── features_sg2000.rst │ │ │ ├── introduction.rst │ │ │ ├── introduction_sg2000.rst │ │ │ ├── system-block-diagram.rst │ │ │ └── system-block-diagram_sg2000.rst │ │ ├── timer │ │ │ ├── 0.index.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ ├── registers_description.rst │ │ │ ├── registers_overview.rst │ │ │ ├── timer_registers_description.table.rst │ │ │ ├── timer_registers_overview.table.rst │ │ │ └── working_method.rst │ │ ├── video │ │ │ ├── 0.index.rst │ │ │ ├── mipi_rx.rst │ │ │ ├── mipi_rx_csi_registers_description.table.rst │ │ │ ├── mipi_rx_phy_registers_description_0x0a0d0000.table.rst │ │ │ ├── mipi_rx_phy_registers_description_0x0a0d0300.table.rst │ │ │ ├── mipi_rx_phy_registers_description_0x0a0d0600.table.rst │ │ │ ├── mipi_rx_phy_registers_overview.table.rst │ │ │ ├── mipi_rx_sub_lvds_registers_description.table.rst │ │ │ ├── mipi_tx.rst │ │ │ ├── mipi_tx_control_registers_description.table.rst │ │ │ ├── mipi_tx_control_registers_overview.table.rst │ │ │ ├── mipi_tx_phy_registers_description.table.rst │ │ │ ├── mipi_tx_phy_registers_overview.table.rst │ │ │ ├── vdp.rst │ │ │ ├── vdp_disp_registers_description.table.rst │ │ │ ├── vdp_disp_registers_overview.table.rst │ │ │ ├── vdp_osd_registers_description.table.rst │ │ │ ├── vdp_osd_registers_overview.table.rst │ │ │ ├── vi.rst │ │ │ ├── vi_registers_description.table.rst │ │ │ └── vi_registers_overview.table.rst │ │ └── watchdog │ │ │ ├── 0.index.rst │ │ │ ├── features.rst │ │ │ ├── functionalities.rst │ │ │ ├── overview.rst │ │ │ ├── registers_description.rst │ │ │ ├── registers_overview.rst │ │ │ ├── watchdog_register_overview.table.rst │ │ │ ├── watchdog_registers_description.table.rst │ │ │ └── working_method.rst │ └── en │ │ ├── audio │ │ ├── 0.index.rst │ │ ├── aiao.rst │ │ └── audio_codec.rst │ │ ├── clock │ │ ├── 0.index.rst │ │ ├── clock_tree.rst │ │ ├── div_configure.rst │ │ ├── div_reg_description.rst │ │ ├── div_reg_overview.rst │ │ ├── function_block.rst │ │ ├── overview.rst │ │ ├── pll_configure.rst │ │ ├── pll_reg_description.rst │ │ └── pll_reg_overview.rst │ │ ├── ddr │ │ ├── 0.index.rst │ │ ├── axi_registers.rst │ │ ├── ddrc_registers.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ └── working_method.rst │ │ ├── disclaimer.rst │ │ ├── dma │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ ├── registers.rst │ │ └── working_method.rst │ │ ├── initialization │ │ └── 0.index.rst │ │ ├── mcu │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── overview.rst │ │ ├── registers_description.rst │ │ ├── registers_overview.rst │ │ └── working_method.rst │ │ ├── network │ │ ├── 0.index.rst │ │ ├── eth_mac.rst │ │ └── eth_phy.rst │ │ ├── peripherals │ │ ├── 0.index.rst │ │ ├── gpio.rst │ │ ├── i2c.rst │ │ ├── irrx.rst │ │ ├── keyscan.rst │ │ ├── pwm.rst │ │ ├── saradc.rst │ │ ├── sdmmc.rst │ │ ├── spi.rst │ │ ├── temperature.rst │ │ ├── uart.rst │ │ ├── usb.rst │ │ └── wiegand.rst │ │ ├── pinmux-pinctrl │ │ └── 0.index.rst │ │ ├── power │ │ ├── 0.index.rst │ │ ├── clock_control.rst │ │ ├── ddr_powerctrl.rst │ │ ├── overview.rst │ │ └── voltage_adjustment.rst │ │ ├── reset │ │ ├── 0.index.rst │ │ ├── overview.rst │ │ ├── reset_control.rst │ │ └── reset_registers.rst │ │ ├── rtc │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ ├── registers_description.rst │ │ ├── registers_overview.rst │ │ └── working_method.rst │ │ ├── security │ │ ├── 0.index.rst │ │ ├── cryptodma.rst │ │ ├── efuse.rst │ │ ├── firewall.rst │ │ └── trng.rst │ │ ├── spi_nandflash │ │ ├── 0.index.rst │ │ ├── data_structure.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ ├── registers_descriptions.rst │ │ ├── registers_overview.rst │ │ └── working_method.rst │ │ ├── spi_norflash │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ ├── registers_descriptions.rst │ │ ├── registers_overview.rst │ │ └── working_method.rst │ │ ├── system-architecture │ │ ├── 0.index.rst │ │ ├── interrupts.rst │ │ ├── memorymap.rst │ │ ├── package_pin.rst │ │ └── processors.rst │ │ ├── system-control │ │ ├── 0.index.rst │ │ ├── function_description.rst │ │ ├── overview.rst │ │ └── registers.rst │ │ ├── system-overview │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── features_sg2000.rst │ │ ├── introduction.rst │ │ ├── introduction_sg2000.rst │ │ ├── system-block-diagram.rst │ │ └── system-block-diagram_sg2000.rst │ │ ├── timer │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ ├── registers_description.rst │ │ ├── registers_overview.rst │ │ └── working_method.rst │ │ ├── video │ │ ├── 0.index.rst │ │ ├── mipi_rx.rst │ │ ├── mipi_tx.rst │ │ ├── vdp.rst │ │ └── vi.rst │ │ └── watchdog │ │ ├── 0.index.rst │ │ ├── features.rst │ │ ├── functionalities.rst │ │ ├── overview.rst │ │ ├── registers_description.rst │ │ ├── registers_overview.rst │ │ └── working_method.rst │ ├── doc │ ├── design.md │ └── design_conditional_sg200x.md │ ├── media │ ├── SOPHON-LOGO-orginal.png │ ├── SOPHON-LOGO.png │ ├── image1.png │ ├── image10.png │ ├── image100.png │ ├── image101.png │ ├── image102.png │ ├── image103.png │ ├── image104.png │ ├── image105.png │ ├── image106.png │ ├── image107.png │ ├── image108.png │ ├── image109.png │ ├── image11.png │ ├── image110.png │ ├── image111.png │ ├── image112.png │ ├── image113.png │ ├── image114.png │ ├── image115.png │ ├── image116.png │ ├── image117.png │ ├── image118.png │ ├── image119.png │ ├── image12.png │ ├── image120.png │ ├── image121.png │ ├── image122.png │ ├── image123.png │ ├── image124.png │ ├── image125.png │ ├── image126.png │ ├── image127.png │ ├── image128.png │ ├── image129.png │ ├── image13.png │ ├── image130.png │ ├── image131.png │ ├── image132.png │ ├── image133.png │ ├── image134.png │ ├── image135.png │ ├── image136.png │ ├── image137.png │ ├── image138.png │ ├── image139.png │ ├── image14.png │ ├── image140.png │ ├── image141.png │ ├── image142.png │ ├── image143.png │ ├── image144.png │ ├── image145.png │ ├── image146.png │ ├── image147.png │ ├── image15.png │ ├── image16.png │ ├── image17.png │ ├── image18.png │ ├── image19.png │ ├── image1_sg2000.png │ ├── image2.png │ ├── image20.png │ ├── image21.png │ ├── image22.png │ ├── image23.png │ ├── image24.png │ ├── image25.png │ ├── image26.png │ ├── image27.png │ ├── image28.png │ ├── image29.png │ ├── image2_sg2000.png │ ├── image3.png │ ├── image30.png │ ├── image31.png │ ├── image32.png │ ├── image33.png │ ├── image34.png │ ├── image35.png │ ├── image36.png │ ├── image37.png │ ├── image38.png │ ├── image39.png │ ├── image3_sg2000.png │ ├── image4.png │ ├── image40.png │ ├── image41.png │ ├── image42.png │ ├── image43.png │ ├── image44.png │ ├── image45.png │ ├── image46.png │ ├── image47.png │ ├── image48.png │ ├── image49.png │ ├── image4_sg2000.png │ ├── image5.png │ ├── image50.png │ ├── image51.png │ ├── image52.png │ ├── image53.png │ ├── image54.png │ ├── image55.png │ ├── image56.png │ ├── image57.png │ ├── image58.png │ ├── image59.png │ ├── image5_2_sg2000.png │ ├── image5_sg2000.png │ ├── image6.png │ ├── image60.png │ ├── image61.png │ ├── image62.png │ ├── image63.png │ ├── image64.png │ ├── image65.png │ ├── image66.png │ ├── image67.png │ ├── image68.png │ ├── image69.png │ ├── image7.png │ ├── image70.png │ ├── image71.png │ ├── image72.png │ ├── image73.png │ ├── image74.png │ ├── image75.png │ ├── image76.png │ ├── image77.png │ ├── image78.png │ ├── image79.png │ ├── image8.png │ ├── image80.png │ ├── image81.png │ ├── image82.png │ ├── image83.png │ ├── image84.png │ ├── image85.png │ ├── image86.png │ ├── image87.png │ ├── image88.png │ ├── image89.png │ ├── image9.png │ ├── image90.png │ ├── image91.png │ ├── image92.png │ ├── image93.png │ ├── image94.png │ ├── image95.png │ ├── image96.png │ ├── image97.png │ ├── image98.png │ └── image99.png │ ├── sg2000_cn │ ├── .gitignore │ ├── Makefile │ ├── make.bat │ └── source │ │ ├── conf.py │ │ ├── contents │ │ └── index.rst │ ├── sg2000_en │ ├── .gitignore │ ├── Makefile │ ├── make.bat │ └── source │ │ ├── conf.py │ │ ├── contents │ │ ├── contents-share │ │ └── index.rst │ ├── sg2002_cn │ ├── .gitignore │ ├── Makefile │ ├── make.bat │ └── source │ │ ├── conf.py │ │ ├── contents │ │ └── index.rst │ └── sg2002_en │ ├── .gitignore │ ├── Makefile │ ├── make.bat │ └── source │ ├── conf.py │ ├── contents │ ├── contents-share │ └── index.rst ├── SG2042 ├── .gitignore ├── HowTo │ ├── A simple way to install ubuntu on SG2042 EVB.rst │ ├── Configuration Info in INI file.rst │ ├── Create Bootable Disk Using Prebuilt Image.rst │ ├── FAQ.rst │ ├── How to Adapt Anolis OS on SG2042 EVB.rst │ ├── How to adjust CPU operating frequency.rst │ ├── How to build SG2042 bsp.rst │ ├── How to build and config grub2.rst │ ├── How to remotely create a system disk for SG 2042 server.rst │ ├── How to update pcie switch config image.rst │ ├── How to use perf on SG2042.rst │ ├── Setup Local Yum Repository.rst │ ├── bootflow.rst │ └── figures │ │ └── bootflow.png ├── T-Head │ └── XuanTie-C910-C920-UserManual.pdf └── TRM │ ├── .gitignore │ ├── Makefile │ ├── README.md │ ├── make.bat │ └── source │ ├── GPIO.rst │ ├── I2C.rst │ ├── LP.rst │ ├── LPC.rst │ ├── PWM.rst │ ├── Power-domain.rst │ ├── Reset.rst │ ├── SPI-flash.rst │ ├── SPI.rst │ ├── abstract.rst │ ├── clock-reg.rst │ ├── clock.rst │ ├── conf.py │ ├── default-clock-frequency.rst │ ├── digit-pin-list.rst │ ├── digital-pin-function.rst │ ├── index.rst │ ├── interrupt.rst │ ├── mmap.rst │ ├── pic │ ├── An-example-of-generating-a-PWM-wave.png │ ├── An-example-of-pulse-detection.png │ ├── Connection-Overview.png │ ├── DW_apb-and-Slave-Data-Widths.png │ ├── Fabric-Auto-Clock-Gating.png │ ├── Interrupt-Scheme.png │ ├── The-effect-of-registers-on-PWM-waves.png │ ├── The-effect-of-registers-on-Pulse-Detection.png │ ├── The-microarchitecture-of-pwmx4.png │ ├── The-microarchitecture-of-the-PWM-generator.png │ ├── The-microarchitecture-of-the-pulse-detector.png │ ├── The-operation-of-the-glitch-filter.png │ ├── The-role-of-Glitch-Filter.png │ ├── clock-gate.png │ ├── clock-tree.png │ ├── image2021.png │ ├── mesh.png │ ├── pll-seq.png │ ├── pll.png │ ├── pwmx4-Overview.png │ ├── spi-flash-fmlen10.png │ ├── spi-flash-fmlen6.png │ └── wdt_reset.png │ ├── pinmux-reg.rst │ ├── pinmux.rst │ ├── system-control.rst │ ├── system.rst │ └── uart.rst └── SG2044 └── HowTo ├── A Simple Method to Install Ubuntu Image on SG2044 EVB.rst ├── BIOS SetUp.rst ├── Configuraton Info in INI file.rst ├── How to Boot from SPI Nor Flash.rst ├── How to Build SG2044 BSP.rst └── SG2044 Boot Flow.rst /.github/workflows/trm.yml: -------------------------------------------------------------------------------- 1 | name: build-trm 2 | 3 | on: 4 | push: 5 | schedule: 6 | - cron: "0 2 * * *" 7 | pull_request: 8 | workflow_dispatch: 9 | 10 | jobs: 11 | build-trm: 12 | runs-on: ubuntu-22.04 13 | steps: 14 | - uses: actions/checkout@v4 15 | 16 | - name: "Prepare" 17 | run: | 18 | sudo apt update 19 | sudo apt install -y python3-sphinx texlive-full texlive-xetex texlive-latex-recommended texlive-latex-extra latexmk 20 | mkdir -p ${GITHUB_WORKSPACE}/artifacts/ 21 | 22 | - name: "Compile TRM for SG200X" 23 | run: | 24 | cd SG200X/TRM && bash build.sh 25 | cp -av out/*.pdf ${GITHUB_WORKSPACE}/artifacts/ 26 | 27 | - name: "Compile TRM for SG2042" 28 | run: | 29 | build_tiemstamp=$(date "+%Y%m%d%H%M") 30 | cd SG2042/TRM && make latexpdf 31 | cp -av build/latex/sg2042technicalreferencemanual.pdf \ 32 | ${GITHUB_WORKSPACE}/artifacts/SG2042TechnicalReferenceManual_${build_tiemstamp}.pdf 33 | 34 | - name: "Upload Artifact" 35 | uses: actions/upload-artifact@v4 36 | with: 37 | name: TechnicalReferenceManual 38 | path: artifacts/*.pdf 39 | retention-days: 60 40 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | .DS_Store 3 | ._.DS_Store 4 | -------------------------------------------------------------------------------- /Benchmark/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | 22 | pdf: latex 23 | @cd $(BUILDDIR)/latex && xelatex $(module_name).tex 24 | @cd $(BUILDDIR)/latex && xelatex $(module_name).tex 25 | @mv $(BUILDDIR)/latex/$(module_name).pdf $(BUILDDIR)/"${pdf_name}" && rm -rf $(BUILDDIR)/latex 26 | 27 | clean: 28 | @rm -rf $(BUILDDIR) 29 | -------------------------------------------------------------------------------- /Benchmark/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /Benchmark/source/10_stress_ng.rst: -------------------------------------------------------------------------------- 1 | stress-ng 2 | ------------------ 3 | 4 | stress-ng测试工具介绍 5 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 6 | 7 | 参考(https://wiki.sophgo.com/display/~zhaohui.yan/Stress-ng) 8 | ``stress-ng`` 是一个强大的工具，用于加载和压力测试系统资源，包括处理器、内存、磁盘、输入/输出设备和网络。 9 | 这个工具能够帮助识别硬件和软件配置中的潜在问题，也可以用于性能评估、系统监控和自动化测试环境中。 10 | 11 | stress-ng工具使用方法 12 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 13 | 14 | 详细步骤 15 | ^^^^^^^^^^^^^^^^^ 16 | 17 | .. code:: bash 18 | 19 | sudo apt-get install stress-ng #安装压力测试工具 20 | stress-ng --cpu 4 --timeout 60 #CPU压力测试,启动4个CPU,持续60s的压力测试 21 | stress-ng --vm 2 --vm-bytes 1G --timeout 60 #启动2个虚拟内存压力测试,分别分配1GB的内存,持续60秒。 22 | 23 | 运行结果示例 24 | ^^^^^^^^^^^^^^^^^ 25 | 26 | stress-ng测试结果 27 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 28 | 29 | 实际压力测试结果: 30 | 31 | ====== ======================== ======== 32 | 压测项 运行命令 测试结果 33 | ====== ======================== ======== 34 | CPU stress-ng -cpu 64 -t 30m PASS 35 | VM stress-ng -vm 64 -t 30m PASS 36 | ====== ======================== ======== -------------------------------------------------------------------------------- /Benchmark/source/11_fio.rst: -------------------------------------------------------------------------------- 1 | fio 2 | ------------------ 3 | 4 | fio测试工具介绍 5 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 6 | 7 | ``fio`` 主要用来对磁盘进行压力测试和性能验证,可以产生许多线程或进程来执行用户特定类型的I/O操作,通过编写作业文件或者直接命令去执行测试动作. 8 | 9 | fio工具使用方法 10 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 11 | 12 | 详细步骤 13 | ^^^^^^^^^^^^^^^^^ 14 | 15 | .. code:: bash 16 | 17 | sudo apt-get install fio #安装 I/O 性能测试工具 18 | 19 | - 读 20 | 21 | .. code:: bash 22 | 23 | sudo fio -filename=/dev/nvme0n1 -direct=1 -iodepth 1 -thread -rw=read -ioengine=psync -bs=1M -size=10G -numjobs=64 -runtime=60 -group_reporting -name=nvme 24 | 25 | - 写 26 | 27 | .. code:: bash 28 | 29 | sudo fio -filename=/dev/nvme0n1 -direct=1 -iodepth 1 -thread -rw=wirte -ioengine=psync -bs=1M -size=10G -numjobs=64 -runtime=60 -group_reporting -name=nvme 30 | 31 | 运行结果示例 32 | ^^^^^^^^^^^^^^^^^ 33 | 34 | fio测试结果 35 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> -------------------------------------------------------------------------------- /Benchmark/source/13_memoryreadlatency.rst: -------------------------------------------------------------------------------- 1 | LMBench 2 | ------------------ 3 | 4 | LMBench工具介绍 5 | >>>>>>>>>>>>>>>>>>>>>>> 6 | 7 | ``LMBench`` 是一个用于测试unix系统cache延迟的工具，通过该工具可以测试出不同级Cache的延时。 8 | 9 | LMBench工具使用方法 10 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 11 | 12 | 详细步骤 13 | ^^^^^^^^^^^^^^^^ 14 | 15 | .. code:: bash 16 | 17 | git clone https://github.com/sophgo/lmbench.git 18 | 19 | # 安装依赖 20 | # ubuntu 21 | sudo apt-get install gcc libtirpc-dev 22 | # fedora 23 | sudo yum install gcc libtirpc-devel 24 | # openEuler 25 | sudo dnf install libtirpc-devel 26 | 27 | cd lmbench 28 | make 29 | 30 | # 运行测试命令 31 | # 测试总长度为256MB，每个step为1024字节（1KB） 32 | ./bin/lat_mem_rd 256 1024 33 | 34 | 命令运行结束后，后输出两列数据，其中第一列为测试长度，单位为MB，第二列为latency，单位为ns。 35 | 36 | 将输出的结果复制到表格中进行处理，其中： 37 | 38 | - 64KB 之前的数据，舍去异常值，取个平均，为 L1 的 latency。 39 | - 1MB 到 64 KB 之间的数据，舍去异常值，取个平均，为 L2 的latency。 40 | - 64MB 到 1MB 之前的数据，舍去异常值，取个平均，为 L3 的latency。 41 | 42 | 结果示例 43 | ^^^^^^^^^^^^^^^^ 44 | 45 | .. figure:: LMBench.png 46 | :alt: LMBench 47 | :scale: 80 48 | :align: center 49 | 50 | LMBench结果 51 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 52 | 53 | 测试环境: 54 | 55 | - ``SG2044 EVB`` 56 | - ``dual-rank 128GB DDR`` 57 | - ``OpenEuler24.03 (LTS) Linux6.12.6`` 58 | - ``64 core C920@2.8GHz`` 59 | 60 | +-----------------+--------------------+ 61 | | cache level | cache latency(ns) | 62 | +=================+====================+ 63 | | L1 | 1.072 | 64 | +-----------------+--------------------+ 65 | | L2 | 5.55 | 66 | +-----------------+--------------------+ 67 | | L3 | 14.43 | 68 | +-----------------+--------------------+ -------------------------------------------------------------------------------- /Benchmark/source/9_ltp.rst: -------------------------------------------------------------------------------- 1 | ltp 2 | ------------------ 3 | 4 | ltp测试工具介绍 5 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 6 | 7 | 参考(https://blog.csdn.net/a1317480843/article/details/80006028) 8 | ``LTP`` 套件是由 Linux Test Project 所开发的一套系统测试套件。 9 | 它基于系统资源的利用率统计开发了一个测试的组合,为系统提供足够的压力。 10 | 通过压力测试来判断系统的稳定性和可靠性。压力测试是一种破坏性的测试,即系统在非正常的、超负荷的条件下的运行情况。 11 | 用来评估在超越最大负载的情况下系统将如何运行,是系统在正常的情况下对某种负载强度的承受能力的考验 。 12 | 13 | ltp测试步骤 14 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> 15 | 16 | 详细步骤 17 | ^^^^^^^^^^^^^^^^^ 18 | 19 | .. code:: bash 20 | 21 | sudo apt-get install build-essential git #安装必要的依赖项 22 | git clone https://github.com/linux-test-project/ltp.git 23 | cd ltp 24 | make 25 | sudo make install 26 | cd /opt/ltp 27 | sudo ./runltp 28 | 29 | 运行结果示例 30 | ^^^^^^^^^^^^^^^^^ 31 | 32 | ltp测试结果 33 | >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> -------------------------------------------------------------------------------- /Benchmark/source/LMBench.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sophgo/sophgo-doc/5e9555e2102fe82ee1a552fa8e07963913bce7ac/Benchmark/source/LMBench.png -------------------------------------------------------------------------------- /Benchmark/source/SPEC.png: -------------------------------------------------------------------------------- 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======== 33 | sg2042 intspeed 64 1.55 34 | sg2042 intrate 128cpoy 45.5 35 | sg2042 intrate 64cpoy 45.6 36 | sg2042 intrate 32cpoy 28.5 37 | sg2042 intrate 1cpoy 1.10 38 | sg2042 fpspeed 64 12.9 39 | sg2042 fprate 128copy 35.5 40 | sg2042 fprate 64copy 42.1 41 | sg2042 fprate 32copy 29.4 42 | sg2042 fprate 1copy 1.31 43 | ====================== ======== 44 | 45 | 1.2 kunpeng920 46 | ^^^^^^^^^^^^^^ 47 | 48 | ========================== ======== 49 | 测试项目 测试结果 50 | ========================== ======== 51 | kunpeng920 intrate 128copy 264 52 | kunpeng920 intrate 128copy 234 53 | kunpeng920 intrate 64copy 152 54 | kunpeng920 fprate 64copy 148 55 | ========================== ======== 56 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | BSD 2-Clause License 2 | 3 | Copyright (c) 2023, Sophgo Technologies 4 | 5 | Redistribution and use in source and binary forms, with or without 6 | modification, are permitted provided that the following conditions are met: 7 | 8 | 1. Redistributions of source code must retain the above copyright notice, this 9 | list of conditions and the following disclaimer. 10 | 11 | 2. Redistributions in binary form must reproduce the above copyright notice, 12 | this list of conditions and the following disclaimer in the documentation 13 | and/or other materials provided with the distribution. 14 | 15 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 18 | DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 19 | FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 | DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 21 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 22 | CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 | OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 24 | OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # Sophgo-doc 2 | 3 | This repository provides software-related support documentation for [SOPHGO](https://www.sophgo.com/) SG2042 and SG200X series of edge computing processors. 4 | 5 | ## Hardware Support 6 | 7 | - [Hardware document release](https://github.com/sophgo/sophgo-hardware/tree/master) 8 | 9 | ## SOC SPEC 10 | 11 | | Chip Name | Web | 12 | | :-------- | :----------------------------------------------- | 13 | | SG2042 | https://sophon.cn/product/introduce/sg2042.html | 14 | | CV1800B | https://sophon.cn/product/introduce/cv180xB.html | 15 | 16 | ## About Contributions 17 | 18 | We thank all developers for using our processors. If you encounter any issues or have any suggestions, please submit them via Issues. We welcome all forms of contributions, including improvements to documentation, bug fixes, the addition of new features and etc. Direct involvement in the development and maintenance of the project is highly appreciated as it helps us continuously improve. With your help, we look forward to developing this project into an even more complete and user-friendly resource library. 19 | 20 | ## Forum 21 | 22 | - [Technical Discussion - Open Source Hardware sophpi](https://developer.sophgo.com/forum/index/25/51.html) 23 | -------------------------------------------------------------------------------- /README_cn.md: -------------------------------------------------------------------------------- 1 | # Sophgo-doc 2 | 3 | 本仓库提供[算能科技](https://www.sophgo.com/)端测处理器 SG200X 系列和 SG2042 处理器的软件相关支持文档。 4 | 5 | ## 硬件支持 6 | 7 | - [硬件资料仓库](https://github.com/sophgo/sophgo-hardware/tree/master) 8 | 9 | ## 处理器规格 10 | 11 | | Chip Name | Web | 12 | | :-------- | :----------------------------------------------- | 13 | | SG2042 | https://sophon.cn/product/introduce/sg2042.html | 14 | | CV1800B | https://sophon.cn/product/introduce/cv180xB.html | 15 | 16 | ## 关于贡献 17 | 18 | 感谢各位开发者使用 SG 处理器，如果您在查阅文档的过程中遇到问题或有任何的建议，请通过 Issues 提交。我们欢迎所有形式的贡献，包括文档改进、bug 修复、新特性添加等等，直接参与到项目的开发和维护中，帮助我们不断改进。我们期待在您的帮助下，将本项目发展成为更加完善、易于使用的资源库。 19 | 20 | ## 技术论坛 21 | 22 | - [技术讨论 - 开源硬件 sophpi](https://developer.sophgo.com/forum/index/25/51.html) 23 | -------------------------------------------------------------------------------- /SG200X/.gitignore: -------------------------------------------------------------------------------- 1 | out/ 2 | .vscode/ 3 | -------------------------------------------------------------------------------- /SG200X/8051/d8051_db.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sophgo/sophgo-doc/5e9555e2102fe82ee1a552fa8e07963913bce7ac/SG200X/8051/d8051_db.pdf -------------------------------------------------------------------------------- /SG200X/8051/imgs/8051interrupt.jpeg: -------------------------------------------------------------------------------- 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https://raw.githubusercontent.com/sophgo/sophgo-doc/5e9555e2102fe82ee1a552fa8e07963913bce7ac/SG200X/8051/sg200x_interrupt.xlsx -------------------------------------------------------------------------------- /SG200X/TRM/build.sh: -------------------------------------------------------------------------------- 1 | #! /bin/bash 2 | 3 | set -e 4 | 5 | ROOT=$(pwd) 6 | 7 | document_list=( 8 | sg2000_cn 9 | sg2000_en 10 | sg2002_cn 11 | sg2002_en 12 | ) 13 | 14 | build_html() { 15 | make -C $1 clean 16 | 17 | make -C $1 html 18 | 19 | mkdir -p out/$1 20 | mv $1/build/html ${ROOT}/out/$1 21 | 22 | make -C $1 clean 23 | } 24 | 25 | build_pdf() { 26 | make -C $1 clean 27 | 28 | make -C $1 pdf 29 | 30 | mv $1/build/*.pdf ${ROOT}/out/ 31 | 32 | make -C $1 clean 33 | } 34 | 35 | build() { 36 | build_pdf $1 37 | # build_html $1 38 | } 39 | 40 | 41 | # Start executing ... 42 | rm -rf ${ROOT}/out 43 | mkdir ${ROOT}/out 44 | 45 | if [ -n "$1" ]; then 46 | build $1 47 | exit 48 | fi 49 | 50 | for dir_name in ${document_list[*]} 51 | do 52 | build $dir_name 53 | done 54 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/audio/0.index.rst: -------------------------------------------------------------------------------- 1 | 音频接口 2 | ======== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./aiao.rst 8 | ./audio_codec.rst 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/audio/audio_codec.rst: -------------------------------------------------------------------------------- 1 | Audio Codec 2 | ----------- 3 | 4 | 概述 5 | ~~~~ 6 | 7 | 芯片集成高性能的 Audio Codec, 包括立体声回放 DAC (90dB DR A-Weighted), 支持两路单端 lineout 输出; 立体声录音 ADC (90dB DR A-Weighted), 支持立体声单端输入。 8 | 9 | 特点 10 | ~~~~ 11 | 12 | - 90dB DR A-Weighted 立体声 DAC 13 | 14 | - 立体声单端 Lineout 输出 15 | 16 | - DAC 数字音量控制范围：-24dB ~ 0dB 17 | 18 | - DAC 支持 8kHz ~ 48kHz 采样率 19 | 20 | - 90dB DR A-Weighted 立体声 ADC 21 | 22 | - ADC PGA 增益范围: 0db ~ 48dB 23 | 24 | - ADC 支持 8kHz ~ 48kHz 采样率 25 | 26 | - ADC 支持 Mic in 立体声单端输入或 Line in 立体声单端输入 27 | 28 | Audio Codec 寄存器 29 | ~~~~~~~~~~~~~~~~~~ 30 | 31 | Audio DAC/ADC 寄存器概览 32 | ^^^^^^^^^^^^^^^^^^^^^^^^ 33 | 34 | .. include:: ./audio_dac_adc_registers_overview.table.rst 35 | 36 | Audio ADC 寄存器描述 37 | ^^^^^^^^^^^^^^^^^^^^ 38 | 39 | .. include:: ./audio_adc_registers_description.table.rst 40 | 41 | Audio DAC 寄存器描述 42 | ^^^^^^^^^^^^^^^^^^^^ 43 | 44 | .. include:: ./audio_dac_registers_description.table.rst 45 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_clock: 2 | 3 | 时钟 4 | ==== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | overview.rst 10 | function_block.rst 11 | clock_tree.rst 12 | pll_configure.rst 13 | div_configure.rst 14 | pll_reg_overview.rst 15 | pll_reg_description.rst 16 | div_reg_overview.rst 17 | div_reg_description.rst 18 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/clock_tree.rst: -------------------------------------------------------------------------------- 1 | 时钟资源与分频结构 2 | ------------------ 3 | 4 | 整个系统的时钟主要分两大部分：PLL 时钟和 IP/子系统时钟。 5 | 6 | 系统时钟来源主要来自外部时钟 XTAL。XTAL 通过 PLL 对其倍频。如 :ref:`diagram_clock_tree` 所示, 对于各 IP，一般以 XTAL 作为最初的时钟源, 通过一个或多个 PLL 时钟进行倍频后，再各自经过分频电路处理后，作为 IP 或子系统之时钟输入。 7 | 8 | .. _diagram_clock_tree: 9 | .. figure:: ../../../../media/image8.png 10 | :align: center 11 | 12 | 时钟源分频示意图 13 | 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/div_reg_description.rst: -------------------------------------------------------------------------------- 1 | IP/子系统时钟控制寄存器描述 2 | --------------------------- 3 | 4 | .. include:: ./div_crg_registers_description.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/div_reg_overview.rst: -------------------------------------------------------------------------------- 1 | IP/子系统时钟控制寄存器概览 2 | --------------------------- 3 | 4 | .. include:: ./div_crg_registers_overview.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/function_block.rst: -------------------------------------------------------------------------------- 1 | 功能框图 2 | -------- 3 | 4 | .. _diagram_clock_block: 5 | .. figure:: ../../../../media/image7.png 6 | :align: center 7 | 8 | 时钟管理框图 9 | 10 | XTAL_XIN 为 PLL 输入时钟, 固定连接 25MHz 晶体; RTC_XIN 为 RTC 输入时钟，固定连接 32.768KHz 晶体。 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 时钟管理模块对芯片时钟进行管理, 包括： 5 | 6 | - 时钟输入的管理和控制 7 | 8 | - PLL 时钟源及相关倍频和分频控制 9 | 10 | - 时钟分频和控制 11 | 12 | - 生成各模块的工作时钟 13 | 14 | - 时钟输出的管理和控制 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/pll_configure.rst: -------------------------------------------------------------------------------- 1 | PLL 配置 2 | -------- 3 | 4 | 如 :ref:`table_pll_configure` , 芯片内置 8 个 PLL (不计入 Analog IP 内建 PLL), 分为整数倍频跟分数倍频两类 PLL。 5 | 6 | 有关更多 PLL Configuration/Control Register 的内容，参考 :ref:`section_clock_pll_reg_overview` 和 :ref:`section_clock_pll_reg_description`。 7 | 8 | .. include:: ./pll_configure_params.table.rst 9 | 10 | 整数倍频 PLL 11 | ~~~~~~~~~~~~ 12 | 13 | 调整整数 PLL 流程: 14 | 15 | 1. 调整时须将相关使用此 PLL 之时钟关闭或是选择时钟源为 XTAL 或其他 PLL 16 | 17 | 2. 配置 \*_pll_csr 寄存器，按整数 PLL 参数表配置 18 | 19 | 3. 清除 \*_pll_pwd 20 | 21 | .. include:: ./pll_configure_integer_params.table.rst 22 | 23 | 分数倍频 PLL 24 | ~~~~~~~~~~~~ 25 | 26 | 调整分数 PLL 流程: 27 | 28 | 1. 时须将相关使用此 PLL 之 IP clock 关闭或是选择 XTAL 或其他稳定时钟源 29 | 30 | 2. 配置 \*_ssc_syn_src_en 以使能 synthesizer 时钟 31 | 32 | 3. 依据PLL 频率需求配置 \*_ssc_syn_set , 33 | 34 | 4. Toggle \*_ssc_syn_up ,使配置生效 35 | 36 | 5. 配置 \*_pll_csr 寄存器，按整数 PLL 参数表配置 37 | 38 | 6. 清除 \*_pll_pwd 39 | 40 | .. include:: ./pll_configure_fractional_params.table.rst 41 | 42 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/pll_reg_description.rst: -------------------------------------------------------------------------------- 1 | .. _section_clock_pll_reg_description: 2 | 3 | PLL 控制寄存器描述 4 | ------------------ 5 | 6 | PLL_G2 寄存器描述 7 | ~~~~~~~~~~~~~~~~~ 8 | 9 | .. include:: ./pll_g2_registers_description.table.rst 10 | 11 | PLL_G6 寄存器描述 12 | ~~~~~~~~~~~~~~~~~ 13 | 14 | .. include:: ./pll_g6_registers_description.table.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/clock/pll_reg_overview.rst: -------------------------------------------------------------------------------- 1 | .. _section_clock_pll_reg_overview: 2 | 3 | PLL 控制寄存器概览 4 | ------------------ 5 | 6 | .. include:: ./pll_crg_registers_overview.table.rst 7 | 8 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_ddr: 2 | 3 | DDR 控制器 4 | ========== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./features.rst 11 | ./functionalities.rst 12 | ./working_method.rst 13 | ./axi_registers.rst 14 | ./ddrc_registers.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/axi_registers.rst: -------------------------------------------------------------------------------- 1 | AXI 寄存器 2 | ---------- 3 | 4 | AXI 寄存器概览 5 | ~~~~~~~~~~~~~~ 6 | 7 | .. include:: ./axi_registers_overview.table.rst 8 | 9 | AXI 寄存器描述 (基址 0x0800_4000) 10 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 | 12 | .. include:: ./axi_registers_description_0x0800_4000.table.rst 13 | 14 | 15 | AXI 寄存器描述 (基址 0x0800_8000) 16 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 17 | 18 | .. include:: ./axi_registers_description_0x0800_8000.table.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/ddrc_registers.rst: -------------------------------------------------------------------------------- 1 | DDRC 寄存器 2 | ----------- 3 | 4 | DDRC 寄存器概览 5 | ~~~~~~~~~~~~~~~ 6 | 7 | 基址 0x0800_4000 8 | 9 | .. include:: ./ddrc_registers_overview.table.rst 10 | 11 | DDRC 寄存器描述 12 | ~~~~~~~~~~~~~~~ 13 | 14 | 基址 0x0800_4000 15 | 16 | .. include:: ./ddrc_registers_description.table.rst 17 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/ddrc_registers_overview.table.rst: -------------------------------------------------------------------------------- 1 | .. _table_ddrc_registers: 2 | .. table:: DDRC Registers Overview 3 | :widths: 2 1 2 4 | 5 | +----------------------+---------+------------------------------------+ 6 | | Name | Address | Description | 7 | | | Offset | | 8 | +======================+=========+====================================+ 9 | | DRAM_REF_CTRL | 0x064 | DRAM refresh parameter | 10 | +----------------------+---------+------------------------------------+ 11 | | DRAM_MRD0 | 0x0dc | DRAM MR value | 12 | +----------------------+---------+------------------------------------+ 13 | | DRAM_MRD1 | 0x0e0 | DRAM MR value | 14 | +----------------------+---------+------------------------------------+ 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ---- 3 | 4 | 功能特点： 5 | 6 | - 支持: 7 | 8 | - DDR2 最高数据速率 1333 Mbps。 9 | 10 | - DDR3 最高数据速率 1866 Mbps。 11 | 12 | - 支持接口数据位宽 16-bit。 13 | 14 | - 支持单通道, 单 rank。 15 | 16 | - 支持自动刷新控制。 17 | 18 | - 支持优先级控制。 19 | 20 | - 支持数据流量统计。 21 | 22 | - 支持低功耗模式。 23 | 24 | - 支持地址映射。 25 | 26 | - 支持管脚复用。 27 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | DDR 控制器实现了动态储存器 (DRAM) 的数据访问, 它将 SoC 中各主设备的数据访问命令转换为符合 JEDEC 标准的动态储存器命令, 加以适当调度, 进而提升动态储存器总线的使用效率。 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/ddr/working_method.rst: -------------------------------------------------------------------------------- 1 | 工作方式 2 | -------- 3 | 4 | 软复位 5 | ~~~~~~ 6 | 7 | 不支持软复位。 8 | 9 | DDR 初始化配置流程 10 | ~~~~~~~~~~~~~~~~~~ 11 | 12 | 本控制器初始化流程以软件包型式提供。 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/disclaimer.rst: -------------------------------------------------------------------------------- 1 | 声明 2 | ---- 3 | 4 | .. figure:: ../../../media/SOPHON-LOGO.png 5 | :align: center 6 | :alt: SOPHGO LOGO 7 | :scale: 50% 8 | 9 | | **联系我们** 10 | 11 | :官方网站: https://www.sophgo.com/ 12 | 13 | :文档发布网站: https://github.com/sophgo/sophgo-doc 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/dma/0.index.rst: -------------------------------------------------------------------------------- 1 | DMA 控制器 2 | ========== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers.rst 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/dma/dmac_access_space_type.table.rst: -------------------------------------------------------------------------------- 1 | .. _table_dmac_access_space_type: 2 | .. table:: DMAC Access Space Type 3 | :widths: 1 1 4 | 5 | +----------------------------------+----------------------------------+ 6 | | Space Type | Description | 7 | +==================================+==================================+ 8 | | Memory | SRAM | 9 | | +----------------------------------+ 10 | | | Non-safe DDR Space | 11 | +----------------------------------+----------------------------------+ 12 | | Peripherals | UART0~UART3 | 13 | | +----------------------------------+ 14 | | | I2C0~I2C4 | 15 | | +----------------------------------+ 16 | | | SPI0~SPI3 | 17 | | +----------------------------------+ 18 | | | SPI_NAND | 19 | | +----------------------------------+ 20 | | | I2S0~I2S3 | 21 | +----------------------------------+----------------------------------+ 22 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/dma/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ---- 3 | 4 | DMAC 特点如下: 5 | 6 | a. 最大可同时建立 8 个 DMA 通道。 7 | 8 | b. 传输的数据来源与数据目的， 皆可设置为内存或设备。 9 | 10 | c. 只允许单向传输配置。 11 | 12 | d. 提供DMA 传输暂停、恢复、取消。 13 | 14 | e. 支持 DMA Burst 长度配置。 15 | 16 | f. 提供 DMA 通道优先等级配置。 17 | 18 | g. 当通道数据是在设备间传输时, 流量控制可交由设备控制。 19 | 20 | h. 支持硬件链表功能。 21 | 22 | i. 支持通道上锁, 在上锁通道未完成前的其他通道请求会被忽略。 -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/dma/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | DMA (Direct Memory Access) 不需 CPU 逐笔数据干涉, 存储器与设备间可直接数据传输， 此机制大大减少 CPU 控制时间，并提高数据传输的速率， 非常适合使用在大量数据传输。芯片工作时往往同时需要多通道的数据传输，一个通道需要一个 DMA 硬件支持, DMAC (DMA 控制器) 负责了多通道的控制。 图表 :ref:`diagram_dma_hardware_control_process` 为DMAC 硬件控制流程图, 来源与目的设备可在不同的 AXI 汇流。 5 | 6 | .. _diagram_dma_hardware_control_process: 7 | .. figure:: ../../../../media/image9.png 8 | 9 | DMAC 硬件控制流程示意图 10 | 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/dma/registers.rst: -------------------------------------------------------------------------------- 1 | .. _section_dma_registers: 2 | 3 | DMAC 寄存器 4 | ----------- 5 | 6 | .. include:: ./dmac_registers.table.rst 7 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/initialization/0.index.rst: -------------------------------------------------------------------------------- 1 | 启动和升级 2 | ========== 3 | 4 | 概述 5 | ---- 6 | 7 | 芯片由内置 ROM (BOOTROM) 启动。芯片在复位时会通过侦测两个管脚(EMMC_DAT3, EMMC_DAT0) 上是否有弱上拉或弱下拉以确认目前选用使用的存储器件类型。 8 | 9 | 安全启动的芯片, 则会在开机及芯片升级时都会验签以确保执行或升级的软件是安全的。 10 | 11 | 启动模式和对应的信号锁存值对应关系 12 | ---------------------------------- 13 | 14 | - 支持由 SPI Nor Flash 启动 (EMMC_DAT3 pull down, EMMC_DAT0 pull up) 15 | 16 | - 支持由 SPI Nand Flash 启动 (EMMC_DAT3 pull down, EMMC_DAT0 pull down) 17 | 18 | - 支持由 eMMC 启动. (EMMC_DAT3 pull up, EMMC_DAT0 pull up) 19 | 20 | Note：因为 SD0 与 eMMC domain 共用 IO power，因为SD 卡default 3.0V，而 eMMC 多为 1.8V，所以基本上不支援 eMMC，除非 SD0 不接SD卡。 21 | 22 | 镜像烧写模式. 23 | -------------- 24 | 25 | - 支持通过 SD 卡烧写镜像。 26 | 27 | - 支持通过 USB device mode 烧写镜像。 28 | 29 | - 若 flash 中己有镜像, 软件支援由网路升级软件。 30 | 31 | 安全启动 32 | -------- 33 | 34 | - 支持安全启动及升级。 35 | 36 | - AES/DES/SM4 硬件加解密。 37 | 38 | - SHA/TRNG/Secure Efuse 安全硬件。 -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/mcu/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_8051: 2 | 3 | 8051 子系统 4 | =========== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./features.rst 11 | ./working_method.rst 12 | ./registers_overview.rst 13 | ./registers_description.rst 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/mcu/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ---- 3 | 4 | 8051 微处理器具有以下特点： 5 | 6 | - 支持标准 8051 指令集。 7 | 8 | - 频率范围 25MHz ~ 300 MHz。 9 | 10 | - 除错功能 : 单步执行/jump2pc/snapshot PSW, DPTR, PC。 11 | 12 | - 支持 32bit 数据存取。 13 | 14 | - 复位向量可配置到系统 AHB SRAM/DRAM/SPINOR。 15 | 16 | - 支持 WFI (Clock gating)。 17 | 18 | - 支持 code banking (最大 64x64 KB)。 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/mcu/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 8051 子系统位于 RTCSYS 内，采用独立供电。系统软件可以使用 8051 在系统休眠时管理唤醒条件和唤醒系统, 并且通过周边控制器与外部装置沟通。 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/mcu/registers_description.rst: -------------------------------------------------------------------------------- 1 | 8051 子系统寄存器描述 2 | --------------------- 3 | 4 | 8051 子系统的寄存器定义在 RTC CTRL 寄存器中，具体参考 :ref:`section_rtc_ctrl_register_description` 部分。 -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/mcu/registers_overview.rst: -------------------------------------------------------------------------------- 1 | 8051 子系统寄存器概览 2 | --------------------- 3 | 4 | 8051 子系统的寄存器定义在 RTC CTRL 寄存器中，具体参考 :ref:`section_rtc_register_overview` 章节的 RTC_CTRL_REG 部分。 5 | 6 | 7 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/mcu/working_method.rst: -------------------------------------------------------------------------------- 1 | 工作方式 2 | -------- 3 | 4 | .. _section_8051_power_domain_control: 5 | 6 | Power domain 控制流程 7 | ~~~~~~~~~~~~~~~~~~~~~ 8 | 9 | RTCSYS 子系统内分成两个 power domain: AO (Always-On) domain 和 MCU domain。可以通过配置寄存器对 MCU domain进行上下电流程, 流程如下: 10 | 11 | MCU power_off: 12 | 13 | 1. 软复位寄存器 = 0 14 | 15 | 2. 配置寄存器 reg_mcu_iso_en = 1 16 | 17 | 3. 配置寄存器 reg_mcu_pwr_req = 0 18 | 19 | MCU power_on: 20 | 21 | 1. 配置寄存器 reg_mcu_pwr_req = 1 22 | 23 | 2. 轮询寄存器 reg_mcu_pwr_ack = 1 24 | 25 | 3. 配置寄存器 reg_mcu_iso_en = 0 26 | 27 | 4. 软复位寄存器 = 1 28 | 29 | 8051 初始化 30 | ~~~~~~~~~~~ 31 | 32 | 8051 在系统初始是处于复位状态, 使用 8051 可以透过 ACPU 来完成下面的软件流程: 33 | 34 | 1. 8051 复位状态处于复位状态 (寄存器 reg_soft_rstn_mcu = 0)。 35 | 36 | 2. 配置寄存器 reg_mcu_rom_addr_size 来决定指令 TCM size。 37 | 38 | 3. 配置寄存器 reg_51irom_ioffset 来决定 TCM 执行在 AHB SRAM 上的位置。 39 | 40 | 4. 配置寄存器 reg_soft_rstn_mcu =1 解除 8051 复位状态。 41 | 42 | .. _section_8051_interrupt: 43 | 44 | 中断处理 45 | ~~~~~~~~ 46 | 47 | 8051 可以透过 int0_n, int1_n 接口接收外部电平触发中断, int0_n/int1_n 分别从 ictl (中断控制) 和配置寄存器 reg_51_int1_src_mask 来选择输出中断信号给 8051。 48 | 49 | .. include:: ./8051_interrupts.table.rst 50 | 51 | .. _section_8051_mailbox: 52 | 53 | MAILBOX 54 | ~~~~~~~ 55 | 56 | Mailbox 提供 2 组 spinlock 功能栏位，和 4 组 32bit 信息栏位，让 ACPU/8051 可以相互传输信息。 57 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/network/0.index.rst: -------------------------------------------------------------------------------- 1 | 网络接口 2 | ======== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./eth_mac.rst 8 | ./eth_phy.rst 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/network/eth_phy.rst: -------------------------------------------------------------------------------- 1 | Ethernet PHY 2 | ------------ 3 | 4 | 概述 5 | ~~~~ 6 | 7 | 芯片提供一组内建 Ethernet 10/100 Base-TX compliant PHY 接口。 8 | 9 | 功能描述 10 | ~~~~~~~~ 11 | 12 | - 支持IEEE 802.3 10/100 Base-TX compliant。 13 | 14 | - 支持传收送速度与全半双工工作模式自动协商功能。 15 | 16 | - 支持以太网路线交叉线或直连线自动移动翻转功能。 17 | 18 | - 支持以太网路 WOL(Wake on Lan) 功能。 19 | 20 | 功能配置图描述 21 | ~~~~~~~~~~~~~~ 22 | 23 | .. _diagram_ethernet_phy: 24 | .. figure:: ../../../../media/image28.png 25 | :align: center 26 | 27 | 内建 10/100 Ethernet PHY 框图 28 | 29 | 10/100Mbps 传送及收发功能在标准 category5 (CAT5) 双绞线上, 传送接收信号经由 transformer 连接于 RJ45 标准接口。 30 | 31 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/peripherals/0.index.rst: -------------------------------------------------------------------------------- 1 | 外围设备 2 | ======== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./i2c.rst 8 | ./uart.rst 9 | ./spi.rst 10 | ./sdmmc.rst 11 | ./gpio.rst 12 | ./usb.rst 13 | ./saradc.rst 14 | ./temperature.rst 15 | ./pwm.rst 16 | ./keyscan.rst 17 | ./wiegand.rst 18 | ./irrx.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/pinmux-pinctrl/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_pinmux_pinctrl: 2 | 3 | 管脚复用与控制 4 | ============== 5 | 6 | .. only:: sg2002 7 | 8 | 管脚复用和管脚控制的相关信息请直接参考在线表格: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/04_SG2002/04_SG2002_PINOUT.xlsx 9 | 10 | .. only:: sg2000 11 | 12 | 管脚复用和管脚控制的相关信息请直接参考在线表格: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/03_SG2000/04_SG2000_PINOUT.xlsx 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/power/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_power: 2 | 3 | 电源管理 4 | ======== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./clock_control.rst 11 | ./ddr_powerctrl.rst 12 | ./voltage_adjustment.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/power/clock_control.rst: -------------------------------------------------------------------------------- 1 | 时钟控制 2 | -------- 3 | 4 | 关闭不需要的时钟分频器 5 | ~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | 参考 :ref:`section_clock` 配置章节，根据各模块所需时钟源，将没使用到之时钟分频器关闭。达到节省功耗之目的。 8 | 9 | 调整模块的工作频率 10 | ~~~~~~~~~~~~~~~~~~ 11 | 12 | 根据各模块所需之时钟规格，选择较低之时钟源。分频配置较多以降低模块工作频率。须注意单一模块之频率降低不一定能降低整体之功耗。 13 | 14 | 模块级低功耗控制 15 | ~~~~~~~~~~~~~~~~ 16 | 17 | - 模拟模块: MIPI/USB/ETH/AUD 相关寄存器设置，将不使用之模块关闭或是进入低功耗模式。 18 | 19 | - 数字模块: 根据硬件与规格，关闭不需要的数字模块之时钟。 20 | 21 | 关闭不使用的 PLL 22 | ~~~~~~~~~~~~~~~~ 23 | 24 | 参考 PLL 配置, 可以将不需要使用之 PLL 做 Powerdown, 以达到功耗之节省。 25 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/power/ddr_powerctrl.rst: -------------------------------------------------------------------------------- 1 | DDR 低功耗控制 2 | -------------- 3 | 4 | 在总线没有存取一段时间之后, DDR 控制器会自动进入 Self refresh 和 Power down 的状态. 以减少系统功耗. 5 | 6 | 有些场景因为存取断断续续无法找到足够大的空隙进入 self refresh。这时还能考虑藉由内建存取资料量的统计寄存器。以确认带宽是否过剩可以考虑直接降频. 7 | 8 | DDR 控制器支援动态频率调整. 但由于调整频率会暂时停止 DDR 的存取一段时间。所以为了减少中断的时间可能造成实时应用缓冲 underflow / overflow. 只限于 50% 和 100% 两个档位。 9 | 10 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/power/voltage_adjustment.rst: -------------------------------------------------------------------------------- 1 | 电压调节 2 | -------- 3 | 4 | 芯片预设使用 PWM0 去控制 VDDC 电压调控之用. 以下是一个使用 PWM 去控制 DCDC 输出电压的例子。 5 | 6 | .. _diagram_example_control_dcdc_with_pwm: 7 | .. figure:: ../../../../media/image14.png 8 | :align: center 9 | 10 | 使用 PWM 控制 DCDC 电压范例 11 | 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/reset/0.index.rst: -------------------------------------------------------------------------------- 1 | 复位 2 | ==== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./reset_control.rst 9 | ./reset_registers.rst 10 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/reset/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 复位管理模块对整个芯片、子系统、各功能模块的复位与时序，进行统一的管理。 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/reset/reset_control.rst: -------------------------------------------------------------------------------- 1 | 复位控制 2 | -------- 3 | 4 | 芯片内部存在三个层级的复位管理模块对整个芯片、子系统，各个功能模块的复位进行管理。 5 | 6 | .. _diagram_reset_block: 7 | .. figure:: ../../../../media/image6.png 8 | :align: center 9 | 10 | 复位管理模块框图 11 | 12 | Reset Ctrl Level 1 电路负责系统上电复位功能。上电复位 (POR) 由实时时钟模块配合全局电源管理与晶振时序生成。详情参照章节 :ref:`section_rtc`。来源由以下途径： 13 | 14 | - 上电复位 15 | 16 | - 过热保护复位 17 | 18 | - 看门狗复位。RCT_CTRL0.hw_wdg_rst_en 为 1, (见 :ref:`table_rtc_ctrl0`) 且 sys_ctrl_reg.reg_sw_root_reset_en 的 bit[0] 为 0 (见 :ref:`table_sys_ctrl_reg`) 情况下 Watchdog 定时器超时触发系统复位。 19 | 20 | Reset Ctrl Level 2 电路负责产生系统硬复位 (System Hard Reset)，对芯片全局包含子系统及各功能模块进行硬复位，来源由以下途径： 21 | 22 | - 看门狗复位, sys_ctrl_reg.reg_sw_root_reset_en 的 bit[0] 为 1 (见 :ref:`table_sys_ctrl_reg`) 情况下 Watchdog 定时器超时触发系统复位。 23 | 24 | - 外部复位管脚 (RSTN)，内建去抖动电路 (Debounce), RSTN 高低电平有效信号须达 6.56ms。 25 | 26 | Reset Ctrl Level 3 电路负责提供实现软复位控制相应的复位配置寄存器 (Reset CRG)，具体参考 :ref:`section_reset_configure_registers`。包含： 27 | 28 | - 系统软复位 : 复位全芯片，除少部分电路及 RTC 内部电路。 29 | 30 | - 处理器子系统复位 : 复位处理器及处理器子系统。操作寄存器 SOFT_CPUAC_RSTN 可对处理器及子系统做软复位，配置寄存器写 0 后，复位控制器会等待 24us 延时后才触发相应处理器复位。这段期间处理器应结束对总线之访问，以避免复位后总线挂死。触发复位后对应之复位信号会持续 8us 后自动解除，处理器及处理器子系统完成复位并开始启动。 31 | 32 | - 功能子系统及功能模块复位: 复位各功能子系统及功能模块。操作寄存器 SOFT_RSTN_0 ~ 3，可对各功能模块进行软复位。复位配置为低电平有效，复位信号并不会自动清除，故软件配置相应寄存器为 0 触发复位后，亦需配置为 1 解除复位。复位前须确保各功能模块及功能子系统内置 DMA 对总线访问与处理器对模块之访问处于闲置状态。否则将使复位失败易造成系统挂死。 33 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/reset/reset_registers.rst: -------------------------------------------------------------------------------- 1 | .. _section_reset_configure_registers: 2 | 3 | 复位配置寄存器 4 | -------------- 5 | 6 | 复位配置寄存器概览 7 | ~~~~~~~~~~~~~~~~~~ 8 | 9 | Base address 0x03003000 10 | 11 | .. include:: ./reset_registers_overview.table.rst 12 | 13 | 复位配置寄存器描述 14 | ~~~~~~~~~~~~~~~~~~ 15 | 16 | .. include:: ./reset_registers_describe.table.rst 17 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/reset/reset_registers_overview.table.rst: -------------------------------------------------------------------------------- 1 | .. _table_reset_registers_overview: 2 | .. table:: Overview of Reset Configuration Registers 3 | :widths: 1 1 2 4 | 5 | +----------------------+---------+------------------------------------+ 6 | | Name | Address | Description | 7 | | | Offset | | 8 | +======================+=========+====================================+ 9 | | SOFT_RSTN_0 | 0x000 | soft-reset ctrl register 0 | 10 | +----------------------+---------+------------------------------------+ 11 | | SOFT_RSTN_1 | 0x004 | soft-reset ctrl register 1 | 12 | +----------------------+---------+------------------------------------+ 13 | | SOFT_RSTN_2 | 0x008 | soft-reset ctrl register 2 | 14 | +----------------------+---------+------------------------------------+ 15 | | SOFT_RSTN_3 | 0x00c | soft-reset ctrl register 3 | 16 | +----------------------+---------+------------------------------------+ 17 | | SOFT_CPUAC_RSTN | 0x020 | CPU auto clear soft-reset ctrl | 18 | | | | register | 19 | +----------------------+---------+------------------------------------+ 20 | | SOFT_CPU_RSTN | 0x024 | CPU soft-reset ctrl register | 21 | +----------------------+---------+------------------------------------+ 22 | 23 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/rtc/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_rtc: 2 | 3 | 实时时钟 4 | ======== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./features.rst 11 | ./functionalities.rst 12 | ./working_method.rst 13 | ./registers_overview.rst 14 | ./registers_description.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/rtc/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ---- 3 | 4 | RTC 具有以下特点： 5 | 6 | - 提供芯片系统复位信号 (System Reset) 7 | 8 | - 提供 32,768 Hz 计数时钟 (误差 < ±1%) 9 | 10 | - 提供 32-bit 秒钟计数器及硬件校准电路，可让秒钟精准度达到 5ppm 水平 11 | 12 | - 支持报警时钟配置，并产生报警中断 13 | 14 | - 提供 2KB 空间 SRAM, 可保存软件代码或暂存数据 15 | 16 | - 支持电池低压检测，并产生中断 17 | 18 | - 支持按键触发芯片从休眠唤醒 19 | 20 | - 支持软件触发芯片休眠、复位或过热重启 21 | 22 | - 支持 Watchdog 触发芯片系统复位 23 | 24 | - 支持报警触发芯片从休眠唤醒 25 | 26 | - 上下电时序、复位时间间隔可配置 27 | 28 | - 提供 1 个超低功耗模拟秒钟计数器 (32 bit to count from 1970~2106 year) 29 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/rtc/functionalities.rst: -------------------------------------------------------------------------------- 1 | 功能描述 2 | -------- 3 | 4 | RTC 是芯片内一个独立供电的恒电模块，当 RTC 首次上电时，内部 POR 模块产生一个低电平脉冲, 32KHz 振荡器开始起振。POR 低电平维持时间大于 13 个 32KHz 时钟周期, RTC 进入初始状态。当状态机检测到电池电压处于正常状态，则开始依默认值时序完成芯片上电流程并解除系统复位信号。软件在首次开机后需要将 RTC 初始化，并配置计数初始值。当系统要执行关机或进入休眠时，可通过配置系统控制寄存器 (RTC_CTRL) 触发 RTC 状态机依配置时序完成芯片下电流程。 5 | 6 | 当芯片处于下电关机或休眠状态时，只要维持 RTC 供电就会持续工作状态，以保存必要的软件代码或用户数据于 SRAM 和信息寄存器 (RTC_INFO0 ~ RTC_INFO3, RTC_NOPOR_INFO0 ~ RTC_NOPOR_INFO3); 计数器会持续计数，同时也会侦测按键是否触发芯片开机或自休眠唤醒, 当收到触发则会由状态机依配置时序完成芯片上电流程并解除系统复位信号。处理器内核在重启后, 软件可藉由回读先前写入信息寄存器的内容来判断芯片状态, RTC 内也提供两个状态寄存器 (RTC_ST_ON_REASON, RTC_ST_OFF_REASON)，分别记录前一次芯片下电或上电、复位的触发条件，提供软件更细致内容，例如是否曾经发生非预期事件：强制复位、芯片过热或电池/电源脱落等。另外，当 RTC 收到 Watchdog 时，会触发状态机依配置时序发出系统复位信号，将芯片重启。 7 | 8 | RTC 的计数时钟采用 32KHz 时钟，运行基于一个 32-bit 的加法计数器提供秒计数，计数初值由寄存器 RTC_SET_SEC_CNTR_VALUE 载入。软件可通过寄存器 RTC_SEC_CNTR_VALUE 回读秒数值，转换为具体的年、月、日、时、分。 9 | 10 | 32KHz 时钟及秒脉冲周期可经由软件流程做校准 (calibration)，或开启硬件模块周期性执行自动校准。 11 | 12 | 软件可通过配置 32-bit 寄存器 RTC_ALARM_TIME, 并将 RTC_ALARM_ENABLE 写 1 使能 Alarm, 当秒计数值 RTC_SEC_CNTR_VALUE 递加到与 RTC_ALARM_TIME 值相等时, RTC 将产生报警中断。中断状态会维持直到 RTC_ALARM_ENABLE 写 0。 13 | 14 | 此外 RTC 提供电池低压检测, 当电池电压低于一定水平时, RTC 将产生中断，软件收到低压中断后，可即时执行关机程序并触发 RTC 完成下电流程，以防止系统发生异常错误。 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/rtc/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 实时时钟 RTC (Real Time Clock) 是芯片内一个独立供电的模块，内部包含一个 32KHz 振荡器与上电复位 (Power-On-Reset/POR) 的子模块，可用于时间显示及定时报警 (Alarm) 产生。此外由硬件状态机提供芯片上电、下电及复位的触发与时序控制。 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/rtc/registers_description.rst: -------------------------------------------------------------------------------- 1 | RTC 寄存器描述 2 | -------------- 3 | 4 | .. include:: ./rtc_registers_description.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/rtc/registers_overview.rst: -------------------------------------------------------------------------------- 1 | .. _section_rtc_register_overview: 2 | 3 | RTC 寄存器概览 4 | -------------- 5 | 6 | RTC 寄存器包含多个部份，RTC_CORE_REG、RTC_MACRO_REG 和 RTC_CTRL_REG，寄存器基址不同，都通过总线存取。 7 | 8 | RTC_CORE_REG 寄存器概览如 :ref:`table_rtc_core_reg_overview`。 9 | 10 | .. include:: ./rtc_core_reg_overview.table.rst 11 | 12 | RTC_MACRO_REG 寄存器概览如 :ref:`table_rtc_macro_reg_overview` 所示。 13 | 14 | .. include:: ./rtc_macro_reg_overview.table.rst 15 | 16 | RTC_CTRL_REG 寄存器概览如 :ref:`table_rtc_ctrl_reg_overview` 所示。 17 | 18 | .. include:: ./rtc_ctrl_reg_overview.table.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/security/0.index.rst: -------------------------------------------------------------------------------- 1 | 安全子系统 2 | ========== 3 | 4 | 芯片提供独立安全子系统模块，负责提供特定安全功能。 5 | 6 | 安全子系统模块包括了下列安全功能模块 7 | 8 | - 密码运算单元 (Crypto DMA) 9 | 10 | - 真随机数产生单元 (True Random Number Generator) 11 | 12 | - 安全除错保护单元 (Secure Debug Protection) 13 | 14 | 密码运算单元 (CryptoDMA) 提供对称密钥加解密及哈希 (Hash) 的硬件加速，安全 eFuse 单元负责提供系统安全设置及安全密钥给安全子系统使用，真随机数产生单元提供合格的随机数供安全系统使用。 15 | 16 | .. _diagram_security_module: 17 | .. figure:: ../../../../media/image143.png 18 | :align: center 19 | 20 | 安全子系统模块 21 | 22 | .. toctree:: 23 | :maxdepth: 2 24 | 25 | ./cryptodma.rst 26 | ./trng.rst 27 | ./firewall.rst 28 | ./efuse.rst 29 | 30 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/security/efuse.rst: -------------------------------------------------------------------------------- 1 | Efuse 控制器 2 | ------------ 3 | 4 | 芯片内部集成 4Kbit eFuse 空间，并以 Efuse Ctrl 对 Efuse 进行编程和读取。 5 | 6 | Efuse Ctrl 的主要功能包括： 7 | 8 | - 提供双 eFuse 位元 (Double bit) 保护机制，由两个实体 eFuse 位元组成单一位元逻辑有效值，等效于提供 2Kbit 寄存器空间，以提高 eFuse 烧写或资料维持的强健性。 9 | 10 | - 上电复位后 (Power-On-Reset), 自动加载 efuse 的内容到寄存器，提供芯片系统所需组态设定及减少对 Efuse 所需读取次数提高使用期限。 11 | 12 | - 提供 efuse 编程、读取、验证读取及上下电指令及内容安全保护机制。 13 | 14 | Efuse 资料寄存器分成两块区域，一块为非安全区域，另一块是安全区域，非安全区域内资料允许所有模块访问，安全区域只允许安全模块访问。非安全区域储存系统组态及公开信息，安全区域储存安全组态、密钥及密码。 15 | 16 | .. _diagram_efuse_block: 17 | .. figure:: ../../../../media/image147.png 18 | :align: center 19 | 20 | eFuse CTRL 模块架构 21 | 22 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/security/firewall.rst: -------------------------------------------------------------------------------- 1 | 安全除错防火墙 2 | -------------- 3 | 4 | 为了提供除错或测试时读取或控制芯片内部相关功能，芯片提供了数种除错接口，如 JTAG、I2C 等不同的外部接口。若缺乏适当的保护机制，这些接口很轻易地会被利用以直接或间接的方式，来攻击芯片安全机制或读取内部需保密的信息。为了保护及控制这些接口，芯片采用了安全除错防火墙措施。 5 | 6 | 概述 7 | ~~~~ 8 | 9 | 芯片支持三种主要的除错接口， 10 | 11 | 1. RISCV JTAG: RISCV 处理器内建调试接口，允许使用者通过 JTAG 接口访问 ARM 内部寄存器 12 | 13 | 2. I2C: 芯片提供除错接口 14 | 15 | 3. Test interface: 芯片提供生产测试专用调试接口 16 | 17 | 对于 JTAG/I2C 接口，安全除错防火墙针对其访问提供特定保护控制 18 | 19 | 对 Test interface 接口，安全除错接口则其访问提供一类独立的保护控制 (Test 访问) 20 | 21 | 针对这些除错类别 ，安全除错防火墙提供三种连接控制状态 22 | 23 | - 开放 (Open): 允许外部通过接品连入，不施加额外控制。 24 | 25 | - 保护 (Protected):不允许外部通过接品连入, 直到由外部通过 I2C 接口输入对应密码解开保护。 26 | 27 | - 关闭 (Closed): 不允许外部通过该接口连入，无法由其他方法再次开启。 28 | 29 | 状态查讯及密码输入接口 (I2C) 30 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 31 | 32 | 安全除错防火墙提供一个独立运作的 I2C 接口，供芯片外部通过 I2C 来查讯除错接口当前状态及输入相对应密码来将在保护状态的接口重新开启。外部需指定正确的 I2C ID 来连接接防火墙接口。 33 | 34 | I2C 接口寄存器位址如下 35 | 36 | .. include:: ./firewall_i2c_query_interface.table.rst 37 | 38 | 状态查讯及密码输入流程 39 | ~~~~~~~~~~~~~~~~~~~~~~ 40 | 41 | 状态查讯流程 42 | ^^^^^^^^^^^^ 43 | 44 | - (步骤一) 控制外部 I2C 发出开始信号。 45 | 46 | - (步骤二) 由 I2C 发出防火墙 I2C ID (预设 0x56)。 47 | 48 | - (步骤三) 由 I2C 读取位址 0x04001A94, 以获得当前除错接口保护状态。 49 | 50 | 密码输入流程 51 | ^^^^^^^^^^^^ 52 | 53 | - (步骤一) 控制外部 I2C 发出开始信号。 54 | 55 | - (步骤二) 由 I2C 发出除错接口防火墙的 I2C ID (预设 0x56)。 56 | 57 | - (步骤三) 由 I2C 读取位址 0x04001A80 / 0x04001A84, 以获得设备序号 Device ID, 读取 0x04001A88 以获得市场区别编号。 58 | 59 | - (步骤四) 经由设备序号及市场区别编号，准备各个类别相对应的解锁密码。 60 | 61 | - (步骤五) 由 I2C 读取位址 0x94, 以获得当前除错接口保护状态，碉认是否上锁。 62 | 63 | - (步骤六) 以非安全除错接口为例，由 I2C 将非安全密码写入位址 0x04001A00 / 0x04001A04 / 0x04001A08 / 0x04001A0C。 64 | 65 | - (步骤七) I2C 写任意值至位址 0x04001A10, 更新密码比较值。 66 | 67 | - (步骤八) 由 I2C 读取位址 0x94, 以获得当前除错接口保护状态, 确认是否解锁。 68 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/security/trng.rst: -------------------------------------------------------------------------------- 1 | TRNG 2 | ---- 3 | 4 | 概述 5 | ~~~~ 6 | 7 | 真随机数生成器 (True Random Number Generator，简称 TRNG) 生成的随机数在统计上等同于均匀分布的随机数据流。该电路包括一个确定性随机位生成器 (Deterministic Random Bit Generator，简称 DRBG)。当创建种子并将其输入到 DRBG 中时，TRNG 会生成随机数。 8 | 9 | 功能特性 10 | ~~~~~~~~ 11 | 12 | TRNG 模块具有以下功能特点： 13 | 14 | - 内部随机种子操作 15 | - 128 位随机数生成 16 | - 128 位安全强度 17 | 18 | 工作方式 19 | ~~~~~~~~ 20 | 21 | 循环测试 STAT.BUSY，直到它空闲。 22 | 23 | 将 GEN_NOISE 写入 CTRL.CMD，从噪声中生成全熵种子。 24 | 25 | 循环测试 ISTAT.DONE，直到上一个命令完成。 26 | 27 | 通过将 1 写入 ISTAT.DONE 来清除它。 28 | 29 | 将 CREATE_STATE 写入 CTRL.CMD，将 DRBG 移至创建状态。 30 | 31 | 循环测试 ISTAT.DONE，直到上一个命令完成。 32 | 33 | 通过将 1 写入 ISTAT.DONE 来清除它。 34 | 35 | 将 GEN_RANDOM 写入 CTRL.CMD，生成随机数。 36 | 37 | 循环测试 ISTAT.DONE，直到上一个命令完成。 38 | 39 | 通过将 1 写入 ISTAT.DONE 来清除它。 40 | 41 | 从 RAND0 读取第一个随机数据 WORD。 42 | 43 | 从 RAND1 读取第二个随机数据 WORD。 44 | 45 | 从 RAND2 读取第三个随机数据 WORD。 46 | 47 | 从 RAND3 读取第四个随机数据 WORD。 48 | 49 | TRNG 寄存器概览 50 | ~~~~~~~~~~~~~~~~~~~~ 51 | 52 | .. include:: ./trng_registers_overview.table.rst 53 | 54 | TRNG 寄存器描述 55 | ~~~~~~~~~~~~~~~~~~~~ 56 | 57 | (基址 0x02070000) 58 | 59 | .. include:: ./trng_registers_description.table.rst 60 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/0.index.rst: -------------------------------------------------------------------------------- 1 | SPI NAND Flash 控制器 2 | ===================== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./data_structure.rst 12 | ./registers_overview.rst 13 | ./registers_descriptions.rst 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/data_structure.rst: -------------------------------------------------------------------------------- 1 | 数据结构 (NAND Flash/SPI NAND Flash) 2 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 | 4 | 2KB page_size 5 | ^^^^^^^^^^^^^ 6 | 7 | 对 2KB page_size 的配置，软件可用的冗余区常见大小为 64Byte。数据在 Buffer 和 Flash 中的结构如下所示。冗余区大小与实际使用器件相关。 8 | 9 | .. 这个表比较小，所以就不单独放文件 include 了 10 | 11 | .. table:: The structure of data in Buffer and Flash (2KB page_size) 12 | :widths: 1 1 1 13 | 14 | +------------------+--------------------------------+------------------+ 15 | | User Data | Data(2048) | OOB(64) | 16 | +------------------+--------------------------------+------------------+ 17 | 18 | 19 | 4KB page_size 20 | ^^^^^^^^^^^^^ 21 | 22 | 对 4KB page_size 的配置，软件可用的冗余区常见大小为 256Byte。数据在 Buffer 和 Flash 中的结构如下所示。冗余区大小与实际使用器件相关。 23 | 24 | .. 这个表比较小，所以就不单独放文件 include 了 25 | 26 | .. table:: The structure of data in Buffer and Flash (4KB page_size) 27 | :widths: 1 1 1 28 | 29 | +------------------+--------------------------------+------------------+ 30 | | User Data | Data(4096) | OOB(256) | 31 | +------------------+--------------------------------+------------------+ 32 | 33 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ~~~~ 3 | 4 | - 支持外接 1 片选。 5 | 6 | - 支持 SPI NAND Flash x1/x2/x4 读写操作。 7 | 8 | - 支时多种规格 SPI NAND Flash 器件。 9 | 10 | - 支持页 2KB、4KB 器件。 11 | 12 | - 支持 64Pages/Block、128Pages/Block 器件。 13 | 14 | - 支持 SPI NAND 的 BOOT 功能。 15 | 16 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ~~~~ 3 | 4 | 提供片外 SPI NAND Flash 数据存取。 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/registers_descriptions.rst: -------------------------------------------------------------------------------- 1 | 寄存器描述 2 | ---------- 3 | 4 | .. include:: ./spi_nandflash_registers_description.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/registers_overview.rst: -------------------------------------------------------------------------------- 1 | 寄存器概览 2 | ---------- 3 | 4 | .. include:: ./spi_nandflash_registers_overview.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_nandflash/working_method.rst: -------------------------------------------------------------------------------- 1 | 工作流程 2 | ~~~~~~~~ 3 | 4 | 初始化流程 5 | ^^^^^^^^^^ 6 | 7 | - 步骤 1: （如果需要调整 Timing 参数）根据器件配置时序寄存器 reg_trx_sck_h 及 reg_trx_sck_l。 8 | 9 | - 步骤 2: 配置中断控制寄存器 reg_trx_done_int_en。 10 | 11 | 器件寄存器操作流程 12 | ^^^^^^^^^^^^^^^^^^ 13 | 14 | - 步骤 1: 配置传输数据长度 reg_trx_cmd_cont_size 及 reg_trx_data_size。 15 | 16 | - 步骤 2: 配置器件指令其相关内容 reg_trx_cmd_id、reg_trx_cmd_cont0 及 reg_trx_cmd_cont1。 17 | 18 | - 步骤 3: 配置 reg_trx_start 寄存器下发操作。 19 | 20 | - 步骤 4: 检测到reg_trx_done_int, 表示操作完成。 21 | 22 | 擦除操作流程 23 | ^^^^^^^^^^^^ 24 | 25 | 对于flash操作, 在编程操作前, 都必须进行擦除, 在擦除操作前还必须完成 WREN 操作。 26 | 27 | - 步骤 1: 配置传输数据长度 reg_trx_cmd_cont_size。 28 | 29 | - 步骤 2: 配置器件指令其相关内容 reg_trx_cmd_id、 reg_trx_cmd_cont0。 30 | 31 | - 步骤 3: 配置 reg_trx_start 寄存器下发操作。 32 | 33 | - 步骤 4: 检测到 reg_trx_done_int, 表示操作完成。 34 | 35 | 内置 DMA 读操作流程 36 | ^^^^^^^^^^^^^^^^^^^ 37 | 38 | - 步骤 1: 配置系统 DMA 寄存器，参照 :ref:`section_dma_registers`。 39 | 40 | - 步骤 2: 配置传输数据长度 reg_trx_cmd_cont_size 、reg_trx_data_size。 41 | 42 | - 步骤 3: 配置器件指令其相关内容 reg_trx_cmd_id、reg_trx_cmd_cont0及reg_trx_cmd_cont1。 43 | 44 | - 步骤 4: 配置 reg_trx_start 寄存器下发操作。 45 | 46 | - 步骤 5: 检测到 reg_trx_done_int, 表示器件内容完成读取且已写入缓冲区。 47 | 48 | 内置 DMA 写操作流程 49 | ^^^^^^^^^^^^^^^^^^^ 50 | 51 | - 步骤 1: 配置系统 DMA 寄存器，参照 :ref:`section_dma_registers`。 52 | 53 | - 步骤 2: 配置传输数据长度 reg_trx_cmd_cont_size 、reg_trx_data_size。 54 | 55 | - 步骤 3: 配置器件指令其相关内容 reg_trx_cmd_id、reg_trx_cmd_cont0及reg_trx_cmd_cont1。 56 | 57 | - 步骤 4: 配置 eg_trx_start 寄存器下发操作。 58 | 59 | - 步骤 5: 检测到 reg_trx_done_int, 表示缓冲区内容已写入器件 cache 完成。 60 | 61 | 其它注意事项 62 | ^^^^^^^^^^^^ 63 | 64 | - 部分 SPI NAND Flash 器件要求在使用之前或者异常复位后必须先进行器件的 RESET 操作；所以为器件相容性考量，开始使用或异常复位后的第一个传输指令需为 RESET。 65 | 66 | - 对器件操作未完成前，不可改动相关寄存器配置，否则可能导致操作不正常。 67 | 68 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_norflash/0.index.rst: -------------------------------------------------------------------------------- 1 | SPI NOR Flash 控制器 2 | ==================== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers_overview.rst 12 | ./registers_descriptions.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_norflash/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ---- 3 | 4 | - 支持外接 1 片选。 5 | 6 | - 支持 Dual/Qual 读写操作。 7 | 8 | - 支持多种规格器件。 9 | 10 | - 支持 3Byte 地址器件及 4Byte 地址器件。 11 | 12 | - 支时最大 256MB 容量器件。 13 | 14 | - 支持 BOOT 功能。 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_norflash/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 提供片外 SPI NOR Flash 数据存取。 5 | 6 | 7 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_norflash/registers_descriptions.rst: -------------------------------------------------------------------------------- 1 | 寄存器描述 2 | ---------- 3 | 4 | .. include:: ./spi_norflash_registers_description.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/spi_norflash/registers_overview.rst: -------------------------------------------------------------------------------- 1 | 寄存器概览 2 | ---------- 3 | 4 | Base Address 0x10000000 5 | 6 | .. include:: ./spi_norflash_registers_overview.table.rst 7 | 8 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-architecture/0.index.rst: -------------------------------------------------------------------------------- 1 | 系统架构 2 | ======== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./processors.rst 8 | ./interrupts.rst 9 | ./memorymap.rst 10 | ./package_pin.rst 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-architecture/interrupts.rst: -------------------------------------------------------------------------------- 1 | 中断子系统 2 | ---------- 3 | 4 | .. include:: ./interrupts.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-architecture/memorymap.rst: -------------------------------------------------------------------------------- 1 | 地址空间映射 2 | ------------ 3 | 4 | .. only:: sg2002 5 | 6 | .. include:: ./memorymap_sg2002.table.rst 7 | 8 | .. only:: sg2000 9 | 10 | .. include:: ./memorymap_sg2000.table.rst 11 | 12 | \* 对保留地址空间进行读写操作，将可能产生无法预期之结果 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-architecture/package_pin.rst: -------------------------------------------------------------------------------- 1 | 封装与管脚分布 2 | -------------- 3 | 4 | 封装 5 | ~~~~ 6 | 7 | .. only:: sg2002 8 | 9 | 使用 QFN 封装, 封装尺寸为 9mm x 9mm x 0.9mm。管脚间距为 0.35mm。管脚总数为 88 个。详细封装尺寸请参考下图。 10 | 11 | .. _diagram_package_top: 12 | .. figure:: ../../../../media/image2.png 13 | 14 | 封装外观尺寸, 上视图 15 | 16 | .. _diagram_package_bottom: 17 | .. figure:: ../../../../media/image3.png 18 | 19 | 封装外观尺寸, 底视图 20 | 21 | .. _diagram_package_pins: 22 | .. figure:: ../../../../media/image4.png 23 | 24 | 管脚分布图 25 | 26 | .. only:: sg2000 27 | 28 | 使用 IFBGA 封装, 封装尺寸为 10mmx10mmx1.9mm. 管脚间距为 0.65mm. 管脚总数为 205 个 。详细封装尺寸请参考下图。 29 | 30 | .. _diagram_package_top_sg2000: 31 | .. figure:: ../../../../media/image2_sg2000.png 32 | 33 | 封装外观尺寸, 上视图 34 | 35 | .. _diagram_package_bottom_sg2000: 36 | .. figure:: ../../../../media/image3_sg2000.png 37 | 38 | 封装外观尺寸, 底视图 39 | 40 | .. _diagram_package_pins_sg2000: 41 | .. figure:: ../../../../media/image4_sg2000.png 42 | 43 | 管脚分布图 44 | 45 | 管脚信息描述 46 | ~~~~~~~~~~~~ 47 | 48 | .. only:: sg2002 49 | 50 | .. include:: ./package_pin_sg2002.table.rst 51 | 52 | .. only:: sg2000 53 | 54 | .. include:: ./package_pin_sg2000.table.rst 55 | 56 | 管脚默认状态 57 | ~~~~~~~~~~~~ 58 | 59 | .. only:: sg2002 60 | 61 | .. _diagram_pins_default_status: 62 | .. figure:: ../../../../media/image5.png 63 | :align: center 64 | 65 | 管脚默认状态表(QFN) 66 | 67 | .. only:: sg2000 68 | 69 | .. _diagram_pins_default_status_sg2000: 70 | .. figure:: ../../../../media/image5_sg2000.png 71 | :align: center 72 | 73 | 管脚默认状态表(IFBGA) (1) 74 | 75 | .. _diagram_pins_default_status_2_sg2000: 76 | .. figure:: ../../../../media/image5_2_sg2000.png 77 | :align: center 78 | 79 | 管脚默认状态表(IFBGA) (2) 80 | 81 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-architecture/processors.rst: -------------------------------------------------------------------------------- 1 | 处理器子系统 2 | ------------ 3 | 4 | 本芯片除了一个小核处理器 (RISC-V C906@700MHz) 外, 还有两个大核主处理器: RISC-V C906@1GHz 和 ARM Cortex-A53@1GHz。大核与小核有两种组合模式, 通过管脚 GPIO_RTX 的外围电路控制进行切换 (具体参考 datasheet): 5 | 6 | - 大核 (RISC-V C906@1GHz) + 小核 (RISC-V C906@700MHz)。 7 | 8 | - 大核 (ARM Cortex-A53@1GHz) + 小核 (RISC-V C906@700MHz)。 9 | 10 | ARM Cortex-A53@1GHz 处理器具有以下特点： 11 | 12 | - 处理器工作频率最高可达 1.0 GHz。 13 | 14 | - 支持 Neon。 15 | 16 | - 支持浮点运算单元 FPU。 17 | 18 | - L1 Cache 包含 32KB Instruction Cache 和 32KB Data Cache。 19 | 20 | - 128KB L2 cache。 21 | 22 | - 支持 MMU (Memory Management Unit) 。 23 | 24 | - 处理器内部集成中断控制器。 25 | 26 | - 支持 JTAG 调试接口。 27 | 28 | RISC-V C906@1GHz 处理器具有以下特点： 29 | 30 | - 处理器工作频率最高可达 1.0GHz。 31 | 32 | - 集成矢量执行单元，浮点协处理器。 33 | 34 | - L1 Cache 包含32KB Instruction Cache 和 64KB Data Cache。 35 | 36 | - 支持 MMU (Memory Management Unit) 。 37 | 38 | - 处理器内部集成中断控制器。 39 | 40 | - 支持 JTAG 调试接口。 41 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-control/0.index.rst: -------------------------------------------------------------------------------- 1 | 系统控制器 2 | ========== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./function_description.rst 9 | ./registers.rst 10 | 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-control/function_description.rst: -------------------------------------------------------------------------------- 1 | 功能描述 2 | -------- 3 | 4 | 全局复位使能 5 | ~~~~~~~~~~~~ 6 | 7 | 系统全局软复位、Debug 复位跟 WatchDog 8 | 复位需要透过配置 reg_sw_root_reset_en 寄存器以使能。详细在 reg_sw_root_reset_en 有各比特之说明。 9 | 10 | .. _section_system_control_function_description_sys_dma_channel_map: 11 | 12 | 系统 DMA 通道映射 13 | ~~~~~~~~~~~~~~~~~ 14 | 15 | 本芯片系统 DMA 内建 8 通道，各自配置 0 ~ 7 通道请求接口。而 0 ~ 7 的通道请求由系统控制寄存器 sdma_dma_ch_remap0、sdma_dma_ch_remap1 映射至下表外设接口之一。注意不能将多个通道配置为同一外设接口。 16 | 17 | 配置步骤： 18 | 19 | 配置 DMA 信道映像寄存器 sdma_dma_ch_remap0、sdma_dma_ch_remap1、update_dma_remp_0_3、update_dma_remp_4_7 写1，使映射生效。 20 | 21 | 系统 DMA 通道映射如下表： 22 | 23 | .. include:: ./system_dma_channel_mapping.table.rst 24 | 25 | DDR AXI Urgent/Qos 配置 26 | ~~~~~~~~~~~~~~~~~~~~~~~ 27 | 28 | 可以由控制系统控制器的 ddr_axi_urgent_ow、ddr_axi_urgent、ddr_axi_qos_0、ddr_axi_qos_1 配置来自子系统之 AXI 传输优先级，详细说明参照 DDR 控制器章节 :ref:`section_ddr`。 29 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-control/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 系统控制器通过寄存器实现对芯片的一些系统控制及使能，包含系统软复位，时钟控制等。复位时钟已在其他章节说明，本章节描述一些其他系统功能模块之配置及状态寄存器。 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-control/registers.rst: -------------------------------------------------------------------------------- 1 | 系统控制寄存器 2 | -------------- 3 | 4 | 系统控制寄存器概览 5 | ~~~~~~~~~~~~~~~~~~ 6 | 7 | Bass address 0x03000000 8 | 9 | .. include:: ./system_control_registers_overview.table.rst 10 | 11 | 系统控制寄存器描述 12 | ~~~~~~~~~~~~~~~~~~ 13 | 14 | .. include:: ./system_control_registers_description.table.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-overview/0.index.rst: -------------------------------------------------------------------------------- 1 | 系统概述 2 | ======== 3 | 4 | .. only:: sg2002 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./introduction.rst 10 | ./system-block-diagram.rst 11 | ./features.rst 12 | 13 | .. only:: sg2000 14 | 15 | .. toctree:: 16 | :maxdepth: 2 17 | 18 | ./introduction_sg2000.rst 19 | ./system-block-diagram_sg2000.rst 20 | ./features_sg2000.rst -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-overview/introduction.rst: -------------------------------------------------------------------------------- 1 | 介绍 2 | ---- 3 | 4 | SG2002 是面向 AIot 领域推出的高性能、低功耗芯片，内置多个强劲内核：2 x C906、1 x Arm Cortex A53、1 x 8051，用户可以根据需求快速切换内核。同时集成硬件编解码器：H.264 视频压缩编解码器, H.265 视频压缩编码器和 ISP，支持配置了专业级的视频图像 ISP：HDR 宽动态、3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法。 5 | 6 | 芯片更集成了自研 TPU，可提供 1.0TOPS IN8 的算力。 特殊设计的 TPU 调度引擎能有效地为所有的张量处理器核心提供极高的带宽数据流。 7 | 8 | 同时支持丰富的外设接口：5 x I2C、2 x SDIO3.0、2 x I2S、15 x PWM、1 x USB 2.0 等，满足多种场景需求。 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-overview/introduction_sg2000.rst: -------------------------------------------------------------------------------- 1 | 介绍 2 | ---- 3 | 4 | SG2000 是面向 AIot 领域推出的高性能、低功耗芯片，内置多个强劲内核：2 x C906、1 x Arm Cortex A53、1 x 8051，用户可以根据需求快速切换内核。同时集成硬件编解码器：H.264 视频压缩编解码器, H.265 视频压缩编码器和 ISP，支持配置了专业级的视频图像 ISP：HDR 宽动态、3D 降噪、除雾、镜头畸变校正等多种图像增强和矫正算法。 5 | 6 | 芯片更集成了自研 TPU，可提供 0.5TOPS IN8 的算力。 特殊设计的 TPU 调度引擎能有效地为所有的张量处理器核心提供极高的带宽数据流。 7 | 8 | 同时支持丰富的外设接口：6 x I2C、2 x SDIO3.0、2 x I2S、15 x PWM、1 x USB 2.0 等，满足多种场景需求。 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-overview/system-block-diagram.rst: -------------------------------------------------------------------------------- 1 | 系统框架图 2 | ---------- 3 | 4 | .. _diagram_system_block: 5 | .. figure:: ../../../../media/image1.png 6 | :align: center 7 | 8 | 系统框架 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/system-overview/system-block-diagram_sg2000.rst: -------------------------------------------------------------------------------- 1 | 系统框架图 2 | ---------- 3 | 4 | .. _diagram_system_block_sg2000: 5 | .. figure:: ../../../../media/image1_sg2000.png 6 | :align: center 7 | 8 | 系统框架 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/0.index.rst: -------------------------------------------------------------------------------- 1 | 定时器 2 | ====== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers_overview.rst 12 | ./registers_description.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ----- 3 | 4 | 定时器具有以下特点： 5 | 6 | - 32bit 减法定时器/计数器。 7 | 8 | - 支持 2 种计数模式：自由运行模式、用户定义计数模式。 9 | 10 | - 系统可读取当前的计数值。 11 | 12 | 当计数值递减到 0 时，会产生一个中断。 -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/functionalities.rst: -------------------------------------------------------------------------------- 1 | 功能描述 2 | --------- 3 | 4 | Timer 基于一个 32bit 减法计数器。计数器的值在每个计数时钟的上升沿减 1。当计数值递减到零，Timer 将产生一个中断。 5 | 6 | Timer 有以下 2 种计数模式： 7 | 8 | - 自由运行模式: 定时器持续计数，当计数值减到 0 时又自动回转到其最大值，并继续计数。计数长度最大值为 0xFFFF_FFFF。 9 | 10 | - 用户定义计数模式: 定时器持续计数，当计数值减到 0 时从 TimerNLoadCount (N=1~8) 寄存器中再次载入初值并继续计数。 11 | 12 | 对定时器载入计数初值的方法如下： 13 | 14 | 通过写 TimerNLoadCount (N=1~8) 寄存器可对定时器载入计数初值。 15 | 16 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 系统配置 8 个 Timer 模块。用作定时、计数功能，可以供应用程序实现定时和计数，也可以供操作系统实现系统时钟。 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/registers_description.rst: -------------------------------------------------------------------------------- 1 | Timer 寄存器描述 2 | ---------------- 3 | 4 | .. include:: ./timer_registers_description.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/registers_overview.rst: -------------------------------------------------------------------------------- 1 | Timer 寄存器概览 2 | ---------------- 3 | 4 | Timer 寄存器通过总线存取。 5 | 6 | Timer 寄存器概览如 :ref:`table_timer_registers_overview` 所示。 7 | 8 | .. include:: ./timer_registers_overview.table.rst 9 | 10 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/timer/working_method.rst: -------------------------------------------------------------------------------- 1 | 工作方式 2 | --------- 3 | 4 | 初始化 5 | ~~~~~~ 6 | 7 | - 步骤 1: 写 TimerNLoadCount (N=1~8) 寄存器，为 Timer 载入计数初值。 8 | 9 | - 步骤 2: 设置 TimerNControlReg[2:0] (N=1~8) 寄存器，选择 Timer 计数模式，屏蔽 Timer 中断，启动 Timer 开始计数。 10 | 11 | 中断处理 12 | ~~~~~~~~ 13 | 14 | 定时器产生中断时，操作步骤如下： 15 | 16 | - 步骤 1: 读 TimerNEOI (N=1~8) 寄存器，清除 TimerN 中断。 17 | 18 | - 步骤 2: 执行等待该中断的进程。 19 | 20 | - 步骤 3: 进程完成后，恢复执行执行被中断的程序。 21 | 22 | 时钟选择 23 | ~~~~~~~~ 24 | 25 | 系统 Timer 可选 25MHz /32KHz 计数时钟。使用 reg_timer_clk_sel 做选择。 26 | 27 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/video/0.index.rst: -------------------------------------------------------------------------------- 1 | 视频接口 2 | ======== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./vi.rst 8 | ./vdp.rst 9 | ./mipi_rx.rst 10 | ./mipi_tx.rst 11 | 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/0.index.rst: -------------------------------------------------------------------------------- 1 | 看门狗 2 | ====== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers_overview.rst 12 | ./registers_description.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/features.rst: -------------------------------------------------------------------------------- 1 | 特点 2 | ---- 3 | 4 | WatchDog 具备以下特点： 5 | 6 | - 配置一个 32bit 递减计数器。 7 | 8 | - 支持计数初值（即时间间隔）可配置。 9 | 10 | - 支持 WatchDog 重启保护，防止误动作导致 WatchDog 被重启。 11 | 12 | - 支持复位信号产生。 13 | 14 | - 支持超时中断产生。 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/functionalities.rst: -------------------------------------------------------------------------------- 1 | 功能描述 2 | -------- 3 | 4 | 系统通过系统总线给 WatchDog 配置寄存器参数值。WatchDog 定时发出 WDT_INTR 中断请求给系统，并在系统没有响应中断的情况下（如：死机），发出 WDT_SYS_RST 复位信号，使系统复位，达到监控系统运行的目的。 5 | 6 | 应用框图 7 | ~~~~~~~~ 8 | 9 | .. _diagram_watchdog_block: 10 | .. figure:: ../../../../media/image13.png 11 | 12 | WatchDog 应用框图 13 | 14 | 功能原理 15 | ~~~~~~~~ 16 | 17 | WatchDog 运行基于 1个 32bit 减法计数器。其计数初值有两个来源，分别从 WDT_ITORR 和 WDT_TORR 载入，并依据 ITOR_MODE 的值计算得到（具体计算方法参考 :ref:`table_wdt_torr` 中的描述）。WDT_ITORR 用于上电后 WatchDog 的第一次定时器计数，其后的定时器计数基于 WDT_TORR 得到。 18 | 19 | 在 WatchDog 时钟使能情况下，计数值在每个计数时钟的上升沿减 1。当计数值递减到 0, WatchDog 将产生一个中断。然后在下一个计数时钟上升沿，计数器又从寄存器 WDT_TORR 中重新载入计数初值，开始递减计数。 20 | 21 | 用户可以通过设置寄存器 WDT_CR[1] 决定是否在计数器的计数值第一次计数递减到 0 时立刻发出复位信号 WDT_SYS_RST，如果设置为 0 则立即发出复位信号，否则如果为 1 则产生一个中断，并开始第二次计数，如果第二次计数递减到 0 时, CPU 还没有清除 WatchDog 中断，则 WatchDog 将发出复位信号 WDT_SYS_RST, 计数器停止计数。 22 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/overview.rst: -------------------------------------------------------------------------------- 1 | 概述 2 | ---- 3 | 4 | 系统配置 4 个看门狗 (WatchDog) 模块。用于系统发生异常情况下，于一定时间后发出中断或复位信号，以中断或复位整个系统。 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/registers_description.rst: -------------------------------------------------------------------------------- 1 | WDT 寄存器描述 2 | -------------- 3 | 4 | .. include:: ./watchdog_registers_description.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/registers_overview.rst: -------------------------------------------------------------------------------- 1 | .. _section_wdt_register_overview: 2 | 3 | WDT 寄存器概览 4 | -------------- 5 | 6 | WDT 寄存器通过总线存取。包括四个 WDT, 3 个 Active Domain，1 个 No-die Domain。其基地址分别为: 7 | 8 | - WDT0 : 0x03010000 9 | 10 | - WDT1 : 0x03011000 11 | 12 | - WDT2 : 0x03012000 13 | 14 | - RTCSYS_WDT : 0x0502D000 15 | 16 | 每个 WDT 由一组控制寄存器组成，每组定义相同，概览如 :ref:`table_watchdog_register_overview` 所示。 17 | 18 | .. include:: ./watchdog_register_overview.table.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/watchdog_register_overview.table.rst: -------------------------------------------------------------------------------- 1 | .. _table_watchdog_register_overview: 2 | .. table:: WDT Registers Overview 3 | :widths: 2 1 2 4 | 5 | +----------------------+---------+------------------------------------+ 6 | | Name | Address | Description | 7 | | | Offset | | 8 | +======================+=========+====================================+ 9 | | WDT_CR | 0x000 | Control register | 10 | +----------------------+---------+------------------------------------+ 11 | | WDT_TORR | 0x004 | Timeout range register | 12 | +----------------------+---------+------------------------------------+ 13 | | WDT_CCVR | 0x008 | Current counter value register | 14 | +----------------------+---------+------------------------------------+ 15 | | WDT_CRR | 0x00c | Counter restart register | 16 | +----------------------+---------+------------------------------------+ 17 | | WDT_STAT | 0x010 | Interrupt status register | 18 | +----------------------+---------+------------------------------------+ 19 | | WDT_EOI | 0x014 | Interrupt clear register | 20 | +----------------------+---------+------------------------------------+ 21 | | WDT_TOC | 0x01C | Time Out Count | 22 | +----------------------+---------+------------------------------------+ 23 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/cn/watchdog/working_method.rst: -------------------------------------------------------------------------------- 1 | 工作方式 2 | -------- 3 | 4 | 计数时钟频率配置 5 | ~~~~~~~~~~~~~~~~ 6 | 7 | WatchDog 计数时钟为 25MHz/32KHz 时钟。使用 reg_wdt_clk_sel 做选择。 8 | 9 | 系统初始化配置 10 | ~~~~~~~~~~~~~~ 11 | 12 | 系统上电复位后 WatchDog 计数器处于停止计数状态，在系统初始化过程中需要将 WatchDog 初始化并启动其运行。WatchDog 的初始化过程如下： 13 | 14 | - 步骤 1: 写寄存器 WDT_TORR, 设置 WatchDog 计数初值。 15 | 16 | - 步骤 2: 写寄存器 WDT_CR[1]，设置 WatchDog 计数超时响应模式。 17 | 18 | - 步骤 3: 写寄存器 WDT_CR[0]，启动 WatchDog 计数。 19 | 20 | 中断处理过程 21 | ~~~~~~~~~~~~ 22 | 23 | 系统收到 WatchDog 发出的中断后，应及时清除其中断状态。 24 | 25 | WatchDog 中断处理的过程如下： 26 | 27 | - 步骤 1: 读寄存器 WDT_EOI, 清除 WatchDog 的中断状态。 28 | 29 | - 步骤 2: 向寄存器 WDT_CRR 写入 0x76, 重启 WatchDog。 30 | 31 | 关闭 WatchDog 32 | ~~~~~~~~~~~~~ 33 | 34 | 向寄存器 WDT_CR[0] 写入 0 或 1 控制 WatchDog的状态: 35 | 36 | - 0: WDT 关闭。 37 | 38 | - 1: WDT 开启。启动后只有系统复位能够使 WDT 关闭。 39 | 40 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/audio/0.index.rst: -------------------------------------------------------------------------------- 1 | Audio Interface 2 | =============== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./aiao.rst 8 | ./audio_codec.rst 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/audio/audio_codec.rst: -------------------------------------------------------------------------------- 1 | Audio Codec 2 | ----------- 3 | 4 | Overview 5 | ~~~~~~~~ 6 | 7 | The chip integrates high-performance Audio Codec, including stereo playback DAC (90dB DR A-Weighted), which supports two single-ended lineout outputs; stereo recording ADC (90dB DR A-Weighted), which supports stereo single-ended input. 8 | 9 | Features 10 | ~~~~~~~~ 11 | 12 | - 90dB DR A-Weighted Stereo DAC 13 | 14 | - Stereo single-ended Lineout output 15 | 16 | - DAC digital volume control range: -24dB ~ 0dB 17 | 18 | - DAC supports 8kHz ~ 48kHz sampling rate 19 | 20 | - 90dB DR A-Weighted Stereo ADC 21 | 22 | - ADC PGA gain range: 0db ~ 48dB 23 | 24 | - ADC supports 8kHz ~ 48kHz sampling rate 25 | 26 | - ADC supports Mic in stereo single-ended input or Line in stereo single-ended input 27 | 28 | Audio Codec Registers 29 | ~~~~~~~~~~~~~~~~~~~~~ 30 | 31 | Audio DAC/ADC Register Overview 32 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 33 | 34 | .. include:: ../../contents-share/audio/audio_dac_adc_registers_overview.table.rst 35 | 36 | Audio ADC Register Description 37 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 38 | 39 | .. include:: ../../contents-share/audio/audio_adc_registers_description.table.rst 40 | 41 | Audio DAC Register Description 42 | ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 43 | 44 | .. include:: ../../contents-share/audio/audio_dac_registers_description.table.rst 45 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_clock: 2 | 3 | Clock 4 | ===== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | overview.rst 10 | function_block.rst 11 | clock_tree.rst 12 | pll_configure.rst 13 | div_configure.rst 14 | pll_reg_overview.rst 15 | pll_reg_description.rst 16 | div_reg_overview.rst 17 | div_reg_description.rst 18 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/clock_tree.rst: -------------------------------------------------------------------------------- 1 | Clock resources and frequency division structure 2 | ------------------------------------------------ 3 | 4 | The clock of the entire system is mainly divided into two parts: PLL clocks and IP/Subsystem clocks. 5 | 6 | The system clock source mainly comes from external XTAL. XTAL has its frequency multiplied by a PLL. As shown in :ref:`diagram_clock_tree`, for each IP, XTAL is generally used as the initial clock source. After being multiplied by one or more PLL clocks, each is processed by a frequency division circuit and then used as clcok input for an IP or subsystem. 7 | 8 | .. _diagram_clock_tree: 9 | .. figure:: ../../../../media/image8.png 10 | :align: center 11 | 12 | Clock source frequency division diagram 13 | 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/div_reg_description.rst: -------------------------------------------------------------------------------- 1 | IP/Subsystem Clcok Control Registers Description 2 | ------------------------------------------------ 3 | 4 | .. include:: ../../contents-share/clock/div_crg_registers_description.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/div_reg_overview.rst: -------------------------------------------------------------------------------- 1 | IP/Subsystem Clcok Control Registers Overview 2 | --------------------------------------------- 3 | 4 | .. include:: ../../contents-share/clock/div_crg_registers_overview.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/function_block.rst: -------------------------------------------------------------------------------- 1 | Functional block diagram 2 | ------------------------ 3 | 4 | .. _diagram_clock_block: 5 | .. figure:: ../../../../media/image7.png 6 | :align: center 7 | 8 | Clock management block diagram 9 | 10 | XTAL_XIN is the PLL input clock, fixedly connected to the 25MHz crystal; RTC_XIN is the RTC input clock, fixedly connected to the 32.768KHz crystal. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The clock management module manages the chip clock, including: 5 | 6 | - Management and control of clock inputs 7 | 8 | - PLL clock source and related frequency multiplication and frequency division control 9 | 10 | - Clock division and control 11 | 12 | - Generate the working clock of each module 13 | 14 | - Management and control of clock outputs -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/pll_configure.rst: -------------------------------------------------------------------------------- 1 | PLL configuration 2 | ----------------- 3 | 4 | See :ref:`table_pll_configure`, the chip has 8 built-in PLLs (not counting Analog IP built-in PLL), which are divided into two types of PLL: integer frequency multiplication and fractional frequency multiplication. 5 | 6 | For more information on PLL Configuration/Control Registers, refer to :ref:`section_clock_pll_reg_overview` and :ref:`section_clock_pll_reg_description`. 7 | 8 | .. include:: ../../contents-share/clock/pll_configure_params.table.rst 9 | 10 | Integer Multiplier PLL 11 | ~~~~~~~~~~~~~~~~~~~~~~ 12 | 13 | Tuning the integer PLL flow: 14 | 15 | 1. When adjusting, you must turn off the clock related to this PLL or select the clock source as XTAL or other PLL. 16 | 17 | 2. Configure the \*_pll_csr register according to the integer PLL parameter table 18 | 19 | 3. Clear \*_pll_pwd 20 | 21 | .. include:: ../../contents-share/clock/pll_configure_integer_params.table.rst 22 | 23 | Fractional Multiplier PLL 24 | ~~~~~~~~~~~~~~~~~~~~~~~~~ 25 | 26 | Adjust fractional PLL process: 27 | 28 | 1. When using this PLL, the IP clock must be turned off or XTAL or other stable clock sources must be selected. 29 | 30 | 2. Configure \*_ssc_syn_src_en to enable the synthesizer clock 31 | 32 | 3. Configure \*_ssc_syn_set according to PLL frequency requirements, 33 | 34 | 4. Toggle \*_ssc_syn_up to make the configuration take effect 35 | 36 | 5. Configure the \*_pll_csr register according to the integer PLL parameter table 37 | 38 | 6. Clear \*_pll_pwd 39 | 40 | .. include:: ../../contents-share/clock/pll_configure_fractional_params.table.rst 41 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/pll_reg_description.rst: -------------------------------------------------------------------------------- 1 | .. _section_clock_pll_reg_description: 2 | 3 | PLL Control Register Description 4 | -------------------------------- 5 | 6 | PLL_G2 Register Description 7 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 | 9 | .. include:: ../../contents-share/clock/pll_g2_registers_description.table.rst 10 | 11 | PLL_G6 Register Description 12 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 | 14 | .. include:: ../../contents-share/clock/pll_g6_registers_description.table.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/clock/pll_reg_overview.rst: -------------------------------------------------------------------------------- 1 | .. _section_clock_pll_reg_overview: 2 | 3 | PLL Control Register Overview 4 | ----------------------------- 5 | 6 | .. include:: ../../contents-share/clock/pll_crg_registers_overview.table.rst 7 | 8 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/ddr/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_ddr: 2 | 3 | DDR Controller 4 | ============== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./features.rst 11 | ./functionalities.rst 12 | ./working_method.rst 13 | ./axi_registers.rst 14 | ./ddrc_registers.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/ddr/axi_registers.rst: -------------------------------------------------------------------------------- 1 | AXI Registers 2 | ------------- 3 | 4 | AXI Register Overview 5 | ~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | .. include:: ../../contents-share/ddr/axi_registers_overview.table.rst 8 | 9 | AXI Register Description (Base address: 0x0800_4000) 10 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 | 12 | .. include:: ../../contents-share/ddr/axi_registers_description_0x0800_4000.table.rst 13 | 14 | 15 | AXI Register Description (Base address: 0x0800_8000) 16 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 17 | 18 | .. include:: ../../contents-share/ddr/axi_registers_description_0x0800_8000.table.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/ddr/ddrc_registers.rst: -------------------------------------------------------------------------------- 1 | DDRC Registers 2 | -------------- 3 | 4 | DDRC Register Overview 5 | ~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | Base address: 0x0800_4000 8 | 9 | .. include:: ../../contents-share/ddr/ddrc_registers_overview.table.rst 10 | 11 | DDRC Register Description 12 | ~~~~~~~~~~~~~~~~~~~~~~~~~ 13 | 14 | Base address: 0x0800_4000 15 | 16 | .. include:: ../../contents-share/ddr/ddrc_registers_description.table.rst 17 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/ddr/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | Function Features: 5 | 6 | - Support: 7 | 8 | - DDR2 maximum data rate 1333 Mbps. 9 | 10 | - DDR3 maximum data rate 1866 Mbps. 11 | 12 | - Supports interface data width 16-bit. 13 | 14 | - Supports single channel, single rank. 15 | 16 | - Support automatic refresh control. 17 | 18 | - Support priority control. 19 | 20 | - Support data traffic statistics. 21 | 22 | - Support low power consumption mode. 23 | 24 | - Support address mapping. 25 | 26 | - Support pin multiplexing. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/ddr/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The DDR controller implements data access to dynamic memory (DRAM). It converts the data access commands of each master device in the SoC into dynamic memory commands that comply with the JEDEC standard, and schedules them appropriately, thereby improving the use efficiency of the dynamic memory bus. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/ddr/working_method.rst: -------------------------------------------------------------------------------- 1 | Way of Working 2 | -------------- 3 | 4 | Soft Reset 5 | ~~~~~~~~~~ 6 | 7 | Soft reset is not supported. 8 | 9 | DDR Initialization Configuration Process 10 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 | 12 | This controller initialization process is provided in the form of a software package. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/disclaimer.rst: -------------------------------------------------------------------------------- 1 | Disclaimer 2 | ---------- 3 | 4 | .. figure:: ../../../media/SOPHON-LOGO.png 5 | :align: center 6 | :alt: SOPHGO LOGO 7 | :scale: 50% 8 | 9 | | **Contact Us** 10 | 11 | :Official website: https://www.sophgo.com/ 12 | 13 | :Document publishing website: https://github.com/sophgo/sophgo-doc 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/dma/0.index.rst: -------------------------------------------------------------------------------- 1 | DMA Controller 2 | ============== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers.rst 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/dma/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | DMAC features are as follows: 5 | 6 | a. A maximum of 8 DMA channels can be established simultaneously. 7 | 8 | b. The data source and data purpose of the transmission can be set to memory or device. 9 | 10 | c. Only one-way transfer of configuration is allowed. 11 | 12 | d. Provide DMA transmission pause, resume, and cancellation. 13 | 14 | e. Support DMA Burst length configuration. 15 | 16 | f. Provide DMA channel priority configuration. 17 | 18 | g. When channel data is transmitted between devices, flow control can be handed over to the device. 19 | 20 | h. Support hardware linked list function. 21 | 22 | i. Supports channel locking, and other channel requests before the locked channel is completed will be ignored. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/dma/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | DMA (Direct Memory Access) does not require the CPU to interfere with data one by one. Data can be transferred directly between the memory and the device. This mechanism greatly reduces the CPU control time and increases the data transfer rate. It is very suitable for use in large amounts of data transfer. When the chip is working, it often requires multiple channels of data transmission at the same time. One channel requires a DMA hardware support, and the DMAC (DMA Controller) is responsible for the control of multiple channels. Diagram :ref:`diagram_dma_hardware_control_process` is a DMAC hardware control flow chart. The source and destination devices can be in different AXI sinks. 5 | 6 | .. _diagram_dma_hardware_control_process: 7 | .. figure:: ../../../../media/image9.png 8 | 9 | DMAC hardware control flow diagram 10 | 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/dma/registers.rst: -------------------------------------------------------------------------------- 1 | .. _section_dma_registers: 2 | 3 | DMAC Resisters 4 | -------------- 5 | 6 | .. include:: ../../contents-share/dma/dmac_registers.table.rst 7 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/initialization/0.index.rst: -------------------------------------------------------------------------------- 1 | Boot and Upgrade 2 | ================ 3 | 4 | Overview 5 | -------- 6 | 7 | The chip is booted from the built-in ROM (BOOTROM). When the chip is reset, it will detect whether there is a weak pull-up or weak pull-down on the two pins (EMMC_DAT3, EMMC_DAT0) to confirm the type of memory device currently selected. 8 | 9 | Secure boot chips will check during boot and chip upgrade to ensure that the software being executed or upgraded is safe. 10 | 11 | Correspondence between startup mode and corresponding signal latch value 12 | ------------------------------------------------------------------------ 13 | 14 | - Support booting from SPI Nor Flash (EMMC_DAT3 pull down, EMMC_DAT0 pull up) 15 | 16 | - Support booting from SPI Nand Flash (EMMC_DAT3 pull down, EMMC_DAT0 pull down) 17 | 18 | - Support booting from eMMC (EMMC_DAT3 pull up, EMMC_DAT0 pull up) 19 | 20 | Note: SD0 and eMMC domain share IO power, because the SD card run with 3.0V by default, and eMMC is mostly 1.8V, basically eMMC is not supported unless SD0 does not connect with the SD card. 21 | 22 | Image burning mode 23 | ------------------ 24 | 25 | - Supports image burning via SD card. 26 | 27 | - Supports image burning through USB device. 28 | 29 | - If there is an image in flash, support software upgrade through the network. 30 | 31 | Secure boot 32 | ----------- 33 | 34 | - Support secure boot and upgrade. 35 | 36 | - AES/DES/SM4 hardware encryption and decryption. 37 | 38 | - SHA/TRNG/Secure Efuse security hardware. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/mcu/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_8051: 2 | 3 | 8051 Subsystem 4 | ============== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./features.rst 11 | ./working_method.rst 12 | ./registers_overview.rst 13 | ./registers_description.rst 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/mcu/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | The 8051 microprocessor has the following features: 5 | 6 | - Supports standard 8051 instruction set. 7 | 8 | - Frequency range: 25MHz ~ 300 MHz. 9 | 10 | - Debugging function: single step execution/jump2pc/snapshot PSW, DPTR, PC. 11 | 12 | - Support 32bit data access. 13 | 14 | - Reset vector configurable to system AHB SRAM/DRAM/SPINOR. 15 | 16 | - Support WFI (Clock gating). 17 | 18 | - Supports code banking (max 64x64 KB). 19 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/mcu/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The 8051 subsystem is located within RTCSYS and is independently powered. System software can use the 8051 to manage wake conditions and wake the system while the system is asleep, and communicate with external devices through peripheral controllers. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/mcu/registers_description.rst: -------------------------------------------------------------------------------- 1 | 8051 Subsystem Register Description 2 | ----------------------------------- 3 | 4 | The registers of the 8051 subsystem are defined in the RTC CTRL register, please refer to the :ref:`section_rtc_ctrl_register_description` section for details. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/mcu/registers_overview.rst: -------------------------------------------------------------------------------- 1 | 8051 Subsystem Register Overview 2 | -------------------------------- 3 | 4 | The registers of the 8051 subsystem are defined in the RTC CTRL register. For details, refer to the RTC_CTRL_REG section of the :ref:`section_rtc_register_overview` chapter. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/network/0.index.rst: -------------------------------------------------------------------------------- 1 | Network Interface 2 | ================= 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./eth_mac.rst 8 | ./eth_phy.rst 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/network/eth_phy.rst: -------------------------------------------------------------------------------- 1 | EthernetPHY 2 | ----------- 3 | 4 | Overview 5 | ~~~~~~~~ 6 | 7 | The chip provides a built-in Ethernet 10/100 Base-TX compliant PHY interface. 8 | 9 | Function Description 10 | ~~~~~~~~~~~~~~~~~~~~ 11 | 12 | - Supports IEEE 802.3 10/100 Base-TX compliant. 13 | 14 | - Supports automatic negotiation of transmission speed and full-half-duplex working mode. 15 | 16 | - Supports the automatic movement and flip function of Ethernet line crossover lines or direct lines. 17 | 18 | - Supports Ethernet WOL (Wake on Lan) function. 19 | 20 | Function Configuration Diagram Description 21 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 | 23 | .. _diagram_ethernet_phy: 24 | .. figure:: ../../../../media/image28.png 25 | :align: center 26 | 27 | Built-in 10/100 Ethernet PHY block diagram 28 | 29 | The 10/100Mbps transmission and reception functions are on standard category 5 (CAT5) twisted pair cables, and the transmission and reception signals are connected to the RJ45 standard interface through a transformer. 30 | 31 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/peripherals/0.index.rst: -------------------------------------------------------------------------------- 1 | Peripherals 2 | =========== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./i2c.rst 8 | ./uart.rst 9 | ./spi.rst 10 | ./sdmmc.rst 11 | ./gpio.rst 12 | ./usb.rst 13 | ./saradc.rst 14 | ./temperature.rst 15 | ./pwm.rst 16 | ./keyscan.rst 17 | ./wiegand.rst 18 | ./irrx.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/pinmux-pinctrl/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_pinmux_pinctrl: 2 | 3 | PinMux and PinCtrl 4 | ================== 5 | 6 | .. only:: sg2002 7 | 8 | For information on pin multiplexing and pin control, please refer directly to the online table: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/04_SG2002/04_SG2002_PINOUT.xlsx 9 | 10 | .. only:: sg2000 11 | 12 | For information on pin multiplexing and pin control, please refer directly to the online table: https://github.com/sophgo/sophgo-hardware/blob/master/SG200X/03_SG2000/04_SG2000_PINOUT.xlsx 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/power/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_power: 2 | 3 | Power Management 4 | ================ 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./clock_control.rst 11 | ./ddr_powerctrl.rst 12 | ./voltage_adjustment.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/power/clock_control.rst: -------------------------------------------------------------------------------- 1 | Clock Control 2 | ------------- 3 | 4 | Turn off unnecessary clock dividers 5 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | Refer to the :ref:`section_clock` configuration chapter and turn off the unused clock divider according to the clock source required by each module, to achieve the purpose of saving power consumption. 8 | 9 | Adjust the operating frequency of the module 10 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 | 12 | Select a lower clock source according to the clock specifications required by each module. There are many frequency division configurations to reduce the module operating frequency. It should be noted that reducing the frequency of a single module may not necessarily reduce the overall power consumption. 13 | 14 | Module-level low-power control 15 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 16 | 17 | - Analog module: MIPI/USB/ETH/AUD related register settings, turn off unused modules or enter low power consumption mode. 18 | 19 | - Digital modules: Turn off the clocks of unnecessary digital modules according to hardware and specifications. 20 | 21 | Shut down unused PLLs 22 | ~~~~~~~~~~~~~~~~~~~~~ 23 | 24 | Referring to the PLL configuration, you can Powerdown the PLL that is not needed to save power consumption. 25 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/power/ddr_powerctrl.rst: -------------------------------------------------------------------------------- 1 | DDR low power control 2 | --------------------- 3 | 4 | After the bus is not accessed for a period of time, the DDR controller will automatically enter the "Self refresh" and "Power down" states to reduce system power consumption. 5 | 6 | In some scenarios, it is impossible to find a large enough gap to enter "self refresh" due to intermittent access. At this time, you can also consider using the built-in statistical register to access the data volume. To confirm whether the bandwidth is excessive, you can consider directly reducing the frequency. 7 | 8 | The DDR controller supports dynamic frequency adjustment. However, adjusting the frequency will temporarily stop DDR access for a period of time. Therefore, in order to reduce interruption time, which may make real-time application buffer underflow or overflow, it is limited to two levels: 50% and 100%. 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/power/voltage_adjustment.rst: -------------------------------------------------------------------------------- 1 | Voltage Regulation 2 | ------------------ 3 | 4 | By default the chip uses PWM0 to control VDDC voltage regulation. The following is an example of using PWM to control the DCDC output voltage. 5 | 6 | .. _diagram_example_control_dcdc_with_pwm: 7 | .. figure:: ../../../../media/image14.png 8 | :align: center 9 | 10 | Example of controlling DCDC voltage using PWM 11 | 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/reset/0.index.rst: -------------------------------------------------------------------------------- 1 | Reset 2 | ===== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./reset_control.rst 9 | ./reset_registers.rst 10 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/reset/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The reset management module uniformly manages the reset and timing of the entire chip, subsystem, and functional modules. 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/reset/reset_registers.rst: -------------------------------------------------------------------------------- 1 | .. _section_reset_configure_registers: 2 | 3 | Reset configuration register 4 | ---------------------------- 5 | 6 | Reset configuration register overview 7 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8 | 9 | Base address 0x03003000 10 | 11 | .. include:: ../../contents-share/reset/reset_registers_overview.table.rst 12 | 13 | Reset configuration register description 14 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 15 | 16 | .. include:: ../../contents-share/reset/reset_registers_describe.table.rst 17 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/rtc/0.index.rst: -------------------------------------------------------------------------------- 1 | .. _section_rtc: 2 | 3 | Real Time Clock 4 | =============== 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./overview.rst 10 | ./features.rst 11 | ./functionalities.rst 12 | ./working_method.rst 13 | ./registers_overview.rst 14 | ./registers_description.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/rtc/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | RTC has the following characteristics: 5 | 6 | - Provide chip system reset signal 7 | 8 | - Provides 32,768 Hz count clock (error < ±1%) 9 | 10 | - Provides 32-bit seconds counter and hardware calibration circuit, allowing second accuracy to reach 5ppm level 11 | 12 | - Support alarm clock configuration and generate alarm interrupt 13 | 14 | - Provide 2KB space SRAM, which can save software code or temporary data 15 | 16 | - Support battery low voltage detection and generate interrupts 17 | 18 | - Support button triggering the chip to wake up from sleep 19 | 20 | - Support software to trigger chip sleep, reset, or restart due to overheating 21 | 22 | - Support Watchdog to trigger chip system reset 23 | 24 | - Support alarm triggering chip to wake up from sleep 25 | 26 | - Configurable power-on and power-off sequence and reset time interval 27 | 28 | - Provides 1 ultra-low power analog seconds counter (32 bit to count from 1970~2106 year) 29 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/rtc/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The RTC (Real Time Clock) is an independently powered module in the chip. It contains a 32KHz oscillator and a Power-On-Reset (POR) sub-module, which can be used for time display and scheduled alarm produce. In addition, the hardware state machine provides triggering and timing control for chip power-on, power-off and reset. 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/rtc/registers_description.rst: -------------------------------------------------------------------------------- 1 | RTC register description 2 | ------------------------ 3 | 4 | .. include:: ../../contents-share/rtc/rtc_registers_description.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/rtc/registers_overview.rst: -------------------------------------------------------------------------------- 1 | .. _section_rtc_register_overview: 2 | 3 | RTC Register Overview 4 | --------------------- 5 | 6 | The RTC register contains multiple parts, RTC_CORE_REG, RTC_MACRO_REG and RTC_CTRL_REG. The register base addresses are different and they are all accessed through the bus. 7 | 8 | The overview of RTC_CORE_REG register is shown in :ref:`table_rtc_core_reg_overview`. 9 | 10 | .. include:: ../../contents-share/rtc/rtc_core_reg_overview.table.rst 11 | 12 | The overview of RTC_MACRO_REG register is shown in :ref:`table_rtc_macro_reg_overview`. 13 | 14 | .. include:: ../../contents-share/rtc/rtc_macro_reg_overview.table.rst 15 | 16 | The overview of RTC_CTRL_REG register is shown in :ref:`table_rtc_ctrl_reg_overview`. 17 | 18 | .. include:: ../../contents-share/rtc/rtc_ctrl_reg_overview.table.rst 19 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/security/0.index.rst: -------------------------------------------------------------------------------- 1 | Security Subsystem 2 | ================== 3 | 4 | The chip provides an independent security subsystem module responsible for providing specific security functions. 5 | 6 | The safety subsystem module includes the following safety function modules 7 | 8 | - Crypto DMA unit (CryptoDMA) 9 | 10 | - True Random Number Generator 11 | 12 | - Secure Debug Protection 13 | 14 | The cryptographic operation unit (CryptoDMA) provides hardware acceleration of symmetric key encryption, decryption and hashing (Hash). The security eFuse unit is responsible for providing system security settings and security keys for use by the security subsystem. The true random number generation unit provides qualified random numbers used by security systems. 15 | 16 | .. _diagram_security_module: 17 | .. figure:: ../../../../media/image143.png 18 | :align: center 19 | 20 | Security subsystem module 21 | 22 | .. toctree:: 23 | :maxdepth: 2 24 | 25 | ./cryptodma.rst 26 | ./trng.rst 27 | ./firewall.rst 28 | ./efuse.rst 29 | 30 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/security/efuse.rst: -------------------------------------------------------------------------------- 1 | Efuse Controller 2 | ---------------- 3 | 4 | The chip integrates 4Kbit eFuse space, and uses Efuse Ctrl to program and read Efuse. 5 | 6 | The main functions of Efuse Ctrl include: 7 | 8 | - Provides a dual eFuse bit (Double bit) protection mechanism, which consists of two physical eFuse bits forming a single bit logical effective value, which is equivalent to providing a 2Kbit register space to improve the robustness of eFuse programming or data maintenance. 9 | 10 | - After power-on reset (Power-On-Reset), the contents of efuse are automatically loaded into the register to provide the required configuration settings for the chip system and reduce the number of times required to read Efuse to increase the service life. 11 | 12 | - Provides efuse programming, reading, verification reading and power-on and power-off instructions and content security protection mechanism. 13 | 14 | The Efuse data register is divided into two areas, one is a non-safe area and the other is a safe area. The data in the non-safe area is allowed to be accessed by all modules, and the safe area only allows access to the safe modules. The non-secure area stores system configuration and public information, and the secure area stores security configuration, keys and passwords. 15 | 16 | .. _diagram_efuse_block: 17 | .. figure:: ../../../../media/image147.png 18 | :align: center 19 | 20 | eFuse CTRL modular architecture 21 | 22 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/security/trng.rst: -------------------------------------------------------------------------------- 1 | TRNG 2 | ---- 3 | 4 | Overview 5 | ~~~~~~~~ 6 | 7 | True Random Number Generator (TRNG) generates random numbers that are intended to be statistically equivalent to a uniformly distributed random data stream. . The circuit includes a Deterministic Random Bit Generator (DRBG). When seed is created and fed into the DRBG, the TRNG generates random numbers. 8 | 9 | Features 10 | ~~~~~~~~ 11 | 12 | The TRNG module has the following functional features: 13 | 14 | - Internal random seeding operation 15 | - 128-bit random number generation 16 | - 128 bits of security strength 17 | 18 | Way of Working 19 | ~~~~~~~~~~~~~~ 20 | 21 | Loop test STAT.BUSY, till it is idle. 22 | 23 | Write GEN_NOISE to CTRL.CMD to generate full-entropy seed from noise. 24 | 25 | Loop test ISTAT.DONE, till last command is completed. 26 | 27 | Clear ISTAT.DONE by writing 1 to it. 28 | 29 | Write CREATE_STATE to CTRL.CMD to move DRBG to create state. 30 | 31 | Loop test ISTAT.DONE, till last command is completed. 32 | 33 | Clear ISTAT.DONE by writing 1 to it. 34 | 35 | Write GEN_RANDOM to CTRL.CMD to generate a random number. 36 | 37 | Loop test ISTAT.DONE, till last command is completed. 38 | 39 | Clear ISTAT.DONE by writing 1 to it. 40 | 41 | Read the random data word 0 from RAND0. 42 | 43 | Read the random data word 1 from RAND1. 44 | 45 | Read the random data word 2 from RAND2. 46 | 47 | Read the random data word 3 from RAND3. 48 | 49 | TRNG Register Overview 50 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~ 51 | 52 | .. include:: ../../contents-share/security/trng_registers_overview.table.rst 53 | 54 | TRNG Register Description 55 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 56 | 57 | (Base address: 0x02070000) 58 | 59 | .. include:: ../../contents-share/security/trng_registers_description.table.rst 60 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_nandflash/0.index.rst: -------------------------------------------------------------------------------- 1 | SPI NAND Flash Controller 2 | ========================= 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./data_structure.rst 12 | ./registers_overview.rst 13 | ./registers_descriptions.rst 14 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_nandflash/data_structure.rst: -------------------------------------------------------------------------------- 1 | Data Structure (NAND Flash/SPI NAND Flash) 2 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 3 | 4 | 2KB page_size 5 | ^^^^^^^^^^^^^ 6 | 7 | For a 2KB page_size configuration, the common size of the redundant area available to the software is 64Byte. The structure of data in Buffer and Flash is as follows. The size of the redundant area is related to the actual device used. 8 | 9 | .. This table is relatively small, so I don’t put the file include separately. 10 | 11 | .. table:: The structure of data in Buffer and Flash (2KB page_size) 12 | :widths: 1 1 1 13 | 14 | +------------------+--------------------------------+------------------+ 15 | | User Data | Data(2048) | OOB(64) | 16 | +------------------+--------------------------------+------------------+ 17 | 18 | 19 | 4KB page_size 20 | ^^^^^^^^^^^^^ 21 | 22 | For a 4KB page_size configuration, the common size of the redundant area available to the software is 256Byte. The structure of data in Buffer and Flash is as follows. The size of the redundant area is related to the actual device used. 23 | 24 | .. This table is relatively small, so I don’t put the file include separately. 25 | 26 | .. table:: The structure of data in Buffer and Flash (4KB page_size) 27 | :widths: 1 1 1 28 | 29 | +------------------+--------------------------------+------------------+ 30 | | User Data | Data(4096) | OOB(256) | 31 | +------------------+--------------------------------+------------------+ 32 | 33 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_nandflash/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | ~~~~~~~~ 3 | 4 | - Supports external 1 chip select. 5 | 6 | - Support SPI NAND Flash x1/x2/x4 read and write operations. 7 | 8 | - Supports various specifications of SPI NAND Flash devices. 9 | 10 | - Supports 2KB and 4KB devices. 11 | 12 | - Supports 64Pages/Block, 128Pages/Block devices. 13 | 14 | - Supports BOOT function of SPI NAND. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_nandflash/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | ~~~~~~~~ 3 | 4 | Provides off-chip SPI NAND Flash data access. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_nandflash/registers_descriptions.rst: -------------------------------------------------------------------------------- 1 | Register Description 2 | -------------------- 3 | 4 | .. include:: ../../contents-share/spi_nandflash/spi_nandflash_registers_description.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_nandflash/registers_overview.rst: -------------------------------------------------------------------------------- 1 | Register Overview 2 | ----------------- 3 | 4 | .. include:: ../../contents-share/spi_nandflash/spi_nandflash_registers_overview.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_norflash/0.index.rst: -------------------------------------------------------------------------------- 1 | SPI NOR Flash Controller 2 | ======================== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers_overview.rst 12 | ./registers_descriptions.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_norflash/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | - Supports external 1 chip select. 5 | 6 | - Supports Dual/Qual read and write operations. 7 | 8 | - Supports devices of various specifications. 9 | 10 | - Supports 3Byte address devices and 4Byte address devices. 11 | 12 | - Supports devices with a maximum capacity of 256MB. 13 | 14 | - Support BOOT function. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_norflash/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | Provides off-chip SPI NOR Flash data access. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_norflash/registers_descriptions.rst: -------------------------------------------------------------------------------- 1 | Register Description 2 | -------------------- 3 | 4 | .. include:: ../../contents-share/spi_norflash/spi_norflash_registers_description.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/spi_norflash/registers_overview.rst: -------------------------------------------------------------------------------- 1 | Register Overview 2 | ----------------- 3 | 4 | Base Address 0x10000000 5 | 6 | .. include:: ../../contents-share/spi_norflash/spi_norflash_registers_overview.table.rst 7 | 8 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-architecture/0.index.rst: -------------------------------------------------------------------------------- 1 | System Architecture 2 | =================== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./processors.rst 8 | ./interrupts.rst 9 | ./memorymap.rst 10 | ./package_pin.rst 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-architecture/interrupts.rst: -------------------------------------------------------------------------------- 1 | Interrupt Subsystem 2 | ------------------- 3 | 4 | .. include:: ../../contents-share/system-architecture/interrupts.table.rst 5 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-architecture/memorymap.rst: -------------------------------------------------------------------------------- 1 | Address-Space Mapping 2 | --------------------- 3 | 4 | .. only:: sg2002 5 | 6 | .. include:: ../../contents-share/system-architecture/memorymap_sg2002.table.rst 7 | 8 | .. only:: sg2000 9 | 10 | .. include:: ../../contents-share/system-architecture/memorymap_sg2000.table.rst 11 | 12 | \* Reading and writing operations on the reserved address space may produce unpredictable results. 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-architecture/processors.rst: -------------------------------------------------------------------------------- 1 | Processor subsystem 2 | ------------------- 3 | 4 | In addition to one little core processor (RISC-V C906@700MHz), this chip also has two big core main processors: RISC-V C906@1GHz and ARM Cortex-A53@1GHz. There are two combination modes of big core and little core, which are switched through the peripheral circuit control of the pin GPIO_RTX (refer to the datasheet for details): 5 | 6 | - Big Core (RISC-V C906@1GHz) + Little Core (RISC-V C906@700MHz). 7 | 8 | - Big Core (ARM Cortex-A53@1GHz) + Little Core (RISC-V C906@700MHz). 9 | 10 | ARM Cortex-A53@1GHz processor has the following features: 11 | 12 | - The processor operating frequency can reach up to 1.0 GHz. 13 | 14 | - Support Neon. 15 | 16 | - Support floating point unit FPU. 17 | 18 | - L1 Cache includes 32KB Instruction Cache and 32KB Data Cache. 19 | 20 | - 128KB L2 cache. 21 | 22 | - Support MMU (Memory Management Unit). 23 | 24 | - The processor has an internal integrated interrupt controller. 25 | 26 | - Support JTAG debugging interface. 27 | 28 | RISC-V C906@1GHz processor has the following features: 29 | 30 | - The processor operating frequency can reach up to 1.0GHz. 31 | 32 | - Integrated vector execution unit, floating point coprocessor. 33 | 34 | - L1 Cache includes 32KB Instruction Cache and 64KB Data Cache. 35 | 36 | - Support MMU (Memory Management Unit). 37 | 38 | - The processor has an internal integrated interrupt controller. 39 | 40 | - Support JTAG debugging interface. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-control/0.index.rst: -------------------------------------------------------------------------------- 1 | System Controller 2 | ================= 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./function_description.rst 9 | ./registers.rst 10 | 11 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-control/function_description.rst: -------------------------------------------------------------------------------- 1 | Function description 2 | -------------------- 3 | 4 | Global reset enable 5 | ~~~~~~~~~~~~~~~~~~~ 6 | 7 | System global soft reset, debug reset and watchdog 8 | reset need to be enabled by configuring the reg_sw_root_reset_en register. Details of each bit are described in reg_sw_root_reset_en. 9 | 10 | .. _section_system_control_function_description_sys_dma_channel_map: 11 | 12 | System DMA channel mapping 13 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ 14 | 15 | This chip system has 8 built-in DMA channels, each configured with 0 ~ 7 channel request interfaces. Channel requests from 0 to 7 are mapped to one of the peripheral interfaces in the table below by the system control registers sdma_dma_ch_remap0 and sdma_dma_ch_remap1. Note that multiple channels cannot be configured as the same peripheral interface. 16 | 17 | Configuration steps: 18 | 19 | Configure the DMA channel image register sdma_dma_ch_remap0, sdma_dma_ch_remap1, update_dma_remp_0_3, update_dma_remp_4_7 and write 1 to make the mapping effective. 20 | 21 | The system DMA channel mapping is as follows: 22 | 23 | .. include:: ../../contents-share/system-control/system_dma_channel_mapping.table.rst 24 | 25 | DDR AXI Urgent/Qos configuration 26 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 27 | 28 | The AXI transmission priority from the subsystem can be configured by ddr_axi_urgent_ow, ddr_axi_urgent, ddr_axi_qos_0, ddr_axi_qos_1 of the control system controller. For details, please refer to the DDR controller chapter :ref:`section_ddr`. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-control/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The system controller implements some system control and enablement of the chip through registers, including system soft reset, clock control, etc. The reset clock has been described in other chapters. This chapter describes the configuration and status registers of some other system function modules. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-control/registers.rst: -------------------------------------------------------------------------------- 1 | System Control Register 2 | ----------------------- 3 | 4 | System Control Register Overview 5 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | Bass address 0x03000000 8 | 9 | .. include:: ../../contents-share/system-control/system_control_registers_overview.table.rst 10 | 11 | System Control Register Description 12 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 13 | 14 | .. include:: ../../contents-share/system-control/system_control_registers_description.table.rst 15 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-overview/0.index.rst: -------------------------------------------------------------------------------- 1 | System Overview 2 | =============== 3 | 4 | .. only:: sg2002 5 | 6 | .. toctree:: 7 | :maxdepth: 2 8 | 9 | ./introduction.rst 10 | ./system-block-diagram.rst 11 | ./features.rst 12 | 13 | .. only:: sg2000 14 | 15 | .. toctree:: 16 | :maxdepth: 2 17 | 18 | ./introduction_sg2000.rst 19 | ./system-block-diagram_sg2000.rst 20 | ./features_sg2000.rst -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-overview/introduction.rst: -------------------------------------------------------------------------------- 1 | Introduction 2 | ------------ 3 | 4 | SG2002 is a high-performance, low-power chip launched for the AIot field. It has multiple built-in powerful cores: 2 x C906, 1 x Arm Cortex A53, 1 x 8051. Users can quickly switch cores according to needs. At the same time, it integrates hardware codecs: H.264 video compression codec, H.265 video compression encoder and ISP, supporting the configuration of professional-level video image ISP: HDR wide dynamic range, 3D noise reduction, defogging, lens distortion correction and other image enhancement and correction algorithms. 5 | 6 | The chip also integrates a self-developed TPU, which can provide 1.0TOPS IN8 computing power. The specially designed TPU scheduling engine efficiently delivers extremely high-bandwidth data streams to all tensor processor cores. 7 | 8 | At the same time, it supports a variety of peripheral interfaces: 5 x I2C, 2 x SDIO3.0, 2 x I2S, 15 x PWM, 1 x USB 2.0, etc., to meet the needs of various scenarios. 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-overview/introduction_sg2000.rst: -------------------------------------------------------------------------------- 1 | Introduction 2 | ------------ 3 | 4 | SG2000 is a high-performance, low-power chip launched for the AIot field. It has multiple built-in powerful cores: 2 x C906, 1 x Arm Cortex A53, 1 x 8051. Users can quickly switch cores according to needs. At the same time, it integrates hardware codecs: H.264 video compression codec, H.265 video compression encoder and ISP, supporting the configuration of professional-level video image ISP: HDR wide dynamic range, 3D noise reduction, defogging, lens distortion correction and other image enhancement and correction algorithms. 5 | 6 | The chip also integrates a self-developed TPU, which can provide 0.5TOPS IN8 computing power. The specially designed TPU scheduling engine efficiently delivers extremely high-bandwidth data streams to all tensor processor cores. 7 | 8 | At the same time, it supports a variety of peripheral interfaces: 6 x I2C, 2 x SDIO3.0, 2 x I2S, 15 x PWM, 1 x USB 2.0, etc., to meet the needs of various scenarios. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-overview/system-block-diagram.rst: -------------------------------------------------------------------------------- 1 | System Framework 2 | ---------------- 3 | 4 | .. _diagram_system_block: 5 | .. figure:: ../../../../media/image1.png 6 | :align: center 7 | 8 | System Framework 9 | 10 | 11 | 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/system-overview/system-block-diagram_sg2000.rst: -------------------------------------------------------------------------------- 1 | System Framework 2 | ---------------- 3 | 4 | .. _diagram_system_block_sg2000: 5 | .. figure:: ../../../../media/image1_sg2000.png 6 | :align: center 7 | 8 | System Framework 9 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/0.index.rst: -------------------------------------------------------------------------------- 1 | Timers 2 | ====== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers_overview.rst 12 | ./registers_description.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | The timer has the following characteristics: 5 | 6 | - 32bit subtraction timer/counter. 7 | 8 | - Supports 2 counting modes: free running mode and user-defined counting mode. 9 | 10 | - The system can read the current count value. 11 | 12 | When the count decreases to 0, an interrupt is generated. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/functionalities.rst: -------------------------------------------------------------------------------- 1 | Function Description 2 | -------------------- 3 | 4 | Timer is based on a 32-bit down counter. The counter value is decremented by 1 on each rising edge of the count clock. When the count value decreases to zero, the Timer will generate an interrupt. 5 | 6 | Timer has the following 2 counting modes: 7 | 8 | - Free running mode: The timer continues to count, and when the count value decreases to 0, it automatically returns to its maximum value and continues counting. The maximum count length is 0xFFFF_FFFF. 9 | 10 | - User-defined counting mode: The timer continues to count. When the count value decreases to 0, the initial value is loaded again from the TimerNLoadCount (N=1~8) register and continues counting. 11 | 12 | The method of loading the initial count value of the timer is as follows: 13 | 14 | The initial count value of the timer can be loaded by writing the TimerNLoadCount (N=1~8) register. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The system is configured with 8 Timer modules providing timing and counting function. These timers can be used to implement timing and counting for applications, and can also be used for the operating system to implement the system clock. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/registers_description.rst: -------------------------------------------------------------------------------- 1 | Timer Register Description 2 | -------------------------- 3 | 4 | .. include:: ../../contents-share/timer/timer_registers_description.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/registers_overview.rst: -------------------------------------------------------------------------------- 1 | Timer Register Overview 2 | ----------------------- 3 | 4 | Timer registers are accessed via the bus. 5 | 6 | An overview of Timer registers is shown in :ref:`table_timer_registers_overview`. 7 | 8 | .. include:: ../../contents-share/timer/timer_registers_overview.table.rst 9 | 10 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/timer/working_method.rst: -------------------------------------------------------------------------------- 1 | Way of Working 2 | -------------- 3 | 4 | Initialization 5 | ~~~~~~~~~~~~~~ 6 | 7 | - Step 1: Write the TimerNLoadCount (N=1~8) register to load the initial count value for the Timer. 8 | 9 | - Step 2: Set the TimerNControlReg[2:0] (N=1~8) register, select the Timer counting mode, mask the Timer interrupt, and start the Timer to start counting. 10 | 11 | Interrupt Handling 12 | ~~~~~~~~~~~~~~~~~~ 13 | 14 | When the timer generates an interrupt, the steps are as follows: 15 | 16 | - Step 1: Read the TimerNEOI (N=1~8) register to clear the TimerN interrupt. 17 | 18 | - Step 2: Execute the process waiting for the interrupt. 19 | 20 | - Step 3: After the process is completed, resume execution of the interrupted program. 21 | 22 | Clock Selection 23 | ~~~~~~~~~~~~~~~ 24 | 25 | System Timer optional 25MHz/32KHz counting clock. Use reg_timer_clk_sel to make the selection. 26 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/video/0.index.rst: -------------------------------------------------------------------------------- 1 | Video Interface 2 | =============== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./vi.rst 8 | ./vdp.rst 9 | ./mipi_rx.rst 10 | ./mipi_tx.rst 11 | 12 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/watchdog/0.index.rst: -------------------------------------------------------------------------------- 1 | WatchDog 2 | ======== 3 | 4 | .. toctree:: 5 | :maxdepth: 2 6 | 7 | ./overview.rst 8 | ./features.rst 9 | ./functionalities.rst 10 | ./working_method.rst 11 | ./registers_overview.rst 12 | ./registers_description.rst 13 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/watchdog/features.rst: -------------------------------------------------------------------------------- 1 | Features 2 | -------- 3 | 4 | WatchDog has the following features: 5 | 6 | - Configure a 32bit down counter. 7 | 8 | - Supports configurable initial counting value (i.e. time interval). 9 | 10 | - Supports WatchDog restart protection to prevent WatchDog from being restarted due to misoperation. 11 | 12 | - Support reset signal generation. 13 | 14 | - Support timeout interrupt generation. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/watchdog/overview.rst: -------------------------------------------------------------------------------- 1 | Overview 2 | -------- 3 | 4 | The system is configured with 4 watchdog modules. It is used to issue an interrupt or reset signal after a certain period of time to interrupt or reset the entire system when an abnormality occurs in the system. -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/watchdog/registers_description.rst: -------------------------------------------------------------------------------- 1 | WDT Register Description 2 | ------------------------ 3 | 4 | .. include:: ../../contents-share/watchdog/watchdog_registers_description.table.rst 5 | 6 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/watchdog/registers_overview.rst: -------------------------------------------------------------------------------- 1 | .. _section_wdt_register_overview: 2 | 3 | WDT Register Overview 4 | --------------------- 5 | 6 | The WDT register is accessed via the bus. Includes four WDTs, 3 are Active Domains, and 1 is No-die Domain. Their base addresses are: 7 | 8 | - WDT0: 0x03010000 9 | 10 | - WDT1: 0x03011000 11 | 12 | - WDT2: 0x03012000 13 | 14 | - RTCSYS_WDT: 0x0502D000 15 | 16 | Each WDT consists of a set of control registers, each set has the same definition, and an overview is shown in :ref:`table_watchdog_register_overview`. 17 | 18 | .. include:: ../../contents-share/watchdog/watchdog_register_overview.table.rst 19 | 20 | -------------------------------------------------------------------------------- /SG200X/TRM/contents/en/watchdog/working_method.rst: -------------------------------------------------------------------------------- 1 | Way of Working 2 | -------------- 3 | 4 | Count Clock Frequency Configuration 5 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 6 | 7 | WatchDog counting clock is 25MHz/32KHz clock. Use reg_wdt_clk_sel to make the selection. 8 | 9 | System Initialization Configuration 10 | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 11 | 12 | After the system is powered on and reset, the WatchDog counter stops counting. During the system initialization process, WatchDog needs to be initialized and started to run. The initialization process of WatchDog is as follows: 13 | 14 | - Step 1: Write register WDT_TORR to set the initial value of WatchDog count. 15 | 16 | - Step 2: Write register WDT_CR[1] to set WatchDog count timeout response mode. 17 | 18 | - Step 3: Write register WDT_CR[0] to start WatchDog counting. 19 | 20 | Interrupt Handling Process 21 | ~~~~~~~~~~~~~~~~~~~~~~~~~~ 22 | 23 | After the system receives an interrupt from WatchDog, it should clear its interrupt status in time. 24 | 25 | The process of WatchDog interrupt processing is as follows: 26 | 27 | - Step 1: Read the register WDT_EOI and clear the interrupt status of WatchDog. 28 | 29 | - Step 2: Write 0x76 to the register WDT_CRR and restart WatchDog. 30 | 31 | Close WatchDog 32 | ~~~~~~~~~~~~~~ 33 | 34 | Write 0 or 1 to register WDT_CR[0] to control the status of WatchDog: 35 | 36 | - 0: WDT is off. 37 | 38 | - 1: WDT is on. Only a system reset can turn off the WDT after startup. 39 | -------------------------------------------------------------------------------- /SG200X/TRM/doc/design_conditional_sg200x.md: -------------------------------------------------------------------------------- 1 | **SG2000 和 SG2002 的条件编译编码设计笔记** 2 | 3 | 4 | SG2000 和 SG2002 不同的地方可以采用 Sphinx 支持的条件编译方式进行编码。具体方式如下： 5 | 6 | - 条件编译文字 7 | 8 | ```rst 9 | .. only:: sg2002 10 | 11 | SG2002 ...... 12 | 13 | .. only:: sg2000 14 | 15 | SG2000 ...... 16 | ``` 17 | 18 | - 条件编译图片或者表格等涉及锚点的情况 19 | 20 | **注意：采用 only 语法时，不同条件下的 "锚点" id 必须不同，否则编译时会报错说有重复。** 21 | 22 | 同时 **注意：对于以上情况请仔细检查引用锚点的文本是否也需要加上条件编译处理。** 23 | 24 | 以图片为例，表格也有类似的问题。 25 | 26 | ```rst 27 | .. only:: sg2002 28 | 29 | .. _diagram_package_pins_sg2002: 30 | .. figure:: ../../../../media/image4.png 31 | 32 | 管脚分布图 33 | 34 | .. only:: sg2000 35 | 36 | .. _diagram_package_pins_sg2000: 37 | .. figure:: ../../../../media/image3.png 38 | 39 | 管脚分布图 40 | ``` 41 | 42 | - 条件编译 include 文件 43 | 44 | ```rst 45 | .. only:: sg2002 46 | 47 | .. include:: ./interrupts-sg2002.table.rst 48 | 49 | .. only:: sg2000 50 | 51 | .. include:: ./interrupts-sg2000.table.rst 52 | ``` 53 | 54 | 项目中需要将 `"sg2002"` / `"sg2000"` 作为 tag 添加在 Makefile 中，具体可以参考 `SG200X/TRM/sg2000_cn/Makefile` 或者 `SG200X/TRM/sg2002_cn/Makefile`。 55 | 56 | 譬如 `SG200X/TRM/sg2002_cn/Makefile` 中，我们为 `SPHINXOPTS` 定义了 tag `"sg2002"` 如下： 57 | 58 | ```makefile 59 | SPHINXOPTS ?= -t sg2002 60 | ``` 61 | 62 | `SPHINXOPTS` 会在执行 `sphinx-build` 时作为命令行参数带入。 63 | 64 | ```makefile 65 | # Catch-all target: route all unknown targets to Sphinx using the new 66 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 67 | %: Makefile 68 | @$(BUILD_CONFIG) $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 69 | ``` -------------------------------------------------------------------------------- /SG200X/TRM/media/SOPHON-LOGO-orginal.png: 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these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= -t sg2000 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | PROJECT = sg2000 12 | DOC_TYPE = trm 13 | DOC_LANG = cn 14 | RELEASE = 1.02 15 | RELEASE_DATE = 2025-02-27 16 | COPYRIGHT = "2025 SOPHGO Co., Ltd" 17 | AUTHOR = Sophgo 18 | 19 | PDF_FILENAME = $(PROJECT)_$(DOC_TYPE)_$(DOC_LANG)_v$(RELEASE).pdf 20 | 21 | BUILD_CONFIG = \ 22 | CONFIG_PROJECT=$(PROJECT) \ 23 | CONFIG_TYPE=$(DOC_TYPE) \ 24 | CONFIG_LANG=$(DOC_LANG) \ 25 | CONFIG_COPYRIGHT=$(COPYRIGHT) \ 26 | CONFIG_AUTHOR=$(AUTHOR) \ 27 | CONFIG_RELEASE=$(RELEASE) \ 28 | CONFIG_RELEASEDATE=$(RELEASE_DATE) 29 | 30 | # Put it first so that "make" without argument is like "make help". 31 | help: 32 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 33 | 34 | .PHONY: help Makefile 35 | 36 | # Catch-all target: route all unknown targets to Sphinx using the new 37 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 38 | %: Makefile 39 | @$(BUILD_CONFIG) $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 40 | 41 | pdf: latexpdf 42 | @mv $(BUILDDIR)/latex/$(PROJECT).pdf $(BUILDDIR)/"${PDF_FILENAME}" 43 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_cn/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_cn/source/conf.py: -------------------------------------------------------------------------------- 1 | ../../conf.py -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_cn/source/contents: -------------------------------------------------------------------------------- 1 | ../../contents/cn/ -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_cn/source/index.rst: -------------------------------------------------------------------------------- 1 | SG2000 技术参考手册 2 | =================== 3 | 4 | **修订记录** 5 | 6 | .. _table_revision_history: 7 | .. table:: 修订记录 8 | :widths: 1 1 2 9 | 10 | =============== ============ ===================================== 11 | Revision Date Description 12 | =============== ============ ===================================== 13 | 1.0-alpha 2023/11/23 初稿 14 | 1.0-beta 2024/03/22 转化为 reStructuredText 格式 15 | 1.0 2024/06/17 修复累积问题，正式发布 v1.0 16 | 1.01 2024/07/05 管脚复用和控制直接引用在线文档 17 | 1.02 2025/02/27 修复累积问题 18 | =============== ============ ===================================== 19 | 20 | .. toctree:: 21 | :maxdepth: 4 22 | :caption: 目录 23 | :numbered: 24 | 25 | ./contents/disclaimer.rst 26 | ./contents/system-overview/0.index.rst 27 | ./contents/system-architecture/0.index.rst 28 | ./contents/initialization/0.index.rst 29 | ./contents/power/0.index.rst 30 | ./contents/rtc/0.index.rst 31 | ./contents/reset/0.index.rst 32 | ./contents/clock/0.index.rst 33 | ./contents/system-control/0.index.rst 34 | ./contents/pinmux-pinctrl/0.index.rst 35 | ./contents/dma/0.index.rst 36 | ./contents/timer/0.index.rst 37 | ./contents/watchdog/0.index.rst 38 | ./contents/mcu/0.index.rst 39 | ./contents/ddr/0.index.rst 40 | ./contents/spi_norflash/0.index.rst 41 | ./contents/spi_nandflash/0.index.rst 42 | ./contents/network/0.index.rst 43 | ./contents/video/0.index.rst 44 | ./contents/audio/0.index.rst 45 | ./contents/peripherals/0.index.rst 46 | ./contents/security/0.index.rst 47 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= -t sg2000 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | PROJECT = sg2000 12 | DOC_TYPE = trm 13 | DOC_LANG = en 14 | RELEASE = 1.02 15 | RELEASE_DATE = 2025-02-27 16 | COPYRIGHT = "2025 SOPHGO Co., Ltd" 17 | AUTHOR = Sophgo 18 | 19 | PDF_FILENAME = $(PROJECT)_$(DOC_TYPE)_$(DOC_LANG)_v$(RELEASE).pdf 20 | 21 | BUILD_CONFIG = \ 22 | CONFIG_PROJECT=$(PROJECT) \ 23 | CONFIG_TYPE=$(DOC_TYPE) \ 24 | CONFIG_LANG=$(DOC_LANG) \ 25 | CONFIG_COPYRIGHT=$(COPYRIGHT) \ 26 | CONFIG_AUTHOR=$(AUTHOR) \ 27 | CONFIG_RELEASE=$(RELEASE) \ 28 | CONFIG_RELEASEDATE=$(RELEASE_DATE) 29 | 30 | # Put it first so that "make" without argument is like "make help". 31 | help: 32 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 33 | 34 | .PHONY: help Makefile 35 | 36 | # Catch-all target: route all unknown targets to Sphinx using the new 37 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 38 | %: Makefile 39 | @$(BUILD_CONFIG) $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 40 | 41 | pdf: latexpdf 42 | @mv $(BUILDDIR)/latex/$(PROJECT).pdf $(BUILDDIR)/"${PDF_FILENAME}" 43 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/source/conf.py: -------------------------------------------------------------------------------- 1 | ../../conf.py -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/source/contents: -------------------------------------------------------------------------------- 1 | ../../contents/en -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/source/contents-share: -------------------------------------------------------------------------------- 1 | ../../contents/cn -------------------------------------------------------------------------------- /SG200X/TRM/sg2000_en/source/index.rst: -------------------------------------------------------------------------------- 1 | SG2000 Technical Reference Manual 2 | ================================= 3 | 4 | **Revision History** 5 | 6 | .. _table_revision_history: 7 | .. table:: Revision History 8 | :widths: 1 1 2 9 | 10 | =============== ============ ===================================== 11 | Revision Date Description 12 | =============== ============ ===================================== 13 | 1.0-alpha 2023/11/23 Initial Version 14 | 1.0-beta 2024/03/22 Converted to reStructuredText 15 | 1.0 2024/06/17 Fixed cumulative issues and officially released v1.0 16 | 1.01 2024/07/05 Pin multiplexing and control directly refer to the online documentation 17 | 1.02 2025/02/27 Fixed cumulative issues. 18 | =============== ============ ===================================== 19 | 20 | .. toctree:: 21 | :maxdepth: 4 22 | :caption: Contents 23 | :numbered: 24 | 25 | ./contents/disclaimer.rst 26 | ./contents/system-overview/0.index.rst 27 | ./contents/system-architecture/0.index.rst 28 | ./contents/initialization/0.index.rst 29 | ./contents/power/0.index.rst 30 | ./contents/rtc/0.index.rst 31 | ./contents/reset/0.index.rst 32 | ./contents/clock/0.index.rst 33 | ./contents/system-control/0.index.rst 34 | ./contents/pinmux-pinctrl/0.index.rst 35 | ./contents/dma/0.index.rst 36 | ./contents/timer/0.index.rst 37 | ./contents/watchdog/0.index.rst 38 | ./contents/mcu/0.index.rst 39 | ./contents/ddr/0.index.rst 40 | ./contents/spi_norflash/0.index.rst 41 | ./contents/spi_nandflash/0.index.rst 42 | ./contents/network/0.index.rst 43 | ./contents/video/0.index.rst 44 | ./contents/audio/0.index.rst 45 | ./contents/peripherals/0.index.rst 46 | ./contents/security/0.index.rst 47 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_cn/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_cn/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= -t sg2002 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | PROJECT = sg2002 12 | DOC_TYPE = trm 13 | DOC_LANG = cn 14 | RELEASE = 1.02 15 | RELEASE_DATE = 2025-02-27 16 | COPYRIGHT = "2025 SOPHGO Co., Ltd" 17 | AUTHOR = Sophgo 18 | 19 | PDF_FILENAME = $(PROJECT)_$(DOC_TYPE)_$(DOC_LANG)_v$(RELEASE).pdf 20 | 21 | BUILD_CONFIG = \ 22 | CONFIG_PROJECT=$(PROJECT) \ 23 | CONFIG_TYPE=$(DOC_TYPE) \ 24 | CONFIG_LANG=$(DOC_LANG) \ 25 | CONFIG_COPYRIGHT=$(COPYRIGHT) \ 26 | CONFIG_AUTHOR=$(AUTHOR) \ 27 | CONFIG_RELEASE=$(RELEASE) \ 28 | CONFIG_RELEASEDATE=$(RELEASE_DATE) 29 | 30 | # Put it first so that "make" without argument is like "make help". 31 | help: 32 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 33 | 34 | .PHONY: help Makefile 35 | 36 | # Catch-all target: route all unknown targets to Sphinx using the new 37 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 38 | %: Makefile 39 | @$(BUILD_CONFIG) $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 40 | 41 | pdf: latexpdf 42 | @mv $(BUILDDIR)/latex/$(PROJECT).pdf $(BUILDDIR)/"${PDF_FILENAME}" 43 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_cn/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_cn/source/conf.py: -------------------------------------------------------------------------------- 1 | ../../conf.py -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_cn/source/contents: -------------------------------------------------------------------------------- 1 | ../../contents/cn/ -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_cn/source/index.rst: -------------------------------------------------------------------------------- 1 | SG2002 技术参考手册 2 | =================== 3 | 4 | **修订记录** 5 | 6 | .. _table_revision_history: 7 | .. table:: 修订记录 8 | :widths: 1 1 2 9 | 10 | =============== ============ ===================================== 11 | Revision Date Description 12 | =============== ============ ===================================== 13 | 1.0-alpha 2023/11/23 初稿 14 | 1.0-beta 2024/02/26 转化为 reStructuredText 格式 15 | 1.0 2024/06/17 修复累积问题，正式发布 v1.0 16 | 1.01 2024/07/05 管脚复用和控制直接引用在线文档 17 | 1.02 2025/02/27 修复累积问题 18 | =============== ============ ===================================== 19 | 20 | .. toctree:: 21 | :maxdepth: 4 22 | :caption: 目录 23 | :numbered: 24 | 25 | ./contents/disclaimer.rst 26 | ./contents/system-overview/0.index.rst 27 | ./contents/system-architecture/0.index.rst 28 | ./contents/initialization/0.index.rst 29 | ./contents/power/0.index.rst 30 | ./contents/rtc/0.index.rst 31 | ./contents/reset/0.index.rst 32 | ./contents/clock/0.index.rst 33 | ./contents/system-control/0.index.rst 34 | ./contents/pinmux-pinctrl/0.index.rst 35 | ./contents/dma/0.index.rst 36 | ./contents/timer/0.index.rst 37 | ./contents/watchdog/0.index.rst 38 | ./contents/mcu/0.index.rst 39 | ./contents/ddr/0.index.rst 40 | ./contents/spi_norflash/0.index.rst 41 | ./contents/spi_nandflash/0.index.rst 42 | ./contents/network/0.index.rst 43 | ./contents/video/0.index.rst 44 | ./contents/audio/0.index.rst 45 | ./contents/peripherals/0.index.rst 46 | ./contents/security/0.index.rst 47 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/.gitignore: -------------------------------------------------------------------------------- 1 | build/ 2 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= -t sg2002 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | PROJECT = sg2002 12 | DOC_TYPE = trm 13 | DOC_LANG = en 14 | RELEASE = 1.02 15 | RELEASE_DATE = 2025-02-27 16 | COPYRIGHT = "2025 SOPHGO Co., Ltd" 17 | AUTHOR = Sophgo 18 | 19 | PDF_FILENAME = $(PROJECT)_$(DOC_TYPE)_$(DOC_LANG)_v$(RELEASE).pdf 20 | 21 | BUILD_CONFIG = \ 22 | CONFIG_PROJECT=$(PROJECT) \ 23 | CONFIG_TYPE=$(DOC_TYPE) \ 24 | CONFIG_LANG=$(DOC_LANG) \ 25 | CONFIG_COPYRIGHT=$(COPYRIGHT) \ 26 | CONFIG_AUTHOR=$(AUTHOR) \ 27 | CONFIG_RELEASE=$(RELEASE) \ 28 | CONFIG_RELEASEDATE=$(RELEASE_DATE) 29 | 30 | # Put it first so that "make" without argument is like "make help". 31 | help: 32 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 33 | 34 | .PHONY: help Makefile 35 | 36 | # Catch-all target: route all unknown targets to Sphinx using the new 37 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 38 | %: Makefile 39 | @$(BUILD_CONFIG) $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 40 | 41 | pdf: latexpdf 42 | @mv $(BUILDDIR)/latex/$(PROJECT).pdf $(BUILDDIR)/"${PDF_FILENAME}" 43 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/source/conf.py: -------------------------------------------------------------------------------- 1 | ../../conf.py -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/source/contents: -------------------------------------------------------------------------------- 1 | ../../contents/en -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/source/contents-share: -------------------------------------------------------------------------------- 1 | ../../contents/cn -------------------------------------------------------------------------------- /SG200X/TRM/sg2002_en/source/index.rst: -------------------------------------------------------------------------------- 1 | SG2002 Technical Reference Manual 2 | ================================= 3 | 4 | **Revision History** 5 | 6 | .. _table_revision_history: 7 | .. table:: Revision History 8 | :widths: 1 1 2 9 | 10 | =============== ============ ===================================== 11 | Revision Date Description 12 | =============== ============ ===================================== 13 | 1.0-alpha 2023/11/23 Initial Version 14 | 1.0-beta 2024/02/26 Converted to reStructuredText 15 | 1.0 2024/06/17 Fixed cumulative issues and officially released v1.0 16 | 1.01 2024/07/05 Pin multiplexing and control directly refer to the online documentation 17 | 1.02 2025/02/27 Fixed cumulative issues. 18 | =============== ============ ===================================== 19 | 20 | .. toctree:: 21 | :maxdepth: 4 22 | :caption: Contents 23 | :numbered: 24 | 25 | ./contents/disclaimer.rst 26 | ./contents/system-overview/0.index.rst 27 | ./contents/system-architecture/0.index.rst 28 | ./contents/initialization/0.index.rst 29 | ./contents/power/0.index.rst 30 | ./contents/rtc/0.index.rst 31 | ./contents/reset/0.index.rst 32 | ./contents/clock/0.index.rst 33 | ./contents/system-control/0.index.rst 34 | ./contents/pinmux-pinctrl/0.index.rst 35 | ./contents/dma/0.index.rst 36 | ./contents/timer/0.index.rst 37 | ./contents/watchdog/0.index.rst 38 | ./contents/mcu/0.index.rst 39 | ./contents/ddr/0.index.rst 40 | ./contents/spi_norflash/0.index.rst 41 | ./contents/spi_nandflash/0.index.rst 42 | ./contents/network/0.index.rst 43 | ./contents/video/0.index.rst 44 | ./contents/audio/0.index.rst 45 | ./contents/peripherals/0.index.rst 46 | ./contents/security/0.index.rst 47 | -------------------------------------------------------------------------------- /SG2042/.gitignore: -------------------------------------------------------------------------------- 1 | *.swp 2 | -------------------------------------------------------------------------------- /SG2042/HowTo/Create Bootable Disk Using Prebuilt Image.rst: -------------------------------------------------------------------------------- 1 | ========================================= 2 | Create bootable disk using prebuilt image 3 | ========================================= 4 | 5 | 1. Environment 6 | =============== 7 | All operations perform on a Linux based PC. 8 | 9 | 2. Download prebuilt images 10 | =========================== 11 | 12 | About how to download images, see `FAQ `_ 'Where can I find OS images' 13 | 14 | 3. Get the device file of you disk 15 | ================================== 16 | 17 | .. highlights:: 18 | 19 | .. code:: sh 20 | 21 | lsblk 22 | 23 | NAME MAJ:MIN RM SIZE RO TYPE MOUNTPOINTS 24 | sdb 8:16 0 1.8T 0 disk 25 | 26 | In my system, the target disk is /dev/sdb 27 | 28 | 4. Flush image to the disk directly 29 | =================================== 30 | 31 | .. highlights:: 32 | 33 | .. code:: sh 34 | 35 | sudo dd if=fedora-sophgo.img of=/dev/sdb bs=4M status=progress 36 | 37 | NOTICE, DONOT flush the image to a partition of that disk, like /dev/sdb1, /dev/sdb2. 38 | 39 | 5. Enlarge the last partition to fit the disk 40 | ============================================= 41 | 42 | .. highlights:: 43 | 44 | .. code:: sh 45 | 46 | sudo parted /dev/sdb resizepart 3 100% 47 | 48 | 6. Check and repair any errors on root partition 49 | ================================================ 50 | 51 | .. highlights:: 52 | 53 | .. code:: sh 54 | 55 | sudo e2fsck -f /dev/sdb3 56 | 57 | 7. Resize file system to fit the new partition size 58 | =================================================== 59 | 60 | .. highlights:: 61 | 62 | .. code:: sh 63 | 64 | sudo resize2fs /dev/sdb3 65 | 66 | -------------------------------------------------------------------------------- /SG2042/HowTo/bootflow.rst: -------------------------------------------------------------------------------- 1 | ================ 2 | SG2042 Boot Flow 3 | ================ 4 | 5 | .. figure:: figures/bootflow.png 6 | 7 | 1. Fip.bin 8 | 2. ZSBL (Zero Stage Bootloader): Code in the ROM of the board to initial DDR, CPU and Ethernet. Then load OpneSBI and U-Boot. 9 | 3. OpenSBI (RISC-V Open Source Supervisor Binary Interface): The goal of the OpenSBI project is to provide an open-source reference implementation of the RISC-V SBI specifications for platform-specific firmwares executing in M-mode. An OpenSBI implementation can be easily extended by RISC-V platform and system-on-chip vendors to fit a particular hardware configuration. 10 | 4. conf.ini: configuration file used to choose next bootloader. 11 | 5. LinuxBoot: LinuxBoot is a firmware for modern servers that replaces specific firmware functionality like the UEFI DXE phase with a Linux kernel and runtime. 12 | 6. U-Boot (Universal Bootloader): Its primary role is to facilitate the booting process of the embedded device. 13 | 7. GRUB2 (GRand Unified Bootloader version 2): It is responsible for loading and transferring control to an operating system kernel software (such as Linux or GNU Mach). The kernel, in turn, initializes the rest of the operating system (e.g. a GNU system). 14 | 8. Kernel 15 | 16 | -------------------------------------------------------------------------------- /SG2042/HowTo/figures/bootflow.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sophgo/sophgo-doc/5e9555e2102fe82ee1a552fa8e07963913bce7ac/SG2042/HowTo/figures/bootflow.png -------------------------------------------------------------------------------- /SG2042/T-Head/XuanTie-C910-C920-UserManual.pdf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sophgo/sophgo-doc/5e9555e2102fe82ee1a552fa8e07963913bce7ac/SG2042/T-Head/XuanTie-C910-C920-UserManual.pdf -------------------------------------------------------------------------------- /SG2042/TRM/.gitignore: -------------------------------------------------------------------------------- 1 | /build/ 2 | -------------------------------------------------------------------------------- /SG2042/TRM/Makefile: -------------------------------------------------------------------------------- 1 | # Minimal makefile for Sphinx documentation 2 | # 3 | 4 | # You can set these variables from the command line, and also 5 | # from the environment for the first two. 6 | SPHINXOPTS ?= 7 | SPHINXBUILD ?= sphinx-build 8 | SOURCEDIR = source 9 | BUILDDIR = build 10 | 11 | # Put it first so that "make" without argument is like "make help". 12 | help: 13 | @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 14 | 15 | .PHONY: help Makefile 16 | 17 | # Catch-all target: route all unknown targets to Sphinx using the new 18 | # "make mode" option. $(O) is meant as a shortcut for $(SPHINXOPTS). 19 | %: Makefile 20 | $(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O) 21 | -------------------------------------------------------------------------------- /SG2042/TRM/README.md: -------------------------------------------------------------------------------- 1 | # Guide on how to setup build env on Ubuntu and create pdf for TRM. 2 | 3 | Install Sphinx: 4 | 5 | ```bash 6 | sudo apt-get update 7 | sudo apt-get install python3-sphinx 8 | ``` 9 | 10 | Install PDF generation tools: 11 | 12 | ```bash 13 | sudo apt-get install texlive-latex-recommended 14 | sudo apt-get install texlive-latex-extra 15 | sudo apt-get install latexmk 16 | ``` 17 | 18 | Create pdf: 19 | ```bash 20 | cd SG2042/TRM 21 | make latexpdf 22 | ``` 23 | 24 | You can see pdf is generated as `./build/latex/SG2042TechnicalReferenceManual.pdf` 25 | 26 | -------------------------------------------------------------------------------- /SG2042/TRM/make.bat: -------------------------------------------------------------------------------- 1 | @ECHO OFF 2 | 3 | pushd %~dp0 4 | 5 | REM Command file for Sphinx documentation 6 | 7 | if "%SPHINXBUILD%" == "" ( 8 | set SPHINXBUILD=sphinx-build 9 | ) 10 | set SOURCEDIR=source 11 | set BUILDDIR=build 12 | 13 | %SPHINXBUILD% >NUL 2>NUL 14 | if errorlevel 9009 ( 15 | echo. 16 | echo.The 'sphinx-build' command was not found. Make sure you have Sphinx 17 | echo.installed, then set the SPHINXBUILD environment variable to point 18 | echo.to the full path of the 'sphinx-build' executable. Alternatively you 19 | echo.may add the Sphinx directory to PATH. 20 | echo. 21 | echo.If you don't have Sphinx installed, grab it from 22 | echo.https://www.sphinx-doc.org/ 23 | exit /b 1 24 | ) 25 | 26 | if "%1" == "" goto help 27 | 28 | %SPHINXBUILD% -M %1 %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 29 | goto end 30 | 31 | :help 32 | %SPHINXBUILD% -M help %SOURCEDIR% %BUILDDIR% %SPHINXOPTS% %O% 33 | 34 | :end 35 | popd 36 | -------------------------------------------------------------------------------- /SG2042/TRM/source/abstract.rst: -------------------------------------------------------------------------------- 1 | Abstract 2 | ========= 3 | SG2042 is server grade chip with high performance, low power consumption and 4 | high data throughput 5 | 6 | Key features 7 | ------------- 8 | - 64 RISC-V cpu cores which implements IMAFDC 9 | - 4 cores per cluster, 16 clusters on chip 10 | - RISC-V vector 0.7 11 | - 2.0GHz CPU frequency 12 | - 64KiB L1 I-Cache and 64KiB L1 D-Cache per core 13 | - 1MiB unified L2 cache per cluster 14 | - 64MiB system level L3 cache 15 | - 512G ops/s for 8bit integer and 256G ops/s for 16bit floating point 16 | - TDP 120W 17 | - 4 DRAM controller, support DDR4 UDIMM/SODIMM/RDIMM up to 3200MT/s with ECC byte 18 | - Max 256GiB DRAM with single chip, 256GiB with dual chips system 19 | - 2 PCIe controller, support PCIe gen4 up to 16GT/s/lan. 32 lans in total. 20 | - 1 1Gbps ethernet RGMII 21 | - 2 eMMC/SDIO, support eMMC 5.1 or SDIO 3.0. 4bit data width 22 | - 2 SPI flash interface 23 | - 1 LPC 24 | - 4 UART 25 | - 4 I2C, support 100K/400K/1M clock frequency 26 | - 2 general SPI controller 27 | - 4 PWM generator for fan control 28 | - 4 Fan speed counter 29 | - 32 GPIO pins 30 | - FCBGA, ball pitch 1mm, package size 57mm x 57mm 31 | 32 | -------------------------------------------------------------------------------- /SG2042/TRM/source/conf.py: -------------------------------------------------------------------------------- 1 | # Configuration file for the Sphinx documentation builder. 2 | # 3 | # For the full list of built-in configuration values, see the documentation: 4 | # https://www.sphinx-doc.org/en/master/usage/configuration.html 5 | 6 | # -- Project information ----------------------------------------------------- 7 | # https://www.sphinx-doc.org/en/master/usage/configuration.html#project-information 8 | 9 | project = 'SG2042 Technical Reference Manual' 10 | copyright = '2023, SOPHGO' 11 | author = '' 12 | 13 | # -- General configuration --------------------------------------------------- 14 | # https://www.sphinx-doc.org/en/master/usage/configuration.html#general-configuration 15 | 16 | extensions = [] 17 | 18 | templates_path = ['_templates'] 19 | exclude_patterns = [] 20 | 21 | 22 | 23 | # -- Options for HTML output ------------------------------------------------- 24 | # https://www.sphinx-doc.org/en/master/usage/configuration.html#options-for-html-output 25 | 26 | html_theme = 'alabaster' 27 | html_static_path = ['_static'] 28 | 29 | # By default, Sphinx expects the master doc to be contents. Set master doc to index instead. 30 | master_doc = 'index' 31 | -------------------------------------------------------------------------------- /SG2042/TRM/source/index.rst: -------------------------------------------------------------------------------- 1 | .. SG2042 Technical Reference Manual documentation master file, created by 2 | sphinx-quickstart on Sat Apr 1 12:54:35 2023. 3 | You can adapt this file completely to your liking, but it should at least 4 | contain the root `toctree` directive. 5 | 6 | Welcome to SG2042 Technical Reference Manual's documentation! 7 | ============================================================== 8 | 9 | .. toctree:: 10 | :maxdepth: 2 11 | :caption: Contents: 12 | 13 | abstract.rst 14 | system.rst 15 | pinmux.rst 16 | clock.rst 17 | Reset.rst 18 | Power-domain.rst 19 | LP.rst 20 | PWM.rst 21 | interrupt.rst 22 | system-control.rst 23 | I2C.rst 24 | SPI-flash.rst 25 | GPIO.rst 26 | uart.rst 27 | SPI.rst 28 | LPC.rst 29 | .. 30 | trm.rst 31 | 32 | 33 | Indices and tables 34 | ================== 35 | 36 | * :ref:`genindex` 37 | * :ref:`modindex` 38 | * :ref:`search` 39 | 40 | -------------------------------------------------------------------------------- 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-------------------------------------------------------------------------------- /SG2042/TRM/source/pic/wdt_reset.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sophgo/sophgo-doc/5e9555e2102fe82ee1a552fa8e07963913bce7ac/SG2042/TRM/source/pic/wdt_reset.png -------------------------------------------------------------------------------- /SG2042/TRM/source/pinmux.rst: -------------------------------------------------------------------------------- 1 | Pin mux 2 | ======= 3 | 4 | SG2042 pins consist of digital pins, analog pins and power supply pins 5 | 6 | Digital pins 7 | ------------ 8 | 9 | Pin list 10 | ~~~~~~~~ 11 | 12 | Digital pins Digital pins are listed in table :ref:`digital_pin_list` 13 | 14 | .. _digital_pin_list: 15 | .. include:: digit-pin-list.rst 16 | 17 | Pin function 18 | ~~~~~~~~~~~~ 19 | 20 | Most digital pins have multiple functions. Each digital pin can have at most four 21 | functions. Pins and functions are listed in table :ref:`digital_pin_function` 22 | The letter in parentheses means, I: input, O: output, IO: input and output. 23 | 24 | .. _digital_pin_function: 25 | .. include:: digital-pin-function.rst 26 | 27 | Registers 28 | ~~~~~~~~~ 29 | 30 | Pinmux module controls attributes of pins. These attributes including function, 31 | pull up, pull down or no pull, if schmitt trigger is enabled and driving strength. 32 | 33 | The base address is listed in table :ref:`mmap_table`, PINMUX device. 34 | 35 | .. include:: pinmux-reg.rst 36 | -------------------------------------------------------------------------------- /SG2044/HowTo/SG2044 Boot Flow.rst: -------------------------------------------------------------------------------- 1 | ================ 2 | SG2044 Boot Flow 3 | ================ 4 | 5 | SG2044's original firmware boot process: 6 | 7 | .. code-block:: text 8 | 9 | +---------+ +------+ +------+ +---------+ +--------+ +--------+ +-------+ 10 | | BootROM |--->| FSBL |--->| ZSBL |--->| OpenSBI |--->| EDK II |--->| GRUB 2 |--->| Linux | 11 | +---------+ +------+ +------+ +---------+ +--------+ +--------+ +-------+ 12 | 13 | - **BootROM** 14 | 15 | Boot code in the ROM. 16 | 17 | - **FSBL (First-Stage BootLoader)** 18 | 19 | System Code to initialize DDR, PCIe Controller, etc. 20 | 21 | - **ZSBL (Zero-Stage BootLoader)** 22 | 23 | Mainly load configuration file (``conf.ini``), DTB, binaries of OpenSBI, and EDK II from microSD card or SPI Nor Flash into memory. 24 | 25 | - **OpenSBI (RISC-V Open Source Supervisor Binary Interface)** 26 | 27 | An open-source reference implementation of the RISC-V SBI 28 | specifications for platform-specific firmwares executing in M-mode. 29 | 30 | - **EDK II (EFI Development Kit Version 2)** 31 | 32 | The reference implementation of UEFI. Unified Extensible Firmware Interface (UEFI) 33 | is a specification for a software program that connects a computer's firmware to its operating system (OS). 34 | 35 | - **GRUB 2 (GRand Unified Bootloader Version 2)** 36 | 37 | Load and transfer control to Linux OS. 38 | 39 | - **Linux** 40 | 41 | Supported Linux distributions: Ubuntu 24.04.1, openEuler 24.03. 42 | 43 | Supported Linux Kernel Version: 6.12. 44 | 45 | --------------------------------------------------------------------------------