├── .gitignore ├── .screenshots └── block-design.png ├── README.md ├── hls-src ├── huffman.h ├── huffman_canonize_tree.cpp ├── huffman_compute_bit_length.cpp ├── huffman_create_codeword.cpp ├── huffman_create_tree.cpp ├── huffman_encoding.cpp ├── huffman_filter.cpp ├── huffman_sort.cpp └── huffman_truncate_tree.cpp ├── setup.tcl └── tests ├── canonize-tree-test ├── bitstream │ ├── canonize-tree-test.bit │ └── canonize-tree-test.tcl └── notebook │ └── canonize-tree-test.ipynb ├── compute-bit-length-test ├── bitstream │ ├── compute-bit-length-test.bit │ └── compute-bit-length-test.tcl └── notebook │ └── compute-bit-length-test.ipynb ├── create-code-word-test ├── bitstream │ ├── create-code-word-test.bit │ └── create-code-word-test.tcl └── notebook │ └── create-code-word-test.ipynb ├── create-tree-core-test ├── bitstream │ ├── create-tree-test.bit │ └── create-tree-test.tcl └── notebook │ └── create-tree-test.ipynb ├── huffman-encoding-test ├── bitstream │ ├── huffman-encoding-test.bit │ └── huffman-encoding-test.tcl └── notebook │ └── huffman-encoding-test.ipynb ├── irq-test ├── bitstream │ ├── irq-test.bit │ └── irq-test.tcl └── notebook │ └── irq-test.ipynb ├── sort-core-test ├── bitstream │ ├── sort-test.bit │ └── sort-test.tcl └── notebook │ ├── .ipynb_checkpoints │ └── sort-test-checkpoint.ipynb │ └── sort-test.ipynb └── truncate-tree-test ├── bitstream ├── truncate-tree-test.bit └── truncate-tree-test.tcl └── notebook └── truncate-tree-test.ipynb /.gitignore: -------------------------------------------------------------------------------- 1 | # log & journal files 2 | *.log 3 | *.jou 4 | -------------------------------------------------------------------------------- /.screenshots/block-design.png: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/.screenshots/block-design.png -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # huffman-encoding-core 2 | Huffman encoding core (Vivado HLS) 3 | 4 | ### Overview 5 | ![block design](./.screenshots/block-design.png) 6 | 7 | ### How to run 8 | 9 | #### Download source code 10 | 11 | ```bash 12 | $ git clone https://github.com/sopynq/huffman-encoding-core.git 13 | ``` 14 | 15 | #### Compile source codes with Vivado-HLS 16 | 17 | ```bash 18 | $ cd huffman-encoding-core 19 | $ vivado_hls -f setup.tcl 20 | ``` 21 | 22 | ### Tests 23 | 24 | `tests` folder contains some test cases which should be run on `PYNQ` board. If you are running a bare zynq board you should write drivers yourself 25 | 26 | ### Reference 27 | 28 | [pp4fpga](https://github.com/KastnerRG/pp4fpgas) Chapter 11. 29 | -------------------------------------------------------------------------------- /hls-src/huffman.h: -------------------------------------------------------------------------------- 1 | #include "ap_int.h" 2 | 3 | // input number of symbols 4 | const static int INPUT_SYMBOL_SIZE = 256; 5 | 6 | // upper bound on codeword length during tree construction 7 | const static int TREE_DEPTH = 64; 8 | 9 | // maximum codeword tree length after rebalancing 10 | const static int MAX_CODEWORD_LENGTH = 27; 11 | 12 | // Should be log2(INPUT_SYMBOL_SIZE) 13 | const static int SYMBOL_BITS = 32; 14 | 15 | // Should be log2(TREE_DEPTH) 16 | const static int TREE_DEPTH_BITS = 6; 17 | 18 | // number of bits needed to record MAX_CODEWORD_LENGTH value 19 | // Should be log2(MAX_CODEWORD_LENGTH) 20 | const static int CODEWORD_LENGTH_BITS = 5; 21 | 22 | // A marker for internal nodes 23 | const static ap_uint INTERNAL_NODE = -1; 24 | 25 | typedef ap_uint Codeword; 26 | typedef ap_uint PackedCodewordAndLength; 27 | typedef ap_uint CodewordLength; 28 | typedef ap_uint<32> Frequency; 29 | 30 | struct Symbol { 31 | ap_uint value; 32 | ap_uint<32> frequency; 33 | }; 34 | 35 | void huffman_encoding ( 36 | Symbol in[INPUT_SYMBOL_SIZE], 37 | PackedCodewordAndLength encoding[INPUT_SYMBOL_SIZE], 38 | int *num_nonzero_symbols 39 | ); 40 | 41 | void filter(Symbol in[INPUT_SYMBOL_SIZE], 42 | Symbol out[INPUT_SYMBOL_SIZE], 43 | int *num_symbols); 44 | void sort(Symbol in[INPUT_SYMBOL_SIZE], 45 | int num_symbols, 46 | Symbol out[INPUT_SYMBOL_SIZE]); 47 | void create_tree ( 48 | Symbol in[INPUT_SYMBOL_SIZE], 49 | int num_symbols, 50 | ap_uint parent[INPUT_SYMBOL_SIZE-1], 51 | ap_uint left[INPUT_SYMBOL_SIZE-1], 52 | ap_uint right[INPUT_SYMBOL_SIZE-1]); 53 | 54 | void compute_bit_length ( 55 | ap_uint parent[INPUT_SYMBOL_SIZE-1], 56 | ap_uint left[INPUT_SYMBOL_SIZE-1], 57 | ap_uint right[INPUT_SYMBOL_SIZE-1], 58 | int num_symbols, 59 | ap_uint bit_length[TREE_DEPTH]); 60 | 61 | void truncate_tree( 62 | ap_uint input_bit_length[TREE_DEPTH], 63 | ap_uint truncated_bit_length1[TREE_DEPTH], 64 | ap_uint truncated_bit_length2[TREE_DEPTH]); 65 | 66 | void canonize_tree( 67 | Symbol sorted[INPUT_SYMBOL_SIZE], 68 | ap_uint num_symbols, 69 | ap_uint bit_length[TREE_DEPTH], 70 | CodewordLength symbol_bits[INPUT_SYMBOL_SIZE]); 71 | 72 | void create_codeword( 73 | CodewordLength symbol_bits[INPUT_SYMBOL_SIZE], 74 | ap_uint bit_length[TREE_DEPTH], 75 | PackedCodewordAndLength encoding[INPUT_SYMBOL_SIZE]); 76 | 77 | 78 | static unsigned int bit_reverse32(unsigned int input) { 79 | int i, rev = 0; 80 | for (i = 0; i < 32; i++) { 81 | rev = (rev << 1) | (input & 1); 82 | input = input >> 1; 83 | } 84 | return rev; 85 | } 86 | -------------------------------------------------------------------------------- /hls-src/huffman_canonize_tree.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | 4 | void canonize_tree( 5 | /* input */ Symbol sorted[INPUT_SYMBOL_SIZE], 6 | /* input */ ap_uint num_symbols, 7 | /* input */ ap_uint codeword_length_histogram[TREE_DEPTH], 8 | /* output */ CodewordLength symbol_bits[INPUT_SYMBOL_SIZE] ) { 9 | 10 | assert(num_symbols <= INPUT_SYMBOL_SIZE); 11 | 12 | init_bits: 13 | for(int i = 0; i < INPUT_SYMBOL_SIZE; i++) { 14 | symbol_bits[i] = 0; 15 | } 16 | 17 | ap_uint length = TREE_DEPTH; 18 | ap_uint count = 0; 19 | 20 | // Iterate across the symbols from lowest frequency to highest 21 | // Assign them largest bit length to smallest 22 | process_symbols: 23 | for(int k = 0; k < num_symbols; k++) { 24 | if (count == 0) { 25 | //find the next non-zero bit length 26 | do { 27 | #pragma HLS LOOP_TRIPCOUNT min=1 avg=1 max=2 28 | length--; 29 | // n is the number of symbols with encoded length i 30 | count = codeword_length_histogram[length]; 31 | } 32 | while (count == 0); 33 | } 34 | symbol_bits[sorted[k].value] = length; //assign symbol k to have length bits 35 | count--; //keep assigning i bits until we have counted off n symbols 36 | } 37 | } 38 | -------------------------------------------------------------------------------- /hls-src/huffman_compute_bit_length.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | void compute_bit_length ( 4 | /* input */ ap_uint parent[INPUT_SYMBOL_SIZE-1], 5 | /* input */ ap_uint left[INPUT_SYMBOL_SIZE-1], 6 | /* input */ ap_uint right[INPUT_SYMBOL_SIZE-1], 7 | /* input */ int num_symbols, 8 | /* output */ ap_uint length_histogram[TREE_DEPTH]) { 9 | 10 | assert(num_symbols > 0); 11 | assert(num_symbols <= INPUT_SYMBOL_SIZE); 12 | ap_uint child_depth[INPUT_SYMBOL_SIZE-1]; 13 | ap_uint internal_length_histogram[TREE_DEPTH]; 14 | init_histogram: 15 | for(int i = 0; i < TREE_DEPTH; i++) { 16 | #pragma HLS pipeline II=1 17 | internal_length_histogram[i] = 0; 18 | } 19 | 20 | child_depth[num_symbols-2] = 1; // Depth of the root node is 1. 21 | 22 | traverse_tree: 23 | for(int i = num_symbols-3; i >= 0; i--) { 24 | #pragma HLS pipeline II=3 25 | ap_uint length = child_depth[parent[i]] + 1; 26 | child_depth[i] = length; 27 | if(left[i] != INTERNAL_NODE || right[i] != INTERNAL_NODE){ 28 | int children; 29 | if(left[i] != INTERNAL_NODE && right[i] != INTERNAL_NODE) { 30 | // Both the children of the original node were symbols 31 | children = 2; 32 | } else { 33 | // One child of the original node was a symbol 34 | children = 1; 35 | } 36 | ap_uint count = internal_length_histogram[length]; 37 | count += children; 38 | internal_length_histogram[length] = count; 39 | length_histogram[length] = count; 40 | } 41 | } 42 | } 43 | -------------------------------------------------------------------------------- /hls-src/huffman_create_codeword.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | #include 4 | 5 | void create_codeword( 6 | /* input */ CodewordLength symbol_bits[INPUT_SYMBOL_SIZE], 7 | /* input */ ap_uint codeword_length_histogram[TREE_DEPTH], 8 | /* output */ PackedCodewordAndLength encoding[INPUT_SYMBOL_SIZE] 9 | ) { 10 | 11 | Codeword first_codeword[MAX_CODEWORD_LENGTH]; 12 | 13 | // Computes the initial codeword value for a symbol with bit length i 14 | first_codeword[0] = 0; 15 | first_codewords: 16 | for(int i = 1; i < MAX_CODEWORD_LENGTH; i++) { 17 | #pragma HLS PIPELINE II=1 18 | first_codeword[i] = (first_codeword[i-1] + codeword_length_histogram[i-1]) << 1; 19 | Codeword c = first_codeword[i]; 20 | // std::cout << c.to_string(2) << " with length " << i << "\n"; 21 | } 22 | 23 | assign_codewords: 24 | for (int i = 0; i < INPUT_SYMBOL_SIZE; ++i) { 25 | #pragma HLS PIPELINE II=5 26 | CodewordLength length = symbol_bits[i]; 27 | //if symbol has 0 bits, it doesn't need to be encoded 28 | make_codeword: 29 | if(length != 0) { 30 | // std::cout << first_codeword[length].to_string(2) << "\n"; 31 | Codeword out_reversed = first_codeword[length]; 32 | out_reversed.reverse(); 33 | out_reversed = out_reversed >> (MAX_CODEWORD_LENGTH - length); 34 | // std::cout << out_reversed.to_string(2) << "\n"; 35 | encoding[i] = (out_reversed << CODEWORD_LENGTH_BITS) + length; 36 | first_codeword[length]++; 37 | } else { 38 | encoding[i] = 0; 39 | } 40 | } 41 | } 42 | -------------------------------------------------------------------------------- /hls-src/huffman_create_tree.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | void create_tree ( 4 | /* input */ Symbol in[INPUT_SYMBOL_SIZE], 5 | /* input */ int num_symbols, 6 | /* output */ ap_uint parent[INPUT_SYMBOL_SIZE-1], 7 | /* output */ ap_uint left[INPUT_SYMBOL_SIZE-1], 8 | /* output */ ap_uint right[INPUT_SYMBOL_SIZE-1]) { 9 | 10 | Frequency frequency[INPUT_SYMBOL_SIZE-1]; 11 | ap_uint tree_count = 0; // Number of intermediate nodes assigned a parent. 12 | ap_uint in_count = 0; // Number of inputs consumed. 13 | 14 | assert(num_symbols > 0); 15 | assert(num_symbols <= INPUT_SYMBOL_SIZE); 16 | 17 | for(int i = 0; i < (num_symbols-1); i++) { 18 | #pragma HLS PIPELINE II=5 19 | Frequency node_freq = 0; 20 | 21 | // There are two cases. 22 | // Case 1: remove a Symbol from in[] 23 | // Case 2: remove an element from intermediate[] 24 | // We do this twice, once for the left and once for the right of the new intermediate node. 25 | assert(in_count < num_symbols || tree_count < i); 26 | Frequency intermediate_freq = frequency[tree_count]; 27 | Symbol s = in[in_count]; 28 | if((in_count < num_symbols && s.frequency <= intermediate_freq) || tree_count == i) { 29 | // Pick symbol from in[]. 30 | left[i] = s.value; // Set input symbol as left node 31 | node_freq = s.frequency; // Add symbol frequency to total node frequency 32 | in_count++; // Move to the next input symbol 33 | } else { 34 | // Pick internal node without a parent. 35 | left[i] = INTERNAL_NODE; // Set symbol to indicate an internal node 36 | node_freq = frequency[tree_count]; // Add child node frequency 37 | parent[tree_count] = i; // Set this node as child's parent 38 | tree_count++; // Go to next parentless internal node 39 | } 40 | 41 | assert(in_count < num_symbols || tree_count < i); 42 | intermediate_freq = frequency[tree_count]; 43 | s = in[in_count]; 44 | if((in_count < num_symbols && s.frequency <= intermediate_freq) || tree_count == i) { 45 | // Pick symbol from in[]. 46 | right[i] = s.value; 47 | frequency[i] = node_freq + s.frequency; 48 | in_count++; 49 | } else { 50 | // Pick internal node without a parent. 51 | right[i] = INTERNAL_NODE; 52 | frequency[i] = node_freq + intermediate_freq; 53 | parent[tree_count] = i; 54 | tree_count++; 55 | } 56 | // Verify that nodes in the tree are sorted by frequency 57 | assert(i == 0 || frequency[i] >= frequency[i-1]); 58 | } 59 | 60 | parent[tree_count] = 0; //Set parent of last node (root) to 0 61 | } 62 | -------------------------------------------------------------------------------- /hls-src/huffman_encoding.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | 4 | void huffman_encoding( 5 | /* input */ Symbol symbol_histogram[INPUT_SYMBOL_SIZE], 6 | /* output */ PackedCodewordAndLength encoding[INPUT_SYMBOL_SIZE], 7 | /* output */ int *num_nonzero_symbols) { 8 | 9 | /* 10 | * Create an new AXI-LITE bus as control bus 11 | * */ 12 | #pragma HLS INTERFACE s_axilite port=return 13 | 14 | /* 15 | * Create an AXI bus for data transferring 16 | * */ 17 | #pragma HLS INTERFACE s_axilite port=symbol_histogram 18 | #pragma HLS INTERFACE s_axilite port=encoding 19 | #pragma HLS INTERFACE s_axilite port=num_nonzero_symbols 20 | 21 | #pragma HLS DATAFLOW 22 | 23 | Symbol filtered[INPUT_SYMBOL_SIZE]; 24 | Symbol sorted[INPUT_SYMBOL_SIZE]; 25 | Symbol sorted_copy1[INPUT_SYMBOL_SIZE]; 26 | Symbol sorted_copy2[INPUT_SYMBOL_SIZE]; 27 | ap_uint parent[INPUT_SYMBOL_SIZE-1]; 28 | ap_uint left[INPUT_SYMBOL_SIZE-1]; 29 | ap_uint right[INPUT_SYMBOL_SIZE-1]; 30 | int n; 31 | 32 | filter(symbol_histogram, filtered, &n); 33 | sort(filtered, n, sorted); 34 | 35 | ap_uint length_histogram[TREE_DEPTH]; 36 | ap_uint truncated_length_histogram1[TREE_DEPTH]; 37 | ap_uint truncated_length_histogram2[TREE_DEPTH]; 38 | CodewordLength symbol_bits[INPUT_SYMBOL_SIZE]; 39 | 40 | int previous_frequency = -1; 41 | copy_sorted: 42 | for(int i = 0; i < n; i++) { 43 | sorted_copy1[i].value = sorted[i].value; 44 | sorted_copy1[i].frequency = sorted[i].frequency; 45 | sorted_copy2[i].value = sorted[i].value; 46 | sorted_copy2[i].frequency = sorted[i].frequency; 47 | // std::cout << sorted[i].value << " " << sorted[i].frequency << "\n"; 48 | assert(previous_frequency <= (int)sorted[i].frequency); 49 | previous_frequency = sorted[i].frequency; 50 | } 51 | 52 | create_tree(sorted_copy1, n, parent, left, right); 53 | compute_bit_length(parent, left, right, n, length_histogram); 54 | 55 | #ifndef __SYNTHESIS__ 56 | // Check the result of computing the tree histogram 57 | int codewords_in_tree = 0; 58 | merge_bit_length: 59 | for(int i = 0; i < TREE_DEPTH; i++) { 60 | #pragma HLS PIPELINE II=1 61 | if(length_histogram[i] > 0) 62 | std::cout << length_histogram[i] << " codewords with length " << i << "\n"; 63 | codewords_in_tree += length_histogram[i]; 64 | } 65 | // prevent infinite loop 66 | // assert(codewords_in_tree == n); 67 | #endif 68 | 69 | truncate_tree(length_histogram, truncated_length_histogram1, truncated_length_histogram2); 70 | canonize_tree(sorted_copy2, n, truncated_length_histogram1, symbol_bits); 71 | create_codeword(symbol_bits, truncated_length_histogram2, encoding); 72 | 73 | *num_nonzero_symbols = n; 74 | } 75 | -------------------------------------------------------------------------------- /hls-src/huffman_filter.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | 3 | void filter( 4 | /* input */ Symbol in[INPUT_SYMBOL_SIZE], 5 | /* output */ Symbol out[INPUT_SYMBOL_SIZE], 6 | /* output */ int *n) { 7 | 8 | #pragma HLS INLINE off 9 | ap_uint j = 0; 10 | for(int i = 0; i < INPUT_SYMBOL_SIZE; i++) { 11 | #pragma HLS pipeline II=1 12 | if(in[i].frequency != 0) { 13 | out[j].frequency = in[i].frequency; 14 | out[j].value = in[i].value; 15 | j++; 16 | } 17 | } 18 | *n = j; 19 | } 20 | -------------------------------------------------------------------------------- /hls-src/huffman_sort.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | 4 | const unsigned int RADIX = 16; 5 | const unsigned int BITS_PER_LOOP = 4; // should be log2(RADIX) 6 | typedef ap_uint Digit; 7 | 8 | void sort( 9 | /* input */ Symbol in[INPUT_SYMBOL_SIZE], 10 | /* input */ int num_symbols, 11 | /* output */ Symbol out[INPUT_SYMBOL_SIZE]) { 12 | 13 | Symbol previous_sorting[INPUT_SYMBOL_SIZE], sorting[INPUT_SYMBOL_SIZE]; 14 | ap_uint digit_histogram[RADIX], digit_location[RADIX]; 15 | 16 | #pragma HLS ARRAY_PARTITION variable=digit_location complete dim=1 17 | #pragma HLS ARRAY_PARTITION variable=digit_histogram complete dim=1 18 | 19 | Digit current_digit[INPUT_SYMBOL_SIZE]; 20 | 21 | assert(num_symbols >= 0); 22 | assert(num_symbols <= INPUT_SYMBOL_SIZE); 23 | copy_in_to_sorting: 24 | for(int j = 0; j < num_symbols; j++) { 25 | #pragma HLS PIPELINE II=1 26 | sorting[j] = in[j]; 27 | } 28 | 29 | radix_sort: 30 | for(int shift = 0; shift < 32; shift += BITS_PER_LOOP) { 31 | init_histogram: 32 | for(int i = 0; i < RADIX; i++) { 33 | #pragma HLS pipeline II=1 34 | digit_histogram[i] = 0; 35 | } 36 | 37 | compute_histogram: 38 | for(int j = 0; j < num_symbols; j++) { 39 | #pragma HLS PIPELINE II=1 40 | Digit digit = (sorting[j].frequency >> shift) & (RADIX - 1); // Extrract a digit 41 | current_digit[j] = digit; // Store the current digit for each symbol 42 | digit_histogram[digit]++; 43 | previous_sorting[j] = sorting[j]; // Save the current sorted order of symbols 44 | } 45 | 46 | digit_location[0] = 0; 47 | find_digit_location: 48 | for(int i = 1; i < RADIX; i++) 49 | #pragma HLS PIPELINE II=1 50 | digit_location[i] = digit_location[i-1] + digit_histogram[i-1]; 51 | 52 | re_sort: 53 | for(int j = 0; j < num_symbols; j++) { 54 | #pragma HLS PIPELINE II=1 55 | Digit digit = current_digit[j]; 56 | sorting[digit_location[digit]] = previous_sorting[j]; // Move symbol to new sorted location 57 | out[digit_location[digit]] = previous_sorting[j]; // Also copy to output 58 | digit_location[digit]++; // Update digit_location 59 | } 60 | } 61 | } 62 | -------------------------------------------------------------------------------- /hls-src/huffman_truncate_tree.cpp: -------------------------------------------------------------------------------- 1 | #include "huffman.h" 2 | #include "assert.h" 3 | 4 | void truncate_tree( 5 | /* input */ ap_uint input_length_histogram[TREE_DEPTH], 6 | /* output */ ap_uint output_length_histogram_0[TREE_DEPTH], 7 | /* output */ ap_uint output_length_histogram_1[TREE_DEPTH] 8 | ) { 9 | 10 | // Copy into temporary storage to maintain dataflow properties 11 | copy_input: 12 | for(int i = 0; i < TREE_DEPTH; i++) { 13 | output_length_histogram_0[i] = input_length_histogram[i]; 14 | } 15 | 16 | ap_uint j = MAX_CODEWORD_LENGTH; 17 | move_nodes: 18 | for(int i = TREE_DEPTH - 1; i > MAX_CODEWORD_LENGTH; i--) { 19 | // Look to see if there is any nodes at lengths greater than target depth 20 | reorder: 21 | while(output_length_histogram_0[i] != 0) { 22 | #pragma HLS LOOP_TRIPCOUNT min=3 max=3 avg=3 23 | if (j == MAX_CODEWORD_LENGTH) { 24 | // Find deepest leaf with codeword length < target depth 25 | do { 26 | #pragma HLS LOOP_TRIPCOUNT min=1 max=1 avg=1 27 | j--; 28 | } while(output_length_histogram_0[j] == 0); 29 | } 30 | 31 | // Move leaf with depth i to depth j+1. 32 | output_length_histogram_0[j] -= 1; // The node at level j is no longer a leaf. 33 | output_length_histogram_0[j+1] += 2; // Two new leaf nodes are attached at level j+1. 34 | output_length_histogram_0[i-1] += 1; // The leaf node at level i+1 gets attached here. 35 | output_length_histogram_0[i] -= 2; // Two leaf nodes have been lost from level i. 36 | 37 | // now deepest leaf with codeword length < target length 38 | // is at level (j+1) unless j+1 == target length 39 | j++; 40 | } 41 | } 42 | 43 | // Copy the output to meet dataflow requirements and check the validity 44 | unsigned int limit = 1; 45 | copy_output: 46 | for(int i = 0; i < TREE_DEPTH; i++) { 47 | output_length_histogram_1[i] = output_length_histogram_0[i]; 48 | assert(output_length_histogram_0[i] >= 0); 49 | assert(output_length_histogram_0[i] <= limit); 50 | limit *= 2; 51 | } 52 | } 53 | -------------------------------------------------------------------------------- /setup.tcl: -------------------------------------------------------------------------------- 1 | ################################################################### 2 | # 3 | # This TCL script is for setting up axi-huffman-encoder-core 4 | # Including synthesis, simulation, co-simulation, export-rtl 5 | # Copyright (c) 2018 Xing GUO 6 | # 7 | ################################################################### 8 | 9 | # Global settings 10 | set project_name huffman_encoding_core_build 11 | set device "xc7z020clg400-1" 12 | set clock_period 10 13 | set solution_dir solution 14 | 15 | # Open project 16 | open_project $project_name -reset 17 | 18 | # add files for synthesis 19 | add_files { 20 | ./hls-src/huffman_canonize_tree.cpp 21 | ./hls-src/huffman_create_tree.cpp 22 | ./hls-src/huffman_filter.cpp 23 | ./hls-src/huffman_compute_bit_length.cpp 24 | ./hls-src/huffman_encoding.cpp 25 | ./hls-src/huffman_sort.cpp 26 | ./hls-src/huffman_create_codeword.cpp 27 | ./hls-src/huffman_truncate_tree.cpp 28 | } 29 | 30 | # set top module 31 | set_top huffman_encoding 32 | 33 | # open solution 34 | open_solution $solution_dir -reset 35 | 36 | # set device part 37 | set_part $device 38 | 39 | # create clock 40 | create_clock -period $clock_period 41 | 42 | # C-simulation 43 | # csim_design -compiler clang 44 | 45 | # C-synthesis 46 | csynth_design 47 | 48 | # export_design 49 | # [Options] 50 | # -description 51 | # -flow 52 | # -format 53 | # -library 54 | # -rtl 55 | # -vendor 56 | # -version 57 | export_design -flow syn -format ip_catalog -rtl verilog -vendor "com.xilinx.hls" -version "0.0.1" 58 | 59 | # exit 60 | exit 61 | 62 | -------------------------------------------------------------------------------- /tests/canonize-tree-test/bitstream/canonize-tree-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/canonize-tree-test/bitstream/canonize-tree-test.bit -------------------------------------------------------------------------------- /tests/canonize-tree-test/bitstream/canonize-tree-test.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: axi_huffman_encoder_bd 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | namespace eval _tcl { 11 | proc get_script_folder {} { 12 | set script_path [file normalize [info script]] 13 | set script_folder [file dirname $script_path] 14 | return $script_folder 15 | } 16 | } 17 | variable script_folder 18 | set script_folder [_tcl::get_script_folder] 19 | 20 | ################################################################ 21 | # Check if script is running in correct Vivado version. 22 | ################################################################ 23 | set scripts_vivado_version 2017.4 24 | set current_vivado_version [version -short] 25 | 26 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 27 | puts "" 28 | catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 29 | 30 | return 1 31 | } 32 | 33 | ################################################################ 34 | # START 35 | ################################################################ 36 | 37 | # To test this script, run the following commands from Vivado Tcl console: 38 | # source axi_huffman_encoder_bd_script.tcl 39 | 40 | # If there is no project opened, this script will create a 41 | # project, but make sure you do not have an existing project 42 | # <./myproj/project_1.xpr> in the current working folder. 43 | 44 | set list_projs [get_projects -quiet] 45 | if { $list_projs eq "" } { 46 | create_project project_1 myproj -part xc7z020clg400-1 47 | set_property BOARD_PART tul.com.tw:pynq-z2:part0:1.0 [current_project] 48 | } 49 | 50 | 51 | # CHANGE DESIGN NAME HERE 52 | variable design_name 53 | set design_name axi_huffman_encoder_bd 54 | 55 | # If you do not already have an existing IP Integrator design open, 56 | # you can create a design using the following command: 57 | # create_bd_design $design_name 58 | 59 | # Creating design if needed 60 | set errMsg "" 61 | set nRet 0 62 | 63 | set cur_design [current_bd_design -quiet] 64 | set list_cells [get_bd_cells -quiet] 65 | 66 | if { ${design_name} eq "" } { 67 | # USE CASES: 68 | # 1) Design_name not set 69 | 70 | set errMsg "Please set the variable to a non-empty value." 71 | set nRet 1 72 | 73 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 74 | # USE CASES: 75 | # 2): Current design opened AND is empty AND names same. 76 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 77 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 78 | 79 | if { $cur_design ne $design_name } { 80 | common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." 81 | set design_name [get_property NAME $cur_design] 82 | } 83 | common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." 84 | 85 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 86 | # USE CASES: 87 | # 5) Current design opened AND has components AND same names. 88 | 89 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 90 | set nRet 1 91 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 92 | # USE CASES: 93 | # 6) Current opened design, has components, but diff names, design_name exists in project. 94 | # 7) No opened design, design_name exists in project. 95 | 96 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 97 | set nRet 2 98 | 99 | } else { 100 | # USE CASES: 101 | # 8) No opened design, design_name not in project. 102 | # 9) Current opened design, has components, but diff names, design_name not in project. 103 | 104 | common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." 105 | 106 | create_bd_design $design_name 107 | 108 | common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." 109 | current_bd_design $design_name 110 | 111 | } 112 | 113 | common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." 114 | 115 | if { $nRet != 0 } { 116 | catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} 117 | return $nRet 118 | } 119 | 120 | set bCheckIPsPassed 1 121 | ################################################################## 122 | # CHECK IPs 123 | ################################################################## 124 | set bCheckIPs 1 125 | if { $bCheckIPs == 1 } { 126 | set list_check_ips "\ 127 | xilinx.com:hls:canonize_tree:1.0\ 128 | xilinx.com:ip:processing_system7:5.5\ 129 | xilinx.com:ip:proc_sys_reset:5.0\ 130 | " 131 | 132 | set list_ips_missing "" 133 | common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 134 | 135 | foreach ip_vlnv $list_check_ips { 136 | set ip_obj [get_ipdefs -all $ip_vlnv] 137 | if { $ip_obj eq "" } { 138 | lappend list_ips_missing $ip_vlnv 139 | } 140 | } 141 | 142 | if { $list_ips_missing ne "" } { 143 | catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 144 | set bCheckIPsPassed 0 145 | } 146 | 147 | } 148 | 149 | if { $bCheckIPsPassed != 1 } { 150 | common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." 151 | return 3 152 | } 153 | 154 | ################################################################## 155 | # DESIGN PROCs 156 | ################################################################## 157 | 158 | 159 | 160 | # Procedure to create entire design; Provide argument to make 161 | # procedure reusable. If parentCell is "", will use root. 162 | proc create_root_design { parentCell } { 163 | 164 | variable script_folder 165 | variable design_name 166 | 167 | if { $parentCell eq "" } { 168 | set parentCell [get_bd_cells /] 169 | } 170 | 171 | # Get object for parentCell 172 | set parentObj [get_bd_cells $parentCell] 173 | if { $parentObj == "" } { 174 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 175 | return 176 | } 177 | 178 | # Make sure parentObj is hier blk 179 | set parentType [get_property TYPE $parentObj] 180 | if { $parentType ne "hier" } { 181 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 182 | return 183 | } 184 | 185 | # Save current instance; Restore later 186 | set oldCurInst [current_bd_instance .] 187 | 188 | # Set parent object as current 189 | current_bd_instance $parentObj 190 | 191 | 192 | # Create interface ports 193 | set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] 194 | set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] 195 | 196 | # Create ports 197 | 198 | # Create instance: canonize_tree_0, and set properties 199 | set canonize_tree_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:canonize_tree:1.0 canonize_tree_0 ] 200 | 201 | set_property -dict [ list \ 202 | CONFIG.NUM_READ_OUTSTANDING {1} \ 203 | CONFIG.NUM_WRITE_OUTSTANDING {1} \ 204 | ] [get_bd_intf_pins /canonize_tree_0/s_axi_AXILiteS] 205 | 206 | # Create instance: processing_system7_0, and set properties 207 | set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] 208 | set_property -dict [ list \ 209 | CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ 210 | CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ 211 | CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ 212 | CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ 213 | CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ 214 | CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ 215 | CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ 216 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 217 | CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ 218 | CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ 219 | CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ 220 | CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ 221 | CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ 222 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ 223 | CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ 224 | CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ 225 | CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ 226 | CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ 227 | CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 228 | CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 229 | CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 230 | CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 231 | CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 232 | CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 233 | CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ 234 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ 235 | CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ 236 | CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ 237 | CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ 238 | CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ 239 | CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ 240 | CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ 241 | CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ 242 | CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ 243 | CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ 244 | CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ 245 | CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ 246 | CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ 247 | CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ 248 | CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ 249 | CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ 250 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ 251 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ 252 | CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ 253 | CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ 254 | CONFIG.PCW_CLK0_FREQ {100000000} \ 255 | CONFIG.PCW_CLK1_FREQ {10000000} \ 256 | CONFIG.PCW_CLK2_FREQ {10000000} \ 257 | CONFIG.PCW_CLK3_FREQ {10000000} \ 258 | CONFIG.PCW_CORE0_FIQ_INTR {0} \ 259 | CONFIG.PCW_CORE0_IRQ_INTR {0} \ 260 | CONFIG.PCW_CORE1_FIQ_INTR {0} \ 261 | CONFIG.PCW_CORE1_IRQ_INTR {0} \ 262 | CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ 263 | CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ 264 | CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ 265 | CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ 266 | CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ 267 | CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ 268 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ 269 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ 270 | CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ 271 | CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ 272 | CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ 273 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 274 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 275 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 276 | CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ 277 | CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ 278 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 279 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 280 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 281 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 282 | CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ 283 | CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ 284 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 285 | CONFIG.PCW_DM_WIDTH {4} \ 286 | CONFIG.PCW_DQS_WIDTH {4} \ 287 | CONFIG.PCW_DQ_WIDTH {32} \ 288 | CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ 289 | CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 290 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ 291 | CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 292 | CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ 293 | CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ 294 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ 295 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ 296 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ 297 | CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ 298 | CONFIG.PCW_ENET0_RESET_ENABLE {1} \ 299 | CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ 300 | CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ 301 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 302 | CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ 303 | CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ 304 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ 305 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ 306 | CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ 307 | CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ 308 | CONFIG.PCW_ENET1_RESET_ENABLE {0} \ 309 | CONFIG.PCW_ENET_RESET_ENABLE {1} \ 310 | CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ 311 | CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ 312 | CONFIG.PCW_EN_4K_TIMER {0} \ 313 | CONFIG.PCW_EN_CAN0 {0} \ 314 | CONFIG.PCW_EN_CAN1 {0} \ 315 | CONFIG.PCW_EN_CLK0_PORT {1} \ 316 | CONFIG.PCW_EN_CLK1_PORT {0} \ 317 | CONFIG.PCW_EN_CLK2_PORT {0} \ 318 | CONFIG.PCW_EN_CLK3_PORT {0} \ 319 | CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ 320 | CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ 321 | CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ 322 | CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ 323 | CONFIG.PCW_EN_DDR {1} \ 324 | CONFIG.PCW_EN_EMIO_CAN0 {0} \ 325 | CONFIG.PCW_EN_EMIO_CAN1 {0} \ 326 | CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ 327 | CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ 328 | CONFIG.PCW_EN_EMIO_ENET0 {0} \ 329 | CONFIG.PCW_EN_EMIO_ENET1 {0} \ 330 | CONFIG.PCW_EN_EMIO_GPIO {0} \ 331 | CONFIG.PCW_EN_EMIO_I2C0 {0} \ 332 | CONFIG.PCW_EN_EMIO_I2C1 {0} \ 333 | CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ 334 | CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ 335 | CONFIG.PCW_EN_EMIO_PJTAG {0} \ 336 | CONFIG.PCW_EN_EMIO_SDIO0 {0} \ 337 | CONFIG.PCW_EN_EMIO_SDIO1 {0} \ 338 | CONFIG.PCW_EN_EMIO_SPI0 {0} \ 339 | CONFIG.PCW_EN_EMIO_SPI1 {0} \ 340 | CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ 341 | CONFIG.PCW_EN_EMIO_TRACE {0} \ 342 | CONFIG.PCW_EN_EMIO_TTC0 {0} \ 343 | CONFIG.PCW_EN_EMIO_TTC1 {0} \ 344 | CONFIG.PCW_EN_EMIO_UART0 {0} \ 345 | CONFIG.PCW_EN_EMIO_UART1 {0} \ 346 | CONFIG.PCW_EN_EMIO_WDT {0} \ 347 | CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ 348 | CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ 349 | CONFIG.PCW_EN_ENET0 {1} \ 350 | CONFIG.PCW_EN_ENET1 {0} \ 351 | CONFIG.PCW_EN_GPIO {1} \ 352 | CONFIG.PCW_EN_I2C0 {0} \ 353 | CONFIG.PCW_EN_I2C1 {0} \ 354 | CONFIG.PCW_EN_MODEM_UART0 {0} \ 355 | CONFIG.PCW_EN_MODEM_UART1 {0} \ 356 | CONFIG.PCW_EN_PJTAG {0} \ 357 | CONFIG.PCW_EN_PTP_ENET0 {0} \ 358 | CONFIG.PCW_EN_PTP_ENET1 {0} \ 359 | CONFIG.PCW_EN_QSPI {1} \ 360 | CONFIG.PCW_EN_RST0_PORT {1} \ 361 | CONFIG.PCW_EN_RST1_PORT {0} \ 362 | CONFIG.PCW_EN_RST2_PORT {0} \ 363 | CONFIG.PCW_EN_RST3_PORT {0} \ 364 | CONFIG.PCW_EN_SDIO0 {1} \ 365 | CONFIG.PCW_EN_SDIO1 {0} \ 366 | CONFIG.PCW_EN_SMC {0} \ 367 | CONFIG.PCW_EN_SPI0 {0} \ 368 | CONFIG.PCW_EN_SPI1 {0} \ 369 | CONFIG.PCW_EN_TRACE {0} \ 370 | CONFIG.PCW_EN_TTC0 {0} \ 371 | CONFIG.PCW_EN_TTC1 {0} \ 372 | CONFIG.PCW_EN_UART0 {1} \ 373 | CONFIG.PCW_EN_UART1 {0} \ 374 | CONFIG.PCW_EN_USB0 {1} \ 375 | CONFIG.PCW_EN_USB1 {0} \ 376 | CONFIG.PCW_EN_WDT {0} \ 377 | CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ 378 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ 379 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ 380 | CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ 381 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ 382 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ 383 | CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ 384 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ 385 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ 386 | CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ 387 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ 388 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ 389 | CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ 390 | CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ 391 | CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ 392 | CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ 393 | CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ 394 | CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ 395 | CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ 396 | CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ 397 | CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ 398 | CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ 399 | CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ 400 | CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ 401 | CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ 402 | CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ 403 | CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ 404 | CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ 405 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ 406 | CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 407 | CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ 408 | CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ 409 | CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ 410 | CONFIG.PCW_I2C0_RESET_ENABLE {0} \ 411 | CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ 412 | CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ 413 | CONFIG.PCW_I2C1_RESET_ENABLE {0} \ 414 | CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ 415 | CONFIG.PCW_I2C_RESET_ENABLE {1} \ 416 | CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ 417 | CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ 418 | CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ 419 | CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ 420 | CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ 421 | CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ 422 | CONFIG.PCW_IRQ_F2P_INTR {0} \ 423 | CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ 424 | CONFIG.PCW_MIO_0_DIRECTION {inout} \ 425 | CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ 426 | CONFIG.PCW_MIO_0_PULLUP {enabled} \ 427 | CONFIG.PCW_MIO_0_SLEW {slow} \ 428 | CONFIG.PCW_MIO_10_DIRECTION {inout} \ 429 | CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ 430 | CONFIG.PCW_MIO_10_PULLUP {enabled} \ 431 | CONFIG.PCW_MIO_10_SLEW {slow} \ 432 | CONFIG.PCW_MIO_11_DIRECTION {inout} \ 433 | CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ 434 | CONFIG.PCW_MIO_11_PULLUP {enabled} \ 435 | CONFIG.PCW_MIO_11_SLEW {slow} \ 436 | CONFIG.PCW_MIO_12_DIRECTION {inout} \ 437 | CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ 438 | CONFIG.PCW_MIO_12_PULLUP {enabled} \ 439 | CONFIG.PCW_MIO_12_SLEW {slow} \ 440 | CONFIG.PCW_MIO_13_DIRECTION {inout} \ 441 | CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ 442 | CONFIG.PCW_MIO_13_PULLUP {enabled} \ 443 | CONFIG.PCW_MIO_13_SLEW {slow} \ 444 | CONFIG.PCW_MIO_14_DIRECTION {in} \ 445 | CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ 446 | CONFIG.PCW_MIO_14_PULLUP {enabled} \ 447 | CONFIG.PCW_MIO_14_SLEW {slow} \ 448 | CONFIG.PCW_MIO_15_DIRECTION {out} \ 449 | CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ 450 | CONFIG.PCW_MIO_15_PULLUP {enabled} \ 451 | CONFIG.PCW_MIO_15_SLEW {slow} \ 452 | CONFIG.PCW_MIO_16_DIRECTION {out} \ 453 | CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ 454 | CONFIG.PCW_MIO_16_PULLUP {enabled} \ 455 | CONFIG.PCW_MIO_16_SLEW {slow} \ 456 | CONFIG.PCW_MIO_17_DIRECTION {out} \ 457 | CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ 458 | CONFIG.PCW_MIO_17_PULLUP {enabled} \ 459 | CONFIG.PCW_MIO_17_SLEW {slow} \ 460 | CONFIG.PCW_MIO_18_DIRECTION {out} \ 461 | CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ 462 | CONFIG.PCW_MIO_18_PULLUP {enabled} \ 463 | CONFIG.PCW_MIO_18_SLEW {slow} \ 464 | CONFIG.PCW_MIO_19_DIRECTION {out} \ 465 | CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ 466 | CONFIG.PCW_MIO_19_PULLUP {enabled} \ 467 | CONFIG.PCW_MIO_19_SLEW {slow} \ 468 | CONFIG.PCW_MIO_1_DIRECTION {out} \ 469 | CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ 470 | CONFIG.PCW_MIO_1_PULLUP {enabled} \ 471 | CONFIG.PCW_MIO_1_SLEW {slow} \ 472 | CONFIG.PCW_MIO_20_DIRECTION {out} \ 473 | CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ 474 | CONFIG.PCW_MIO_20_PULLUP {enabled} \ 475 | CONFIG.PCW_MIO_20_SLEW {slow} \ 476 | CONFIG.PCW_MIO_21_DIRECTION {out} \ 477 | CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ 478 | CONFIG.PCW_MIO_21_PULLUP {enabled} \ 479 | CONFIG.PCW_MIO_21_SLEW {slow} \ 480 | CONFIG.PCW_MIO_22_DIRECTION {in} \ 481 | CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ 482 | CONFIG.PCW_MIO_22_PULLUP {enabled} \ 483 | CONFIG.PCW_MIO_22_SLEW {slow} \ 484 | CONFIG.PCW_MIO_23_DIRECTION {in} \ 485 | CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ 486 | CONFIG.PCW_MIO_23_PULLUP {enabled} \ 487 | CONFIG.PCW_MIO_23_SLEW {slow} \ 488 | CONFIG.PCW_MIO_24_DIRECTION {in} \ 489 | CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ 490 | CONFIG.PCW_MIO_24_PULLUP {enabled} \ 491 | CONFIG.PCW_MIO_24_SLEW {slow} \ 492 | CONFIG.PCW_MIO_25_DIRECTION {in} \ 493 | CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ 494 | CONFIG.PCW_MIO_25_PULLUP {enabled} \ 495 | CONFIG.PCW_MIO_25_SLEW {slow} \ 496 | CONFIG.PCW_MIO_26_DIRECTION {in} \ 497 | CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ 498 | CONFIG.PCW_MIO_26_PULLUP {enabled} \ 499 | CONFIG.PCW_MIO_26_SLEW {slow} \ 500 | CONFIG.PCW_MIO_27_DIRECTION {in} \ 501 | CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ 502 | CONFIG.PCW_MIO_27_PULLUP {enabled} \ 503 | CONFIG.PCW_MIO_27_SLEW {slow} \ 504 | CONFIG.PCW_MIO_28_DIRECTION {inout} \ 505 | CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ 506 | CONFIG.PCW_MIO_28_PULLUP {enabled} \ 507 | CONFIG.PCW_MIO_28_SLEW {slow} \ 508 | CONFIG.PCW_MIO_29_DIRECTION {in} \ 509 | CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ 510 | CONFIG.PCW_MIO_29_PULLUP {enabled} \ 511 | CONFIG.PCW_MIO_29_SLEW {slow} \ 512 | CONFIG.PCW_MIO_2_DIRECTION {inout} \ 513 | CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ 514 | CONFIG.PCW_MIO_2_PULLUP {disabled} \ 515 | CONFIG.PCW_MIO_2_SLEW {slow} \ 516 | CONFIG.PCW_MIO_30_DIRECTION {out} \ 517 | CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ 518 | CONFIG.PCW_MIO_30_PULLUP {enabled} \ 519 | CONFIG.PCW_MIO_30_SLEW {slow} \ 520 | CONFIG.PCW_MIO_31_DIRECTION {in} \ 521 | CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ 522 | CONFIG.PCW_MIO_31_PULLUP {enabled} \ 523 | CONFIG.PCW_MIO_31_SLEW {slow} \ 524 | CONFIG.PCW_MIO_32_DIRECTION {inout} \ 525 | CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ 526 | CONFIG.PCW_MIO_32_PULLUP {enabled} \ 527 | CONFIG.PCW_MIO_32_SLEW {slow} \ 528 | CONFIG.PCW_MIO_33_DIRECTION {inout} \ 529 | CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ 530 | CONFIG.PCW_MIO_33_PULLUP {enabled} \ 531 | CONFIG.PCW_MIO_33_SLEW {slow} \ 532 | CONFIG.PCW_MIO_34_DIRECTION {inout} \ 533 | CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ 534 | CONFIG.PCW_MIO_34_PULLUP {enabled} \ 535 | CONFIG.PCW_MIO_34_SLEW {slow} \ 536 | CONFIG.PCW_MIO_35_DIRECTION {inout} \ 537 | CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ 538 | CONFIG.PCW_MIO_35_PULLUP {enabled} \ 539 | CONFIG.PCW_MIO_35_SLEW {slow} \ 540 | CONFIG.PCW_MIO_36_DIRECTION {in} \ 541 | CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ 542 | CONFIG.PCW_MIO_36_PULLUP {enabled} \ 543 | CONFIG.PCW_MIO_36_SLEW {slow} \ 544 | CONFIG.PCW_MIO_37_DIRECTION {inout} \ 545 | CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ 546 | CONFIG.PCW_MIO_37_PULLUP {enabled} \ 547 | CONFIG.PCW_MIO_37_SLEW {slow} \ 548 | CONFIG.PCW_MIO_38_DIRECTION {inout} \ 549 | CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ 550 | CONFIG.PCW_MIO_38_PULLUP {enabled} \ 551 | CONFIG.PCW_MIO_38_SLEW {slow} \ 552 | CONFIG.PCW_MIO_39_DIRECTION {inout} \ 553 | CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ 554 | CONFIG.PCW_MIO_39_PULLUP {enabled} \ 555 | CONFIG.PCW_MIO_39_SLEW {slow} \ 556 | CONFIG.PCW_MIO_3_DIRECTION {inout} \ 557 | CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ 558 | CONFIG.PCW_MIO_3_PULLUP {disabled} \ 559 | CONFIG.PCW_MIO_3_SLEW {slow} \ 560 | CONFIG.PCW_MIO_40_DIRECTION {inout} \ 561 | CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ 562 | CONFIG.PCW_MIO_40_PULLUP {enabled} \ 563 | CONFIG.PCW_MIO_40_SLEW {slow} \ 564 | CONFIG.PCW_MIO_41_DIRECTION {inout} \ 565 | CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ 566 | CONFIG.PCW_MIO_41_PULLUP {enabled} \ 567 | CONFIG.PCW_MIO_41_SLEW {slow} \ 568 | CONFIG.PCW_MIO_42_DIRECTION {inout} \ 569 | CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ 570 | CONFIG.PCW_MIO_42_PULLUP {enabled} \ 571 | CONFIG.PCW_MIO_42_SLEW {slow} \ 572 | CONFIG.PCW_MIO_43_DIRECTION {inout} \ 573 | CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ 574 | CONFIG.PCW_MIO_43_PULLUP {enabled} \ 575 | CONFIG.PCW_MIO_43_SLEW {slow} \ 576 | CONFIG.PCW_MIO_44_DIRECTION {inout} \ 577 | CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ 578 | CONFIG.PCW_MIO_44_PULLUP {enabled} \ 579 | CONFIG.PCW_MIO_44_SLEW {slow} \ 580 | CONFIG.PCW_MIO_45_DIRECTION {inout} \ 581 | CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ 582 | CONFIG.PCW_MIO_45_PULLUP {enabled} \ 583 | CONFIG.PCW_MIO_45_SLEW {slow} \ 584 | CONFIG.PCW_MIO_46_DIRECTION {out} \ 585 | CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ 586 | CONFIG.PCW_MIO_46_PULLUP {enabled} \ 587 | CONFIG.PCW_MIO_46_SLEW {slow} \ 588 | CONFIG.PCW_MIO_47_DIRECTION {in} \ 589 | CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ 590 | CONFIG.PCW_MIO_47_PULLUP {enabled} \ 591 | CONFIG.PCW_MIO_47_SLEW {slow} \ 592 | CONFIG.PCW_MIO_48_DIRECTION {inout} \ 593 | CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ 594 | CONFIG.PCW_MIO_48_PULLUP {enabled} \ 595 | CONFIG.PCW_MIO_48_SLEW {slow} \ 596 | CONFIG.PCW_MIO_49_DIRECTION {inout} \ 597 | CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ 598 | CONFIG.PCW_MIO_49_PULLUP {enabled} \ 599 | CONFIG.PCW_MIO_49_SLEW {slow} \ 600 | CONFIG.PCW_MIO_4_DIRECTION {inout} \ 601 | CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ 602 | CONFIG.PCW_MIO_4_PULLUP {disabled} \ 603 | CONFIG.PCW_MIO_4_SLEW {slow} \ 604 | CONFIG.PCW_MIO_50_DIRECTION {inout} \ 605 | CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ 606 | CONFIG.PCW_MIO_50_PULLUP {enabled} \ 607 | CONFIG.PCW_MIO_50_SLEW {slow} \ 608 | CONFIG.PCW_MIO_51_DIRECTION {inout} \ 609 | CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ 610 | CONFIG.PCW_MIO_51_PULLUP {enabled} \ 611 | CONFIG.PCW_MIO_51_SLEW {slow} \ 612 | CONFIG.PCW_MIO_52_DIRECTION {out} \ 613 | CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ 614 | CONFIG.PCW_MIO_52_PULLUP {enabled} \ 615 | CONFIG.PCW_MIO_52_SLEW {slow} \ 616 | CONFIG.PCW_MIO_53_DIRECTION {inout} \ 617 | CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ 618 | CONFIG.PCW_MIO_53_PULLUP {enabled} \ 619 | CONFIG.PCW_MIO_53_SLEW {slow} \ 620 | CONFIG.PCW_MIO_5_DIRECTION {inout} \ 621 | CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ 622 | CONFIG.PCW_MIO_5_PULLUP {disabled} \ 623 | CONFIG.PCW_MIO_5_SLEW {slow} \ 624 | CONFIG.PCW_MIO_6_DIRECTION {out} \ 625 | CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ 626 | CONFIG.PCW_MIO_6_PULLUP {disabled} \ 627 | CONFIG.PCW_MIO_6_SLEW {slow} \ 628 | CONFIG.PCW_MIO_7_DIRECTION {out} \ 629 | CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ 630 | CONFIG.PCW_MIO_7_PULLUP {disabled} \ 631 | CONFIG.PCW_MIO_7_SLEW {slow} \ 632 | CONFIG.PCW_MIO_8_DIRECTION {out} \ 633 | CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ 634 | CONFIG.PCW_MIO_8_PULLUP {disabled} \ 635 | CONFIG.PCW_MIO_8_SLEW {slow} \ 636 | CONFIG.PCW_MIO_9_DIRECTION {out} \ 637 | CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ 638 | CONFIG.PCW_MIO_9_PULLUP {enabled} \ 639 | CONFIG.PCW_MIO_9_SLEW {slow} \ 640 | CONFIG.PCW_MIO_PRIMITIVE {54} \ 641 | CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ 642 | CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ 643 | CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ 644 | CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ 645 | CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ 646 | CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ 647 | CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ 648 | CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ 649 | CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ 650 | CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ 651 | CONFIG.PCW_NAND_CYCLES_T_AR {1} \ 652 | CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ 653 | CONFIG.PCW_NAND_CYCLES_T_RC {11} \ 654 | CONFIG.PCW_NAND_CYCLES_T_REA {1} \ 655 | CONFIG.PCW_NAND_CYCLES_T_RR {1} \ 656 | CONFIG.PCW_NAND_CYCLES_T_WC {11} \ 657 | CONFIG.PCW_NAND_CYCLES_T_WP {1} \ 658 | CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ 659 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 660 | CONFIG.PCW_NOR_CS0_T_CEOE {1} \ 661 | CONFIG.PCW_NOR_CS0_T_PC {1} \ 662 | CONFIG.PCW_NOR_CS0_T_RC {11} \ 663 | CONFIG.PCW_NOR_CS0_T_TR {1} \ 664 | CONFIG.PCW_NOR_CS0_T_WC {11} \ 665 | CONFIG.PCW_NOR_CS0_T_WP {1} \ 666 | CONFIG.PCW_NOR_CS0_WE_TIME {0} \ 667 | CONFIG.PCW_NOR_CS1_T_CEOE {1} \ 668 | CONFIG.PCW_NOR_CS1_T_PC {1} \ 669 | CONFIG.PCW_NOR_CS1_T_RC {11} \ 670 | CONFIG.PCW_NOR_CS1_T_TR {1} \ 671 | CONFIG.PCW_NOR_CS1_T_WC {11} \ 672 | CONFIG.PCW_NOR_CS1_T_WP {1} \ 673 | CONFIG.PCW_NOR_CS1_WE_TIME {0} \ 674 | CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ 675 | CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ 676 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 677 | CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ 678 | CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ 679 | CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ 680 | CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ 681 | CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ 682 | CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ 683 | CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ 684 | CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ 685 | CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ 686 | CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ 687 | CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ 688 | CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ 689 | CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ 690 | CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ 691 | CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ 692 | CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ 693 | CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ 694 | CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ 695 | CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ 696 | CONFIG.PCW_P2F_CAN0_INTR {0} \ 697 | CONFIG.PCW_P2F_CAN1_INTR {0} \ 698 | CONFIG.PCW_P2F_CTI_INTR {0} \ 699 | CONFIG.PCW_P2F_DMAC0_INTR {0} \ 700 | CONFIG.PCW_P2F_DMAC1_INTR {0} \ 701 | CONFIG.PCW_P2F_DMAC2_INTR {0} \ 702 | CONFIG.PCW_P2F_DMAC3_INTR {0} \ 703 | CONFIG.PCW_P2F_DMAC4_INTR {0} \ 704 | CONFIG.PCW_P2F_DMAC5_INTR {0} \ 705 | CONFIG.PCW_P2F_DMAC6_INTR {0} \ 706 | CONFIG.PCW_P2F_DMAC7_INTR {0} \ 707 | CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ 708 | CONFIG.PCW_P2F_ENET0_INTR {0} \ 709 | CONFIG.PCW_P2F_ENET1_INTR {0} \ 710 | CONFIG.PCW_P2F_GPIO_INTR {0} \ 711 | CONFIG.PCW_P2F_I2C0_INTR {0} \ 712 | CONFIG.PCW_P2F_I2C1_INTR {0} \ 713 | CONFIG.PCW_P2F_QSPI_INTR {0} \ 714 | CONFIG.PCW_P2F_SDIO0_INTR {0} \ 715 | CONFIG.PCW_P2F_SDIO1_INTR {0} \ 716 | CONFIG.PCW_P2F_SMC_INTR {0} \ 717 | CONFIG.PCW_P2F_SPI0_INTR {0} \ 718 | CONFIG.PCW_P2F_SPI1_INTR {0} \ 719 | CONFIG.PCW_P2F_UART0_INTR {0} \ 720 | CONFIG.PCW_P2F_UART1_INTR {0} \ 721 | CONFIG.PCW_P2F_USB0_INTR {0} \ 722 | CONFIG.PCW_P2F_USB1_INTR {0} \ 723 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.279} \ 724 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.260} \ 725 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ 726 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ 727 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.051} \ 728 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.006} \ 729 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 730 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 731 | CONFIG.PCW_PACKAGE_NAME {clg400} \ 732 | CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ 733 | CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ 734 | CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ 735 | CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ 736 | CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ 737 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 738 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ 739 | CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ 740 | CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ 741 | CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ 742 | CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ 743 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ 744 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ 745 | CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ 746 | CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ 747 | CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ 748 | CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ 749 | CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ 750 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ 751 | CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ 752 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ 753 | CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 754 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 755 | CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ 756 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ 757 | CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 758 | CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ 759 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 760 | CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ 761 | CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ 762 | CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ 763 | CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ 764 | CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ 765 | CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ 766 | CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ 767 | CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ 768 | CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ 769 | CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ 770 | CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ 771 | CONFIG.PCW_SMC_CYCLE_T0 {NA} \ 772 | CONFIG.PCW_SMC_CYCLE_T1 {NA} \ 773 | CONFIG.PCW_SMC_CYCLE_T2 {NA} \ 774 | CONFIG.PCW_SMC_CYCLE_T3 {NA} \ 775 | CONFIG.PCW_SMC_CYCLE_T4 {NA} \ 776 | CONFIG.PCW_SMC_CYCLE_T5 {NA} \ 777 | CONFIG.PCW_SMC_CYCLE_T6 {NA} \ 778 | CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ 779 | CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ 780 | CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ 781 | CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ 782 | CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ 783 | CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ 784 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 785 | CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ 786 | CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ 787 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 788 | CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ 789 | CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ 790 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 791 | CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ 792 | CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ 793 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 794 | CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ 795 | CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ 796 | CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ 797 | CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ 798 | CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ 799 | CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ 800 | CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ 801 | CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ 802 | CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ 803 | CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ 804 | CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ 805 | CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ 806 | CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ 807 | CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ 808 | CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ 809 | CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ 810 | CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ 811 | CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ 812 | CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ 813 | CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ 814 | CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ 815 | CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ 816 | CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ 817 | CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ 818 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 819 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ 820 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 821 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 822 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ 823 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 824 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 825 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ 826 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 827 | CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ 828 | CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ 829 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 830 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ 831 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 832 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 833 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ 834 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 835 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 836 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ 837 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 838 | CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ 839 | CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ 840 | CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ 841 | CONFIG.PCW_UART0_BAUD_RATE {115200} \ 842 | CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ 843 | CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ 844 | CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ 845 | CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ 846 | CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ 847 | CONFIG.PCW_UART1_BAUD_RATE {115200} \ 848 | CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ 849 | CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ 850 | CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ 851 | CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ 852 | CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ 853 | CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ 854 | CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ 855 | CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ 856 | CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ 857 | CONFIG.PCW_UIPARAM_DDR_AL {0} \ 858 | CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ 859 | CONFIG.PCW_UIPARAM_DDR_BL {8} \ 860 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.279} \ 861 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.260} \ 862 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ 863 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ 864 | CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ 865 | CONFIG.PCW_UIPARAM_DDR_CL {7} \ 866 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {27.95} \ 867 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ 868 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ 869 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {27.95} \ 870 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ 871 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ 872 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ 873 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ 874 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ 875 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ 876 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ 877 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ 878 | CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ 879 | CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ 880 | CONFIG.PCW_UIPARAM_DDR_CWL {6} \ 881 | CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ 882 | CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {32.14} \ 883 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ 884 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ 885 | CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {31.12} \ 886 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ 887 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ 888 | CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ 889 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ 890 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ 891 | CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ 892 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ 893 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ 894 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.051} \ 895 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.006} \ 896 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 897 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 898 | CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {32.2} \ 899 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ 900 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ 901 | CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {31.08} \ 902 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ 903 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ 904 | CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ 905 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ 906 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ 907 | CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ 908 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ 909 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ 910 | CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ 911 | CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ 912 | CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ 913 | CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ 914 | CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ 915 | CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ 916 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ 917 | CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ 918 | CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ 919 | CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 920 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ 921 | CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 922 | CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ 923 | CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ 924 | CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ 925 | CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ 926 | CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ 927 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ 928 | CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ 929 | CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ 930 | CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ 931 | CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ 932 | CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ 933 | CONFIG.PCW_USB0_RESET_ENABLE {1} \ 934 | CONFIG.PCW_USB0_RESET_IO {MIO 46} \ 935 | CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ 936 | CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ 937 | CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ 938 | CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ 939 | CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ 940 | CONFIG.PCW_USB1_RESET_ENABLE {0} \ 941 | CONFIG.PCW_USB_RESET_ENABLE {1} \ 942 | CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ 943 | CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ 944 | CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ 945 | CONFIG.PCW_USE_AXI_NONSECURE {0} \ 946 | CONFIG.PCW_USE_CORESIGHT {0} \ 947 | CONFIG.PCW_USE_CROSS_TRIGGER {0} \ 948 | CONFIG.PCW_USE_CR_FABRIC {1} \ 949 | CONFIG.PCW_USE_DDR_BYPASS {0} \ 950 | CONFIG.PCW_USE_DEBUG {0} \ 951 | CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ 952 | CONFIG.PCW_USE_DMA0 {0} \ 953 | CONFIG.PCW_USE_DMA1 {0} \ 954 | CONFIG.PCW_USE_DMA2 {0} \ 955 | CONFIG.PCW_USE_DMA3 {0} \ 956 | CONFIG.PCW_USE_EXPANDED_IOP {0} \ 957 | CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ 958 | CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ 959 | CONFIG.PCW_USE_HIGH_OCM {0} \ 960 | CONFIG.PCW_USE_M_AXI_GP0 {1} \ 961 | CONFIG.PCW_USE_M_AXI_GP1 {0} \ 962 | CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ 963 | CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ 964 | CONFIG.PCW_USE_S_AXI_ACP {0} \ 965 | CONFIG.PCW_USE_S_AXI_GP0 {0} \ 966 | CONFIG.PCW_USE_S_AXI_GP1 {0} \ 967 | CONFIG.PCW_USE_S_AXI_HP0 {0} \ 968 | CONFIG.PCW_USE_S_AXI_HP1 {0} \ 969 | CONFIG.PCW_USE_S_AXI_HP2 {0} \ 970 | CONFIG.PCW_USE_S_AXI_HP3 {0} \ 971 | CONFIG.PCW_USE_TRACE {0} \ 972 | CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ 973 | CONFIG.PCW_VALUE_SILVERSION {3} \ 974 | CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ 975 | CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ 976 | CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ 977 | ] $processing_system7_0 978 | 979 | # Create instance: ps7_0_axi_periph, and set properties 980 | set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] 981 | set_property -dict [ list \ 982 | CONFIG.NUM_MI {1} \ 983 | ] $ps7_0_axi_periph 984 | 985 | # Create instance: rst_ps7_0_100M, and set properties 986 | set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] 987 | 988 | # Create interface connections 989 | connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] 990 | connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] 991 | connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] 992 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins canonize_tree_0/s_axi_AXILiteS] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] 993 | 994 | # Create port connections 995 | connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins canonize_tree_0/ap_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] 996 | connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] 997 | connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] 998 | connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins canonize_tree_0/ap_rst_n] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] 999 | 1000 | # Create address segments 1001 | create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs canonize_tree_0/s_axi_AXILiteS/Reg] SEG_canonize_tree_0_Reg 1002 | 1003 | 1004 | # Restore current instance 1005 | current_bd_instance $oldCurInst 1006 | 1007 | save_bd_design 1008 | } 1009 | # End of create_root_design() 1010 | 1011 | 1012 | ################################################################## 1013 | # MAIN FLOW 1014 | ################################################################## 1015 | 1016 | create_root_design "" 1017 | 1018 | 1019 | -------------------------------------------------------------------------------- /tests/canonize-tree-test/notebook/canonize-tree-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": [ 11 | "\n", 12 | "require(['notebook/js/codecell'], function(codecell) {\n", 13 | " codecell.CodeCell.options_default.highlight_modes[\n", 14 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 15 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 16 | " Jupyter.notebook.get_cells().map(function(cell){\n", 17 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 18 | " });\n", 19 | "});\n" 20 | ] 21 | }, 22 | "metadata": {}, 23 | "output_type": "display_data" 24 | }, 25 | { 26 | "name": "stdout", 27 | "output_type": "stream", 28 | "text": [ 29 | "S : f L : 4\n", 30 | "S : b L : 4\n", 31 | "S : c L : 3\n", 32 | "S : a L : 2\n", 33 | "S : d L : 2\n", 34 | "S : e L : 2\n" 35 | ] 36 | } 37 | ], 38 | "source": [ 39 | "# AXILiteS\n", 40 | "# 0x000 : Control signals\n", 41 | "# bit 0 - ap_start (Read/Write/COH)\n", 42 | "# bit 1 - ap_done (Read/COR)\n", 43 | "# bit 2 - ap_idle (Read)\n", 44 | "# bit 3 - ap_ready (Read)\n", 45 | "# bit 7 - auto_restart (Read/Write)\n", 46 | "# others - reserved\n", 47 | "# 0x004 : Global Interrupt Enable Register\n", 48 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 49 | "# others - reserved\n", 50 | "# 0x008 : IP Interrupt Enable Register (Read/Write)\n", 51 | "# bit 0 - Channel 0 (ap_done)\n", 52 | "# bit 1 - Channel 1 (ap_ready)\n", 53 | "# others - reserved\n", 54 | "# 0x00c : IP Interrupt Status Register (Read/TOW)\n", 55 | "# bit 0 - Channel 0 (ap_done)\n", 56 | "# bit 1 - Channel 1 (ap_ready)\n", 57 | "# others - reserved\n", 58 | "# 0xc00 : Data signal of num_symbols_V\n", 59 | "# bit 31~0 - num_symbols_V[31:0] (Read/Write)\n", 60 | "# 0xc04 : reserved\n", 61 | "# 0x400 ~\n", 62 | "# 0x7ff : Memory 'sorted_value_V' (256 * 32b)\n", 63 | "# Word n : bit [31:0] - sorted_value_V[n]\n", 64 | "# 0x800 ~\n", 65 | "# 0xbff : Memory 'sorted_frequency_V' (256 * 32b)\n", 66 | "# Word n : bit [31:0] - sorted_frequency_V[n]\n", 67 | "# 0xd00 ~\n", 68 | "# 0xdff : Memory 'codeword_length_histogram_V' (64 * 32b)\n", 69 | "# Word n : bit [31:0] - codeword_length_histogram_V[n]\n", 70 | "# 0xe00 ~\n", 71 | "# 0xeff : Memory 'symbol_bits_V' (256 * 5b)\n", 72 | "# Word n : bit [ 4: 0] - symbol_bits_V[4n]\n", 73 | "# bit [12: 8] - symbol_bits_V[4n+1]\n", 74 | "# bit [20:16] - symbol_bits_V[4n+2]\n", 75 | "# bit [28:24] - symbol_bits_V[4n+3]\n", 76 | "# others - reserved\n", 77 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 78 | "\n", 79 | "from pynq import Overlay\n", 80 | "\n", 81 | "overlay = Overlay(\"../bitstream/canonize-tree-test.bit\")\n", 82 | "overlay.download()\n", 83 | "\n", 84 | "canonize_tree = overlay.canonize_tree_0\n", 85 | "\n", 86 | "# sorted table\n", 87 | "sorted_table = [\n", 88 | " { 'symbol': 'f', 'freq': 1 },\n", 89 | " { 'symbol': 'b', 'freq': 1 },\n", 90 | " { 'symbol': 'c', 'freq': 2 },\n", 91 | " { 'symbol': 'a', 'freq': 3 },\n", 92 | " { 'symbol': 'd', 'freq': 5 },\n", 93 | " { 'symbol': 'e', 'freq': 5 }\n", 94 | "]\n", 95 | "\n", 96 | "bit_len = [ 0, 0, 3, 1, 2 ]\n", 97 | "\n", 98 | "# write symbol number\n", 99 | "canonize_tree.write(0xc00, 6)\n", 100 | "\n", 101 | "for idx, symbol in enumerate(sorted_table):\n", 102 | " # write symbol\n", 103 | " canonize_tree.write(0x400 + 4*idx, ord(symbol['symbol']))\n", 104 | " # write frequency\n", 105 | " canonize_tree.write(0x800 + 4*idx, symbol['freq'])\n", 106 | "\n", 107 | "for idx, bt in enumerate(bit_len):\n", 108 | " # write bit length\n", 109 | " canonize_tree.write(0xd00 + 4*idx, bt)\n", 110 | " \n", 111 | "# start\n", 112 | "canonize_tree.write(0x000, 1)\n", 113 | "\n", 114 | "from time import sleep\n", 115 | "\n", 116 | "sleep(1)\n", 117 | "\n", 118 | "# 0x1f = 00011111b\n", 119 | "word_mask = 0x1f\n", 120 | "\n", 121 | "# search memory for coding length\n", 122 | "for idx, symbol in enumerate(sorted_table):\n", 123 | " word_addr = int(ord(symbol['symbol']) / 4)\n", 124 | " bit_len_word = canonize_tree.read(0xe00 + 4*word_addr)\n", 125 | " seg_pos = ord(symbol['symbol']) % 4\n", 126 | " bit_len = (bit_len_word >> (seg_pos*8)) & word_mask\n", 127 | " print('S : ' + symbol['symbol'] + ' L : ' + str(bit_len))" 128 | ] 129 | } 130 | ], 131 | "metadata": { 132 | "kernelspec": { 133 | "display_name": "Python 3", 134 | "language": "python", 135 | "name": "python3" 136 | }, 137 | "language_info": { 138 | "codemirror_mode": { 139 | "name": "ipython", 140 | "version": 3 141 | }, 142 | "file_extension": ".py", 143 | "mimetype": "text/x-python", 144 | "name": "python", 145 | "nbconvert_exporter": "python", 146 | "pygments_lexer": "ipython3", 147 | "version": "3.6.0" 148 | } 149 | }, 150 | "nbformat": 4, 151 | "nbformat_minor": 2 152 | } 153 | -------------------------------------------------------------------------------- /tests/compute-bit-length-test/bitstream/compute-bit-length-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/compute-bit-length-test/bitstream/compute-bit-length-test.bit -------------------------------------------------------------------------------- /tests/compute-bit-length-test/notebook/compute-bit-length-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": [ 11 | "\n", 12 | "require(['notebook/js/codecell'], function(codecell) {\n", 13 | " codecell.CodeCell.options_default.highlight_modes[\n", 14 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 15 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 16 | " Jupyter.notebook.get_cells().map(function(cell){\n", 17 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 18 | " });\n", 19 | "});\n" 20 | ] 21 | }, 22 | "metadata": {}, 23 | "output_type": "display_data" 24 | }, 25 | { 26 | "name": "stdout", 27 | "output_type": "stream", 28 | "text": [ 29 | "L : 2 N : 3\n", 30 | "L : 3 N : 1\n", 31 | "L : 4 N : 2\n" 32 | ] 33 | } 34 | ], 35 | "source": [ 36 | "# AXILiteS\n", 37 | "# 0x0000 : Control signals\n", 38 | "# bit 0 - ap_start (Read/Write/COH)\n", 39 | "# bit 1 - ap_done (Read/COR)\n", 40 | "# bit 2 - ap_idle (Read)\n", 41 | "# bit 3 - ap_ready (Read)\n", 42 | "# bit 7 - auto_restart (Read/Write)\n", 43 | "# others - reserved\n", 44 | "# 0x0004 : Global Interrupt Enable Register\n", 45 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 46 | "# others - reserved\n", 47 | "# 0x0008 : IP Interrupt Enable Register (Read/Write)\n", 48 | "# bit 0 - Channel 0 (ap_done)\n", 49 | "# bit 1 - Channel 1 (ap_ready)\n", 50 | "# others - reserved\n", 51 | "# 0x000c : IP Interrupt Status Register (Read/TOW)\n", 52 | "# bit 0 - Channel 0 (ap_done)\n", 53 | "# bit 1 - Channel 1 (ap_ready)\n", 54 | "# others - reserved\n", 55 | "# 0x1000 : Data signal of num_symbols\n", 56 | "# bit 31~0 - num_symbols[31:0] (Read/Write)\n", 57 | "# 0x1004 : reserved\n", 58 | "# 0x0400 ~\n", 59 | "# 0x07ff : Memory 'parent_V' (255 * 32b)\n", 60 | "# Word n : bit [31:0] - parent_V[n]\n", 61 | "# 0x0800 ~\n", 62 | "# 0x0bff : Memory 'left_V' (255 * 32b)\n", 63 | "# Word n : bit [31:0] - left_V[n]\n", 64 | "# 0x0c00 ~\n", 65 | "# 0x0fff : Memory 'right_V' (255 * 32b)\n", 66 | "# Word n : bit [31:0] - right_V[n]\n", 67 | "# 0x1100 ~\n", 68 | "# 0x11ff : Memory 'length_histogram_V' (64 * 32b)\n", 69 | "# Word n : bit [31:0] - length_histogram_V[n]\n", 70 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 71 | "\n", 72 | "from pynq import Overlay\n", 73 | "\n", 74 | "overlay = Overlay(\"../bitstream/compute-bit-length-test.bit\")\n", 75 | "overlay.download()\n", 76 | "\n", 77 | "compute_bit_len = overlay.compute_bit_length_0\n", 78 | "\n", 79 | "# set symbol numbers\n", 80 | "compute_bit_len.write(0x1000, 6)\n", 81 | "\n", 82 | "# given tree\n", 83 | "# pos : 0 parent : 1\n", 84 | "# lchild : 102\n", 85 | "# rchild : 98\n", 86 | "# pos : 1 parent : 2\n", 87 | "# lchild : 99\n", 88 | "# rchild : 4294967295\n", 89 | "# pos : 2 parent : 4\n", 90 | "# lchild : 97\n", 91 | "# rchild : 4294967295\n", 92 | "# pos : 3 parent : 4\n", 93 | "# lchild : 100\n", 94 | "# rchild : 101\n", 95 | "# pos : 4 parent : 0\n", 96 | "# lchild : 4294967295\n", 97 | "# rchild : 4294967295\n", 98 | "\n", 99 | "tree_nodes = [\n", 100 | " { 'p': 1, 'l': 102, 'r': 98 },\n", 101 | " { 'p': 2, 'l': 99, 'r': -1 },\n", 102 | " { 'p': 4, 'l': 97, 'r': -1 },\n", 103 | " { 'p': 4, 'l': 100, 'r': 101 },\n", 104 | " { 'p': 0, 'l': -1, 'r': -1 },\n", 105 | "]\n", 106 | "\n", 107 | "for idx, node in enumerate(tree_nodes):\n", 108 | " # write parent\n", 109 | " compute_bit_len.write(0x0400 + 4*idx, node['p'])\n", 110 | " # write left & right child\n", 111 | " compute_bit_len.write(0x0800 + 4*idx, node['l'])\n", 112 | " compute_bit_len.write(0x0c00 + 4*idx, node['r'])\n", 113 | "\n", 114 | "# start\n", 115 | "compute_bit_len.write(0x0000, 1)\n", 116 | "\n", 117 | "from time import sleep\n", 118 | "\n", 119 | "sleep(1)\n", 120 | "\n", 121 | "for i in range(10):\n", 122 | " bit_len = compute_bit_len.read(0x1100 + 4*i)\n", 123 | " if (not bit_len == 0):\n", 124 | " print('L : ' + str(i) + ' N : ' + str(bit_len))" 125 | ] 126 | }, 127 | { 128 | "cell_type": "code", 129 | "execution_count": null, 130 | "metadata": {}, 131 | "outputs": [], 132 | "source": [] 133 | } 134 | ], 135 | "metadata": { 136 | "kernelspec": { 137 | "display_name": "Python 3", 138 | "language": "python", 139 | "name": "python3" 140 | }, 141 | "language_info": { 142 | "codemirror_mode": { 143 | "name": "ipython", 144 | "version": 3 145 | }, 146 | "file_extension": ".py", 147 | "mimetype": "text/x-python", 148 | "name": "python", 149 | "nbconvert_exporter": "python", 150 | "pygments_lexer": "ipython3", 151 | "version": "3.6.0" 152 | } 153 | }, 154 | "nbformat": 4, 155 | "nbformat_minor": 2 156 | } 157 | -------------------------------------------------------------------------------- /tests/create-code-word-test/bitstream/create-code-word-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/create-code-word-test/bitstream/create-code-word-test.bit -------------------------------------------------------------------------------- /tests/create-code-word-test/notebook/create-code-word-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": { 7 | "scrolled": false 8 | }, 9 | "outputs": [ 10 | { 11 | "data": { 12 | "application/javascript": [ 13 | "\n", 14 | "require(['notebook/js/codecell'], function(codecell) {\n", 15 | " codecell.CodeCell.options_default.highlight_modes[\n", 16 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 17 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 18 | " Jupyter.notebook.get_cells().map(function(cell){\n", 19 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 20 | " });\n", 21 | "});\n" 22 | ] 23 | }, 24 | "metadata": {}, 25 | "output_type": "display_data" 26 | }, 27 | { 28 | "name": "stdout", 29 | "output_type": "stream", 30 | "text": [ 31 | "symbol : a, code word : 00000000000000000000000000000010\n", 32 | "symbol : b, code word : 00000000000000000000000011100100\n", 33 | "symbol : c, code word : 00000000000000000000000001100011\n", 34 | "symbol : d, code word : 00000000000000000000000001000010\n", 35 | "symbol : e, code word : 00000000000000000000000000100010\n", 36 | "symbol : f, code word : 00000000000000000000000111100100\n" 37 | ] 38 | } 39 | ], 40 | "source": [ 41 | "# AXILiteS\n", 42 | "# 0x000 : Control signals\n", 43 | "# bit 0 - ap_start (Read/Write/COH)\n", 44 | "# bit 1 - ap_done (Read/COR)\n", 45 | "# bit 2 - ap_idle (Read)\n", 46 | "# bit 3 - ap_ready (Read)\n", 47 | "# bit 7 - auto_restart (Read/Write)\n", 48 | "# others - reserved\n", 49 | "# 0x004 : Global Interrupt Enable Register\n", 50 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 51 | "# others - reserved\n", 52 | "# 0x008 : IP Interrupt Enable Register (Read/Write)\n", 53 | "# bit 0 - Channel 0 (ap_done)\n", 54 | "# bit 1 - Channel 1 (ap_ready)\n", 55 | "# others - reserved\n", 56 | "# 0x00c : IP Interrupt Status Register (Read/TOW)\n", 57 | "# bit 0 - Channel 0 (ap_done)\n", 58 | "# bit 1 - Channel 1 (ap_ready)\n", 59 | "# others - reserved\n", 60 | "# 0x100 ~\n", 61 | "# 0x1ff : Memory 'symbol_bits_V' (256 * 5b)\n", 62 | "# Word n : bit [ 4: 0] - symbol_bits_V[4n]\n", 63 | "# bit [12: 8] - symbol_bits_V[4n+1]\n", 64 | "# bit [20:16] - symbol_bits_V[4n+2]\n", 65 | "# bit [28:24] - symbol_bits_V[4n+3]\n", 66 | "# others - reserved\n", 67 | "# 0x200 ~\n", 68 | "# 0x2ff : Memory 'codeword_length_histogram_V' (64 * 32b)\n", 69 | "# Word n : bit [31:0] - codeword_length_histogram_V[n]\n", 70 | "# 0x400 ~\n", 71 | "# 0x7ff : Memory 'encoding_V' (256 * 32b)\n", 72 | "# Word n : bit [31:0] - encoding_V[n]\n", 73 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 74 | "\n", 75 | "from pynq import Overlay\n", 76 | "\n", 77 | "overlay = Overlay(\"../bitstream/create-code-word-test.bit\")\n", 78 | "overlay.download()\n", 79 | "\n", 80 | "create_codeword = overlay.create_codeword_0\n", 81 | "\n", 82 | "# write symbol bits\n", 83 | "create_codeword.write(0x100 + 4*24, 50594304)\n", 84 | "create_codeword.write(0x100 + 4*25, 262658 )\n", 85 | "\n", 86 | "# create code word len histogram\n", 87 | "# code_word_len_histo = [\n", 88 | "# { 'symbol': 'a', 'len': 2 },\n", 89 | "# { 'symbol': 'd', 'len': 2 },\n", 90 | "# { 'symbol': 'e', 'len': 2 },\n", 91 | "# { 'symbol': 'c', 'len': 3 },\n", 92 | "# { 'symbol': 'b', 'len': 4 },\n", 93 | "# { 'symbol': 'f', 'len': 4 },\n", 94 | "# ]\n", 95 | "\n", 96 | "symbols = [ 'a', 'b', 'c', 'd', 'e', 'f' ]\n", 97 | "code_word_len_histo = [ 0, 0, 3, 1, 2 ]\n", 98 | "\n", 99 | "# code_word_len_histo = [\n", 100 | "# { 'symbol': 'a', 'len': 2 },\n", 101 | "# { 'symbol': 'b', 'len': 4 },\n", 102 | "# { 'symbol': 'c', 'len': 3 },\n", 103 | "# { 'symbol': 'd', 'len': 2 },\n", 104 | "# { 'symbol': 'e', 'len': 2 },\n", 105 | "# { 'symbol': 'f', 'len': 4 },\n", 106 | "# ]\n", 107 | "\n", 108 | "for idx, num in enumerate(code_word_len_histo):\n", 109 | " create_codeword.write(0x200 + 4*idx, num)\n", 110 | " \n", 111 | "# start\n", 112 | "create_codeword.write(0x000, 1)\n", 113 | "\n", 114 | "from time import sleep\n", 115 | "\n", 116 | "sleep(1)\n", 117 | "\n", 118 | "get_bin = lambda x, n: format(x, 'b').zfill(n)\n", 119 | "\n", 120 | "for sym in symbols:\n", 121 | " encoding = create_codeword.read(0x400 + 4*ord(sym))\n", 122 | " print('symbol : ' + sym + ', code word : ' + get_bin(encoding, 32))" 123 | ] 124 | } 125 | ], 126 | "metadata": { 127 | "kernelspec": { 128 | "display_name": "Python 3", 129 | "language": "python", 130 | "name": "python3" 131 | }, 132 | "language_info": { 133 | "codemirror_mode": { 134 | "name": "ipython", 135 | "version": 3 136 | }, 137 | "file_extension": ".py", 138 | "mimetype": "text/x-python", 139 | "name": "python", 140 | "nbconvert_exporter": "python", 141 | "pygments_lexer": "ipython3", 142 | "version": "3.6.0" 143 | } 144 | }, 145 | "nbformat": 4, 146 | "nbformat_minor": 2 147 | } 148 | -------------------------------------------------------------------------------- /tests/create-tree-core-test/bitstream/create-tree-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/create-tree-core-test/bitstream/create-tree-test.bit -------------------------------------------------------------------------------- /tests/create-tree-core-test/bitstream/create-tree-test.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: axi_huffman_encoder_bd 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | namespace eval _tcl { 11 | proc get_script_folder {} { 12 | set script_path [file normalize [info script]] 13 | set script_folder [file dirname $script_path] 14 | return $script_folder 15 | } 16 | } 17 | variable script_folder 18 | set script_folder [_tcl::get_script_folder] 19 | 20 | ################################################################ 21 | # Check if script is running in correct Vivado version. 22 | ################################################################ 23 | set scripts_vivado_version 2017.4 24 | set current_vivado_version [version -short] 25 | 26 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 27 | puts "" 28 | catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 29 | 30 | return 1 31 | } 32 | 33 | ################################################################ 34 | # START 35 | ################################################################ 36 | 37 | # To test this script, run the following commands from Vivado Tcl console: 38 | # source axi_huffman_encoder_bd_script.tcl 39 | 40 | # If there is no project opened, this script will create a 41 | # project, but make sure you do not have an existing project 42 | # <./myproj/project_1.xpr> in the current working folder. 43 | 44 | set list_projs [get_projects -quiet] 45 | if { $list_projs eq "" } { 46 | create_project project_1 myproj -part xc7z020clg400-1 47 | set_property BOARD_PART tul.com.tw:pynq-z2:part0:1.0 [current_project] 48 | } 49 | 50 | 51 | # CHANGE DESIGN NAME HERE 52 | variable design_name 53 | set design_name axi_huffman_encoder_bd 54 | 55 | # If you do not already have an existing IP Integrator design open, 56 | # you can create a design using the following command: 57 | # create_bd_design $design_name 58 | 59 | # Creating design if needed 60 | set errMsg "" 61 | set nRet 0 62 | 63 | set cur_design [current_bd_design -quiet] 64 | set list_cells [get_bd_cells -quiet] 65 | 66 | if { ${design_name} eq "" } { 67 | # USE CASES: 68 | # 1) Design_name not set 69 | 70 | set errMsg "Please set the variable to a non-empty value." 71 | set nRet 1 72 | 73 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 74 | # USE CASES: 75 | # 2): Current design opened AND is empty AND names same. 76 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 77 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 78 | 79 | if { $cur_design ne $design_name } { 80 | common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." 81 | set design_name [get_property NAME $cur_design] 82 | } 83 | common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." 84 | 85 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 86 | # USE CASES: 87 | # 5) Current design opened AND has components AND same names. 88 | 89 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 90 | set nRet 1 91 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 92 | # USE CASES: 93 | # 6) Current opened design, has components, but diff names, design_name exists in project. 94 | # 7) No opened design, design_name exists in project. 95 | 96 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 97 | set nRet 2 98 | 99 | } else { 100 | # USE CASES: 101 | # 8) No opened design, design_name not in project. 102 | # 9) Current opened design, has components, but diff names, design_name not in project. 103 | 104 | common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." 105 | 106 | create_bd_design $design_name 107 | 108 | common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." 109 | current_bd_design $design_name 110 | 111 | } 112 | 113 | common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." 114 | 115 | if { $nRet != 0 } { 116 | catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} 117 | return $nRet 118 | } 119 | 120 | set bCheckIPsPassed 1 121 | ################################################################## 122 | # CHECK IPs 123 | ################################################################## 124 | set bCheckIPs 1 125 | if { $bCheckIPs == 1 } { 126 | set list_check_ips "\ 127 | xilinx.com:hls:create_tree:1.0\ 128 | xilinx.com:ip:processing_system7:5.5\ 129 | xilinx.com:ip:proc_sys_reset:5.0\ 130 | " 131 | 132 | set list_ips_missing "" 133 | common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 134 | 135 | foreach ip_vlnv $list_check_ips { 136 | set ip_obj [get_ipdefs -all $ip_vlnv] 137 | if { $ip_obj eq "" } { 138 | lappend list_ips_missing $ip_vlnv 139 | } 140 | } 141 | 142 | if { $list_ips_missing ne "" } { 143 | catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 144 | set bCheckIPsPassed 0 145 | } 146 | 147 | } 148 | 149 | if { $bCheckIPsPassed != 1 } { 150 | common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." 151 | return 3 152 | } 153 | 154 | ################################################################## 155 | # DESIGN PROCs 156 | ################################################################## 157 | 158 | 159 | 160 | # Procedure to create entire design; Provide argument to make 161 | # procedure reusable. If parentCell is "", will use root. 162 | proc create_root_design { parentCell } { 163 | 164 | variable script_folder 165 | variable design_name 166 | 167 | if { $parentCell eq "" } { 168 | set parentCell [get_bd_cells /] 169 | } 170 | 171 | # Get object for parentCell 172 | set parentObj [get_bd_cells $parentCell] 173 | if { $parentObj == "" } { 174 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 175 | return 176 | } 177 | 178 | # Make sure parentObj is hier blk 179 | set parentType [get_property TYPE $parentObj] 180 | if { $parentType ne "hier" } { 181 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 182 | return 183 | } 184 | 185 | # Save current instance; Restore later 186 | set oldCurInst [current_bd_instance .] 187 | 188 | # Set parent object as current 189 | current_bd_instance $parentObj 190 | 191 | 192 | # Create interface ports 193 | set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] 194 | set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] 195 | 196 | # Create ports 197 | 198 | # Create instance: create_tree_0, and set properties 199 | set create_tree_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:create_tree:1.0 create_tree_0 ] 200 | 201 | set_property -dict [ list \ 202 | CONFIG.NUM_READ_OUTSTANDING {1} \ 203 | CONFIG.NUM_WRITE_OUTSTANDING {1} \ 204 | ] [get_bd_intf_pins /create_tree_0/s_axi_AXILiteS] 205 | 206 | # Create instance: processing_system7_0, and set properties 207 | set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] 208 | set_property -dict [ list \ 209 | CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ 210 | CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ 211 | CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ 212 | CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ 213 | CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ 214 | CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ 215 | CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ 216 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 217 | CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ 218 | CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ 219 | CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ 220 | CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ 221 | CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ 222 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ 223 | CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ 224 | CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ 225 | CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ 226 | CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ 227 | CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 228 | CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 229 | CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 230 | CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 231 | CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 232 | CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 233 | CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ 234 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ 235 | CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ 236 | CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ 237 | CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ 238 | CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ 239 | CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ 240 | CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ 241 | CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ 242 | CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ 243 | CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ 244 | CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ 245 | CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ 246 | CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ 247 | CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ 248 | CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ 249 | CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ 250 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ 251 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ 252 | CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ 253 | CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ 254 | CONFIG.PCW_CLK0_FREQ {100000000} \ 255 | CONFIG.PCW_CLK1_FREQ {10000000} \ 256 | CONFIG.PCW_CLK2_FREQ {10000000} \ 257 | CONFIG.PCW_CLK3_FREQ {10000000} \ 258 | CONFIG.PCW_CORE0_FIQ_INTR {0} \ 259 | CONFIG.PCW_CORE0_IRQ_INTR {0} \ 260 | CONFIG.PCW_CORE1_FIQ_INTR {0} \ 261 | CONFIG.PCW_CORE1_IRQ_INTR {0} \ 262 | CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ 263 | CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ 264 | CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ 265 | CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ 266 | CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ 267 | CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ 268 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ 269 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ 270 | CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ 271 | CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ 272 | CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ 273 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 274 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 275 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 276 | CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ 277 | CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ 278 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 279 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 280 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 281 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 282 | CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ 283 | CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ 284 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 285 | CONFIG.PCW_DM_WIDTH {4} \ 286 | CONFIG.PCW_DQS_WIDTH {4} \ 287 | CONFIG.PCW_DQ_WIDTH {32} \ 288 | CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ 289 | CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 290 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ 291 | CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 292 | CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ 293 | CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ 294 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ 295 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ 296 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ 297 | CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ 298 | CONFIG.PCW_ENET0_RESET_ENABLE {1} \ 299 | CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ 300 | CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ 301 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 302 | CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ 303 | CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ 304 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ 305 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ 306 | CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ 307 | CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ 308 | CONFIG.PCW_ENET1_RESET_ENABLE {0} \ 309 | CONFIG.PCW_ENET_RESET_ENABLE {1} \ 310 | CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ 311 | CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ 312 | CONFIG.PCW_EN_4K_TIMER {0} \ 313 | CONFIG.PCW_EN_CAN0 {0} \ 314 | CONFIG.PCW_EN_CAN1 {0} \ 315 | CONFIG.PCW_EN_CLK0_PORT {1} \ 316 | CONFIG.PCW_EN_CLK1_PORT {0} \ 317 | CONFIG.PCW_EN_CLK2_PORT {0} \ 318 | CONFIG.PCW_EN_CLK3_PORT {0} \ 319 | CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ 320 | CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ 321 | CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ 322 | CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ 323 | CONFIG.PCW_EN_DDR {1} \ 324 | CONFIG.PCW_EN_EMIO_CAN0 {0} \ 325 | CONFIG.PCW_EN_EMIO_CAN1 {0} \ 326 | CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ 327 | CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ 328 | CONFIG.PCW_EN_EMIO_ENET0 {0} \ 329 | CONFIG.PCW_EN_EMIO_ENET1 {0} \ 330 | CONFIG.PCW_EN_EMIO_GPIO {0} \ 331 | CONFIG.PCW_EN_EMIO_I2C0 {0} \ 332 | CONFIG.PCW_EN_EMIO_I2C1 {0} \ 333 | CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ 334 | CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ 335 | CONFIG.PCW_EN_EMIO_PJTAG {0} \ 336 | CONFIG.PCW_EN_EMIO_SDIO0 {0} \ 337 | CONFIG.PCW_EN_EMIO_SDIO1 {0} \ 338 | CONFIG.PCW_EN_EMIO_SPI0 {0} \ 339 | CONFIG.PCW_EN_EMIO_SPI1 {0} \ 340 | CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ 341 | CONFIG.PCW_EN_EMIO_TRACE {0} \ 342 | CONFIG.PCW_EN_EMIO_TTC0 {0} \ 343 | CONFIG.PCW_EN_EMIO_TTC1 {0} \ 344 | CONFIG.PCW_EN_EMIO_UART0 {0} \ 345 | CONFIG.PCW_EN_EMIO_UART1 {0} \ 346 | CONFIG.PCW_EN_EMIO_WDT {0} \ 347 | CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ 348 | CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ 349 | CONFIG.PCW_EN_ENET0 {1} \ 350 | CONFIG.PCW_EN_ENET1 {0} \ 351 | CONFIG.PCW_EN_GPIO {1} \ 352 | CONFIG.PCW_EN_I2C0 {0} \ 353 | CONFIG.PCW_EN_I2C1 {0} \ 354 | CONFIG.PCW_EN_MODEM_UART0 {0} \ 355 | CONFIG.PCW_EN_MODEM_UART1 {0} \ 356 | CONFIG.PCW_EN_PJTAG {0} \ 357 | CONFIG.PCW_EN_PTP_ENET0 {0} \ 358 | CONFIG.PCW_EN_PTP_ENET1 {0} \ 359 | CONFIG.PCW_EN_QSPI {1} \ 360 | CONFIG.PCW_EN_RST0_PORT {1} \ 361 | CONFIG.PCW_EN_RST1_PORT {0} \ 362 | CONFIG.PCW_EN_RST2_PORT {0} \ 363 | CONFIG.PCW_EN_RST3_PORT {0} \ 364 | CONFIG.PCW_EN_SDIO0 {1} \ 365 | CONFIG.PCW_EN_SDIO1 {0} \ 366 | CONFIG.PCW_EN_SMC {0} \ 367 | CONFIG.PCW_EN_SPI0 {0} \ 368 | CONFIG.PCW_EN_SPI1 {0} \ 369 | CONFIG.PCW_EN_TRACE {0} \ 370 | CONFIG.PCW_EN_TTC0 {0} \ 371 | CONFIG.PCW_EN_TTC1 {0} \ 372 | CONFIG.PCW_EN_UART0 {1} \ 373 | CONFIG.PCW_EN_UART1 {0} \ 374 | CONFIG.PCW_EN_USB0 {1} \ 375 | CONFIG.PCW_EN_USB1 {0} \ 376 | CONFIG.PCW_EN_WDT {0} \ 377 | CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ 378 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ 379 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ 380 | CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ 381 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ 382 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ 383 | CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ 384 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ 385 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ 386 | CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ 387 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ 388 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ 389 | CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ 390 | CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ 391 | CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ 392 | CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ 393 | CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ 394 | CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ 395 | CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ 396 | CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ 397 | CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ 398 | CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ 399 | CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ 400 | CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ 401 | CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ 402 | CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ 403 | CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ 404 | CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ 405 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ 406 | CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 407 | CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ 408 | CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ 409 | CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ 410 | CONFIG.PCW_I2C0_RESET_ENABLE {0} \ 411 | CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ 412 | CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ 413 | CONFIG.PCW_I2C1_RESET_ENABLE {0} \ 414 | CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ 415 | CONFIG.PCW_I2C_RESET_ENABLE {1} \ 416 | CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ 417 | CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ 418 | CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ 419 | CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ 420 | CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ 421 | CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ 422 | CONFIG.PCW_IRQ_F2P_INTR {0} \ 423 | CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ 424 | CONFIG.PCW_MIO_0_DIRECTION {inout} \ 425 | CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ 426 | CONFIG.PCW_MIO_0_PULLUP {enabled} \ 427 | CONFIG.PCW_MIO_0_SLEW {slow} \ 428 | CONFIG.PCW_MIO_10_DIRECTION {inout} \ 429 | CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ 430 | CONFIG.PCW_MIO_10_PULLUP {enabled} \ 431 | CONFIG.PCW_MIO_10_SLEW {slow} \ 432 | CONFIG.PCW_MIO_11_DIRECTION {inout} \ 433 | CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ 434 | CONFIG.PCW_MIO_11_PULLUP {enabled} \ 435 | CONFIG.PCW_MIO_11_SLEW {slow} \ 436 | CONFIG.PCW_MIO_12_DIRECTION {inout} \ 437 | CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ 438 | CONFIG.PCW_MIO_12_PULLUP {enabled} \ 439 | CONFIG.PCW_MIO_12_SLEW {slow} \ 440 | CONFIG.PCW_MIO_13_DIRECTION {inout} \ 441 | CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ 442 | CONFIG.PCW_MIO_13_PULLUP {enabled} \ 443 | CONFIG.PCW_MIO_13_SLEW {slow} \ 444 | CONFIG.PCW_MIO_14_DIRECTION {in} \ 445 | CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ 446 | CONFIG.PCW_MIO_14_PULLUP {enabled} \ 447 | CONFIG.PCW_MIO_14_SLEW {slow} \ 448 | CONFIG.PCW_MIO_15_DIRECTION {out} \ 449 | CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ 450 | CONFIG.PCW_MIO_15_PULLUP {enabled} \ 451 | CONFIG.PCW_MIO_15_SLEW {slow} \ 452 | CONFIG.PCW_MIO_16_DIRECTION {out} \ 453 | CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ 454 | CONFIG.PCW_MIO_16_PULLUP {enabled} \ 455 | CONFIG.PCW_MIO_16_SLEW {slow} \ 456 | CONFIG.PCW_MIO_17_DIRECTION {out} \ 457 | CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ 458 | CONFIG.PCW_MIO_17_PULLUP {enabled} \ 459 | CONFIG.PCW_MIO_17_SLEW {slow} \ 460 | CONFIG.PCW_MIO_18_DIRECTION {out} \ 461 | CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ 462 | CONFIG.PCW_MIO_18_PULLUP {enabled} \ 463 | CONFIG.PCW_MIO_18_SLEW {slow} \ 464 | CONFIG.PCW_MIO_19_DIRECTION {out} \ 465 | CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ 466 | CONFIG.PCW_MIO_19_PULLUP {enabled} \ 467 | CONFIG.PCW_MIO_19_SLEW {slow} \ 468 | CONFIG.PCW_MIO_1_DIRECTION {out} \ 469 | CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ 470 | CONFIG.PCW_MIO_1_PULLUP {enabled} \ 471 | CONFIG.PCW_MIO_1_SLEW {slow} \ 472 | CONFIG.PCW_MIO_20_DIRECTION {out} \ 473 | CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ 474 | CONFIG.PCW_MIO_20_PULLUP {enabled} \ 475 | CONFIG.PCW_MIO_20_SLEW {slow} \ 476 | CONFIG.PCW_MIO_21_DIRECTION {out} \ 477 | CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ 478 | CONFIG.PCW_MIO_21_PULLUP {enabled} \ 479 | CONFIG.PCW_MIO_21_SLEW {slow} \ 480 | CONFIG.PCW_MIO_22_DIRECTION {in} \ 481 | CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ 482 | CONFIG.PCW_MIO_22_PULLUP {enabled} \ 483 | CONFIG.PCW_MIO_22_SLEW {slow} \ 484 | CONFIG.PCW_MIO_23_DIRECTION {in} \ 485 | CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ 486 | CONFIG.PCW_MIO_23_PULLUP {enabled} \ 487 | CONFIG.PCW_MIO_23_SLEW {slow} \ 488 | CONFIG.PCW_MIO_24_DIRECTION {in} \ 489 | CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ 490 | CONFIG.PCW_MIO_24_PULLUP {enabled} \ 491 | CONFIG.PCW_MIO_24_SLEW {slow} \ 492 | CONFIG.PCW_MIO_25_DIRECTION {in} \ 493 | CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ 494 | CONFIG.PCW_MIO_25_PULLUP {enabled} \ 495 | CONFIG.PCW_MIO_25_SLEW {slow} \ 496 | CONFIG.PCW_MIO_26_DIRECTION {in} \ 497 | CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ 498 | CONFIG.PCW_MIO_26_PULLUP {enabled} \ 499 | CONFIG.PCW_MIO_26_SLEW {slow} \ 500 | CONFIG.PCW_MIO_27_DIRECTION {in} \ 501 | CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ 502 | CONFIG.PCW_MIO_27_PULLUP {enabled} \ 503 | CONFIG.PCW_MIO_27_SLEW {slow} \ 504 | CONFIG.PCW_MIO_28_DIRECTION {inout} \ 505 | CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ 506 | CONFIG.PCW_MIO_28_PULLUP {enabled} \ 507 | CONFIG.PCW_MIO_28_SLEW {slow} \ 508 | CONFIG.PCW_MIO_29_DIRECTION {in} \ 509 | CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ 510 | CONFIG.PCW_MIO_29_PULLUP {enabled} \ 511 | CONFIG.PCW_MIO_29_SLEW {slow} \ 512 | CONFIG.PCW_MIO_2_DIRECTION {inout} \ 513 | CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ 514 | CONFIG.PCW_MIO_2_PULLUP {disabled} \ 515 | CONFIG.PCW_MIO_2_SLEW {slow} \ 516 | CONFIG.PCW_MIO_30_DIRECTION {out} \ 517 | CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ 518 | CONFIG.PCW_MIO_30_PULLUP {enabled} \ 519 | CONFIG.PCW_MIO_30_SLEW {slow} \ 520 | CONFIG.PCW_MIO_31_DIRECTION {in} \ 521 | CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ 522 | CONFIG.PCW_MIO_31_PULLUP {enabled} \ 523 | CONFIG.PCW_MIO_31_SLEW {slow} \ 524 | CONFIG.PCW_MIO_32_DIRECTION {inout} \ 525 | CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ 526 | CONFIG.PCW_MIO_32_PULLUP {enabled} \ 527 | CONFIG.PCW_MIO_32_SLEW {slow} \ 528 | CONFIG.PCW_MIO_33_DIRECTION {inout} \ 529 | CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ 530 | CONFIG.PCW_MIO_33_PULLUP {enabled} \ 531 | CONFIG.PCW_MIO_33_SLEW {slow} \ 532 | CONFIG.PCW_MIO_34_DIRECTION {inout} \ 533 | CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ 534 | CONFIG.PCW_MIO_34_PULLUP {enabled} \ 535 | CONFIG.PCW_MIO_34_SLEW {slow} \ 536 | CONFIG.PCW_MIO_35_DIRECTION {inout} \ 537 | CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ 538 | CONFIG.PCW_MIO_35_PULLUP {enabled} \ 539 | CONFIG.PCW_MIO_35_SLEW {slow} \ 540 | CONFIG.PCW_MIO_36_DIRECTION {in} \ 541 | CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ 542 | CONFIG.PCW_MIO_36_PULLUP {enabled} \ 543 | CONFIG.PCW_MIO_36_SLEW {slow} \ 544 | CONFIG.PCW_MIO_37_DIRECTION {inout} \ 545 | CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ 546 | CONFIG.PCW_MIO_37_PULLUP {enabled} \ 547 | CONFIG.PCW_MIO_37_SLEW {slow} \ 548 | CONFIG.PCW_MIO_38_DIRECTION {inout} \ 549 | CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ 550 | CONFIG.PCW_MIO_38_PULLUP {enabled} \ 551 | CONFIG.PCW_MIO_38_SLEW {slow} \ 552 | CONFIG.PCW_MIO_39_DIRECTION {inout} \ 553 | CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ 554 | CONFIG.PCW_MIO_39_PULLUP {enabled} \ 555 | CONFIG.PCW_MIO_39_SLEW {slow} \ 556 | CONFIG.PCW_MIO_3_DIRECTION {inout} \ 557 | CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ 558 | CONFIG.PCW_MIO_3_PULLUP {disabled} \ 559 | CONFIG.PCW_MIO_3_SLEW {slow} \ 560 | CONFIG.PCW_MIO_40_DIRECTION {inout} \ 561 | CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ 562 | CONFIG.PCW_MIO_40_PULLUP {enabled} \ 563 | CONFIG.PCW_MIO_40_SLEW {slow} \ 564 | CONFIG.PCW_MIO_41_DIRECTION {inout} \ 565 | CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ 566 | CONFIG.PCW_MIO_41_PULLUP {enabled} \ 567 | CONFIG.PCW_MIO_41_SLEW {slow} \ 568 | CONFIG.PCW_MIO_42_DIRECTION {inout} \ 569 | CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ 570 | CONFIG.PCW_MIO_42_PULLUP {enabled} \ 571 | CONFIG.PCW_MIO_42_SLEW {slow} \ 572 | CONFIG.PCW_MIO_43_DIRECTION {inout} \ 573 | CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ 574 | CONFIG.PCW_MIO_43_PULLUP {enabled} \ 575 | CONFIG.PCW_MIO_43_SLEW {slow} \ 576 | CONFIG.PCW_MIO_44_DIRECTION {inout} \ 577 | CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ 578 | CONFIG.PCW_MIO_44_PULLUP {enabled} \ 579 | CONFIG.PCW_MIO_44_SLEW {slow} \ 580 | CONFIG.PCW_MIO_45_DIRECTION {inout} \ 581 | CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ 582 | CONFIG.PCW_MIO_45_PULLUP {enabled} \ 583 | CONFIG.PCW_MIO_45_SLEW {slow} \ 584 | CONFIG.PCW_MIO_46_DIRECTION {out} \ 585 | CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ 586 | CONFIG.PCW_MIO_46_PULLUP {enabled} \ 587 | CONFIG.PCW_MIO_46_SLEW {slow} \ 588 | CONFIG.PCW_MIO_47_DIRECTION {in} \ 589 | CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ 590 | CONFIG.PCW_MIO_47_PULLUP {enabled} \ 591 | CONFIG.PCW_MIO_47_SLEW {slow} \ 592 | CONFIG.PCW_MIO_48_DIRECTION {inout} \ 593 | CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ 594 | CONFIG.PCW_MIO_48_PULLUP {enabled} \ 595 | CONFIG.PCW_MIO_48_SLEW {slow} \ 596 | CONFIG.PCW_MIO_49_DIRECTION {inout} \ 597 | CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ 598 | CONFIG.PCW_MIO_49_PULLUP {enabled} \ 599 | CONFIG.PCW_MIO_49_SLEW {slow} \ 600 | CONFIG.PCW_MIO_4_DIRECTION {inout} \ 601 | CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ 602 | CONFIG.PCW_MIO_4_PULLUP {disabled} \ 603 | CONFIG.PCW_MIO_4_SLEW {slow} \ 604 | CONFIG.PCW_MIO_50_DIRECTION {inout} \ 605 | CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ 606 | CONFIG.PCW_MIO_50_PULLUP {enabled} \ 607 | CONFIG.PCW_MIO_50_SLEW {slow} \ 608 | CONFIG.PCW_MIO_51_DIRECTION {inout} \ 609 | CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ 610 | CONFIG.PCW_MIO_51_PULLUP {enabled} \ 611 | CONFIG.PCW_MIO_51_SLEW {slow} \ 612 | CONFIG.PCW_MIO_52_DIRECTION {out} \ 613 | CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ 614 | CONFIG.PCW_MIO_52_PULLUP {enabled} \ 615 | CONFIG.PCW_MIO_52_SLEW {slow} \ 616 | CONFIG.PCW_MIO_53_DIRECTION {inout} \ 617 | CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ 618 | CONFIG.PCW_MIO_53_PULLUP {enabled} \ 619 | CONFIG.PCW_MIO_53_SLEW {slow} \ 620 | CONFIG.PCW_MIO_5_DIRECTION {inout} \ 621 | CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ 622 | CONFIG.PCW_MIO_5_PULLUP {disabled} \ 623 | CONFIG.PCW_MIO_5_SLEW {slow} \ 624 | CONFIG.PCW_MIO_6_DIRECTION {out} \ 625 | CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ 626 | CONFIG.PCW_MIO_6_PULLUP {disabled} \ 627 | CONFIG.PCW_MIO_6_SLEW {slow} \ 628 | CONFIG.PCW_MIO_7_DIRECTION {out} \ 629 | CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ 630 | CONFIG.PCW_MIO_7_PULLUP {disabled} \ 631 | CONFIG.PCW_MIO_7_SLEW {slow} \ 632 | CONFIG.PCW_MIO_8_DIRECTION {out} \ 633 | CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ 634 | CONFIG.PCW_MIO_8_PULLUP {disabled} \ 635 | CONFIG.PCW_MIO_8_SLEW {slow} \ 636 | CONFIG.PCW_MIO_9_DIRECTION {out} \ 637 | CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ 638 | CONFIG.PCW_MIO_9_PULLUP {enabled} \ 639 | CONFIG.PCW_MIO_9_SLEW {slow} \ 640 | CONFIG.PCW_MIO_PRIMITIVE {54} \ 641 | CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ 642 | CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ 643 | CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ 644 | CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ 645 | CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ 646 | CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ 647 | CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ 648 | CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ 649 | CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ 650 | CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ 651 | CONFIG.PCW_NAND_CYCLES_T_AR {1} \ 652 | CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ 653 | CONFIG.PCW_NAND_CYCLES_T_RC {11} \ 654 | CONFIG.PCW_NAND_CYCLES_T_REA {1} \ 655 | CONFIG.PCW_NAND_CYCLES_T_RR {1} \ 656 | CONFIG.PCW_NAND_CYCLES_T_WC {11} \ 657 | CONFIG.PCW_NAND_CYCLES_T_WP {1} \ 658 | CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ 659 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 660 | CONFIG.PCW_NOR_CS0_T_CEOE {1} \ 661 | CONFIG.PCW_NOR_CS0_T_PC {1} \ 662 | CONFIG.PCW_NOR_CS0_T_RC {11} \ 663 | CONFIG.PCW_NOR_CS0_T_TR {1} \ 664 | CONFIG.PCW_NOR_CS0_T_WC {11} \ 665 | CONFIG.PCW_NOR_CS0_T_WP {1} \ 666 | CONFIG.PCW_NOR_CS0_WE_TIME {0} \ 667 | CONFIG.PCW_NOR_CS1_T_CEOE {1} \ 668 | CONFIG.PCW_NOR_CS1_T_PC {1} \ 669 | CONFIG.PCW_NOR_CS1_T_RC {11} \ 670 | CONFIG.PCW_NOR_CS1_T_TR {1} \ 671 | CONFIG.PCW_NOR_CS1_T_WC {11} \ 672 | CONFIG.PCW_NOR_CS1_T_WP {1} \ 673 | CONFIG.PCW_NOR_CS1_WE_TIME {0} \ 674 | CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ 675 | CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ 676 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 677 | CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ 678 | CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ 679 | CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ 680 | CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ 681 | CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ 682 | CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ 683 | CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ 684 | CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ 685 | CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ 686 | CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ 687 | CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ 688 | CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ 689 | CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ 690 | CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ 691 | CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ 692 | CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ 693 | CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ 694 | CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ 695 | CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ 696 | CONFIG.PCW_P2F_CAN0_INTR {0} \ 697 | CONFIG.PCW_P2F_CAN1_INTR {0} \ 698 | CONFIG.PCW_P2F_CTI_INTR {0} \ 699 | CONFIG.PCW_P2F_DMAC0_INTR {0} \ 700 | CONFIG.PCW_P2F_DMAC1_INTR {0} \ 701 | CONFIG.PCW_P2F_DMAC2_INTR {0} \ 702 | CONFIG.PCW_P2F_DMAC3_INTR {0} \ 703 | CONFIG.PCW_P2F_DMAC4_INTR {0} \ 704 | CONFIG.PCW_P2F_DMAC5_INTR {0} \ 705 | CONFIG.PCW_P2F_DMAC6_INTR {0} \ 706 | CONFIG.PCW_P2F_DMAC7_INTR {0} \ 707 | CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ 708 | CONFIG.PCW_P2F_ENET0_INTR {0} \ 709 | CONFIG.PCW_P2F_ENET1_INTR {0} \ 710 | CONFIG.PCW_P2F_GPIO_INTR {0} \ 711 | CONFIG.PCW_P2F_I2C0_INTR {0} \ 712 | CONFIG.PCW_P2F_I2C1_INTR {0} \ 713 | CONFIG.PCW_P2F_QSPI_INTR {0} \ 714 | CONFIG.PCW_P2F_SDIO0_INTR {0} \ 715 | CONFIG.PCW_P2F_SDIO1_INTR {0} \ 716 | CONFIG.PCW_P2F_SMC_INTR {0} \ 717 | CONFIG.PCW_P2F_SPI0_INTR {0} \ 718 | CONFIG.PCW_P2F_SPI1_INTR {0} \ 719 | CONFIG.PCW_P2F_UART0_INTR {0} \ 720 | CONFIG.PCW_P2F_UART1_INTR {0} \ 721 | CONFIG.PCW_P2F_USB0_INTR {0} \ 722 | CONFIG.PCW_P2F_USB1_INTR {0} \ 723 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.279} \ 724 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.260} \ 725 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ 726 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ 727 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.051} \ 728 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.006} \ 729 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 730 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 731 | CONFIG.PCW_PACKAGE_NAME {clg400} \ 732 | CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ 733 | CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ 734 | CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ 735 | CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ 736 | CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ 737 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 738 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ 739 | CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ 740 | CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ 741 | CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ 742 | CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ 743 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ 744 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ 745 | CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ 746 | CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ 747 | CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ 748 | CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ 749 | CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ 750 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ 751 | CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ 752 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ 753 | CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 754 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 755 | CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ 756 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ 757 | CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 758 | CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ 759 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 760 | CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ 761 | CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ 762 | CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ 763 | CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ 764 | CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ 765 | CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ 766 | CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ 767 | CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ 768 | CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ 769 | CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ 770 | CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ 771 | CONFIG.PCW_SMC_CYCLE_T0 {NA} \ 772 | CONFIG.PCW_SMC_CYCLE_T1 {NA} \ 773 | CONFIG.PCW_SMC_CYCLE_T2 {NA} \ 774 | CONFIG.PCW_SMC_CYCLE_T3 {NA} \ 775 | CONFIG.PCW_SMC_CYCLE_T4 {NA} \ 776 | CONFIG.PCW_SMC_CYCLE_T5 {NA} \ 777 | CONFIG.PCW_SMC_CYCLE_T6 {NA} \ 778 | CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ 779 | CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ 780 | CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ 781 | CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ 782 | CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ 783 | CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ 784 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 785 | CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ 786 | CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ 787 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 788 | CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ 789 | CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ 790 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 791 | CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ 792 | CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ 793 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 794 | CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ 795 | CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ 796 | CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ 797 | CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ 798 | CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ 799 | CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ 800 | CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ 801 | CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ 802 | CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ 803 | CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ 804 | CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ 805 | CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ 806 | CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ 807 | CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ 808 | CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ 809 | CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ 810 | CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ 811 | CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ 812 | CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ 813 | CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ 814 | CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ 815 | CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ 816 | CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ 817 | CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ 818 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 819 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ 820 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 821 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 822 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ 823 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 824 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 825 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ 826 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 827 | CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ 828 | CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ 829 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 830 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ 831 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 832 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 833 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ 834 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 835 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 836 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ 837 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 838 | CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ 839 | CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ 840 | CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ 841 | CONFIG.PCW_UART0_BAUD_RATE {115200} \ 842 | CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ 843 | CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ 844 | CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ 845 | CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ 846 | CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ 847 | CONFIG.PCW_UART1_BAUD_RATE {115200} \ 848 | CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ 849 | CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ 850 | CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ 851 | CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ 852 | CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ 853 | CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ 854 | CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ 855 | CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ 856 | CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ 857 | CONFIG.PCW_UIPARAM_DDR_AL {0} \ 858 | CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ 859 | CONFIG.PCW_UIPARAM_DDR_BL {8} \ 860 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.279} \ 861 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.260} \ 862 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ 863 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ 864 | CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ 865 | CONFIG.PCW_UIPARAM_DDR_CL {7} \ 866 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {27.95} \ 867 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ 868 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ 869 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {27.95} \ 870 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ 871 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ 872 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ 873 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ 874 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ 875 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ 876 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ 877 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ 878 | CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ 879 | CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ 880 | CONFIG.PCW_UIPARAM_DDR_CWL {6} \ 881 | CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ 882 | CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {32.14} \ 883 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ 884 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ 885 | CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {31.12} \ 886 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ 887 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ 888 | CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ 889 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ 890 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ 891 | CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ 892 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ 893 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ 894 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.051} \ 895 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.006} \ 896 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 897 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 898 | CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {32.2} \ 899 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ 900 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ 901 | CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {31.08} \ 902 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ 903 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ 904 | CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ 905 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ 906 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ 907 | CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ 908 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ 909 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ 910 | CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ 911 | CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ 912 | CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ 913 | CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ 914 | CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ 915 | CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ 916 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ 917 | CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ 918 | CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ 919 | CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 920 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ 921 | CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 922 | CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ 923 | CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ 924 | CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ 925 | CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ 926 | CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ 927 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ 928 | CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ 929 | CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ 930 | CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ 931 | CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ 932 | CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ 933 | CONFIG.PCW_USB0_RESET_ENABLE {1} \ 934 | CONFIG.PCW_USB0_RESET_IO {MIO 46} \ 935 | CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ 936 | CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ 937 | CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ 938 | CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ 939 | CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ 940 | CONFIG.PCW_USB1_RESET_ENABLE {0} \ 941 | CONFIG.PCW_USB_RESET_ENABLE {1} \ 942 | CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ 943 | CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ 944 | CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ 945 | CONFIG.PCW_USE_AXI_NONSECURE {0} \ 946 | CONFIG.PCW_USE_CORESIGHT {0} \ 947 | CONFIG.PCW_USE_CROSS_TRIGGER {0} \ 948 | CONFIG.PCW_USE_CR_FABRIC {1} \ 949 | CONFIG.PCW_USE_DDR_BYPASS {0} \ 950 | CONFIG.PCW_USE_DEBUG {0} \ 951 | CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ 952 | CONFIG.PCW_USE_DMA0 {0} \ 953 | CONFIG.PCW_USE_DMA1 {0} \ 954 | CONFIG.PCW_USE_DMA2 {0} \ 955 | CONFIG.PCW_USE_DMA3 {0} \ 956 | CONFIG.PCW_USE_EXPANDED_IOP {0} \ 957 | CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ 958 | CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ 959 | CONFIG.PCW_USE_HIGH_OCM {0} \ 960 | CONFIG.PCW_USE_M_AXI_GP0 {1} \ 961 | CONFIG.PCW_USE_M_AXI_GP1 {0} \ 962 | CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ 963 | CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ 964 | CONFIG.PCW_USE_S_AXI_ACP {0} \ 965 | CONFIG.PCW_USE_S_AXI_GP0 {0} \ 966 | CONFIG.PCW_USE_S_AXI_GP1 {0} \ 967 | CONFIG.PCW_USE_S_AXI_HP0 {0} \ 968 | CONFIG.PCW_USE_S_AXI_HP1 {0} \ 969 | CONFIG.PCW_USE_S_AXI_HP2 {0} \ 970 | CONFIG.PCW_USE_S_AXI_HP3 {0} \ 971 | CONFIG.PCW_USE_TRACE {0} \ 972 | CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ 973 | CONFIG.PCW_VALUE_SILVERSION {3} \ 974 | CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ 975 | CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ 976 | CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ 977 | ] $processing_system7_0 978 | 979 | # Create instance: ps7_0_axi_periph, and set properties 980 | set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] 981 | set_property -dict [ list \ 982 | CONFIG.NUM_MI {1} \ 983 | ] $ps7_0_axi_periph 984 | 985 | # Create instance: rst_ps7_0_100M, and set properties 986 | set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] 987 | 988 | # Create interface connections 989 | connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] 990 | connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] 991 | connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] 992 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins create_tree_0/s_axi_AXILiteS] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] 993 | 994 | # Create port connections 995 | connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins create_tree_0/ap_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] 996 | connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] 997 | connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] 998 | connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins create_tree_0/ap_rst_n] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] 999 | 1000 | # Create address segments 1001 | create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs create_tree_0/s_axi_AXILiteS/Reg] SEG_create_tree_0_Reg 1002 | 1003 | 1004 | # Restore current instance 1005 | current_bd_instance $oldCurInst 1006 | 1007 | save_bd_design 1008 | } 1009 | # End of create_root_design() 1010 | 1011 | 1012 | ################################################################## 1013 | # MAIN FLOW 1014 | ################################################################## 1015 | 1016 | create_root_design "" 1017 | 1018 | 1019 | -------------------------------------------------------------------------------- /tests/create-tree-core-test/notebook/create-tree-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": { 7 | "scrolled": true 8 | }, 9 | "outputs": [ 10 | { 11 | "data": { 12 | "application/javascript": [ 13 | "\n", 14 | "require(['notebook/js/codecell'], function(codecell) {\n", 15 | " codecell.CodeCell.options_default.highlight_modes[\n", 16 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 17 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 18 | " Jupyter.notebook.get_cells().map(function(cell){\n", 19 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 20 | " });\n", 21 | "});\n" 22 | ] 23 | }, 24 | "metadata": {}, 25 | "output_type": "display_data" 26 | }, 27 | { 28 | "name": "stdout", 29 | "output_type": "stream", 30 | "text": [ 31 | "pos : 0 parent : 1\n", 32 | " lchild : 102\n", 33 | " rchild : 98\n", 34 | "pos : 1 parent : 2\n", 35 | " lchild : 99\n", 36 | " rchild : 4294967295\n", 37 | "pos : 2 parent : 4\n", 38 | " lchild : 97\n", 39 | " rchild : 4294967295\n", 40 | "pos : 3 parent : 4\n", 41 | " lchild : 100\n", 42 | " rchild : 101\n", 43 | "pos : 4 parent : 0\n", 44 | " lchild : 4294967295\n", 45 | " rchild : 4294967295\n", 46 | "pos : 5 parent : 0\n", 47 | " lchild : 0\n", 48 | " rchild : 0\n", 49 | "pos : 6 parent : 0\n", 50 | " lchild : 0\n", 51 | " rchild : 0\n", 52 | "pos : 7 parent : 0\n", 53 | " lchild : 0\n", 54 | " rchild : 0\n", 55 | "pos : 8 parent : 0\n", 56 | " lchild : 0\n", 57 | " rchild : 0\n", 58 | "pos : 9 parent : 0\n", 59 | " lchild : 0\n", 60 | " rchild : 0\n" 61 | ] 62 | } 63 | ], 64 | "source": [ 65 | "# AXILiteS\n", 66 | "# 0x0000 : Control signals\n", 67 | "# bit 0 - ap_start (Read/Write/COH)\n", 68 | "# bit 1 - ap_done (Read/COR)\n", 69 | "# bit 2 - ap_idle (Read)\n", 70 | "# bit 3 - ap_ready (Read)\n", 71 | "# bit 7 - auto_restart (Read/Write)\n", 72 | "# others - reserved\n", 73 | "# 0x0004 : Global Interrupt Enable Register\n", 74 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 75 | "# others - reserved\n", 76 | "# 0x0008 : IP Interrupt Enable Register (Read/Write)\n", 77 | "# bit 0 - Channel 0 (ap_done)\n", 78 | "# bit 1 - Channel 1 (ap_ready)\n", 79 | "# others - reserved\n", 80 | "# 0x000c : IP Interrupt Status Register (Read/TOW)\n", 81 | "# bit 0 - Channel 0 (ap_done)\n", 82 | "# bit 1 - Channel 1 (ap_ready)\n", 83 | "# others - reserved\n", 84 | "# 0x0c00 : Data signal of num_symbols\n", 85 | "# bit 31~0 - num_symbols[31:0] (Read/Write)\n", 86 | "# 0x0c04 : reserved\n", 87 | "# 0x0400 ~\n", 88 | "# 0x07ff : Memory 'in_value_V' (256 * 32b)\n", 89 | "# Word n : bit [31:0] - in_value_V[n]\n", 90 | "# 0x0800 ~\n", 91 | "# 0x0bff : Memory 'in_frequency_V' (256 * 32b)\n", 92 | "# Word n : bit [31:0] - in_frequency_V[n]\n", 93 | "# 0x1000 ~\n", 94 | "# 0x13ff : Memory 'parent_V' (255 * 32b)\n", 95 | "# Word n : bit [31:0] - parent_V[n]\n", 96 | "# 0x1400 ~\n", 97 | "# 0x17ff : Memory 'left_V' (255 * 32b)\n", 98 | "# Word n : bit [31:0] - left_V[n]\n", 99 | "# 0x1800 ~\n", 100 | "# 0x1bff : Memory 'right_V' (255 * 32b)\n", 101 | "# Word n : bit [31:0] - right_V[n]\n", 102 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 103 | "\n", 104 | "from pynq import Overlay\n", 105 | "\n", 106 | "overlay = Overlay(\"../bitstream/create-tree-test.bit\")\n", 107 | "overlay.download()\n", 108 | "\n", 109 | "create_tree = overlay.create_tree_0\n", 110 | "\n", 111 | "# Sorted Table\n", 112 | "# ------------\n", 113 | "# F | 1\n", 114 | "# B | 1\n", 115 | "# C | 2\n", 116 | "# A | 3\n", 117 | "# D | 5\n", 118 | "# E | 5\n", 119 | "\n", 120 | "sorted_table = [\n", 121 | " { 'symbol': 'f', 'freq': 1 },\n", 122 | " { 'symbol': 'b', 'freq': 1 },\n", 123 | " { 'symbol': 'c', 'freq': 2 },\n", 124 | " { 'symbol': 'a', 'freq': 3 },\n", 125 | " { 'symbol': 'd', 'freq': 5 },\n", 126 | " { 'symbol': 'e', 'freq': 5 }\n", 127 | "]\n", 128 | "\n", 129 | "# set symbol numbers\n", 130 | "create_tree.write(0x0c00, 6)\n", 131 | "\n", 132 | "# write register\n", 133 | "for idx, pair in enumerate(sorted_table):\n", 134 | " # write symbol order\n", 135 | " create_tree.write(0x0400 + 4*idx, ord(pair['symbol']))\n", 136 | " # write symbol frequency\n", 137 | " create_tree.write(0x0800 + 4*idx, pair['freq'])\n", 138 | "\n", 139 | "# start\n", 140 | "create_tree.write(0x0000, 1)\n", 141 | "\n", 142 | "from time import sleep\n", 143 | "\n", 144 | "sleep(5)\n", 145 | "\n", 146 | "# read created tree\n", 147 | "for i in range(10):\n", 148 | " # read node\n", 149 | " parent = create_tree.read(0x1000 + 4*i)\n", 150 | " lchild = create_tree.read(0x1400 + 4*i)\n", 151 | " rchild = create_tree.read(0x1800 + 4*i)\n", 152 | " # read left & right\n", 153 | " print(\"pos : \" + str(i) + \" parent : \" + str(parent))\n", 154 | " print(\" lchild : \" + str(lchild))\n", 155 | " print(\" rchild : \" + str(rchild))" 156 | ] 157 | }, 158 | { 159 | "cell_type": "code", 160 | "execution_count": null, 161 | "metadata": {}, 162 | "outputs": [], 163 | "source": [] 164 | } 165 | ], 166 | "metadata": { 167 | "kernelspec": { 168 | "display_name": "Python 3", 169 | "language": "python", 170 | "name": "python3" 171 | }, 172 | "language_info": { 173 | "codemirror_mode": { 174 | "name": "ipython", 175 | "version": 3 176 | }, 177 | "file_extension": ".py", 178 | "mimetype": "text/x-python", 179 | "name": "python", 180 | "nbconvert_exporter": "python", 181 | "pygments_lexer": "ipython3", 182 | "version": "3.6.0" 183 | } 184 | }, 185 | "nbformat": 4, 186 | "nbformat_minor": 2 187 | } 188 | -------------------------------------------------------------------------------- /tests/huffman-encoding-test/bitstream/huffman-encoding-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/huffman-encoding-test/bitstream/huffman-encoding-test.bit -------------------------------------------------------------------------------- /tests/huffman-encoding-test/notebook/huffman-encoding-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": [ 11 | "\n", 12 | "require(['notebook/js/codecell'], function(codecell) {\n", 13 | " codecell.CodeCell.options_default.highlight_modes[\n", 14 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 15 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 16 | " Jupyter.notebook.get_cells().map(function(cell){\n", 17 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 18 | " });\n", 19 | "});\n" 20 | ] 21 | }, 22 | "metadata": {}, 23 | "output_type": "display_data" 24 | }, 25 | { 26 | "name": "stdout", 27 | "output_type": "stream", 28 | "text": [ 29 | "There are 6 symbols in huffman tree:\n", 30 | "symbol : a, code word : 00000000000000000000000000000010\n", 31 | "symbol : b, code word : 00000000000000000000000011100100\n", 32 | "symbol : c, code word : 00000000000000000000000001100011\n", 33 | "symbol : d, code word : 00000000000000000000000001000010\n", 34 | "symbol : e, code word : 00000000000000000000000000100010\n", 35 | "symbol : f, code word : 00000000000000000000000111100100\n", 36 | "symbol : g, code word : 00000000000000000000000000000000\n" 37 | ] 38 | } 39 | ], 40 | "source": [ 41 | "# AXILiteS\n", 42 | "# 0x0000 : Control signals\n", 43 | "# bit 0 - ap_start (Read/Write/COH)\n", 44 | "# bit 1 - ap_done (Read/COR)\n", 45 | "# bit 2 - ap_idle (Read)\n", 46 | "# bit 3 - ap_ready (Read)\n", 47 | "# bit 7 - auto_restart (Read/Write)\n", 48 | "# others - reserved\n", 49 | "# 0x0004 : Global Interrupt Enable Register\n", 50 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 51 | "# others - reserved\n", 52 | "# 0x0008 : IP Interrupt Enable Register (Read/Write)\n", 53 | "# bit 0 - Channel 0 (ap_done)\n", 54 | "# bit 1 - Channel 1 (ap_ready)\n", 55 | "# others - reserved\n", 56 | "# 0x000c : IP Interrupt Status Register (Read/TOW)\n", 57 | "# bit 0 - Channel 0 (ap_done)\n", 58 | "# bit 1 - Channel 1 (ap_ready)\n", 59 | "# others - reserved\n", 60 | "# 0x1000 : Data signal of num_nonzero_symbols\n", 61 | "# bit 31~0 - num_nonzero_symbols[31:0] (Read)\n", 62 | "# 0x1004 : Control signal of num_nonzero_symbols\n", 63 | "# bit 0 - num_nonzero_symbols_ap_vld (Read/COR)\n", 64 | "# others - reserved\n", 65 | "# 0x0400 ~\n", 66 | "# 0x07ff : Memory 'symbol_histogram_value_V' (256 * 32b)\n", 67 | "# Word n : bit [31:0] - symbol_histogram_value_V[n]\n", 68 | "# 0x0800 ~\n", 69 | "# 0x0bff : Memory 'symbol_histogram_frequency_V' (256 * 32b)\n", 70 | "# Word n : bit [31:0] - symbol_histogram_frequency_V[n]\n", 71 | "# 0x0c00 ~\n", 72 | "# 0x0fff : Memory 'encoding_V' (256 * 32b)\n", 73 | "# Word n : bit [31:0] - encoding_V[n]\n", 74 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 75 | "\n", 76 | "from pynq import Overlay\n", 77 | "\n", 78 | "overlay = Overlay(\"../bitstream/huffman-encoding-test.bit\")\n", 79 | "overlay.download()\n", 80 | "\n", 81 | "huffman_encoding = overlay.huffman_encoding_0\n", 82 | "\n", 83 | "symbol_table = [\n", 84 | " { 'symbol': 'a', 'freq': 3 },\n", 85 | " { 'symbol': 'b', 'freq': 1 },\n", 86 | " { 'symbol': 'c', 'freq': 2 },\n", 87 | " { 'symbol': 'd', 'freq': 5 },\n", 88 | " { 'symbol': 'e', 'freq': 5 },\n", 89 | " { 'symbol': 'f', 'freq': 1 },\n", 90 | " { 'symbol': 'g', 'freq': 0 },\n", 91 | "]\n", 92 | "\n", 93 | "for idx, sym in enumerate(symbol_table):\n", 94 | " # write symbol & frequency\n", 95 | " huffman_encoding.write(0x0400 + 4*idx, ord(sym['symbol']))\n", 96 | " huffman_encoding.write(0x0800 + 4*idx, sym['freq'])\n", 97 | " \n", 98 | "# start\n", 99 | "huffman_encoding.write(0x0000, 1)\n", 100 | "\n", 101 | "from time import sleep\n", 102 | "\n", 103 | "sleep(1)\n", 104 | "\n", 105 | "# read number of symbols\n", 106 | "num = huffman_encoding.read(0x1000)\n", 107 | "print('There are ' + str(num) + ' symbols in huffman tree:')\n", 108 | "\n", 109 | "# read encoding\n", 110 | "get_bin = lambda x, n: format(x, 'b').zfill(n)\n", 111 | "for idx, sym in enumerate(symbol_table):\n", 112 | " encoding = huffman_encoding.read(0x0c00 + 4*ord(sym['symbol']))\n", 113 | " print('symbol : ' + sym['symbol'] + ', code word : ' + get_bin(encoding, 32))" 114 | ] 115 | } 116 | ], 117 | "metadata": { 118 | "kernelspec": { 119 | "display_name": "Python 3", 120 | "language": "python", 121 | "name": "python3" 122 | }, 123 | "language_info": { 124 | "codemirror_mode": { 125 | "name": "ipython", 126 | "version": 3 127 | }, 128 | "file_extension": ".py", 129 | "mimetype": "text/x-python", 130 | "name": "python", 131 | "nbconvert_exporter": "python", 132 | "pygments_lexer": "ipython3", 133 | "version": "3.6.0" 134 | } 135 | }, 136 | "nbformat": 4, 137 | "nbformat_minor": 2 138 | } 139 | -------------------------------------------------------------------------------- /tests/irq-test/bitstream/irq-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/irq-test/bitstream/irq-test.bit -------------------------------------------------------------------------------- /tests/irq-test/notebook/irq-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": null, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "name": "stdout", 10 | "output_type": "stream", 11 | "text": [ 12 | "intr received from 1\n", 13 | "There are 6 symbols in huffman tree:\n", 14 | "symbol : a, code word : 00000000000000000000000000000010\n", 15 | "symbol : b, code word : 00000000000000000000000011100100\n", 16 | "symbol : c, code word : 00000000000000000000000001100011\n", 17 | "symbol : d, code word : 00000000000000000000000001000010\n", 18 | "symbol : e, code word : 00000000000000000000000000100010\n", 19 | "symbol : f, code word : 00000000000000000000000111100100\n", 20 | "symbol : g, code word : 00000000000000000000000000000000\n", 21 | "intr received from 0\n" 22 | ] 23 | } 24 | ], 25 | "source": [ 26 | "# AXILiteS\n", 27 | "# 0x0000 : Control signals\n", 28 | "# bit 0 - ap_start (Read/Write/COH)\n", 29 | "# bit 1 - ap_done (Read/COR)\n", 30 | "# bit 2 - ap_idle (Read)\n", 31 | "# bit 3 - ap_ready (Read)\n", 32 | "# bit 7 - auto_restart (Read/Write)\n", 33 | "# others - reserved\n", 34 | "# 0x0004 : Global Interrupt Enable Register\n", 35 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 36 | "# others - reserved\n", 37 | "# 0x0008 : IP Interrupt Enable Register (Read/Write)\n", 38 | "# bit 0 - Channel 0 (ap_done)\n", 39 | "# bit 1 - Channel 1 (ap_ready)\n", 40 | "# others - reserved\n", 41 | "# 0x000c : IP Interrupt Status Register (Read/TOW)\n", 42 | "# bit 0 - Channel 0 (ap_done)\n", 43 | "# bit 1 - Channel 1 (ap_ready)\n", 44 | "# others - reserved\n", 45 | "# 0x1000 : Data signal of num_nonzero_symbols\n", 46 | "# bit 31~0 - num_nonzero_symbols[31:0] (Read)\n", 47 | "# 0x1004 : Control signal of num_nonzero_symbols\n", 48 | "# bit 0 - num_nonzero_symbols_ap_vld (Read/COR)\n", 49 | "# others - reserved\n", 50 | "# 0x0400 ~\n", 51 | "# 0x07ff : Memory 'symbol_histogram_value_V' (256 * 32b)\n", 52 | "# Word n : bit [31:0] - symbol_histogram_value_V[n]\n", 53 | "# 0x0800 ~\n", 54 | "# 0x0bff : Memory 'symbol_histogram_frequency_V' (256 * 32b)\n", 55 | "# Word n : bit [31:0] - symbol_histogram_frequency_V[n]\n", 56 | "# 0x0c00 ~\n", 57 | "# 0x0fff : Memory 'encoding_V' (256 * 32b)\n", 58 | "# Word n : bit [31:0] - encoding_V[n]\n", 59 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 60 | "\n", 61 | "from pynq import Overlay\n", 62 | "import asyncio\n", 63 | "\n", 64 | "overlay = Overlay(\"../bitstream/irq-test.bit\")\n", 65 | "# overlay.download()\n", 66 | "\n", 67 | "huffman_encoding = overlay.huffman_encoding_0\n", 68 | "\n", 69 | "symbol_table = [\n", 70 | " { 'symbol': 'a', 'freq': 3 },\n", 71 | " { 'symbol': 'b', 'freq': 1 },\n", 72 | " { 'symbol': 'c', 'freq': 2 },\n", 73 | " { 'symbol': 'd', 'freq': 5 },\n", 74 | " { 'symbol': 'e', 'freq': 5 },\n", 75 | " { 'symbol': 'f', 'freq': 1 },\n", 76 | " { 'symbol': 'g', 'freq': 0 },\n", 77 | "]\n", 78 | "\n", 79 | "for idx, sym in enumerate(symbol_table):\n", 80 | " # write symbol & frequency\n", 81 | " huffman_encoding.write(0x0400 + 4*idx, ord(sym['symbol']))\n", 82 | " huffman_encoding.write(0x0800 + 4*idx, sym['freq'])\n", 83 | " \n", 84 | "# set interrupt for done signal\n", 85 | "huffman_encoding.write(0x0008, 1)\n", 86 | "# enable globel interrupt\n", 87 | "huffman_encoding.write(0x0004, 1)\n", 88 | "# start\n", 89 | "huffman_encoding.write(0x0000, 1)\n", 90 | " \n", 91 | "async def huff_intr_handler(huff):\n", 92 | " while True:\n", 93 | " await huff.interrupt.wait()\n", 94 | " print('intr received from ' + str(huff.read(0x000c)))\n", 95 | " if (huff.read(0x000c) == 1):\n", 96 | " # read number of symbols\n", 97 | " num = huff.read(0x1000)\n", 98 | " print('There are ' + str(num) + ' symbols in huffman tree:')\n", 99 | "\n", 100 | " # read encoding\n", 101 | " get_bin = lambda x, n: format(x, 'b').zfill(n)\n", 102 | " for idx, sym in enumerate(symbol_table):\n", 103 | " encoding = huff.read(0x0c00 + 4*ord(sym['symbol']))\n", 104 | " print('symbol : ' + sym['symbol'] + ', code word : ' + get_bin(encoding, 32))\n", 105 | " if (huff.read(0x000c) & 0x1):\n", 106 | " huff.write(0x000c, 1)\n", 107 | "\n", 108 | "# get EventLoop:\n", 109 | "loop = asyncio.get_event_loop()\n", 110 | "# run coroutine\n", 111 | "loop.run_until_complete(huff_intr_handler(huffman_encoding))\n", 112 | "loop.close()" 113 | ] 114 | } 115 | ], 116 | "metadata": { 117 | "kernelspec": { 118 | "display_name": "Python 3", 119 | "language": "python", 120 | "name": "python3" 121 | }, 122 | "language_info": { 123 | "codemirror_mode": { 124 | "name": "ipython", 125 | "version": 3 126 | }, 127 | "file_extension": ".py", 128 | "mimetype": "text/x-python", 129 | "name": "python", 130 | "nbconvert_exporter": "python", 131 | "pygments_lexer": "ipython3", 132 | "version": "3.6.0" 133 | } 134 | }, 135 | "nbformat": 4, 136 | "nbformat_minor": 2 137 | } 138 | -------------------------------------------------------------------------------- /tests/sort-core-test/bitstream/sort-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/sort-core-test/bitstream/sort-test.bit -------------------------------------------------------------------------------- /tests/sort-core-test/bitstream/sort-test.tcl: -------------------------------------------------------------------------------- 1 | 2 | ################################################################ 3 | # This is a generated script based on design: axi_huffman_encoder_bd 4 | # 5 | # Though there are limitations about the generated script, 6 | # the main purpose of this utility is to make learning 7 | # IP Integrator Tcl commands easier. 8 | ################################################################ 9 | 10 | namespace eval _tcl { 11 | proc get_script_folder {} { 12 | set script_path [file normalize [info script]] 13 | set script_folder [file dirname $script_path] 14 | return $script_folder 15 | } 16 | } 17 | variable script_folder 18 | set script_folder [_tcl::get_script_folder] 19 | 20 | ################################################################ 21 | # Check if script is running in correct Vivado version. 22 | ################################################################ 23 | set scripts_vivado_version 2017.4 24 | set current_vivado_version [version -short] 25 | 26 | if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { 27 | puts "" 28 | catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} 29 | 30 | return 1 31 | } 32 | 33 | ################################################################ 34 | # START 35 | ################################################################ 36 | 37 | # To test this script, run the following commands from Vivado Tcl console: 38 | # source axi_huffman_encoder_bd_script.tcl 39 | 40 | # If there is no project opened, this script will create a 41 | # project, but make sure you do not have an existing project 42 | # <./myproj/project_1.xpr> in the current working folder. 43 | 44 | set list_projs [get_projects -quiet] 45 | if { $list_projs eq "" } { 46 | create_project project_1 myproj -part xc7z020clg400-1 47 | set_property BOARD_PART tul.com.tw:pynq-z2:part0:1.0 [current_project] 48 | } 49 | 50 | 51 | # CHANGE DESIGN NAME HERE 52 | variable design_name 53 | set design_name axi_huffman_encoder_bd 54 | 55 | # If you do not already have an existing IP Integrator design open, 56 | # you can create a design using the following command: 57 | # create_bd_design $design_name 58 | 59 | # Creating design if needed 60 | set errMsg "" 61 | set nRet 0 62 | 63 | set cur_design [current_bd_design -quiet] 64 | set list_cells [get_bd_cells -quiet] 65 | 66 | if { ${design_name} eq "" } { 67 | # USE CASES: 68 | # 1) Design_name not set 69 | 70 | set errMsg "Please set the variable to a non-empty value." 71 | set nRet 1 72 | 73 | } elseif { ${cur_design} ne "" && ${list_cells} eq "" } { 74 | # USE CASES: 75 | # 2): Current design opened AND is empty AND names same. 76 | # 3): Current design opened AND is empty AND names diff; design_name NOT in project. 77 | # 4): Current design opened AND is empty AND names diff; design_name exists in project. 78 | 79 | if { $cur_design ne $design_name } { 80 | common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." 81 | set design_name [get_property NAME $cur_design] 82 | } 83 | common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." 84 | 85 | } elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { 86 | # USE CASES: 87 | # 5) Current design opened AND has components AND same names. 88 | 89 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 90 | set nRet 1 91 | } elseif { [get_files -quiet ${design_name}.bd] ne "" } { 92 | # USE CASES: 93 | # 6) Current opened design, has components, but diff names, design_name exists in project. 94 | # 7) No opened design, design_name exists in project. 95 | 96 | set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." 97 | set nRet 2 98 | 99 | } else { 100 | # USE CASES: 101 | # 8) No opened design, design_name not in project. 102 | # 9) Current opened design, has components, but diff names, design_name not in project. 103 | 104 | common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." 105 | 106 | create_bd_design $design_name 107 | 108 | common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." 109 | current_bd_design $design_name 110 | 111 | } 112 | 113 | common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." 114 | 115 | if { $nRet != 0 } { 116 | catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} 117 | return $nRet 118 | } 119 | 120 | set bCheckIPsPassed 1 121 | ################################################################## 122 | # CHECK IPs 123 | ################################################################## 124 | set bCheckIPs 1 125 | if { $bCheckIPs == 1 } { 126 | set list_check_ips "\ 127 | xilinx.com:ip:processing_system7:5.5\ 128 | xilinx.com:ip:proc_sys_reset:5.0\ 129 | xilinx.com:hls:sort:1.0\ 130 | " 131 | 132 | set list_ips_missing "" 133 | common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." 134 | 135 | foreach ip_vlnv $list_check_ips { 136 | set ip_obj [get_ipdefs -all $ip_vlnv] 137 | if { $ip_obj eq "" } { 138 | lappend list_ips_missing $ip_vlnv 139 | } 140 | } 141 | 142 | if { $list_ips_missing ne "" } { 143 | catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } 144 | set bCheckIPsPassed 0 145 | } 146 | 147 | } 148 | 149 | if { $bCheckIPsPassed != 1 } { 150 | common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." 151 | return 3 152 | } 153 | 154 | ################################################################## 155 | # DESIGN PROCs 156 | ################################################################## 157 | 158 | 159 | 160 | # Procedure to create entire design; Provide argument to make 161 | # procedure reusable. If parentCell is "", will use root. 162 | proc create_root_design { parentCell } { 163 | 164 | variable script_folder 165 | variable design_name 166 | 167 | if { $parentCell eq "" } { 168 | set parentCell [get_bd_cells /] 169 | } 170 | 171 | # Get object for parentCell 172 | set parentObj [get_bd_cells $parentCell] 173 | if { $parentObj == "" } { 174 | catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} 175 | return 176 | } 177 | 178 | # Make sure parentObj is hier blk 179 | set parentType [get_property TYPE $parentObj] 180 | if { $parentType ne "hier" } { 181 | catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} 182 | return 183 | } 184 | 185 | # Save current instance; Restore later 186 | set oldCurInst [current_bd_instance .] 187 | 188 | # Set parent object as current 189 | current_bd_instance $parentObj 190 | 191 | 192 | # Create interface ports 193 | set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] 194 | set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] 195 | 196 | # Create ports 197 | 198 | # Create instance: processing_system7_0, and set properties 199 | set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] 200 | set_property -dict [ list \ 201 | CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ 202 | CONFIG.PCW_ACT_CAN0_PERIPHERAL_FREQMHZ {23.8095} \ 203 | CONFIG.PCW_ACT_CAN1_PERIPHERAL_FREQMHZ {23.8095} \ 204 | CONFIG.PCW_ACT_CAN_PERIPHERAL_FREQMHZ {10.000000} \ 205 | CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ 206 | CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ 207 | CONFIG.PCW_ACT_ENET1_PERIPHERAL_FREQMHZ {10.000000} \ 208 | CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ 209 | CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ 210 | CONFIG.PCW_ACT_FPGA2_PERIPHERAL_FREQMHZ {10.000000} \ 211 | CONFIG.PCW_ACT_FPGA3_PERIPHERAL_FREQMHZ {10.000000} \ 212 | CONFIG.PCW_ACT_I2C_PERIPHERAL_FREQMHZ {50} \ 213 | CONFIG.PCW_ACT_PCAP_PERIPHERAL_FREQMHZ {200.000000} \ 214 | CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ 215 | CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ 216 | CONFIG.PCW_ACT_SMC_PERIPHERAL_FREQMHZ {10.000000} \ 217 | CONFIG.PCW_ACT_SPI_PERIPHERAL_FREQMHZ {10.000000} \ 218 | CONFIG.PCW_ACT_TPIU_PERIPHERAL_FREQMHZ {200.000000} \ 219 | CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 220 | CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 221 | CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 222 | CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ 223 | CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ 224 | CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ 225 | CONFIG.PCW_ACT_TTC_PERIPHERAL_FREQMHZ {50} \ 226 | CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ 227 | CONFIG.PCW_ACT_USB0_PERIPHERAL_FREQMHZ {60} \ 228 | CONFIG.PCW_ACT_USB1_PERIPHERAL_FREQMHZ {60} \ 229 | CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ 230 | CONFIG.PCW_APU_CLK_RATIO_ENABLE {6:2:1} \ 231 | CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ 232 | CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ 233 | CONFIG.PCW_CAN0_BASEADDR {0xE0008000} \ 234 | CONFIG.PCW_CAN0_HIGHADDR {0xE0008FFF} \ 235 | CONFIG.PCW_CAN0_PERIPHERAL_CLKSRC {External} \ 236 | CONFIG.PCW_CAN0_PERIPHERAL_FREQMHZ {-1} \ 237 | CONFIG.PCW_CAN1_BASEADDR {0xE0009000} \ 238 | CONFIG.PCW_CAN1_HIGHADDR {0xE0009FFF} \ 239 | CONFIG.PCW_CAN1_PERIPHERAL_CLKSRC {External} \ 240 | CONFIG.PCW_CAN1_PERIPHERAL_FREQMHZ {-1} \ 241 | CONFIG.PCW_CAN_PERIPHERAL_CLKSRC {IO PLL} \ 242 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR0 {1} \ 243 | CONFIG.PCW_CAN_PERIPHERAL_DIVISOR1 {1} \ 244 | CONFIG.PCW_CAN_PERIPHERAL_FREQMHZ {100} \ 245 | CONFIG.PCW_CAN_PERIPHERAL_VALID {0} \ 246 | CONFIG.PCW_CLK0_FREQ {100000000} \ 247 | CONFIG.PCW_CLK1_FREQ {10000000} \ 248 | CONFIG.PCW_CLK2_FREQ {10000000} \ 249 | CONFIG.PCW_CLK3_FREQ {10000000} \ 250 | CONFIG.PCW_CORE0_FIQ_INTR {0} \ 251 | CONFIG.PCW_CORE0_IRQ_INTR {0} \ 252 | CONFIG.PCW_CORE1_FIQ_INTR {0} \ 253 | CONFIG.PCW_CORE1_IRQ_INTR {0} \ 254 | CONFIG.PCW_CPU_CPU_6X4X_MAX_RANGE {667} \ 255 | CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ 256 | CONFIG.PCW_CPU_PERIPHERAL_CLKSRC {ARM PLL} \ 257 | CONFIG.PCW_CPU_PERIPHERAL_DIVISOR0 {2} \ 258 | CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ 259 | CONFIG.PCW_DCI_PERIPHERAL_CLKSRC {DDR PLL} \ 260 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ 261 | CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ 262 | CONFIG.PCW_DCI_PERIPHERAL_FREQMHZ {10.159} \ 263 | CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ 264 | CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ 265 | CONFIG.PCW_DDR_HPRLPR_QUEUE_PARTITION {HPR(0)/LPR(32)} \ 266 | CONFIG.PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL {15} \ 267 | CONFIG.PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL {2} \ 268 | CONFIG.PCW_DDR_PERIPHERAL_CLKSRC {DDR PLL} \ 269 | CONFIG.PCW_DDR_PERIPHERAL_DIVISOR0 {2} \ 270 | CONFIG.PCW_DDR_PORT0_HPR_ENABLE {0} \ 271 | CONFIG.PCW_DDR_PORT1_HPR_ENABLE {0} \ 272 | CONFIG.PCW_DDR_PORT2_HPR_ENABLE {0} \ 273 | CONFIG.PCW_DDR_PORT3_HPR_ENABLE {0} \ 274 | CONFIG.PCW_DDR_RAM_BASEADDR {0x00100000} \ 275 | CONFIG.PCW_DDR_RAM_HIGHADDR {0x1FFFFFFF} \ 276 | CONFIG.PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL {2} \ 277 | CONFIG.PCW_DM_WIDTH {4} \ 278 | CONFIG.PCW_DQS_WIDTH {4} \ 279 | CONFIG.PCW_DQ_WIDTH {32} \ 280 | CONFIG.PCW_ENET0_BASEADDR {0xE000B000} \ 281 | CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ 282 | CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ 283 | CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ 284 | CONFIG.PCW_ENET0_HIGHADDR {0xE000BFFF} \ 285 | CONFIG.PCW_ENET0_PERIPHERAL_CLKSRC {IO PLL} \ 286 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ 287 | CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR1 {1} \ 288 | CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ 289 | CONFIG.PCW_ENET0_PERIPHERAL_FREQMHZ {1000 Mbps} \ 290 | CONFIG.PCW_ENET0_RESET_ENABLE {1} \ 291 | CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ 292 | CONFIG.PCW_ENET1_BASEADDR {0xE000C000} \ 293 | CONFIG.PCW_ENET1_GRP_MDIO_ENABLE {0} \ 294 | CONFIG.PCW_ENET1_HIGHADDR {0xE000CFFF} \ 295 | CONFIG.PCW_ENET1_PERIPHERAL_CLKSRC {IO PLL} \ 296 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR0 {1} \ 297 | CONFIG.PCW_ENET1_PERIPHERAL_DIVISOR1 {1} \ 298 | CONFIG.PCW_ENET1_PERIPHERAL_ENABLE {0} \ 299 | CONFIG.PCW_ENET1_PERIPHERAL_FREQMHZ {1000 Mbps} \ 300 | CONFIG.PCW_ENET1_RESET_ENABLE {0} \ 301 | CONFIG.PCW_ENET_RESET_ENABLE {1} \ 302 | CONFIG.PCW_ENET_RESET_POLARITY {Active Low} \ 303 | CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ 304 | CONFIG.PCW_EN_4K_TIMER {0} \ 305 | CONFIG.PCW_EN_CAN0 {0} \ 306 | CONFIG.PCW_EN_CAN1 {0} \ 307 | CONFIG.PCW_EN_CLK0_PORT {1} \ 308 | CONFIG.PCW_EN_CLK1_PORT {0} \ 309 | CONFIG.PCW_EN_CLK2_PORT {0} \ 310 | CONFIG.PCW_EN_CLK3_PORT {0} \ 311 | CONFIG.PCW_EN_CLKTRIG0_PORT {0} \ 312 | CONFIG.PCW_EN_CLKTRIG1_PORT {0} \ 313 | CONFIG.PCW_EN_CLKTRIG2_PORT {0} \ 314 | CONFIG.PCW_EN_CLKTRIG3_PORT {0} \ 315 | CONFIG.PCW_EN_DDR {1} \ 316 | CONFIG.PCW_EN_EMIO_CAN0 {0} \ 317 | CONFIG.PCW_EN_EMIO_CAN1 {0} \ 318 | CONFIG.PCW_EN_EMIO_CD_SDIO0 {0} \ 319 | CONFIG.PCW_EN_EMIO_CD_SDIO1 {0} \ 320 | CONFIG.PCW_EN_EMIO_ENET0 {0} \ 321 | CONFIG.PCW_EN_EMIO_ENET1 {0} \ 322 | CONFIG.PCW_EN_EMIO_GPIO {0} \ 323 | CONFIG.PCW_EN_EMIO_I2C0 {0} \ 324 | CONFIG.PCW_EN_EMIO_I2C1 {0} \ 325 | CONFIG.PCW_EN_EMIO_MODEM_UART0 {0} \ 326 | CONFIG.PCW_EN_EMIO_MODEM_UART1 {0} \ 327 | CONFIG.PCW_EN_EMIO_PJTAG {0} \ 328 | CONFIG.PCW_EN_EMIO_SDIO0 {0} \ 329 | CONFIG.PCW_EN_EMIO_SDIO1 {0} \ 330 | CONFIG.PCW_EN_EMIO_SPI0 {0} \ 331 | CONFIG.PCW_EN_EMIO_SPI1 {0} \ 332 | CONFIG.PCW_EN_EMIO_SRAM_INT {0} \ 333 | CONFIG.PCW_EN_EMIO_TRACE {0} \ 334 | CONFIG.PCW_EN_EMIO_TTC0 {0} \ 335 | CONFIG.PCW_EN_EMIO_TTC1 {0} \ 336 | CONFIG.PCW_EN_EMIO_UART0 {0} \ 337 | CONFIG.PCW_EN_EMIO_UART1 {0} \ 338 | CONFIG.PCW_EN_EMIO_WDT {0} \ 339 | CONFIG.PCW_EN_EMIO_WP_SDIO0 {0} \ 340 | CONFIG.PCW_EN_EMIO_WP_SDIO1 {0} \ 341 | CONFIG.PCW_EN_ENET0 {1} \ 342 | CONFIG.PCW_EN_ENET1 {0} \ 343 | CONFIG.PCW_EN_GPIO {1} \ 344 | CONFIG.PCW_EN_I2C0 {0} \ 345 | CONFIG.PCW_EN_I2C1 {0} \ 346 | CONFIG.PCW_EN_MODEM_UART0 {0} \ 347 | CONFIG.PCW_EN_MODEM_UART1 {0} \ 348 | CONFIG.PCW_EN_PJTAG {0} \ 349 | CONFIG.PCW_EN_PTP_ENET0 {0} \ 350 | CONFIG.PCW_EN_PTP_ENET1 {0} \ 351 | CONFIG.PCW_EN_QSPI {1} \ 352 | CONFIG.PCW_EN_RST0_PORT {1} \ 353 | CONFIG.PCW_EN_RST1_PORT {0} \ 354 | CONFIG.PCW_EN_RST2_PORT {0} \ 355 | CONFIG.PCW_EN_RST3_PORT {0} \ 356 | CONFIG.PCW_EN_SDIO0 {1} \ 357 | CONFIG.PCW_EN_SDIO1 {0} \ 358 | CONFIG.PCW_EN_SMC {0} \ 359 | CONFIG.PCW_EN_SPI0 {0} \ 360 | CONFIG.PCW_EN_SPI1 {0} \ 361 | CONFIG.PCW_EN_TRACE {0} \ 362 | CONFIG.PCW_EN_TTC0 {0} \ 363 | CONFIG.PCW_EN_TTC1 {0} \ 364 | CONFIG.PCW_EN_UART0 {1} \ 365 | CONFIG.PCW_EN_UART1 {0} \ 366 | CONFIG.PCW_EN_USB0 {1} \ 367 | CONFIG.PCW_EN_USB1 {0} \ 368 | CONFIG.PCW_EN_WDT {0} \ 369 | CONFIG.PCW_FCLK0_PERIPHERAL_CLKSRC {IO PLL} \ 370 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ 371 | CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ 372 | CONFIG.PCW_FCLK1_PERIPHERAL_CLKSRC {IO PLL} \ 373 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {1} \ 374 | CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {1} \ 375 | CONFIG.PCW_FCLK2_PERIPHERAL_CLKSRC {IO PLL} \ 376 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR0 {1} \ 377 | CONFIG.PCW_FCLK2_PERIPHERAL_DIVISOR1 {1} \ 378 | CONFIG.PCW_FCLK3_PERIPHERAL_CLKSRC {IO PLL} \ 379 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR0 {1} \ 380 | CONFIG.PCW_FCLK3_PERIPHERAL_DIVISOR1 {1} \ 381 | CONFIG.PCW_FCLK_CLK0_BUF {TRUE} \ 382 | CONFIG.PCW_FCLK_CLK1_BUF {FALSE} \ 383 | CONFIG.PCW_FCLK_CLK2_BUF {FALSE} \ 384 | CONFIG.PCW_FCLK_CLK3_BUF {FALSE} \ 385 | CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ 386 | CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {50} \ 387 | CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {50} \ 388 | CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {50} \ 389 | CONFIG.PCW_FPGA_FCLK0_ENABLE {1} \ 390 | CONFIG.PCW_FPGA_FCLK1_ENABLE {0} \ 391 | CONFIG.PCW_FPGA_FCLK2_ENABLE {0} \ 392 | CONFIG.PCW_FPGA_FCLK3_ENABLE {0} \ 393 | CONFIG.PCW_GPIO_BASEADDR {0xE000A000} \ 394 | CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {0} \ 395 | CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {64} \ 396 | CONFIG.PCW_GPIO_HIGHADDR {0xE000AFFF} \ 397 | CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ 398 | CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ 399 | CONFIG.PCW_GPIO_PERIPHERAL_ENABLE {0} \ 400 | CONFIG.PCW_I2C0_BASEADDR {0xE0004000} \ 401 | CONFIG.PCW_I2C0_HIGHADDR {0xE0004FFF} \ 402 | CONFIG.PCW_I2C0_RESET_ENABLE {0} \ 403 | CONFIG.PCW_I2C1_BASEADDR {0xE0005000} \ 404 | CONFIG.PCW_I2C1_HIGHADDR {0xE0005FFF} \ 405 | CONFIG.PCW_I2C1_RESET_ENABLE {0} \ 406 | CONFIG.PCW_I2C_PERIPHERAL_FREQMHZ {25} \ 407 | CONFIG.PCW_I2C_RESET_ENABLE {1} \ 408 | CONFIG.PCW_I2C_RESET_POLARITY {Active Low} \ 409 | CONFIG.PCW_IMPORT_BOARD_PRESET {None} \ 410 | CONFIG.PCW_INCLUDE_ACP_TRANS_CHECK {0} \ 411 | CONFIG.PCW_INCLUDE_TRACE_BUFFER {0} \ 412 | CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ 413 | CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ 414 | CONFIG.PCW_IRQ_F2P_INTR {0} \ 415 | CONFIG.PCW_IRQ_F2P_MODE {DIRECT} \ 416 | CONFIG.PCW_MIO_0_DIRECTION {inout} \ 417 | CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ 418 | CONFIG.PCW_MIO_0_PULLUP {enabled} \ 419 | CONFIG.PCW_MIO_0_SLEW {slow} \ 420 | CONFIG.PCW_MIO_10_DIRECTION {inout} \ 421 | CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ 422 | CONFIG.PCW_MIO_10_PULLUP {enabled} \ 423 | CONFIG.PCW_MIO_10_SLEW {slow} \ 424 | CONFIG.PCW_MIO_11_DIRECTION {inout} \ 425 | CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ 426 | CONFIG.PCW_MIO_11_PULLUP {enabled} \ 427 | CONFIG.PCW_MIO_11_SLEW {slow} \ 428 | CONFIG.PCW_MIO_12_DIRECTION {inout} \ 429 | CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ 430 | CONFIG.PCW_MIO_12_PULLUP {enabled} \ 431 | CONFIG.PCW_MIO_12_SLEW {slow} \ 432 | CONFIG.PCW_MIO_13_DIRECTION {inout} \ 433 | CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ 434 | CONFIG.PCW_MIO_13_PULLUP {enabled} \ 435 | CONFIG.PCW_MIO_13_SLEW {slow} \ 436 | CONFIG.PCW_MIO_14_DIRECTION {in} \ 437 | CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ 438 | CONFIG.PCW_MIO_14_PULLUP {enabled} \ 439 | CONFIG.PCW_MIO_14_SLEW {slow} \ 440 | CONFIG.PCW_MIO_15_DIRECTION {out} \ 441 | CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ 442 | CONFIG.PCW_MIO_15_PULLUP {enabled} \ 443 | CONFIG.PCW_MIO_15_SLEW {slow} \ 444 | CONFIG.PCW_MIO_16_DIRECTION {out} \ 445 | CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ 446 | CONFIG.PCW_MIO_16_PULLUP {enabled} \ 447 | CONFIG.PCW_MIO_16_SLEW {slow} \ 448 | CONFIG.PCW_MIO_17_DIRECTION {out} \ 449 | CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ 450 | CONFIG.PCW_MIO_17_PULLUP {enabled} \ 451 | CONFIG.PCW_MIO_17_SLEW {slow} \ 452 | CONFIG.PCW_MIO_18_DIRECTION {out} \ 453 | CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ 454 | CONFIG.PCW_MIO_18_PULLUP {enabled} \ 455 | CONFIG.PCW_MIO_18_SLEW {slow} \ 456 | CONFIG.PCW_MIO_19_DIRECTION {out} \ 457 | CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ 458 | CONFIG.PCW_MIO_19_PULLUP {enabled} \ 459 | CONFIG.PCW_MIO_19_SLEW {slow} \ 460 | CONFIG.PCW_MIO_1_DIRECTION {out} \ 461 | CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ 462 | CONFIG.PCW_MIO_1_PULLUP {enabled} \ 463 | CONFIG.PCW_MIO_1_SLEW {slow} \ 464 | CONFIG.PCW_MIO_20_DIRECTION {out} \ 465 | CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ 466 | CONFIG.PCW_MIO_20_PULLUP {enabled} \ 467 | CONFIG.PCW_MIO_20_SLEW {slow} \ 468 | CONFIG.PCW_MIO_21_DIRECTION {out} \ 469 | CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ 470 | CONFIG.PCW_MIO_21_PULLUP {enabled} \ 471 | CONFIG.PCW_MIO_21_SLEW {slow} \ 472 | CONFIG.PCW_MIO_22_DIRECTION {in} \ 473 | CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ 474 | CONFIG.PCW_MIO_22_PULLUP {enabled} \ 475 | CONFIG.PCW_MIO_22_SLEW {slow} \ 476 | CONFIG.PCW_MIO_23_DIRECTION {in} \ 477 | CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ 478 | CONFIG.PCW_MIO_23_PULLUP {enabled} \ 479 | CONFIG.PCW_MIO_23_SLEW {slow} \ 480 | CONFIG.PCW_MIO_24_DIRECTION {in} \ 481 | CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ 482 | CONFIG.PCW_MIO_24_PULLUP {enabled} \ 483 | CONFIG.PCW_MIO_24_SLEW {slow} \ 484 | CONFIG.PCW_MIO_25_DIRECTION {in} \ 485 | CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ 486 | CONFIG.PCW_MIO_25_PULLUP {enabled} \ 487 | CONFIG.PCW_MIO_25_SLEW {slow} \ 488 | CONFIG.PCW_MIO_26_DIRECTION {in} \ 489 | CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ 490 | CONFIG.PCW_MIO_26_PULLUP {enabled} \ 491 | CONFIG.PCW_MIO_26_SLEW {slow} \ 492 | CONFIG.PCW_MIO_27_DIRECTION {in} \ 493 | CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ 494 | CONFIG.PCW_MIO_27_PULLUP {enabled} \ 495 | CONFIG.PCW_MIO_27_SLEW {slow} \ 496 | CONFIG.PCW_MIO_28_DIRECTION {inout} \ 497 | CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ 498 | CONFIG.PCW_MIO_28_PULLUP {enabled} \ 499 | CONFIG.PCW_MIO_28_SLEW {slow} \ 500 | CONFIG.PCW_MIO_29_DIRECTION {in} \ 501 | CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ 502 | CONFIG.PCW_MIO_29_PULLUP {enabled} \ 503 | CONFIG.PCW_MIO_29_SLEW {slow} \ 504 | CONFIG.PCW_MIO_2_DIRECTION {inout} \ 505 | CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ 506 | CONFIG.PCW_MIO_2_PULLUP {disabled} \ 507 | CONFIG.PCW_MIO_2_SLEW {slow} \ 508 | CONFIG.PCW_MIO_30_DIRECTION {out} \ 509 | CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ 510 | CONFIG.PCW_MIO_30_PULLUP {enabled} \ 511 | CONFIG.PCW_MIO_30_SLEW {slow} \ 512 | CONFIG.PCW_MIO_31_DIRECTION {in} \ 513 | CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ 514 | CONFIG.PCW_MIO_31_PULLUP {enabled} \ 515 | CONFIG.PCW_MIO_31_SLEW {slow} \ 516 | CONFIG.PCW_MIO_32_DIRECTION {inout} \ 517 | CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ 518 | CONFIG.PCW_MIO_32_PULLUP {enabled} \ 519 | CONFIG.PCW_MIO_32_SLEW {slow} \ 520 | CONFIG.PCW_MIO_33_DIRECTION {inout} \ 521 | CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ 522 | CONFIG.PCW_MIO_33_PULLUP {enabled} \ 523 | CONFIG.PCW_MIO_33_SLEW {slow} \ 524 | CONFIG.PCW_MIO_34_DIRECTION {inout} \ 525 | CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ 526 | CONFIG.PCW_MIO_34_PULLUP {enabled} \ 527 | CONFIG.PCW_MIO_34_SLEW {slow} \ 528 | CONFIG.PCW_MIO_35_DIRECTION {inout} \ 529 | CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ 530 | CONFIG.PCW_MIO_35_PULLUP {enabled} \ 531 | CONFIG.PCW_MIO_35_SLEW {slow} \ 532 | CONFIG.PCW_MIO_36_DIRECTION {in} \ 533 | CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ 534 | CONFIG.PCW_MIO_36_PULLUP {enabled} \ 535 | CONFIG.PCW_MIO_36_SLEW {slow} \ 536 | CONFIG.PCW_MIO_37_DIRECTION {inout} \ 537 | CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ 538 | CONFIG.PCW_MIO_37_PULLUP {enabled} \ 539 | CONFIG.PCW_MIO_37_SLEW {slow} \ 540 | CONFIG.PCW_MIO_38_DIRECTION {inout} \ 541 | CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ 542 | CONFIG.PCW_MIO_38_PULLUP {enabled} \ 543 | CONFIG.PCW_MIO_38_SLEW {slow} \ 544 | CONFIG.PCW_MIO_39_DIRECTION {inout} \ 545 | CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ 546 | CONFIG.PCW_MIO_39_PULLUP {enabled} \ 547 | CONFIG.PCW_MIO_39_SLEW {slow} \ 548 | CONFIG.PCW_MIO_3_DIRECTION {inout} \ 549 | CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ 550 | CONFIG.PCW_MIO_3_PULLUP {disabled} \ 551 | CONFIG.PCW_MIO_3_SLEW {slow} \ 552 | CONFIG.PCW_MIO_40_DIRECTION {inout} \ 553 | CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ 554 | CONFIG.PCW_MIO_40_PULLUP {enabled} \ 555 | CONFIG.PCW_MIO_40_SLEW {slow} \ 556 | CONFIG.PCW_MIO_41_DIRECTION {inout} \ 557 | CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ 558 | CONFIG.PCW_MIO_41_PULLUP {enabled} \ 559 | CONFIG.PCW_MIO_41_SLEW {slow} \ 560 | CONFIG.PCW_MIO_42_DIRECTION {inout} \ 561 | CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ 562 | CONFIG.PCW_MIO_42_PULLUP {enabled} \ 563 | CONFIG.PCW_MIO_42_SLEW {slow} \ 564 | CONFIG.PCW_MIO_43_DIRECTION {inout} \ 565 | CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ 566 | CONFIG.PCW_MIO_43_PULLUP {enabled} \ 567 | CONFIG.PCW_MIO_43_SLEW {slow} \ 568 | CONFIG.PCW_MIO_44_DIRECTION {inout} \ 569 | CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ 570 | CONFIG.PCW_MIO_44_PULLUP {enabled} \ 571 | CONFIG.PCW_MIO_44_SLEW {slow} \ 572 | CONFIG.PCW_MIO_45_DIRECTION {inout} \ 573 | CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ 574 | CONFIG.PCW_MIO_45_PULLUP {enabled} \ 575 | CONFIG.PCW_MIO_45_SLEW {slow} \ 576 | CONFIG.PCW_MIO_46_DIRECTION {out} \ 577 | CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ 578 | CONFIG.PCW_MIO_46_PULLUP {enabled} \ 579 | CONFIG.PCW_MIO_46_SLEW {slow} \ 580 | CONFIG.PCW_MIO_47_DIRECTION {in} \ 581 | CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ 582 | CONFIG.PCW_MIO_47_PULLUP {enabled} \ 583 | CONFIG.PCW_MIO_47_SLEW {slow} \ 584 | CONFIG.PCW_MIO_48_DIRECTION {inout} \ 585 | CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ 586 | CONFIG.PCW_MIO_48_PULLUP {enabled} \ 587 | CONFIG.PCW_MIO_48_SLEW {slow} \ 588 | CONFIG.PCW_MIO_49_DIRECTION {inout} \ 589 | CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ 590 | CONFIG.PCW_MIO_49_PULLUP {enabled} \ 591 | CONFIG.PCW_MIO_49_SLEW {slow} \ 592 | CONFIG.PCW_MIO_4_DIRECTION {inout} \ 593 | CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ 594 | CONFIG.PCW_MIO_4_PULLUP {disabled} \ 595 | CONFIG.PCW_MIO_4_SLEW {slow} \ 596 | CONFIG.PCW_MIO_50_DIRECTION {inout} \ 597 | CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ 598 | CONFIG.PCW_MIO_50_PULLUP {enabled} \ 599 | CONFIG.PCW_MIO_50_SLEW {slow} \ 600 | CONFIG.PCW_MIO_51_DIRECTION {inout} \ 601 | CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ 602 | CONFIG.PCW_MIO_51_PULLUP {enabled} \ 603 | CONFIG.PCW_MIO_51_SLEW {slow} \ 604 | CONFIG.PCW_MIO_52_DIRECTION {out} \ 605 | CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ 606 | CONFIG.PCW_MIO_52_PULLUP {enabled} \ 607 | CONFIG.PCW_MIO_52_SLEW {slow} \ 608 | CONFIG.PCW_MIO_53_DIRECTION {inout} \ 609 | CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ 610 | CONFIG.PCW_MIO_53_PULLUP {enabled} \ 611 | CONFIG.PCW_MIO_53_SLEW {slow} \ 612 | CONFIG.PCW_MIO_5_DIRECTION {inout} \ 613 | CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ 614 | CONFIG.PCW_MIO_5_PULLUP {disabled} \ 615 | CONFIG.PCW_MIO_5_SLEW {slow} \ 616 | CONFIG.PCW_MIO_6_DIRECTION {out} \ 617 | CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ 618 | CONFIG.PCW_MIO_6_PULLUP {disabled} \ 619 | CONFIG.PCW_MIO_6_SLEW {slow} \ 620 | CONFIG.PCW_MIO_7_DIRECTION {out} \ 621 | CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ 622 | CONFIG.PCW_MIO_7_PULLUP {disabled} \ 623 | CONFIG.PCW_MIO_7_SLEW {slow} \ 624 | CONFIG.PCW_MIO_8_DIRECTION {out} \ 625 | CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ 626 | CONFIG.PCW_MIO_8_PULLUP {disabled} \ 627 | CONFIG.PCW_MIO_8_SLEW {slow} \ 628 | CONFIG.PCW_MIO_9_DIRECTION {out} \ 629 | CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ 630 | CONFIG.PCW_MIO_9_PULLUP {enabled} \ 631 | CONFIG.PCW_MIO_9_SLEW {slow} \ 632 | CONFIG.PCW_MIO_PRIMITIVE {54} \ 633 | CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#USB Reset#SD 0#GPIO#GPIO#GPIO#GPIO#Enet 0#Enet 0} \ 634 | CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#reset#cd#gpio[48]#gpio[49]#gpio[50]#gpio[51]#mdc#mdio} \ 635 | CONFIG.PCW_M_AXI_GP0_ENABLE_STATIC_REMAP {0} \ 636 | CONFIG.PCW_M_AXI_GP0_ID_WIDTH {12} \ 637 | CONFIG.PCW_M_AXI_GP0_SUPPORT_NARROW_BURST {0} \ 638 | CONFIG.PCW_M_AXI_GP0_THREAD_ID_WIDTH {12} \ 639 | CONFIG.PCW_M_AXI_GP1_ENABLE_STATIC_REMAP {0} \ 640 | CONFIG.PCW_M_AXI_GP1_ID_WIDTH {12} \ 641 | CONFIG.PCW_M_AXI_GP1_SUPPORT_NARROW_BURST {0} \ 642 | CONFIG.PCW_M_AXI_GP1_THREAD_ID_WIDTH {12} \ 643 | CONFIG.PCW_NAND_CYCLES_T_AR {1} \ 644 | CONFIG.PCW_NAND_CYCLES_T_CLR {1} \ 645 | CONFIG.PCW_NAND_CYCLES_T_RC {11} \ 646 | CONFIG.PCW_NAND_CYCLES_T_REA {1} \ 647 | CONFIG.PCW_NAND_CYCLES_T_RR {1} \ 648 | CONFIG.PCW_NAND_CYCLES_T_WC {11} \ 649 | CONFIG.PCW_NAND_CYCLES_T_WP {1} \ 650 | CONFIG.PCW_NAND_GRP_D8_ENABLE {0} \ 651 | CONFIG.PCW_NAND_PERIPHERAL_ENABLE {0} \ 652 | CONFIG.PCW_NOR_CS0_T_CEOE {1} \ 653 | CONFIG.PCW_NOR_CS0_T_PC {1} \ 654 | CONFIG.PCW_NOR_CS0_T_RC {11} \ 655 | CONFIG.PCW_NOR_CS0_T_TR {1} \ 656 | CONFIG.PCW_NOR_CS0_T_WC {11} \ 657 | CONFIG.PCW_NOR_CS0_T_WP {1} \ 658 | CONFIG.PCW_NOR_CS0_WE_TIME {0} \ 659 | CONFIG.PCW_NOR_CS1_T_CEOE {1} \ 660 | CONFIG.PCW_NOR_CS1_T_PC {1} \ 661 | CONFIG.PCW_NOR_CS1_T_RC {11} \ 662 | CONFIG.PCW_NOR_CS1_T_TR {1} \ 663 | CONFIG.PCW_NOR_CS1_T_WC {11} \ 664 | CONFIG.PCW_NOR_CS1_T_WP {1} \ 665 | CONFIG.PCW_NOR_CS1_WE_TIME {0} \ 666 | CONFIG.PCW_NOR_GRP_A25_ENABLE {0} \ 667 | CONFIG.PCW_NOR_GRP_CS0_ENABLE {0} \ 668 | CONFIG.PCW_NOR_GRP_CS1_ENABLE {0} \ 669 | CONFIG.PCW_NOR_GRP_SRAM_CS0_ENABLE {0} \ 670 | CONFIG.PCW_NOR_GRP_SRAM_CS1_ENABLE {0} \ 671 | CONFIG.PCW_NOR_GRP_SRAM_INT_ENABLE {0} \ 672 | CONFIG.PCW_NOR_PERIPHERAL_ENABLE {0} \ 673 | CONFIG.PCW_NOR_SRAM_CS0_T_CEOE {1} \ 674 | CONFIG.PCW_NOR_SRAM_CS0_T_PC {1} \ 675 | CONFIG.PCW_NOR_SRAM_CS0_T_RC {11} \ 676 | CONFIG.PCW_NOR_SRAM_CS0_T_TR {1} \ 677 | CONFIG.PCW_NOR_SRAM_CS0_T_WC {11} \ 678 | CONFIG.PCW_NOR_SRAM_CS0_T_WP {1} \ 679 | CONFIG.PCW_NOR_SRAM_CS0_WE_TIME {0} \ 680 | CONFIG.PCW_NOR_SRAM_CS1_T_CEOE {1} \ 681 | CONFIG.PCW_NOR_SRAM_CS1_T_PC {1} \ 682 | CONFIG.PCW_NOR_SRAM_CS1_T_RC {11} \ 683 | CONFIG.PCW_NOR_SRAM_CS1_T_TR {1} \ 684 | CONFIG.PCW_NOR_SRAM_CS1_T_WC {11} \ 685 | CONFIG.PCW_NOR_SRAM_CS1_T_WP {1} \ 686 | CONFIG.PCW_NOR_SRAM_CS1_WE_TIME {0} \ 687 | CONFIG.PCW_OVERRIDE_BASIC_CLOCK {0} \ 688 | CONFIG.PCW_P2F_CAN0_INTR {0} \ 689 | CONFIG.PCW_P2F_CAN1_INTR {0} \ 690 | CONFIG.PCW_P2F_CTI_INTR {0} \ 691 | CONFIG.PCW_P2F_DMAC0_INTR {0} \ 692 | CONFIG.PCW_P2F_DMAC1_INTR {0} \ 693 | CONFIG.PCW_P2F_DMAC2_INTR {0} \ 694 | CONFIG.PCW_P2F_DMAC3_INTR {0} \ 695 | CONFIG.PCW_P2F_DMAC4_INTR {0} \ 696 | CONFIG.PCW_P2F_DMAC5_INTR {0} \ 697 | CONFIG.PCW_P2F_DMAC6_INTR {0} \ 698 | CONFIG.PCW_P2F_DMAC7_INTR {0} \ 699 | CONFIG.PCW_P2F_DMAC_ABORT_INTR {0} \ 700 | CONFIG.PCW_P2F_ENET0_INTR {0} \ 701 | CONFIG.PCW_P2F_ENET1_INTR {0} \ 702 | CONFIG.PCW_P2F_GPIO_INTR {0} \ 703 | CONFIG.PCW_P2F_I2C0_INTR {0} \ 704 | CONFIG.PCW_P2F_I2C1_INTR {0} \ 705 | CONFIG.PCW_P2F_QSPI_INTR {0} \ 706 | CONFIG.PCW_P2F_SDIO0_INTR {0} \ 707 | CONFIG.PCW_P2F_SDIO1_INTR {0} \ 708 | CONFIG.PCW_P2F_SMC_INTR {0} \ 709 | CONFIG.PCW_P2F_SPI0_INTR {0} \ 710 | CONFIG.PCW_P2F_SPI1_INTR {0} \ 711 | CONFIG.PCW_P2F_UART0_INTR {0} \ 712 | CONFIG.PCW_P2F_UART1_INTR {0} \ 713 | CONFIG.PCW_P2F_USB0_INTR {0} \ 714 | CONFIG.PCW_P2F_USB1_INTR {0} \ 715 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.279} \ 716 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.260} \ 717 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ 718 | CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ 719 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {-0.051} \ 720 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {-0.006} \ 721 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 722 | CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 723 | CONFIG.PCW_PACKAGE_NAME {clg400} \ 724 | CONFIG.PCW_PCAP_PERIPHERAL_CLKSRC {IO PLL} \ 725 | CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ 726 | CONFIG.PCW_PCAP_PERIPHERAL_FREQMHZ {200} \ 727 | CONFIG.PCW_PERIPHERAL_BOARD_PRESET {None} \ 728 | CONFIG.PCW_PLL_BYPASSMODE_ENABLE {0} \ 729 | CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 3.3V} \ 730 | CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ 731 | CONFIG.PCW_PS7_SI_REV {PRODUCTION} \ 732 | CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ 733 | CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ 734 | CONFIG.PCW_QSPI_GRP_IO1_ENABLE {0} \ 735 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ 736 | CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ 737 | CONFIG.PCW_QSPI_GRP_SS1_ENABLE {0} \ 738 | CONFIG.PCW_QSPI_INTERNAL_HIGHADDRESS {0xFCFFFFFF} \ 739 | CONFIG.PCW_QSPI_PERIPHERAL_CLKSRC {IO PLL} \ 740 | CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ 741 | CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ 742 | CONFIG.PCW_QSPI_PERIPHERAL_FREQMHZ {200} \ 743 | CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ 744 | CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ 745 | CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ 746 | CONFIG.PCW_SD0_GRP_POW_ENABLE {0} \ 747 | CONFIG.PCW_SD0_GRP_WP_ENABLE {0} \ 748 | CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ 749 | CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ 750 | CONFIG.PCW_SD1_GRP_CD_ENABLE {0} \ 751 | CONFIG.PCW_SD1_GRP_POW_ENABLE {0} \ 752 | CONFIG.PCW_SD1_GRP_WP_ENABLE {0} \ 753 | CONFIG.PCW_SD1_PERIPHERAL_ENABLE {0} \ 754 | CONFIG.PCW_SDIO0_BASEADDR {0xE0100000} \ 755 | CONFIG.PCW_SDIO0_HIGHADDR {0xE0100FFF} \ 756 | CONFIG.PCW_SDIO1_BASEADDR {0xE0101000} \ 757 | CONFIG.PCW_SDIO1_HIGHADDR {0xE0101FFF} \ 758 | CONFIG.PCW_SDIO_PERIPHERAL_CLKSRC {IO PLL} \ 759 | CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ 760 | CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ 761 | CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ 762 | CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ 763 | CONFIG.PCW_SMC_CYCLE_T0 {NA} \ 764 | CONFIG.PCW_SMC_CYCLE_T1 {NA} \ 765 | CONFIG.PCW_SMC_CYCLE_T2 {NA} \ 766 | CONFIG.PCW_SMC_CYCLE_T3 {NA} \ 767 | CONFIG.PCW_SMC_CYCLE_T4 {NA} \ 768 | CONFIG.PCW_SMC_CYCLE_T5 {NA} \ 769 | CONFIG.PCW_SMC_CYCLE_T6 {NA} \ 770 | CONFIG.PCW_SMC_PERIPHERAL_CLKSRC {IO PLL} \ 771 | CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ 772 | CONFIG.PCW_SMC_PERIPHERAL_FREQMHZ {100} \ 773 | CONFIG.PCW_SMC_PERIPHERAL_VALID {0} \ 774 | CONFIG.PCW_SPI0_BASEADDR {0xE0006000} \ 775 | CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ 776 | CONFIG.PCW_SPI0_GRP_SS1_ENABLE {0} \ 777 | CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ 778 | CONFIG.PCW_SPI0_HIGHADDR {0xE0006FFF} \ 779 | CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {0} \ 780 | CONFIG.PCW_SPI1_BASEADDR {0xE0007000} \ 781 | CONFIG.PCW_SPI1_GRP_SS0_ENABLE {0} \ 782 | CONFIG.PCW_SPI1_GRP_SS1_ENABLE {0} \ 783 | CONFIG.PCW_SPI1_GRP_SS2_ENABLE {0} \ 784 | CONFIG.PCW_SPI1_HIGHADDR {0xE0007FFF} \ 785 | CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {0} \ 786 | CONFIG.PCW_SPI_PERIPHERAL_CLKSRC {IO PLL} \ 787 | CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {1} \ 788 | CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ 789 | CONFIG.PCW_SPI_PERIPHERAL_VALID {0} \ 790 | CONFIG.PCW_S_AXI_ACP_ARUSER_VAL {31} \ 791 | CONFIG.PCW_S_AXI_ACP_AWUSER_VAL {31} \ 792 | CONFIG.PCW_S_AXI_ACP_ID_WIDTH {3} \ 793 | CONFIG.PCW_S_AXI_GP0_ID_WIDTH {6} \ 794 | CONFIG.PCW_S_AXI_GP1_ID_WIDTH {6} \ 795 | CONFIG.PCW_S_AXI_HP0_DATA_WIDTH {64} \ 796 | CONFIG.PCW_S_AXI_HP0_ID_WIDTH {6} \ 797 | CONFIG.PCW_S_AXI_HP1_DATA_WIDTH {64} \ 798 | CONFIG.PCW_S_AXI_HP1_ID_WIDTH {6} \ 799 | CONFIG.PCW_S_AXI_HP2_DATA_WIDTH {64} \ 800 | CONFIG.PCW_S_AXI_HP2_ID_WIDTH {6} \ 801 | CONFIG.PCW_S_AXI_HP3_DATA_WIDTH {64} \ 802 | CONFIG.PCW_S_AXI_HP3_ID_WIDTH {6} \ 803 | CONFIG.PCW_TPIU_PERIPHERAL_CLKSRC {External} \ 804 | CONFIG.PCW_TPIU_PERIPHERAL_DIVISOR0 {1} \ 805 | CONFIG.PCW_TPIU_PERIPHERAL_FREQMHZ {200} \ 806 | CONFIG.PCW_TRACE_BUFFER_CLOCK_DELAY {12} \ 807 | CONFIG.PCW_TRACE_BUFFER_FIFO_SIZE {128} \ 808 | CONFIG.PCW_TRACE_PIPELINE_WIDTH {8} \ 809 | CONFIG.PCW_TTC0_BASEADDR {0xE0104000} \ 810 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 811 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_DIVISOR0 {1} \ 812 | CONFIG.PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 813 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 814 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_DIVISOR0 {1} \ 815 | CONFIG.PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 816 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 817 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_DIVISOR0 {1} \ 818 | CONFIG.PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 819 | CONFIG.PCW_TTC0_HIGHADDR {0xE0104fff} \ 820 | CONFIG.PCW_TTC1_BASEADDR {0xE0105000} \ 821 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_CLKSRC {CPU_1X} \ 822 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_DIVISOR0 {1} \ 823 | CONFIG.PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ {133.333333} \ 824 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_CLKSRC {CPU_1X} \ 825 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_DIVISOR0 {1} \ 826 | CONFIG.PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ {133.333333} \ 827 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_CLKSRC {CPU_1X} \ 828 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_DIVISOR0 {1} \ 829 | CONFIG.PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ {133.333333} \ 830 | CONFIG.PCW_TTC1_HIGHADDR {0xE0105fff} \ 831 | CONFIG.PCW_TTC_PERIPHERAL_FREQMHZ {50} \ 832 | CONFIG.PCW_UART0_BASEADDR {0xE0000000} \ 833 | CONFIG.PCW_UART0_BAUD_RATE {115200} \ 834 | CONFIG.PCW_UART0_GRP_FULL_ENABLE {0} \ 835 | CONFIG.PCW_UART0_HIGHADDR {0xE0000FFF} \ 836 | CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ 837 | CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ 838 | CONFIG.PCW_UART1_BASEADDR {0xE0001000} \ 839 | CONFIG.PCW_UART1_BAUD_RATE {115200} \ 840 | CONFIG.PCW_UART1_GRP_FULL_ENABLE {0} \ 841 | CONFIG.PCW_UART1_HIGHADDR {0xE0001FFF} \ 842 | CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \ 843 | CONFIG.PCW_UART_PERIPHERAL_CLKSRC {IO PLL} \ 844 | CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ 845 | CONFIG.PCW_UART_PERIPHERAL_FREQMHZ {100} \ 846 | CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ 847 | CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ 848 | CONFIG.PCW_UIPARAM_DDR_ADV_ENABLE {0} \ 849 | CONFIG.PCW_UIPARAM_DDR_AL {0} \ 850 | CONFIG.PCW_UIPARAM_DDR_BANK_ADDR_COUNT {3} \ 851 | CONFIG.PCW_UIPARAM_DDR_BL {8} \ 852 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.279} \ 853 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.260} \ 854 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ 855 | CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ 856 | CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ 857 | CONFIG.PCW_UIPARAM_DDR_CL {7} \ 858 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {27.95} \ 859 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ 860 | CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY {160} \ 861 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {27.95} \ 862 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ 863 | CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY {160} \ 864 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM {0} \ 865 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ 866 | CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY {160} \ 867 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM {0} \ 868 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ 869 | CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY {160} \ 870 | CONFIG.PCW_UIPARAM_DDR_CLOCK_STOP_EN {0} \ 871 | CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {10} \ 872 | CONFIG.PCW_UIPARAM_DDR_CWL {6} \ 873 | CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ 874 | CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {32.14} \ 875 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ 876 | CONFIG.PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY {160} \ 877 | CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {31.12} \ 878 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ 879 | CONFIG.PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY {160} \ 880 | CONFIG.PCW_UIPARAM_DDR_DQS_2_LENGTH_MM {0} \ 881 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ 882 | CONFIG.PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY {160} \ 883 | CONFIG.PCW_UIPARAM_DDR_DQS_3_LENGTH_MM {0} \ 884 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ 885 | CONFIG.PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY {160} \ 886 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {-0.051} \ 887 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {-0.006} \ 888 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ 889 | CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ 890 | CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {32.2} \ 891 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ 892 | CONFIG.PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY {160} \ 893 | CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {31.08} \ 894 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ 895 | CONFIG.PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY {160} \ 896 | CONFIG.PCW_UIPARAM_DDR_DQ_2_LENGTH_MM {0} \ 897 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ 898 | CONFIG.PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY {160} \ 899 | CONFIG.PCW_UIPARAM_DDR_DQ_3_LENGTH_MM {0} \ 900 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ 901 | CONFIG.PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY {160} \ 902 | CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ 903 | CONFIG.PCW_UIPARAM_DDR_ECC {Disabled} \ 904 | CONFIG.PCW_UIPARAM_DDR_ENABLE {1} \ 905 | CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ 906 | CONFIG.PCW_UIPARAM_DDR_HIGH_TEMP {Normal (0-85)} \ 907 | CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {DDR 3} \ 908 | CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ 909 | CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ 910 | CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {DDR3_1066F} \ 911 | CONFIG.PCW_UIPARAM_DDR_TRAIN_DATA_EYE {1} \ 912 | CONFIG.PCW_UIPARAM_DDR_TRAIN_READ_GATE {1} \ 913 | CONFIG.PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL {1} \ 914 | CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ 915 | CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {35.0} \ 916 | CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ 917 | CONFIG.PCW_UIPARAM_DDR_T_RCD {7} \ 918 | CONFIG.PCW_UIPARAM_DDR_T_RP {7} \ 919 | CONFIG.PCW_UIPARAM_DDR_USE_INTERNAL_VREF {0} \ 920 | CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NA} \ 921 | CONFIG.PCW_USB0_BASEADDR {0xE0102000} \ 922 | CONFIG.PCW_USB0_HIGHADDR {0xE0102fff} \ 923 | CONFIG.PCW_USB0_PERIPHERAL_ENABLE {1} \ 924 | CONFIG.PCW_USB0_PERIPHERAL_FREQMHZ {60} \ 925 | CONFIG.PCW_USB0_RESET_ENABLE {1} \ 926 | CONFIG.PCW_USB0_RESET_IO {MIO 46} \ 927 | CONFIG.PCW_USB0_USB0_IO {MIO 28 .. 39} \ 928 | CONFIG.PCW_USB1_BASEADDR {0xE0103000} \ 929 | CONFIG.PCW_USB1_HIGHADDR {0xE0103fff} \ 930 | CONFIG.PCW_USB1_PERIPHERAL_ENABLE {0} \ 931 | CONFIG.PCW_USB1_PERIPHERAL_FREQMHZ {60} \ 932 | CONFIG.PCW_USB1_RESET_ENABLE {0} \ 933 | CONFIG.PCW_USB_RESET_ENABLE {1} \ 934 | CONFIG.PCW_USB_RESET_POLARITY {Active Low} \ 935 | CONFIG.PCW_USB_RESET_SELECT {Share reset pin} \ 936 | CONFIG.PCW_USE_AXI_FABRIC_IDLE {0} \ 937 | CONFIG.PCW_USE_AXI_NONSECURE {0} \ 938 | CONFIG.PCW_USE_CORESIGHT {0} \ 939 | CONFIG.PCW_USE_CROSS_TRIGGER {0} \ 940 | CONFIG.PCW_USE_CR_FABRIC {1} \ 941 | CONFIG.PCW_USE_DDR_BYPASS {0} \ 942 | CONFIG.PCW_USE_DEBUG {0} \ 943 | CONFIG.PCW_USE_DEFAULT_ACP_USER_VAL {0} \ 944 | CONFIG.PCW_USE_DMA0 {0} \ 945 | CONFIG.PCW_USE_DMA1 {0} \ 946 | CONFIG.PCW_USE_DMA2 {0} \ 947 | CONFIG.PCW_USE_DMA3 {0} \ 948 | CONFIG.PCW_USE_EXPANDED_IOP {0} \ 949 | CONFIG.PCW_USE_EXPANDED_PS_SLCR_REGISTERS {0} \ 950 | CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \ 951 | CONFIG.PCW_USE_HIGH_OCM {0} \ 952 | CONFIG.PCW_USE_M_AXI_GP0 {1} \ 953 | CONFIG.PCW_USE_M_AXI_GP1 {0} \ 954 | CONFIG.PCW_USE_PROC_EVENT_BUS {0} \ 955 | CONFIG.PCW_USE_PS_SLCR_REGISTERS {0} \ 956 | CONFIG.PCW_USE_S_AXI_ACP {0} \ 957 | CONFIG.PCW_USE_S_AXI_GP0 {0} \ 958 | CONFIG.PCW_USE_S_AXI_GP1 {0} \ 959 | CONFIG.PCW_USE_S_AXI_HP0 {0} \ 960 | CONFIG.PCW_USE_S_AXI_HP1 {0} \ 961 | CONFIG.PCW_USE_S_AXI_HP2 {0} \ 962 | CONFIG.PCW_USE_S_AXI_HP3 {0} \ 963 | CONFIG.PCW_USE_TRACE {0} \ 964 | CONFIG.PCW_USE_TRACE_DATA_EDGE_DETECTOR {0} \ 965 | CONFIG.PCW_VALUE_SILVERSION {3} \ 966 | CONFIG.PCW_WDT_PERIPHERAL_CLKSRC {CPU_1X} \ 967 | CONFIG.PCW_WDT_PERIPHERAL_DIVISOR0 {1} \ 968 | CONFIG.PCW_WDT_PERIPHERAL_FREQMHZ {133.333333} \ 969 | ] $processing_system7_0 970 | 971 | # Create instance: ps7_0_axi_periph, and set properties 972 | set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] 973 | set_property -dict [ list \ 974 | CONFIG.NUM_MI {1} \ 975 | ] $ps7_0_axi_periph 976 | 977 | # Create instance: rst_ps7_0_100M, and set properties 978 | set rst_ps7_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_ps7_0_100M ] 979 | 980 | # Create instance: sort_0, and set properties 981 | set sort_0 [ create_bd_cell -type ip -vlnv xilinx.com:hls:sort:1.0 sort_0 ] 982 | 983 | set_property -dict [ list \ 984 | CONFIG.NUM_READ_OUTSTANDING {1} \ 985 | CONFIG.NUM_WRITE_OUTSTANDING {1} \ 986 | ] [get_bd_intf_pins /sort_0/s_axi_AXILiteS] 987 | 988 | # Create interface connections 989 | connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] 990 | connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] 991 | connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] 992 | connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] [get_bd_intf_pins sort_0/s_axi_AXILiteS] 993 | 994 | # Create port connections 995 | connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] [get_bd_pins sort_0/ap_clk] 996 | connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] 997 | connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] 998 | connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] [get_bd_pins sort_0/ap_rst_n] 999 | 1000 | # Create address segments 1001 | create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs sort_0/s_axi_AXILiteS/Reg] SEG_sort_0_Reg 1002 | 1003 | 1004 | # Restore current instance 1005 | current_bd_instance $oldCurInst 1006 | 1007 | save_bd_design 1008 | } 1009 | # End of create_root_design() 1010 | 1011 | 1012 | ################################################################## 1013 | # MAIN FLOW 1014 | ################################################################## 1015 | 1016 | create_root_design "" 1017 | 1018 | 1019 | -------------------------------------------------------------------------------- /tests/sort-core-test/notebook/.ipynb_checkpoints/sort-test-checkpoint.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": [ 11 | "\n", 12 | "require(['notebook/js/codecell'], function(codecell) {\n", 13 | " codecell.CodeCell.options_default.highlight_modes[\n", 14 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 15 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 16 | " Jupyter.notebook.get_cells().map(function(cell){\n", 17 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 18 | " });\n", 19 | "});\n" 20 | ] 21 | }, 22 | "metadata": {}, 23 | "output_type": "display_data" 24 | }, 25 | { 26 | "name": "stdout", 27 | "output_type": "stream", 28 | "text": [ 29 | "val : 10\n", 30 | "val : 9\n", 31 | "val : 8\n", 32 | "val : 7\n", 33 | "val : 6\n", 34 | "val : 5\n", 35 | "val : 4\n", 36 | "val : 3\n", 37 | "val : 2\n", 38 | "val : 1\n", 39 | "freq : 1\n", 40 | "freq : 2\n", 41 | "freq : 3\n", 42 | "freq : 4\n", 43 | "freq : 5\n", 44 | "freq : 6\n", 45 | "freq : 7\n", 46 | "freq : 8\n", 47 | "freq : 9\n", 48 | "freq : 10\n" 49 | ] 50 | } 51 | ], 52 | "source": [ 53 | "# AXILiteS\n", 54 | "# 0x0000 : Control signals\n", 55 | "# bit 0 - ap_start (Read/Write/COH)\n", 56 | "# bit 1 - ap_done (Read/COR)\n", 57 | "# bit 2 - ap_idle (Read)\n", 58 | "# bit 3 - ap_ready (Read)\n", 59 | "# bit 7 - auto_restart (Read/Write)\n", 60 | "# others - reserved\n", 61 | "# 0x0004 : Global Interrupt Enable Register\n", 62 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 63 | "# others - reserved\n", 64 | "# 0x0008 : IP Interrupt Enable Register (Read/Write)\n", 65 | "# bit 0 - Channel 0 (ap_done)\n", 66 | "# bit 1 - Channel 1 (ap_ready)\n", 67 | "# others - reserved\n", 68 | "# 0x000c : IP Interrupt Status Register (Read/TOW)\n", 69 | "# bit 0 - Channel 0 (ap_done)\n", 70 | "# bit 1 - Channel 1 (ap_ready)\n", 71 | "# others - reserved\n", 72 | "# 0x0c00 : Data signal of num_symbols\n", 73 | "# bit 31~0 - num_symbols[31:0] (Read/Write)\n", 74 | "# 0x0c04 : reserved\n", 75 | "# 0x0400 ~\n", 76 | "# 0x07ff : Memory 'in_value_V' (256 * 32b)\n", 77 | "# Word n : bit [31:0] - in_value_V[n]\n", 78 | "# 0x0800 ~\n", 79 | "# 0x0bff : Memory 'in_frequency_V' (256 * 32b)\n", 80 | "# Word n : bit [31:0] - in_frequency_V[n]\n", 81 | "# 0x1000 ~\n", 82 | "# 0x13ff : Memory 'out_value_V' (256 * 32b)\n", 83 | "# Word n : bit [31:0] - out_value_V[n]\n", 84 | "# 0x1400 ~\n", 85 | "# 0x17ff : Memory 'out_frequency_V' (256 * 32b)\n", 86 | "# Word n : bit [31:0] - out_frequency_V[n]\n", 87 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 88 | "\n", 89 | "from pynq import Overlay\n", 90 | "\n", 91 | "overlay = Overlay(\"../bitstream/sort-test.bit\")\n", 92 | "overlay.download()\n", 93 | "\n", 94 | "sort = overlay.sort_0\n", 95 | "\n", 96 | "# set symbol numbers\n", 97 | "sort.write(0x0c00, 10)\n", 98 | "\n", 99 | "# write register\n", 100 | "for i in range(10):\n", 101 | " sort.write(0x0400 + 4*i, i + 1)\n", 102 | "\n", 103 | "for i in range(10):\n", 104 | " sort.write(0x0800 + 4*i, 10 - i)\n", 105 | " \n", 106 | "# start\n", 107 | "sort.write(0x0000, 1)\n", 108 | "\n", 109 | "from time import sleep\n", 110 | "\n", 111 | "sleep(3)\n", 112 | "\n", 113 | "# read sorted value\n", 114 | "for i in range(10):\n", 115 | " print(\"val : \" + str(sort.read(0x1000 + 4*i)))\n", 116 | " \n", 117 | "for i in range(10):\n", 118 | " print(\"freq : \" + str(sort.read(0x1400 + 4*i)))\n", 119 | " " 120 | ] 121 | }, 122 | { 123 | "cell_type": "code", 124 | "execution_count": 2, 125 | "metadata": { 126 | "scrolled": true 127 | }, 128 | "outputs": [ 129 | { 130 | "name": "stdout", 131 | "output_type": "stream", 132 | "text": [ 133 | "val : 10\n", 134 | "val : 9\n", 135 | "val : 8\n", 136 | "val : 7\n", 137 | "val : 6\n", 138 | "val : 5\n", 139 | "val : 4\n", 140 | "val : 3\n", 141 | "val : 2\n", 142 | "val : 1\n", 143 | "val : 0\n", 144 | "val : 0\n", 145 | "val : 0\n", 146 | "val : 0\n", 147 | "val : 0\n", 148 | "val : 0\n", 149 | "val : 0\n", 150 | "val : 0\n", 151 | "val : 0\n", 152 | "val : 0\n", 153 | "freq : 1\n", 154 | "freq : 2\n", 155 | "freq : 3\n", 156 | "freq : 4\n", 157 | "freq : 5\n", 158 | "freq : 6\n", 159 | "freq : 7\n", 160 | "freq : 8\n", 161 | "freq : 9\n", 162 | "freq : 10\n", 163 | "freq : 0\n", 164 | "freq : 0\n", 165 | "freq : 0\n", 166 | "freq : 0\n", 167 | "freq : 0\n", 168 | "freq : 0\n", 169 | "freq : 0\n", 170 | "freq : 0\n", 171 | "freq : 0\n", 172 | "freq : 0\n" 173 | ] 174 | } 175 | ], 176 | "source": [ 177 | "# sort and shift upwards\n", 178 | "\n", 179 | "sort.write(0x0c00, 10)\n", 180 | "\n", 181 | "# write registers\n", 182 | "for i in range(20):\n", 183 | " if (i > 10):\n", 184 | " sort.write(0x0400 + 4*i, i - 10)\n", 185 | "\n", 186 | "for i in range(20):\n", 187 | " if (i > 10):\n", 188 | " sort.write(0x0800 + 4*i, 20 - i)\n", 189 | "# start\n", 190 | "sort.write(0x0000, 1)\n", 191 | "\n", 192 | "from time import sleep\n", 193 | "\n", 194 | "sleep(3)\n", 195 | "\n", 196 | "# read sorted value\n", 197 | "for i in range(20):\n", 198 | " print(\"val : \" + str(sort.read(0x1000 + 4*i)))\n", 199 | " \n", 200 | "for i in range(20):\n", 201 | " print(\"freq : \" + str(sort.read(0x1400 + 4*i)))\n", 202 | " " 203 | ] 204 | } 205 | ], 206 | "metadata": { 207 | "kernelspec": { 208 | "display_name": "Python 3", 209 | "language": "python", 210 | "name": "python3" 211 | }, 212 | "language_info": { 213 | "codemirror_mode": { 214 | "name": "ipython", 215 | "version": 3 216 | }, 217 | "file_extension": ".py", 218 | "mimetype": "text/x-python", 219 | "name": "python", 220 | "nbconvert_exporter": "python", 221 | "pygments_lexer": "ipython3", 222 | "version": "3.6.0" 223 | } 224 | }, 225 | "nbformat": 4, 226 | "nbformat_minor": 2 227 | } 228 | -------------------------------------------------------------------------------- /tests/sort-core-test/notebook/sort-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": [ 11 | "\n", 12 | "require(['notebook/js/codecell'], function(codecell) {\n", 13 | " codecell.CodeCell.options_default.highlight_modes[\n", 14 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 15 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 16 | " Jupyter.notebook.get_cells().map(function(cell){\n", 17 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 18 | " });\n", 19 | "});\n" 20 | ] 21 | }, 22 | "metadata": {}, 23 | "output_type": "display_data" 24 | }, 25 | { 26 | "name": "stdout", 27 | "output_type": "stream", 28 | "text": [ 29 | "val : 10\n", 30 | "val : 9\n", 31 | "val : 8\n", 32 | "val : 7\n", 33 | "val : 6\n", 34 | "val : 5\n", 35 | "val : 4\n", 36 | "val : 3\n", 37 | "val : 2\n", 38 | "val : 1\n", 39 | "freq : 1\n", 40 | "freq : 2\n", 41 | "freq : 3\n", 42 | "freq : 4\n", 43 | "freq : 5\n", 44 | "freq : 6\n", 45 | "freq : 7\n", 46 | "freq : 8\n", 47 | "freq : 9\n", 48 | "freq : 10\n" 49 | ] 50 | } 51 | ], 52 | "source": [ 53 | "# AXILiteS\n", 54 | "# 0x0000 : Control signals\n", 55 | "# bit 0 - ap_start (Read/Write/COH)\n", 56 | "# bit 1 - ap_done (Read/COR)\n", 57 | "# bit 2 - ap_idle (Read)\n", 58 | "# bit 3 - ap_ready (Read)\n", 59 | "# bit 7 - auto_restart (Read/Write)\n", 60 | "# others - reserved\n", 61 | "# 0x0004 : Global Interrupt Enable Register\n", 62 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 63 | "# others - reserved\n", 64 | "# 0x0008 : IP Interrupt Enable Register (Read/Write)\n", 65 | "# bit 0 - Channel 0 (ap_done)\n", 66 | "# bit 1 - Channel 1 (ap_ready)\n", 67 | "# others - reserved\n", 68 | "# 0x000c : IP Interrupt Status Register (Read/TOW)\n", 69 | "# bit 0 - Channel 0 (ap_done)\n", 70 | "# bit 1 - Channel 1 (ap_ready)\n", 71 | "# others - reserved\n", 72 | "# 0x0c00 : Data signal of num_symbols\n", 73 | "# bit 31~0 - num_symbols[31:0] (Read/Write)\n", 74 | "# 0x0c04 : reserved\n", 75 | "# 0x0400 ~\n", 76 | "# 0x07ff : Memory 'in_value_V' (256 * 32b)\n", 77 | "# Word n : bit [31:0] - in_value_V[n]\n", 78 | "# 0x0800 ~\n", 79 | "# 0x0bff : Memory 'in_frequency_V' (256 * 32b)\n", 80 | "# Word n : bit [31:0] - in_frequency_V[n]\n", 81 | "# 0x1000 ~\n", 82 | "# 0x13ff : Memory 'out_value_V' (256 * 32b)\n", 83 | "# Word n : bit [31:0] - out_value_V[n]\n", 84 | "# 0x1400 ~\n", 85 | "# 0x17ff : Memory 'out_frequency_V' (256 * 32b)\n", 86 | "# Word n : bit [31:0] - out_frequency_V[n]\n", 87 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 88 | "\n", 89 | "from pynq import Overlay\n", 90 | "\n", 91 | "overlay = Overlay(\"../bitstream/sort-test.bit\")\n", 92 | "overlay.download()\n", 93 | "\n", 94 | "sort = overlay.sort_0\n", 95 | "\n", 96 | "# set symbol numbers\n", 97 | "sort.write(0x0c00, 10)\n", 98 | "\n", 99 | "# write register\n", 100 | "for i in range(10):\n", 101 | " sort.write(0x0400 + 4*i, i + 1)\n", 102 | "\n", 103 | "for i in range(10):\n", 104 | " sort.write(0x0800 + 4*i, 10 - i)\n", 105 | " \n", 106 | "# start\n", 107 | "sort.write(0x0000, 1)\n", 108 | "\n", 109 | "from time import sleep\n", 110 | "\n", 111 | "sleep(3)\n", 112 | "\n", 113 | "# read sorted value\n", 114 | "for i in range(10):\n", 115 | " print(\"val : \" + str(sort.read(0x1000 + 4*i)))\n", 116 | " \n", 117 | "for i in range(10):\n", 118 | " print(\"freq : \" + str(sort.read(0x1400 + 4*i)))\n", 119 | " " 120 | ] 121 | }, 122 | { 123 | "cell_type": "code", 124 | "execution_count": 2, 125 | "metadata": { 126 | "scrolled": true 127 | }, 128 | "outputs": [ 129 | { 130 | "name": "stdout", 131 | "output_type": "stream", 132 | "text": [ 133 | "val : 10\n", 134 | "val : 9\n", 135 | "val : 8\n", 136 | "val : 7\n", 137 | "val : 6\n", 138 | "val : 5\n", 139 | "val : 4\n", 140 | "val : 3\n", 141 | "val : 2\n", 142 | "val : 1\n", 143 | "val : 0\n", 144 | "val : 0\n", 145 | "val : 0\n", 146 | "val : 0\n", 147 | "val : 0\n", 148 | "val : 0\n", 149 | "val : 0\n", 150 | "val : 0\n", 151 | "val : 0\n", 152 | "val : 0\n", 153 | "freq : 1\n", 154 | "freq : 2\n", 155 | "freq : 3\n", 156 | "freq : 4\n", 157 | "freq : 5\n", 158 | "freq : 6\n", 159 | "freq : 7\n", 160 | "freq : 8\n", 161 | "freq : 9\n", 162 | "freq : 10\n", 163 | "freq : 0\n", 164 | "freq : 0\n", 165 | "freq : 0\n", 166 | "freq : 0\n", 167 | "freq : 0\n", 168 | "freq : 0\n", 169 | "freq : 0\n", 170 | "freq : 0\n", 171 | "freq : 0\n", 172 | "freq : 0\n" 173 | ] 174 | } 175 | ], 176 | "source": [ 177 | "# sort and shift upwards\n", 178 | "\n", 179 | "sort.write(0x0c00, 10)\n", 180 | "\n", 181 | "# write registers\n", 182 | "for i in range(20):\n", 183 | " if (i > 10):\n", 184 | " sort.write(0x0400 + 4*i, i - 10)\n", 185 | "\n", 186 | "for i in range(20):\n", 187 | " if (i > 10):\n", 188 | " sort.write(0x0800 + 4*i, 20 - i)\n", 189 | "# start\n", 190 | "sort.write(0x0000, 1)\n", 191 | "\n", 192 | "from time import sleep\n", 193 | "\n", 194 | "sleep(3)\n", 195 | "\n", 196 | "# read sorted value\n", 197 | "for i in range(20):\n", 198 | " print(\"val : \" + str(sort.read(0x1000 + 4*i)))\n", 199 | " \n", 200 | "for i in range(20):\n", 201 | " print(\"freq : \" + str(sort.read(0x1400 + 4*i)))\n", 202 | " " 203 | ] 204 | } 205 | ], 206 | "metadata": { 207 | "kernelspec": { 208 | "display_name": "Python 3", 209 | "language": "python", 210 | "name": "python3" 211 | }, 212 | "language_info": { 213 | "codemirror_mode": { 214 | "name": "ipython", 215 | "version": 3 216 | }, 217 | "file_extension": ".py", 218 | "mimetype": "text/x-python", 219 | "name": "python", 220 | "nbconvert_exporter": "python", 221 | "pygments_lexer": "ipython3", 222 | "version": "3.6.0" 223 | } 224 | }, 225 | "nbformat": 4, 226 | "nbformat_minor": 2 227 | } 228 | -------------------------------------------------------------------------------- /tests/truncate-tree-test/bitstream/truncate-tree-test.bit: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/sopynq/huffman-encoding-core/f9c8819703dca7d038c7c567b5cdee2d41fac847/tests/truncate-tree-test/bitstream/truncate-tree-test.bit -------------------------------------------------------------------------------- /tests/truncate-tree-test/notebook/truncate-tree-test.ipynb: -------------------------------------------------------------------------------- 1 | { 2 | "cells": [ 3 | { 4 | "cell_type": "code", 5 | "execution_count": 1, 6 | "metadata": {}, 7 | "outputs": [ 8 | { 9 | "data": { 10 | "application/javascript": [ 11 | "\n", 12 | "require(['notebook/js/codecell'], function(codecell) {\n", 13 | " codecell.CodeCell.options_default.highlight_modes[\n", 14 | " 'magic_text/x-csrc'] = {'reg':[/^%%microblaze/]};\n", 15 | " Jupyter.notebook.events.one('kernel_ready.Kernel', function(){\n", 16 | " Jupyter.notebook.get_cells().map(function(cell){\n", 17 | " if (cell.cell_type == 'code'){ cell.auto_highlight(); } }) ;\n", 18 | " });\n", 19 | "});\n" 20 | ] 21 | }, 22 | "metadata": {}, 23 | "output_type": "display_data" 24 | }, 25 | { 26 | "name": "stdout", 27 | "output_type": "stream", 28 | "text": [ 29 | "pos : 0 len histogram_0 : 0\n", 30 | "pos : 0 len histogram_1 : 0\n", 31 | "pos : 1 len histogram_0 : 0\n", 32 | "pos : 1 len histogram_1 : 0\n", 33 | "pos : 2 len histogram_0 : 3\n", 34 | "pos : 2 len histogram_1 : 3\n", 35 | "pos : 3 len histogram_0 : 1\n", 36 | "pos : 3 len histogram_1 : 1\n", 37 | "pos : 4 len histogram_0 : 2\n", 38 | "pos : 4 len histogram_1 : 2\n" 39 | ] 40 | } 41 | ], 42 | "source": [ 43 | "# AXILiteS\n", 44 | "# 0x000 : Control signals\n", 45 | "# bit 0 - ap_start (Read/Write/COH)\n", 46 | "# bit 1 - ap_done (Read/COR)\n", 47 | "# bit 2 - ap_idle (Read)\n", 48 | "# bit 3 - ap_ready (Read)\n", 49 | "# bit 7 - auto_restart (Read/Write)\n", 50 | "# others - reserved\n", 51 | "# 0x004 : Global Interrupt Enable Register\n", 52 | "# bit 0 - Global Interrupt Enable (Read/Write)\n", 53 | "# others - reserved\n", 54 | "# 0x008 : IP Interrupt Enable Register (Read/Write)\n", 55 | "# bit 0 - Channel 0 (ap_done)\n", 56 | "# bit 1 - Channel 1 (ap_ready)\n", 57 | "# others - reserved\n", 58 | "# 0x00c : IP Interrupt Status Register (Read/TOW)\n", 59 | "# bit 0 - Channel 0 (ap_done)\n", 60 | "# bit 1 - Channel 1 (ap_ready)\n", 61 | "# others - reserved\n", 62 | "# 0x100 ~\n", 63 | "# 0x1ff : Memory 'input_length_histogram_V' (64 * 32b)\n", 64 | "# Word n : bit [31:0] - input_length_histogram_V[n]\n", 65 | "# 0x200 ~\n", 66 | "# 0x2ff : Memory 'output_length_histogram_0_V' (64 * 32b)\n", 67 | "# Word n : bit [31:0] - output_length_histogram_0_V[n]\n", 68 | "# 0x300 ~\n", 69 | "# 0x3ff : Memory 'output_length_histogram_1_V' (64 * 32b)\n", 70 | "# Word n : bit [31:0] - output_length_histogram_1_V[n]\n", 71 | "# (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)\n", 72 | "\n", 73 | "from pynq import Overlay\n", 74 | "\n", 75 | "overlay = Overlay(\"../bitstream/truncate-tree-test.bit\")\n", 76 | "overlay.download()\n", 77 | "\n", 78 | "truncate_tree = overlay.truncate_tree_0\n", 79 | "\n", 80 | "# bit length\n", 81 | "# L : 2 N : 3\n", 82 | "# L : 3 N : 1\n", 83 | "# L : 4 N : 2\n", 84 | "bit_len = [ 0, 0, 3, 1, 2 ]\n", 85 | "\n", 86 | "for idx, n in enumerate(bit_len):\n", 87 | " truncate_tree.write(0x100 + 4*idx, n)\n", 88 | " \n", 89 | "# start\n", 90 | "truncate_tree.write(0x000, 1)\n", 91 | "\n", 92 | "from time import sleep\n", 93 | "\n", 94 | "sleep(1)\n", 95 | "\n", 96 | "for i in range(5):\n", 97 | " len_histo_0 = truncate_tree.read(0x200 + 4*i)\n", 98 | " len_histo_1 = truncate_tree.read(0x300 + 4*i)\n", 99 | " print('pos : ' + str(i) + ' len histogram_0 : ' + str(len_histo_0))\n", 100 | " print('pos : ' + str(i) + ' len histogram_1 : ' + str(len_histo_1))" 101 | ] 102 | } 103 | ], 104 | "metadata": { 105 | "kernelspec": { 106 | "display_name": "Python 3", 107 | "language": "python", 108 | "name": "python3" 109 | }, 110 | "language_info": { 111 | "codemirror_mode": { 112 | "name": "ipython", 113 | "version": 3 114 | }, 115 | "file_extension": ".py", 116 | "mimetype": "text/x-python", 117 | "name": "python", 118 | "nbconvert_exporter": "python", 119 | "pygments_lexer": "ipython3", 120 | "version": "3.6.0" 121 | } 122 | }, 123 | "nbformat": 4, 124 | "nbformat_minor": 2 125 | } 126 | --------------------------------------------------------------------------------