├── .github └── workflows │ └── add_issue_to_project.yml ├── .gitignore ├── LICENSE.md ├── README.md ├── examples ├── Basic_Readings │ └── Basic_Readings.ino ├── Fifo_Example │ └── Fifo_Example.ino ├── Hardware_Interrupts │ └── Hardware_Interrupts.ino └── Software_Interrupts │ └── Software_Interrupts.ino ├── keywords.txt ├── library.properties └── src ├── README.md ├── SparkFunLSM6DSO.cpp └── SparkFunLSM6DSO.h /.github/workflows/add_issue_to_project.yml: -------------------------------------------------------------------------------- 1 | name: Add new issue to our main project 2 | 3 | on: 4 | issues: 5 | types: 6 | - opened 7 | 8 | jobs: 9 | add-to-project: 10 | name: Add issue to project 11 | runs-on: ubuntu-latest 12 | steps: 13 | - uses: actions/add-to-project@main 14 | with: 15 | # You can target a project in a different organization 16 | # to the issue 17 | project-url: https://github.com/orgs/sparkfun/projects/19 18 | github-token: ${{ secrets.DEFECT_ADD_TO_PROJECT }} 19 | -------------------------------------------------------------------------------- /.gitignore: -------------------------------------------------------------------------------- 1 | *~ 2 | [._]*.un~ 3 | *.swp 4 | -------------------------------------------------------------------------------- /LICENSE.md: -------------------------------------------------------------------------------- 1 | SparkFun License Information 2 | ============================ 3 | 4 | SparkFun uses two different licenses for our files - one for hardware and one for code. 5 | 6 | Hardware 7 | --------- 8 | 9 | **SparkFun hardware is released under [Creative Commons Share-alike 4.0 International](http://creativecommons.org/licenses/by-sa/4.0/).** 10 | 11 | Note: This is a human-readable summary of (and not a substitute for) the [license](http://creativecommons.org/licenses/by-sa/4.0/legalcode). 12 | 13 | You are free to: 14 | 15 | Share — copy and redistribute the material in any medium or format 16 | Adapt — remix, transform, and build upon the material 17 | for any purpose, even commercially. 18 | The licensor cannot revoke these freedoms as long as you follow the license terms. 19 | Under the following terms: 20 | 21 | Attribution — You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use. 22 | ShareAlike — If you remix, transform, or build upon the material, you must distribute your contributions under the same license as the original. 23 | No additional restrictions — You may not apply legal terms or technological measures that legally restrict others from doing anything the license permits. 24 | Notices: 25 | 26 | You do not have to comply with the license for elements of the material in the public domain or where your use is permitted by an applicable exception or limitation. 27 | No warranties are given. The license may not give you all of the permissions necessary for your intended use. For example, other rights such as publicity, privacy, or moral rights may limit how you use the material. 28 | 29 | 30 | Code 31 | -------- 32 | 33 | **SparkFun code, firmware, and software is released under the [MIT License](http://opensource.org/licenses/MIT).** 34 | 35 | The MIT License (MIT) 36 | 37 | Copyright (c) 2015 SparkFun Electronics 38 | 39 | Permission is hereby granted, free of charge, to any person obtaining a copy 40 | of this software and associated documentation files (the "Software"), to deal 41 | in the Software without restriction, including without limitation the rights 42 | to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 43 | copies of the Software, and to permit persons to whom the Software is 44 | furnished to do so, subject to the following conditions: 45 | 46 | The above copyright notice and this permission notice shall be included in all 47 | copies or substantial portions of the Software. 48 | 49 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 50 | IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 51 | FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 52 | AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 53 | LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 54 | OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 55 | SOFTWARE. 56 | 57 | 58 | -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | SparkFun Qwiic 6DoF LSM6DSO Breakout Arduino Library 2 | ======================================== 3 | 4 | [![SparkFun Qwiic 6DoF LSM6DSO Breakout](https://cdn.sparkfun.com/assets/parts/1/7/2/4/2/18020-SparkFun_6_Degrees_of_Freedom_Breakout_-_LSM6DSO__Qwiic_-01.jpg)](https://www.sparkfun.com/products/18020) 5 | 6 | [*SparkFun Qwiic 6DoF LSM6DSO Breakout (SEN-18020)*](https://www.sparkfun.com/products/18020) 7 | 8 | Arduino library support to control the SparkFun Qwiic 6DoF LSM6DSO. It can be configured to use I2C or SPI with 2 instances per I2C channel or any number of SPI instances. 9 | 10 | Repository Contents 11 | ------------------- 12 | 13 | * **/examples** - Example sketches for the library (.ino). Run these from the Arduino IDE. 14 | * **/extras** - Contains class diagrams for the driver. Ignored by IDE. 15 | * **/src** - Source files for the library (.cpp, .h). 16 | * **keywords.txt** - Keywords from this library that will be highlighted in the Arduino IDE. 17 | * **library.properties** - General library properties for the Arduino package manager. 18 | 19 | Example Briefs 20 | -------------- 21 | 22 | * FifoExample - Demonstrates using the built-in buffer to burst-collect data - **Good demonstration of settings** 23 | * InterruptFreeFall - Embedded function demonstrating free-fall detection 24 | * InterruptHWTapConfig - Embedded function demonstrating tap and double-tap detection 25 | * LowLevelExample - Demonstrates using only the core driver without math and settings overhead 26 | * MemoryPagingExample - Demonstrates switching between memory pages 27 | * MinimalistExample - The **easiest** configuration 28 | * MultiI2C - Using two LSM6DSOs over I2C 29 | * MultiSPI - Using two LSM6DSOs over SPI 30 | * Pedometer - Embedded function demonstrating step-counting feature 31 | 32 | Documentation 33 | -------------- 34 | 35 | * **[Installing an Arduino Library Guide](https://learn.sparkfun.com/tutorials/installing-an-arduino-library)** - Basic information on how to install an Arduino library. 36 | * **[Product Repository](https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO)** - Main repository (including hardware files) for the LSM6DSO Breakout. 37 | * **[Hookup Guide](https://learn.sparkfun.com/tutorials/1664)** - Basic hookup guide for the SparkFun Qwiic 6DoF LSM6DSO. 38 | 39 | Products that use this Library 40 | --------------------------------- 41 | 42 | * [SEN-18020](https://www.sparkfun.com/products/18020) 43 | 44 | Version History 45 | --------------- 46 | 47 | * V 1.0.0 48 | 49 | License Information 50 | ------------------- 51 | 52 | This product is _**open source**_! 53 | 54 | Please review the LICENSE.md file for license information. 55 | 56 | If you have any questions or concerns on licensing, please contact technical support on our [SparkFun forums](https://forum.sparkfun.com/viewforum.php?f=152). 57 | 58 | Distributed as-is; no warranty is given. 59 | 60 | - Your friends at SparkFun. 61 | 62 | -------------------------------------------------------------------------------- /examples/Basic_Readings/Basic_Readings.ino: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | Basic_Readings.ino 3 | 4 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO 5 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO_Arduino_Library 6 | 7 | Description: 8 | Most basic example of use. 9 | 10 | Example using the LSM6DSO with basic settings. This sketch collects Gyro and 11 | Accelerometer data every second, then presents it on the serial monitor. 12 | 13 | Development environment tested: 14 | Arduino IDE 1.8.2 15 | 16 | This code is released under the [MIT License](http://opensource.org/licenses/MIT). 17 | Please review the LICENSE.md file included with this example. If you have any questions 18 | or concerns with licensing, please contact techsupport@sparkfun.com. 19 | Distributed as-is; no warranty is given. 20 | ******************************************************************************/ 21 | 22 | #include "SparkFunLSM6DSO.h" 23 | #include "Wire.h" 24 | //#include "SPI.h" 25 | 26 | LSM6DSO myIMU; //Default constructor is I2C, addr 0x6B 27 | 28 | void setup() { 29 | 30 | 31 | Serial.begin(115200); 32 | delay(500); 33 | 34 | Wire.begin(); 35 | delay(10); 36 | if( myIMU.begin() ) 37 | Serial.println("Ready."); 38 | else { 39 | Serial.println("Could not connect to IMU."); 40 | Serial.println("Freezing"); 41 | } 42 | 43 | if( myIMU.initialize(BASIC_SETTINGS) ) 44 | Serial.println("Loaded Settings."); 45 | 46 | } 47 | 48 | 49 | void loop() 50 | { 51 | //Get all parameters 52 | Serial.print("\nAccelerometer:\n"); 53 | Serial.print(" X = "); 54 | Serial.println(myIMU.readFloatAccelX(), 3); 55 | Serial.print(" Y = "); 56 | Serial.println(myIMU.readFloatAccelY(), 3); 57 | Serial.print(" Z = "); 58 | Serial.println(myIMU.readFloatAccelZ(), 3); 59 | 60 | Serial.print("\nGyroscope:\n"); 61 | Serial.print(" X = "); 62 | Serial.println(myIMU.readFloatGyroX(), 3); 63 | Serial.print(" Y = "); 64 | Serial.println(myIMU.readFloatGyroY(), 3); 65 | Serial.print(" Z = "); 66 | Serial.println(myIMU.readFloatGyroZ(), 3); 67 | 68 | Serial.print("\nThermometer:\n"); 69 | Serial.print(" Degrees F = "); 70 | Serial.println(myIMU.readTempF(), 3); 71 | 72 | delay(1000); 73 | } 74 | -------------------------------------------------------------------------------- /examples/Fifo_Example/Fifo_Example.ino: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | Fifo_Example.ino 3 | 4 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO 5 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO_Arduino_Library 6 | 7 | Description: 8 | This example enables the use of the FIFO for data collection. The FIFO is set 9 | to collect 500 bytes of temperature and gyroscopic data before it stops 10 | collecting data (FIFO_MODE). Upon reading the data (or if you continuously read the FIFO) 11 | the FIFO will begine to refill. 12 | 13 | There are other available modes (see datasheet found in github repository for 14 | more information) but the entire list of fifo functionality predefines can be found below. 15 | 16 | myIMU.setFifoMode( -arguments below- ) 17 | 18 | FIFO_MODE_DISABLED 19 | FIFO_MODE_STOP_WHEN_FULL 20 | FIFO_MODE_CONT_TO_FIFO 21 | FIFO_MODE_BYPASS_TO_CONT 22 | FIFO_MODE_CONTINUOUS 23 | FIFO_MODE_BYPASS_TO_FIFO 24 | FIFO_MODE_MASK 25 | 26 | Development environment tested: 27 | Arduino IDE 1.8.2 28 | 29 | This code is released under the [MIT License](http://opensource.org/licenses/MIT). 30 | Please review the LICENSE.md file included with this example. If you have any questions 31 | or concerns with licensing, please contact techsupport@sparkfugn.com. 32 | Distributed as-is; no warranty is given. 33 | ******************************************************************************/ 34 | 35 | #include "SparkFunLSM6DSO.h" 36 | #include "Wire.h" 37 | //#include "SPI.h" 38 | 39 | LSM6DSO myIMU; 40 | fifoData myFifo; //This will hold our FIFO data 41 | int availableBytes = 0; 42 | 43 | void setup() 44 | { 45 | 46 | Serial.begin(115200); 47 | delay(500); 48 | 49 | Wire.begin(); 50 | delay(10); 51 | if( myIMU.begin() ) 52 | Serial.println("Ready."); 53 | else { 54 | Serial.println("Could not connect to IMU."); 55 | Serial.println("Freezing"); 56 | } 57 | 58 | if( myIMU.initialize(FIFO_SETTINGS) ) 59 | Serial.println("Loaded Settings."); 60 | 61 | 62 | 63 | } 64 | 65 | 66 | void loop() 67 | { 68 | availableBytes = myIMU.getFifoStatus(); //Check for data in FIFO 69 | 70 | if( availableBytes > 0 ){ 71 | Serial.print("Number of bytes in FIFO: "); 72 | Serial.println(availableBytes); 73 | 74 | myFifo = myIMU.fifoRead(); // Get the data 75 | 76 | if( myFifo.fifoTag == ACCELEROMETER_DATA ){ 77 | Serial.println("Accelerometer:"); 78 | Serial.print(" X = "); 79 | Serial.println(myFifo.xAccel, 3); 80 | Serial.print(" Y = "); 81 | Serial.println(myFifo.yAccel, 3); 82 | Serial.print(" Z = "); 83 | Serial.println(myFifo.zAccel, 3); 84 | } 85 | 86 | if( myFifo.fifoTag == GYROSCOPE_DATA ){ 87 | Serial.println("Gyroscope: "); 88 | Serial.print(" X = "); 89 | Serial.println(myFifo.xGyro, 3); 90 | Serial.print(" Y = "); 91 | Serial.println(myFifo.yGyro, 3); 92 | Serial.print(" Z = "); 93 | Serial.println(myFifo.zGyro, 3); 94 | } 95 | } 96 | 97 | delay(500); 98 | 99 | } 100 | -------------------------------------------------------------------------------- /examples/Hardware_Interrupts/Hardware_Interrupts.ino: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | Hardware_Interrupts.ino 3 | 4 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO 5 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO_Arduino_Library 6 | 7 | Description: 8 | This examples gets acclerometer data when an interrupt is deteced from "INT1" 9 | and gyroscopic data when an interrupt is detected from "INT2". These two 10 | interrupts can be put anywhere on your dev board, but for this example pins 11 | two and three were used for "INT1" and INT2" respectively. 12 | 13 | Interrupts can be changed to be active low: 14 | myIMU.configHardOutInt(INT_ACTIVE_LOW); 15 | Interrupts are being configured automatically like so: 16 | myIMU.setInterruptOne(INT1_DRDY_XL_ENABLED); 17 | myIMU.setInterruptTwo(INT2_DRDY_G_ENABLED); 18 | 19 | Development environment tested: 20 | Arduino IDE 1.8.2 21 | 22 | This code is released under the [MIT License](http://opensource.org/licenses/MIT). 23 | Please review the LICENSE.md file included with this example. If you have any questions 24 | or concerns with licensing, please contact techsupport@sparkfugn.com. 25 | Distributed as-is; no warranty is given. 26 | ******************************************************************************/ 27 | #include "SparkFunLSM6DSO.h" 28 | #include "Wire.h" 29 | //#include "SPI.h" 30 | 31 | 32 | LSM6DSO myIMU; 33 | 34 | int accelInt = 2; 35 | int gyroInt = 3; 36 | 37 | void setup() 38 | { 39 | 40 | Serial.begin(115200); 41 | delay(500); 42 | 43 | pinMode(accelInt, INPUT); 44 | pinMode(gyroInt,INPUT); 45 | 46 | Wire.begin(); 47 | if( myIMU.begin() ) 48 | Serial.println("Ready."); 49 | else { 50 | Serial.println("Could not connect to IMU."); 51 | Serial.println("Freezing"); 52 | while(1); 53 | } 54 | 55 | if( myIMU.initialize(HARD_INT_SETTINGS) ) 56 | Serial.println("Settings Loaded."); 57 | 58 | } 59 | 60 | 61 | void loop() 62 | { 63 | 64 | if( digitalRead(accelInt) == HIGH ){ 65 | Serial.print("\nAccelerometer:\n"); 66 | Serial.print(" X = "); 67 | Serial.println(myIMU.readFloatAccelX(), 3); 68 | Serial.print(" Y = "); 69 | Serial.println(myIMU.readFloatAccelY(), 3); 70 | Serial.print(" Z = "); 71 | Serial.println(myIMU.readFloatAccelZ(), 3); 72 | } 73 | 74 | if( digitalRead(gyroInt) == HIGH ){ 75 | Serial.print("\nGyroscope:\n"); 76 | Serial.print(" X = "); 77 | Serial.println(myIMU.readFloatGyroX(), 3); 78 | Serial.print(" Y = "); 79 | Serial.println(myIMU.readFloatGyroY(), 3); 80 | Serial.print(" Z = "); 81 | Serial.println(myIMU.readFloatGyroZ(), 3); 82 | } 83 | 84 | delay(1000); 85 | } 86 | 87 | 88 | -------------------------------------------------------------------------------- /examples/Software_Interrupts/Software_Interrupts.ino: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | Software_Interrupts.ino 3 | 4 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO 5 | https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DSO_Arduino_Library 6 | 7 | Description: 8 | This examples polls the "data ready" bit before checking for new acceleromter, 9 | gyroscopic, and temperature data. The data is then printed out to the serial 10 | monitor. 11 | 12 | For the sake of demonstration all the data points by have been turned on by default and 13 | so you can expect the IMU to send "all the data" when data is ready: 14 | "myIMU.listenDataReady()". 15 | 16 | Development environment tested: 17 | Arduino IDE 1.8.2 18 | 19 | This code is released under the [MIT License](http://opensource.org/licenses/MIT). 20 | Please review the LICENSE.md file included with this example. If you have any questions 21 | or concerns with licensing, please contact techsupport@sparkfun.com. 22 | Distributed as-is; no warranty is given. 23 | ******************************************************************************/ 24 | 25 | #include "SparkFunLSM6DSO.h" 26 | #include "Wire.h" 27 | // #include "SPI.h" 28 | 29 | LSM6DSO myIMU; 30 | 31 | int data; 32 | 33 | void setup() { 34 | 35 | Serial.begin(115200); 36 | delay(500); 37 | 38 | Wire.begin(); 39 | if( myIMU.begin() )// Load software interrupt related settings 40 | Serial.println("Ready."); 41 | else { 42 | Serial.println("Could not connect to IMU."); 43 | Serial.println("Freezing"); 44 | } 45 | 46 | if( myIMU.initialize(SOFT_INT_SETTINGS)) 47 | Serial.println("Loaded Settings."); 48 | 49 | } 50 | 51 | 52 | void loop() 53 | { 54 | 55 | data = myIMU.listenDataReady(); 56 | 57 | if( data == ALL_DATA_READY ){ 58 | Serial.print("\nAccelerometer:\n"); 59 | Serial.print(" X = "); 60 | Serial.println(myIMU.readFloatAccelX(), 3); 61 | Serial.print(" Y = "); 62 | Serial.println(myIMU.readFloatAccelY(), 3); 63 | Serial.print(" Z = "); 64 | Serial.println(myIMU.readFloatAccelZ(), 3); 65 | Serial.print("\nGyroscope:\n"); 66 | Serial.print(" X = "); 67 | Serial.println(myIMU.readFloatGyroX(), 3); 68 | Serial.print(" Y = "); 69 | Serial.println(myIMU.readFloatGyroY(), 3); 70 | Serial.print(" Z = "); 71 | Serial.println(myIMU.readFloatGyroZ(), 3); 72 | Serial.print("\nThermometer:\n"); 73 | Serial.print(" Degrees F = "); 74 | Serial.println(myIMU.readTempF(), 3); 75 | } 76 | 77 | delay(1000); 78 | /* 79 | if( data == ACCEL_DATA_READY ){ 80 | Serial.print("\nAccelerometer:\n"); 81 | Serial.print(" X = "); 82 | Serial.println(myIMU.readFloatAccelX(), 3); 83 | Serial.print(" Y = "); 84 | Serial.println(myIMU.readFloatAccelY(), 3); 85 | Serial.print(" Z = "); 86 | Serial.println(myIMU.readFloatAccelZ(), 3); 87 | } 88 | 89 | if( data == GYRO_DATA_READY ){ 90 | Serial.print("\nGyroscope:\n"); 91 | Serial.print(" X = "); 92 | Serial.println(myIMU.readFloatGyroX(), 3); 93 | Serial.print(" Y = "); 94 | Serial.println(myIMU.readFloatGyroY(), 3); 95 | Serial.print(" Z = "); 96 | Serial.println(myIMU.readFloatGyroZ(), 3); 97 | } 98 | 99 | if( data == TEMP_DATA_READY ){ 100 | Serial.print("\nThermometer:\n"); 101 | Serial.print(" Degrees F = "); 102 | Serial.println(myIMU.readTempF(), 3); 103 | } 104 | */ 105 | } 106 | 107 | 108 | -------------------------------------------------------------------------------- /keywords.txt: -------------------------------------------------------------------------------- 1 | ######################################################## 2 | # Syntax Coloring Map for SparkFun LSM6DS3 IMU Library # 3 | ######################################################## 4 | # Class 5 | ################################################################### 6 | 7 | LSM6DS3 KEYWORD1 8 | LSM6DS3Core KEYWORD1 9 | 10 | ################################################################### 11 | # Methods and Functions 12 | ################################################################### 13 | 14 | beginCore KEYWORD2 15 | beginSPICore KEYWORD2 16 | readRegister KEYWORD2 17 | readRegisterInt16 KEYWORD2 18 | readMultipleRegisters KEYWORD2 19 | writeRegister KEYWORD2 20 | writeMultipleRegisters KEYWORD2 21 | enableEmbeddedFunctions KEYWORD2 22 | begin KEYWORD2 23 | beginSPI KEYWORD2 24 | initialize KEYWORD2 25 | setAccelRange KEYWORD2 26 | setAccelDataRate KEYWORD2 27 | setGyroRange KEYWORD2 28 | setBlockDataUpdate KEYWORD2 29 | setHighPerfGyro KEYWORD2 30 | getAccelRange KEYWORD2 31 | getAccelDataRate KEYWORD2 32 | getGyroDataRate KEYWORD2 33 | getGyroRange KEYWORD2 34 | listenDataReady KEYWORD2 35 | getAccelFullScale KEYWORD2 36 | getAccelHighPerf KEYWORD2 37 | readFloatAccelX KEYWORD2 38 | readFloatAccelY KEYWORD2 39 | readFloatAccelZ KEYWORD2 40 | readFloatGyroX KEYWORD2 41 | readFloatGyroY KEYWORD2 42 | readFloatGyroZ KEYWORD2 43 | calcGyro KEYWORD2 44 | calcAccel KEYWORD2 45 | 46 | readRawTemp KEYWORD2 47 | readTempC KEYWORD2 48 | readTempF KEYWORD2 49 | 50 | setInterruptOne KEYWORD2 51 | getInterruptOne KEYWORD2 52 | setInterruptTwo KEYWORD2 53 | configHardOutInt KEYWORD2 54 | 55 | fifoBegin KEYWORD2 56 | fifoBeginSettings KEYWORD2 57 | setFifoMode KEYWORD2 58 | getFifoMode KEYWORD2 59 | setFifoDepth KEYWORD2 60 | getFifoDepth KEYWORD2 61 | setAccelBatchDataRate KEYWORD2 62 | getAccelBatchDataRate KEYWORD2 63 | setGyroBatchDataRate KEYWORD2 64 | getGyroBatchDataRate KEYWORD2 65 | fifoClear KEYWORD2 66 | fifoRead KEYWORD2 67 | getFifoStatus KEYWORD2 68 | fifoEnd KEYWORD2 69 | 70 | enablePedometer KEYWORD2 71 | getPedometer KEYWORD2 72 | getSteps KEYWORD2 73 | resetSteps KEYWORD2 74 | enableTap KEYWORD2 75 | setTapDirPrior KEYWORD2 76 | getTapDirPrior KEYWORD2 77 | setTapClearOnRead KEYWORD2 78 | getTapClearOnRead KEYWORD2 79 | clearTapInt KEYWORD2 80 | setXThreshold KEYWORD2 81 | listenStep KEYWORD2 82 | configureTap KEYWORD2 83 | 84 | routeHardInterOne KEYWORD2 85 | routeHardInterTwo KEYWORD2 86 | setIncrement KEYWORD2 87 | softwareReset KEYWORD2 88 | clearAllInt KEYWORD2 89 | 90 | 91 | ################################################################### 92 | # Constants 93 | ################################################################### 94 | 95 | I2C_MODE LITERAL1 96 | SPI_MODE LITERAL1 97 | IMU_SUCCESS LITERAL1 98 | IMU_HW_ERROR LITERAL1 99 | IMU_NOT_SUPPORTED LITERAL1 100 | IMU_GENERIC_ERROR LITERAL1 101 | IMU_OUT_OF_BOUNDS LITERAL1 102 | IMU_ALL_ONES_WARNING LITERAL1 103 | ACCEL_DATA_READY LITERAL1 104 | GYRO_DATA_READY LITERAL1 105 | TEMP_DATA_READY LITERAL1 106 | ALL_DATA_READY LITERAL1 107 | BASIC_SETTINGS LITERAL1 108 | SOFT_INT_SETTINGS LITERAL1 109 | HARD_INT_SETTINGS LITERAL1 110 | FIFO_SETTINGS LITERAL1 111 | PEDOMETER_SETTINGS LITERAL1 112 | TAP_SETTINGS LITERAL1 113 | FREE_FALL_SETTINGS LITERAL1 114 | SPI_READ_COMMAND LITERAL1 115 | DEFAULT_ADDRESS LITERAL1 116 | ALT_ADDRESS LITERAL1 117 | -------------------------------------------------------------------------------- /library.properties: -------------------------------------------------------------------------------- 1 | name=SparkFun Qwiic 6Dof - LSM6DSO 2 | version=1.0.4 3 | author=SparkFun Electronics 4 | maintainer=SparkFun Electronics 5 | sentence=A library to drive the STmicro LSM6DSO by SPI or I2C. 6 | paragraph= 7 | category=Sensors 8 | url=https://github.com/sparkfun/SparkFun_Qwiic_6DoF_LSM6DS0_Arduino_Library 9 | architectures=* 10 | -------------------------------------------------------------------------------- /src/README.md: -------------------------------------------------------------------------------- 1 | This folder should contain the .cpp and .h files for the library. 2 | 3 | If backward compatibility is needed, source code should be placed in the library root folder and in a "utility" folder. 4 | 5 | Check out the [library specification](https://github.com/arduino/Arduino/wiki/Arduino-IDE-1.5:-Library-specification) for more details. -------------------------------------------------------------------------------- /src/SparkFunLSM6DSO.cpp: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | SparkFunLSM6DSO.cpp 3 | LSM6DSO Arduino and Teensy Driver 4 | 5 | Marshall Taylor @ SparkFun Electronics 6 | May 20, 2015 7 | https://github.com/sparkfun/LSM6DSO_Breakout 8 | https://github.com/sparkfun/SparkFun_LSM6DSO_Arduino_Library 9 | 10 | Resources: 11 | Uses Wire.h for i2c operation 12 | Uses SPI.h for SPI operation 13 | Either can be omitted if not used 14 | 15 | Development environment specifics: 16 | Arduino IDE 1.6.4 17 | Teensy loader 1.23 18 | 0 19 | This code is released under the [MIT License](http://opensource.org/licenses/MIT). 20 | 21 | Please review the LICENSE.md file included with this example. If you have any questions 22 | or concerns with licensing, please contact techsupport@sparkfun.com. 23 | 24 | Distributed as-is; no warranty is given. 25 | ******************************************************************************/ 26 | 27 | 28 | #include "SparkFunLSM6DSO.h" 29 | 30 | LSM6DSOCore::LSM6DSOCore() { } 31 | 32 | status_t LSM6DSOCore::beginCore(uint8_t deviceAddress, TwoWire &i2cPort) 33 | { 34 | 35 | 36 | commInterface = I2C_MODE; 37 | _i2cPort = &i2cPort; 38 | I2CAddress = deviceAddress; 39 | 40 | uint8_t partID; 41 | status_t returnError = readRegister(&partID, WHO_AM_I_REG); 42 | if( partID != 0x6C && returnError != IMU_SUCCESS) 43 | return returnError; 44 | else 45 | return IMU_SUCCESS; 46 | 47 | } 48 | 49 | status_t LSM6DSOCore::beginSPICore(uint8_t csPin, uint32_t spiPortSpeed, SPIClass &spiPort){ 50 | 51 | commInterface = SPI_MODE; 52 | _spiPort = &spiPort; 53 | chipSelectPin = csPin; 54 | 55 | #ifdef __AVR__ 56 | mySpiSettings = SPISettings(spiPortSpeed, MSBFIRST, SPI_MODE1); 57 | #endif 58 | // MODE0 for Teensy 3.1 operation 59 | #ifdef __MK20DX256__ 60 | mySpiSettings = SPISettings(spiPortSpeed, MSBFIRST, SPI_MODE0); 61 | #endif 62 | 63 | #ifdef ESP32 64 | mySpiSettings = SPISettings(spiPortSpeed, SPI_MSBFIRST, SPI_MODE0); 65 | #endif 66 | 67 | pinMode(chipSelectPin, OUTPUT); 68 | digitalWrite(chipSelectPin, HIGH); 69 | 70 | uint8_t partID; 71 | readRegister(&partID, WHO_AM_I_REG); 72 | if( partID != 0x6C ) 73 | return IMU_HW_ERROR; 74 | else 75 | return IMU_SUCCESS; 76 | } 77 | 78 | //****************************************************************************// 79 | // 80 | // ReadRegisterRegion 81 | // 82 | // Parameters: 83 | // *outputPointer -- Pass &variable (base address of) to save read data to 84 | // address -- register to read 85 | // numBytes -- number of bytes to read 86 | // 87 | // Note: Does not know if the target memory space is an array or not, or 88 | // if there is the array is big enough. if the variable passed is only 89 | // two bytes long and 3 bytes are requested, this will over-write some 90 | // other memory! 91 | // 92 | //****************************************************************************// 93 | status_t LSM6DSOCore::readMultipleRegisters(uint8_t outputPointer[], uint8_t address, uint8_t numBytes) 94 | { 95 | 96 | status_t returnError; 97 | uint8_t byteReturn; 98 | 99 | switch( commInterface ){ 100 | 101 | case I2C_MODE: 102 | 103 | _i2cPort->beginTransmission(I2CAddress); 104 | _i2cPort->write(address); 105 | if( _i2cPort->endTransmission(false) != 0 ) 106 | return IMU_HW_ERROR; 107 | 108 | byteReturn = _i2cPort->requestFrom(static_cast(I2CAddress), static_cast(numBytes)); 109 | 110 | if( byteReturn == 0 ) 111 | return IMU_HW_ERROR; 112 | 113 | for(size_t i = 0; i < numBytes; i++){ 114 | outputPointer[i] = _i2cPort->read(); 115 | } 116 | 117 | return IMU_SUCCESS; 118 | 119 | case SPI_MODE: 120 | 121 | _spiPort->beginTransaction(mySpiSettings); 122 | digitalWrite(chipSelectPin, LOW); 123 | 124 | _spiPort->transfer(address | SPI_READ_COMMAND); 125 | 126 | for(size_t i = 0; i < numBytes; i++ ) { 127 | outputPointer[i] = _spiPort->transfer(0x00); // receive a byte as character 128 | } 129 | 130 | digitalWrite(chipSelectPin, HIGH); 131 | _spiPort->endTransaction(); 132 | 133 | return IMU_SUCCESS; 134 | 135 | default: 136 | return IMU_GENERIC_ERROR; 137 | 138 | } 139 | } 140 | 141 | //****************************************************************************// 142 | // readRegister 143 | // 144 | // Parameters: 145 | // *outputPointer -- Pass &variable (address of) to save read data to 146 | // address -- register to read 147 | //****************************************************************************// 148 | status_t LSM6DSOCore::readRegister(uint8_t* outputPointer, uint8_t address) { 149 | 150 | status_t returnError; 151 | uint8_t byteReturn; 152 | 153 | switch (commInterface) { 154 | 155 | case I2C_MODE: 156 | 157 | _i2cPort->beginTransmission(I2CAddress); 158 | _i2cPort->write(address); 159 | if( _i2cPort->endTransmission() != 0 ) 160 | return IMU_HW_ERROR; 161 | 162 | byteReturn = _i2cPort->requestFrom(static_cast(I2CAddress), static_cast(1)); 163 | 164 | if( byteReturn == 0 ) 165 | return IMU_HW_ERROR; 166 | 167 | *outputPointer = _i2cPort->read(); // receive a byte as a proper uint8_t 168 | 169 | return IMU_SUCCESS; 170 | 171 | case SPI_MODE: 172 | // take the chip select low to select the device: 173 | digitalWrite(chipSelectPin, LOW); 174 | _spiPort->beginTransaction(mySpiSettings); 175 | 176 | _spiPort->transfer(address | SPI_READ_COMMAND); 177 | *outputPointer = _spiPort->transfer(0x00); 178 | 179 | digitalWrite(chipSelectPin, HIGH); 180 | _spiPort->endTransaction(); 181 | 182 | return IMU_SUCCESS; 183 | 184 | default: 185 | return IMU_GENERIC_ERROR; 186 | } 187 | 188 | } 189 | 190 | //****************************************************************************// 191 | // readRegisterInt16 192 | // 193 | // Parameters: 194 | // *outputPointer -- Pass &variable (base address of) to save read data to 195 | // address -- register to read 196 | //****************************************************************************// 197 | status_t LSM6DSOCore::readRegisterInt16(int16_t* outputPointer, uint8_t address) 198 | { 199 | uint8_t myBuffer[2]; 200 | status_t returnError = readMultipleRegisters(myBuffer, address, 2); //Does memory transfer 201 | int16_t output = myBuffer[0] | static_cast(myBuffer[1] << 8); 202 | 203 | *outputPointer = output; 204 | return returnError; 205 | } 206 | 207 | //****************************************************************************// 208 | // writeRegister 209 | // 210 | // Parameters: 211 | // address -- register to write 212 | // dataToWrite -- 8 bit data to write to register 213 | //****************************************************************************// 214 | status_t LSM6DSOCore::writeRegister(uint8_t address, uint8_t dataToWrite) { 215 | 216 | status_t returnError; 217 | 218 | switch (commInterface) { 219 | 220 | case I2C_MODE: 221 | //Write the byte 222 | _i2cPort->beginTransmission(I2CAddress); 223 | _i2cPort->write(address); 224 | _i2cPort->write(dataToWrite); 225 | if( _i2cPort->endTransmission() != 0 ) 226 | return IMU_HW_ERROR; 227 | break; 228 | 229 | case SPI_MODE: 230 | // take the chip select low to select the device: 231 | _spiPort->beginTransaction(mySpiSettings); 232 | digitalWrite(chipSelectPin, LOW); 233 | 234 | _spiPort->transfer(address); 235 | _spiPort->transfer(dataToWrite); 236 | 237 | digitalWrite(chipSelectPin, HIGH); 238 | _spiPort->endTransaction(); 239 | break; 240 | 241 | default: 242 | break; 243 | 244 | } 245 | 246 | return IMU_SUCCESS; 247 | } 248 | 249 | //****************************************************************************// 250 | // writeMultipleRegisters 251 | // 252 | // Parameters: 253 | // inputPointer -- array to be written to device 254 | // address -- register to write 255 | // numBytes -- number of bytes contained in the array 256 | //****************************************************************************// 257 | status_t LSM6DSOCore::writeMultipleRegisters(uint8_t inputPointer[], uint8_t address, uint8_t numBytes) { 258 | 259 | status_t returnError; 260 | 261 | switch( commInterface ){ 262 | 263 | case I2C_MODE: 264 | 265 | _i2cPort->beginTransmission(I2CAddress); 266 | _i2cPort->write(address); 267 | 268 | for(size_t i = 0; i < numBytes; i++){ 269 | _i2cPort->write(inputPointer[i]); 270 | } 271 | 272 | if( _i2cPort->endTransmission() != 0 ) 273 | return IMU_HW_ERROR; 274 | else 275 | return IMU_SUCCESS; 276 | 277 | case SPI_MODE: 278 | 279 | _spiPort->beginTransaction(mySpiSettings); 280 | digitalWrite(chipSelectPin, LOW); 281 | 282 | _spiPort->transfer(inputPointer, 2); 283 | 284 | digitalWrite(chipSelectPin, HIGH); 285 | _spiPort->endTransaction(); 286 | 287 | return IMU_SUCCESS; 288 | 289 | default: 290 | return IMU_GENERIC_ERROR; 291 | 292 | } 293 | } 294 | 295 | 296 | status_t LSM6DSOCore::enableEmbeddedFunctions(bool enable) 297 | { 298 | uint8_t tempVal; 299 | readRegister(&tempVal, FUNC_CFG_ACCESS); 300 | 301 | tempVal &= 0x7F; 302 | 303 | if( enable ) 304 | tempVal |= 0x80; 305 | else 306 | tempVal |= 0x7F; 307 | 308 | status_t returnError = writeRegister( FUNC_CFG_ACCESS, tempVal ); 309 | return returnError; 310 | } 311 | 312 | //****************************************************************************// 313 | // 314 | // Main user class -- wrapper for the core class + maths 315 | // 316 | // Construct with same rules as the core ( uint8_t busType, uint8_t inputArg ) 317 | // 318 | //****************************************************************************// 319 | LSM6DSO::LSM6DSO() 320 | { 321 | //Construct with these default imuSettings 322 | 323 | imuSettings.gyroEnabled = true; //Can be 0 or 1 324 | imuSettings.gyroRange = 500; //Max deg/s. Can be: 125, 250, 500, 1000, 2000 325 | imuSettings.gyroSampleRate = 416; //Hz. Can be: 13, 26, 52, 104, 208, 416, 833, 1666 326 | imuSettings.gyroBandWidth = 400; //Hz. Can be: 50, 100, 200, 400; 327 | imuSettings.gyroFifoEnabled = 1; //Set to include gyro in FIFO 328 | imuSettings.gyroAccelDecimation = 1; //Set to include gyro in FIFO 329 | 330 | imuSettings.accelEnabled = true; 331 | imuSettings.accelRange = 8; //Max G force readable. Can be: 2, 4, 8, 16 332 | imuSettings.accelSampleRate = 416; //Hz. Can be: 1.6 (16), 12.5 (125), 26, 52, 104, 208, 416, 833, 1660, 3330, 6660 333 | imuSettings.accelFifoEnabled = 1; //Set to include accelerometer in the FIFO 334 | 335 | imuSettings.fifoEnabled = true; 336 | imuSettings.fifoThreshold = 3000; //Can be 0 to 4096 (16 bit bytes) 337 | imuSettings.fifoSampleRate = 416; 338 | imuSettings.fifoModeWord = 0; //Default off 339 | 340 | allOnesCounter = 0; 341 | nonSuccessCounter = 0; 342 | 343 | 344 | } 345 | 346 | bool LSM6DSO::begin(uint8_t address, TwoWire &i2cPort){ 347 | 348 | if( address != DEFAULT_ADDRESS && address != ALT_ADDRESS ) 349 | return false; 350 | 351 | uint8_t regVal; 352 | status_t returnError = beginCore(address, i2cPort); 353 | if( returnError != IMU_SUCCESS ) 354 | return false; 355 | else 356 | return true; 357 | 358 | } 359 | 360 | bool LSM6DSO::beginSPI(uint8_t csPin, uint32_t spiPortSpeed, SPIClass &spiPort){ 361 | 362 | 363 | status_t returnError = beginSPICore(csPin, spiPortSpeed, spiPort); 364 | if( returnError != IMU_SUCCESS ) 365 | return false; 366 | else 367 | return true; 368 | } 369 | 370 | bool LSM6DSO::initialize(uint8_t settings){ 371 | 372 | setIncrement(); 373 | 374 | if( settings == BASIC_SETTINGS ){ 375 | setAccelRange(8); 376 | setAccelDataRate(416); 377 | setGyroRange(500); 378 | setGyroDataRate(416); 379 | setBlockDataUpdate(true); 380 | } 381 | else if( settings == SOFT_INT_SETTINGS ){ 382 | setAccelRange(8); 383 | setAccelDataRate(416); 384 | setGyroRange(500); 385 | setGyroDataRate(416); 386 | } 387 | else if( settings == HARD_INT_SETTINGS ){ 388 | setInterruptOne(INT1_DRDY_XL_ENABLED); 389 | setInterruptTwo(INT2_DRDY_G_ENABLED); 390 | setAccelRange(8); 391 | setAccelDataRate(416); 392 | setGyroRange(500); 393 | setGyroDataRate(416); 394 | } 395 | else if( settings == FIFO_SETTINGS ){ 396 | setFifoDepth(500); // bytes 397 | //setTSDecimation(); // FIFO_CTRL4 398 | //getSamplesStored(); // FIFO_STATUS1 and STATUS2 399 | setAccelBatchDataRate(417); 400 | setGyroBatchDataRate(417); 401 | setFifoMode(FIFO_MODE_STOP_WHEN_FULL); 402 | setAccelRange(8); 403 | setAccelDataRate(833); 404 | setGyroRange(500); 405 | setGyroDataRate(833); 406 | } 407 | else if( settings == PEDOMETER_SETTINGS ){ 408 | enableEmbeddedFunctions(true); 409 | setAccelDataRate(52); 410 | enablePedometer(true); 411 | } 412 | else if( settings == TAP_SETTINGS ){ 413 | setAccelRange(2); 414 | setAccelDataRate(417); // Must be at least 417 415 | enableTap(true, true, true, true); 416 | setTapDirPrior( TAP_PRIORITY_YXZ ); 417 | setXThreshold(9); 418 | configureTap(0x06); 419 | routeHardInterOne(INT1_SINGLE_TAP_ENABLED); 420 | //setTapClearOnRead(true); //TAP_CFG0 421 | } 422 | else if( settings == FREE_FALL_SETTINGS ){ 423 | enableEmbeddedFunctions(true); 424 | //setFreeFall(true); 425 | // getFreeFall(); 426 | } 427 | 428 | return true; 429 | 430 | } 431 | 432 | status_t LSM6DSO::beginSettings() { 433 | 434 | uint8_t dataToWrite = 0; //Temporary variable 435 | 436 | //Setup the accelerometer****************************** 437 | dataToWrite = 0; //Start Fresh! 438 | if ( imuSettings.accelEnabled == 1) { 439 | //Range 440 | switch (imuSettings.accelRange) { 441 | case 2: 442 | dataToWrite |= FS_XL_2g; 443 | break; 444 | case 4: 445 | dataToWrite |= FS_XL_4g; 446 | break; 447 | case 8: 448 | dataToWrite |= FS_XL_8g; 449 | break; 450 | default: //set default case to 16(max) 451 | case 16: 452 | dataToWrite |= FS_XL_16g; 453 | break; 454 | } 455 | // Accelerometer ODR 456 | switch (imuSettings.accelSampleRate) { 457 | case 16: 458 | dataToWrite |= ODR_XL_1_6Hz; 459 | break; 460 | case 125: 461 | dataToWrite |= ODR_XL_12_5Hz; 462 | break; 463 | case 26: 464 | dataToWrite |= ODR_XL_26Hz; 465 | break; 466 | case 52: 467 | dataToWrite |= ODR_XL_52Hz; 468 | break; 469 | default: //Set default to 104 470 | case 104: 471 | dataToWrite |= ODR_XL_104Hz; 472 | break; 473 | case 208: 474 | dataToWrite |= ODR_XL_208Hz; 475 | break; 476 | case 416: 477 | dataToWrite |= ODR_XL_416Hz; 478 | break; 479 | case 833: 480 | dataToWrite |= ODR_XL_833Hz; 481 | break; 482 | case 1660: 483 | dataToWrite |= ODR_XL_1660Hz; 484 | break; 485 | case 3330: 486 | dataToWrite |= ODR_XL_3330Hz; 487 | break; 488 | case 6660: 489 | dataToWrite |= ODR_XL_6660Hz; 490 | break; 491 | } 492 | } 493 | 494 | // Write Accelerometer Settings.... 495 | writeRegister(CTRL1_XL, dataToWrite); 496 | 497 | //Setup the gyroscope********************************************** 498 | dataToWrite = 0; // Clear variable 499 | 500 | if ( imuSettings.gyroEnabled == 1) { 501 | switch (imuSettings.gyroRange) { 502 | case 125: 503 | dataToWrite |= FS_G_125dps; 504 | break; 505 | case 245: 506 | dataToWrite |= FS_G_250dps; 507 | break; 508 | case 500: 509 | dataToWrite |= FS_G_500dps; 510 | break; 511 | case 1000: 512 | dataToWrite |= FS_G_1000dps; 513 | break; 514 | default: //Default to full 2000DPS range 515 | case 2000: 516 | dataToWrite |= FS_G_2000dps; 517 | break; 518 | } 519 | switch (imuSettings.gyroSampleRate) { 520 | case 125: 521 | dataToWrite |= ODR_GYRO_12_5Hz; 522 | break; 523 | case 26: 524 | dataToWrite |= ODR_GYRO_26Hz; 525 | break; 526 | case 52: 527 | dataToWrite |= ODR_GYRO_52Hz; 528 | break; 529 | default: //Set default to 104 530 | case 104: 531 | dataToWrite |= ODR_GYRO_104Hz; 532 | break; 533 | case 208: 534 | dataToWrite |= ODR_GYRO_208Hz; 535 | break; 536 | case 416: 537 | dataToWrite |= ODR_GYRO_416Hz; 538 | break; 539 | case 833: 540 | dataToWrite |= ODR_GYRO_833Hz; 541 | break; 542 | case 1660: 543 | dataToWrite |= ODR_GYRO_1660Hz; 544 | break; 545 | case 3330: 546 | dataToWrite |= ODR_GYRO_3330Hz; 547 | break; 548 | case 6660: 549 | dataToWrite |= ODR_GYRO_6660Hz; 550 | break; 551 | } 552 | } 553 | 554 | // Write the gyroscope imuSettings. 555 | writeRegister(CTRL2_G, dataToWrite); 556 | 557 | return IMU_SUCCESS; 558 | } 559 | 560 | // Address: 0x1E , bit[2:0]: default value is: 0x00 561 | // Checks if there is new accelerometer, gyro, or temperature data. 562 | uint8_t LSM6DSO::listenDataReady(){ 563 | 564 | uint8_t regVal; 565 | status_t returnError = readRegister(®Val, STATUS_REG); 566 | 567 | if( returnError != IMU_SUCCESS ) 568 | return IMU_GENERIC_ERROR; 569 | else 570 | return regVal; 571 | } 572 | 573 | // Address:0x12 CTRL3_C , bit[6] default value is: 0x00 574 | // This function sets the BDU (Block Data Update) bit. Use when not employing 575 | // the FIFO buffer. 576 | bool LSM6DSO::setBlockDataUpdate(bool enable){ 577 | 578 | uint8_t regVal; 579 | status_t returnError = readRegister(®Val, CTRL3_C); 580 | if( returnError != IMU_SUCCESS ) 581 | return false; 582 | 583 | regVal &= 0xBF; 584 | regVal |= BDU_BLOCK_UPDATE; 585 | 586 | returnError = writeRegister(CTRL3_C, regVal); 587 | if( returnError != IMU_SUCCESS ) 588 | return false; 589 | else 590 | return true; 591 | 592 | 593 | } 594 | 595 | // Address:0x0D , bit[7:0]: default value is: 0x00 596 | // Sets whether the accelerometer, gyroscope, or FIFO trigger on hardware 597 | // interrupt one. Error checking for the user's argument is tricky (could be a 598 | // long list of "if not this and not this and not this" instead the function relies on the 599 | // user to set the correct value. 600 | bool LSM6DSO::setInterruptOne(uint8_t setting) { 601 | 602 | uint8_t regVal; 603 | status_t returnError = readRegister(®Val, INT1_CTRL); 604 | if( returnError != IMU_SUCCESS ) 605 | return false; 606 | 607 | regVal &= 0xFE; 608 | regVal |= setting; 609 | 610 | returnError = writeRegister(INT1_CTRL, regVal); 611 | if( returnError != IMU_SUCCESS ) 612 | return false; 613 | else 614 | return true; 615 | } 616 | 617 | // Address:0x0D , bit[7:0]: default value is: 0x00 618 | // Gets whether the accelerometer, gyroscope, or FIFO trigger on hardware 619 | // interrupt one. 620 | uint8_t LSM6DSO::getInterruptOne() { 621 | 622 | uint8_t regVal; 623 | status_t returnError = readRegister(®Val, INT1_CTRL); 624 | if( returnError != IMU_SUCCESS ) 625 | return false; 626 | else 627 | return regVal; 628 | } 629 | 630 | // Address: 0x12, bit[5,4]: default value is: 0x00 631 | // Configures the polarity of the hardware interrupts and whether they are 632 | // push-pull or open-drain. 633 | bool LSM6DSO::configHardOutInt(uint8_t polarity, uint8_t pushOrDrain) { 634 | 635 | uint8_t regVal; 636 | status_t returnError = readRegister(®Val, CTRL3_C); 637 | if( returnError != IMU_SUCCESS ) 638 | return false; 639 | 640 | regVal &= 0xCF; 641 | regVal |= polarity; 642 | regVal |= pushOrDrain; 643 | 644 | returnError = writeRegister(CTRL3_C, regVal); 645 | if( returnError != IMU_SUCCESS ) 646 | return false; 647 | else 648 | return true; 649 | } 650 | // Address:0x0E , bit[7:0]: default value is: 0x00 651 | // Sets whether the accelerometer, gyroscope, temperature sensor or FIFO trigger on hardware 652 | // interrupt two. Error checking for the user's argument is tricky (could be a 653 | // long list of "if not this and not this and not this" instead the function relies on the 654 | // user to set the correct value. 655 | bool LSM6DSO::setInterruptTwo(uint8_t setting) { 656 | 657 | status_t returnError = writeRegister(INT2_CTRL, setting); 658 | if( returnError != IMU_SUCCESS ) 659 | return false; 660 | else 661 | return true; 662 | 663 | } 664 | 665 | // Address:0x15 , bit[4]: default value is: 0x00 666 | // Sets whether high performance mode is on for the acclerometer, by default it is ON. 667 | bool LSM6DSO::setHighPerfAccel(bool enable){ 668 | 669 | uint8_t regVal; 670 | status_t returnError = readRegister(®Val, CTRL6_C); 671 | if( returnError != IMU_SUCCESS ) 672 | return false; 673 | 674 | if( enable ) 675 | regVal |= HIGH_PERF_ACC_ENABLE; 676 | else 677 | regVal |= HIGH_PERF_ACC_DISABLE; 678 | 679 | returnError = writeRegister(CTRL6_C, regVal); 680 | if( returnError != IMU_SUCCESS ) 681 | return false; 682 | else 683 | return true; 684 | } 685 | 686 | // Address:0x16 , bit[7]: default value is: 0x00 687 | // Sets whether high performance mode is on for the gyroscope, by default it is ON. 688 | bool LSM6DSO::setHighPerfGyro(bool enable){ 689 | 690 | uint8_t regVal; 691 | status_t returnError = readRegister(®Val, CTRL7_G); 692 | if( returnError != IMU_SUCCESS ) 693 | return false; 694 | 695 | if( enable ) 696 | regVal |= HIGH_PERF_GYRO_ENABLE; 697 | else 698 | regVal |= HIGH_PERF_GYRO_DISABLE; 699 | 700 | returnError = writeRegister(CTRL7_G, regVal); 701 | if( returnError != IMU_SUCCESS ) 702 | return false; 703 | else 704 | return true; 705 | } 706 | 707 | //****************************************************************************// 708 | // 709 | // Accelerometer section 710 | // 711 | //****************************************************************************// 712 | 713 | // Address: 0x10 , bit[4:3]: default value is: 0x00 (2g) 714 | // Sets the acceleration range of the accleromter portion of the IMU. 715 | bool LSM6DSO::setAccelRange(uint8_t range) { 716 | 717 | if( range < 0 | range > 16) 718 | return false; 719 | 720 | uint8_t regVal; 721 | uint8_t fullScale; 722 | status_t returnError = readRegister(®Val, CTRL1_XL); 723 | if( returnError != IMU_SUCCESS ) 724 | return false; 725 | 726 | fullScale = getAccelFullScale(); 727 | 728 | // Can't have 16g with XL_FS_MODE == 1 729 | if( fullScale == 1 && range == 16 ) 730 | range = 8; 731 | 732 | regVal &= FS_XL_MASK; 733 | 734 | switch( range ) { 735 | case 2: 736 | regVal |= FS_XL_2g; 737 | break; 738 | case 4: 739 | regVal |= FS_XL_4g; 740 | break; 741 | case 8: 742 | regVal |= FS_XL_8g; 743 | break; 744 | case 16: 745 | regVal |= FS_XL_16g; 746 | break; 747 | default: 748 | break; 749 | } 750 | 751 | returnError = writeRegister(CTRL1_XL, regVal); 752 | if( returnError != IMU_SUCCESS ) 753 | return false; 754 | else 755 | return true; 756 | } 757 | 758 | // Address: 0x10 , bit[4:3]: default value is: 0x00 (2g) 759 | // Gets the acceleration range of the accleromter portion of the IMU. 760 | // The value is dependent on the full scale bit (see getAccelFullScale). 761 | uint8_t LSM6DSO::getAccelRange(){ 762 | 763 | uint8_t regVal; 764 | uint8_t fullScale; 765 | 766 | status_t returnError = readRegister(®Val, CTRL1_XL); 767 | if( returnError != IMU_SUCCESS ) 768 | return IMU_GENERIC_ERROR; 769 | 770 | fullScale = getAccelFullScale(); 771 | regVal = (regVal & 0x0C) >> 2; 772 | 773 | if( fullScale == 1 ){ 774 | switch( regVal ){ 775 | case 0: 776 | return 2; 777 | case 1: 778 | return 2; 779 | case 2: 780 | return 4; 781 | case 3: 782 | return 8; 783 | default: 784 | return IMU_GENERIC_ERROR; 785 | } 786 | } 787 | else if( fullScale == 0 ){ 788 | switch( regVal ){ 789 | case 0: 790 | return 2; 791 | case 1: 792 | return 16; 793 | case 2: 794 | return 4; 795 | case 3: 796 | return 8; 797 | default: 798 | return IMU_GENERIC_ERROR; 799 | } 800 | } 801 | else 802 | return IMU_GENERIC_ERROR; 803 | 804 | } 805 | 806 | // Address: 0x10, bit[7:4]: default value is: 0x00 (Power Down) 807 | // Sets the output data rate of the accelerometer there-by enabling it. 808 | bool LSM6DSO::setAccelDataRate(uint16_t rate) { 809 | 810 | if( rate < 16 | rate > 6660) 811 | return false; 812 | 813 | uint8_t regVal; 814 | uint8_t highPerf; 815 | status_t returnError = readRegister(®Val, CTRL1_XL); 816 | if( returnError != IMU_SUCCESS ) 817 | return false; 818 | 819 | highPerf = getAccelHighPerf(); 820 | 821 | // Can't have 1.6Hz and have high performance mode enabled. 822 | if( highPerf == 0 && rate == 16 ) 823 | rate = 125; 824 | 825 | regVal &= ODR_XL_MASK; 826 | 827 | switch ( rate ) { 828 | case 0: 829 | regVal |= ODR_XL_DISABLE; 830 | break; 831 | case 16: 832 | regVal |= ODR_XL_1_6Hz; 833 | break; 834 | case 125: 835 | regVal |= ODR_XL_12_5Hz; 836 | break; 837 | case 26: 838 | regVal |= ODR_XL_26Hz; 839 | break; 840 | case 52: 841 | regVal |= ODR_XL_52Hz; 842 | break; 843 | case 104: 844 | regVal |= ODR_XL_104Hz; 845 | break; 846 | case 208: 847 | regVal |= ODR_XL_208Hz; 848 | break; 849 | case 416: 850 | regVal |= ODR_XL_416Hz; 851 | break; 852 | case 833: 853 | regVal |= ODR_XL_833Hz; 854 | break; 855 | case 1660: 856 | regVal |= ODR_XL_1660Hz; 857 | break; 858 | case 3330: 859 | regVal |= ODR_XL_3330Hz; 860 | break; 861 | case 6660: 862 | regVal |= ODR_XL_6660Hz; 863 | break; 864 | default: 865 | break; 866 | } 867 | 868 | returnError = writeRegister(CTRL1_XL, regVal); 869 | if( returnError != IMU_SUCCESS ) 870 | return false; 871 | else 872 | return true; 873 | } 874 | 875 | // Address: 0x10, bit[7:4]: default value is: 0x00 (Power Down) 876 | // Gets the output data rate of the accelerometer checking if high performance 877 | // mode is enabled in which case the lowest possible data rate is 12.5Hz. 878 | float LSM6DSO::getAccelDataRate(){ 879 | 880 | uint8_t regVal; 881 | uint8_t highPerf; 882 | 883 | status_t returnError = readRegister(®Val, CTRL1_XL); 884 | highPerf = getAccelHighPerf(); 885 | 886 | if( returnError != IMU_SUCCESS ) 887 | return static_cast( IMU_GENERIC_ERROR ); 888 | 889 | regVal &= ~ODR_XL_MASK; 890 | 891 | switch( regVal ){ 892 | case 0: 893 | return ODR_XL_DISABLE; 894 | case ODR_XL_1_6Hz: // Can't have 1.6 and high performance mode 895 | if( highPerf == 0 ) 896 | return 12.5; 897 | return 1.6; 898 | case ODR_XL_12_5Hz: 899 | return 12.5; 900 | case ODR_XL_26Hz: 901 | return 26.0; 902 | case ODR_XL_52Hz: 903 | return 52.0; 904 | case ODR_XL_104Hz: 905 | return 104.0; 906 | case ODR_XL_208Hz: 907 | return 208.0; 908 | case ODR_XL_416Hz: 909 | return 416.0; 910 | case ODR_XL_833Hz: 911 | return 833.0; 912 | case ODR_XL_1660Hz: 913 | return 1660.0; 914 | case ODR_XL_3330Hz: 915 | return 3330.0; 916 | case ODR_XL_6660Hz: 917 | return 6660.0; 918 | default: 919 | return static_cast(IMU_GENERIC_ERROR); 920 | } 921 | 922 | } 923 | 924 | // Address: 0x15, bit[4]: default value is: 0x00 (Enabled) 925 | // Checks wheter high performance is enabled or disabled. 926 | uint8_t LSM6DSO::getAccelHighPerf(){ 927 | 928 | uint8_t regVal; 929 | status_t returnError = readRegister(®Val, CTRL6_C); 930 | 931 | if( returnError != IMU_SUCCESS ) 932 | return IMU_GENERIC_ERROR; 933 | else 934 | return ((regVal & 0x10) >> 4); 935 | 936 | } 937 | 938 | // Address: 0x17, bit[2]: default value is: 0x00 939 | // Checks whether the acclerometer is using "old" full scale or "new", see 940 | // datasheet for more information. 941 | uint8_t LSM6DSO::getAccelFullScale(){ 942 | 943 | uint8_t regVal; 944 | status_t returnError = readRegister(®Val, CTRL8_XL); 945 | 946 | if( returnError != IMU_SUCCESS ) 947 | return IMU_GENERIC_ERROR; 948 | else 949 | return ((regVal & 0x02) >> 1); 950 | } 951 | 952 | int16_t LSM6DSO::readRawAccelX() { 953 | 954 | int16_t output; 955 | status_t errorLevel = readRegisterInt16( &output, OUTX_L_A ); 956 | if( errorLevel != IMU_SUCCESS ) 957 | { 958 | if( errorLevel == IMU_ALL_ONES_WARNING ) 959 | allOnesCounter++; 960 | else 961 | nonSuccessCounter++; 962 | } 963 | return output; 964 | } 965 | 966 | float LSM6DSO::readFloatAccelX() { 967 | float output = calcAccel(readRawAccelX()); 968 | return output; 969 | } 970 | 971 | int16_t LSM6DSO::readRawAccelY() 972 | { 973 | int16_t output; 974 | status_t errorLevel = readRegisterInt16( &output, OUTY_L_A ); 975 | if( errorLevel != IMU_SUCCESS ) 976 | { 977 | if( errorLevel == IMU_ALL_ONES_WARNING ) 978 | allOnesCounter++; 979 | else 980 | nonSuccessCounter++; 981 | } 982 | return output; 983 | } 984 | 985 | float LSM6DSO::readFloatAccelY() 986 | { 987 | float output = calcAccel(readRawAccelY()); 988 | return output; 989 | } 990 | 991 | int16_t LSM6DSO::readRawAccelZ() 992 | { 993 | int16_t output; 994 | status_t errorLevel = readRegisterInt16( &output, OUTZ_L_A ); 995 | if( errorLevel != IMU_SUCCESS ) 996 | { 997 | if( errorLevel == IMU_ALL_ONES_WARNING ) 998 | allOnesCounter++; 999 | else 1000 | nonSuccessCounter++; 1001 | } 1002 | return output; 1003 | } 1004 | 1005 | float LSM6DSO::readFloatAccelZ() 1006 | { 1007 | float output = calcAccel(readRawAccelZ()); 1008 | return output; 1009 | } 1010 | 1011 | float LSM6DSO::calcAccel( int16_t input ) 1012 | { 1013 | uint8_t accelRange; 1014 | uint8_t scale; 1015 | float output; 1016 | 1017 | readRegister(&accelRange, CTRL1_XL); 1018 | scale = (accelRange >> 1) & 0x01; 1019 | accelRange = (accelRange >> 2) & (0x03); 1020 | 1021 | if( scale == 0 ) { 1022 | switch( accelRange ){ 1023 | case 0:// Register value 0: 2g 1024 | output = (static_cast(input) * (.061)) / 1000; 1025 | break; 1026 | case 1: //Register value 1 : 16g 1027 | output = (static_cast(input) * (.488)) / 1000; 1028 | break; 1029 | case 2: //Register value 2 : 4g 1030 | output = (static_cast(input) * (.122)) / 1000; 1031 | break; 1032 | case 3://Register value 3: 8g 1033 | output = (static_cast(input) * (.244)) / 1000; 1034 | break; 1035 | } 1036 | } 1037 | 1038 | if( scale == 1 ){ 1039 | switch( accelRange ){ 1040 | case 0: //Register value 0: 2g 1041 | output = (static_cast(input) * (0.061)) / 1000; 1042 | break; 1043 | case 1://Register value 1: 2g 1044 | output = (static_cast(input) * (0.061)) / 1000; 1045 | break; 1046 | case 2://Register value 2: 4g 1047 | output = (static_cast(input) * (.122)) / 1000; 1048 | break; 1049 | case 3://Register value 3: 8g 1050 | output = (static_cast(input) * (.244)) / 1000; 1051 | break; 1052 | } 1053 | } 1054 | 1055 | return output; 1056 | } 1057 | 1058 | //****************************************************************************// 1059 | // 1060 | // Gyroscope section 1061 | // 1062 | //****************************************************************************// 1063 | 1064 | // Address:CTRL2_G , bit[7:4]: default value is: 0x00. 1065 | // Sets the gyro's output data rate thereby enabling it. 1066 | bool LSM6DSO::setGyroDataRate(uint16_t rate) { 1067 | 1068 | if( rate < 0 | rate > 6660 ) 1069 | return false; 1070 | 1071 | uint8_t regVal; 1072 | status_t returnError = readRegister(®Val, CTRL2_G); 1073 | if( returnError != IMU_SUCCESS ) 1074 | return false; 1075 | 1076 | regVal &= ODR_GYRO_MASK; 1077 | 1078 | switch( rate ) { 1079 | case 0: 1080 | regVal |= ODR_GYRO_DISABLE; 1081 | break; 1082 | case 125: 1083 | regVal |= ODR_GYRO_12_5Hz; 1084 | break; 1085 | case 26: 1086 | regVal |= ODR_GYRO_26Hz; 1087 | break; 1088 | case 52: 1089 | regVal |= ODR_GYRO_52Hz; 1090 | break; 1091 | case 104: 1092 | regVal |= ODR_GYRO_104Hz; 1093 | break; 1094 | case 208: 1095 | regVal |= ODR_GYRO_208Hz; 1096 | break; 1097 | case 416: 1098 | regVal |= ODR_GYRO_416Hz; 1099 | break; 1100 | case 833: 1101 | regVal |= ODR_GYRO_833Hz; 1102 | break; 1103 | case 1660: 1104 | regVal |= ODR_GYRO_1660Hz; 1105 | break; 1106 | case 3330: 1107 | regVal |= ODR_GYRO_3330Hz; 1108 | break; 1109 | case 6660: 1110 | regVal |= ODR_GYRO_6660Hz; 1111 | break; 1112 | default: 1113 | break; 1114 | } 1115 | 1116 | returnError = writeRegister(CTRL2_G, regVal); 1117 | if( returnError != IMU_SUCCESS ) 1118 | return false; 1119 | else 1120 | return true; 1121 | } 1122 | 1123 | // Address:CTRL2_G , bit[7:4]: default value is:0x00 1124 | // Gets the gyro's data rate. A data rate of 0, implies that the gyro portion 1125 | // of the IMU is disabled. 1126 | float LSM6DSO::getGyroDataRate(){ 1127 | 1128 | uint8_t regVal; 1129 | status_t returnError = readRegister(®Val, CTRL2_G); 1130 | 1131 | if( returnError != IMU_SUCCESS ) 1132 | return static_cast(IMU_GENERIC_ERROR); 1133 | 1134 | regVal &= ~ODR_GYRO_MASK; 1135 | 1136 | switch( regVal ){ 1137 | case ODR_GYRO_DISABLE: 1138 | return 0.0; 1139 | case ODR_GYRO_12_5Hz: 1140 | return 12.5; 1141 | case ODR_GYRO_26Hz: 1142 | return 26.5; 1143 | case ODR_GYRO_52Hz: 1144 | return 52.0; 1145 | case ODR_GYRO_104Hz: 1146 | return 104.0; 1147 | case ODR_GYRO_208Hz: 1148 | return 208.0; 1149 | case ODR_GYRO_416Hz: 1150 | return 416.0; 1151 | case ODR_GYRO_833Hz: 1152 | return 833.0; 1153 | case ODR_GYRO_1660Hz: 1154 | return 1660.0; 1155 | case ODR_GYRO_3330Hz: 1156 | return 3330.0; 1157 | case ODR_GYRO_6660Hz: 1158 | return 6660.0; 1159 | default: 1160 | return static_cast(IMU_GENERIC_ERROR); 1161 | } 1162 | 1163 | } 1164 | 1165 | // Address: 0x11, bit[3:0]: default value is: 0x00 1166 | // Sets the gyroscope's range. 1167 | bool LSM6DSO::setGyroRange(uint16_t range) { 1168 | 1169 | if( range < 125| range > 2000) 1170 | return false; 1171 | 1172 | uint8_t regVal; 1173 | status_t returnError = readRegister(®Val, CTRL2_G); 1174 | if( returnError != IMU_SUCCESS ) 1175 | return false; 1176 | 1177 | regVal &= FS_G_MASK; 1178 | 1179 | switch( range ){ 1180 | case 125: 1181 | regVal |= FS_G_125dps; 1182 | break; 1183 | case 250: 1184 | regVal |= FS_G_250dps; 1185 | break; 1186 | case 500: 1187 | regVal |= FS_G_500dps; 1188 | break; 1189 | case 1000: 1190 | regVal |= FS_G_1000dps; 1191 | break; 1192 | case 2000: 1193 | regVal |= FS_G_2000dps; 1194 | break; 1195 | } 1196 | 1197 | returnError = writeRegister(CTRL2_G, regVal); 1198 | if( returnError != IMU_SUCCESS ) 1199 | return false; 1200 | else 1201 | return true; 1202 | } 1203 | 1204 | // Address: 0x11, bit[3:0]: default value is: 0x00 1205 | // Gets the gyroscope's range. 1206 | uint16_t LSM6DSO::getGyroRange(){ 1207 | 1208 | uint8_t regVal; 1209 | 1210 | status_t returnError = readRegister(®Val, CTRL2_G); 1211 | if( returnError != IMU_SUCCESS ) 1212 | return IMU_GENERIC_ERROR; 1213 | 1214 | regVal &= ~FS_G_MASK; 1215 | 1216 | switch( regVal ){ 1217 | case FS_G_125dps: 1218 | return 125; 1219 | case FS_G_250dps: 1220 | return 250; 1221 | case FS_G_500dps: 1222 | return 500; 1223 | case FS_G_1000dps: 1224 | return 1000; 1225 | case FS_G_2000dps: 1226 | return 2000; 1227 | default: 1228 | return IMU_GENERIC_ERROR; 1229 | } 1230 | } 1231 | 1232 | int16_t LSM6DSO::readRawGyroX() { 1233 | 1234 | int16_t output; 1235 | status_t errorLevel = readRegisterInt16( &output, OUTX_L_G ); 1236 | 1237 | if( errorLevel != IMU_SUCCESS ) { 1238 | if( errorLevel == IMU_ALL_ONES_WARNING ) 1239 | allOnesCounter++; 1240 | else 1241 | nonSuccessCounter++; 1242 | } 1243 | 1244 | return output; 1245 | } 1246 | 1247 | float LSM6DSO::readFloatGyroX() { 1248 | 1249 | float output = calcGyro(readRawGyroX()); 1250 | return output; 1251 | } 1252 | 1253 | int16_t LSM6DSO::readRawGyroY() { 1254 | 1255 | int16_t output; 1256 | status_t errorLevel = readRegisterInt16( &output, OUTY_L_G ); 1257 | 1258 | if( errorLevel != IMU_SUCCESS ) { 1259 | if( errorLevel == IMU_ALL_ONES_WARNING ) 1260 | allOnesCounter++; 1261 | else 1262 | nonSuccessCounter++; 1263 | } 1264 | 1265 | return output; 1266 | } 1267 | 1268 | float LSM6DSO::readFloatGyroY() { 1269 | 1270 | float output = calcGyro(readRawGyroY()); 1271 | return output; 1272 | } 1273 | 1274 | int16_t LSM6DSO::readRawGyroZ() { 1275 | 1276 | int16_t output; 1277 | status_t errorLevel = readRegisterInt16( &output, OUTZ_L_G ); 1278 | 1279 | if( errorLevel != IMU_SUCCESS ) { 1280 | if( errorLevel == IMU_ALL_ONES_WARNING ) 1281 | allOnesCounter++; 1282 | else 1283 | nonSuccessCounter++; 1284 | } 1285 | 1286 | return output; 1287 | } 1288 | 1289 | float LSM6DSO::readFloatGyroZ() { 1290 | 1291 | float output = calcGyro(readRawGyroZ()); 1292 | return output; 1293 | 1294 | } 1295 | 1296 | float LSM6DSO::calcGyro( int16_t input ) { 1297 | 1298 | uint8_t gyroRange; 1299 | uint8_t fullScale; 1300 | float output; 1301 | 1302 | readRegister(&gyroRange, CTRL2_G) ; 1303 | fullScale = (gyroRange >> 1) & 0x01; 1304 | gyroRange = (gyroRange >> 2) & 0x03; 1305 | 1306 | if( fullScale ) 1307 | output = (static_cast(input) * 4.375)/1000; 1308 | else { 1309 | switch( gyroRange ){ 1310 | case 0: 1311 | output = (static_cast(input) * 8.75)/1000; 1312 | break; 1313 | case 1: 1314 | output = (static_cast(input) * 17.50)/1000; 1315 | break; 1316 | case 2: 1317 | output = (static_cast(input) * 35)/1000; 1318 | break; 1319 | case 3: 1320 | output = (static_cast(input) * 70)/1000; 1321 | break; 1322 | } 1323 | } 1324 | 1325 | return output; 1326 | } 1327 | 1328 | //****************************************************************************// 1329 | // 1330 | // Temperature section 1331 | // 1332 | //****************************************************************************// 1333 | int16_t LSM6DSO::readRawTemp() 1334 | { 1335 | int16_t output; 1336 | readRegisterInt16( &output, OUT_TEMP_L ); 1337 | return output; 1338 | } 1339 | 1340 | float LSM6DSO::readTempC() 1341 | { 1342 | int16_t temp = (readRawTemp()); 1343 | int8_t msbTemp = (temp & 0xFF00) >> 8; 1344 | float tempFloat = static_cast(msbTemp); 1345 | float lsbTemp = temp & 0x00FF; 1346 | 1347 | lsbTemp /= 256; 1348 | 1349 | tempFloat += lsbTemp; 1350 | tempFloat += 25; //Add 25 degrees to remove offset 1351 | 1352 | return tempFloat; 1353 | 1354 | } 1355 | 1356 | float LSM6DSO::readTempF() 1357 | { 1358 | float output = readTempC(); 1359 | output = (output * 9) / 5 + 32; 1360 | 1361 | return output; 1362 | 1363 | } 1364 | 1365 | //****************************************************************************// 1366 | // 1367 | // FIFO section 1368 | // 1369 | //****************************************************************************// 1370 | 1371 | void LSM6DSO::fifoBeginSettings() { 1372 | 1373 | //Split and mask the threshold 1374 | uint8_t thresholdLByte = (imuSettings.fifoThreshold & 0x007F) >> 1; 1375 | uint8_t thresholdHByte = (imuSettings.fifoThreshold & 0x00F0) >> 7; 1376 | 1377 | //CONFIGURE FIFO_CTRL4 1378 | uint8_t tempFIFO_CTRL4; 1379 | readRegister(&tempFIFO_CTRL4, FIFO_CTRL4); 1380 | // Clear fifoMode bits 1381 | tempFIFO_CTRL4 &= 0xF8; 1382 | // Merge bits 1383 | tempFIFO_CTRL4 |= imuSettings.fifoModeWord; 1384 | if (imuSettings.gyroFifoEnabled == 1 | imuSettings.accelFifoEnabled == 1) 1385 | { 1386 | //Decimation is calculated as max rate between accel and gyro 1387 | //Clear decimation bits 1388 | tempFIFO_CTRL4 &= 0x3F; 1389 | // Merge bits 1390 | tempFIFO_CTRL4 |= (imuSettings.gyroAccelDecimation << 6); 1391 | } 1392 | 1393 | //Write the data 1394 | writeRegister(FIFO_CTRL1, thresholdLByte); 1395 | uint8_t tempVal; 1396 | tempVal = readRegister(&tempVal, FIFO_CTRL2); 1397 | // Mask threshold bytes 1398 | tempVal &= 0xFE; 1399 | // Merge bytes 1400 | tempVal |= thresholdHByte; 1401 | writeRegister(FIFO_CTRL2, tempVal); 1402 | 1403 | writeRegister(FIFO_CTRL4, tempFIFO_CTRL4); 1404 | 1405 | } 1406 | 1407 | // Address:0x0A , bit[2:0]: default value is: 0x00 (disabled). 1408 | // Sets the fifo mode. 1409 | bool LSM6DSO::setFifoMode(uint8_t mode) { 1410 | 1411 | if( mode < 0 | mode > 7) 1412 | return false; 1413 | 1414 | uint8_t regVal; 1415 | status_t returnError = readRegister(®Val, FIFO_CTRL4); 1416 | if( returnError != IMU_SUCCESS ) 1417 | return false; 1418 | 1419 | regVal &= FIFO_MODE_MASK; 1420 | regVal |= mode; 1421 | 1422 | returnError = writeRegister(FIFO_CTRL4, regVal); 1423 | if( returnError != IMU_SUCCESS ) 1424 | return false; 1425 | else 1426 | return true; 1427 | } 1428 | 1429 | // Address:0x0A , bit[2:0]: default value is: 0x00 (disabled). 1430 | // Gets the fifo mode. 1431 | uint8_t LSM6DSO::getFifoMode(){ 1432 | 1433 | uint8_t regVal; 1434 | status_t returnError = readRegister(®Val, FIFO_CTRL4); 1435 | if( returnError != IMU_SUCCESS ) 1436 | return returnError; 1437 | else 1438 | return (regVal & ~FIFO_MODE_MASK); 1439 | } 1440 | 1441 | // Address:0x07 and 0x08 , bit[7:0] bit[0]: default value is: 0x000 1442 | // This sets the number of bytes that the FIFO can hold. Maximum possible value 1443 | // is 511 1444 | bool LSM6DSO::setFifoDepth(uint16_t depth) { 1445 | 1446 | if( depth < 0 | depth > 511 ) 1447 | return false; 1448 | 1449 | uint8_t dataToWrite[2]; 1450 | uint8_t regVal; 1451 | status_t returnError = readRegister(®Val, FIFO_CTRL2); 1452 | 1453 | regVal &= 0x01; 1454 | dataToWrite[0] = depth & 0x00FF; // full byte 1455 | dataToWrite[1] = (depth & 0x0100) >> 8; //one bit 1456 | dataToWrite[1] |= regVal;// add the contents from the read 1457 | 1458 | 1459 | returnError = writeMultipleRegisters(dataToWrite, FIFO_CTRL1, 2); 1460 | if( returnError != IMU_SUCCESS ) 1461 | return false; 1462 | else 1463 | return true; 1464 | } 1465 | 1466 | // Address:0x07 and 0x08 , bit[7:0] bit[0]: default value is: 0x000 1467 | // This function gets the number of bytes that the FIFO can hold. 1468 | uint16_t LSM6DSO::getFifoDepth(){ 1469 | 1470 | uint8_t regVal[2]; 1471 | uint16_t waterMark; 1472 | status_t returnError = readMultipleRegisters(regVal, FIFO_CTRL1, 2); 1473 | if( returnError != IMU_SUCCESS ) 1474 | return IMU_GENERIC_ERROR; 1475 | 1476 | waterMark = static_cast(regVal[1]) << 8 | regVal[0]; 1477 | return waterMark; 1478 | } 1479 | 1480 | // Address: 0x07 , bit[3:0]: default value is: 0x00 1481 | // Sets the accelerometer's batch data rate for the FIFO. 1482 | bool LSM6DSO::setAccelBatchDataRate(uint16_t rate) { 1483 | 1484 | if( rate < 0 | rate > 1660 ) 1485 | return false; 1486 | 1487 | uint8_t regVal; 1488 | status_t returnError = readRegister(®Val, FIFO_CTRL3); 1489 | if( returnError != IMU_SUCCESS ) 1490 | return false; 1491 | 1492 | regVal &= FIFO_BDR_ACC_MASK; 1493 | 1494 | switch( rate ){ 1495 | case 0: 1496 | regVal |= FIFO_BDR_ACC_NOT_BATCHED; 1497 | break; 1498 | case 16: 1499 | regVal |= FIFO_BDR_ACC_1_6Hz; 1500 | break; 1501 | case 125: 1502 | regVal |= FIFO_BDR_ACC_12_5Hz; 1503 | break; 1504 | case 52: 1505 | regVal |= FIFO_BDR_ACC_52Hz; 1506 | break; 1507 | case 104: 1508 | regVal |= FIFO_BDR_ACC_104Hz; 1509 | break; 1510 | case 208: 1511 | regVal |= FIFO_BDR_ACC_208Hz; 1512 | break; 1513 | case 417: 1514 | regVal |= FIFO_BDR_ACC_417Hz; 1515 | break; 1516 | case 833: 1517 | regVal |= FIFO_BDR_ACC_833Hz; 1518 | break; 1519 | case 1667: 1520 | regVal |= FIFO_BDR_ACC_1667Hz; 1521 | break; 1522 | case 3333: 1523 | regVal |= FIFO_BDR_ACC_3333Hz; 1524 | break; 1525 | case 6667: 1526 | regVal |= FIFO_BDR_ACC_6667Hz; 1527 | break; 1528 | default: 1529 | FIFO_BDR_ACC_NOT_BATCHED; 1530 | } 1531 | 1532 | returnError = writeRegister(FIFO_CTRL3, regVal); 1533 | if( returnError != IMU_SUCCESS ) 1534 | return false; 1535 | else 1536 | return true; 1537 | } 1538 | 1539 | // Address: 0x07 , bit[3:0]: default value is: 0x00 1540 | // Gets the accelerometer's batch data rate for the FIFO. 1541 | float LSM6DSO::getAccelBatchDataRate() { 1542 | 1543 | uint8_t regVal; 1544 | status_t returnError = readRegister(®Val, FIFO_CTRL3); 1545 | if( returnError != IMU_SUCCESS ) 1546 | return static_cast(IMU_GENERIC_ERROR); 1547 | 1548 | regVal &= ~FIFO_BDR_ACC_MASK; 1549 | 1550 | switch( regVal ){ 1551 | case FIFO_BDR_ACC_NOT_BATCHED: 1552 | return 0.0; 1553 | case FIFO_BDR_ACC_1_6Hz: 1554 | return 1.6; 1555 | case FIFO_BDR_ACC_12_5Hz: 1556 | return 12.5; 1557 | case FIFO_BDR_ACC_52Hz: 1558 | return 52.0; 1559 | case FIFO_BDR_ACC_104Hz: 1560 | return 104.0; 1561 | case FIFO_BDR_ACC_208Hz: 1562 | return 208.0; 1563 | case FIFO_BDR_ACC_417Hz: 1564 | return 417.0; 1565 | case FIFO_BDR_ACC_833Hz: 1566 | return 833.0; 1567 | case FIFO_BDR_ACC_1667Hz: 1568 | return 1667.0; 1569 | case FIFO_BDR_ACC_3333Hz: 1570 | return 3333.0; 1571 | case FIFO_BDR_ACC_6667Hz: 1572 | return 6667.0; 1573 | default: 1574 | return static_cast(IMU_GENERIC_ERROR); 1575 | } 1576 | 1577 | } 1578 | 1579 | // Address: 0x07 , bit[7:4]: default value is: 0x00 1580 | // Sets the gyroscope's batch data rate for the FIFO. 1581 | bool LSM6DSO::setGyroBatchDataRate(uint16_t rate) { 1582 | 1583 | if( rate < 0 | rate > 6667 ) 1584 | return false; 1585 | 1586 | uint8_t regVal; 1587 | status_t returnError = readRegister(®Val, FIFO_CTRL3); 1588 | if( returnError != IMU_SUCCESS ) 1589 | return false; 1590 | 1591 | regVal &= FIFO_BDR_GYRO_MASK; 1592 | 1593 | switch( rate ){ 1594 | case 0: 1595 | regVal |= FIFO_BDR_GYRO_NOT_BATCHED; 1596 | break; 1597 | case 65: 1598 | regVal |= FIFO_BDR_GYRO_6_5Hz; 1599 | break; 1600 | case 125: 1601 | regVal |= FIFO_BDR_GYRO_12_5Hz; 1602 | break; 1603 | case 52: 1604 | regVal |= FIFO_BDR_GYRO_52Hz; 1605 | break; 1606 | case 104: 1607 | regVal |= FIFO_BDR_GYRO_104Hz; 1608 | break; 1609 | case 208: 1610 | regVal |= FIFO_BDR_GYRO_208Hz; 1611 | break; 1612 | case 417: 1613 | regVal |= FIFO_BDR_GYRO_417Hz; 1614 | break; 1615 | case 833: 1616 | regVal |= FIFO_BDR_GYRO_833Hz; 1617 | break; 1618 | case 1667: 1619 | regVal |= FIFO_BDR_GYRO_1667Hz; 1620 | break; 1621 | case 3333: 1622 | regVal |= FIFO_BDR_GYRO_3333Hz; 1623 | break; 1624 | case 6667: 1625 | regVal |= FIFO_BDR_GYRO_6667Hz; 1626 | break; 1627 | default: 1628 | FIFO_BDR_GYRO_NOT_BATCHED; 1629 | } 1630 | 1631 | returnError = writeRegister(FIFO_CTRL3, regVal); 1632 | if( returnError != IMU_SUCCESS ) 1633 | return false; 1634 | else 1635 | return true; 1636 | } 1637 | 1638 | // Address: 0x07 , bit[7:4]: default value is: 0x00 1639 | // Gets the gyroscope's batch data rate for the FIFO. 1640 | float LSM6DSO::getGyroBatchDataRate() { 1641 | 1642 | uint8_t regVal; 1643 | status_t returnError = readRegister(®Val, FIFO_CTRL3); 1644 | if( returnError != IMU_SUCCESS ) 1645 | return static_cast(IMU_GENERIC_ERROR); 1646 | 1647 | regVal &= ~FIFO_BDR_GYRO_MASK; 1648 | 1649 | switch( regVal ){ 1650 | case FIFO_BDR_GYRO_NOT_BATCHED: 1651 | return 0.0; 1652 | case FIFO_BDR_GYRO_6_5Hz: 1653 | return 6.5; 1654 | case FIFO_BDR_GYRO_12_5Hz: 1655 | return 12.5; 1656 | case FIFO_BDR_GYRO_52Hz: 1657 | return 52.0; 1658 | case FIFO_BDR_GYRO_104Hz: 1659 | return 104.0; 1660 | case FIFO_BDR_GYRO_208Hz: 1661 | return 208.0; 1662 | case FIFO_BDR_GYRO_417Hz: 1663 | return 417.0; 1664 | case FIFO_BDR_GYRO_833Hz: 1665 | return 833.0; 1666 | case FIFO_BDR_GYRO_1667Hz: 1667 | return 1667.0; 1668 | case FIFO_BDR_GYRO_3333Hz: 1669 | return 3333.0; 1670 | case FIFO_BDR_GYRO_6667Hz: 1671 | return 6667.0; 1672 | default: 1673 | return static_cast(IMU_GENERIC_ERROR); 1674 | } 1675 | 1676 | } 1677 | 1678 | void LSM6DSO::fifoClear() { 1679 | //Drain the fifo data and dump it 1680 | 1681 | } 1682 | 1683 | fifoData LSM6DSO::fifoRead() { 1684 | //Pull the last data from the fifo 1685 | uint8_t tempTagByte; 1686 | int16_t tempData; 1687 | fifoData tempFifoData; 1688 | 1689 | status_t returnError = readRegister(&tempTagByte, FIFO_DATA_OUT_TAG); 1690 | tempTagByte &= 0xF8; 1691 | tempTagByte = tempTagByte >> 3; 1692 | 1693 | if( returnError != IMU_SUCCESS ){ 1694 | tempFifoData.fifoTag = IMU_GENERIC_ERROR; 1695 | return tempFifoData; 1696 | } 1697 | 1698 | 1699 | tempFifoData.fifoTag = tempTagByte; 1700 | 1701 | if( tempTagByte == ACCELEROMETER_DATA | 1702 | tempTagByte == ACCELERTOMETER_DATA_T_1 | 1703 | tempTagByte == ACCELERTOMETER_DATA_T_2 | 1704 | tempTagByte == ACCELERTOMETER_DATA_2xC | 1705 | tempTagByte == ACCELERTOMETER_DATA_3xC) { 1706 | 1707 | readRegisterInt16(&tempData, FIFO_DATA_OUT_X_L); 1708 | tempFifoData.xAccel = calcAccel(tempData); 1709 | readRegisterInt16(&tempData, FIFO_DATA_OUT_Y_L); 1710 | tempFifoData.yAccel = calcAccel(tempData); 1711 | readRegisterInt16(&tempData, FIFO_DATA_OUT_Z_L); 1712 | tempFifoData.zAccel = calcAccel(tempData); 1713 | } 1714 | 1715 | 1716 | if( tempTagByte == GYROSCOPE_DATA | 1717 | tempTagByte == GYRO_DATA_T_1 | 1718 | tempTagByte == GYRO_DATA_T_2 | 1719 | tempTagByte == GYRO_DATA_2xC | 1720 | tempTagByte == GYRO_DATA_3xC) { 1721 | 1722 | readRegisterInt16(&tempData, FIFO_DATA_OUT_X_L); 1723 | tempFifoData.xGyro = calcGyro(tempData); 1724 | readRegisterInt16(&tempData, FIFO_DATA_OUT_Y_L); 1725 | tempFifoData.yGyro = calcGyro(tempData); 1726 | readRegisterInt16(&tempData, FIFO_DATA_OUT_Z_L); 1727 | tempFifoData.zGyro = calcGyro(tempData); 1728 | } 1729 | 1730 | 1731 | if( tempTagByte == TEMPERATURE_DATA ){ 1732 | readRegisterInt16(&tempData, FIFO_DATA_OUT_X_L); 1733 | //tempFifoData.temperature = tempData; 1734 | } 1735 | 1736 | return tempFifoData; 1737 | 1738 | } 1739 | 1740 | uint16_t LSM6DSO::getFifoStatus() { 1741 | 1742 | uint8_t regVal; 1743 | int16_t numBytes; 1744 | 1745 | readRegisterInt16(&numBytes, FIFO_STATUS1); 1746 | numBytes &= 0x03FF; 1747 | 1748 | return numBytes; 1749 | 1750 | } 1751 | 1752 | void LSM6DSO::fifoEnd() { 1753 | // turn off the fifo 1754 | writeRegister(FIFO_STATUS1, 0x00); //Disable 1755 | } 1756 | 1757 | // Address: 0x04 , bit[3]: default value is: 0x00 (disabled) 1758 | // Enables the pedometer functionality of the IMU. 1759 | bool LSM6DSO::enablePedometer(bool enable) { 1760 | 1761 | uint8_t regVal; 1762 | status_t returnError = readRegister(®Val, EMB_FUNC_EN_A); 1763 | if( returnError != IMU_SUCCESS ) 1764 | return false; 1765 | 1766 | regVal &= PEDO_MASK; 1767 | regVal |= enable; 1768 | 1769 | returnError = writeRegister(EMB_FUNC_EN_A, regVal); 1770 | if( returnError != IMU_SUCCESS ) 1771 | return false; 1772 | else 1773 | return true; 1774 | } 1775 | 1776 | // Address: 0x04 , bit[3]: default value is: 0x00 1777 | // Checks the state of the pedometer. 1778 | uint8_t LSM6DSO::getPedometer() { 1779 | 1780 | uint8_t regVal; 1781 | status_t returnError = readRegister(®Val, EMB_FUNC_EN_A); 1782 | if( returnError != IMU_SUCCESS ) 1783 | return false; 1784 | 1785 | regVal &= ~PEDO_MASK; 1786 | if( regVal == PEDO_ENABLED ) 1787 | return true; 1788 | else 1789 | return false; 1790 | } 1791 | 1792 | // Address: 0x62 and 0x63 , bit[7:0] 1793 | // Gets the amount of steps taken. 1794 | uint8_t LSM6DSO::getSteps(){ 1795 | 1796 | int16_t steps; 1797 | status_t returnError = readRegisterInt16(&steps, STEP_COUNTER_L); 1798 | if( returnError != IMU_SUCCESS ) 1799 | return returnError; 1800 | else 1801 | return steps; 1802 | 1803 | } 1804 | 1805 | // Address:0x64 , bit[8]: default value is: 0x00 1806 | // Resets the number of steps held in the STEP COUNTER registers. 1807 | bool LSM6DSO::resetSteps() { 1808 | 1809 | uint8_t regVal; 1810 | status_t returnError = readRegister(®Val, EMB_FUNC_SRC); 1811 | if( returnError != IMU_SUCCESS ) 1812 | return false; 1813 | 1814 | regVal |= PEDO_RST_STEP_ENABLED; 1815 | 1816 | returnError = writeRegister(EMB_FUNC_SRC, regVal); 1817 | if( returnError != IMU_SUCCESS ) 1818 | return false; 1819 | else 1820 | return true; 1821 | } 1822 | 1823 | // Address: 0x56 and 0x58, bit[3:1] and bit[7]: default value is: 0x00 1824 | // Enables the single tap interrupts, as well as the direction that initiates 1825 | // the interrupt: X, Y, Z, or some combination of all three. 1826 | bool LSM6DSO::enableTap(bool enable, bool xEnable, bool yEnable, bool zEnable) { 1827 | 1828 | uint8_t regVal; 1829 | status_t returnError = readRegister(®Val, TAP_CFG2); 1830 | if( returnError != IMU_SUCCESS ) 1831 | return false; 1832 | 1833 | regVal &= INTERRUPTS_MASK; 1834 | if( enable ) 1835 | regVal |= INTERRUPTS_ENABLED; 1836 | else 1837 | regVal |= INTERRUPTS_DISABLED; 1838 | 1839 | returnError = writeRegister(regVal, TAP_CFG2); 1840 | if( returnError != IMU_SUCCESS ) 1841 | return false; 1842 | 1843 | returnError = readRegister(®Val, TAP_CFG0); 1844 | if( returnError != IMU_SUCCESS ) 1845 | return false; 1846 | 1847 | regVal &= TAP_INTERRUPT_MASK; 1848 | 1849 | if( xEnable ) 1850 | regVal |= TAP_X_EN_ENABLED; 1851 | else 1852 | regVal |= TAP_X_EN_DISABLED; 1853 | 1854 | if( yEnable ) 1855 | regVal |= TAP_Y_EN_ENABLED; 1856 | else 1857 | regVal |= TAP_X_EN_DISABLED; 1858 | 1859 | if( zEnable ) 1860 | regVal |= TAP_Z_EN_ENABLED; 1861 | else 1862 | regVal |= TAP_X_EN_DISABLED; 1863 | 1864 | returnError = writeRegister(TAP_CFG0, regVal); 1865 | if( returnError != IMU_SUCCESS ) 1866 | return false; 1867 | else 1868 | return true; 1869 | } 1870 | 1871 | // Address: 0x57, bit[7:5]: default value is: 0x00 1872 | // Sets the direction priority for tap detection e.g. an X direction tap is 1873 | // prioritized over a Y-direction tap etc. 1874 | bool LSM6DSO::setTapDirPrior(uint8_t prior) { 1875 | 1876 | if( prior < 0 | prior > 0x08 ) 1877 | return false; 1878 | 1879 | uint8_t regVal; 1880 | status_t returnError = readRegister(®Val, TAP_CFG1); 1881 | if( returnError != IMU_SUCCESS ) 1882 | return false; 1883 | 1884 | regVal &= TAP_PRIORITY_MASK; 1885 | 1886 | switch( prior ){ 1887 | case TAP_PRIORITY_XYZ: 1888 | regVal |= TAP_PRIORITY_XYZ; 1889 | break; 1890 | case TAP_PRIORITY_YXZ: 1891 | regVal |= TAP_PRIORITY_YXZ; 1892 | break; 1893 | case TAP_PRIORITY_XZY: 1894 | regVal |= TAP_PRIORITY_XZY; 1895 | break; 1896 | case TAP_PRIORITY_ZYX: 1897 | regVal |= TAP_PRIORITY_ZYX; 1898 | break; 1899 | case TAP_PRIORITY_YZX: 1900 | regVal |= TAP_PRIORITY_YZX; 1901 | break; 1902 | case TAP_PRIORITY_ZXY: 1903 | regVal |= TAP_PRIORITY_ZXY; 1904 | break; 1905 | default: 1906 | break; 1907 | } 1908 | 1909 | returnError = writeRegister(TAP_CFG1, regVal); 1910 | if( returnError != IMU_SUCCESS ) 1911 | return false; 1912 | else 1913 | return true; 1914 | } 1915 | 1916 | // Address: 0x57, bit[7:5]: default value is: 0x00 1917 | // Sets the direction priority for tap detection e.g. an X direction tap is 1918 | // prioritized over a Y-direction tap etc. 1919 | uint8_t LSM6DSO::getTapDirPrior(){ 1920 | 1921 | uint8_t regVal; 1922 | status_t returnError = readRegister(®Val, TAP_CFG2); 1923 | if( returnError != IMU_SUCCESS ) 1924 | return IMU_GENERIC_ERROR; 1925 | else 1926 | return (regVal & ~TAP_PRIORITY_MASK); 1927 | } 1928 | 1929 | // Address: 0x56, bit[7,0]: default value is: 0x00 1930 | // Sets the configuration that clears the tap interrupt upon reading the 1931 | // interrupt. 1932 | bool LSM6DSO::setTapClearOnRead(bool enable) { 1933 | 1934 | uint8_t regVal; 1935 | status_t returnError = readRegister(®Val, TAP_CFG0); 1936 | if( returnError != IMU_SUCCESS ) 1937 | return false; 1938 | 1939 | regVal &= 0x7E; 1940 | 1941 | if( enable ) { 1942 | regVal |= LIR_ENABLED; 1943 | regVal |= INT_CLR_ON_READ_IMMEDIATE; 1944 | } 1945 | 1946 | regVal |= 0x08; // remove- brute force 1947 | 1948 | returnError = writeRegister(TAP_CFG0, regVal); 1949 | if( returnError != IMU_SUCCESS ) 1950 | return false; 1951 | else 1952 | return true; 1953 | 1954 | } 1955 | 1956 | // Address: 0x56, bit[7,0]: default value is: 0x00 1957 | // Gets the configuration that clears the tap interrupt upon reading the 1958 | // interrupt. 1959 | uint8_t LSM6DSO::getTapClearOnRead() { 1960 | 1961 | uint8_t regVal; 1962 | status_t returnError = readRegister(®Val, TAP_CFG0); 1963 | if( returnError != IMU_SUCCESS ) 1964 | return IMU_GENERIC_ERROR; 1965 | else 1966 | return regVal &= ~0x7E; 1967 | 1968 | } 1969 | 1970 | // Address:0x64 , bit[6]: default value is: 0x00 1971 | // Checks if a step has been detected. 1972 | bool LSM6DSO::listenStep() { 1973 | 1974 | uint8_t regVal; 1975 | readRegister(®Val, EMB_FUNC_SRC); 1976 | regVal &= ~STEP_DETECED_MASK; 1977 | 1978 | if( regVal ) 1979 | return true; 1980 | else 1981 | return false; 1982 | } 1983 | 1984 | // Address: 0x5E , bit[7:0]: default value is: 0x00 1985 | // Routes the given interrupt to hardware pin one. 1986 | bool LSM6DSO::routeHardInterOne(uint8_t interrupt) { 1987 | 1988 | if( interrupt < 0 | interrupt > 0x80 ) 1989 | return false; 1990 | 1991 | uint8_t regVal; 1992 | status_t returnError = readRegister(®Val, MD1_CFG); 1993 | 1994 | regVal &= ~interrupt; //Preserve all but the one to set 1995 | regVal |= interrupt; 1996 | regVal = INT1_SINGLE_TAP_ENABLED;// remove 1997 | 1998 | returnError = writeRegister(MD1_CFG, regVal); 1999 | if( returnError != IMU_SUCCESS ) 2000 | return false; 2001 | else 2002 | return true; 2003 | } 2004 | 2005 | // Address: 0x5F , bit[7:0]: default value is: 0x00 2006 | // Routes the given interrupt to hardware pin two. 2007 | bool LSM6DSO::routeHardInterTwo(uint8_t interrupt) { 2008 | 2009 | if( interrupt < 0 | interrupt > 0x80 ) 2010 | return false; 2011 | 2012 | uint8_t regVal; 2013 | status_t returnError = readRegister(®Val, MD2_CFG); 2014 | 2015 | regVal &= ~interrupt; //Preserve all but the one to set 2016 | regVal |= interrupt; 2017 | 2018 | returnError = writeRegister(MD2_CFG, regVal); 2019 | if( returnError != IMU_SUCCESS ) 2020 | return false; 2021 | else 2022 | return true; 2023 | } 2024 | 2025 | // Address: 0x12 , bit[4]: default value is: 0x01 2026 | // Sets register iteration when making multiple reads. 2027 | bool LSM6DSO::setIncrement(bool enable) { 2028 | 2029 | uint8_t regVal; 2030 | status_t returnError = readRegister(®Val, CTRL3_C); 2031 | if( returnError != IMU_SUCCESS ) 2032 | return false; 2033 | 2034 | regVal &= 0xFD; 2035 | regVal |= IF_INC_ENABLED; 2036 | 2037 | returnError = writeRegister(CTRL3_C, regVal); 2038 | if( returnError != IMU_SUCCESS ) 2039 | return false; 2040 | else 2041 | return true; 2042 | } 2043 | 2044 | bool LSM6DSO::softwareReset(){ 2045 | 2046 | status_t returnError = writeRegister(SW_RESET_DEVICE, CTRL3_C); 2047 | if( returnError != IMU_SUCCESS ) 2048 | return false; 2049 | else 2050 | return true; 2051 | } 2052 | 2053 | // Address:0x1A , bit[7:0]: default value is: 0x00 2054 | // This function clears the given interrupt upon reading it from the register. 2055 | uint8_t LSM6DSO::clearAllInt() { 2056 | 2057 | uint8_t regVal; 2058 | status_t returnError = readRegister(®Val, ALL_INT_SRC); 2059 | if( returnError != IMU_SUCCESS ) 2060 | return returnError; 2061 | else 2062 | return regVal; 2063 | } 2064 | 2065 | // Address:0x1C , bit[7:0]: default value is: 0x00 2066 | // This function clears the given interrupt upon reading it from the register. 2067 | uint8_t LSM6DSO::clearTapInt() { 2068 | 2069 | uint8_t regVal; 2070 | status_t returnError = readRegister(®Val, TAP_SRC); 2071 | if( returnError != IMU_SUCCESS ) 2072 | return returnError; 2073 | else 2074 | return regVal; 2075 | } 2076 | 2077 | // Address: 0x57, bit[4:0]: default value is: 0x00 2078 | // Sets the threshold for x-axis tap recognintion. 2079 | bool LSM6DSO::setXThreshold(uint8_t thresh) { 2080 | 2081 | if( thresh < 0 | thresh > 31 ) 2082 | return false; 2083 | 2084 | uint8_t regVal; 2085 | status_t returnError = readRegister(®Val, TAP_CFG1); 2086 | regVal &= 0xE0; 2087 | 2088 | regVal |= thresh; 2089 | returnError = writeRegister(TAP_CFG1, thresh); 2090 | if( returnError != IMU_SUCCESS ) 2091 | return false; 2092 | else 2093 | return true; 2094 | } 2095 | 2096 | // Address: 0x5A, bit[7:0]: default value is: 0x00 2097 | // Sets the various tap configurations. This is a broad function that just 2098 | // writes the entier register. 2099 | bool LSM6DSO::configureTap(uint8_t settings) { 2100 | 2101 | uint8_t regVal; 2102 | 2103 | status_t returnError = writeRegister(INT_DUR2, settings); 2104 | if( returnError != IMU_SUCCESS ) 2105 | return false; 2106 | else 2107 | return true; 2108 | } 2109 | -------------------------------------------------------------------------------- /src/SparkFunLSM6DSO.h: -------------------------------------------------------------------------------- 1 | /****************************************************************************** 2 | SparkFunLSM6DSO.h 3 | LSM6DSO Arduino and Teensy Driver 4 | 5 | Marshall Taylor @ SparkFun Electronics 6 | May 20, 2015 7 | https://github.com/sparkfun/LSM6DSO_Breakout 8 | https://github.com/sparkfun/SparkFun_LSM6DSO_Arduino_Library 9 | 10 | Resources: 11 | Uses Wire.h for i2c operation 12 | Uses SPI.h for SPI operation 13 | Either can be omitted if not used 14 | 15 | Development environment specifics: 16 | Arduino IDE 1.8.1 17 | Teensy loader 1.23 18 | 19 | This code is released under the [MIT License](http://opensource.org/licenses/MIT). 20 | 21 | Please review the LICENSE.md file included with this example. If you have any questions 22 | or concerns with licensing, please contact techsupport@sparkfun.com. 23 | 24 | Distributed as-is; no warranty is given. 25 | ******************************************************************************/ 26 | 27 | #ifndef __LSM6DSOIMU_H__ 28 | #define __LSM6DSOIMU_H__ 29 | 30 | #include 31 | #include 32 | #include 33 | #include 34 | 35 | #define I2C_MODE 0 36 | #define SPI_MODE 1 37 | #define SPI_READ_COMMAND 0x80 38 | #define DEFAULT_ADDRESS 0x6B 39 | #define ALT_ADDRESS 0x6A 40 | 41 | // Return values 42 | typedef enum 43 | { 44 | IMU_SUCCESS = 0x00, 45 | IMU_HW_ERROR, 46 | IMU_NOT_SUPPORTED, 47 | IMU_OUT_OF_BOUNDS, 48 | IMU_ALL_ONES_WARNING, 49 | IMU_GENERIC_ERROR = 0xFF, 50 | } status_t; 51 | 52 | // This is the core operational class of the driver. 53 | // LSM6DSOCore contains only read and write operations towards the IMU. 54 | // To use the higher level functions, use the class LSM6DSO which inherits 55 | // this class. 56 | 57 | class LSM6DSOCore 58 | { 59 | public: 60 | 61 | LSM6DSOCore(); 62 | status_t beginCore(uint8_t, TwoWire &i2cPort ); 63 | status_t beginSPICore(uint8_t, uint32_t, SPIClass &spiPort ); 64 | 65 | status_t readMultipleRegisters(uint8_t*, uint8_t, uint8_t ); 66 | status_t readRegister(uint8_t*, uint8_t); 67 | status_t readRegisterInt16(int16_t*, uint8_t); 68 | status_t writeRegister(uint8_t, uint8_t); 69 | status_t writeMultipleRegisters(uint8_t*, uint8_t, uint8_t); 70 | status_t enableEmbeddedFunctions(bool = true); 71 | 72 | SPISettings mySpiSettings; 73 | 74 | private: 75 | 76 | uint8_t commInterface; 77 | uint8_t I2CAddress; 78 | uint8_t chipSelectPin; 79 | 80 | TwoWire *_i2cPort; 81 | SPIClass *_spiPort; 82 | 83 | 84 | }; 85 | 86 | //This struct holds the settings the driver uses to do calculations 87 | struct SensorSettings { 88 | public: 89 | 90 | 91 | //Gyro settings 92 | bool gyroEnabled; 93 | uint16_t gyroRange; 94 | uint16_t gyroSampleRate; 95 | uint16_t gyroBandWidth; 96 | 97 | uint8_t gyroFifoEnabled; 98 | uint8_t gyroAccelDecimation; 99 | 100 | //Accelerometer settings 101 | bool accelEnabled; 102 | uint8_t accelODROff; 103 | uint16_t accelRange; 104 | uint16_t accelSampleRate; 105 | uint16_t accelBandWidth; 106 | 107 | uint8_t accelFifoEnabled; 108 | 109 | 110 | //Non-basic mode settings 111 | uint8_t commMode; 112 | 113 | //FIFO control data 114 | bool fifoEnabled; 115 | uint16_t fifoThreshold; 116 | int16_t fifoSampleRate; 117 | uint8_t fifoModeWord; 118 | 119 | }; 120 | 121 | struct fifoData{ 122 | public: 123 | uint8_t fifoTag; 124 | float xAccel; 125 | float yAccel; 126 | float zAccel; 127 | 128 | float xGyro; 129 | float yGyro; 130 | float zGyro; 131 | 132 | float temperatureC; 133 | float temperatureF; 134 | }; 135 | 136 | 137 | 138 | //This is the highest level class of the driver. 139 | //LSM6DSO inherits LSM6DSOcore and makes use of the beginCore() 140 | //method through it's own begin() method. It also contains the 141 | //settings struct to hold user settings. 142 | 143 | #define ACCEL_DATA_READY 0x01 144 | #define GYRO_DATA_READY 0x02 145 | #define TEMP_DATA_READY 0x04 146 | #define ALL_DATA_READY 0x07 147 | 148 | #define BASIC_SETTINGS 0x00 149 | #define SOFT_INT_SETTINGS 0x01 150 | #define HARD_INT_SETTINGS 0x02 151 | #define FIFO_SETTINGS 0x03 152 | #define PEDOMETER_SETTINGS 0x04 153 | #define TAP_SETTINGS 0x05 154 | #define FREE_FALL_SETTINGS 0x06 155 | 156 | class LSM6DSO : public LSM6DSOCore 157 | { 158 | public: 159 | //IMU settings 160 | SensorSettings imuSettings; 161 | 162 | //Error checking 163 | uint16_t allOnesCounter; 164 | uint16_t nonSuccessCounter; 165 | 166 | LSM6DSO(); 167 | bool begin(uint8_t deviceAddress = DEFAULT_ADDRESS, TwoWire &i2cPort = Wire); 168 | bool beginSPI(uint8_t, uint32_t spiPortSpeed = 10000000, SPIClass &spiPort = SPI ); 169 | bool initialize(uint8_t settings = BASIC_SETTINGS); 170 | status_t beginSettings(); 171 | 172 | 173 | bool setAccelRange(uint8_t) ; 174 | bool setAccelDataRate(uint16_t) ; 175 | bool setGyroDataRate(uint16_t); 176 | bool setGyroRange(uint16_t) ; 177 | bool setBlockDataUpdate(bool); 178 | bool setHighPerfAccel(bool); 179 | bool setHighPerfGyro(bool); 180 | 181 | uint8_t getAccelRange(); 182 | float getAccelDataRate(); 183 | float getGyroDataRate(); 184 | uint16_t getGyroRange(); 185 | uint8_t listenDataReady(); 186 | uint8_t getAccelFullScale(); 187 | uint8_t getAccelHighPerf(); 188 | 189 | int16_t readRawAccelX(); 190 | int16_t readRawAccelY(); 191 | int16_t readRawAccelZ(); 192 | int16_t readRawGyroX(); 193 | int16_t readRawGyroY(); 194 | int16_t readRawGyroZ(); 195 | 196 | float readFloatAccelX(); 197 | float readFloatAccelY(); 198 | float readFloatAccelZ(); 199 | float readFloatGyroX(); 200 | float readFloatGyroY(); 201 | float readFloatGyroZ(); 202 | 203 | bool setInterruptOne(uint8_t); 204 | uint8_t getInterruptOne(); 205 | bool configHardOutInt(uint8_t, uint8_t pushOrDrain = 0x00) ; 206 | bool setInterruptTwo(uint8_t); 207 | int16_t readRawTemp(); 208 | float readTempC(); 209 | float readTempF(); 210 | 211 | void fifoBeginSettings(); 212 | bool setFifoMode(uint8_t); 213 | uint8_t getFifoMode(); 214 | bool setFifoDepth(uint16_t); 215 | uint16_t getFifoDepth(); 216 | bool setAccelBatchDataRate(uint16_t); 217 | float getAccelBatchDataRate(); 218 | bool setGyroBatchDataRate(uint16_t); 219 | float getGyroBatchDataRate(); 220 | void fifoClear(); 221 | fifoData fifoRead(); 222 | uint16_t getFifoStatus(); 223 | void fifoEnd(); 224 | 225 | float calcGyro( int16_t ); 226 | float calcAccel( int16_t ); 227 | 228 | bool enablePedometer(bool enable = true); 229 | uint8_t getPedometer(); 230 | uint8_t getSteps(); 231 | bool resetSteps(); 232 | bool enableTap(bool enable = true, bool xEnable = true, bool yEnable = false, bool zEnable = false) ; 233 | bool setTapDirPrior(uint8_t); 234 | uint8_t getTapDirPrior(); 235 | bool setTapClearOnRead(bool = true); 236 | uint8_t getTapClearOnRead(); 237 | uint8_t clearTapInt(); 238 | bool setXThreshold(uint8_t); 239 | bool listenStep(); 240 | bool configureTap(uint8_t); 241 | 242 | bool routeHardInterOne(uint8_t) ; 243 | bool routeHardInterTwo(uint8_t); 244 | bool setIncrement(bool enable = true) ; 245 | bool softwareReset(); 246 | uint8_t clearAllInt(); 247 | 248 | private: 249 | 250 | }; 251 | 252 | enum LSM6DSO_REGISTERS { 253 | 254 | FUNC_CFG_ACCESS = 0x01, 255 | LSM6DO_PIN_CTRL = 0x02, 256 | 257 | FIFO_CTRL1 = 0x07, 258 | FIFO_CTRL2 = 0x08, 259 | FIFO_CTRL3 = 0x09, 260 | FIFO_CTRL4 = 0x0A, 261 | 262 | COUNTER_BDR_REG1 = 0x0B, 263 | COUNTER_BDR_REG2 = 0x0C, 264 | 265 | INT1_CTRL = 0x0D, 266 | INT2_CTRL = 0x0E, 267 | WHO_AM_I_REG = 0x0F, 268 | CTRL1_XL = 0x10, 269 | CTRL2_G = 0x11, 270 | CTRL3_C = 0x12, 271 | CTRL4_C = 0x13, 272 | CTRL5_C = 0x14, 273 | CTRL6_C = 0x15, 274 | CTRL7_G = 0x16, 275 | CTRL8_XL = 0x17, 276 | CTRL9_XL = 0x18, 277 | CTRL10_C = 0x19, 278 | ALL_INT_SRC = 0x1A, 279 | WAKE_UP_SRC = 0x1B, 280 | TAP_SRC = 0x1C, 281 | D6D_SRC = 0x1D, 282 | STATUS_REG = 0x1E, 283 | OUT_TEMP_L = 0x20, 284 | OUT_TEMP_H = 0x21, 285 | OUTX_L_G = 0x22, 286 | OUTX_H_G = 0x23, 287 | OUTY_L_G = 0x24, 288 | OUTY_H_G = 0x25, 289 | OUTZ_L_G = 0x26, 290 | OUTZ_H_G = 0x27, 291 | 292 | OUTX_L_A = 0x28, 293 | OUTX_H_A = 0x29, 294 | OUTY_L_A = 0x2A, 295 | OUTY_H_A = 0x2B, 296 | OUTZ_L_A = 0x2C, 297 | OUTZ_H_A = 0x2D, 298 | 299 | EMB_FUNC_STATUS_MP = 0x35, 300 | FSM_FUNC_STATUS_A_MP = 0x36, 301 | FSM_FUNC_STATUS_B_MP = 0x37, 302 | STATUS_MASTER_MAINPAGE = 0x39, 303 | 304 | FIFO_STATUS1 = 0x3A, 305 | FIFO_STATUS2 = 0x3B, 306 | 307 | TIMESTAMP0_REG = 0x40, 308 | TIMESTAMP1_REG = 0x41, 309 | TIMESTAMP2_REG = 0x42, 310 | TIMESTAMP3_REG = 0x43, 311 | 312 | TAP_CFG0 = 0x56, 313 | TAP_CFG1 = 0x57, 314 | TAP_CFG2 = 0x58, 315 | TAP_THS_6D = 0x59, 316 | INT_DUR2 = 0x5A, 317 | WAKE_UP_THS = 0x5B, 318 | WAKE_UP_DUR = 0x5C, 319 | FREE_FALL = 0x5D, 320 | MD1_CFG = 0x5E, 321 | MD2_CFG = 0x5F, 322 | 323 | I3C_BUS_AVB = 0x62, 324 | INTERNAL_FREQ_FINE = 0x63, 325 | 326 | 327 | INT_OIS = 0x6F, 328 | CTRL1_OIS = 0x70, 329 | CTRL2_OIS = 0x71, 330 | CTRL3_OIS = 0x72, 331 | X_OFS_USR = 0x73, 332 | Y_OFS_USR = 0x74, 333 | Z_OFS_USR = 0x75, 334 | 335 | FIFO_DATA_OUT_TAG = 0x78, 336 | FIFO_DATA_OUT_X_L = 0x79, 337 | FIFO_DATA_OUT_X_H = 0x7A, 338 | FIFO_DATA_OUT_Y_L = 0x7B, 339 | FIFO_DATA_OUT_Y_H = 0x7C, 340 | FIFO_DATA_OUT_Z_L = 0x7D, 341 | FIFO_DATA_OUT_Z_H = 0x7E, 342 | 343 | }; 344 | 345 | #define GYRO_RAM_SIZE 4096 346 | 347 | enum EMBEDDED_REGISTERS { 348 | 349 | PAGE_SEL = 0x02, 350 | EMB_FUNC_EN_A = 0x04, 351 | EMB_FUNC_EN_B = 0x05, 352 | PAGE_ADDRESS = 0x08, 353 | PAGE_VALUE = 0x09, 354 | EMB_FUNC_INT1 = 0x0A, 355 | FSM_INT1_A = 0x0B, 356 | FSM_INT1_B = 0x0C, 357 | EMB_FUNC_INT2 = 0x0E, 358 | FSM_INT2_A = 0x0F, 359 | FSM_INT2_B = 0x10, 360 | EMB_FUNC_STATUS = 0x12, 361 | FSM_STATUS_A = 0x13, 362 | FSM_STATUS_B = 0x14, 363 | PAGE_RW = 0x17, 364 | // RESERVED = 0x18-0x43, 365 | EMB_FUNC_FIFO_CFG = 0x44, 366 | FSM_ENABLE_A = 0x46, 367 | FSM_ENABLE_B = 0x47, 368 | FSM_LONG_COUNTER_L = 0x48, 369 | FSM_LONG_COUNTER_H = 0x49, 370 | FSM_LONG_COUNTER_CLEAR = 0x4A, 371 | FSM_OUTS1 = 0x4C, 372 | FSM_OUTS2 = 0x4D, 373 | FSM_OUTS3 = 0x4E, 374 | FSM_OUTS4 = 0x4F, 375 | FSM_OUTS5 = 0x50, 376 | FSM_OUTS6 = 0x51, 377 | FSM_OUTS7 = 0x52, 378 | FSM_OUTS8 = 0x53, 379 | FSM_OUTS9 = 0x54, 380 | FSM_OUTS10 = 0x55, 381 | FSM_OUTS11 = 0x56, 382 | FSM_OUTS12 = 0x57, 383 | FSM_OUTS13 = 0x58, 384 | FSM_OUTS14 = 0x59, 385 | FSM_OUTS15 = 0x5A, 386 | FSM_OUTS16 = 0x5B, 387 | //RESERVED = 0x5E 388 | EMB_FUNC_ODR_CFG_B = 0x5F, 389 | STEP_COUNTER_L = 0x62, 390 | STEP_COUNTER_H = 0x63, 391 | EMB_FUNC_SRC = 0x64, 392 | EMB_FUNC_INIT_A = 0x66, 393 | EMB_FUNC_INIT_B = 0x67 394 | 395 | }; 396 | 397 | // Fifo Tags - not a complete list. 398 | typedef enum { 399 | 400 | GYROSCOPE_DATA = 0x01, 401 | ACCELEROMETER_DATA, 402 | TEMPERATURE_DATA, 403 | TIMESTAMP_DATA, 404 | CFG_CHANGE_DATA, 405 | ACCELERTOMETER_DATA_T_2, 406 | ACCELERTOMETER_DATA_T_1, 407 | ACCELERTOMETER_DATA_2xC, 408 | ACCELERTOMETER_DATA_3xC, 409 | GYRO_DATA_T_2, 410 | GYRO_DATA_T_1, 411 | GYRO_DATA_2xC, 412 | GYRO_DATA_3xC, 413 | 414 | } LSM6DSO_FIFO_TAGS_t; 415 | 416 | /******************************************************************************* 417 | * Register : FIFO_CTRL2 418 | * Address : 0x08 419 | * Bit Group Name: STOP_ON_WTM 420 | * Permission : RW 421 | *******************************************************************************/ 422 | typedef enum { 423 | FIFO_STOP_ON_WTM_DISABLED = 0x00, 424 | FIFO_STOP_ON_WTM_ENABLED = 0x01, 425 | FIFO_STOP_ON_WTM_MASK = 0x7F 426 | } LSM6DSO_STOP_ON_WTM_t; 427 | 428 | /******************************************************************************* 429 | * Register : FIFO_CTRL2 430 | * Address : 0x08 431 | * Bit Group Name: FIFO_COMPR_RT_EN 432 | * Permission : RW 433 | *******************************************************************************/ 434 | typedef enum { 435 | FIFO_COMPR_RT_DISABLED = 0x00, 436 | FIFO_COMPR_RT_ENABLE = 0x01, 437 | FIFO_COMPR_RT_MASK = 0xBF 438 | } LSM6DSO_FIFO_COMPR_RT_t; 439 | 440 | 441 | /******************************************************************************* 442 | * Register : FIFO_CTRL2 443 | * Address : 0x08 444 | * Bit Group Name: ODRCHG_EN 445 | * Permission : RW 446 | *******************************************************************************/ 447 | typedef enum { 448 | FIFO_ODRCHG_DISABLED = 0x00, 449 | FIFO_ODRCHG_ENABLE = 0x01, 450 | FIFO_ODRCHG_MASK = 0xEF 451 | } LSM6DSO_FIFO_ODRCHG_t; 452 | 453 | 454 | /******************************************************************************* 455 | * Register : FIFO_CTRL2 456 | * Address : 0x08 457 | * Bit Group Name: UNCOPTR_RATE 458 | * Permission : RW 459 | *******************************************************************************/ 460 | typedef enum { 461 | FIFO_UNCOPTR_RATE_DISABLED = 0x00, 462 | FIFO_UNCOPTR_RATE_8 = 0x02, 463 | FIFO_UNCOPTR_RATE_16 = 0x04, 464 | FIFO_UNCOPTR_RATE_32 = 0x06, 465 | FIFO_UNCOPTR_RATE_MASK = 0xF9 466 | } LSM6DSO_FIFO_UNCOPTR_RATE_t; 467 | 468 | /******************************************************************************* 469 | * Register : FIFO_CTRL3 470 | * Address : 0x09 471 | * Bit Group Name: BDR_GY 472 | * Permission : RW 473 | *******************************************************************************/ 474 | typedef enum { 475 | FIFO_BDR_GYRO_NOT_BATCHED = 0x00, 476 | FIFO_BDR_GYRO_12_5Hz = 0x10, 477 | FIFO_BDR_GYRO_26Hz = 0x20, 478 | FIFO_BDR_GYRO_52Hz = 0x30, 479 | FIFO_BDR_GYRO_104Hz = 0x40, 480 | FIFO_BDR_GYRO_208Hz = 0x50, 481 | FIFO_BDR_GYRO_417Hz = 0x60, 482 | FIFO_BDR_GYRO_833Hz = 0x70, 483 | FIFO_BDR_GYRO_1667Hz = 0x80, 484 | FIFO_BDR_GYRO_3333Hz = 0x90, 485 | FIFO_BDR_GYRO_6667Hz = 0xA0, 486 | FIFO_BDR_GYRO_6_5Hz = 0xB0, 487 | FIFO_BDR_GYRO_MASK = 0x0F 488 | } LSM6DSO_BDR_GY_FIFO_t; 489 | 490 | /******************************************************************************* 491 | * Register : FIFO_CTRL3 492 | * Address : 0x09 493 | * Bit Group Name: BDR_Xl 494 | * Permission : RW 495 | *******************************************************************************/ 496 | typedef enum { 497 | FIFO_BDR_ACC_NOT_BATCHED = 0x00, 498 | FIFO_BDR_ACC_12_5Hz = 0x01, 499 | FIFO_BDR_ACC_26Hz = 0x02, 500 | FIFO_BDR_ACC_52Hz = 0x03, 501 | FIFO_BDR_ACC_104Hz = 0x04, 502 | FIFO_BDR_ACC_208Hz = 0x05, 503 | FIFO_BDR_ACC_417Hz = 0x06, 504 | FIFO_BDR_ACC_833Hz = 0x07, 505 | FIFO_BDR_ACC_1667Hz = 0x08, 506 | FIFO_BDR_ACC_3333Hz = 0x09, 507 | FIFO_BDR_ACC_6667Hz = 0x0A, 508 | FIFO_BDR_ACC_1_6Hz = 0x0B, 509 | FIFO_BDR_ACC_MASK = 0xF0 510 | } LSM6DSO_BDR_XL_FIFO_t; 511 | 512 | 513 | /******************************************************************************* 514 | * Register : FIFO_CTRL4 515 | * Address : 0x0A 516 | * Bit Group Name: DEC_TS_BATCH 517 | * Permission : RW 518 | *******************************************************************************/ 519 | typedef enum { 520 | FIFO_TS_DEC_DISABLED = 0x00, 521 | FIFO_TS_DEC_BY_1 = 0x04, 522 | FIFO_TS_DEC_BY_8 = 0x08, 523 | FIFO_TS_DEC_BY_32 = 0x0C 524 | } LSM6DSO_FIFO_TS_DEC_t; 525 | 526 | /******************************************************************************* 527 | * Register : FIFO_CTRL4 528 | * Address : 0x0A 529 | * Bit Group Name: ODR_T_BATCH_ 530 | * Permission : RW 531 | *******************************************************************************/ 532 | typedef enum { 533 | FIFO_TEMP_ODR_DISABLE = 0x00, 534 | FIFO_TEMP_ODR_1_6 = 0x10, 535 | FIFO_TEMP_ODR_12_5 = 0x20, 536 | FIFO_TEMP_ORD_52 = 0x30 537 | } LSM6DSO_TEMPERATURE_ODR_BATCH_t; 538 | 539 | /******************************************************************************* 540 | * Register : FIFO_CTRL4 541 | * Address : 0x0A 542 | * Bit Group Name: FIFO_MODE 543 | * Permission : RW 544 | *******************************************************************************/ 545 | typedef enum { 546 | FIFO_MODE_DISABLED = 0x00, 547 | FIFO_MODE_STOP_WHEN_FULL = 0x01, 548 | FIFO_MODE_CONT_TO_FIFO = 0x03, 549 | FIFO_MODE_BYPASS_TO_CONT = 0x04, 550 | FIFO_MODE_CONTINUOUS = 0x06, 551 | FIFO_MODE_BYPASS_TO_FIFO = 0x07, 552 | FIFO_MODE_MASK = 0xF0 553 | } LSM6DSO_FIFO_MODE_t; 554 | 555 | /******************************************************************************* 556 | * Register : ORIENT_CFG_G 557 | * Address : 0x0B 558 | * Bit Group Name: ORIENT 559 | * Permission : RW 560 | *******************************************************************************/ 561 | typedef enum { 562 | ORIENT_XYZ = 0x00, 563 | ORIENT_XZY = 0x01, 564 | ORIENT_YXZ = 0x02, 565 | ORIENT_YZX = 0x03, 566 | ORIENT_ZXY = 0x04, 567 | ORIENT_ZYX = 0x05 568 | } LSM6DSO_ORIENT_t; 569 | 570 | /******************************************************************************* 571 | * Register : ORIENT_CFG_G 572 | * Address : 0x0B 573 | * Bit Group Name: SIGN_Z_G 574 | * Permission : RW 575 | *******************************************************************************/ 576 | typedef enum { 577 | SIGN_Z_G_POSITIVE = 0x00, 578 | SIGN_Z_G_NEGATIVE = 0x08, 579 | } LSM6DSO_SIGN_Z_G_t; 580 | 581 | /******************************************************************************* 582 | * Register : ORIENT_CFG_G 583 | * Address : 0x0B 584 | * Bit Group Name: SIGN_Y_G 585 | * Permission : RW 586 | *******************************************************************************/ 587 | typedef enum { 588 | SIGN_Y_G_POSITIVE = 0x00, 589 | SIGN_Y_G_NEGATIVE = 0x10, 590 | } LSM6DSO_SIGN_Y_G_t; 591 | 592 | /******************************************************************************* 593 | * Register : ORIENT_CFG_G 594 | * Address : 0x0B 595 | * Bit Group Name: SIGN_X_G 596 | * Permission : RW 597 | *******************************************************************************/ 598 | typedef enum { 599 | SIGN_X_G_POSITIVE = 0x00, 600 | SIGN_X_G_NEGATIVE = 0x20, 601 | } LSM6DSO_SIGN_X_G_t; 602 | 603 | /******************************************************************************* 604 | * Register : REFERENCE_G 605 | * Address : 0x0C 606 | * Bit Group Name: REF_G 607 | * Permission : RW 608 | *******************************************************************************/ 609 | #define REF_G_MASK 0xFF 610 | #define REF_G_POSITION 0 611 | 612 | /******************************************************************************* 613 | * Register : INT1_CTRL 614 | * Address : 0x0D 615 | * Bit Group Name: INT1_DRDY_XL 616 | * Permission : RW 617 | *******************************************************************************/ 618 | typedef enum { 619 | INT1_DRDY_XL_DISABLED = 0x00, 620 | INT1_DRDY_XL_ENABLED = 0x01, 621 | } LSM6DSO_INT1_DRDY_XL_t; 622 | 623 | /******************************************************************************* 624 | * Register : INT1_CTRL 625 | * Address : 0x0D 626 | * Bit Group Name: INT1_DRDY_G 627 | * Permission : RW 628 | *******************************************************************************/ 629 | typedef enum { 630 | INT1_DRDY_G_DISABLED = 0x00, 631 | INT1_DRDY_G_ENABLED = 0x02, 632 | } LSM6DSO_INT1_DRDY_G_t; 633 | 634 | /******************************************************************************* 635 | * Register : INT1_CTRL 636 | * Address : 0x0D 637 | * Bit Group Name: INT1_BOOT 638 | * Permission : RW 639 | *******************************************************************************/ 640 | typedef enum { 641 | INT1_BOOT_DISABLED = 0x00, 642 | INT1_BOOT_ENABLED = 0x04, 643 | } LSM6DSO_INT1_BOOT_t; 644 | 645 | /******************************************************************************* 646 | * Register : INT1_CTRL 647 | * Address : 0x0D 648 | * Bit Group Name: INT1_FULL_TH 649 | * Permission : RW 650 | *******************************************************************************/ 651 | typedef enum { 652 | INT1_FIFO_TH_DISABLED = 0x00, 653 | INT1_FIFO_TH_ENABLED = 0x08, 654 | } LSM6DSO_INT1_TH_FULL_t; 655 | 656 | /******************************************************************************* 657 | * Register : INT1_CTRL 658 | * Address : 0x0D 659 | * Bit Group Name: INT1_FIFO_OVR 660 | * Permission : RW 661 | *******************************************************************************/ 662 | typedef enum { 663 | INT1_FIFO_OVR_DISABLED = 0x00, 664 | INT1_FIFO_OVR_ENABLED = 0x10, 665 | } LSM6DSO_INT1_FIFO_OVR_t; 666 | 667 | /******************************************************************************* 668 | * Register : INT1_CTRL 669 | * Address : 0x0D 670 | * Bit Group Name: INT1_FIFO_FULL 671 | * Permission : RW 672 | *******************************************************************************/ 673 | typedef enum { 674 | INT1_FIFO_FULL_DISABLED = 0x00, 675 | INT1_FIFO_FULL_ENABLED = 0x20, 676 | } LSM6DSO_INT1_FIFO_FULL_t; 677 | 678 | /******************************************************************************* 679 | * Register : INT1_CTRL 680 | * Address : 0x0D 681 | * Bit Group Name: INT1_CNT_BDR 682 | * Permission : RW 683 | *******************************************************************************/ 684 | typedef enum { 685 | INT1_CNT_BDR_DISABLED = 0x00, 686 | INT1_CNT_BDR_ENABLED = 0x40, 687 | } LSM6DSO_INT1_CNT_BDR_t; 688 | 689 | 690 | /******************************************************************************* 691 | * Register : INT2_CTRL 692 | * Address : 0x0E 693 | * Bit Group Name: INT2_DRDY_XL 694 | * Permission : RW 695 | *******************************************************************************/ 696 | typedef enum { 697 | INT2_DRDY_XL_DISABLED = 0x00, 698 | INT2_DRDY_XL_ENABLED = 0x01, 699 | } LSM6DSO_INT2_DRDY_XL_t; 700 | 701 | /******************************************************************************* 702 | * Register : INT2_CTRL 703 | * Address : 0x0E 704 | * Bit Group Name: INT2_DRDY_G 705 | * Permission : RW 706 | *******************************************************************************/ 707 | typedef enum { 708 | INT2_DRDY_G_DISABLED = 0x00, 709 | INT2_DRDY_G_ENABLED = 0x02, 710 | } LSM6DSO_INT2_DRDY_G_t; 711 | 712 | /******************************************************************************* 713 | * Register : INT2_CTRL 714 | * Address : 0x0E 715 | * Bit Group Name: INT2_DRDY_TEMP 716 | * Permission : RW 717 | *******************************************************************************/ 718 | typedef enum { 719 | INT2_DRDY_TEMP_DISABLED = 0x00, 720 | INT2_DRDY_TEMP_ENABLED = 0x04, 721 | } LSM6DSO_INT2_DRDY_TEMP_t; 722 | 723 | /******************************************************************************* 724 | * Register : INT2_CTRL 725 | * Address : 0x0E 726 | * Bit Group Name: INT2_FIFO_TH 727 | * Permission : RW 728 | *******************************************************************************/ 729 | typedef enum { 730 | INT2_FIFO_TH_DISABLED = 0x00, 731 | INT2_FIFO_TH_ENABLED = 0x08, 732 | } LSM6DSO_INT2_FIFO_TH_t; 733 | 734 | /******************************************************************************* 735 | * Register : INT2_CTRL 736 | * Address : 0x0E 737 | * Bit Group Name: INT2_FIFO_OVR 738 | * Permission : RW 739 | *******************************************************************************/ 740 | typedef enum { 741 | INT2_FIFO_OVR_DISABLED = 0x00, 742 | INT2_FIFO_OVR_ENABLED = 0x10, 743 | } LSM6DSO_INT2_FIFO_OVR_t; 744 | 745 | /******************************************************************************* 746 | * Register : INT2_CTRL 747 | * Address : 0x0E 748 | * Bit Group Name: INT2_FIFO_FULL 749 | * Permission : RW 750 | *******************************************************************************/ 751 | typedef enum { 752 | INT2_FIFO_FULL_DISABLED = 0x00, 753 | INT2_FIFO_FULL_ENABLED = 0x20, 754 | } LSM6DSO_INT2_FIFO_FULL_t; 755 | 756 | /******************************************************************************* 757 | * Register : INT2_CTRL 758 | * Address : 0x0E 759 | * Bit Group Name: INT2_CNT_BDR 760 | * Permission : RW 761 | *******************************************************************************/ 762 | typedef enum { 763 | INT2_CNT_BDR_DISABLED = 0x00, 764 | INT2_CNT_BDR_ENABLE = 0x40, 765 | } LSM6DSO_INT2_CNT_BDR_t; 766 | 767 | /******************************************************************************* 768 | * Register : WHO_AM_I 769 | * Address : 0x0F 770 | * Bit Group Name: WHO_AM_I_BIT 771 | * Permission : RO 772 | *******************************************************************************/ 773 | #define WHO_AM_I_BIT_MASK 0xFF 774 | #define WHO_AM_I_BIT_POSITION 0 775 | 776 | 777 | /******************************************************************************* 778 | * Register : CTRL1_XL 779 | * Address : 0x10 780 | * Bits : [1] 781 | * Bit Group Name: LPF2_XL_EN 782 | * Permission : RW 783 | *******************************************************************************/ 784 | typedef enum { 785 | LPF2_XL_DISABLE = 0x00, 786 | LPF2_XL_EN = 0x02 787 | } LSM6DSO_LPF2_XL_t; 788 | 789 | /******************************************************************************* 790 | * Register : CTRL1_XL 791 | * Address : 0x10 792 | * Bits : [3:2] 793 | * Bit Group Name: FS_XL 794 | * Permission : RW 795 | *******************************************************************************/ 796 | typedef enum { 797 | FS_XL_2g = 0x00, 798 | FS_XL_16g = 0x04, 799 | FS_XL_4g = 0x08, 800 | FS_XL_8g = 0x0C, 801 | FS_XL_MASK = 0xF3 802 | } LSM6DSO_FS_XL_t; 803 | 804 | /******************************************************************************* 805 | * Register : CTRL1_XL 806 | * Address : 0x10 807 | * Bits : [7:4] 808 | * Bit Group Name: ODR_XL 809 | * Permission : RW 810 | *******************************************************************************/ 811 | typedef enum { 812 | ODR_XL_DISABLE = 0x00, 813 | ODR_XL_1_6Hz = 0xB0, // Low Power only 814 | ODR_XL_12_5Hz = 0x10, // Low Power only 815 | ODR_XL_26Hz = 0x20, // Low Power only 816 | ODR_XL_52Hz = 0x30, // Low Power only 817 | ODR_XL_104Hz = 0x40, // Normal Mode 818 | ODR_XL_208Hz = 0x50, // Normal Mode 819 | ODR_XL_416Hz = 0x60, // High performance 820 | ODR_XL_833Hz = 0x70, // High Performance 821 | ODR_XL_1660Hz = 0x80, // High Performance 822 | ODR_XL_3330Hz = 0x90, // High Performance 823 | ODR_XL_6660Hz = 0xA0, // High Performance 824 | ODR_XL_MASK = 0x0F 825 | } LSM6DSO_ODR_XL_t; 826 | 827 | /******************************************************************************* 828 | * Register : CTRL2_G 829 | * Address : 0x11 830 | * Bit : [3:2] 831 | * Bit Group Name: FS_G 832 | * Permission : RW 833 | *******************************************************************************/ 834 | typedef enum { 835 | FS_G_125dps = 0x02, 836 | FS_G_250dps = 0x00, 837 | FS_G_500dps = 0x04, 838 | FS_G_1000dps = 0x08, 839 | FS_G_2000dps = 0x0C, 840 | FS_G_MASK = 0xF0 841 | } LSM6DSO_FS_G_t; 842 | 843 | /******************************************************************************* 844 | * Register : CTRL2_G 845 | * Address : 0x11 846 | * Bit : [7:4] 847 | * Bit Group Name: ODR_G 848 | * Permission : RW 849 | *******************************************************************************/ 850 | typedef enum { 851 | ODR_GYRO_DISABLE = 0x00, 852 | ODR_GYRO_12_5Hz = 0x10, // Low Power only 853 | ODR_GYRO_26Hz = 0x20, // Low Power only 854 | ODR_GYRO_52Hz = 0x30, // Low Power only 855 | ODR_GYRO_104Hz = 0x40, // Normal Mode 856 | ODR_GYRO_208Hz = 0x50, // Normal Mode 857 | ODR_GYRO_416Hz = 0x60, // High performance 858 | ODR_GYRO_833Hz = 0x70, // High Performance 859 | ODR_GYRO_1660Hz = 0x80, // High Performance 860 | ODR_GYRO_3330Hz = 0x90, // High Performance 861 | ODR_GYRO_6660Hz = 0xA0, // High Performance 862 | ODR_GYRO_MASK = 0x0F 863 | } LSM6DSO_ODR_GYRO_G_t; 864 | 865 | /******************************************************************************* 866 | * Register : CTRL3_C 867 | * Address : 0x12 868 | * Bit Group Name: SW_RESET 869 | * Permission : RW 870 | *******************************************************************************/ 871 | typedef enum { 872 | SW_RESET_NORMAL_MODE = 0x00, 873 | SW_RESET_DEVICE = 0x01, 874 | } LSM6DSO_SW_RESET_t; 875 | 876 | /******************************************************************************* 877 | * Register : CTRL3_C 878 | * Address : 0x12 879 | * Bit Group Name: IF_INC 880 | * Permission : RW 881 | *******************************************************************************/ 882 | typedef enum { 883 | IF_INC_DISABLED = 0x00, 884 | IF_INC_ENABLED = 0x04, 885 | } LSM6DSO_IF_INC_t; 886 | 887 | /******************************************************************************* 888 | * Register : CTRL3_C 889 | * Address : 0x12 890 | * Bit Group Name: SIM 891 | * Permission : RW 892 | *******************************************************************************/ 893 | typedef enum { 894 | SIM_4_WIRE = 0x00, 895 | SIM_3_WIRE = 0x08, 896 | } LSM6DSO_SIM_t; 897 | 898 | /******************************************************************************* 899 | * Register : CTRL3_C 900 | * Address : 0x12 901 | * Bit Group Name: PP_OD 902 | * Permission : RW 903 | *******************************************************************************/ 904 | typedef enum { 905 | PP_OD_PUSH_PULL = 0x00, 906 | PP_OD_OPEN_DRAIN = 0x10, 907 | } LSM6DSO_PP_OD_t; 908 | 909 | /******************************************************************************* 910 | * Register : CTRL3_C 911 | * Address : 0x12 912 | * Bit Group Name: H_LACTIVE 913 | * Permission : RW 914 | *******************************************************************************/ 915 | typedef enum { 916 | INT_ACTIVE_HIGH = 0x00, 917 | INT_ACTIVE_LOW = 0x20, 918 | } LSM6DSO_H_LACTIVE_t; 919 | 920 | /******************************************************************************* 921 | * Register : CTRL3_C 922 | * Address : 0x12 923 | * Bit Group Name: BDU 924 | * Permission : RW 925 | *******************************************************************************/ 926 | typedef enum { 927 | BDU_CONTINUOS = 0x00, 928 | BDU_BLOCK_UPDATE = 0x40, 929 | BDU_MASK = 0xBF 930 | } LSM6DSO_BDU_t; 931 | 932 | /******************************************************************************* 933 | * Register : CTRL3_C 934 | * Address : 0x12 935 | * Bit Group Name: BOOT 936 | * Permission : RW 937 | *******************************************************************************/ 938 | typedef enum { 939 | BOOT_NORMAL_MODE = 0x00, 940 | BOOT_REBOOT_MODE = 0x80, 941 | } LSM6DSO_BOOT_t; 942 | 943 | /******************************************************************************* 944 | * Register : CTRL4_C 945 | * Address : 0x13 946 | * Bit Group Name: STOP_ON_FTH 947 | * Permission : RW 948 | *******************************************************************************/ 949 | typedef enum { 950 | STOP_ON_FTH_DISABLED = 0x00, 951 | STOP_ON_FTH_ENABLED = 0x01, 952 | } LSM6DSO_STOP_ON_FTH_t; 953 | 954 | /******************************************************************************* 955 | * Register : CTRL4_C 956 | * Address : 0x13 957 | * Bit Group Name: MODE3_EN 958 | * Permission : RW 959 | *******************************************************************************/ 960 | typedef enum { 961 | MODE3_EN_DISABLED = 0x00, 962 | MODE3_EN_ENABLED = 0x02, 963 | } LSM6DSO_MODE3_EN_t; 964 | 965 | /******************************************************************************* 966 | * Register : CTRL4_C 967 | * Address : 0x13 968 | * Bit Group Name: I2C_DISABLE 969 | * Permission : RW 970 | *******************************************************************************/ 971 | typedef enum { 972 | I2C_DISABLE_I2C_AND_SPI = 0x00, 973 | I2C_DISABLE_SPI_ONLY = 0x04, 974 | } LSM6DSO_I2C_DISABLE_t; 975 | 976 | /******************************************************************************* 977 | * Register : CTRL4_C 978 | * Address : 0x13 979 | * Bit Group Name: DRDY_MSK 980 | * Permission : RW 981 | *******************************************************************************/ 982 | typedef enum { 983 | DRDY_MSK_DISABLED = 0x00, 984 | DRDY_MSK_ENABLED = 0x08, 985 | } LSM6DSO_DRDY_MSK_t; 986 | 987 | /******************************************************************************* 988 | * Register : CTRL4_C 989 | * Address : 0x13 990 | * Bit Group Name: FIFO_TEMP_EN 991 | * Permission : RW 992 | *******************************************************************************/ 993 | typedef enum { 994 | FIFO_TEMP_EN_DISABLED = 0x00, 995 | FIFO_TEMP_EN_ENABLED = 0x10, 996 | } LSM6DSO_FIFO_TEMP_EN_t; 997 | 998 | /******************************************************************************* 999 | * Register : CTRL4_C 1000 | * Address : 0x13 1001 | * Bit Group Name: INT2_ON_INT1 1002 | * Permission : RW 1003 | *******************************************************************************/ 1004 | typedef enum { 1005 | INT2_ON_INT1_DISABLED = 0x00, 1006 | INT2_ON_INT1_ENABLED = 0x20, 1007 | } LSM6DSO_INT2_ON_INT1_t; 1008 | 1009 | /******************************************************************************* 1010 | * Register : CTRL4_C 1011 | * Address : 0x13 1012 | * Bit Group Name: SLEEP_G 1013 | * Permission : RW 1014 | *******************************************************************************/ 1015 | typedef enum { 1016 | SLEEP_G_DISABLED = 0x00, 1017 | SLEEP_G_ENABLED = 0x40, 1018 | } LSM6DSO_SLEEP_G_t; 1019 | 1020 | /******************************************************************************* 1021 | * Register : CTRL4_C 1022 | * Address : 0x13 1023 | * Bit Group Name: BW_SCAL_ODR 1024 | * Permission : RW 1025 | *******************************************************************************/ 1026 | typedef enum { 1027 | BW_SCAL_ODR_DISABLED = 0x00, 1028 | BW_SCAL_ODR_ENABLED = 0x80, 1029 | } LSM6DSO_BW_SCAL_ODR_t; 1030 | 1031 | /******************************************************************************* 1032 | * Register : CTRL5_C 1033 | * Address : 0x14 1034 | * Bit Group Name: ST_XL 1035 | * Permission : RW 1036 | *******************************************************************************/ 1037 | typedef enum { 1038 | ST_XL_NORMAL_MODE = 0x00, 1039 | ST_XL_POS_SIGN_TEST = 0x01, 1040 | ST_XL_NEG_SIGN_TEST = 0x02, 1041 | ST_XL_NA = 0x03, 1042 | } LSM6DSO_ST_XL_t; 1043 | 1044 | /******************************************************************************* 1045 | * Register : CTRL5_C 1046 | * Address : 0x14 1047 | * Bit Group Name: ST_G 1048 | * Permission : RW 1049 | *******************************************************************************/ 1050 | typedef enum { 1051 | ST_G_NORMAL_MODE = 0x00, 1052 | ST_G_POS_SIGN_TEST = 0x04, 1053 | ST_G_NA = 0x08, 1054 | ST_G_NEG_SIGN_TEST = 0x0C, 1055 | } LSM6DSO_ST_G_t; 1056 | 1057 | /******************************************************************************* 1058 | * Register : CTRL6_C 1059 | * Address : 0x15 1060 | * Bits : [2:0] 1061 | * Bit Group Name: FTYPE 1062 | * Permission : RW 1063 | *******************************************************************************/ 1064 | typedef enum { 1065 | FTYPE_ONE = 0x00, 1066 | FTYPE_TWO = 0x01, 1067 | FTYPE_THREE = 0x02, 1068 | FTYPE_FOUR = 0x03, 1069 | FTYPE_FIVE = 0x04, 1070 | FTYPE_SIX = 0x05, 1071 | FTYPE_SEVEN = 0x06, 1072 | FTYPE_EIGHT = 0x07, 1073 | FTYPE_NINE = 0x08, 1074 | FTYPE_TEN = 0x09 1075 | } LSM6DSO_FTYPE_t; 1076 | 1077 | /******************************************************************************* 1078 | * Register : CTRL6_C 1079 | * Address : 0x15 1080 | * Bit Group Name: USR_OFF_W 1081 | * Permission : RW 1082 | *******************************************************************************/ 1083 | typedef enum { 1084 | USER_OFFSET_2_10 = 0x00, 1085 | USER_OFFSET_2_6 = 0x08, 1086 | } LSM6DSO_USER_OFFSET_t; 1087 | 1088 | /******************************************************************************* 1089 | * Register : CTRL6_C 1090 | * Address : 0x15 1091 | * Bit Group Name: XL_HM_MODE 1092 | * Permission : RW 1093 | *******************************************************************************/ 1094 | typedef enum { 1095 | HIGH_PERF_ACC_ENABLE = 0x00, //Default 1096 | HIGH_PERF_ACC_DISABLE = 0x10, 1097 | } LSM6DSO_HIGH_PERF_ACC_t; 1098 | 1099 | /******************************************************************************* 1100 | * Register : CTRL6_C 1101 | * Address : 0x15 1102 | * Bits : [7:5] 1103 | * Bit Group Names: TRIG_EN, LVL1_EN, LVL2_EN 1104 | * Permission : RW 1105 | *******************************************************************************/ 1106 | typedef enum { 1107 | TRIG_MODE_EDGE = 0x80, 1108 | TRIG_MODE_TRIGGER = 0x40, 1109 | TRIG_MODE_LATCH = 0x30, 1110 | TRIG_MODE_FIFO = 0x60, 1111 | } LSM6DSO_TRIG_MODE_t; 1112 | 1113 | /******************************************************************************* 1114 | * Register : CTRL7_G 1115 | * Address : 0x16 1116 | * Bit Group Name: G_HM_MODE 1117 | * Permission : RW 1118 | *******************************************************************************/ 1119 | typedef enum { 1120 | HIGH_PERF_GYRO_ENABLE = 0x00, 1121 | HIGH_PERF_GYRO_DISABLE = 0x80 1122 | } LSM6DSO_HIGH_PERF_GYRO_t; 1123 | 1124 | /******************************************************************************* 1125 | * Register : CTRL7_G 1126 | * Address : 0x16 1127 | * Bit Group Name: HP_EN_G 1128 | * Permission : RW 1129 | *******************************************************************************/ 1130 | typedef enum { 1131 | HP_EN_DISABLED = 0x00, 1132 | HP_EN_ENABLED = 0x40, 1133 | } LSM6DSO_HP_EN_t; 1134 | 1135 | /******************************************************************************* 1136 | * Register : CTRL7_G 1137 | * Address : 0x16 1138 | * Bit Group Name: HPM_G 1139 | * Permission : RW 1140 | *******************************************************************************/ 1141 | typedef enum { 1142 | HPM_G_16mHz = 0x00, 1143 | HPM_G_65mHz = 0x20, 1144 | HPM_G_260mHz = 0x30, 1145 | HPM_G_1_04Hz = 0x40, 1146 | } LSM6DSO_HPM_G_t; 1147 | 1148 | /******************************************************************************* 1149 | * Register : CTRL8_XL 1150 | * Address : 0x17 1151 | * Bit Group Name: FDS 1152 | * Permission : RW 1153 | *******************************************************************************/ 1154 | typedef enum { 1155 | FDS_FILTER_OFF = 0x00, 1156 | FDS_FILTER_ON = 0x04, 1157 | } LSM6DSO_FDS_t; 1158 | 1159 | /******************************************************************************* 1160 | * Register : CTRL9_XL 1161 | * Address : 0x18 1162 | * Bit Group Name: XEN_XL 1163 | * Permission : RW 1164 | *******************************************************************************/ 1165 | typedef enum { 1166 | XEN_XL_DISABLED = 0x00, 1167 | XEN_XL_ENABLED = 0x08, 1168 | } LSM6DSO_XEN_XL_t; 1169 | 1170 | /******************************************************************************* 1171 | * Register : CTRL9_XL 1172 | * Address : 0x18 1173 | * Bit Group Name: YEN_XL 1174 | * Permission : RW 1175 | *******************************************************************************/ 1176 | typedef enum { 1177 | YEN_XL_DISABLED = 0x00, 1178 | YEN_XL_ENABLED = 0x10, 1179 | } LSM6DSO_YEN_XL_t; 1180 | 1181 | /******************************************************************************* 1182 | * Register : CTRL9_XL 1183 | * Address : 0x18 1184 | * Bit Group Name: ZEN_XL 1185 | * Permission : RW 1186 | *******************************************************************************/ 1187 | typedef enum { 1188 | ZEN_XL_DISABLED = 0x00, 1189 | ZEN_XL_ENABLED = 0x20, 1190 | } LSM6DSO_ZEN_XL_t; 1191 | 1192 | /******************************************************************************* 1193 | * Register : CTRL10_C 1194 | * Address : 0x19 1195 | * Bit Group Name: XEN_G 1196 | * Permission : RW 1197 | *******************************************************************************/ 1198 | typedef enum { 1199 | XEN_G_DISABLED = 0x00, 1200 | XEN_G_ENABLED = 0x08, 1201 | } LSM6DSO_XEN_G_t; 1202 | 1203 | /******************************************************************************* 1204 | * Register : CTRL10_C 1205 | * Address : 0x19 1206 | * Bit Group Name: YEN_G 1207 | * Permission : RW 1208 | *******************************************************************************/ 1209 | typedef enum { 1210 | YEN_G_DISABLED = 0x00, 1211 | YEN_G_ENABLED = 0x10, 1212 | } LSM6DSO_YEN_G_t; 1213 | 1214 | /******************************************************************************* 1215 | * Register : CTRL10_C 1216 | * Address : 0x19 1217 | * Bit Group Name: ZEN_G 1218 | * Permission : RW 1219 | *******************************************************************************/ 1220 | typedef enum { 1221 | ZEN_G_DISABLED = 0x00, 1222 | ZEN_G_ENABLED = 0x20, 1223 | } LSM6DSO_ZEN_G_t; 1224 | 1225 | /******************************************************************************* 1226 | * Register : CTRL10_C 1227 | * Address : 0x19 1228 | * Bit Group Name: FUNC_EN 1229 | * Permission : RW 1230 | *******************************************************************************/ 1231 | typedef enum { 1232 | FUNC_EN_DISABLED = 0x00, 1233 | FUNC_EN_ENABLED = 0x04, 1234 | } LSM6DSO_FUNC_EN_t; 1235 | 1236 | /******************************************************************************* 1237 | * Register : ALL_INT_SRC 1238 | * Address : 0x1A 1239 | * Permission : R 1240 | *******************************************************************************/ 1241 | typedef enum { 1242 | INT_FREE_FALL = 0x01, 1243 | INT_WAKE_UP = 0x02, 1244 | INT_SINGLE_TAP = 0x04, 1245 | INT_DOUBLE_TAP = 0x08, 1246 | INT_D6D = 0x10, 1247 | INT_SLEEP_CHANGEN = 0x20, 1248 | INT_TIMESTAMP_ENDCOUNT = 0x80, 1249 | } LSM6DSO_ALL_INT_t; 1250 | 1251 | /******************************************************************************* 1252 | * Register : MASTER_CONFIG 1253 | * Address : 0x1A 1254 | * Bit Group Name: MASTER_ON 1255 | * Permission : RW 1256 | *******************************************************************************/ 1257 | typedef enum { 1258 | MASTER_ON_DISABLED = 0x00, 1259 | MASTER_ON_ENABLED = 0x01, 1260 | } LSM6DSO_MASTER_ON_t; 1261 | 1262 | /******************************************************************************* 1263 | * Register : MASTER_CONFIG 1264 | * Address : 0x1A 1265 | * Bit Group Name: IRON_EN 1266 | * Permission : RW 1267 | *******************************************************************************/ 1268 | typedef enum { 1269 | IRON_EN_DISABLED = 0x00, 1270 | IRON_EN_ENABLED = 0x02, 1271 | } LSM6DSO_IRON_EN_t; 1272 | 1273 | /******************************************************************************* 1274 | * Register : MASTER_CONFIG 1275 | * Address : 0x1A 1276 | * Bit Group Name: PASS_THRU_MODE 1277 | * Permission : RW 1278 | *******************************************************************************/ 1279 | typedef enum { 1280 | PASS_THRU_MODE_DISABLED = 0x00, 1281 | PASS_THRU_MODE_ENABLED = 0x04, 1282 | } LSM6DSO_PASS_THRU_MODE_t; 1283 | 1284 | /******************************************************************************* 1285 | * Register : MASTER_CONFIG 1286 | * Address : 0x1A 1287 | * Bit Group Name: PULL_UP_EN 1288 | * Permission : RW 1289 | *******************************************************************************/ 1290 | typedef enum { 1291 | PULL_UP_EN_DISABLED = 0x00, 1292 | PULL_UP_EN_ENABLED = 0x08, 1293 | } LSM6DSO_PULL_UP_EN_t; 1294 | 1295 | /******************************************************************************* 1296 | * Register : MASTER_CONFIG 1297 | * Address : 0x1A 1298 | * Bit Group Name: START_CONFIG 1299 | * Permission : RW 1300 | *******************************************************************************/ 1301 | typedef enum { 1302 | START_CONFIG_XL_G_DRDY = 0x00, 1303 | START_CONFIG_EXT_INT2 = 0x10, 1304 | } LSM6DSO_START_CONFIG_t; 1305 | 1306 | /******************************************************************************* 1307 | * Register : MASTER_CONFIG 1308 | * Address : 0x1A 1309 | * Bit Group Name: DATA_VAL_SEL_FIFO 1310 | * Permission : RW 1311 | *******************************************************************************/ 1312 | typedef enum { 1313 | DATA_VAL_SEL_FIFO_XL_G_DRDY = 0x00, 1314 | DATA_VAL_SEL_FIFO_SHUB_DRDY = 0x40, 1315 | } LSM6DSO_DATA_VAL_SEL_FIFO_t; 1316 | 1317 | /******************************************************************************* 1318 | * Register : MASTER_CONFIG 1319 | * Address : 0x1A 1320 | * Bit Group Name: DRDY_ON_INT1 1321 | * Permission : RW 1322 | *******************************************************************************/ 1323 | typedef enum { 1324 | DRDY_ON_INT1_DISABLED = 0x00, 1325 | DRDY_ON_INT1_ENABLED = 0x80, 1326 | } LSM6DSO_DRDY_ON_INT1_t; 1327 | 1328 | /******************************************************************************* 1329 | * Register : WAKE_UP_SRC 1330 | * Address : 0x1B 1331 | * Bit Group Name: Z_WU 1332 | * Permission : RO 1333 | *******************************************************************************/ 1334 | typedef enum { 1335 | Z_WU_NOT_DETECTED = 0x00, 1336 | Z_WU_DETECTED = 0x01, 1337 | } LSM6DSO_Z_WU_t; 1338 | 1339 | /******************************************************************************* 1340 | * Register : WAKE_UP_SRC 1341 | * Address : 0x1B 1342 | * Bit Group Name: Y_WU 1343 | * Permission : RO 1344 | *******************************************************************************/ 1345 | typedef enum { 1346 | Y_WU_NOT_DETECTED = 0x00, 1347 | Y_WU_DETECTED = 0x02, 1348 | } LSM6DSO_Y_WU_t; 1349 | 1350 | /******************************************************************************* 1351 | * Register : WAKE_UP_SRC 1352 | * Address : 0x1B 1353 | * Bit Group Name: X_WU 1354 | * Permission : RO 1355 | *******************************************************************************/ 1356 | typedef enum { 1357 | X_WU_NOT_DETECTED = 0x00, 1358 | X_WU_DETECTED = 0x04, 1359 | } LSM6DSO_X_WU_t; 1360 | 1361 | /******************************************************************************* 1362 | * Register : WAKE_UP_SRC 1363 | * Address : 0x1B 1364 | * Bit Group Name: WU_EV_STATUS 1365 | * Permission : RO 1366 | *******************************************************************************/ 1367 | typedef enum { 1368 | WU_EV_STATUS_NOT_DETECTED = 0x00, 1369 | WU_EV_STATUS_DETECTED = 0x08, 1370 | } LSM6DSO_WU_EV_STATUS_t; 1371 | 1372 | /******************************************************************************* 1373 | * Register : WAKE_UP_SRC 1374 | * Address : 0x1B 1375 | * Bit Group Name: SLEEP_EV_STATUS 1376 | * Permission : RO 1377 | *******************************************************************************/ 1378 | typedef enum { 1379 | SLEEP_EV_STATUS_NOT_DETECTED = 0x00, 1380 | SLEEP_EV_STATUS_DETECTED = 0x10, 1381 | } LSM6DSO_SLEEP_EV_STATUS_t; 1382 | 1383 | /******************************************************************************* 1384 | * Register : WAKE_UP_SRC 1385 | * Address : 0x1B 1386 | * Bit Group Name: FF_EV_STATUS 1387 | * Permission : RO 1388 | *******************************************************************************/ 1389 | typedef enum { 1390 | FF_EV_STATUS_NOT_DETECTED = 0x00, 1391 | FF_EV_STATUS_DETECTED = 0x20, 1392 | } LSM6DSO_FF_EV_STATUS_t; 1393 | 1394 | /******************************************************************************* 1395 | * Register : TAP_SRC 1396 | * Address : 0x1C 1397 | * Bit Group Name: Z_TAP 1398 | * Permission : RO 1399 | *******************************************************************************/ 1400 | typedef enum { 1401 | Z_TAP_NOT_DETECTED = 0x00, 1402 | Z_TAP_DETECTED = 0x01, 1403 | } LSM6DSO_Z_TAP_t; 1404 | 1405 | /******************************************************************************* 1406 | * Register : TAP_SRC 1407 | * Address : 0x1C 1408 | * Bit Group Name: Y_TAP 1409 | * Permission : RO 1410 | *******************************************************************************/ 1411 | typedef enum { 1412 | Y_TAP_NOT_DETECTED = 0x00, 1413 | Y_TAP_DETECTED = 0x02, 1414 | } LSM6DSO_Y_TAP_t; 1415 | 1416 | /******************************************************************************* 1417 | * Register : TAP_SRC 1418 | * Address : 0x1C 1419 | * Bit Group Name: X_TAP 1420 | * Permission : RO 1421 | *******************************************************************************/ 1422 | typedef enum { 1423 | X_TAP_NOT_DETECTED = 0x00, 1424 | X_TAP_DETECTED = 0x04, 1425 | } LSM6DSO_X_TAP_t; 1426 | 1427 | /******************************************************************************* 1428 | * Register : TAP_SRC 1429 | * Address : 0x1C 1430 | * Bit Group Name: TAP_SIGN 1431 | * Permission : RO 1432 | *******************************************************************************/ 1433 | typedef enum { 1434 | TAP_SIGN_POS_SIGN = 0x00, 1435 | TAP_SIGN_NEG_SIGN = 0x08, 1436 | } LSM6DSO_TAP_SIGN_t; 1437 | 1438 | /******************************************************************************* 1439 | * Register : TAP_SRC 1440 | * Address : 0x1C 1441 | * Bit Group Name: DOUBLE_TAP 1442 | * Permission : RO 1443 | *******************************************************************************/ 1444 | typedef enum { 1445 | DOUBLE_TAP_NOT_DETECTED = 0x00, 1446 | DOUBLE_TAP_DETECTED = 0x10, 1447 | } LSM6DSO_DOUBLE_TAP_EV_STATUS_t; 1448 | 1449 | /******************************************************************************* 1450 | * Register : TAP_SRC 1451 | * Address : 0x1C 1452 | * Bit Group Name: SINGLE_TAP 1453 | * Permission : RO 1454 | *******************************************************************************/ 1455 | typedef enum { 1456 | SINGLE_TAP_NOT_DETECTED = 0x00, 1457 | SINGLE_TAP_DETECTED = 0x20, 1458 | } LSM6DSO_SINGLE_TAP_EV_STATUS_t; 1459 | 1460 | /******************************************************************************* 1461 | * Register : TAP_SRC 1462 | * Address : 0x1C 1463 | * Bit Group Name: TAP_EV_STATUS 1464 | * Permission : RO 1465 | *******************************************************************************/ 1466 | typedef enum { 1467 | TAP_EV_NOT_DETECTED = 0x00, 1468 | TAP_EV_DETECTED = 0x40, 1469 | } LSM6DSO_TAP_EV_STATUS_t; 1470 | 1471 | /******************************************************************************* 1472 | * Register : D6D_SRC 1473 | * Address : 0x1D 1474 | * Bit Group Name: DSD_XL 1475 | * Permission : RO 1476 | *******************************************************************************/ 1477 | typedef enum { 1478 | DSD_XL_NOT_DETECTED = 0x00, 1479 | DSD_XL_DETECTED = 0x01, 1480 | } LSM6DSO_DSD_XL_t; 1481 | 1482 | /******************************************************************************* 1483 | * Register : D6D_SRC 1484 | * Address : 0x1D 1485 | * Bit Group Name: DSD_XH 1486 | * Permission : RO 1487 | *******************************************************************************/ 1488 | typedef enum { 1489 | DSD_XH_NOT_DETECTED = 0x00, 1490 | DSD_XH_DETECTED = 0x02, 1491 | } LSM6DSO_DSD_XH_t; 1492 | 1493 | /******************************************************************************* 1494 | * Register : D6D_SRC 1495 | * Address : 0x1D 1496 | * Bit Group Name: DSD_YL 1497 | * Permission : RO 1498 | *******************************************************************************/ 1499 | typedef enum { 1500 | DSD_YL_NOT_DETECTED = 0x00, 1501 | DSD_YL_DETECTED = 0x04, 1502 | } LSM6DSO_DSD_YL_t; 1503 | 1504 | /******************************************************************************* 1505 | * Register : D6D_SRC 1506 | * Address : 0x1D 1507 | * Bit Group Name: DSD_YH 1508 | * Permission : RO 1509 | *******************************************************************************/ 1510 | typedef enum { 1511 | DSD_YH_NOT_DETECTED = 0x00, 1512 | DSD_YH_DETECTED = 0x08, 1513 | } LSM6DSO_DSD_YH_t; 1514 | 1515 | /******************************************************************************* 1516 | * Register : D6D_SRC 1517 | * Address : 0x1D 1518 | * Bit Group Name: DSD_ZL 1519 | * Permission : RO 1520 | *******************************************************************************/ 1521 | typedef enum { 1522 | DSD_ZL_NOT_DETECTED = 0x00, 1523 | DSD_ZL_DETECTED = 0x10, 1524 | } LSM6DSO_DSD_ZL_t; 1525 | 1526 | /******************************************************************************* 1527 | * Register : D6D_SRC 1528 | * Address : 0x1D 1529 | * Bit Group Name: DSD_ZH 1530 | * Permission : RO 1531 | *******************************************************************************/ 1532 | typedef enum { 1533 | DSD_ZH_NOT_DETECTED = 0x00, 1534 | DSD_ZH_DETECTED = 0x20, 1535 | } LSM6DSO_DSD_ZH_t; 1536 | 1537 | /******************************************************************************* 1538 | * Register : D6D_SRC 1539 | * Address : 0x1D 1540 | * Bit Group Name: D6D_EV_STATUS 1541 | * Permission : RO 1542 | *******************************************************************************/ 1543 | typedef enum { 1544 | D6D_EV_STATUS_NOT_DETECTED = 0x00, 1545 | D6D_EV_STATUS_DETECTED = 0x40, 1546 | } LSM6DSO_D6D_EV_STATUS_t; 1547 | 1548 | /******************************************************************************* 1549 | * Register : STATUS_REG 1550 | * Address : 0x1E 1551 | * Bit Group Name: XLDA 1552 | * Permission : RO 1553 | *******************************************************************************/ 1554 | typedef enum { 1555 | XLDA_NO_DATA_AVAIL = 0x00, 1556 | XLDA_DATA_AVAIL = 0x01, 1557 | } LSM6DSO_XLDA_t; 1558 | 1559 | /******************************************************************************* 1560 | * Register : STATUS_REG 1561 | * Address : 0x1E 1562 | * Bit Group Name: GDA 1563 | * Permission : RO 1564 | *******************************************************************************/ 1565 | typedef enum { 1566 | GDA_NO_DATA_AVAIL = 0x00, 1567 | GDA_DATA_AVAIL = 0x02, 1568 | } LSM6DSO_GDA_t; 1569 | 1570 | /******************************************************************************* 1571 | * Register : STATUS_REG 1572 | * Address : 0x1E 1573 | * Bit Group Name: EV_BOOT 1574 | * Permission : RO 1575 | *******************************************************************************/ 1576 | typedef enum { 1577 | EV_BOOT_NO_BOOT_RUNNING = 0x00, 1578 | EV_BOOT_BOOT_IS_RUNNING = 0x08, 1579 | } LSM6DSO_EV_BOOT_t; 1580 | 1581 | /******************************************************************************* 1582 | * Register : FIFO_STATUS1 1583 | * Address : 0x3A 1584 | * Bit Group Name: DIFF_FIFO 1585 | * Permission : RO 1586 | *******************************************************************************/ 1587 | #define DIFF_FIFO_STATUS1_MASK 0xFF 1588 | #define DIFF_FIFO_STATUS1_POSITION 0 1589 | #define DIFF_FIFO_STATUS2_MASK 0xF 1590 | #define DIFF_FIFO_STATUS2_POSITION 0 1591 | 1592 | /******************************************************************************* 1593 | * Register : FIFO_STATUS2 1594 | * Address : 0x3B 1595 | * Bit Group Name: FIFO_EMPTY 1596 | * Permission : RO 1597 | *******************************************************************************/ 1598 | typedef enum { 1599 | FIFO_EMPTY_FIFO_NOT_EMPTY = 0x00, 1600 | FIFO_EMPTY_FIFO_EMPTY = 0x10, 1601 | } LSM6DSO_FIFO_EMPTY_t; 1602 | 1603 | /******************************************************************************* 1604 | * Register : FIFO_STATUS2 1605 | * Address : 0x3B 1606 | * Bit Group Name: FIFO_FULL 1607 | * Permission : RO 1608 | *******************************************************************************/ 1609 | typedef enum { 1610 | FIFO_FULL_FIFO_NOT_FULL = 0x00, 1611 | FIFO_FULL_FIFO_FULL = 0x20, 1612 | } LSM6DSO_FIFO_FULL_t; 1613 | 1614 | /******************************************************************************* 1615 | * Register : FIFO_STATUS2 1616 | * Address : 0x3B 1617 | * Bit Group Name: OVERRUN 1618 | * Permission : RO 1619 | *******************************************************************************/ 1620 | typedef enum { 1621 | OVERRUN_NO_OVERRUN = 0x00, 1622 | OVERRUN_OVERRUN = 0x40, 1623 | } LSM6DSO_OVERRUN_t; 1624 | 1625 | /******************************************************************************* 1626 | * Register : FIFO_STATUS2 1627 | * Address : 0x3B 1628 | * Bit Group Name: WTM 1629 | * Permission : RO 1630 | *******************************************************************************/ 1631 | typedef enum { 1632 | WTM_BELOW_WTM = 0x00, 1633 | WTM_ABOVE_OR_EQUAL_WTM = 0x80, 1634 | } LSM6DSO_WTM_t; 1635 | 1636 | 1637 | /******************************************************************************* 1638 | * Register : FIFO_DATA_OUT_TAG 1639 | * Address : 0x78 1640 | * Bit Group Name: TAG_SENSOR 1641 | * Permission : R 1642 | *******************************************************************************/ 1643 | typedef enum { 1644 | TAG_GYRO_NC = 0x01, 1645 | TAG_ACCEL_NC = 0x02, 1646 | TAG_TEMPERATURE = 0x03, 1647 | TAG_TIME_STAMP = 0x04, 1648 | TAG_CFG_CHANGE = 0x05, 1649 | TAG_ACCEL_NC_T_2 = 0x06, 1650 | TAG_ACCEL_NC_T_1 = 0x07, 1651 | TAG_ACCEL_2xC = 0x08, 1652 | TAG_ACCEL_3xC = 0x09, 1653 | TAG_GYRO_NC_T_2 = 0x0A, 1654 | TAG_GYRO_NC_T_1 = 0x0B, 1655 | TAG_GYRO_2xC = 0x0C, 1656 | TAG_GYRO_3xC = 0x0D, 1657 | TAG_SENSOR_HUB_0 = 0x0E, 1658 | TAG_SENSOR_HUB_1 = 0x0F, 1659 | TAG_SENSOR_HUB_2 = 0x10, 1660 | TAG_SENSOR_HUB_3 = 0x11, 1661 | STEP_COUNTER = 0x12, 1662 | SENSOR_HUB_NACK = 0x19, 1663 | } LSM6DSO_FIFO_TAG_t; 1664 | 1665 | /******************************************************************************* 1666 | * Register : FUNC_SRC 1667 | * Address : 0x53 1668 | * Bit Group Name: SENS_HUB_END 1669 | * Permission : RO 1670 | *******************************************************************************/ 1671 | typedef enum { 1672 | SENS_HUB_END_STILL_ONGOING = 0x00, 1673 | SENS_HUB_END_OP_COMPLETED = 0x01, 1674 | } LSM6DSO_SENS_HUB_END_t; 1675 | 1676 | /******************************************************************************* 1677 | * Register : FUNC_SRC 1678 | * Address : 0x53 1679 | * Bit Group Name: SOFT_IRON_END 1680 | * Permission : RO 1681 | *******************************************************************************/ 1682 | typedef enum { 1683 | SOFT_IRON_END_NOT_COMPLETED = 0x00, 1684 | SOFT_IRON_END_COMPLETED = 0x02, 1685 | } LSM6DSO_SOFT_IRON_END_t; 1686 | 1687 | /******************************************************************************* 1688 | * Register : FUNC_SRC 1689 | * Address : 0x53 1690 | * Bit Group Name: PEDO_EV_STATUS 1691 | * Permission : RO 1692 | *******************************************************************************/ 1693 | typedef enum { 1694 | PEDO_EV_STATUS_NOT_DETECTED = 0x00, 1695 | PEDO_EV_STATUS_DETECTED = 0x10, 1696 | } LSM6DSO_PEDO_EV_STATUS_t; 1697 | 1698 | /******************************************************************************* 1699 | * Register : FUNC_SRC 1700 | * Address : 0x53 1701 | * Bit Group Name: TILT_EV_STATUS 1702 | * Permission : RO 1703 | *******************************************************************************/ 1704 | typedef enum { 1705 | TILT_EV_STATUS_NOT_DETECTED = 0x00, 1706 | TILT_EV_STATUS_DETECTED = 0x20, 1707 | } LSM6DSO_TILT_EV_STATUS_t; 1708 | 1709 | /******************************************************************************* 1710 | * Register : FUNC_SRC 1711 | * Address : 0x53 1712 | * Bit Group Name: SIGN_MOT_EV_STATUS 1713 | * Permission : RO 1714 | *******************************************************************************/ 1715 | typedef enum { 1716 | SIGN_MOT_EV_STATUS_NOT_DETECTED = 0x00, 1717 | SIGN_MOT_EV_STATUS_DETECTED = 0x40, 1718 | } LSM6DSO_SIGN_MOT_EV_STATUS_t; 1719 | 1720 | /******************************************************************************* 1721 | * Register : TAP_CFG0 1722 | * Address : 0x56 1723 | * Bit Group Name: LIR 1724 | * Permission : RW 1725 | *******************************************************************************/ 1726 | typedef enum { 1727 | LIR_DISABLED = 0x00, 1728 | LIR_ENABLED = 0x01, 1729 | LIR_MASK = 0xFE 1730 | } LSM6DSO_LIR_t; 1731 | 1732 | #define TAP_INTERRUPT_MASK 0xF1 1733 | /******************************************************************************* 1734 | * Register : TAP_CFG0 1735 | * Address : 0x56 1736 | * Bit Group Name: TAP_Z_EN 1737 | * Permission : RW 1738 | *******************************************************************************/ 1739 | typedef enum { 1740 | TAP_Z_EN_DISABLED = 0x00, 1741 | TAP_Z_EN_ENABLED = 0x02, 1742 | } LSM6DSO_TAP_Z_EN_t; 1743 | 1744 | /******************************************************************************* 1745 | * Register : TAP_CFG0 1746 | * Address : 0x56 1747 | * Bit Group Name: TAP_Y_EN 1748 | * Permission : RW 1749 | *******************************************************************************/ 1750 | typedef enum { 1751 | TAP_Y_EN_DISABLED = 0x00, 1752 | TAP_Y_EN_ENABLED = 0x04, 1753 | } LSM6DSO_TAP_Y_EN_t; 1754 | 1755 | /******************************************************************************* 1756 | * Register : TAP_CFG0 1757 | * Address : 0x56 1758 | * Bit Group Name: TAP_X_EN 1759 | * Permission : RW 1760 | *******************************************************************************/ 1761 | typedef enum { 1762 | TAP_X_EN_DISABLED = 0x00, 1763 | TAP_X_EN_ENABLED = 0x08, 1764 | } LSM6DSO_TAP_X_EN_t; 1765 | 1766 | /******************************************************************************* 1767 | * Register : TAP_CFG0 1768 | * Address : 0x56 1769 | * Bit Group Name: TAP_X_EN 1770 | * Permission : RW 1771 | *******************************************************************************/ 1772 | typedef enum { 1773 | INT_CLR_ON_READ_AT_ODR = 0x00, 1774 | INT_CLR_ON_READ_IMMEDIATE = 0x80 1775 | } LSM6DSO_INT_CLEAR_ON_READ_t; 1776 | 1777 | /******************************************************************************* 1778 | * Register : TAP_CFG1 1779 | * Address : 0x58 1780 | * Bit Group Name: TAP_PRIORITY 1781 | * Permission : RW 1782 | *******************************************************************************/ 1783 | typedef enum { 1784 | TAP_PRIORITY_XYZ = 0x00, 1785 | TAP_PRIORITY_YXZ = 0x01, 1786 | TAP_PRIORITY_XZY = 0x02, 1787 | TAP_PRIORITY_ZYX = 0x03, 1788 | //TAP_PRIORITY_XYZ = 0x04, repeated 1789 | TAP_PRIORITY_YZX = 0x05, 1790 | TAP_PRIORITY_ZXY = 0x06, 1791 | //TAP_PRIORITY_ZYX = 0x07, repeated 1792 | TAP_PRIORITY_MASK = 0x1F 1793 | } LSM6DSO_TAP_PRIORITY_t; 1794 | 1795 | 1796 | /******************************************************************************* 1797 | * Register : TAP_CFG2 1798 | * Address : 0x58 1799 | * Bit Group Name: INTERRUPTS_ENABLE 1800 | * Permission : RW 1801 | *******************************************************************************/ 1802 | typedef enum { 1803 | INTERRUPTS_DISABLED = 0x00, 1804 | INTERRUPTS_ENABLED = 0x80, 1805 | INTERRUPTS_MASK = 0x7F, 1806 | } LSM6DSO_INTERRUPTS_t; 1807 | 1808 | /******************************************************************************* 1809 | * Register : EMB_FUNC_EN_A 1810 | * Address : 0x04 1811 | * Bit Group Name: TILT_EN 1812 | * Permission : RW 1813 | *******************************************************************************/ 1814 | typedef enum { 1815 | TILT_DISABLED = 0x00, 1816 | TILT_ENABLED = 0x10, 1817 | } LSM6DSO_TILT_EN_t; 1818 | 1819 | /******************************************************************************* 1820 | * Register : EMB_FUNC_EN_A 1821 | * Address : 0x04 1822 | * Bit Group Name: PEDO_EN 1823 | * Permission : RW 1824 | *******************************************************************************/ 1825 | typedef enum { 1826 | PEDO_DISABLED = 0x00, 1827 | PEDO_ENABLED = 0x08, 1828 | PEDO_MASK = 0xF7, 1829 | } LSM6DSO_PEDO_EN_t; 1830 | 1831 | /******************************************************************************* 1832 | * Register : EMB_FUNC_EN_A 1833 | * Address : 0x04 1834 | * Bit Group Name: SIGN_MOTION_EN 1835 | * Permission : RW 1836 | *******************************************************************************/ 1837 | typedef enum { 1838 | SIGN_MOTION_DISABLED = 0x00, 1839 | SIGN_MOTION_ENABLED = 0x20, 1840 | } LSM6DSO_SIGN_MOTION_EN_t; 1841 | 1842 | 1843 | /******************************************************************************* 1844 | * Register : EMB_FUNC_SRC 1845 | * Address : 0x64 1846 | * Bit Group Name: PEDO_RST_STEP 1847 | * Permission : RW 1848 | *******************************************************************************/ 1849 | typedef enum { 1850 | PEDO_RST_STEP_ENABLED = 0x80, 1851 | PEDO_RST_STEP_DISABLED = 0x00, 1852 | PEDO_RST_STEP_MASK = 0x7F, 1853 | } PEDO_RST_STEP_t; 1854 | 1855 | /******************************************************************************* 1856 | * Register : EMB_FUNC_SRC 1857 | * Address : 0x64 1858 | * Bit Group Name: STEP_DETECTED 1859 | * Permission : RW 1860 | *******************************************************************************/ 1861 | typedef enum { 1862 | STEP_NOT_DETECED = 0x00, 1863 | STEP_DETECED = 0x40, 1864 | STEP_DETECED_MASK = 0xBF 1865 | } PEDO_STEP_DETECT_t; 1866 | 1867 | /******************************************************************************* 1868 | * Register : TAP_THS_6D 1869 | * Address : 0x59 1870 | * Bit Group Name: TAP_THS 1871 | * Permission : RW 1872 | *******************************************************************************/ 1873 | #define TAP_THS_MASK 0x1F 1874 | #define TAP_THS_POSITION 0 1875 | 1876 | /******************************************************************************* 1877 | * Register : TAP_THS_6D 1878 | * Address : 0x59 1879 | * Bit Group Name: SIXD_THS 1880 | * Permission : RW 1881 | *******************************************************************************/ 1882 | typedef enum { 1883 | SIXD_THS_80_degree = 0x00, 1884 | SIXD_THS_70_degree = 0x20, 1885 | SIXD_THS_60_degree = 0x40, 1886 | SIXD_THS_50_degree = 0x60, 1887 | } LSM6DSO_SIXD_THS_t; 1888 | 1889 | /******************************************************************************* 1890 | * Register : INT_DUR2 1891 | * Address : 0x5A 1892 | * Bit Group Name: SHOCK 1893 | * Permission : RW 1894 | *******************************************************************************/ 1895 | #define SHOCK_MASK 0x03 1896 | #define SHOCK_POSITION 0 1897 | 1898 | /******************************************************************************* 1899 | * Register : INT_DUR2 1900 | * Address : 0x5A 1901 | * Bit Group Name: QUIET 1902 | * Permission : RW 1903 | *******************************************************************************/ 1904 | #define QUIET_MASK 0x0C 1905 | #define QUIET_POSITION 2 1906 | 1907 | /******************************************************************************* 1908 | * Register : INT_DUR2 1909 | * Address : 0x5A 1910 | * Bit Group Name: DUR 1911 | * Permission : RW 1912 | *******************************************************************************/ 1913 | #define DUR_MASK 0xF0 1914 | #define DUR_POSITION 4 1915 | 1916 | /******************************************************************************* 1917 | * Register : WAKE_UP_THS 1918 | * Address : 0x5B 1919 | * Bit Group Name: WK_THS 1920 | * Permission : RW 1921 | *******************************************************************************/ 1922 | #define WK_THS_MASK 0x3F 1923 | #define WK_THS_POSITION 0 1924 | 1925 | /******************************************************************************* 1926 | * Register : WAKE_UP_THS 1927 | * Address : 0x5B 1928 | * Bit Group Name: INACTIVITY_ON 1929 | * Permission : RW 1930 | *******************************************************************************/ 1931 | typedef enum { 1932 | INACTIVITY_ON_DISABLED = 0x00, 1933 | INACTIVITY_ON_ENABLED = 0x40, 1934 | } LSM6DSO_INACTIVITY_ON_t; 1935 | 1936 | /******************************************************************************* 1937 | * Register : WAKE_UP_THS 1938 | * Address : 0x5B 1939 | * Bit Group Name: SINGLE_DOUBLE_TAP 1940 | * Permission : RW 1941 | *******************************************************************************/ 1942 | typedef enum { 1943 | SINGLE_DOUBLE_TAP_DOUBLE_TAP = 0x00, 1944 | SINGLE_DOUBLE_TAP_SINGLE_TAP = 0x80, 1945 | } LSM6DSO_SINGLE_DOUBLE_TAP_t; 1946 | 1947 | /******************************************************************************* 1948 | * Register : WAKE_UP_DUR 1949 | * Address : 0x5C 1950 | * Bit Group Name: SLEEP_DUR 1951 | * Permission : RW 1952 | *******************************************************************************/ 1953 | #define SLEEP_DUR_MASK 0x0F 1954 | #define SLEEP_DUR_POSITION 0 1955 | 1956 | /******************************************************************************* 1957 | * Register : WAKE_UP_DUR 1958 | * Address : 0x5C 1959 | * Bit Group Name: TIMER_HR 1960 | * Permission : RW 1961 | *******************************************************************************/ 1962 | typedef enum { 1963 | TIMER_HR_6_4ms = 0x00, 1964 | TIMER_HR_25us = 0x10, 1965 | } LSM6DSO_TIMER_HR_t; 1966 | 1967 | /******************************************************************************* 1968 | * Register : WAKE_UP_DUR 1969 | * Address : 0x5C 1970 | * Bit Group Name: WAKE_DUR 1971 | * Permission : RW 1972 | *******************************************************************************/ 1973 | #define WAKE_DUR_MASK 0x60 1974 | #define WAKE_DUR_POSITION 5 1975 | 1976 | /******************************************************************************* 1977 | * Register : FREE_FALL 1978 | * Address : 0x5D 1979 | * Bit Group Name: FF_DUR 1980 | * Permission : RW 1981 | *******************************************************************************/ 1982 | #define FF_FREE_FALL_DUR_MASK 0xF8 1983 | #define FF_FREE_FALL_DUR_POSITION 3 1984 | #define FF_WAKE_UP_DUR_MASK 0x80 1985 | #define FF_WAKE_UP_DUR_POSITION 7 1986 | 1987 | 1988 | /******************************************************************************* 1989 | * Register : FREE_FALL 1990 | * Address : 0x5D 1991 | * Bit Group Name: FF_THS 1992 | * Permission : RW 1993 | *******************************************************************************/ 1994 | typedef enum { 1995 | FF_THS_5 = 0x00, 1996 | FF_THS_7 = 0x01, 1997 | FF_THS_8 = 0x02, 1998 | FF_THS_10 = 0x03, 1999 | FF_THS_11 = 0x04, 2000 | FF_THS_13 = 0x05, 2001 | FF_THS_15 = 0x06, 2002 | FF_THS_16 = 0x07, 2003 | } LSM6DSO_FF_THS_t; 2004 | 2005 | /******************************************************************************* 2006 | * Register : MD1_CFG 2007 | * Address : 0x5E 2008 | * Bit Group Name: INT1_SHUB 2009 | * Permission : RW 2010 | *******************************************************************************/ 2011 | typedef enum { 2012 | INT1_SHUB_DISABLED = 0x00, 2013 | INT1_SHUB_ENABLED = 0x01, 2014 | } LSM6DSO_INT1_SHUB_t; 2015 | 2016 | /******************************************************************************* 2017 | * Register : MD1_CFG 2018 | * Address : 0x5E 2019 | * Bit Group Name: INT1_EMB_FUNC 2020 | * Permission : RW 2021 | *******************************************************************************/ 2022 | typedef enum { 2023 | INT1_EMB_FUNC_DISABLED = 0x00, 2024 | INT1_EMB_FUNC_ENABLED = 0x02, 2025 | } LSM6DSO_INT1_TILT_t; 2026 | 2027 | /******************************************************************************* 2028 | * Register : MD1_CFG 2029 | * Address : 0x5E 2030 | * Bit Group Name: INT1_6D 2031 | * Permission : RW 2032 | *******************************************************************************/ 2033 | typedef enum { 2034 | INT1_6D_DISABLED = 0x00, 2035 | INT1_6D_ENABLED = 0x04, 2036 | } LSM6DSO_INT1_6D_t; 2037 | 2038 | /******************************************************************************* 2039 | * Register : MD1_CFG 2040 | * Address : 0x5E 2041 | * Bit Group Name: INT1_DOUBLE_TAP 2042 | * Permission : RW 2043 | *******************************************************************************/ 2044 | typedef enum { 2045 | INT1_DOUBLE_TAP_DISABLED = 0x00, 2046 | INT1_DOUBLE_TAP_ENABLED = 0x08, 2047 | } LSM6DSO_INT1_TAP_t; 2048 | 2049 | /******************************************************************************* 2050 | * Register : MD1_CFG 2051 | * Address : 0x5E 2052 | * Bit Group Name: INT1_FF 2053 | * Permission : RW 2054 | *******************************************************************************/ 2055 | typedef enum { 2056 | INT1_FF_DISABLED = 0x00, 2057 | INT1_FF_ENABLED = 0x10, 2058 | } LSM6DSO_INT1_FF_t; 2059 | 2060 | /******************************************************************************* 2061 | * Register : MD1_CFG 2062 | * Address : 0x5E 2063 | * Bit Group Name: INT1_WU 2064 | * Permission : RW 2065 | *******************************************************************************/ 2066 | typedef enum { 2067 | INT1_WU_DISABLED = 0x00, 2068 | INT1_WU_ENABLED = 0x20, 2069 | } LSM6DSO_INT1_WU_t; 2070 | 2071 | /******************************************************************************* 2072 | * Register : MD1_CFG 2073 | * Address : 0x5E 2074 | * Bit Group Name: INT1_SINGLE_TAP 2075 | * Permission : RW 2076 | *******************************************************************************/ 2077 | typedef enum { 2078 | INT1_SINGLE_TAP_DISABLED = 0x00, 2079 | INT1_SINGLE_TAP_ENABLED = 0x40, 2080 | INT1_SINGLE_TAP_MASK = 0xBF 2081 | } LSM6DSO_INT1_SINGLE_TAP_t; 2082 | 2083 | /******************************************************************************* 2084 | * Register : MD1_CFG 2085 | * Address : 0x5E 2086 | * Bit Group Name: INT1_SLEEP 2087 | * Permission : RW 2088 | *******************************************************************************/ 2089 | typedef enum { 2090 | INT1_SLEEP_DISABLED = 0x00, 2091 | INT1_SLEEP_ENABLED = 0x80, 2092 | } LSM6DSO_INT1_SLEEP_t; 2093 | 2094 | /******************************************************************************* 2095 | * Register : MD2_CFG 2096 | * Address : 0x5F 2097 | * Bit Group Name: INT2_TIMESTAMP 2098 | * Permission : RW 2099 | *******************************************************************************/ 2100 | typedef enum { 2101 | INT2_TIMESTAMP_DISABLED = 0x00, 2102 | INT2_TIMESTAMP_ENABLED = 0x01, 2103 | } LSM6DSO_INT2_TIMESTAMP_t; 2104 | 2105 | /******************************************************************************* 2106 | * Register : MD2_CFG 2107 | * Address : 0x5F 2108 | * Bit Group Name: INT2_EMB_FUNC 2109 | * Permission : RW 2110 | *******************************************************************************/ 2111 | typedef enum { 2112 | INT2_EMB_FUNC_DISABLED = 0x00, 2113 | INT2_EMB_FUNC_ENABLED = 0x02, 2114 | } LSM6DSO_INT2_EMB_FUNC_t; 2115 | 2116 | /******************************************************************************* 2117 | * Register : MD2_CFG 2118 | * Address : 0x5F 2119 | * Bit Group Name: INT2_6D 2120 | * Permission : RW 2121 | *******************************************************************************/ 2122 | typedef enum { 2123 | INT2_6D_DISABLED = 0x00, 2124 | INT2_6D_ENABLED = 0x04, 2125 | } LSM6DSO_INT2_6D_t; 2126 | 2127 | /******************************************************************************* 2128 | * Register : MD2_CFG 2129 | * Address : 0x5F 2130 | * Bit Group Name: INT2_DOUBLE_TAP 2131 | * Permission : RW 2132 | *******************************************************************************/ 2133 | typedef enum { 2134 | INT2_DOUBLE_TAP_DISABLED = 0x00, 2135 | INT2_DOUBLE_TAP_ENABLED = 0x08, 2136 | } LSM6DSO_INT2_DOUBLE_TAP_t; 2137 | 2138 | /******************************************************************************* 2139 | * Register : MD2_CFG 2140 | * Address : 0x5F 2141 | * Bit Group Name: INT2_FF 2142 | * Permission : RW 2143 | *******************************************************************************/ 2144 | typedef enum { 2145 | INT2_FF_DISABLED = 0x00, 2146 | INT2_FF_ENABLED = 0x10, 2147 | } LSM6DSO_INT2_FF_t; 2148 | 2149 | /******************************************************************************* 2150 | * Register : MD2_CFG 2151 | * Address : 0x5F 2152 | * Bit Group Name: INT2_WU 2153 | * Permission : RW 2154 | *******************************************************************************/ 2155 | typedef enum { 2156 | INT2_WU_DISABLED = 0x00, 2157 | INT2_WU_ENABLED = 0x20, 2158 | } LSM6DSO_INT2_WU_t; 2159 | 2160 | /******************************************************************************* 2161 | * Register : MD2_CFG 2162 | * Address : 0x5F 2163 | * Bit Group Name: INT2_SINGLE_TAP 2164 | * Permission : RW 2165 | *******************************************************************************/ 2166 | typedef enum { 2167 | INT2_SINGLE_TAP_DISABLED = 0x00, 2168 | INT2_SINGLE_TAP_ENABLED = 0x40, 2169 | } LSM6DSO_INT2_SINGLE_TAP_t; 2170 | 2171 | /******************************************************************************* 2172 | * Register : MD2_CFG 2173 | * Address : 0x5F 2174 | * Bit Group Name: INT2_SLEEP 2175 | * Permission : RW 2176 | *******************************************************************************/ 2177 | typedef enum { 2178 | INT2_SLEEP_DISABLED = 0x00, 2179 | INT2_SLEEP_ENABLED = 0x80, 2180 | } LSM6DSO_INT2_SLEEP_t; 2181 | 2182 | #endif // End of __LSM6DSOIMU_H__ definition check 2183 | --------------------------------------------------------------------------------