├── .gitignore ├── Descriptions ├── Control Unit signals │ └── ControlUnit_OPs.png └── README.md ├── Flow Diagrams ├── Architecture.png ├── FPGA Design Flow.png └── c45e5e76-cd15-468a-bf65-dc7a4b69c358.jfif ├── LICENSE ├── README.md ├── RV32IM GNU Toolchain ├── README.md └── Sample │ ├── RV32I │ ├── Arithmetic │ │ ├── Compressed_main │ │ │ ├── outputC.out │ │ │ └── output_assemC.txt │ │ ├── Full │ │ │ ├── output.out │ │ │ └── output_assem.txt │ │ └── prog.c │ ├── Branch │ │ ├── branch_program.c │ │ ├── output.out │ │ └── output_assem.txt │ └── Jump │ │ ├── Jump_prog.c │ │ ├── output.out │ │ └── output_assem.txt │ └── RV32IM │ ├── AssemblyCode.txt │ ├── output-assem │ └── prog.c └── RV32IM ├── RV32IM.ip_user_files ├── README.txt └── mem_init_files │ └── Code.txt ├── RV32IM.runs ├── impl_2 │ ├── Execution_main_source.bit │ ├── Execution_main_source.tcl │ ├── Execution_main_source.vdi │ ├── Execution_main_source_6528.backup.vdi │ ├── Execution_main_source_bus_skew_routed.rpt │ ├── Execution_main_source_clock_utilization_routed.rpt │ ├── Execution_main_source_control_sets_placed.rpt │ ├── Execution_main_source_drc_opted.rpt │ ├── Execution_main_source_drc_routed.rpt │ ├── Execution_main_source_io_placed.rpt │ ├── Execution_main_source_methodology_drc_routed.rpt │ ├── Execution_main_source_power_routed.rpt │ ├── Execution_main_source_route_status.rpt │ ├── Execution_main_source_timing_summary_routed.rpt │ ├── Execution_main_source_utilization_placed.rpt │ └── htr.txt ├── synth_1 │ ├── Execution_main_source.tcl │ ├── Execution_main_source_utilization_synth.rpt │ └── htr.txt └── synth_2 │ ├── .Xil │ └── Execution_main_source_propImpl.xdc │ ├── Code.txt │ ├── Execution_main_source.tcl │ ├── Execution_main_source_utilization_synth.rpt │ └── htr.txt ├── RV32IM.sim └── sim_1 │ └── behav │ ├── RV32Core_TB_behav.wcfg │ └── xsim │ ├── Code.txt │ ├── Execution_Main.tcl │ ├── Execution_main_source.tcl │ ├── ROM_Module_TestBench.tcl │ ├── RV32Core.tcl │ ├── RV32Core_TB.tcl │ ├── Stage_MEM_TB.tcl │ ├── Stage_MEM_TestBench.tcl │ ├── controUnit_TestBench.tcl │ ├── glbl.v │ ├── webtalk.jou │ └── xsim.dir │ ├── Execution_Main_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ ├── obj │ │ └── xsim_1.c │ └── webtalk │ │ └── xsim_webtalk.tcl │ ├── Execution_main_source_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ └── obj │ │ └── xsim_1.c │ ├── ROM_Module_TestBench_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ ├── obj │ │ └── xsim_1.c │ └── webtalk │ │ └── xsim_webtalk.tcl │ ├── RV32Core_TB_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ ├── obj │ │ └── xsim_1.c │ └── webtalk │ │ └── xsim_webtalk.tcl │ ├── RV32Core_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ └── obj │ │ └── xsim_1.c │ ├── Stage_MEM_TB_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ ├── obj │ │ └── xsim_1.c │ └── webtalk │ │ └── xsim_webtalk.tcl │ ├── Stage_MEM_TestBench_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ ├── obj │ │ └── xsim_1.c │ └── webtalk │ │ └── xsim_webtalk.tcl │ └── controUnit_TestBench_behav │ ├── Compile_Options.txt │ ├── TempBreakPointFile.txt │ └── obj │ └── xsim_1.c └── RV32IM.srcs ├── constrs_1 └── new │ ├── IO_Constraints.xdc │ └── timing.xdc ├── sim_1 ├── imports │ └── new │ │ ├── ALU_TestBench.v │ │ ├── ALU_control_unit_testbench.v │ │ ├── RegisterModule_Testbench.v │ │ └── controUnit_TestBench.v └── new │ ├── Execution_Main.v │ ├── ROM_Module_TestBench.v │ ├── RV32Core_TB.v │ ├── Stage_MEM_TB.v │ ├── Stage_MEM_TestBench.v │ └── Stage_MEM_pipelined_testbench.v └── sources_1 └── imports └── new ├── ALU_control_unit.v ├── ALU_module.v ├── BranchControl.v ├── ControlUnit.v ├── MMU.v ├── RAM_Module.v ├── ROM_Module.v ├── RV32Core.v ├── RamMemory.v ├── Registers_Module.v ├── Stage_EX.v ├── Stage_ID.v ├── Stage_IF.v ├── Stage_MEM.v ├── Stage_WB.v ├── defines.v ├── input_shifter.v ├── main.v ├── output_shifter.v ├── reg_EX_MEM.v ├── reg_ID_EX.v ├── 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