├── LICENSE
├── README.md
├── rtl model
├── HuffmanCode.v
├── freqcount.v
├── huffman_top.v
├── para2ser.v
└── sortnet
│ ├── BitonicSortX4.v
│ ├── BitonicSortX8.v
│ ├── SortElement.v
│ ├── SortX16.v
│ ├── SortX4.v
│ └── SortX8.v
├── simulation
├── huffman_test.v
└── sortx16_sim.v
└── software model
└── HuffNode.cpp
/LICENSE:
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--------------------------------------------------------------------------------
/README.md:
--------------------------------------------------------------------------------
1 | # HuffmanCode
--------------------------------------------------------------------------------
/rtl model/HuffmanCode.v:
--------------------------------------------------------------------------------
1 | /****************************************************************
2 | /*
3 | /* Description:
4 | /* main FSM control of huffman coding process
5 | /* Author:
6 | /* Guozhu Xin
7 | /* Date:
8 | /* 2017/7/27
9 | /* Email:
10 | /* spikexin@outlook.com
11 | ******************************************************************/
12 |
13 | module HuffmanCode (
14 | input clk,
15 | input rst_n,
16 | input [18:0] data_in0,
17 | input [18:0] data_in1,
18 | input [18:0] data_in2,
19 | input [18:0] data_in3,
20 | input [18:0] data_in4,
21 | input [18:0] data_in5,
22 | input [18:0] data_in6,
23 | input [18:0] data_in7,
24 | input [18:0] data_in8,
25 | input [18:0] data_in9,
26 | input req_coding,
27 | output reg ack_coding,
28 | output reg [8:0] data_out,
29 | output reg [3:0] data_len,
30 | output wire trans_start
31 | );
32 |
33 | localparam IDLE = 2'd0;
34 | localparam CODING = 2'd1;
35 | localparam TRAVERSE = 2'd2;
36 | localparam OUTPUT = 2'd3;
37 | reg [1:0] state; // coding=0, traverse=1
38 | reg [1:0] next_state;
39 | reg [3:0] phase;
40 | reg [3:0] next_phase;
41 | reg [3:0] loop;
42 | reg [3:0] next_loop;
43 |
44 | reg [18:0] mem [0:18];
45 | reg [18:0] a0;
46 | reg [18:0] a1;
47 | reg [18:0] a2;
48 | reg [18:0] a3;
49 | reg [18:0] a4;
50 | reg [18:0] a5;
51 | reg [18:0] a6;
52 | reg [18:0] a7;
53 | reg [18:0] a8;
54 | reg [18:0] a9;
55 | reg [18:0] a10;
56 | reg [18:0] a11;
57 | reg [18:0] a12;
58 | reg [18:0] a13;
59 | reg [18:0] a14;
60 | reg [18:0] a15;
61 | wire [18:0] sort0;
62 | wire [18:0] sort1;
63 | wire [18:0] sort2;
64 | wire [18:0] sort3;
65 | wire [18:0] sort4;
66 | wire [18:0] sort5;
67 | wire [18:0] sort6;
68 | wire [18:0] sort7;
69 | wire [18:0] sort8;
70 | wire [18:0] sort9;
71 | wire [18:0] sort10;
72 | wire [18:0] sort11;
73 | wire [18:0] sort12;
74 | wire [18:0] sort13;
75 | wire [18:0] sort14;
76 | wire [18:0] sort15;
77 |
78 | always @(posedge clk or negedge rst_n) begin
79 | if (~rst_n)
80 | ack_coding <= 1'b0;
81 | else if (req_coding)
82 | ack_coding <= 1'b1;
83 | else
84 | ack_coding <= 1'b0;
85 | end
86 |
87 | always @(posedge clk or negedge rst_n) begin
88 | if (~rst_n) begin
89 | state <= IDLE;
90 | phase <= 4'b0;
91 | loop <= 4'd0;
92 | end else begin
93 | state <= next_state;
94 | phase <= next_phase;
95 | loop <= next_loop;
96 | end
97 | end
98 |
99 | always @(*) begin
100 | case (state)
101 | IDLE: begin
102 | if (req_coding)
103 | next_state = CODING;
104 | else
105 | next_state = IDLE;
106 | next_phase = 4'b0;
107 | next_loop = 4'd0;
108 | end
109 | CODING: begin
110 | if (phase == 4'd9) begin
111 | next_state = TRAVERSE;
112 | next_phase = 4'd0;
113 | end else begin
114 | next_state = CODING;
115 | next_phase = phase + 1;
116 | end
117 | next_loop = 4'd0;
118 | end
119 | TRAVERSE: begin
120 | if (phase == 4'd8) begin
121 | next_state = OUTPUT;
122 | next_phase = 4'd0;
123 | next_loop = code_length[0];
124 | end else begin
125 | next_state = TRAVERSE;
126 | next_phase = phase + 1;
127 | next_loop = 4'd0;
128 | end
129 | end
130 | OUTPUT: begin
131 | if (loop == 4'd1) begin
132 | if (phase == 4'd9) begin
133 | next_state = IDLE;
134 | next_phase = 4'd0;
135 | next_loop = 4'd0;
136 | end else begin
137 | next_state = OUTPUT;
138 | next_phase = phase + 1;
139 | next_loop = code_length[phase+1];
140 | end
141 | end
142 | else begin
143 | next_state = OUTPUT;
144 | next_phase = phase;
145 | next_loop = loop - 1;
146 | end
147 | end
148 | default: begin
149 | next_state = state;
150 | next_phase = phase;
151 | next_loop = loop;
152 | end
153 | endcase
154 | end
155 |
156 | always @(posedge clk or negedge rst_n) begin
157 | if (~rst_n) begin
158 | a0 <= 19'b0;
159 | a1 <= 19'b0;
160 | a2 <= 19'b0;
161 | a3 <= 19'b0;
162 | a4 <= 19'b0;
163 | a5 <= 19'b0;
164 | a6 <= 19'b0;
165 | a7 <= 19'b0;
166 | a8 <= 19'b0;
167 | a9 <= 19'b0;
168 | a10 <= 19'b0;
169 | a11 <= 19'b0;
170 | a12 <= 19'b0;
171 | a13 <= 19'b0;
172 | a14 <= 19'b0;
173 | a15 <= 19'b0;
174 | end
175 | else if (state==CODING) begin
176 | case(phase)
177 | 4'd0: begin
178 | a0 <= data_in0;
179 | a1 <= data_in1;
180 | a2 <= data_in2;
181 | a3 <= data_in3;
182 | a4 <= data_in4;
183 | a5 <= data_in5;
184 | a6 <= data_in6;
185 | a7 <= data_in7;
186 | a8 <= data_in8;
187 | a9 <= data_in9;
188 | a10 <= 19'd255;
189 | a11 <= 19'd255;
190 | a12 <= 19'd255;
191 | a13 <= 19'd255;
192 | a14 <= 19'd255;
193 | a15 <= 19'd255;
194 | end
195 | 4'd1: begin
196 | a0 <= {6'b0, 5'd10, sort0[7:0]+sort1[7:0]};
197 | a1 <= sort2;
198 | a2 <= sort3;
199 | a3 <= sort4;
200 | a4 <= sort5;
201 | a5 <= sort6;
202 | a6 <= sort7;
203 | a7 <= sort8;
204 | a8 <= sort9;
205 | a9 <= 19'd255;
206 | a10 <= 19'd255;
207 | a11 <= 19'd255;
208 | a12 <= 19'd255;
209 | a13 <= 19'd255;
210 | a14 <= 19'd255;
211 | a15 <= 19'd255;
212 | end
213 | 4'd2: begin
214 | a0 <= {6'b0, 5'd11, sort0[7:0]+sort1[7:0]};
215 | a1 <= sort2;
216 | a2 <= sort3;
217 | a3 <= sort4;
218 | a4 <= sort5;
219 | a5 <= sort6;
220 | a6 <= sort7;
221 | a7 <= sort8;
222 | a8 <= 19'd255;
223 | a9 <= 19'd255;
224 | a10 <= 19'd255;
225 | a11 <= 19'd255;
226 | a12 <= 19'd255;
227 | a13 <= 19'd255;
228 | a14 <= 19'd255;
229 | a15 <= 19'd255;
230 | end
231 | 4'd3: begin
232 | a0 <= {6'b0, 5'd12, sort0[7:0]+sort1[7:0]};
233 | a1 <= sort2;
234 | a2 <= sort3;
235 | a3 <= sort4;
236 | a4 <= sort5;
237 | a5 <= sort6;
238 | a6 <= sort7;
239 | a7 <= 19'd255;
240 | a8 <= 19'd255;
241 | a9 <= 19'd255;
242 | a10 <= 19'd255;
243 | a11 <= 19'd255;
244 | a12 <= 19'd255;
245 | a13 <= 19'd255;
246 | a14 <= 19'd255;
247 | a15 <= 19'd255;
248 | end
249 | 4'd4: begin
250 | a0 <= {6'b0, 5'd13, sort0[7:0]+sort1[7:0]};
251 | a1 <= sort2;
252 | a2 <= sort3;
253 | a3 <= sort4;
254 | a4 <= sort5;
255 | a5 <= sort6;
256 | a6 <= 19'd255;
257 | a7 <= 19'd255;
258 | a8 <= 19'd255;
259 | a9 <= 19'd255;
260 | a10 <= 19'd255;
261 | a11 <= 19'd255;
262 | a12 <= 19'd255;
263 | a13 <= 19'd255;
264 | a14 <= 19'd255;
265 | a15 <= 19'd255;
266 | end
267 | 4'd5: begin
268 | a0 <= {6'b0, 5'd14, sort0[7:0]+sort1[7:0]};
269 | a1 <= sort2;
270 | a2 <= sort3;
271 | a3 <= sort4;
272 | a4 <= sort5;
273 | a5 <= 19'd255;
274 | a6 <= 19'd255;
275 | a7 <= 19'd255;
276 | a8 <= 19'd255;
277 | a9 <= 19'd255;
278 | a10 <= 19'd255;
279 | a11 <= 19'd255;
280 | a12 <= 19'd255;
281 | a13 <= 19'd255;
282 | a14 <= 19'd255;
283 | a15 <= 19'd255;
284 | end
285 | 4'd6: begin
286 | a0 <= {6'b0, 5'd15, sort0[7:0]+sort1[7:0]};
287 | a1 <= sort2;
288 | a2 <= sort3;
289 | a3 <= sort4;
290 | a4 <= 19'd255;
291 | a5 <= 19'd255;
292 | a6 <= 19'd255;
293 | a7 <= 19'd255;
294 | a8 <= 19'd255;
295 | a9 <= 19'd255;
296 | a10 <= 19'd255;
297 | a11 <= 19'd255;
298 | a12 <= 19'd255;
299 | a13 <= 19'd255;
300 | a14 <= 19'd255;
301 | a15 <= 19'd255;
302 | end
303 | 4'd7: begin
304 | a0 <= {6'b0, 5'd16, sort0[7:0]+sort1[7:0]};
305 | a1 <= sort2;
306 | a2 <= sort3;
307 | a3 <= 19'd255;
308 | a4 <= 19'd255;
309 | a5 <= 19'd255;
310 | a6 <= 19'd255;
311 | a7 <= 19'd255;
312 | a8 <= 19'd255;
313 | a9 <= 19'd255;
314 | a10 <= 19'd255;
315 | a11 <= 19'd255;
316 | a12 <= 19'd255;
317 | a13 <= 19'd255;
318 | a14 <= 19'd255;
319 | a15 <= 19'd255;
320 | end
321 | 4'd8: begin
322 | a0 <= {6'b0, 5'd17, sort0[7:0]+sort1[7:0]};
323 | a1 <= sort2;
324 | a2 <= 19'd255;
325 | a3 <= 19'd255;
326 | a4 <= 19'd255;
327 | a5 <= 19'd255;
328 | a6 <= 19'd255;
329 | a7 <= 19'd255;
330 | a8 <= 19'd255;
331 | a9 <= 19'd255;
332 | a10 <= 19'd255;
333 | a11 <= 19'd255;
334 | a12 <= 19'd255;
335 | a13 <= 19'd255;
336 | a14 <= 19'd255;
337 | a15 <= 19'd255;
338 | end
339 | 4'd9: begin
340 | a0 <= 19'b0;
341 | a1 <= 19'b0;
342 | a2 <= 19'b0;
343 | a3 <= 19'b0;
344 | a4 <= 19'b0;
345 | a5 <= 19'b0;
346 | a6 <= 19'b0;
347 | a7 <= 19'b0;
348 | a8 <= 19'b0;
349 | a9 <= 19'b0;
350 | a10 <= 19'b0;
351 | a11 <= 19'b0;
352 | a12 <= 19'b0;
353 | a13 <= 19'b0;
354 | a14 <= 19'b0;
355 | a15 <= 19'b0;
356 | end
357 | default: begin
358 | a0 <= 20'b0;
359 | a1 <= 20'b0;
360 | a2 <= 20'b0;
361 | a3 <= 20'b0;
362 | a4 <= 20'b0;
363 | a5 <= 20'b0;
364 | a6 <= 20'b0;
365 | a7 <= 20'b0;
366 | a8 <= 20'b0;
367 | a9 <= 20'b0;
368 | a10 <= 20'b0;
369 | a11 <= 20'b0;
370 | a12 <= 20'b0;
371 | a13 <= 20'b0;
372 | a14 <= 20'b0;
373 | a15 <= 20'b0;
374 | end
375 | endcase
376 | end
377 | else begin
378 | a0 <= 20'b0;
379 | a1 <= 20'b0;
380 | a2 <= 20'b0;
381 | a3 <= 20'b0;
382 | a4 <= 20'b0;
383 | a5 <= 20'b0;
384 | a6 <= 20'b0;
385 | a7 <= 20'b0;
386 | a8 <= 20'b0;
387 | a9 <= 20'b0;
388 | a10 <= 20'b0;
389 | a11 <= 20'b0;
390 | a12 <= 20'b0;
391 | a13 <= 20'b0;
392 | a14 <= 20'b0;
393 | a15 <= 20'b0;
394 | end
395 | end
396 |
397 | integer i;
398 | always @(posedge clk or negedge rst_n) begin
399 | if (~rst_n) begin
400 | for (i = 0; i < 19; i = i + 1) begin
401 | mem[i] <= 19'b0;
402 | end
403 | end
404 | else if (state == CODING) begin
405 | case (phase)
406 | 4'd0: ;
407 | 4'd1: begin
408 | mem[sort0[12:8]] <= {5'd10, 1'd0, sort0[12:0]};
409 | mem[sort1[12:8]] <= {5'd10, 1'd1, sort1[12:0]};
410 | end
411 | 4'd2: begin
412 | mem[sort0[12:8]] <= {5'd11, 1'd0, sort0[12:0]};
413 | mem[sort1[12:8]] <= {5'd11, 1'd1, sort1[12:0]};
414 | end
415 | 4'd3: begin
416 | mem[sort0[12:8]] <= {5'd12, 1'd0, sort0[12:0]};
417 | mem[sort1[12:8]] <= {5'd12, 1'd1, sort1[12:0]};
418 | end
419 | 4'd4: begin
420 | mem[sort0[12:8]] <= {5'd13, 1'd0, sort0[12:0]};
421 | mem[sort1[12:8]] <= {5'd13, 1'd1, sort1[12:0]};
422 | end
423 | 4'd5: begin
424 | mem[sort0[12:8]] <= {5'd14, 1'd0, sort0[12:0]};
425 | mem[sort1[12:8]] <= {5'd14, 1'd1, sort1[12:0]};
426 | end
427 | 4'd6: begin
428 | mem[sort0[12:8]] <= {5'd15, 1'd0, sort0[12:0]};
429 | mem[sort1[12:8]] <= {5'd15, 1'd1, sort1[12:0]};
430 | end
431 | 4'd7: begin
432 | mem[sort0[12:8]] <= {5'd16, 1'd0, sort0[12:0]};
433 | mem[sort1[12:8]] <= {5'd16, 1'd1, sort1[12:0]};
434 | end
435 | 4'd8: begin
436 | mem[sort0[12:8]] <= {5'd17, 1'd0, sort0[12:0]};
437 | mem[sort1[12:8]] <= {5'd17, 1'd1, sort1[12:0]};
438 | end
439 | 4'd9: begin
440 | mem[sort0[12:8]] <= {5'd18, 1'd0, sort0[12:0]};
441 | mem[sort1[12:8]] <= {5'd18, 1'd1, sort1[12:0]};
442 | mem[18] <= {5'd31, 1'd0, 5'd18, sort0[7:0]+sort1[7:0]}; // parent number 31
443 | end
444 | default: ;
445 | endcase
446 | end
447 | end
448 |
449 | SortX16 # (
450 | .DSIZE (5'd19),
451 | .OFFSET (4'd8)
452 | ) sortx16_inst0 (
453 | .a0 (a0),
454 | .a1 (a1),
455 | .a2 (a2),
456 | .a3 (a3),
457 | .a4 (a4),
458 | .a5 (a5),
459 | .a6 (a6),
460 | .a7 (a7),
461 | .a8 (a8),
462 | .a9 (a9),
463 | .a10 (a10),
464 | .a11 (a11),
465 | .a12 (a12),
466 | .a13 (a13),
467 | .a14 (a14),
468 | .a15 (a15),
469 | .sort0 (sort0),
470 | .sort1 (sort1),
471 | .sort2 (sort2),
472 | .sort3 (sort3),
473 | .sort4 (sort4),
474 | .sort5 (sort5),
475 | .sort6 (sort6),
476 | .sort7 (sort7),
477 | .sort8 (sort8),
478 | .sort9 (sort9),
479 | .sort10 (sort10),
480 | .sort11 (sort11),
481 | .sort12 (sort12),
482 | .sort13 (sort13),
483 | .sort14 (sort14),
484 | .sort15 (sort15)
485 | );
486 |
487 | // traverse
488 | genvar j;
489 | reg [8:0] code_result [0:9];
490 | reg [3:0] code_length [0:9];
491 | reg [4:0] index [0:9];
492 |
493 | generate
494 | for (j = 0; j < 10; j = j + 1) begin
495 | always @(posedge clk or negedge rst_n) begin
496 | if (~rst_n) begin
497 | code_result[j] <= 9'b0;
498 | code_length[j] <= 4'b0;
499 | index[j] <= 5'b0;
500 | end else if (state == TRAVERSE) begin
501 | case (phase)
502 | 4'd0: begin
503 | code_result[j][0] <= mem[j][13];
504 | code_length[j] <= code_length[j] + 1;
505 | index[j] <= mem[j][18:14];
506 | end
507 | 4'd1: begin
508 | if (index[j] != 5'd18) begin
509 | code_result[j][1] <= mem[index[j]][13];
510 | code_length[j] <= code_length[j] + 1;
511 | index[j] <= mem[index[j]][18:14];
512 | end
513 | end
514 | 4'd2: begin
515 | if (index[j] != 5'd18) begin
516 | code_result[j][2] <= mem[index[j]][13];
517 | code_length[j] <= code_length[j] + 1;
518 | index[j] <= mem[index[j]][18:14];
519 | end
520 | end
521 | 4'd3: begin
522 | if (index[j] != 5'd18) begin
523 | code_result[j][3] <= mem[index[j]][13];
524 | code_length[j] <= code_length[j] + 1;
525 | index[j] <= mem[index[j]][18:14];
526 | end
527 | end
528 | 4'd4: begin
529 | if (index[j] != 5'd18) begin
530 | code_result[j][4] <= mem[index[j]][13];
531 | code_length[j] <= code_length[j] + 1;
532 | index[j] <= mem[index[j]][18:14];
533 | end
534 | end
535 | 4'd5: begin
536 | if (index[j] != 5'd18) begin
537 | code_result[j][5] <= mem[index[j]][13];
538 | code_length[j] <= code_length[j] + 1;
539 | index[j] <= mem[index[j]][18:14];
540 | end
541 | end
542 | 4'd6: begin
543 | if (index[j] != 5'd18) begin
544 | code_result[j][6] <= mem[index[j]][13];
545 | code_length[j] <= code_length[j] + 1;
546 | index[j] <= mem[index[j]][18:14];
547 | end
548 | end
549 | 4'd7: begin
550 | if (index[j] != 5'd18) begin
551 | code_result[j][7] <= mem[index[j]][13];
552 | code_length[j] <= code_length[j] + 1;
553 | index[j] <= mem[index[j]][18:14];
554 | end
555 | end
556 | 4'd8: begin
557 | if (index[j] != 5'd18) begin
558 | code_result[j][8] <= mem[index[j]][13];
559 | code_length[j] <= code_length[j] + 1;
560 | index[j] <= mem[index[j]][18:14];
561 | end
562 | end
563 | default: begin
564 | code_result[j] <= 9'b0;
565 | code_length[j] <= 4'b0;
566 | index[j] <= 5'b0;
567 | end
568 | endcase
569 | end
570 | end
571 | end
572 | endgenerate
573 |
574 | always @(posedge clk or negedge rst_n) begin
575 | if (~rst_n) begin
576 | data_out <= 9'd0;
577 | data_len <= 4'd0;
578 | end
579 | else begin
580 | if (next_state == OUTPUT) begin
581 | data_out <= code_result[next_phase];
582 | data_len <= code_length[next_phase];
583 | end
584 | else begin
585 | data_out <= 9'd0;
586 | data_len <= 4'd0;
587 | end
588 | end
589 | end
590 |
591 | assign trans_start = (state == OUTPUT) ? 1'b1 : 1'b0;
592 |
593 | endmodule
594 |
--------------------------------------------------------------------------------
/rtl model/freqcount.v:
--------------------------------------------------------------------------------
1 | /****************************************************************
2 | /*
3 | /* Description:
4 | /* count the frequency of each signal,
5 | /* for the huffman codeing processs afterwards
6 | /* Author:
7 | /* Guozhu Xin
8 | /* Date:
9 | /* 2017/7/11
10 | /* Email:
11 | /* spikexin@outlook.com
12 | ******************************************************************/
13 | /* data_out bit domain
14 | /* | 18 --- 14 | 13 | 12 --- 8 | 7 --- 0
15 | /* | 0-18 | | 0-18 | 0-254
16 | /* | parent number | 0 or 1 |number (0-9)| frequency
17 | ******************************************************************/
18 | /*
19 |
20 | NOTICE: 1.make sure the number of signals is less than 255 !!
21 | 2. the coding result may be different from the software,
22 | but they generate a same huffman tree,only the coding method
23 | is different
24 |
25 | ********************************************************************/
26 | module freqcount(
27 | input clk,
28 | input rst_n,
29 | input start, // pulse signal
30 | input start_done, // along with the last data_in, pulse signal
31 | input [3:0] data_in,
32 | input ack_coding, // return signal of huffman coding module
33 | output reg req_coding, // request signal of huffman coding module
34 | output wire [18:0] data_out0,
35 | output wire [18:0] data_out1,
36 | output wire [18:0] data_out2,
37 | output wire [18:0] data_out3,
38 | output wire [18:0] data_out4,
39 | output wire [18:0] data_out5,
40 | output wire [18:0] data_out6,
41 | output wire [18:0] data_out7,
42 | output wire [18:0] data_out8,
43 | output wire [18:0] data_out9
44 | );
45 |
46 | reg processing;
47 |
48 | always @(posedge clk or negedge rst_n) begin
49 | if (~rst_n)
50 | processing <= 1'b0;
51 | else if (start)
52 | processing <= 1'b1;
53 | else if (start_done)
54 | processing <= 1'b0;
55 | end
56 |
57 | reg [7:0] data_mem [0:9];
58 |
59 | integer i;
60 | always @(posedge clk or negedge rst_n) begin
61 | if (~rst_n) begin
62 | for (i = 0; i < 10; i = i + 1) begin
63 | data_mem[i] <= 8'b0;
64 | end
65 | end else if (processing) begin
66 | case(data_in)
67 | 4'b0000: data_mem[0] <= data_mem[0] + 1;
68 | 4'b0001: data_mem[1] <= data_mem[1] + 1;
69 | 4'b0010: data_mem[2] <= data_mem[2] + 1;
70 | 4'b0011: data_mem[3] <= data_mem[3] + 1;
71 | 4'b0100: data_mem[4] <= data_mem[4] + 1;
72 | 4'b0101: data_mem[5] <= data_mem[5] + 1;
73 | 4'b0110: data_mem[6] <= data_mem[6] + 1;
74 | 4'b0111: data_mem[7] <= data_mem[7] + 1;
75 | 4'b1000: data_mem[8] <= data_mem[8] + 1;
76 | 4'b1001: data_mem[9] <= data_mem[9] + 1;
77 | default: ;
78 | endcase
79 | end
80 | end
81 |
82 | always @(posedge clk or negedge rst_n) begin
83 | if (~rst_n)
84 | req_coding <= 1'b0;
85 | else if (start_done)
86 | req_coding <= 1'b1;
87 | else if (ack_coding)
88 | req_coding <= 1'b0;
89 | end
90 |
91 | assign data_out0 = {6'b0, 5'd0, data_mem[0]};
92 | assign data_out1 = {6'b0, 5'd1, data_mem[1]};
93 | assign data_out2 = {6'b0, 5'd2, data_mem[2]};
94 | assign data_out3 = {6'b0, 5'd3, data_mem[3]};
95 | assign data_out4 = {6'b0, 5'd4, data_mem[4]};
96 | assign data_out5 = {6'b0, 5'd5, data_mem[5]};
97 | assign data_out6 = {6'b0, 5'd6, data_mem[6]};
98 | assign data_out7 = {6'b0, 5'd7, data_mem[7]};
99 | assign data_out8 = {6'b0, 5'd8, data_mem[8]};
100 | assign data_out9 = {6'b0, 5'd9, data_mem[9]};
101 |
102 | endmodule
103 |
--------------------------------------------------------------------------------
/rtl model/huffman_top.v:
--------------------------------------------------------------------------------
1 | /****************************************************************
2 | /*
3 | /* Description:
4 | /* top file
5 | /* Author:
6 | /* Guozhu Xin
7 | /* Date:
8 | /* 2017/7/30
9 | /* Email:
10 | /* spikexin@outlook.com
11 | ******************************************************************/
12 |
13 | module huffman_top(
14 | input clk,
15 | input rst_n,
16 | input start, // pulse signal
17 | input start_done, // along with the last data_in, pulse signal
18 | input [3:0] data_in,
19 | output wire output_data, // MSB first
20 | output wire output_start,
21 | output wire output_done
22 | );
23 |
24 | wire ack_coding;
25 | wire req_coding;
26 | wire [18:0] data0;
27 | wire [18:0] data1;
28 | wire [18:0] data2;
29 | wire [18:0] data3;
30 | wire [18:0] data4;
31 | wire [18:0] data5;
32 | wire [18:0] data6;
33 | wire [18:0] data7;
34 | wire [18:0] data8;
35 | wire [18:0] data9;
36 | wire [8:0] data_para;
37 | wire [3:0] data_len;
38 | wire trans_start;
39 |
40 | freqcount freq_inst(
41 | .clk (clk),
42 | .rst_n (rst_n),
43 | .start (start), // pulse signal
44 | .start_done (start_done), // along with the last data_in, pulse signal
45 | .data_in (data_in),
46 | .ack_coding (ack_coding), // return signal of huffman coding module
47 | .req_coding (req_coding), // request signal of huffman coding module
48 | .data_out0 (data0),
49 | .data_out1 (data1),
50 | .data_out2 (data2),
51 | .data_out3 (data3),
52 | .data_out4 (data4),
53 | .data_out5 (data5),
54 | .data_out6 (data6),
55 | .data_out7 (data7),
56 | .data_out8 (data8),
57 | .data_out9 (data9)
58 | );
59 |
60 | HuffmanCode huffmancode (
61 | .clk (clk),
62 | .rst_n (rst_n),
63 | .data_in0 (data0),
64 | .data_in1 (data1),
65 | .data_in2 (data2),
66 | .data_in3 (data3),
67 | .data_in4 (data4),
68 | .data_in5 (data5),
69 | .data_in6 (data6),
70 | .data_in7 (data7),
71 | .data_in8 (data8),
72 | .data_in9 (data9),
73 | .req_coding (req_coding),
74 | .ack_coding (ack_coding),
75 | .data_out (data_para),
76 | .data_len (data_len),
77 | .trans_start(trans_start)
78 | );
79 |
80 | para2ser para2ser_inst(
81 | .clk (clk),
82 | .rst_n (rst_n),
83 | .trans_start (trans_start), // indicate tansform begin, level signal
84 | .data (data_para), // signal:0-9 max coding length:9
85 | .data_len (data_len), // 9 - 1
86 | .output_data (output_data), // MSB first
87 | .output_start (output_start),
88 | .output_done (output_done)
89 | );
90 |
91 | endmodule
92 |
--------------------------------------------------------------------------------
/rtl model/para2ser.v:
--------------------------------------------------------------------------------
1 | /****************************************************************
2 | /*
3 | /* Description:
4 | /* change internal parallel data to output
5 | /* serial data
6 | /* Author:
7 | /* Guozhu Xin
8 | /* Date:
9 | /* 2017/7/10
10 | /* Email:
11 | /* spikexin@outlook.com
12 | ******************************************************************/
13 |
14 | module para2ser(
15 | input clk,
16 | input rst_n,
17 | input trans_start, // indicate tansform begin, level signal
18 | input [8:0] data, // signal:0-9 max coding length:9
19 | input [3:0] data_len, // 9 - 1
20 | output wire output_data, // MSB first
21 | output wire output_start,
22 | output wire output_done
23 | );
24 |
25 | reg [3:0] data_cnt;
26 | reg [8:0] data_reg;
27 |
28 | always @(posedge clk or negedge rst_n) begin
29 | if(~rst_n) begin
30 | data_cnt <= 4'b0;
31 | data_reg <= 9'b0;
32 | end
33 | else if(trans_start) begin
34 | data_cnt <= (data_cnt == 4'b0) ? data_len-1 : data_cnt-1;
35 | data_reg <= data;
36 | end
37 | end
38 |
39 | reg trans_start_q1;
40 | reg trans_start_q2;
41 | always @(posedge clk or negedge rst_n) begin
42 | if (~rst_n) begin
43 | trans_start_q1 <= 1'b0;
44 | trans_start_q2 <= 1'b0;
45 | end
46 | else begin
47 | trans_start_q1 <= trans_start;
48 | trans_start_q2 <= trans_start_q1;
49 | end
50 | end
51 |
52 | assign output_start = trans_start & ~trans_start_q1;
53 | assign output_done = ~trans_start_q1 & trans_start_q2;
54 | assign output_data = (data_reg >> data_cnt) & 1'b1;
55 |
56 | endmodule
57 |
--------------------------------------------------------------------------------
/rtl model/sortnet/BitonicSortX4.v:
--------------------------------------------------------------------------------
1 | module BitonicSortX4 # (
2 | parameter DSIZE = 18,
3 | parameter OFFSET = 8
4 | )(
5 | input [DSIZE-1:0] a0,
6 | input [DSIZE-1:0] a1,
7 | input [DSIZE-1:0] a2,
8 | input [DSIZE-1:0] a3,
9 | output wire [DSIZE-1:0] sort0,
10 | output wire [DSIZE-1:0] sort1,
11 | output wire [DSIZE-1:0] sort2,
12 | output wire [DSIZE-1:0] sort3
13 | );
14 |
15 | wire [DSIZE-1:0] sort0_0;
16 | wire [DSIZE-1:0] sort0_1;
17 | wire [DSIZE-1:0] sort1_0;
18 | wire [DSIZE-1:0] sort1_1;
19 |
20 | // half-clean
21 | SortElement # (
22 | .DSIZE (DSIZE),
23 | .OFFSET(OFFSET)
24 | ) sort_inst0 (
25 | .a(a0),
26 | .b(a2),
27 | .sort0(sort0_0),
28 | .sort1(sort0_1)
29 | );
30 | SortElement # (
31 | .DSIZE (DSIZE),
32 | .OFFSET(OFFSET)
33 | ) sort_inst1 (
34 | .a(a1),
35 | .b(a3),
36 | .sort0(sort1_0),
37 | .sort1(sort1_1)
38 | );
39 |
40 | // divide sort
41 | SortElement # (
42 | .DSIZE (DSIZE),
43 | .OFFSET(OFFSET)
44 | ) sort_inst2 (
45 | .a(sort0_0),
46 | .b(sort1_0),
47 | .sort0(sort0),
48 | .sort1(sort1)
49 | );
50 | SortElement # (
51 | .DSIZE (DSIZE),
52 | .OFFSET(OFFSET)
53 | ) sort_inst3 (
54 | .a(sort0_1),
55 | .b(sort1_1),
56 | .sort0(sort2),
57 | .sort1(sort3)
58 | );
59 |
60 | endmodule
61 |
--------------------------------------------------------------------------------
/rtl model/sortnet/BitonicSortX8.v:
--------------------------------------------------------------------------------
1 | module BitonicSortX8 # (
2 | parameter DSIZE = 18,
3 | parameter OFFSET = 8
4 | )(
5 | input [DSIZE-1:0] a0,
6 | input [DSIZE-1:0] a1,
7 | input [DSIZE-1:0] a2,
8 | input [DSIZE-1:0] a3,
9 | input [DSIZE-1:0] a4,
10 | input [DSIZE-1:0] a5,
11 | input [DSIZE-1:0] a6,
12 | input [DSIZE-1:0] a7,
13 | output wire [DSIZE-1:0] sort0,
14 | output wire [DSIZE-1:0] sort1,
15 | output wire [DSIZE-1:0] sort2,
16 | output wire [DSIZE-1:0] sort3,
17 | output wire [DSIZE-1:0] sort4,
18 | output wire [DSIZE-1:0] sort5,
19 | output wire [DSIZE-1:0] sort6,
20 | output wire [DSIZE-1:0] sort7
21 | );
22 |
23 | wire [DSIZE-1:0] sort0_0;
24 | wire [DSIZE-1:0] sort0_1;
25 | wire [DSIZE-1:0] sort1_0;
26 | wire [DSIZE-1:0] sort1_1;
27 | wire [DSIZE-1:0] sort2_0;
28 | wire [DSIZE-1:0] sort2_1;
29 | wire [DSIZE-1:0] sort3_0;
30 | wire [DSIZE-1:0] sort3_1;
31 |
32 | // half-clean
33 | SortElement # (
34 | .DSIZE (DSIZE),
35 | .OFFSET(OFFSET)
36 | ) sort_inst0 (
37 | .a(a0),
38 | .b(a4),
39 | .sort0(sort0_0),
40 | .sort1(sort0_1)
41 | );
42 | SortElement # (
43 | .DSIZE (DSIZE),
44 | .OFFSET(OFFSET)
45 | ) sort_inst1 (
46 | .a(a1),
47 | .b(a5),
48 | .sort0(sort1_0),
49 | .sort1(sort1_1)
50 | );
51 | SortElement # (
52 | .DSIZE (DSIZE),
53 | .OFFSET(OFFSET)
54 | ) sort_inst2 (
55 | .a(a2),
56 | .b(a6),
57 | .sort0(sort2_0),
58 | .sort1(sort2_1)
59 | );
60 | SortElement # (
61 | .DSIZE (DSIZE),
62 | .OFFSET(OFFSET)
63 | ) sort_inst3 (
64 | .a(a3),
65 | .b(a7),
66 | .sort0(sort3_0),
67 | .sort1(sort3_1)
68 | );
69 | // divide sort
70 | BitonicSortX4 # (
71 | .DSIZE (DSIZE),
72 | .OFFSET(OFFSET)
73 | ) bitonicsortx4_inst0 (
74 | .a0 (sort0_0),
75 | .a1 (sort1_0),
76 | .a2 (sort2_0),
77 | .a3 (sort3_0),
78 | .sort0 (sort0),
79 | .sort1 (sort1),
80 | .sort2 (sort2),
81 | .sort3 (sort3)
82 | );
83 | BitonicSortX4 # (
84 | .DSIZE (DSIZE),
85 | .OFFSET(OFFSET)
86 | ) bitonicsortx4_inst1 (
87 | .a0 (sort0_1),
88 | .a1 (sort1_1),
89 | .a2 (sort2_1),
90 | .a3 (sort3_1),
91 | .sort0 (sort4),
92 | .sort1 (sort5),
93 | .sort2 (sort6),
94 | .sort3 (sort7)
95 | );
96 |
97 | endmodule
98 |
--------------------------------------------------------------------------------
/rtl model/sortnet/SortElement.v:
--------------------------------------------------------------------------------
1 | module SortElement # (
2 | parameter DSIZE = 18,
3 | parameter OFFSET = 8
4 | )(
5 | input [DSIZE-1:0] a,
6 | input [DSIZE-1:0] b,
7 | output wire [DSIZE-1:0] sort0,
8 | output wire [DSIZE-1:0] sort1
9 | );
10 |
11 | assign sort0 = a[OFFSET-1:0] > b[OFFSET-1:0] ? b : a;
12 | assign sort1 = a[OFFSET-1:0] > b[OFFSET-1:0] ? a : b;
13 |
14 | endmodule
15 |
--------------------------------------------------------------------------------
/rtl model/sortnet/SortX16.v:
--------------------------------------------------------------------------------
1 | module SortX16 # (
2 | parameter DSIZE = 18,
3 | parameter OFFSET = 8
4 | )(
5 | input [DSIZE-1:0] a0,
6 | input [DSIZE-1:0] a1,
7 | input [DSIZE-1:0] a2,
8 | input [DSIZE-1:0] a3,
9 | input [DSIZE-1:0] a4,
10 | input [DSIZE-1:0] a5,
11 | input [DSIZE-1:0] a6,
12 | input [DSIZE-1:0] a7,
13 | input [DSIZE-1:0] a8,
14 | input [DSIZE-1:0] a9,
15 | input [DSIZE-1:0] a10,
16 | input [DSIZE-1:0] a11,
17 | input [DSIZE-1:0] a12,
18 | input [DSIZE-1:0] a13,
19 | input [DSIZE-1:0] a14,
20 | input [DSIZE-1:0] a15,
21 | output wire [DSIZE-1:0] sort0,
22 | output wire [DSIZE-1:0] sort1,
23 | output wire [DSIZE-1:0] sort2,
24 | output wire [DSIZE-1:0] sort3,
25 | output wire [DSIZE-1:0] sort4,
26 | output wire [DSIZE-1:0] sort5,
27 | output wire [DSIZE-1:0] sort6,
28 | output wire [DSIZE-1:0] sort7,
29 | output wire [DSIZE-1:0] sort8,
30 | output wire [DSIZE-1:0] sort9,
31 | output wire [DSIZE-1:0] sort10,
32 | output wire [DSIZE-1:0] sort11,
33 | output wire [DSIZE-1:0] sort12,
34 | output wire [DSIZE-1:0] sort13,
35 | output wire [DSIZE-1:0] sort14,
36 | output wire [DSIZE-1:0] sort15
37 | );
38 |
39 | wire [DSIZE-1:0] sortX8_0_0;
40 | wire [DSIZE-1:0] sortX8_0_1;
41 | wire [DSIZE-1:0] sortX8_0_2;
42 | wire [DSIZE-1:0] sortX8_0_3;
43 | wire [DSIZE-1:0] sortX8_0_4;
44 | wire [DSIZE-1:0] sortX8_0_5;
45 | wire [DSIZE-1:0] sortX8_0_6;
46 | wire [DSIZE-1:0] sortX8_0_7;
47 | wire [DSIZE-1:0] sortX8_1_0;
48 | wire [DSIZE-1:0] sortX8_1_1;
49 | wire [DSIZE-1:0] sortX8_1_2;
50 | wire [DSIZE-1:0] sortX8_1_3;
51 | wire [DSIZE-1:0] sortX8_1_4;
52 | wire [DSIZE-1:0] sortX8_1_5;
53 | wire [DSIZE-1:0] sortX8_1_6;
54 | wire [DSIZE-1:0] sortX8_1_7;
55 |
56 | wire [DSIZE-1:0] sort0_0;
57 | wire [DSIZE-1:0] sort0_1;
58 | wire [DSIZE-1:0] sort1_0;
59 | wire [DSIZE-1:0] sort1_1;
60 | wire [DSIZE-1:0] sort2_0;
61 | wire [DSIZE-1:0] sort2_1;
62 | wire [DSIZE-1:0] sort3_0;
63 | wire [DSIZE-1:0] sort3_1;
64 | wire [DSIZE-1:0] sort4_0;
65 | wire [DSIZE-1:0] sort4_1;
66 | wire [DSIZE-1:0] sort5_0;
67 | wire [DSIZE-1:0] sort5_1;
68 | wire [DSIZE-1:0] sort6_0;
69 | wire [DSIZE-1:0] sort6_1;
70 | wire [DSIZE-1:0] sort7_0;
71 | wire [DSIZE-1:0] sort7_1;
72 |
73 | // divide sort
74 | SortX8 # (
75 | .DSIZE (DSIZE),
76 | .OFFSET(OFFSET)
77 | ) sortX8_inst0 (
78 | .a0 (a0),
79 | .a1 (a1),
80 | .a2 (a2),
81 | .a3 (a3),
82 | .a4 (a4),
83 | .a5 (a5),
84 | .a6 (a6),
85 | .a7 (a7),
86 | .sort0 (sortX8_0_0),
87 | .sort1 (sortX8_0_1),
88 | .sort2 (sortX8_0_2),
89 | .sort3 (sortX8_0_3),
90 | .sort4 (sortX8_0_4),
91 | .sort5 (sortX8_0_5),
92 | .sort6 (sortX8_0_6),
93 | .sort7 (sortX8_0_7)
94 | );
95 | SortX8 # (
96 | .DSIZE (DSIZE),
97 | .OFFSET(OFFSET)
98 | ) sortX8_inst1 (
99 | .a0 (a8),
100 | .a1 (a9),
101 | .a2 (a10),
102 | .a3 (a11),
103 | .a4 (a12),
104 | .a5 (a13),
105 | .a6 (a14),
106 | .a7 (a15),
107 | .sort0 (sortX8_1_0),
108 | .sort1 (sortX8_1_1),
109 | .sort2 (sortX8_1_2),
110 | .sort3 (sortX8_1_3),
111 | .sort4 (sortX8_1_4),
112 | .sort5 (sortX8_1_5),
113 | .sort6 (sortX8_1_6),
114 | .sort7 (sortX8_1_7)
115 | );
116 |
117 | // merge
118 | SortElement # (
119 | .DSIZE (DSIZE),
120 | .OFFSET(OFFSET)
121 | ) sort_inst0 (
122 | .a(sortX8_0_0),
123 | .b(sortX8_1_7),
124 | .sort0(sort0_0),
125 | .sort1(sort0_1)
126 | );
127 | SortElement # (
128 | .DSIZE (DSIZE),
129 | .OFFSET(OFFSET)
130 | ) sort_inst1 (
131 | .a(sortX8_0_1),
132 | .b(sortX8_1_6),
133 | .sort0(sort1_0),
134 | .sort1(sort1_1)
135 | );
136 | SortElement # (
137 | .DSIZE (DSIZE),
138 | .OFFSET(OFFSET)
139 | ) sort_inst2 (
140 | .a(sortX8_0_2),
141 | .b(sortX8_1_5),
142 | .sort0(sort2_0),
143 | .sort1(sort2_1)
144 | );
145 | SortElement # (
146 | .DSIZE (DSIZE),
147 | .OFFSET(OFFSET)
148 | ) sort_inst3 (
149 | .a(sortX8_0_3),
150 | .b(sortX8_1_4),
151 | .sort0(sort3_0),
152 | .sort1(sort3_1)
153 | );
154 | SortElement # (
155 | .DSIZE (DSIZE),
156 | .OFFSET(OFFSET)
157 | ) sort_inst4 (
158 | .a(sortX8_0_4),
159 | .b(sortX8_1_3),
160 | .sort0(sort4_0),
161 | .sort1(sort4_1)
162 | );
163 | SortElement # (
164 | .DSIZE (DSIZE),
165 | .OFFSET(OFFSET)
166 | ) sort_inst5 (
167 | .a(sortX8_0_5),
168 | .b(sortX8_1_2),
169 | .sort0(sort5_0),
170 | .sort1(sort5_1)
171 | );
172 | SortElement # (
173 | .DSIZE (DSIZE),
174 | .OFFSET(OFFSET)
175 | ) sort_inst6 (
176 | .a(sortX8_0_6),
177 | .b(sortX8_1_1),
178 | .sort0(sort6_0),
179 | .sort1(sort6_1)
180 | );
181 | SortElement # (
182 | .DSIZE (DSIZE),
183 | .OFFSET(OFFSET)
184 | ) sort_inst7 (
185 | .a(sortX8_0_7),
186 | .b(sortX8_1_0),
187 | .sort0(sort7_0),
188 | .sort1(sort7_1)
189 | );
190 |
191 | // bitonic
192 | BitonicSortX8 # (
193 | .DSIZE (DSIZE),
194 | .OFFSET(OFFSET)
195 | ) bitonicsortx8_inst0 (
196 | .a0 (sort0_0),
197 | .a1 (sort1_0),
198 | .a2 (sort2_0),
199 | .a3 (sort3_0),
200 | .a4 (sort4_0),
201 | .a5 (sort5_0),
202 | .a6 (sort6_0),
203 | .a7 (sort7_0),
204 | .sort0 (sort0),
205 | .sort1 (sort1),
206 | .sort2 (sort2),
207 | .sort3 (sort3),
208 | .sort4 (sort4),
209 | .sort5 (sort5),
210 | .sort6 (sort6),
211 | .sort7 (sort7)
212 | );
213 | BitonicSortX8 # (
214 | .DSIZE (DSIZE),
215 | .OFFSET(OFFSET)
216 | ) bitonicsortx8_inst1 (
217 | .a0 (sort7_1),
218 | .a1 (sort6_1),
219 | .a2 (sort5_1),
220 | .a3 (sort4_1),
221 | .a4 (sort3_1),
222 | .a5 (sort2_1),
223 | .a6 (sort1_1),
224 | .a7 (sort0_1),
225 | .sort0 (sort8),
226 | .sort1 (sort9),
227 | .sort2 (sort10),
228 | .sort3 (sort11),
229 | .sort4 (sort12),
230 | .sort5 (sort13),
231 | .sort6 (sort14),
232 | .sort7 (sort15)
233 | );
234 |
235 | endmodule
236 |
--------------------------------------------------------------------------------
/rtl model/sortnet/SortX4.v:
--------------------------------------------------------------------------------
1 | module SortX4 # (
2 | parameter DSIZE = 18,
3 | parameter OFFSET = 8
4 | )(
5 | input [DSIZE-1:0] a0,
6 | input [DSIZE-1:0] a1,
7 | input [DSIZE-1:0] a2,
8 | input [DSIZE-1:0] a3,
9 | output wire [DSIZE-1:0] sort0,
10 | output wire [DSIZE-1:0] sort1,
11 | output wire [DSIZE-1:0] sort2,
12 | output wire [DSIZE-1:0] sort3
13 | );
14 |
15 | wire [DSIZE-1:0] sort0_0;
16 | wire [DSIZE-1:0] sort0_1;
17 | wire [DSIZE-1:0] sort1_0;
18 | wire [DSIZE-1:0] sort1_1;
19 | wire [DSIZE-1:0] sort2_0;
20 | wire [DSIZE-1:0] sort2_1;
21 | wire [DSIZE-1:0] sort3_0;
22 | wire [DSIZE-1:0] sort3_1;
23 |
24 | // divide sort
25 | SortElement # (
26 | .DSIZE (DSIZE),
27 | .OFFSET(OFFSET)
28 | ) sort_inst0 (
29 | .a(a0),
30 | .b(a1),
31 | .sort0(sort0_0),
32 | .sort1(sort0_1)
33 | );
34 | SortElement # (
35 | .DSIZE (DSIZE),
36 | .OFFSET(OFFSET)
37 | ) sort_inst1 (
38 | .a(a2),
39 | .b(a3),
40 | .sort0(sort1_0),
41 | .sort1(sort1_1)
42 | );
43 |
44 | // merge
45 | SortElement # (
46 | .DSIZE (DSIZE),
47 | .OFFSET(OFFSET)
48 | ) sort_inst2 (
49 | .a(sort0_0),
50 | .b(sort1_1),
51 | .sort0(sort2_0),
52 | .sort1(sort2_1)
53 | );
54 | SortElement # (
55 | .DSIZE (DSIZE),
56 | .OFFSET(OFFSET)
57 | ) sort_inst3 (
58 | .a(sort0_1),
59 | .b(sort1_0),
60 | .sort0(sort3_0),
61 | .sort1(sort3_1)
62 | );
63 |
64 | SortElement # (
65 | .DSIZE (DSIZE),
66 | .OFFSET(OFFSET)
67 | ) sort_inst4 (
68 | .a(sort2_0),
69 | .b(sort3_0),
70 | .sort0(sort0),
71 | .sort1(sort1)
72 | );
73 | SortElement # (
74 | .DSIZE (DSIZE),
75 | .OFFSET(OFFSET)
76 | ) sort_inst5 (
77 | .a(sort3_1),
78 | .b(sort2_1),
79 | .sort0(sort2),
80 | .sort1(sort3)
81 | );
82 |
83 | endmodule
84 |
--------------------------------------------------------------------------------
/rtl model/sortnet/SortX8.v:
--------------------------------------------------------------------------------
1 | module SortX8 # (
2 | parameter DSIZE = 18,
3 | parameter OFFSET = 8
4 | )(
5 | input [DSIZE-1:0] a0,
6 | input [DSIZE-1:0] a1,
7 | input [DSIZE-1:0] a2,
8 | input [DSIZE-1:0] a3,
9 | input [DSIZE-1:0] a4,
10 | input [DSIZE-1:0] a5,
11 | input [DSIZE-1:0] a6,
12 | input [DSIZE-1:0] a7,
13 | output wire [DSIZE-1:0] sort0,
14 | output wire [DSIZE-1:0] sort1,
15 | output wire [DSIZE-1:0] sort2,
16 | output wire [DSIZE-1:0] sort3,
17 | output wire [DSIZE-1:0] sort4,
18 | output wire [DSIZE-1:0] sort5,
19 | output wire [DSIZE-1:0] sort6,
20 | output wire [DSIZE-1:0] sort7
21 | );
22 |
23 | wire [DSIZE-1:0] sortx4_0_0;
24 | wire [DSIZE-1:0] sortx4_0_1;
25 | wire [DSIZE-1:0] sortx4_0_2;
26 | wire [DSIZE-1:0] sortx4_0_3;
27 | wire [DSIZE-1:0] sortx4_1_0;
28 | wire [DSIZE-1:0] sortx4_1_1;
29 | wire [DSIZE-1:0] sortx4_1_2;
30 | wire [DSIZE-1:0] sortx4_1_3;
31 |
32 | wire [DSIZE-1:0] sort0_0;
33 | wire [DSIZE-1:0] sort0_1;
34 | wire [DSIZE-1:0] sort1_0;
35 | wire [DSIZE-1:0] sort1_1;
36 | wire [DSIZE-1:0] sort2_0;
37 | wire [DSIZE-1:0] sort2_1;
38 | wire [DSIZE-1:0] sort3_0;
39 | wire [DSIZE-1:0] sort3_1;
40 |
41 | // divide sort
42 | SortX4 # (
43 | .DSIZE (DSIZE),
44 | .OFFSET(OFFSET)
45 | ) sortx4_inst0 (
46 | .a0 (a0),
47 | .a1 (a1),
48 | .a2 (a2),
49 | .a3 (a3),
50 | .sort0 (sortx4_0_0),
51 | .sort1 (sortx4_0_1),
52 | .sort2 (sortx4_0_2),
53 | .sort3 (sortx4_0_3)
54 | );
55 | SortX4 # (
56 | .DSIZE (DSIZE),
57 | .OFFSET(OFFSET)
58 | ) sortx4_inst1 (
59 | .a0 (a4),
60 | .a1 (a5),
61 | .a2 (a6),
62 | .a3 (a7),
63 | .sort0 (sortx4_1_0),
64 | .sort1 (sortx4_1_1),
65 | .sort2 (sortx4_1_2),
66 | .sort3 (sortx4_1_3)
67 | );
68 |
69 | // merge
70 | SortElement # (
71 | .DSIZE (DSIZE),
72 | .OFFSET(OFFSET)
73 | ) sort_inst0 (
74 | .a(sortx4_0_0),
75 | .b(sortx4_1_3),
76 | .sort0(sort0_0),
77 | .sort1(sort0_1)
78 | );
79 | SortElement # (
80 | .DSIZE (DSIZE),
81 | .OFFSET(OFFSET)
82 | ) sort_inst1 (
83 | .a(sortx4_0_1),
84 | .b(sortx4_1_2),
85 | .sort0(sort1_0),
86 | .sort1(sort1_1)
87 | );
88 | SortElement # (
89 | .DSIZE (DSIZE),
90 | .OFFSET(OFFSET)
91 | ) sort_inst2 (
92 | .a(sortx4_0_2),
93 | .b(sortx4_1_1),
94 | .sort0(sort2_0),
95 | .sort1(sort2_1)
96 | );
97 | SortElement # (
98 | .DSIZE (DSIZE),
99 | .OFFSET(OFFSET)
100 | ) sort_inst3 (
101 | .a(sortx4_0_3),
102 | .b(sortx4_1_0),
103 | .sort0(sort3_0),
104 | .sort1(sort3_1)
105 | );
106 |
107 | // bitonic
108 | BitonicSortX4 # (
109 | .DSIZE (DSIZE),
110 | .OFFSET(OFFSET)
111 | ) bitonicsortx4_inst0 (
112 | .a0 (sort0_0),
113 | .a1 (sort1_0),
114 | .a2 (sort2_0),
115 | .a3 (sort3_0),
116 | .sort0 (sort0),
117 | .sort1 (sort1),
118 | .sort2 (sort2),
119 | .sort3 (sort3)
120 | );
121 | BitonicSortX4 # (
122 | .DSIZE (DSIZE),
123 | .OFFSET(OFFSET)
124 | ) bitonicsortx4_inst1 (
125 | .a0 (sort3_1),
126 | .a1 (sort2_1),
127 | .a2 (sort1_1),
128 | .a3 (sort0_1),
129 | .sort0 (sort4),
130 | .sort1 (sort5),
131 | .sort2 (sort6),
132 | .sort3 (sort7)
133 | );
134 |
135 | endmodule
136 |
--------------------------------------------------------------------------------
/simulation/huffman_test.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 2017/07/27 17:45:20
7 | // Design Name:
8 | // Module Name: huffmancode
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 | module huffmancode_test();
23 | reg clk;
24 | reg rst_n;
25 | reg start; // pulse signal
26 | reg start_done; // along with the last data_in, pulse signal
27 | reg [3:0] data_in;
28 |
29 | initial begin
30 | rst_n = 1'b1;
31 | #10 rst_n = 1'b0;
32 | #10 rst_n = 1'b1;
33 | end
34 | initial begin
35 | clk = 1'b1;
36 | forever #1 clk = ~clk;
37 | end
38 | initial begin
39 | start = 1'b0;
40 | #50 start = 1'b1;
41 | #2 start = 1'b0;
42 | end
43 | initial begin
44 | data_in = 4'b0;
45 | #52 data_in = 4'd0; // 5
46 | #10 data_in = 4'd1; // 1
47 | #2 data_in = 4'd2; // 3
48 | #6 data_in = 4'd3; // 2
49 | #4 data_in = 4'd4; // 9
50 | #18 data_in = 4'd5; // 7
51 | #14 data_in = 4'd6; // 4
52 | #8 data_in = 4'd7; // 8
53 | #16 data_in = 4'd8; // 6
54 | #12 data_in = 4'd0; // 0
55 | end
56 | initial begin
57 | start_done = 1'b0;
58 | #140 start_done = 1'b1;
59 | #2 start_done = 1'b0;
60 | end
61 |
62 | wire output_data; // MSB first
63 | wire output_start;
64 | wire output_done;
65 |
66 | huffman_top sim_top(
67 | .clk (clk),
68 | .rst_n (rst_n),
69 | .start (start), // pulse signal
70 | .start_done (start_done), // along with the last data_in, pulse signal
71 | .data_in (data_in),
72 | .output_data (output_data), // MSB first
73 | .output_start (output_start),
74 | .output_done (output_done)
75 | );
76 |
77 | endmodule
78 |
--------------------------------------------------------------------------------
/simulation/sortx16_sim.v:
--------------------------------------------------------------------------------
1 | `timescale 1ns / 1ps
2 | //////////////////////////////////////////////////////////////////////////////////
3 | // Company:
4 | // Engineer:
5 | //
6 | // Create Date: 2017/07/25 17:45:20
7 | // Design Name:
8 | // Module Name: sortx16_sim
9 | // Project Name:
10 | // Target Devices:
11 | // Tool Versions:
12 | // Description:
13 | //
14 | // Dependencies:
15 | //
16 | // Revision:
17 | // Revision 0.01 - File Created
18 | // Additional Comments:
19 | //
20 | //////////////////////////////////////////////////////////////////////////////////
21 |
22 |
23 | module sortx16_sim # (
24 | parameter DSIZE = 5,
25 | parameter OFFSET = 4
26 | )(
27 | output wire [DSIZE-1:0] sort0,
28 | output wire [DSIZE-1:0] sort1,
29 | output wire [DSIZE-1:0] sort2,
30 | output wire [DSIZE-1:0] sort3,
31 | output wire [DSIZE-1:0] sort4,
32 | output wire [DSIZE-1:0] sort5,
33 | output wire [DSIZE-1:0] sort6,
34 | output wire [DSIZE-1:0] sort7,
35 | output wire [DSIZE-1:0] sort8,
36 | output wire [DSIZE-1:0] sort9,
37 | output wire [DSIZE-1:0] sort10,
38 | output wire [DSIZE-1:0] sort11,
39 | output wire [DSIZE-1:0] sort12,
40 | output wire [DSIZE-1:0] sort13,
41 | output wire [DSIZE-1:0] sort14,
42 | output wire [DSIZE-1:0] sort15
43 | );
44 |
45 | SortX16 # (
46 | .DSIZE (DSIZE),
47 | .OFFSET(OFFSET)
48 | ) sortx16_inst(
49 | .a0 (5'd3),
50 | .a1 (5'd9),
51 | .a2 (5'd15),
52 | .a3 (5'd6),
53 | .a4 (5'd12),
54 | .a5 (5'd2),
55 | .a6 (5'd8),
56 | .a7 (5'd14),
57 | .a8 (5'd4),
58 | .a9 (5'd10),
59 | .a10 (5'd0),
60 | .a11 (5'd1),
61 | .a12 (5'd7),
62 | .a13 (5'd23),
63 | .a14 (5'd13),
64 | .a15 (5'd5),
65 | .sort0 (sort0),
66 | .sort1 (sort1),
67 | .sort2 (sort2),
68 | .sort3 (sort3),
69 | .sort4 (sort4),
70 | .sort5 (sort5),
71 | .sort6 (sort6),
72 | .sort7 (sort7),
73 | .sort8 (sort8),
74 | .sort9 (sort9),
75 | .sort10 (sort10),
76 | .sort11 (sort11),
77 | .sort12 (sort12),
78 | .sort13 (sort13),
79 | .sort14 (sort14),
80 | .sort15 (sort15)
81 | );
82 |
83 | endmodule
84 |
--------------------------------------------------------------------------------
/software model/HuffNode.cpp:
--------------------------------------------------------------------------------
1 | /*******************************************************************
2 | /* Description:
3 | /* high-level model of huffman coding, written in C.
4 | /* it is a static huffman coding
5 | /* input data: 0 - 9
6 | /* totally 256 times
7 | /* Author:
8 | /* Guozhu Xin
9 | /* Date:
10 | /* 2017/7/8
11 | /* Email contact:
12 | /* spikexin@outlook.com
13 | *********************************************************************/
14 | #include
15 | #include
16 | using namespace std;
17 |
18 | struct HuffNode{
19 | int Value; // 0 - 9
20 | int Freq; // appear times
21 | HuffNode* LeftNode;
22 | HuffNode* RightNode;
23 | };
24 | struct HuffNode node[50];
25 |
26 | void InitNode()
27 | {
28 | node[0] = {0,5,NULL,NULL};
29 | node[1] = {1,10,NULL,NULL};
30 | node[2] = {2,15,NULL,NULL};
31 | node[3] = {3,20,NULL,NULL};
32 | node[4] = {4,25,NULL,NULL};
33 | node[5] = {5,30,NULL,NULL};
34 | node[6] = {6,35,NULL,NULL};
35 | node[7] = {7,40,NULL,NULL};
36 | node[8] = {8,45,NULL,NULL};
37 | node[9] = {9,31,NULL,NULL};
38 | }
39 |
40 |
41 | void SwitchNode(HuffNode* a, HuffNode* b)
42 | {
43 | HuffNode temp;
44 | temp = *a;
45 | *a = *b;
46 | *b = temp;
47 | }
48 |
49 | void SortNode(int StartIdx, int len)
50 | {
51 | if(len > 1){
52 | for(int i = StartIdx+len-1; i > StartIdx; i--){
53 | for(int j = StartIdx; j < i; j++){
54 | if(node[j].Freq > node[j+1].Freq){
55 | SwitchNode(&node[j], &node[j+1]);
56 | }
57 | }
58 | }
59 | }
60 | }
61 |
62 | HuffNode GenTree()
63 | {
64 | int Len = 10;
65 | SortNode(0,Len);
66 | int StartIdx = 0,GenIdx = 10;
67 | while(Len > 1){
68 | Len --;
69 | StartIdx += 2;
70 | node[GenIdx++] = {-1,node[StartIdx-2].Freq+node[StartIdx-1].Freq,
71 | &node[StartIdx-2],&node[StartIdx-1]};
72 | SortNode(StartIdx,Len);
73 | }
74 | return node[StartIdx];
75 | }
76 |
77 | void Traverse(HuffNode* node_ptr, string str)
78 | {
79 | if(node_ptr->Value != -1){
80 | cout << node_ptr->Value << ": " << str << "\n";
81 | }
82 | else{
83 | str = str + '0';
84 | if(node_ptr->LeftNode){
85 | Traverse(node_ptr->LeftNode,str);
86 | }
87 | str[str.size()-1] = '1';
88 | if(node_ptr->RightNode){
89 | Traverse(node_ptr->RightNode,str);
90 | }
91 | }
92 | }
93 |
94 | int main()
95 | {
96 | HuffNode root;
97 | HuffNode* node_ptr;
98 | string str;
99 | InitNode();
100 | root = GenTree();
101 | node_ptr = &root;
102 | Traverse(node_ptr,str);
103 | return 0;
104 | }
105 |
--------------------------------------------------------------------------------