├── .gitignore ├── B-Bus.xlsx ├── CART.sv ├── CD ├── CD.qpf ├── CD.qsf ├── CD.sv ├── CD_tb.sv ├── RAM_tb.sv ├── SH1.sv ├── YGR019.sv ├── YGR019_PKG.sv ├── sh7034.mif ├── sh7034.txt ├── vsim.wlf └── wave.do ├── DCC.sv ├── FX68K ├── fx68k.qip ├── fx68k.sdc ├── fx68k.sv ├── fx68k.txt ├── fx68kAlu.sv ├── microrom.mem ├── nanorom.mem └── uaddrPla.sv ├── RAM.sv ├── SCSP ├── RAM_tb.sv ├── SCSP DSP.vsd ├── SCSP.qpf ├── SCSP.qsf ├── SCSP.sv ├── SCSP_pkg.sv ├── SCSP_tb.sv ├── sndram.txt └── wave.do ├── SCU ├── DSP.sv ├── DSP_PKG.sv ├── RAM.sv ├── SCU DSP.xlsx ├── SCU.qip ├── SCU.qpf ├── SCU.qsf ├── SCU.sv ├── SCU_PKG.sv ├── SCU_tb.sv ├── modelsim.ini ├── prg.txt ├── transcript ├── vsim.wlf └── wave.do ├── SMPC.sv ├── Saturn.qip ├── Saturn.qpf ├── Saturn.qsf ├── Saturn.sv ├── Saturn_tb.sv ├── VDP1 ├── RAM_tb.sv ├── VDP1.qpf ├── VDP1.qsf ├── VDP1.sv ├── VDP1_pkg.sv ├── VDP1_tb.sv ├── vram.bin ├── vram.txt └── wave.do ├── VDP2 ├── RAM_tb.sv ├── VDP2.qpf ├── VDP2.qsf ├── VDP2.sv ├── VDP2.xlsx ├── VDP2_MEM.sv ├── VDP2_pkg.sv ├── VDP2_tb.sv ├── vram_a0.txt ├── vram_a1.txt ├── vsim.wlf └── wave.do ├── bios.txt └── wave.do /.gitignore: -------------------------------------------------------------------------------- 1 | db 2 | greybox_tmp 3 | incremental_db 4 | output_files 5 | simulation 6 | hc_output 7 | scaler 8 | hps_isw_handoff 9 | vip 10 | verilog_libs 11 | work 12 | *_sim 13 | .qsys_edit 14 | PLLJ_PLLSPE_INFO.txt 15 | *.bak 16 | *.orig 17 | *.rej 18 | *.qdf 19 | *.rpt 20 | *.smsg 21 | *.summary 22 | *.done 23 | *.jdi 24 | *.pin 25 | *.sof 26 | *.qws 27 | *.ppf 28 | *.ddb 29 | build_id.v 30 | c5_pin_model_dump.txt 31 | *.sopcinfo 32 | *.csv 33 | *.f 34 | *.cmp 35 | *.sip 36 | *.spd 37 | *.bsf 38 | *~ 39 | *.xml 40 | *.cdf 41 | -------------------------------------------------------------------------------- /B-Bus.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/B-Bus.xlsx -------------------------------------------------------------------------------- /CART.sv: -------------------------------------------------------------------------------- 1 | module CART ( 2 | input CLK, 3 | input RST_N, 4 | 5 | input [2:0] MODE, //0-none, 1-ROM 2M, 2-DRAM 1M, 3-DRAM 4M 6 | 7 | input RES_N, 8 | 9 | input CE_R, 10 | input CE_F, 11 | input [25:0] AA, 12 | input [15:0] ADI, 13 | output [15:0] ADO, 14 | input [1:0] AFC, 15 | input ACS0_N, 16 | input ACS1_N, 17 | input ACS2_N, 18 | input ARD_N, 19 | input AWRL_N, 20 | input AWRU_N, 21 | input ATIM0_N, 22 | input ATIM2_N, 23 | output AWAIT_N, 24 | output ARQT_N, 25 | 26 | output [21:1] MEM_A, 27 | input [15:0] MEM_DI, 28 | output [15:0] MEM_DO, 29 | output [ 1:0] MEM_WE, 30 | output MEM_RD, 31 | input MEM_RDY 32 | ); 33 | 34 | wire DRAM1M_SEL = (AA[24:20] ==? 5'b001?0) && ~ACS0_N; 35 | wire [21:1] DRAM1M_ADDR = {2'b00,AA[21],AA[18:1]}; 36 | 37 | wire DRAM4M_SEL = (AA[24:20] ==? 5'b001??) && ~ACS0_N; 38 | wire [21:1] DRAM4M_ADDR = {AA[21:1]}; 39 | 40 | wire ROM2M_SEL = ~ACS0_N; 41 | wire [21:1] ROM2M_ADDR = {1'b0,AA[20:1]}; 42 | 43 | wire CART_ID_SEL = (AA[23:1] == 24'hFFFFFF>>1) && ~ACS1_N; 44 | wire CART_MEM_SEL = ~ACS0_N || ~ACS1_N; 45 | bit [15:0] ABUS_DO; 46 | bit ABUS_WAIT; 47 | always @(posedge CLK or negedge RST_N) begin 48 | bit AWR_N_OLD; 49 | bit ARD_N_OLD; 50 | 51 | if (!RST_N) begin 52 | ABUS_WAIT <= 0; 53 | end else begin 54 | if (!RES_N) begin 55 | 56 | end else begin 57 | AWR_N_OLD <= AWRL_N & AWRU_N; 58 | ARD_N_OLD <= ARD_N; 59 | 60 | if (CART_ID_SEL) begin 61 | if (!ARD_N && ARD_N_OLD) begin 62 | case (MODE) 63 | 3'h1: ABUS_DO <= 16'hFFFF; 64 | 3'h2: ABUS_DO <= 16'hFF5A; 65 | 3'h3: ABUS_DO <= 16'hFF5C; 66 | default: ABUS_DO <= 16'hFFFF; 67 | endcase 68 | end 69 | end 70 | else if (CART_MEM_SEL) begin 71 | if ((!AWRL_N || !AWRU_N) && AWR_N_OLD) begin 72 | case (MODE) 73 | 3'h2: MEM_A <= DRAM1M_ADDR; 74 | 3'h3: MEM_A <= DRAM4M_ADDR; 75 | default: MEM_A <= '1; 76 | endcase 77 | MEM_DO <= ADI; 78 | case (MODE) 79 | 3'h2, 80 | 3'h3: MEM_WE <= ~{AWRU_N,AWRL_N}; 81 | default: MEM_WE <= '0; 82 | endcase 83 | ABUS_WAIT <= (MODE == 3'h2 || MODE == 3'h3); 84 | end else if (!ARD_N && ARD_N_OLD) begin 85 | case (MODE) 86 | 3'h1: MEM_A <= ROM2M_ADDR; 87 | 3'h2: MEM_A <= DRAM1M_ADDR; 88 | 3'h3: MEM_A <= DRAM4M_ADDR; 89 | default: MEM_A <= '1; 90 | endcase 91 | MEM_RD <= 1; 92 | ABUS_WAIT <= 1; 93 | end 94 | end 95 | 96 | if (ABUS_WAIT && MEM_RDY) begin 97 | case (MODE) 98 | 3'h1, 99 | 3'h2, 100 | 3'h3: ABUS_DO <= MEM_DI; 101 | default: ABUS_DO <= 16'hFFFF; 102 | endcase 103 | MEM_WE <= '0; 104 | MEM_RD <= 0; 105 | ABUS_WAIT <= 0; 106 | end 107 | end 108 | end 109 | end 110 | 111 | assign ADO = ABUS_DO; 112 | assign AWAIT_N = ~ABUS_WAIT; 113 | assign ARQT_N = 1; 114 | 115 | endmodule 116 | -------------------------------------------------------------------------------- /CD/CD.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 20:33:38 March 10, 2021 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "20:33:38 March 10, 2021" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "CD" 31 | -------------------------------------------------------------------------------- /CD/CD.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 20:33:38 March 10, 2021 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # CD_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEMA6F31I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY CD 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:33:38 MARCH 10, 2021" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 50 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 51 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 52 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 53 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 54 | set_global_assignment -name QIP_FILE ../../SH2/SH7034/SH7034.qip 55 | set_global_assignment -name SYSTEMVERILOG_FILE SH1.sv 56 | set_global_assignment -name SYSTEMVERILOG_FILE YGR019.sv 57 | set_global_assignment -name VERILOG_FILE CDFIFO.v 58 | set_global_assignment -name SYSTEMVERILOG_FILE CD.sv 59 | set_global_assignment -name SYSTEMVERILOG_FILE RAM_tb.sv 60 | set_global_assignment -name SYSTEMVERILOG_FILE CD_tb.sv 61 | set_global_assignment -name SYSTEMVERILOG_FILE YGR019_PKG.sv 62 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /CD/CD.sv: -------------------------------------------------------------------------------- 1 | module CD 2 | #( 3 | parameter rom_file = "sh7034.mif" 4 | ) 5 | ( 6 | input CLK, 7 | input RST_N, 8 | input CE, 9 | 10 | input RES_N, 11 | 12 | input CE_R, 13 | input CE_F, 14 | input [14:1] AA, 15 | input [15:0] ADI, 16 | output [15:0] ADO, 17 | input [1:0] AFC, 18 | input ACS2_N, 19 | input ARD_N, 20 | input AWRL_N, 21 | input AWRU_N, 22 | input ATIM0_N, 23 | input ATIM2_N, 24 | output AWAIT_N, 25 | output ARQT_N, 26 | 27 | input CDATA, 28 | output HDATA, 29 | output COMCLK, 30 | input COMREQ_N, 31 | input COMSYNC_N, 32 | output DEMP, 33 | 34 | output [18:1] RAM_A, 35 | output [15:0] RAM_D, 36 | input [15:0] RAM_Q, 37 | output RAM_CS, 38 | output [1:0] RAM_WE, 39 | output RAM_RD, 40 | input RAM_RDY, 41 | 42 | input [15:0] CD_D, 43 | input CD_CK 44 | ); 45 | 46 | bit [21:0] SA; 47 | bit [15:0] SDI; 48 | bit [15:0] SDO; 49 | bit SWRL_N; 50 | bit SWRH_N; 51 | bit SRD_N; 52 | bit SCS1_N; 53 | bit SCS2_N; 54 | bit SCS6_N; 55 | bit SWAIT_N; 56 | bit DACK0; 57 | bit DACK1; 58 | bit DREQ0_N; 59 | bit DREQ1_N; 60 | bit SIRQL_N; 61 | bit SIRQH_N; 62 | 63 | bit [15:0] YGR019_DO; 64 | 65 | bit SHCLK; 66 | bit SHCE_R, SHCE_F; 67 | always @(posedge CLK) begin 68 | if (CE) SHCLK <= ~SHCLK; 69 | end 70 | assign SHCE_R = SHCLK & CE; 71 | assign SHCE_F = ~SHCLK & CE; 72 | 73 | SH1 #(rom_file) sh1 74 | ( 75 | .CLK(CLK), 76 | .RST_N(RST_N), 77 | .CE_R(SHCE_R), 78 | .CE_F(SHCE_F), 79 | 80 | .RES_N(RES_N), 81 | 82 | .A(SA), 83 | .DI(SDI), 84 | .DO(SDO), 85 | 86 | .CS1N_CASHN(SCS1_N),//in original CASH_N 87 | .CS2N(SCS2_N), 88 | .CS6N(SCS6_N), 89 | .WRLN(SWRL_N), 90 | .WRHN(SWRH_N), 91 | .RDN(SRD_N), 92 | .WAITN(SWAIT_N), 93 | 94 | .IRQ6N(SIRQL_N), 95 | .IRQ7N(SIRQH_N), 96 | 97 | .DACK0(DACK0), 98 | .DACK1(DACK1), 99 | .DREQ0N(DREQ0_N), 100 | .DREQ1N(DREQ1_N), 101 | 102 | .RXD0(CDATA), 103 | .TXD0(HDATA), 104 | .SCK0O(COMCLK), 105 | .PB2I(COMSYNC_N), 106 | .TIOCB3(COMREQ_N), 107 | .PB6O(DEMP), 108 | 109 | .TIOCA0(1'b0),//MPEG 110 | .TIOCA1(1'b0),//MPEG 111 | .TIOCA2(1'b1),//MPEGA_IRQ_N 112 | .TIOCB2(1'b1)//MPEGV_IRQ_N 113 | ); 114 | 115 | assign SDI = !SCS1_N ? RAM_Q : YGR019_DO; 116 | 117 | YGR019 ygr 118 | ( 119 | .CLK(CLK), 120 | .RST_N(RST_N), 121 | 122 | .RES_N(RES_N), 123 | 124 | .CE_R(CE_R), 125 | .CE_F(CE_F), 126 | .AA(AA), 127 | .ADI(ADI), 128 | .ADO(ADO), 129 | .AFC(AFC), 130 | .ACS2_N(ACS2_N), 131 | .ARD_N(ARD_N), 132 | .AWRL_N(AWRL_N), 133 | .AWRU_N(AWRU_N), 134 | .ATIM0_N(ATIM0_N), 135 | .ATIM2_N(ATIM2_N), 136 | .AWAIT_N(AWAIT_N), 137 | .ARQT_N(ARQT_N), 138 | 139 | .SHCE_R(SHCE_R), 140 | .SHCE_F(SHCE_F), 141 | .SA(SA[21:1]), 142 | .SDI(SDO), 143 | .BDI(SDI), 144 | .SDO(YGR019_DO), 145 | .SWRL_N(SWRL_N), 146 | .SWRH_N(SWRH_N), 147 | .SRD_N(SRD_N), 148 | .SCS2_N(SCS2_N), 149 | .SCS6_N(SCS6_N), 150 | .SIRQL_N(SIRQL_N), 151 | .SIRQH_N(SIRQH_N), 152 | 153 | .DACK0(DACK0), 154 | .DACK1(DACK1), 155 | .DREQ0_N(DREQ0_N), 156 | .DREQ1_N(DREQ1_N), 157 | 158 | .CD_D(CD_D), 159 | .CD_CK(CD_CK) 160 | ); 161 | 162 | assign SWAIT_N = RAM_RDY; 163 | 164 | assign RAM_A = SA[18:1]; 165 | assign RAM_D = SDO; 166 | assign RAM_CS = ~SCS1_N; 167 | assign RAM_WE = ~{SWRH_N,SWRL_N}; 168 | assign RAM_RD = ~SRD_N; 169 | 170 | 171 | endmodule 172 | -------------------------------------------------------------------------------- /CD/CD_tb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | module CD_tb; 4 | 5 | // import SCU_PKG::*; 6 | 7 | bit CLK; 8 | bit RST_N; 9 | bit RES_N; 10 | 11 | bit [18:1] RAM_A; 12 | bit [15:0] RAM_D; 13 | bit [15:0] RAM_Q; 14 | bit [1:0] RAM_WE; 15 | bit RAM_RD; 16 | bit RAM_CS; 17 | 18 | 19 | //clock generation 20 | always #5 CLK = ~CLK; 21 | 22 | //reset generation 23 | initial begin 24 | RST_N = 0; 25 | #12 RST_N = 1; 26 | 27 | RES_N = 0; 28 | #5 RES_N = 1; 29 | end 30 | 31 | CD #("sh7034.txt") cd 32 | ( 33 | .CLK(CLK), 34 | .RST_N(RST_N), 35 | .CE(1'b1), 36 | 37 | .RES_N(RES_N), 38 | 39 | .CE_R(1'b0), 40 | .CE_F(1'b0), 41 | .AA('0), 42 | .ADI('0), 43 | .ADO(), 44 | .AFC('0), 45 | .ACS2_N(1'b1), 46 | .ARD_N(1'b1), 47 | .AWRL_N(1'b1), 48 | .AWRU_N(1'b1), 49 | .ATIM0_N(1'b1), 50 | .ATIM2_N(1'b1), 51 | .AWAIT_N(), 52 | .ARQT_N(), 53 | 54 | .CDATA(1'b1), 55 | .HDATA(), 56 | .COMCLK(), 57 | .COMREQ_N(1'b1), 58 | .COMSYNC_N(1'b1), 59 | 60 | .RAM_A(RAM_A), 61 | .RAM_D(RAM_D), 62 | .RAM_Q(RAM_Q), 63 | .RAM_CS(RAM_CS), 64 | .RAM_WE(RAM_WE), 65 | .RAM_RD(RAM_RD), 66 | 67 | .CD_D('0), 68 | .CD_CK(0) 69 | ); 70 | 71 | RAM_tb #(18,16,"") dram(CLK, RAM_A, RAM_D, RAM_CS, RAM_WE, RAM_Q); 72 | 73 | 74 | endmodule 75 | -------------------------------------------------------------------------------- /CD/RAM_tb.sv: -------------------------------------------------------------------------------- 1 | module RAM_tb 2 | #( 3 | parameter addr_width = 8, 4 | parameter data_width = 8, 5 | parameter mem_sim_file = "" 6 | ) 7 | ( 8 | input CLK, 9 | 10 | input [addr_width-1:0] ADDR, 11 | input [data_width-1:0] DATA, 12 | input CS, 13 | input [data_width/8-1:0] WREN, 14 | output [data_width-1:0] Q 15 | ); 16 | 17 | // synopsys translate_off 18 | `define SIM 19 | // synopsys translate_on 20 | 21 | `ifdef SIM 22 | 23 | reg [data_width-1:0] MEM [2**addr_width]; 24 | 25 | initial begin 26 | MEM = '{2**addr_width{'0}}; 27 | $readmemh(mem_sim_file, MEM); 28 | end 29 | 30 | always @(posedge CLK) begin 31 | bit [data_width-1:0] temp; 32 | 33 | if (data_width > 0) temp[ 7: 0] = WREN[0] ? DATA[ 7: 0] : Q[ 7: 0]; 34 | if (data_width > 8) temp[15: 8] = WREN[1] ? DATA[15: 8] : Q[15: 8]; 35 | if (data_width > 16) temp[23:16] = WREN[2] ? DATA[23:16] : Q[23:16]; 36 | if (data_width > 24) temp[31:24] = WREN[3] ? DATA[31:24] : Q[31:24]; 37 | 38 | if (WREN && CS) begin 39 | MEM[ADDR] <= temp; 40 | end 41 | end 42 | 43 | assign Q = MEM[ADDR]; 44 | 45 | `else 46 | 47 | 48 | 49 | `endif 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /CD/SH1.sv: -------------------------------------------------------------------------------- 1 | module SH1 2 | #( 3 | parameter rom_file = " " 4 | ) 5 | ( 6 | input CLK, 7 | input RST_N, 8 | input CE_R, 9 | input CE_F, 10 | input EN, 11 | 12 | input RES_N, 13 | 14 | output [21:0] A, 15 | input [15:0] DI, 16 | output [15:0] DO, 17 | 18 | //PA in 19 | input TIOCA0, 20 | input TIOCA1, 21 | input DREQ0N, 22 | input DREQ1N, 23 | //PA out 24 | output RASN, 25 | output CS6N, 26 | output WRLN, 27 | output WRHN, 28 | output RDN, 29 | output DACK0, 30 | output DACK1, 31 | 32 | //PB in 33 | input TIOCA2, 34 | input TIOCB2, 35 | input PB2I, 36 | input TIOCB3, 37 | input RXD0, 38 | input IRQ6N, 39 | input IRQ7N, 40 | //PB out 41 | output PB6O, 42 | output TXD0, 43 | output SCK0O, 44 | 45 | output CS1N_CASHN, 46 | output CS2N, 47 | output CASLN, 48 | input WAITN 49 | ); 50 | 51 | SH7034 #(rom_file) sh7034 52 | ( 53 | .CLK(CLK), 54 | .RST_N(RST_N), 55 | .CE_R(CE_R), 56 | .CE_F(CE_F), 57 | .EN(EN), 58 | 59 | .RES_N(RES_N), 60 | .NMI_N(1'b1), 61 | 62 | .A(A), 63 | .DI(DI), 64 | .DO(DO), 65 | 66 | .PA0I_TIOCA0(TIOCA0), 67 | .PA1I(1'b0), 68 | .PA2I_TIOCB0(1'b0), 69 | .PA3I_WAITN(WAITN), 70 | .PA4I(1'b0), 71 | .PA5I(1'b0), 72 | .PA6I(1'b0), 73 | .PA7I(1'b0), 74 | .PA8I_BREQN(1'b0), 75 | .PA9I_ADTRGN(1'b0), 76 | .PA10I_DPL_TIOCA1(TIOCA1), 77 | .PA11I_DPH_TIOCB1(1'b0), 78 | .PA12I_IRQ0N_TCLKA(1'b0), 79 | .PA13I_IRQ1N_TCLKB_DREQ0N(DREQ0N), 80 | .PA14I_IRQ2N(1'b0), 81 | .PA15I_IRQ3N_DREQ1N(DREQ1N), 82 | 83 | .PB0I_TIOCA2(TIOCA2), 84 | .PB1I_TIOCB2(TIOCB2), 85 | .PB2I_TIOCA3(PB2I), 86 | .PB3I_TIOCB3(TIOCB3), 87 | .PB4I_TIOCA4(1'b0), 88 | .PB5I_TIOCB4(1'b0), 89 | .PB6I_TCLKC(1'b0), 90 | .PB7I_TCLKD(1'b0), 91 | .PB8I_RXD0(RXD0), 92 | .PB9I(1'b0), 93 | .PB10I_RXD1(1'b1), 94 | .PB11I(1'b0), 95 | .PB12I_IRQ4N_SCK0I(1'b0), 96 | .PB13I_IRQ5N_SCK1I(1'b0), 97 | .PB14I_IRQ6N(IRQ6N), 98 | .PB15I_IRQ7N(IRQ7N), 99 | 100 | .PC0I(1'b0), 101 | .PC1I(1'b0), 102 | .PC2I(1'b0), 103 | .PC3I(1'b0), 104 | .PC4I(1'b0), 105 | .PC5I(1'b0), 106 | .PC6I(1'b0), 107 | .PC7I(1'b0), 108 | 109 | .PA0O_CS4N_TIOCA0(), 110 | .PA1O_CS5N_RASN(RASN), 111 | .PA2O_CS6N_TIOCB0(CS6N), 112 | .PA3O_CS7N(), 113 | .PA4O_WRLN(WRLN), 114 | .PA5O_WRHN(WRHN), 115 | .PA6O_RDN(RDN), 116 | .PA7O_BACKN(), 117 | .PA8O(), 118 | .PA9O_AHN_IRQOUTN(), 119 | .PA10O_DPL_TIOCA1(), 120 | .PA11O_DPH_TIOCB1(), 121 | .PA12O_DACK0(DACK0), 122 | .PA13O(), 123 | .PA14O_DACK1(DACK1), 124 | .PA15O(), 125 | 126 | .PB0O_TIOCA2_TP0(), 127 | .PB1O_TIOCB2_TP1(), 128 | .PB2O_TIOCA3_TP2(), 129 | .PB3O_TIOCB3_TP3(), 130 | .PB4O_TIOCA4_TP4(), 131 | .PB5O_TIOCB4_TP5(), 132 | .PB6O_TOCXA4_TP6(PB6O), 133 | .PB7O_TOCXB4_TP7(), 134 | .PB8O_TP8(), 135 | .PB9O_TXD0_TP9(TXD0), 136 | .PB10O_TP10(), 137 | .PB11O_TXD1_TP11(), 138 | .PB12O_SCK0O_TP12(SCK0O), 139 | .PB13O_SCK1O_TP13(), 140 | .PB14O_TP14(), 141 | .PB15O_TP15(), 142 | 143 | .CS0N(), 144 | .CS1N_CASHN(CS1N_CASHN), 145 | .CS2N(CS2N), 146 | .CS3N_CASLN(CASLN), 147 | 148 | .WDTOVF_N(), 149 | 150 | .MD(3'b010) 151 | ); 152 | 153 | 154 | endmodule 155 | -------------------------------------------------------------------------------- /CD/YGR019.sv: -------------------------------------------------------------------------------- 1 | module YGR019 ( 2 | input CLK, 3 | input RST_N, 4 | 5 | input RES_N, 6 | 7 | input CE_R, 8 | input CE_F, 9 | input [14:1] AA, 10 | input [15:0] ADI, 11 | output [15:0] ADO, 12 | input [1:0] AFC, 13 | input ACS2_N, 14 | input ARD_N, 15 | input AWRL_N, 16 | input AWRU_N, 17 | input ATIM0_N, 18 | input ATIM2_N, 19 | output AWAIT_N, 20 | output ARQT_N, 21 | 22 | input SHCE_R, 23 | input SHCE_F, 24 | input [21:1] SA, 25 | input [15:0] SDI, 26 | input [15:0] BDI, 27 | output [15:0] SDO, 28 | input SWRL_N, 29 | input SWRH_N, 30 | input SRD_N, 31 | input SCS2_N, 32 | input SCS6_N, 33 | input DACK0, 34 | input DACK1, 35 | output DREQ0_N, 36 | output DREQ1_N, 37 | output reg SIRQL_N, 38 | output reg SIRQH_N, 39 | 40 | input [15:0] CD_D, 41 | input CD_CK, 42 | input CD_AUDIO, 43 | 44 | output [15:0] CD_SL, 45 | output [15:0] CD_SR 46 | 47 | `ifdef DEBUG 48 | , 49 | output [31:0] DBG_HEADER, 50 | // output [7:0] DBG_CNT, 51 | // output [7:0] FIFO_CNT_DBG, 52 | output [15:0] ABUS_READ_CNT_DBG, 53 | output [7:0] ABUS_WAIT_CNT_DBG, 54 | output reg HOOK, 55 | output reg HOOK2, 56 | output [11:0] DBG_CDD_CNT 57 | `endif 58 | ); 59 | import YGR019_PKG::*; 60 | 61 | CR_t CR[4]; 62 | CR_t RR[4]; 63 | bit [15:0] HIRQ; 64 | bit [15:0] HMASK; 65 | bit [15:0] DTR; 66 | bit [15:0] TRCTL; 67 | bit [ 7:0] CDIRQL; 68 | bit [ 7:0] CDIRQU; 69 | bit [ 7:0] CDMASKU; 70 | bit [ 7:0] CDMASKL; 71 | bit [15:0] REG1A; 72 | //bit [15:0] REG1C; 73 | 74 | bit [15:0] FIFO_BUF[8]; 75 | bit [2:0] FIFO_WR_POS; 76 | bit [2:0] FIFO_RD_POS; 77 | bit [2:0] FIFO_AMOUNT; 78 | bit FIFO_EMPTY; 79 | bit FIFO_FULL; 80 | bit FIFO_DREQ; 81 | bit [1:0] CDD_DREQ; 82 | bit [15:0] CDD_DATA; 83 | bit [15:0] HOST_DATA; 84 | 85 | wire SCU_REG_SEL = (AA[14:12] == 3'b000) & ~ACS2_N; 86 | wire SH_REG_SEL = (SA[21:20] == 2'b00) & ~SCS2_N; 87 | wire SH_MPEG_SEL = (SA[21:20] == 2'b01) & ~SCS2_N; 88 | wire ABUS_WAIT_EN = SCU_REG_SEL && AA[5:2] == 4'b0000; 89 | bit [15:0] SCU_REG_DO; 90 | bit ABUS_WAIT; 91 | bit [15:0] SH_REG_DO; 92 | always @(posedge CLK or negedge RST_N) begin 93 | bit AWR_N_OLD; 94 | bit ARD_N_OLD; 95 | bit SWR_N_OLD; 96 | bit SRD_N_OLD; 97 | bit DACK0_OLD; 98 | bit DACK1_OLD; 99 | bit [ 1:0] ABUS_WAIT_CNT; 100 | bit FIFO_INC_AMOUNT; 101 | bit FIFO_DEC_AMOUNT; 102 | bit FIFO_DREQ_PEND; 103 | bit TRCTL1_OLD,TRCTL2_OLD; 104 | bit CDD_SYNCED; 105 | bit [11:0] CDD_CNT; 106 | bit CDD_PEND; 107 | bit CDDA_CHAN; 108 | 109 | if (!RST_N) begin 110 | CR <= '{4{'0}}; 111 | RR <= '{4{'0}}; 112 | HIRQ <= '0; 113 | HMASK <= '0; 114 | 115 | CDIRQL <= '0; 116 | CDMASKL <= '0; 117 | REG1A <= '0; 118 | //REG1C <= '0; 119 | 120 | CDIRQU <= '0; 121 | CDMASKU <= '0; 122 | 123 | SH_REG_DO <= '0; 124 | ABUS_WAIT <= 0; 125 | ABUS_WAIT_CNT <= '0; 126 | 127 | TRCTL <= '0; 128 | FIFO_BUF <= '{8{'0}}; 129 | FIFO_WR_POS <= '0; 130 | FIFO_RD_POS <= '0; 131 | FIFO_AMOUNT <= '0; 132 | FIFO_EMPTY <= 1; 133 | FIFO_FULL <= 0; 134 | FIFO_DREQ_PEND <= 0; 135 | FIFO_DREQ <= 0; 136 | 137 | CDD_DREQ <= '0; 138 | CDD_SYNCED <= 0; 139 | CDD_CNT <= 4'd0; 140 | CDD_PEND <= 0; 141 | CDDA_CHAN <= 0; 142 | 143 | `ifdef DEBUG 144 | HOOK <= 0; 145 | `endif 146 | end else begin 147 | if (!RES_N) begin 148 | 149 | end else begin 150 | if (CE_R) begin 151 | AWR_N_OLD <= AWRL_N & AWRU_N; 152 | ARD_N_OLD <= ARD_N; 153 | end 154 | if (CE_F) begin 155 | if (ABUS_WAIT_CNT) ABUS_WAIT_CNT <= ABUS_WAIT_CNT - 2'd1; 156 | end 157 | 158 | `ifdef DEBUG 159 | if (ABUS_WAIT_CNT_DBG < 8'hF0 && CE_R) ABUS_WAIT_CNT_DBG <= ABUS_WAIT_CNT_DBG + 8'd1; 160 | `endif 161 | if (SCU_REG_SEL) begin 162 | if ((!AWRL_N || !AWRU_N) && AWR_N_OLD && CE_R) begin 163 | case ({AA[5:2],2'b00}) 164 | 6'h00: begin 165 | ABUS_WAIT <= 1; 166 | ABUS_WAIT_CNT <= 2'd2; 167 | `ifdef DEBUG 168 | ABUS_WAIT_CNT_DBG <= '0; 169 | `endif 170 | end 171 | 6'h08: begin 172 | for (int i=0; i<16; i++) if (!ADI[i]) HIRQ[i] <= 0; 173 | end 174 | 6'h0C: HMASK <= ADI; 175 | 6'h18: CR[0] <= ADI; 176 | 6'h1C: CR[1] <= ADI; 177 | 6'h20: CR[2] <= ADI; 178 | 6'h24: begin CR[3] <= ADI; if (!CDIRQL[0]) CDIRQL[0] <= 1; CDIRQL[1] <= 0; end 179 | default:; 180 | endcase 181 | 182 | `ifdef DEBUG 183 | case ({AA[5:2],2'b00}) 184 | 6'h08: begin 185 | end 186 | 6'h24: begin 187 | if (CR[0] == 16'h1081 && CR[1] == 16'hAE58) HOOK <= 1; 188 | end 189 | default:; 190 | endcase 191 | `endif 192 | end else if (!ARD_N && ARD_N_OLD && CE_F) begin 193 | case ({AA[5:2],2'b00}) 194 | 6'h00: begin 195 | ABUS_WAIT <= 1; 196 | ABUS_WAIT_CNT <= 2'd2; 197 | `ifdef DEBUG 198 | ABUS_WAIT_CNT_DBG <= '0; 199 | ABUS_READ_CNT_DBG <= ABUS_READ_CNT_DBG + 1'd1; 200 | `endif 201 | end 202 | 6'h08: SCU_REG_DO <= HIRQ; 203 | 6'h0C: SCU_REG_DO <= HMASK; 204 | 6'h18: SCU_REG_DO <= RR[0]; 205 | 6'h1C: SCU_REG_DO <= RR[1]; 206 | 6'h20: SCU_REG_DO <= RR[2]; 207 | 6'h24: begin 208 | SCU_REG_DO <= RR[3]; 209 | if (!CDIRQL[1]) CDIRQL[1] <= 1; 210 | end 211 | default: SCU_REG_DO <= '0; 212 | endcase 213 | end 214 | end 215 | 216 | if (CE_F) begin 217 | if (ABUS_WAIT && !ABUS_WAIT_CNT && !TRCTL[0] && (!FIFO_EMPTY || TRCTL[3])) begin 218 | SCU_REG_DO <= FIFO_BUF[FIFO_RD_POS]; 219 | FIFO_RD_POS <= FIFO_RD_POS + 3'd1; 220 | FIFO_DEC_AMOUNT <= 1; 221 | if (FIFO_AMOUNT <= 7'd1) begin 222 | FIFO_DREQ_PEND <= 1; 223 | end 224 | ABUS_WAIT <= 0; 225 | `ifdef DEBUG 226 | ABUS_WAIT_CNT_DBG <= 8'hFF; 227 | `endif 228 | end 229 | if (ABUS_WAIT && !ABUS_WAIT_CNT && TRCTL[0] && !FIFO_FULL) begin 230 | FIFO_BUF[FIFO_WR_POS] <= ADI; 231 | FIFO_WR_POS <= FIFO_WR_POS + 3'd1; 232 | FIFO_INC_AMOUNT <= 1; 233 | if (FIFO_AMOUNT >= 7'd5) begin 234 | FIFO_DREQ_PEND <= 1; 235 | end 236 | ABUS_WAIT <= 0; 237 | `ifdef DEBUG 238 | ABUS_WAIT_CNT_DBG <= 8'hFF; 239 | `endif 240 | end 241 | end 242 | 243 | if (SHCE_R) begin 244 | SWR_N_OLD <= SWRL_N & SWRH_N; 245 | SRD_N_OLD <= SRD_N; 246 | if (SH_REG_SEL) begin 247 | if ((!SWRL_N || !SWRH_N) && SWR_N_OLD) begin 248 | case ({SA[4:1],1'b0}) 249 | 5'h00: begin 250 | if (TRCTL[2] && !TRCTL[0]) begin 251 | FIFO_BUF[FIFO_WR_POS] <= SDI; 252 | FIFO_WR_POS <= FIFO_WR_POS + 3'd1; 253 | FIFO_INC_AMOUNT <= 1; 254 | end 255 | end 256 | 5'h02: begin 257 | TRCTL <= SDI & TRCTL_WMASK; 258 | if (SDI[2] && !SDI[0]) FIFO_DREQ_PEND <= 1; 259 | if (SDI[1]) begin 260 | FIFO_WR_POS <= '0; 261 | FIFO_RD_POS <= '0; 262 | FIFO_AMOUNT <= '0; 263 | FIFO_FULL <= 0; 264 | FIFO_EMPTY <= 1; 265 | FIFO_DREQ <= 0; 266 | end 267 | end 268 | 5'h04: for (int i=0; i<8; i++) if (!SDI[i] && CDIRQL[i]) CDIRQL[i] <= 0; 269 | 5'h06: for (int i=0; i<8; i++) if (!SDI[i] && CDIRQU[i]) CDIRQU[i] <= 0; 270 | 5'h08: CDMASKL <= SDI[7:0] & CDMASKL_WMASK[7:0]; 271 | 5'h0A: CDMASKU <= SDI[7:0] & CDMASKU_WMASK[7:0]; 272 | 5'h10: RR[0] <= SDI; 273 | 5'h12: RR[1] <= SDI; 274 | 5'h14: RR[2] <= SDI; 275 | 5'h16: RR[3] <= SDI; 276 | 5'h1A: REG1A <= SDI & REG1A_WMASK; 277 | // 5'h1C: REG1C <= SDI; 278 | 5'h1E: begin 279 | for (int i=0; i<16; i++) if (SDI[i]) HIRQ[i] <= 1; 280 | `ifdef DEBUG 281 | if (CR[0] == 16'h5100 && RR[3] == 16'h00C8 && SDI[0]) HOOK2 <= HOOK; 282 | `endif 283 | end 284 | default:; 285 | endcase 286 | end else if (!SRD_N && SRD_N_OLD) begin 287 | case ({SA[4:1],1'b0}) 288 | 5'h00: begin 289 | SH_REG_DO <= FIFO_BUF[FIFO_RD_POS]; 290 | FIFO_RD_POS <= FIFO_RD_POS + 3'd1; 291 | FIFO_DEC_AMOUNT <= 1; 292 | if (FIFO_RD_POS[1:0] == 2'd3) begin 293 | FIFO_DREQ_PEND <= 1; 294 | end 295 | end 296 | 5'h02: SH_REG_DO <= TRCTL & TRCTL_RMASK; 297 | 5'h04: SH_REG_DO <= {8'h00,CDIRQL} & CDIRQL_RMASK; 298 | 5'h06: SH_REG_DO <= {8'h00,CDIRQU} & CDIRQU_RMASK; 299 | 5'h08: SH_REG_DO <= {8'h00,CDMASKL} & CDMASKL_RMASK; 300 | 5'h0A: SH_REG_DO <= {8'h00,CDMASKU} & CDMASKU_RMASK; 301 | 5'h10: SH_REG_DO <= CR[0]; 302 | 5'h12: SH_REG_DO <= CR[1]; 303 | 5'h14: SH_REG_DO <= CR[2]; 304 | 5'h16: SH_REG_DO <= CR[3]; 305 | 5'h1A: SH_REG_DO <= REG1A & REG1A_RMASK; 306 | 5'h1C: SH_REG_DO <= 16'h0016;//REG1C; 307 | default: SH_REG_DO <= '0; 308 | endcase 309 | end 310 | end else if (SH_MPEG_SEL) begin 311 | if (!SRD_N && SRD_N_OLD) begin 312 | case ({SA[4:1],1'b0}) 313 | 5'h02: SH_REG_DO <= 16'h006C; 314 | default: SH_REG_DO <= '0; 315 | endcase 316 | end 317 | end 318 | end 319 | 320 | //DREQ1 321 | if (SHCE_R) begin 322 | // if (FIFO_CNT_DBG < 8'h80) FIFO_CNT_DBG <= FIFO_CNT_DBG + 8'd1; 323 | 324 | if (FIFO_DREQ_PEND) begin 325 | FIFO_DREQ_PEND <= 0; 326 | FIFO_DREQ <= 1; 327 | // FIFO_CNT_DBG <= '0; 328 | end 329 | 330 | DACK1_OLD <= DACK1; 331 | if (TRCTL[2] && DACK1 && !DACK1_OLD) begin 332 | if (!TRCTL[0]) begin 333 | FIFO_BUF[FIFO_WR_POS] <= BDI; 334 | FIFO_WR_POS <= FIFO_WR_POS + 3'd1; 335 | FIFO_INC_AMOUNT <= 1; 336 | if (FIFO_AMOUNT > 7'd2 && FIFO_DREQ) begin 337 | FIFO_DREQ <= 0; 338 | // FIFO_CNT_DBG <= 8'hFF; 339 | end 340 | end else begin 341 | HOST_DATA <= FIFO_BUF[FIFO_RD_POS]; 342 | FIFO_RD_POS <= FIFO_RD_POS + 3'd1; 343 | FIFO_DEC_AMOUNT <= 1; 344 | if (FIFO_AMOUNT < 7'd5 && FIFO_DREQ) begin 345 | FIFO_DREQ <= 0; 346 | // FIFO_CNT_DBG <= 8'hFF; 347 | end 348 | end 349 | end 350 | end 351 | HOST_DATA <= FIFO_BUF[FIFO_RD_POS]; 352 | 353 | if (FIFO_INC_AMOUNT && FIFO_DEC_AMOUNT) begin 354 | FIFO_INC_AMOUNT <= 0; 355 | FIFO_DEC_AMOUNT <= 0; 356 | end else if (FIFO_INC_AMOUNT) begin 357 | FIFO_AMOUNT <= FIFO_AMOUNT + 3'd1; 358 | if (FIFO_AMOUNT == 3'd7) FIFO_AMOUNT <= 3'd7; 359 | if (FIFO_AMOUNT == 3'd6) FIFO_FULL <= 1; 360 | FIFO_EMPTY <= 0; 361 | FIFO_INC_AMOUNT <= 0; 362 | end else if (FIFO_DEC_AMOUNT) begin 363 | FIFO_AMOUNT <= FIFO_AMOUNT - 3'd1; 364 | if (FIFO_AMOUNT == 3'd0) FIFO_AMOUNT <= 3'd0; 365 | FIFO_FULL <= 0; 366 | if (FIFO_AMOUNT == 3'd1) FIFO_EMPTY <= 1; 367 | FIFO_DEC_AMOUNT <= 0; 368 | end 369 | 370 | //DREQ0 371 | if (CD_CK) begin 372 | if (!CD_AUDIO) begin 373 | CDD_CNT <= CDD_CNT + 12'd2; 374 | if (!CDD_SYNCED) begin 375 | if (CDD_CNT == 12'd10) begin 376 | CDD_SYNCED <= 1; 377 | REG1A[7] <= 1; 378 | end 379 | end else if (CDD_CNT == 12'd12) begin 380 | `ifdef DEBUG 381 | DBG_HEADER[31:16] <= {CD_D[7:0],CD_D[15:8]}; 382 | `endif 383 | end else if (CDD_CNT == 12'd14) begin 384 | if (!CDIRQU[4]) CDIRQU[4] <= 1; 385 | `ifdef DEBUG 386 | DBG_HEADER[15:0] <= {CD_D[7:0],CD_D[15:8]}; 387 | `endif 388 | end else if (CDD_CNT == 12'd2352-2) begin 389 | CDD_SYNCED <= 0; 390 | CDD_CNT <= 12'd0; 391 | end 392 | CDD_DATA <= {CD_D[7:0],CD_D[15:8]}; 393 | CDD_PEND <= CDD_SYNCED; 394 | 395 | CD_SL <= '0; 396 | CD_SR <= '0; 397 | 398 | end else begin 399 | CDDA_CHAN <= ~CDDA_CHAN; 400 | if (!CDDA_CHAN) CD_SL <= CD_D[15:0]; 401 | if ( CDDA_CHAN) CD_SR <= CD_D[15:0]; 402 | end 403 | end 404 | `ifdef DEBUG 405 | DBG_CDD_CNT <= CDD_CNT; 406 | `endif 407 | 408 | if (SHCE_R) begin 409 | // if (DBG_CNT < 8'h80) DBG_CNT <= DBG_CNT + 8'd1; 410 | 411 | if (CDD_PEND) begin 412 | CDD_DREQ[0] <= REG1A[7]; 413 | CDD_PEND <= 0; 414 | // if (REG1A[7]) DBG_CNT <= '0; 415 | end else if (CDD_DREQ[0]) begin 416 | CDD_DREQ[0] <= 0; 417 | end 418 | CDD_DREQ[1] <= CDD_DREQ[0]; 419 | 420 | DACK0_OLD <= DACK0; 421 | if (DACK0 && !DACK0_OLD) begin 422 | // DBG_CNT <= 8'hFF; 423 | end 424 | end 425 | end 426 | end 427 | end 428 | 429 | assign ADO = SCU_REG_DO; 430 | assign AWAIT_N = ~(ABUS_WAIT & ABUS_WAIT_EN); 431 | assign ARQT_N = 1;//TODO 432 | 433 | assign SDO = !DACK0 ? CDD_DATA : 434 | !DACK1 ? HOST_DATA : SH_REG_DO; 435 | 436 | assign SIRQL_N = ~|(CDIRQL & CDMASKL); 437 | assign SIRQH_N = ~|(CDIRQU & CDMASKU); 438 | assign DREQ0_N = ~|CDD_DREQ; 439 | assign DREQ1_N = ~FIFO_DREQ; 440 | 441 | 442 | endmodule 443 | -------------------------------------------------------------------------------- /CD/YGR019_PKG.sv: -------------------------------------------------------------------------------- 1 | package YGR019_PKG; 2 | 3 | typedef bit [15:0] DATATRNS_t; //R/W;258XXX00,258XXX02 4 | parameter bit [15:0] DATATRNS_WMASK = 16'hFFFF; 5 | parameter bit [15:0] DATATRNS_RMASK = 16'hFFFF; 6 | parameter bit [15:0] DATATRNS_INIT = 16'hFFFF; 7 | 8 | typedef struct packed //R;258XXX04,258XXX06 9 | { 10 | bit [12: 0] UNUSED; 11 | bit DIR; //R 12 | bit FUL; //R 13 | bit EMP; //R 14 | } DATASTAT_t; 15 | parameter bit [15:0] DATASTAT_WMASK = 16'h0007; 16 | parameter bit [15:0] DATASTAT_RMASK = 16'h0007; 17 | parameter bit [15:0] DATASTAT_INIT = 16'h0000; 18 | 19 | typedef struct packed //R/W;258XXX08,258XXX0A 20 | { 21 | bit [ 1: 0] UNUSED; 22 | bit MPST; //R/W0 23 | bit MPCM; //R/W0 24 | bit MPED; //R/W0 25 | bit SCDQ; //R/W0 26 | bit EFLS; //R/W0 27 | bit ECPY; //R/W0 28 | bit EHST; //R/W0 29 | bit ESEL; //R/W0 30 | bit DCHG; //R/W0 31 | bit PEND; //R/W0 32 | bit BFUL; //R/W0 33 | bit CSCT; //R/W0 34 | bit DRDY; //R/W0 35 | bit CMOK; //R/W0 36 | } HIRQREQ_t; 37 | parameter bit [15:0] HIRQREQ_WMASK = 16'h3FFF; 38 | parameter bit [15:0] HIRQREQ_RMASK = 16'h3FFF; 39 | parameter bit [15:0] HIRQREQ_INIT = 16'h0000; 40 | 41 | typedef struct packed //R/W;258XXX0C,258XXX0E 42 | { 43 | bit [ 1: 0] UNUSED; 44 | bit MPST; //R/W 45 | bit MPCM; //R/W 46 | bit MPED; //R/W 47 | bit SCDQ; //R/W 48 | bit EFLS; //R/W 49 | bit ECPY; //R/W 50 | bit EHST; //R/W 51 | bit ESEL; //R/W 52 | bit DCHG; //R/W 53 | bit PEND; //R/W 54 | bit BFUL; //R/W 55 | bit CSCT; //R/W 56 | bit DRDY; //R/W 57 | bit CMOK; //R/W 58 | } HIRQMSK_t; 59 | parameter bit [15:0] HIRQMSK_WMASK = 16'h3FFF; 60 | parameter bit [15:0] HIRQMSK_RMASK = 16'h3FFF; 61 | parameter bit [15:0] HIRQMSK_INIT = 16'hFFFF; 62 | 63 | typedef bit [15:0] CR_t; //R/W;258XXX18-258XXX26 64 | parameter bit [15:0] CR_WMASK = 16'hFFFF; 65 | parameter bit [15:0] CR_RMASK = 16'hFFFF; 66 | parameter bit [15:0] CR_INIT = 16'h0000; 67 | 68 | typedef bit [15:0] MPEGRGB_t; //R;258XXX28,258XXX2A 69 | parameter bit [15:0] MPEGRGB_WMASK = 16'hFFFF; 70 | parameter bit [15:0] MPEGRGB_RMASK = 16'hFFFF; 71 | parameter bit [15:0] MPEGRGB_INIT = 16'h0000; 72 | 73 | typedef bit [15:0] TRCTL_t; //R/W;0A000002 74 | parameter bit [15:0] TRCTL_WMASK = 16'h000F; 75 | parameter bit [15:0] TRCTL_RMASK = 16'h000F; 76 | parameter bit [15:0] TRCTL_INIT = 16'h0000; 77 | 78 | typedef bit [15:0] CDIRQL_t; //R/W;0A000004 79 | parameter bit [15:0] CDIRQL_WMASK = 16'h0003; 80 | parameter bit [15:0] CDIRQL_RMASK = 16'h0003; 81 | parameter bit [15:0] CDIRQL_INIT = 16'h0000; 82 | 83 | typedef bit [15:0] CDIRQU_t; //R/W;0A000006 84 | parameter bit [15:0] CDIRQU_WMASK = 16'h0070; 85 | parameter bit [15:0] CDIRQU_RMASK = 16'h0070; 86 | parameter bit [15:0] CDIRQU_INIT = 16'h0000; 87 | 88 | typedef bit [15:0] CDMASKL_t; //R/W;0A000008 89 | parameter bit [15:0] CDMASKL_WMASK = 16'h0003; 90 | parameter bit [15:0] CDMASKL_RMASK = 16'h0003; 91 | parameter bit [15:0] CDMASKL_INIT = 16'h0000; 92 | 93 | typedef bit [15:0] CDMASKU_t; //R/W;0A00000A 94 | parameter bit [15:0] CDMASKU_WMASK = 16'h0070; 95 | parameter bit [15:0] CDMASKU_RMASK = 16'h0070; 96 | parameter bit [15:0] CDMASKU_INIT = 16'h0000; 97 | 98 | typedef bit [15:0] REG1A_t; //R/W;0A00001A 99 | parameter bit [15:0] REG1A_WMASK = 16'h00FF; 100 | parameter bit [15:0] REG1A_RMASK = 16'h00FF; 101 | parameter bit [15:0] REG1A_INIT = 16'h0000; 102 | 103 | endpackage 104 | -------------------------------------------------------------------------------- /CD/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/CD/vsim.wlf -------------------------------------------------------------------------------- /CD/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /CD_tb/cd/sh1/CLK 4 | add wave -noupdate /CD_tb/cd/sh1/CE_F 5 | add wave -noupdate /CD_tb/cd/sh1/CE_R 6 | add wave -noupdate /CD_tb/cd/sh1/A 7 | add wave -noupdate /CD_tb/cd/sh1/DI 8 | add wave -noupdate /CD_tb/cd/sh1/DO 9 | add wave -noupdate /CD_tb/cd/sh1/RDN 10 | add wave -noupdate /CD_tb/cd/sh1/WRLN 11 | add wave -noupdate /CD_tb/cd/sh1/WRHN 12 | add wave -noupdate /CD_tb/cd/sh1/CS1N_CASHN 13 | add wave -noupdate /CD_tb/cd/sh1/CS2N 14 | add wave -noupdate /CD_tb/cd/sh1/CS6N 15 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_A 16 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_DI 17 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_DO 18 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_WR 19 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_BA 20 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_REQ 21 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/BUS_WAIT 22 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/STATE 23 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/PIPE.ID 24 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/PIPE.EX 25 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/PIPE.MA 26 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/PIPE.WB 27 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/ALU_A 28 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/ALU_B 29 | add wave -noupdate /CD_tb/cd/sh1/sh7034/core/ALU_RES 30 | add wave -noupdate /CD_tb/cd/sh1/sh7034/bsc/BUS_STATE 31 | add wave -noupdate /CD_tb/cd/sh1/sh7034/bsc/WAIT_N 32 | add wave -noupdate /CD_tb/cd/sh1/sh7034/bsc/NEXT_BA 33 | add wave -noupdate /CD_tb/cd/sh1/sh7034/bsc/BUSY 34 | add wave -noupdate {/CD_tb/cd/sh1/sh7034/core/regfile/GR[0]} 35 | add wave -noupdate /CD_tb/cd/ygr/SH_REG_SEL 36 | add wave -noupdate /CD_tb/cd/ygr/SA 37 | add wave -noupdate /CD_tb/cd/ygr/SDI 38 | add wave -noupdate /CD_tb/cd/ygr/FIFO_BUF 39 | add wave -noupdate /CD_tb/cd/ygr/FIFO_WR_POS 40 | add wave -noupdate /CD_tb/cd/ygr/FIFO_RD_POS 41 | add wave -noupdate /CD_tb/cd/ygr/FIFO_AMOUNT 42 | add wave -noupdate /CD_tb/cd/ygr/FIFO_DREQ 43 | add wave -noupdate /CD_tb/cd/ygr/DACK1 44 | add wave -noupdate /CD_tb/cd/ygr/BDI 45 | add wave -noupdate /CD_tb/cd/sh1/sh7034/dmac/DMA_RD 46 | add wave -noupdate {/CD_tb/cd/sh1/sh7034/dmac/TCR[1]} 47 | add wave -noupdate /CD_tb/cd/sh1/sh7034/dmac/DBUS_WAIT 48 | TreeUpdate [SetDefaultTree] 49 | WaveRestoreCursors {{Cursor 1} {2995730998 ps} 0} 50 | quietly wave cursor active 1 51 | configure wave -namecolwidth 150 52 | configure wave -valuecolwidth 100 53 | configure wave -justifyvalue left 54 | configure wave -signalnamewidth 0 55 | configure wave -snapdistance 10 56 | configure wave -datasetprefix 0 57 | configure wave -rowmargin 4 58 | configure wave -childrowmargin 2 59 | configure wave -gridoffset 0 60 | configure wave -gridperiod 1 61 | configure wave -griddelta 40 62 | configure wave -timeline 0 63 | configure wave -timelineunits us 64 | update 65 | WaveRestoreZoom {2995578451 ps} {2995834451 ps} 66 | -------------------------------------------------------------------------------- /DCC.sv: -------------------------------------------------------------------------------- 1 | module DCC ( 2 | input CLK, 3 | input RST_N, 4 | input CE_R, 5 | input CE_F, 6 | 7 | input RES_N, 8 | 9 | input [24:1] A, 10 | input BS_N, 11 | input CS0_N, 12 | input CS1_N, 13 | input CS2_N, 14 | input RD_WR_N, 15 | input [1:0] WE_N, 16 | input RD_N, 17 | output WAIT_N, 18 | 19 | output BRLS_N, 20 | input BGR_N, 21 | input BREQ_N, 22 | output BACK_N, 23 | input EXBREQ_N, 24 | output EXBACK_N, 25 | 26 | input WTIN_N, 27 | input IVECF_N, 28 | 29 | input HINT_N, 30 | input VINT_N, 31 | output [2:1] IREQ_N, 32 | 33 | output reg MFTI, 34 | output reg SFTI, 35 | 36 | output DCE_N, 37 | output DOE_N, 38 | output [1:0] DWE_N, 39 | 40 | output ROMCE_N, 41 | output SRAMCE_N, 42 | output SMPCCE_N, 43 | output MOE_N, 44 | output MWR_N 45 | ); 46 | 47 | //SCU bus arbitration 48 | bit SSH_ACTIVE; 49 | bit SCU_ACTIVE; 50 | always @(posedge CLK or negedge RST_N) begin 51 | if (!RST_N) begin 52 | SSH_ACTIVE <= '0; 53 | SCU_ACTIVE <= 0; 54 | end else if (CE_R) begin 55 | if (!BREQ_N && !SSH_ACTIVE && !SCU_ACTIVE) SSH_ACTIVE <= 1; 56 | else if (BREQ_N && SSH_ACTIVE) SSH_ACTIVE <= 0; 57 | 58 | if (!EXBREQ_N && BREQ_N && !SCU_ACTIVE && !SSH_ACTIVE) SCU_ACTIVE <= 1; 59 | else if (EXBREQ_N && SCU_ACTIVE) SCU_ACTIVE <= 0; 60 | end 61 | end 62 | assign BRLS_N = (BREQ_N | ~SSH_ACTIVE) & (EXBREQ_N | ~SCU_ACTIVE); 63 | assign BACK_N = BGR_N | ~SSH_ACTIVE; 64 | assign EXBACK_N = BGR_N | ~SCU_ACTIVE; 65 | 66 | //ROM (BIOS) 67 | assign ROMCE_N = ~(A[24:20] == 5'b00000) | CS0_N; 68 | //SMPC 69 | assign SMPCCE_N = ~(A[24:19] == 6'b000010) | CS0_N; 70 | //SRAM (backup) 71 | assign SRAMCE_N = ~(A[24:19] == 6'b000011) | CS0_N; 72 | 73 | assign MOE_N = RD_N; 74 | assign MWR_N = WE_N[0]; 75 | 76 | //DRAM (LWRAM) 77 | assign DCE_N = ~(A[24:21] == 4'b0001) | CS0_N; 78 | assign DOE_N = RD_N; 79 | assign DWE_N = WE_N; 80 | bit DRAM_WAIT; 81 | always @(posedge CLK or negedge RST_N) begin 82 | bit RD_N_OLD; 83 | bit WE_N_OLD; 84 | bit [ 2: 0] DRAM_WAIT_CNT; 85 | 86 | if (!RST_N) begin 87 | DRAM_WAIT <= 0; 88 | DRAM_WAIT_CNT <= '0; 89 | end else begin 90 | RD_N_OLD <= RD_N; 91 | WE_N_OLD <= |WE_N; 92 | if ((!RD_N && RD_N_OLD && !DCE_N) || (!WE_N && WE_N_OLD && !DCE_N)) begin 93 | DRAM_WAIT <= 1; 94 | DRAM_WAIT_CNT <= 3'd5; 95 | end else if (!DRAM_WAIT_CNT && CE_F) begin 96 | DRAM_WAIT <= 0; 97 | end 98 | 99 | if (DRAM_WAIT_CNT && CE_R) DRAM_WAIT_CNT <= DRAM_WAIT_CNT - 3'd1; 100 | end 101 | end 102 | 103 | //MINIT/SINIT 104 | wire MINIT_SEL = (A[24:23] == 2'b10) & ~CS0_N; 105 | wire SINIT_SEL = (A[24:23] == 2'b11) & ~CS0_N; 106 | always @(posedge CLK or negedge RST_N) begin 107 | bit WE_N_OLD; 108 | 109 | if (!RST_N) begin 110 | MFTI = 1; 111 | SFTI = 1; 112 | end else if (!RES_N) begin 113 | MFTI = 1; 114 | SFTI = 1; 115 | end else if (CE_R) begin 116 | MFTI = 1; 117 | SFTI = 1; 118 | 119 | WE_N_OLD <= &WE_N; 120 | if (!(&WE_N) && WE_N_OLD) begin 121 | if (SINIT_SEL) MFTI <= 0; 122 | if (MINIT_SEL) SFTI <= 0; 123 | end 124 | end 125 | end 126 | 127 | assign WAIT_N = WTIN_N & ~DRAM_WAIT; 128 | 129 | assign IREQ_N = {VINT_N,VINT_N&HINT_N}; 130 | 131 | endmodule 132 | -------------------------------------------------------------------------------- /FX68K/fx68k.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fx68k.sv ] 2 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) fx68kAlu.sv ] 3 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) uaddrPla.sv ] 4 | set_global_assignment -name SDC_FILE [file join $::quartus(qip_path) fx68k.sdc ] -------------------------------------------------------------------------------- /FX68K/fx68k.sdc: -------------------------------------------------------------------------------- 1 | set_multicycle_path -start -setup -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|microAddr[*]] 2 2 | set_multicycle_path -start -hold -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|microAddr[*]] 1 3 | set_multicycle_path -start -setup -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|nanoAddr[*]] 2 4 | set_multicycle_path -start -hold -from [get_keepers *fx68k:*|Ir[*]] -to [get_keepers *fx68k:*|nanoAddr[*]] 1 5 | 6 | set_multicycle_path -start -setup -from {*|nanoLatch[*]} -to {*|excUnit|alu|pswCcr[*]} 2 7 | set_multicycle_path -start -hold -from {*|nanoLatch[*]} -to {*|excUnit|alu|pswCcr[*]} 1 8 | set_multicycle_path -start -setup -from {*|excUnit|alu|oper[*]} -to {*|excUnit|alu|pswCcr[*]} 2 9 | set_multicycle_path -start -hold -from {*|excUnit|alu|oper[*]} -to {*|excUnit|alu|pswCcr[*]} 1 -------------------------------------------------------------------------------- /FX68K/fx68k.txt: -------------------------------------------------------------------------------- 1 | FX68K 2 | 3 | 68000 cycle accurate core 4 | Copyright (c) 2018 by Jorge Cwik 5 | fx68k@fxatari.com 6 | 7 | 8 | FX68K is a 68K cycle exact compatible core. In theory at least, it should be impossible to distinguish functionally from a real 68K processor. 9 | 10 | On Cyclone families it uses just over 5,100 LEs and about 5KB internal ram, reaching a max clock frequency close to 40MHz. Some optimizations are still possible to implement and increase the performance. 11 | 12 | The core is fully synchronous. Considerable effort was done to avoid any asynchronous logic. 13 | 14 | Written in SystemVerilog. 15 | 16 | The timing of the external bus signals is exactly as the original processor. The only feature that is not implemented yet is bus retry using the external HALT input signal. 17 | 18 | It was designed to replace an actual chip on a real board. This wasn't yet tested however and not all necessary output enable control signals are fully implemented. 19 | 20 | 21 | Copyright 22 | 23 | // 24 | // This source file is free software; you can redistribute it and/or modify 25 | // it under the terms of the GNU General Public License as published by 26 | // the Free Software Foundation; either version 3 of the License, or 27 | // (at your option) any later version. 28 | // 29 | // This source file is distributed in the hope that it will be useful, 30 | // but WITHOUT ANY WARRANTY; without even the implied warranty of 31 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 32 | // GNU General Public License for more details. 33 | // 34 | // You should have received a copy of the GNU General Public License 35 | // along with this program. If not, see . 36 | // 37 | 38 | 39 | Developer Notes 40 | 41 | 42 | The core receives a clock that must be at least twice the frequency of the desired nominal speed. The core also receives two signals for masking both phases of the clock (PHI1 and PHI2). These signals are implemented as simple clock enable for all the flip flops used by the core. This way, the original clock frequency can be any multiple and it doesn't even need to be regular or constant. 43 | 44 | These two signals are enPhi1 and enPhi2. They must be a single cycle pulse, and they don't need to be registered. Because they are actually used as clock enable, the output signals change one cycle later. 45 | 46 | enPhi1 should be asserted one cycle before the high phase of the nominal clock, and enPhi2 one cycle before the low phase. 47 | 48 | E.g., during a bus cycle, AS is asserted one cycle after enPhi1 is asserted, and AS is deasserted one cycle after enPhi2 is asserted. This follows the original bus timing that specify AS being asserted on the raising edge of the clock, and deasserted on the falling edge one. 49 | 50 | All signals follow the original polarity and then most are low active. 51 | 52 | extReset is external reset and is synchronous and high active. Hence is doesn't have to be registered. 53 | 54 | pwrUp qualifies external reset as being a cold power up reset. If it is asserted, then extReset must be asserted as well. Most system don't need to distinguish between a cold and a warm reset at the CPU level. Then both signals can be always asserted together. The core does expect pwrUp to be asserted initially because there is no true asynchronous reset. The signal is high active. 55 | 56 | 57 | Timing analysis 58 | 59 | Microcode access is one of the slowest paths on the core. But the microcode output is not needed immediately. Use the following constraints to get a more accurate timing analysis. Note that the full path might need to be modified: 60 | 61 | # Altera/Intel 62 | 63 | set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 2 64 | set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|microAddr[*]] 1 65 | set_multicycle_path -start -setup -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 2 66 | set_multicycle_path -start -hold -from [get_keepers fx68k:fx68k|Ir[*]] -to [get_keepers fx68k:fx68k|nanoAddr[*]] 1 67 | 68 | # For Xilinx Vivado 69 | 70 | set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 2 71 | set_multicycle_path -setup -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 2 72 | set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/nanoAddr_reg*/D] 1 73 | set_multicycle_path -hold -from [get_pins fx68k/Ir*/C] -to [get_pins fx68k/microAddr_reg*/D] 1 74 | 75 | 76 | The update of the CCR flags is also time critical. Some compilers might benefit with the following constraints, but this wasn't fully verified yet: 77 | 78 | 79 | # Altera/Intel 80 | # set_multicycle_path -start -setup -from [fx68k:fx68k|nanoLatch[*]] 81 | # -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2 82 | # set_multicycle_path -start -setup -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]] 83 | # -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 2 84 | # set_multicycle_path -start -hold -from [fx68k:fx68k|nanoLatch[*]] 85 | # -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1 86 | # set_multicycle_path -start -hold -from [fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|oper[*]] 87 | # -to [get_keepers fx68k:fx68k|excUnit:excUnit|fx68kAlu:alu|pswCcr[*]] 1 -------------------------------------------------------------------------------- /FX68K/nanorom.mem: -------------------------------------------------------------------------------- 1 | 00000000000000000000000000000000000000000000000010000000000000000000 2 | 00000000000000000000000000000000000000000000000010000000000000000000 3 | 00000000000000000000000000000000000000000000000010000000000000000000 4 | 00000000000000000000000000001000000110011100000000000000101001000001 5 | 00100001000000011000010001001000000110100000000001000000011001001001 6 | 00000001100000000010100000001000000110000000001001000000001001001001 7 | 00100000000000011000010001000000000101000000000010000000100001010000 8 | 11000001000000000000000000001000000100010000000001000000000001010001 9 | 00100001000000011000010000000000000000000000000101000000000000010000 10 | 01000001011000000000100000000110010001000000001100000000110100011000 11 | 01000001011000000000100000000110010001000000001100000001100100011000 12 | 00100001000000011000010000000000000100000000000001000000000001010000 13 | 10100100001000011000001000010000101001110000000001000100110010100001 14 | 01000000000000000000000010000000010100000000001000110001000000000000 15 | 00100001000000011000000000110010100100011111010001100000000001000000 16 | 00100010000000011000000000000000100010000100000000010100000100000011 17 | 00000001011000000000000001000110000000000000000010000000000100000000 18 | 00000000000000000000000000001000000100000000000001000000000001010001 19 | 00000001100000000010100000001000000110000000001001010000001001001001 20 | 00101000000000001000010000000000000000000000000010000000000000000000 21 | 01100010000000011000010010000000010100000000001000110001000000000000 22 | 00000000000000000000000010010010100000000000000100110010000000000000 23 | 00100000000000011000010001001000000110000000001001010000001001001001 24 | 00000000000000000000001000000000100100000000000000110010000001011000 25 | 00010010000000000100100000001000000100000000000010000000000001010001 26 | 00100010000000011100000000000000000001100000000010001000100000000000 27 | 00010010000000000100000000000000010001100000000010000000000000000000 28 | 00000000000000000000000000011001100110100000010001000000011011010001 29 | 10100010110000000000000000000000100000010000010010000100000100000000 30 | 10000000000000000000000000001000000100010000000001000000000001000001 31 | 00100000000000011001000000011010000110000000001001000000001001001001 32 | 00010011000000000000101000010000001001000000010101000000100000110000 33 | 00000001000000000001010000000000000000000000000101100000000000010000 34 | 00100010000000011000001000001000100110000000000001000000000001010001 35 | 00000001000000000010100001010000001001000000010110000000100000110000 36 | 01000001000000000000000000000000000001101010001100000000110000000000 37 | 00110100000000000100000100000000000000000000000010000000000000000000 38 | 00000000000100100000100000000000010000000000000000000001000000011000 39 | 01110101000000000100100000100010000001100000000000000000110100001010 40 | 00100010000000011010000100000000100010000100000000010100000100000011 41 | 11000001000000000000000000001000000100010000000001000000000001010001 42 | 01010011000000000100100000100010000001100000000000000000110100001010 43 | 11000001000000000000000000001001100110110000000001000000011011000001 44 | 01001001110000000000001000001000001000000000000101000000000000100001 45 | 00000000000000000000100000100010010000000000000000110001000100000010 46 | 00010000110000000001010000000000000000011100000010000000000000011000 47 | 01010001110000000001000000011010100100000000000001000000000001000001 48 | 00000000000000000000000001000000000100000000001100010000000001010000 49 | 00001000000000011001001000001000000110100000000001000100000011010001 50 | 01010001110000000001010000001000001000000000000101000000000000110001 51 | 10100010110100100100000001000000000001110000000010000000110000010000 52 | 00000000000100000000000000000010100001001010000101100000100000010000 53 | 00010000110000000001000000000000100000000000010010000100000100000000 54 | 10000000000000000000000000001000000100010000000001000000000001000001 55 | 00000001000000000000000001000000001001000000000101000000100000100000 56 | 00010010000000000000100000001010101000000000000101000000000000110001 57 | 10100000000100111000000000100001100010111010000101100000011010010010 58 | 00100000000000011000000000110010100110000000010000100000001101000010 59 | 00010010000000001100000000000000000000000000000010000000000000000000 60 | 11000001000000000000001000011101100100010000000001000000000001000001 61 | 00010100000000000100000100000000000000000000000010000000000000000000 62 | 10100010110000000100001000000000100000010000010010000100000010000000 63 | 00100000000100111000000000000000100000010010000101000100000100010010 64 | 00100010000000011000000000000000100010000100000000010100000100000011 65 | 00100010100000011001010000010000100100000000001110000100001000000000 66 | 00000000000100000000000000000010100000001010000101000000000000010000 67 | 00100010100000011001000000010010100100000000001110000100001000000000 68 | 00000001000000000000010000000000100000000000010101000100000010010000 69 | 00000000000100100000000000100010000000000100000000110001000100011010 70 | 00100000000000011000000000010000100110000000011000100000001001000000 71 | 00000000000100100000100000100010010000000000000000110001000100011010 72 | 00000000011000000000000000000110000000000000001110000000110100111000 73 | 00011000000000011001001000001000000100000000000001000000000001010001 74 | 00100010000000011100000000000000000001100000000010001000100000000000 75 | 00110000100000001000000100000000100000000000000010000100000100000000 76 | 00000000000100000000000000000010100001000000000101100000100000010000 77 | 10100010110000000100001000010001100000010000000010000000000000000000 78 | 01000001000000000000000000000000000000000000000101000000000000010000 79 | 10000000000000000000000000001000000100010000000001000000000001000001 80 | 00000000000000000000000000001000001000000000000101000000000000110001 81 | 00001000110000000000001000000000000000000000000010000000000000000000 82 | 00010010000000001100000000000000000000000000000010000000000000000000 83 | 00010000000000001010000100000000110001000000000010000100011000000000 84 | 01010001000000011000001000000000000001100000000000000000110000000000 85 | 00001100000000011000001000100001000010100000000101110000000000000011 86 | 01000000000000000000000010000000010100000000001000110000000001000000 87 | 11000001000000000000000000001000001000010000000101000000000000100001 88 | 00000000000000000000000000001000000100011100000001100000000001000001 89 | 00000000000000000000000000000000000000000000000101100000000000000000 90 | 00000000000100000000000000000000100000000000000101000100000100010000 91 | 11101011000000000000000000000000000000010000000010000000000000000000 92 | 01100001000000011001000000011010100100000000000001000000000001000001 93 | 01100010000000011000010010000000010100000000001000110000000001000000 94 | 00000000000000000000000010010010100000000000010100110000000100000000 95 | 01000001000000000000010000011001101000000000000101000100001000110001 96 | 00100000000100111100000000000000000010000010000100100010001000010000 97 | 00010010000000000000000000000010110100000000001110000000000000011000 98 | 00000000000000000000001000010000100100000000011100110010000001011000 99 | 00000000000100000000000000010000111000000000010101000100011000110000 100 | 00000000011000000010100000000110000100000000001101110000000101000000 101 | 00000000000000000000000000000000000000000000000010000000000000000000 102 | 00000001000000000000000000000000010101001010001101000000100001010000 103 | 00000001000000000000010000000000100000000000000101000100001000010000 104 | 01110101000000010000001000000000000001100000000000000000110000000000 105 | 01000001000000000000000010000000010100001010001000110001000000000000 106 | 00100010000000011000000000011010101010000000010101000000001100110001 107 | 00100001000000011000010001010000000100000000010000010000000001010000 108 | 01000001000000000000010000000000100000000110000101000000000000010000 109 | 01000001000000000000000010000000010100001010001000110001000000000000 110 | 00100000000000011000010001010001000000000000011010000000000010001000 111 | 00000001000000000000000001010000000100000000010001110000000001000000 112 | 00010010000000001000000000011010101000000000000101000000000000110001 113 | 00000000000000000000000000001000001000000000000101000000000000110001 114 | 00010010000000000001100000000010000000000000000101100000000000000000 115 | 00010010000000000001000000000010000100000000000101100000000000000000 116 | 00100010000000011100000000001000001000000000000101000000000000100001 117 | 00000001000000000001010000000000001010100000000110000000011000101000 118 | 00000001100000000000100000000000000000000000000101000000000000010000 119 | 00010010000000000000101000001001000100000000001001000000000011010001 120 | 11110101001000000100000000000000000000010000000010000000000000000000 121 | 00000000000000000000010000001001101000000000000101000010000010110001 122 | 00000000000000000000010000000000100000000110000101100000000000000000 123 | 00100010100000001001100000000010000010000100001000000000001000001000 124 | 00100010100000001001000000000010000110000100001000000000001000001000 125 | 00010010000000001000010000000000000000000000001110000000000000011000 126 | 00110100000100101100000000000000000001100000000001100000110000010000 127 | 01110101000000001000000100000000111000000000010010000100000100000000 128 | 01000000000000000000010000010000100110000000011100100000000001011000 129 | 11010011000000000000101000001001000100010000001001000000000011010001 130 | 11110101001000000000000000000000100000010000000010000100000100000000 131 | 01110101000000000100000000000000010000000000010010001000000001000000 132 | 01110101000000000000000000000000110000000000010010001100000101000000 133 | 01110101000000000000000000000000110000000000010010001100011001000000 134 | 01110000000000011100000000000000000001100000001101000000110000000000 135 | 00010000000000001000000000000010100000000000000010000000000000000000 136 | 00010010000000000100000100000000010001000000000010000000000000000000 137 | 01000000000000000000010000010000100110000000011100100010001001011000 138 | 00100000000000011000010000000000000100000000000000100000000001000000 139 | 00000001000000000000000000000000001000000000000101000000000000110000 140 | 00100001000000011100000001011001000110000000011000000000001011001001 141 | 01100001000000011000000000010010100110000000011100100000001101011000 142 | 01100001000000011000010000010010000010000000010101000000001100010000 143 | 00000000000000000000000100000000010010100000001100110001011000011000 144 | 01100001000000011000000000010000100110000000011000100000001001000000 145 | 00000000000000000000000000001000000100011100000001100000000001000001 146 | 00010010000000000000000000010010110110000000001110000010001000011000 147 | 01000001000000000000100000010010010000000000010000110001000100011000 148 | 00010010000000000000010000010000110110000000001110000010001000011000 149 | 01000001000000000000000010000000010100001010001000110000000001000000 150 | 01000001000000000000010000001000101000000110000101000000000000110001 151 | 00000001000000000000010000000000100000000000000101000100001000010000 152 | 00101000000000001000010000000000000000000000000010000000000000000000 153 | 00100010000000011000000000000000100000000000000010000100011000000000 154 | 00100010001000011010000000000000100000000000000010000100000100000000 155 | 11010011001000000100000000010000011000010000000010000000000000000000 156 | 00010010000000000100000000000000010000000000010010001000000001000000 157 | 00001000000000011000001000000000000000000000000101110000000000000011 158 | 00100010110000000000010000001000001000000000000101000000000000110001 159 | 00100010000000011000000000000000100010100000000010000000000000000000 160 | 00100000000000011000000000110001100100011111011001100000000011000010 161 | 00100000000000011000000000001000100110000000001001010000001001000001 162 | 01000001000000000000000000010000000100000000011100100000000001011000 163 | 00000000100000000010100000000000000001000000000101000000100000010000 164 | 00000001000000000000000000011001000100000000011001000000000011000001 165 | 00000000011000000010100001000110000101000000000000010000100101010000 166 | 00100001000000011100000001011001000100000000011001000000000011000001 167 | 01000000000000000000000000000000000101001010001101100000100001000000 168 | 00000000000100000000000000000000100001001010000101100100100100010000 169 | 00000000011000000000000000000010110110000000001100000000001101011000 170 | 01000001000000000000000000000001111001100000001010000000110010100000 171 | 00110010000000011000000000010010100010000000001110000010001000011000 172 | 11000001000000000000000000011001100110110000010001000000011011000001 173 | 00100000000000011010000000100001110000001100001010000000000010000010 174 | 00000000000000000000000000010000000100010101010001100000000001000000 175 | 01000000000000000000000000000000000010100000000010000000011000001000 176 | 00000001000000000000000000000000000001101010001101000000110000010000 177 | 10000000000000000000001000001101100100010000000001000000000001000001 178 | 01110101000000000000000000000000110000000000000010001100000101000000 179 | 11000001000000000000000000001000000100010000000001000000000001000001 180 | 00100010000000011000000000001001101000000010000101000010000010110001 181 | 00100010000100011000000000010010100000000000000101000000000000010000 182 | 11100101000000011100000000001001000100010000001001000000000011010001 183 | 00100100000100111000000000000000100000000000010101100100000100010000 184 | 00100010000100011000000000011010100100000000000000000000000001011001 185 | 00100000000000001000001000000000100000000000000010000100000010000000 186 | 00100010000000011100001000001000100100000000000001000100001001010001 187 | 00010010000000000100000100000000010001000000000010000000000000000000 188 | 10000000000000000000001000011101000100010000000001000000000001000001 189 | 00011000000000011000001000000000100010000000000010000000000000000000 190 | 01000000000000000000000000000000000100000000000001000000000001010000 191 | 01000000000000000000010000010000100110000000011100100000011001001000 192 | 00000000001000000010001000010001010000000000000010001000000000100000 193 | 11100101000000011100000000001000001000010000000101000000000000110001 194 | 01000001000000000000001000010001100000000000000010000000000000000000 195 | 00110100000000000000000000000000110000000000000010001100000101000000 196 | 10000000000000000000001000001000100100010000010001000100000011000001 197 | 01110101000000000100001000000001110000000000010010001000000001000000 198 | 10000000000000000000001000001000100100010000000001000100000011000001 199 | 00110100000000000000000000000000110000000000010010001100000101000000 200 | 00110100000000000000000000000000110000000000010010001100011001000000 201 | 01000000000000000000000000010000000110100000011100100000011001001000 202 | 00000000000100000000000000010000111000000000010101000100000100110010 203 | 00000000000100000000000000100010100001100000000001000000110000011000 204 | 01000000000000000000000000010010000110000000010000100000001101001000 205 | 00000000000000000000000000001000000110000000001001000000001001001001 206 | 01000000000000000000010000000001100000000000000101000010000010010000 207 | 01000000000000000000000000001000000110000000001001010000001001000001 208 | 00000001000000000000000000000000000001101010001101000000110000000000 209 | 11100101000000011000000000010000111001110000010010000100110100100000 210 | 00000000000000000000000000011010101010000000000101000010001000110001 211 | 11000001000000000000001000001101100100010000000001000000000001000001 212 | 00000000000000000000000100000000010000000000000001100001000000000000 213 | 00000000000000000000000000001001100100000000001001000000000011010001 214 | 11000001000000000000010000010001100000010000010010000000011010000000 215 | 00000000000000000000000000000000000000010110000010000000000000000000 216 | 00000000000000000000000000000000000000001100000000000001000000000000 217 | 00100010000000011000000000000000100010100000000010000000000000000000 218 | 00001000000000011000001000000000000000000000000101110000000000000011 219 | 10000000000000000000000000000000000000010000000010000000000000000000 220 | 00000000000000000000010000000000100010000000000010000010001000000000 221 | 00101000000000001000001000000000000000000000000010000000000000000000 222 | 01010011000000000000100000000010100001100000001100000000110000011000 223 | 00000001000010000000000001000000000000000000000101000000000000010000 224 | 00100010000000011000010000001101101000000000000101000000000000110001 225 | 00000000000000000000100000010010010000000000010000110001000100000000 226 | 01000000000000000000000000010000000100000000011100100000000001000000 227 | 00000000000000000000000100010010010000000000010000110001000100000000 228 | 01000000000000000000100000000000010000000000000001000000110000010000 229 | 01010011000000001000010000000000000001100000001100000000110000011000 230 | 01000001000000000000010000001001101000000000000101000000000000110001 231 | 00100100000100011001000000000000100000000000010101000100000100010000 232 | 01100010000000011000100000010010110010000000001100000000110000011000 233 | 00011000000000011000001000000000000000000000000101110000000000000011 234 | 00000000000000000000000000001000000100000000000001000000000001010001 235 | 00010010000000000100000100000000010001000000000010000000000000000000 236 | 00001010000000011000001000000000000000000000000101110000000000000011 237 | 00010010000000000000000000000001110100000010001110000010000010011000 238 | 01100010000000011000100000010010110010000000001100000001000000011000 239 | 01000000000000000000100000000010010000000000001100110001000100011000 240 | 00100010000100011000000001011010100100000000000001000000000001011001 241 | 00000001000000000000010000000001100001001010000101000000100000010000 242 | 00000000000000000000010000000000100101000110001110000000100001011000 243 | 00000000000000000000100000010010010000000000010000110001000100011000 244 | 01010011000000000000100000000001100001100010001100000010110010011000 245 | 01100011000000011000000000010010100100000000011101110000000001011000 246 | 00000000000100000001000000010000100100000000011101000100000101010000 247 | 00100010000100011000000001010010100100000000011100010000000001010000 248 | 00000001000000000000010000000000100000000001000101000100000010010000 249 | 00000001000000000000010000000001100000001111000101000000000000010000 250 | 00000000000000000000000000010010100000000110010101100000000100000000 251 | 00000111000000000000010000010000111000001000010110000100001000100000 252 | 01000000000000000000100000000001110000000000001001000000110010010000 253 | 01001011000000011000001000000000000001100000000000000000110000000000 254 | 00000000000000000000010000000000100010000000000101000000000000010000 255 | 10100100000000011100000000001000000100010000000001000000000001000001 256 | 00010000000000000000000000010000100100000010000010000000000000000000 257 | 00000000000000000000000000001000000100000010000000110010000001000001 258 | 01000000000000000000000000001001100100000000001001010000000011000001 259 | 00000000000000000000000000001001100100000000001001010000000011000001 260 | 00100000000000011000000000010010100010000000010101000000001100010000 261 | 00000000000100000000000000000000101000000000000101000100011000110000 262 | 00000000000100100000100000010010010000000000010000110001000100011000 263 | 01000000000000000000010000010001100000000000010101000010000010010000 264 | 00100001000000011100010100000000110010000000001110001000100000011000 265 | 00000000000000000000001000000000100000000110000101000000000000000000 266 | 00000110000000000000000000000000000000001000000010000000000000000000 267 | 01000000000000000000010000000000100100001010001100110010000001000000 268 | 01000000000000000000000000000000000100001010001100000000000001000000 269 | 01100001000000011000000000000000100001100010000000000000110000000000 270 | 01000001000000000000010000000000100000000110000101010000000000010000 271 | 00101000000000001000010000001000101010000000000101100000000000100001 272 | 10000110000000000000000000001000001000001000000101100000000000100001 273 | 00000000000000000000000000001000000100000000000001000000000001010001 274 | 00100010000100111000100000000000110010100000000001000000110000010000 275 | 00100100000100111100000000001000000100000000000001000000000001011001 276 | 00100011000000011000010100000000010000000000001110001000100000011000 277 | 00000000000000000000000000011001100110100000010001000000011011010001 278 | 00000000000000000000000000000000000000000000000010000000000000000000 279 | 00000000000100100000010001001000100100000000000001000000011001001001 280 | 00100100001000111100001000000000100010000000000101000000000000010000 281 | 01000001000000000000000000010001100000000010000010000000000000000000 282 | 00100010000000011010000000000000110100000000011110001100100100011000 283 | 11100101000000011100000100000000001000010000010101000000011010000000 284 | 00010000000000000000100000000000100001100010001100000000110000000000 285 | 00100010000100111000010001001000000100000000000000000000000001011001 286 | 00010000000000000010000000000000100100000010001110000000000000011000 287 | 11100011000000011100001000010101100000010000000101000000000000000000 288 | 00100000000000011000000000110010100100011111010001100000000001000000 289 | 10000000000100000000000000001000100110110000000001000000000001011001 290 | 11000001000000000000000000001001000100010000001001000000000011010001 291 | 00100100000100111100000000000000000000000000000101100000000000010000 292 | 10000000000100100000000001001001000100010000001001000000000011001001 293 | 11000001000000000000000000000000000000010000000010000000000000000000 294 | 00110100001100100000000000000000100000000000000101100100000100010000 295 | 00000001000001000000000001000000000000000000000101000000000000010000 296 | 00000001000010000000010001000000100000000000000101000100000010010000 297 | 00100000000100111000000000010000101000010111010101000100000100110010 298 | 11100101000000011100000000000000000000010000000010000000000000000000 299 | 11100101000000011000000000000000100000010000010010000100000100000000 300 | 00000000000000000000000000001000001000000000000101000000000000110001 301 | 00000000000000000000000000000000000000000000000010000000000000000000 302 | 00000000000000000000000000000000000000000000000010000000000000000000 303 | 00000000000000000000000000000000000000000000000010000000000000000000 304 | 00000001000000000000000000001000001001100000000001000000110000110001 305 | 00000001000001000000000001001000000100000000000001010000000001011001 306 | 00100000000000001000001000000000100000000000000010000100000010000000 307 | 11000001000000000000010000001001001000010000000101000000000000110001 308 | 00000000000110000000000001000000100000000000000101000100000100010000 309 | 00000000000101000000000001000000100000000000000101000100000100010000 310 | 00000000000010100000000001010000000100000000000101000000000000010000 311 | 00000000000101000000000001001010000100000000000001010000000001011001 312 | 11100101001000011100000000000000010000010000010010001000000000100000 313 | 00100000000000001000000000001000001000000000000110000000000000110001 314 | 00100000000000011000000000000000100000000100011100000101000100011000 315 | 00100000000000011000000000010000110100000000011100000101000100011000 316 | 01100011100000011000000100010010000000000000000101110000000000000011 317 | 01100010000000011000010100000000010000000000001100000001000000011000 318 | 10000000000100100000000001001000000100010000000001000000000001011001 319 | 01100010000000011000010100000010010000000000001100110001000100011000 320 | 01100011000000011000010000010000000100000000011101110000000001011000 321 | 00000000000000000000010000000000100000000110000101000000000000010000 322 | 00000000000000000000000000000000000000011100001110000000000000011000 323 | 10100000000000001000010000001000101000000110000101000000000000100001 324 | 00100000000000011000000000110001100100001111011001100000000011000010 325 | 00000001000000000000010000000001100001001010000101000010100010010000 326 | 00100010001000111000010000010000000100000000011101000000000001010000 327 | 00100100000100111100000000000000000000000000000101000000000000010000 328 | 00100010000100011000010001010000000100000000011100010000000001010000 329 | 01000001000000000000000100010000011000000000000010000000000000000000 330 | 00000000000000000000010000000000100010000000000101000010001000010000 331 | 00100000000100111000000000000000100000000010000100100000000000010000 332 | 00100010000000011000010000001000001000000000000101000000000000110001 333 | 00000001000000000000010000000000100000000000000101000100000010010000 334 | 00000000000000000000000000000000000000000000000010000000000000000000 335 | 00000000000000000000001000000000100100000000000000110010000001011000 336 | 00000000011000000000000000000010110110000000001100000000001101011000 337 | -------------------------------------------------------------------------------- /RAM.sv: -------------------------------------------------------------------------------- 1 | module RAM_tb 2 | #( 3 | parameter addr_width = 8, 4 | parameter data_width = 8, 5 | parameter mem_sim_file = "" 6 | ) 7 | ( 8 | input CLK, 9 | 10 | input [addr_width-1:0] ADDR, 11 | input [data_width-1:0] DATA, 12 | input CS, 13 | input [data_width/8-1:0] WREN, 14 | output [data_width-1:0] Q 15 | ); 16 | 17 | // synopsys translate_off 18 | `define SIM 19 | // synopsys translate_on 20 | 21 | `ifdef SIM 22 | 23 | reg [data_width-1:0] MEM [2**addr_width]; 24 | 25 | initial begin 26 | MEM = '{2**addr_width{'0}}; 27 | $readmemh(mem_sim_file, MEM); 28 | end 29 | 30 | always @(posedge CLK) begin 31 | bit [data_width-1:0] temp; 32 | 33 | if (data_width > 0) temp[ 7: 0] = WREN[0] ? DATA[ 7: 0] : Q[ 7: 0]; 34 | if (data_width > 8) temp[15: 8] = WREN[1] ? DATA[15: 8] : Q[15: 8]; 35 | if (data_width > 16) temp[23:16] = WREN[2] ? DATA[23:16] : Q[23:16]; 36 | if (data_width > 24) temp[31:24] = WREN[3] ? DATA[31:24] : Q[31:24]; 37 | 38 | if (WREN && CS) begin 39 | MEM[ADDR] <= temp; 40 | end 41 | end 42 | 43 | assign Q = MEM[ADDR]; 44 | 45 | `else 46 | 47 | 48 | 49 | `endif 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /SCSP/RAM_tb.sv: -------------------------------------------------------------------------------- 1 | module RAM_tb 2 | #( 3 | parameter addr_width = 8, 4 | parameter data_width = 8, 5 | parameter mem_sim_file = "" 6 | ) 7 | ( 8 | input CLK, 9 | 10 | input [addr_width-1:0] ADDR, 11 | input [data_width-1:0] DATA, 12 | input CS, 13 | input [data_width/8-1:0] WREN, 14 | output [data_width-1:0] Q 15 | ); 16 | 17 | // synopsys translate_off 18 | `define SIM 19 | // synopsys translate_on 20 | 21 | `ifdef SIM 22 | 23 | reg [data_width-1:0] MEM [2**addr_width]; 24 | 25 | initial begin 26 | MEM = '{2**addr_width{'0}}; 27 | $readmemh(mem_sim_file, MEM); 28 | end 29 | 30 | always @(posedge CLK) begin 31 | bit [data_width-1:0] temp; 32 | 33 | if (data_width > 0) temp[ 7: 0] = WREN[0] ? DATA[ 7: 0] : Q[ 7: 0]; 34 | if (data_width > 8) temp[15: 8] = WREN[1] ? DATA[15: 8] : Q[15: 8]; 35 | if (data_width > 16) temp[23:16] = WREN[2] ? DATA[23:16] : Q[23:16]; 36 | if (data_width > 24) temp[31:24] = WREN[3] ? DATA[31:24] : Q[31:24]; 37 | 38 | if (WREN && CS) begin 39 | MEM[ADDR] <= temp; 40 | end 41 | end 42 | 43 | assign Q = MEM[ADDR]; 44 | 45 | `else 46 | 47 | 48 | 49 | `endif 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /SCSP/SCSP DSP.vsd: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/SCSP/SCSP DSP.vsd -------------------------------------------------------------------------------- /SCSP/SCSP.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 11:18:18 December 28, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "11:18:18 December 28, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "SCSP" 31 | -------------------------------------------------------------------------------- /SCSP/SCSP.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 11:18:18 December 28, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # SCSP_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEMA6F31I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY SCSP 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:18:18 DECEMBER 28, 2020" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 50 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 51 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 53 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 54 | set_global_assignment -name SYSTEMVERILOG_FILE SCSP.sv 55 | set_global_assignment -name SYSTEMVERILOG_FILE SCSP_pkg.sv 56 | set_global_assignment -name QIP_FILE ../FX68K/fx68k.qip 57 | set_global_assignment -name SYSTEMVERILOG_FILE RAM_tb.sv 58 | set_global_assignment -name SYSTEMVERILOG_FILE SCSP_tb.sv 59 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /SCSP/SCSP_tb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | module SCSP_tb; 4 | 5 | bit CLK; 6 | bit RST_N, RES_N; 7 | 8 | always #5 CLK = ~CLK; 9 | 10 | initial begin 11 | RST_N = 0; 12 | RES_N = 0; 13 | #100 RST_N = 1; 14 | RES_N = 1; 15 | end 16 | 17 | bit [18:1] RAM_A; 18 | bit [15:0] RAM_D; 19 | bit [15:0] RAM_Q; 20 | bit [1:0] RAM_WE; 21 | bit RAM_RD; 22 | bit RAM_CS; 23 | 24 | bit SCCE_R; 25 | bit SCCE_F; 26 | bit [23:1] SCA; 27 | bit [15:0] SCDI; 28 | bit [15:0] SCDO; 29 | bit SCRW_N; 30 | bit SCAS_N; 31 | bit SCLDS_N; 32 | bit SCUDS_N; 33 | bit SCDTACK_N; 34 | bit [2:0] SCFC; 35 | bit SCAVEC_N; 36 | bit [2:0] SCIPL_N; 37 | 38 | bit [23:0] SCA_DBG; 39 | 40 | SCSP SCSP 41 | ( 42 | .CLK(CLK), 43 | .RST_N(RST_N), 44 | .CE(1'b1), 45 | 46 | .RES_N(RES_N), 47 | 48 | 49 | .CE_R(1'b0), 50 | .CE_F(1'b0), 51 | .DI('0), 52 | .DO(), 53 | .CS_N(1'b1), 54 | .AD_N(1'b1), 55 | .DTEN_N(1'b1), 56 | .WE_N(2'b11), 57 | .RDY_N(), 58 | 59 | .SCCE_R(SCCE_R), 60 | .SCCE_F(SCCE_F), 61 | .SCA(SCA), 62 | .SCDI(SCDI), 63 | .SCDO(SCDO), 64 | .SCRW_N(SCRW_N), 65 | .SCAS_N(SCAS_N), 66 | .SCLDS_N(SCLDS_N), 67 | .SCUDS_N(SCUDS_N), 68 | .SCDTACK_N(SCDTACK_N), 69 | .SCFC(SCFC), 70 | .SCAVEC_N(SCAVEC_N), 71 | .SCIPL_N(SCIPL_N), 72 | 73 | .RAM_A(RAM_A), 74 | .RAM_D(RAM_D), 75 | .RAM_WE(RAM_WE), 76 | .RAM_RD(RAM_RD), 77 | .RAM_Q(RAM_Q), 78 | .RAM_CS(RAM_CS), 79 | .RAM_RDY(1'b1) 80 | ); 81 | 82 | fx68k M68K 83 | ( 84 | .clk(CLK), 85 | .extReset(~RES_N), 86 | .pwrUp(~RST_N), 87 | .enPhi1(SCCE_R), 88 | .enPhi2(SCCE_F), 89 | 90 | .eab(SCA), 91 | .iEdb(SCDO), 92 | .oEdb(SCDI), 93 | .eRWn(SCRW_N), 94 | .ASn(SCAS_N), 95 | .LDSn(SCLDS_N), 96 | .UDSn(SCUDS_N), 97 | .DTACKn(SCDTACK_N), 98 | 99 | .IPL0n(SCIPL_N[0]), 100 | .IPL1n(SCIPL_N[1]), 101 | .IPL2n(SCIPL_N[2]), 102 | 103 | .VPAn(SCAVEC_N), 104 | 105 | .FC0(SCFC[0]), 106 | .FC1(SCFC[1]), 107 | .FC2(SCFC[2]), 108 | 109 | .BGn(), 110 | .BRn(1'b1), 111 | .BGACKn(1'b1), 112 | 113 | .BERRn(1'b1), 114 | .HALTn(1'b1) 115 | ); 116 | 117 | assign SCA_DBG = {SCA,1'b0}; 118 | 119 | RAM_tb #(18,16,"sndram.txt") RAM(CLK, RAM_A, RAM_D, RAM_CS, RAM_WE, RAM_Q); 120 | 121 | 122 | 123 | endmodule 124 | 125 | -------------------------------------------------------------------------------- /SCSP/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /SCSP_tb/SCSP/CLK 4 | add wave -noupdate /SCSP_tb/SCSP/SCCE_R 5 | add wave -noupdate /SCSP_tb/SCSP/SCCE_F 6 | add wave -noupdate /SCSP_tb/SCSP/SCA_DBG 7 | add wave -noupdate /SCSP_tb/M68K/iEdb 8 | add wave -noupdate /SCSP_tb/M68K/oEdb 9 | add wave -noupdate /SCSP_tb/M68K/eRWn 10 | add wave -noupdate /SCSP_tb/M68K/ASn 11 | add wave -noupdate /SCSP_tb/M68K/LDSn 12 | add wave -noupdate /SCSP_tb/M68K/UDSn 13 | add wave -noupdate /SCSP_tb/M68K/DTACKn 14 | add wave -noupdate /SCSP_tb/SCSP/MEM_ST 15 | add wave -noupdate /SCSP_tb/SCSP/MEM_A 16 | add wave -noupdate /SCSP_tb/SCSP/MEM_D 17 | add wave -noupdate /SCSP_tb/SCSP/MEM_Q 18 | add wave -noupdate /SCSP_tb/SCSP/MEM_WE 19 | add wave -noupdate /SCSP_tb/SCSP/MEM_RD 20 | add wave -noupdate /SCSP_tb/SCSP/MEM_CS 21 | add wave -noupdate /SCSP_tb/SCSP/REG_CS 22 | TreeUpdate [SetDefaultTree] 23 | WaveRestoreCursors {{Cursor 1} {2999951 ns} 0} 24 | quietly wave cursor active 1 25 | configure wave -namecolwidth 150 26 | configure wave -valuecolwidth 100 27 | configure wave -justifyvalue left 28 | configure wave -signalnamewidth 0 29 | configure wave -snapdistance 10 30 | configure wave -datasetprefix 0 31 | configure wave -rowmargin 4 32 | configure wave -childrowmargin 2 33 | configure wave -gridoffset 0 34 | configure wave -gridperiod 1 35 | configure wave -griddelta 40 36 | configure wave -timeline 0 37 | configure wave -timelineunits us 38 | update 39 | WaveRestoreZoom {2999050 ns} {3000050 ns} 40 | -------------------------------------------------------------------------------- /SCU/DSP.sv: -------------------------------------------------------------------------------- 1 | module SCU_DSP ( 2 | input CLK, 3 | input RST_N, 4 | input CE, 5 | 6 | input RES_N, 7 | 8 | input CE_R, 9 | input CE_F, 10 | input [1:0] A, 11 | input [31:0] DI, 12 | output reg [31:0] DO, 13 | input [3:0] WE, 14 | input RE, 15 | 16 | output [31:0] DSO, 17 | output RA0W, 18 | output WA0W, 19 | output DMAW, 20 | 21 | input [31:0] DMA_DI, 22 | output [31:0] DMA_DO, 23 | output DMA_WE, 24 | output reg DMA_REQ, 25 | input DMA_ACK, 26 | output DMA_RUN, 27 | output DMA_LAST, 28 | input DMA_END, 29 | 30 | output IRQ, 31 | output DecInst_t DBG_DECI, 32 | output [47:0] DBG_Q, 33 | output [47:0] DBG_AC, 34 | output [47:0] DBG_P, 35 | output reg HOOK1, 36 | output reg HOOK2 37 | ); 38 | 39 | import SCUDSP_PKG::*; 40 | 41 | //Registers 42 | ALUReg_t AC; 43 | ALUReg_t P; 44 | bit [31:0] RX; 45 | bit [31:0] RY; 46 | bit [7:0] PC; 47 | bit [11:0] LOP; 48 | bit [7:0] TOP; 49 | bit [5:0] CT0; 50 | bit [5:0] CT1; 51 | bit [5:0] CT2; 52 | bit [5:0] CT3; 53 | bit [7:0] TN0; 54 | bit T0; 55 | bit EX; 56 | bit EP; 57 | bit PR; 58 | bit ES; 59 | bit LE; 60 | bit E; 61 | bit S; 62 | bit Z; 63 | bit C; 64 | bit V; 65 | 66 | bit [5:0] DATA_RAM_ADDR [4]; 67 | bit [31:0] DATA_RAM_D [4]; 68 | bit DATA_RAM_WE [4]; 69 | bit [31:0] DATA_RAM_Q [4]; 70 | 71 | bit [7:0] PRG_RAM_ADDR; 72 | bit [31:0] PRG_RAM_D; 73 | bit PRG_RAM_WE; 74 | bit [31:0] PRG_RAM_Q; 75 | 76 | bit [7:0] DATA_TRANS_ADDR; 77 | // bit PRG_TRANS_AS; 78 | bit PRG_TRANS_WE; 79 | bit [7:0] PRG_TRANS_ADDR; 80 | bit DATA_TRANS_WE; 81 | bit DATA_TRANS_RE; 82 | 83 | wire DMA_CE = T0 && DMA_ACK; 84 | wire RUN = (EX || ES) && ~T0; 85 | 86 | 87 | reg [31:0] IC; 88 | DecInst_t DECI; 89 | always @(posedge CLK or negedge RST_N) begin 90 | if (!RST_N) begin 91 | IC <= '0; 92 | end else if (!RES_N) begin 93 | IC <= '0; 94 | end else if (CE) begin 95 | if (!EX) begin 96 | IC <= '0; 97 | end 98 | if (RUN) begin 99 | IC <= PRG_RAM_Q; 100 | end 101 | end 102 | end 103 | 104 | wire COND = IC[24] ? ((IC[22]&T0) | (IC[21]&C) | (IC[20]&S) | (IC[19]&Z)) : ((~IC[22]|~T0) & (~IC[21]|~C) & (~IC[20]|~S) & (~IC[19]|~Z)); 105 | assign DECI = Decode(IC, COND); 106 | assign DBG_DECI = DECI; 107 | 108 | DMAInst_t DMAI; 109 | 110 | 111 | //ALU 112 | ALUReg_t ALU_Q; 113 | bit ALU_C; 114 | always_comb begin 115 | {ALU_C,ALU_Q} = {1'b0,AC}; 116 | case (IC[29:26]) 117 | 4'b0001: {ALU_C,ALU_Q.L} = {1'b0,AC.L} & {1'b0,P.L}; 118 | 4'b0010: {ALU_C,ALU_Q.L} = {1'b0,AC.L} | {1'b0,P.L}; 119 | 4'b0011: {ALU_C,ALU_Q.L} = {1'b0,AC.L} ^ {1'b0,P.L}; 120 | 4'b0100: {ALU_C,ALU_Q.L} = {1'b0,AC.L} + {1'b0,P.L}; 121 | 4'b0101: {ALU_C,ALU_Q.L} = {1'b0,AC.L} - {1'b0,P.L}; 122 | 4'b0110: {ALU_C,ALU_Q } = {1'b0,AC } + {1'b0,P }; 123 | 4'b1000: {ALU_Q.L,ALU_C} = {AC.L[31],AC.L}; 124 | 4'b1001: {ALU_Q.L,ALU_C} = {AC.L[0],AC.L}; 125 | 4'b1010: {ALU_C,ALU_Q.L} = {AC.L,1'b0}; 126 | 4'b1011: {ALU_C,ALU_Q.L} = {AC.L,AC.L[31]}; 127 | 4'b1111: {ALU_C,ALU_Q.L} = {AC.L[24:0],AC.L[31:24]}; 128 | default: ; 129 | endcase 130 | end 131 | 132 | assign DBG_Q = ALU_Q; 133 | assign DBG_AC = AC; 134 | assign DBG_P = P; 135 | 136 | always @(posedge CLK or negedge RST_N) begin 137 | bit S31, S47, ZL, ZH; 138 | 139 | if (!RST_N) begin 140 | S <= 0; 141 | Z <= 0; 142 | C <= 0; 143 | V <= 0; 144 | end else if (!RES_N) begin 145 | S <= 0; 146 | Z <= 0; 147 | C <= 0; 148 | V <= 0; 149 | end else if (RUN && CE) begin 150 | S31 = ALU_Q[31]; 151 | S47 = ALU_Q[47]; 152 | ZL = ~|ALU_Q.L; 153 | ZH = ~|ALU_Q.H; 154 | if (DECI.ALU) begin 155 | case (IC[29:26]) 156 | 4'b0001: begin S <= S31; Z <= ZL; C <= ALU_C; end 157 | 4'b0010: begin S <= S31; Z <= ZL; C <= ALU_C; end 158 | 4'b0011: begin S <= S31; Z <= ZL; C <= ALU_C; end 159 | 4'b0100: begin S <= S31; Z <= ZL; C <= ALU_C; end 160 | 4'b0101: begin S <= S31; Z <= ZL; C <= ALU_C; end 161 | 4'b0110: begin S <= S47; Z <= ZL&ZH; C <= ALU_C; end 162 | 4'b1000: begin S <= S31; Z <= ZL; C <= ALU_C; end 163 | 4'b1001: begin S <= S31; Z <= ZL; C <= ALU_C; end 164 | 4'b1010: begin S <= S31; Z <= ZL; C <= ALU_C; end 165 | 4'b1011: begin S <= S31; Z <= ZL; C <= ALU_C; end 166 | 4'b1111: begin S <= S31; Z <= ZL; C <= ALU_C; end 167 | default:; 168 | endcase 169 | V <= 0;//TODO 170 | end 171 | // else begin 172 | // if (A == 2'b00 && RE) begin 173 | // V <= 0; 174 | // end 175 | // end 176 | end 177 | end 178 | 179 | wire [47: 0] MUL = $signed(RX) * $signed(RY); 180 | 181 | 182 | wire [31: 0] D0BUSI = DMA_DI; 183 | bit [31: 0] D0BUSO; 184 | bit [31: 0] D1BUS; 185 | bit [31: 0] XBUS; 186 | bit [31: 0] YBUS; 187 | always_comb begin 188 | XBUS = DATA_RAM_Q[DECI.XBUS.RAMS]; 189 | YBUS = DATA_RAM_Q[DECI.YBUS.RAMS]; 190 | 191 | if (DECI.D1BUS.IMMS) begin 192 | D1BUS = ImmSext(IC, DECI.D1BUS.IMMT);; 193 | end else if (DECI.D1BUS.ALUS) begin 194 | case (DECI.D1BUS.RAMS[0]) 195 | 1'b0: D1BUS = ALU_Q[47:16];//ALU HIGH 196 | 2'b1: D1BUS = ALU_Q[31: 0];//ALU LOW 197 | endcase 198 | end else if (DECI.D1BUS.DMAW) begin 199 | D1BUS = IC; 200 | end else begin 201 | D1BUS = DATA_RAM_Q[DECI.D1BUS.RAMS]; 202 | end 203 | 204 | D0BUSO = DATA_RAM_Q[DMAI.RAMS]; 205 | end 206 | 207 | always @(posedge CLK or negedge RST_N) begin 208 | if (!RST_N) begin 209 | // synopsys translate_off 210 | RX <= '0; 211 | RY <= '0; 212 | AC <= '0; 213 | P <= '0; 214 | // synopsys translate_on 215 | end else if (!RES_N) begin 216 | RX <= '0; 217 | RY <= '0; 218 | AC <= '0; 219 | P <= '0; 220 | end else if (RUN && CE) begin 221 | //X set 222 | if (DECI.XBUS.RXW) begin 223 | RX <= XBUS; 224 | end 225 | if (DECI.D1BUS.RXW) begin 226 | RX <= D1BUS; 227 | end 228 | 229 | //Y set 230 | if (DECI.YBUS.RYW) begin 231 | RY <= YBUS; 232 | end 233 | 234 | //AC set 235 | if (DECI.YBUS.ACW) begin 236 | case (DECI.YBUS.ACS) 237 | 2'b01: AC <= '0; 238 | 2'b10: AC <= ALU_Q; 239 | 2'b11: AC <= {{16{YBUS[31]}},YBUS}; 240 | default:; 241 | endcase 242 | end 243 | 244 | //P set 245 | if (DECI.XBUS.PW) begin 246 | if (DECI.XBUS.MULS) P <= MUL[47:0]; 247 | else P <= {{16{XBUS[31]}},XBUS}; 248 | end 249 | if (DECI.D1BUS.PW) begin 250 | P <= {{16{D1BUS[31]}},D1BUS}; 251 | end 252 | end 253 | end 254 | 255 | always @(posedge CLK or negedge RST_N) begin 256 | if (!RST_N) begin 257 | // synopsys translate_off 258 | CT0 <= '0; 259 | CT1 <= '0; 260 | CT2 <= '0; 261 | CT3 <= '0; 262 | // synopsys translate_on 263 | end else if (!RES_N) begin 264 | CT0 <= '0; 265 | CT1 <= '0; 266 | CT2 <= '0; 267 | CT3 <= '0; 268 | end else begin 269 | if (RUN && CE) begin 270 | if (DECI.XBUS.CTI[0] || DECI.YBUS.CTI[0] || DECI.D1BUS.CTI[0] || DECI.DMA.CTI[0]) CT0 <= CT0 + 6'd1; 271 | if (DECI.D1BUS.CTW[0]) CT0 <= D1BUS[5:0]; 272 | 273 | if (DECI.XBUS.CTI[1] || DECI.YBUS.CTI[1] || DECI.D1BUS.CTI[1] || DECI.DMA.CTI[1]) CT1 <= CT1 + 6'd1; 274 | if (DECI.D1BUS.CTW[1]) CT1 <= D1BUS[5:0]; 275 | 276 | if (DECI.XBUS.CTI[2] || DECI.YBUS.CTI[2] || DECI.D1BUS.CTI[2] || DECI.DMA.CTI[2]) CT2 <= CT2 + 6'd1; 277 | if (DECI.D1BUS.CTW[2]) CT2 <= D1BUS[5:0]; 278 | 279 | if (DECI.XBUS.CTI[3] || DECI.YBUS.CTI[3] || DECI.D1BUS.CTI[3] || DECI.DMA.CTI[3]) CT3 <= CT3 + 6'd1; 280 | if (DECI.D1BUS.CTW[3]) CT3 <= D1BUS[5:0]; 281 | end 282 | 283 | if (DMA_CE && CE_R) begin 284 | if (DMAI.RAMW[0] || DMAI.RAMR[0]) CT0 <= CT0 + 6'd1; 285 | if (DMAI.RAMW[1] || DMAI.RAMR[1]) CT1 <= CT1 + 6'd1; 286 | if (DMAI.RAMW[2] || DMAI.RAMR[2]) CT2 <= CT2 + 6'd1; 287 | if (DMAI.RAMW[3] || DMAI.RAMR[3]) CT3 <= CT3 + 6'd1; 288 | end 289 | end 290 | end 291 | 292 | always @(posedge CLK or negedge RST_N) begin 293 | if (!RST_N) begin 294 | // synopsys translate_off 295 | PC <= '0; 296 | LOP <= '0; 297 | TOP <= '0; 298 | // synopsys translate_on 299 | end else if (!RES_N) begin 300 | PC <= '0; 301 | LOP <= '0; 302 | TOP <= '0; 303 | end else begin 304 | if (RUN && CE) begin 305 | PC <= PC + 8'd1; 306 | if (DECI.D1BUS.PCW) begin 307 | PC <= D1BUS[7:0]; 308 | TOP <= PC; 309 | end 310 | if (DECI.JPCW) begin 311 | PC <= IC[7:0]; 312 | end 313 | if (DECI.CTL.BTM || DECI.CTL.LPS) begin 314 | if (LOP) begin 315 | LOP <= LOP - 12'd1; 316 | if (DECI.CTL.BTM) PC <= TOP; 317 | if (DECI.CTL.LPS) PC <= PC - 8'd1;//? 318 | end 319 | end 320 | 321 | if (DECI.D1BUS.LOPW) begin 322 | LOP <= D1BUS[11:0]; 323 | end 324 | 325 | if (DECI.D1BUS.TOPW) begin 326 | TOP <= D1BUS[7:0]; 327 | end 328 | end 329 | 330 | if (A == 2'b00 && WE && DI[15] && CE_R) begin 331 | PC <= DI[7:0]; 332 | end 333 | end 334 | end 335 | 336 | always @(posedge CLK or negedge RST_N) begin 337 | bit [7:0] CNT_VAL; 338 | bit DMA_END_OLD; 339 | bit DMA_END_PEND; 340 | 341 | if (!RST_N) begin 342 | TN0 <= '0; 343 | T0 <= 0; 344 | DMAI <= '0; 345 | DMA_REQ <= 0; 346 | DMA_END_PEND <= 0; 347 | 348 | HOOK1 <= 0; 349 | HOOK2 <= 0; 350 | end else if (!RES_N) begin 351 | TN0 <= '0; 352 | T0 <= 0; 353 | DMAI <= '0; 354 | DMA_REQ <= 0; 355 | end else begin 356 | if (CE) begin 357 | if (RUN) begin 358 | if (DECI.DMA.CNTM) begin 359 | CNT_VAL = DATA_RAM_Q[DECI.DMA.CNTS][7:0]; 360 | end 361 | else begin 362 | CNT_VAL = IC[7:0]; 363 | end 364 | 365 | if (DECI.DMA.ST && !T0) begin 366 | T0 <= 1; 367 | TN0 <= CNT_VAL; 368 | DMAI <= DECI.DMA; 369 | DMA_REQ <= 1; 370 | end 371 | end 372 | 373 | DMA_END_PEND <= 0; 374 | if (DMA_END_PEND) begin 375 | T0 <= 0; 376 | end 377 | end 378 | 379 | if (CE_F) begin 380 | DMA_END_OLD <= DMA_END; 381 | if (!DMA_END && DMA_END_OLD) begin 382 | DMA_END_PEND <= 1; 383 | end 384 | end 385 | if (CE_R) begin 386 | if (DMA_CE) begin 387 | DMA_REQ <= 0; 388 | TN0 <= TN0 - 8'd1; 389 | if (TN0 > 8'd1) begin 390 | DMA_REQ <= 1; 391 | end 392 | 393 | if (D0BUSO[31:16] != 16'h0000 && D0BUSO[31:16] != 16'hFFFF && DMAI.RAMR[3] && DMAI.DIR) HOOK1 <= 1; 394 | if (DMA_DI[31:16] != 16'h0000 && DMA_DI[31:16] != 16'hFFFF && (DMAI.RAMW[1] || DMAI.RAMW[2]) && !DMAI.DIR) HOOK2 <= 1; 395 | end 396 | end 397 | end 398 | end 399 | 400 | assign DMA_DO = D0BUSO; 401 | assign DMA_WE = DMAI.DIR; 402 | assign DMA_RUN = T0; 403 | assign DMA_LAST = (TN0 == 8'd1); 404 | 405 | assign DSO = D1BUS; 406 | assign RA0W = DECI.D1BUS.RA0W & RUN & CE; 407 | assign WA0W = DECI.D1BUS.WA0W & RUN & CE; 408 | assign DMAW = DECI.D1BUS.DMAW & RUN & CE; 409 | 410 | //DATA RAM 411 | wire DATA_TRANS_CS[4] = '{DATA_TRANS_ADDR[7:6] == 2'b00,DATA_TRANS_ADDR[7:6] == 2'b01,DATA_TRANS_ADDR[7:6] == 2'b10,DATA_TRANS_ADDR[7:6] == 2'b11}; 412 | 413 | assign DATA_RAM_ADDR[0] = RUN || T0 ? CT0 : DATA_TRANS_ADDR[5:0]; 414 | assign DATA_RAM_D[0] = T0 ? D0BUSI : RUN ? D1BUS : DI; 415 | assign DATA_RAM_WE[0] = T0 ? DMAI.RAMW[0] & DMA_CE & CE_R : RUN ? DECI.D1BUS.RAMW[0] & CE : DATA_TRANS_WE && DATA_TRANS_CS[0] & CE_R; 416 | DSP_DATA_RAM #(6,32) DATA_RAM0(CLK, DATA_RAM_ADDR[0], DATA_RAM_D[0], DATA_RAM_WE[0], DATA_RAM_Q[0]); 417 | 418 | assign DATA_RAM_ADDR[1] = RUN || T0 ? CT1 : DATA_TRANS_ADDR[5:0]; 419 | assign DATA_RAM_D[1] = T0 ? D0BUSI : RUN ? D1BUS : DI; 420 | assign DATA_RAM_WE[1] = T0 ? DMAI.RAMW[1] & DMA_CE & CE_R : RUN ? DECI.D1BUS.RAMW[1] & CE : DATA_TRANS_WE && DATA_TRANS_CS[1] & CE_R ; 421 | DSP_DATA_RAM #(6,32) DATA_RAM1(CLK, DATA_RAM_ADDR[1], DATA_RAM_D[1], DATA_RAM_WE[1], DATA_RAM_Q[1]); 422 | 423 | assign DATA_RAM_ADDR[2] = RUN || T0 ? CT2 : DATA_TRANS_ADDR[5:0]; 424 | assign DATA_RAM_D[2] = T0 ? D0BUSI : RUN ? D1BUS : DI; 425 | assign DATA_RAM_WE[2] = T0 ? DMAI.RAMW[2] & DMA_CE & CE_R : RUN ? DECI.D1BUS.RAMW[2] & CE : DATA_TRANS_WE && DATA_TRANS_CS[2] & CE_R ; 426 | DSP_DATA_RAM #(6,32) DATA_RAM2(CLK, DATA_RAM_ADDR[2], DATA_RAM_D[2], DATA_RAM_WE[2], DATA_RAM_Q[2]); 427 | 428 | assign DATA_RAM_ADDR[3] = RUN || T0 ? CT3 : DATA_TRANS_ADDR[5:0]; 429 | assign DATA_RAM_D[3] = T0 ? D0BUSI : RUN ? D1BUS : DI; 430 | assign DATA_RAM_WE[3] = T0 ? DMAI.RAMW[3] & DMA_CE & CE_R : RUN ? DECI.D1BUS.RAMW[3] & CE : DATA_TRANS_WE && DATA_TRANS_CS[3] & CE_R ; 431 | DSP_DATA_RAM #(6,32) DATA_RAM3(CLK, DATA_RAM_ADDR[3], DATA_RAM_D[3], DATA_RAM_WE[3], DATA_RAM_Q[3]); 432 | 433 | //Control port 434 | always @(posedge CLK or negedge RST_N) begin 435 | bit WE_OLD; 436 | bit RE_OLD; 437 | 438 | if (!RST_N) begin 439 | EX <= 0; 440 | EP <= 0; 441 | PR <= 0; 442 | ES <= 0; 443 | LE <= 0; 444 | E <= 0; 445 | PRG_TRANS_ADDR <= '0; 446 | PRG_TRANS_WE <= 0; 447 | DATA_TRANS_ADDR <= '0; 448 | DATA_TRANS_WE <= 0; 449 | DATA_TRANS_RE <= 0; 450 | end else if (!RES_N) begin 451 | EX <= 0; 452 | EP <= 0; 453 | PR <= 0; 454 | ES <= 0; 455 | LE <= 0; 456 | E <= 0; 457 | end else begin 458 | if (CE_R) begin 459 | PRG_TRANS_WE <= 0; 460 | DATA_TRANS_WE <= 0; 461 | if (PRG_TRANS_WE) PRG_TRANS_ADDR <= PRG_TRANS_ADDR + 8'd1; 462 | if (DATA_TRANS_WE) DATA_TRANS_ADDR <= DATA_TRANS_ADDR + 8'd1; 463 | 464 | WE_OLD <= |WE; 465 | if (WE && !WE_OLD) begin 466 | case (A) 467 | 2'b00: begin 468 | EX <= DI[16]; 469 | LE <= DI[15]; 470 | PRG_TRANS_ADDR <= DI[7:0]; 471 | if (EX && !EP && DI[25]) begin 472 | EP <= 1; 473 | PR <= 0; 474 | end 475 | if (EX && !PR && DI[26]) begin 476 | PR <= 1; 477 | EP <= 0; 478 | end 479 | if (!EX && DI[17]) begin 480 | ES <= 1; 481 | end 482 | end 483 | 2'b01: begin 484 | PRG_TRANS_WE <= 1; 485 | end 486 | 2'b10: begin 487 | DATA_TRANS_ADDR <= DI[7:0]; 488 | end 489 | 2'b11: begin 490 | DATA_TRANS_WE <= 1; 491 | end 492 | default:; 493 | endcase 494 | end 495 | end else if (CE_F) begin 496 | DATA_TRANS_RE <= 0; 497 | if (DATA_TRANS_RE) DATA_TRANS_ADDR <= DATA_TRANS_ADDR + 8'd1; 498 | 499 | RE_OLD <= RE; 500 | if (RE && !RE_OLD) begin 501 | case (A) 502 | 2'b00: DO <= {8'h00,T0,S,Z,C,V,E,1'b0,EX,8'h00,PC}; 503 | 2'b01: DO <= '0; 504 | 2'b10: DO <= '0; 505 | 2'b11: begin 506 | DO <= DATA_RAM_Q[DATA_TRANS_ADDR[7:6]]; 507 | DATA_TRANS_RE <= 1; 508 | end 509 | default: DO <= '0; 510 | endcase 511 | if (A == 2'b00 && E) begin 512 | E <= 0; 513 | end 514 | end 515 | end 516 | 517 | if (RUN && CE) begin 518 | if (ES) ES <= 0; 519 | 520 | if (DECI.CTL.END) begin 521 | EX <= 0; 522 | if (DECI.CTL.EI) E <= 1; 523 | end 524 | end 525 | end 526 | end 527 | 528 | assign IRQ = E; 529 | 530 | //PRG RAM 531 | assign PRG_RAM_ADDR = RUN ? PC : PRG_TRANS_ADDR; 532 | assign PRG_RAM_D = DI; 533 | assign PRG_RAM_WE = !RUN && PRG_TRANS_WE; 534 | DSP_PRG_RAM #(8,32," ","prg.txt") PRG_RAM(CLK, PRG_RAM_ADDR, PRG_RAM_D, PRG_RAM_WE & CE_R, PRG_RAM_Q); 535 | 536 | 537 | endmodule 538 | -------------------------------------------------------------------------------- /SCU/DSP_PKG.sv: -------------------------------------------------------------------------------- 1 | package SCUDSP_PKG; 2 | 3 | typedef struct packed 4 | { 5 | bit [15: 0] H; 6 | bit [31: 0] L; 7 | } ALUReg_t; 8 | 9 | typedef struct packed 10 | { 11 | bit [ 1: 0] RAMS; 12 | bit MULS; 13 | bit RXW; 14 | bit PW; 15 | bit [ 3: 0] CTI; 16 | } XBusInst_t; 17 | 18 | typedef struct packed 19 | { 20 | bit [ 1: 0] RAMS; 21 | bit [ 1: 0] ACS; 22 | bit RYW; 23 | bit ACW; 24 | bit [ 3: 0] CTI; 25 | } YBusInst_t; 26 | 27 | typedef struct packed 28 | { 29 | bit IMMS; 30 | bit [ 1: 0] IMMT; //Immadiate type (8/25/19) 31 | bit ALUS; 32 | bit [ 1: 0] RAMS; 33 | bit RXW; 34 | bit PW; 35 | bit RA0W; 36 | bit WA0W; 37 | bit LOPW; 38 | bit TOPW; 39 | bit PCW; 40 | bit DMAW; //DMA opcode out 41 | bit [ 3: 0] RAMW; 42 | bit [ 3: 0] CTW; 43 | bit [ 3: 0] CTI; 44 | } D1BusInst_t; 45 | 46 | typedef struct packed 47 | { 48 | bit ST; //DMA start 49 | bit DIR; //DMA direction (0: D0->RAM, 1: RAM->D0) 50 | bit [ 3: 0] RAMW; //DMA DATA RAM write 51 | bit PRGW; //DMA PRG RAM write 52 | bit [ 3: 0] RAMR; //DMA DATA RAM read 53 | bit [ 1: 0] RAMS; //DMA DATA RAM bank select 54 | // bit [ 2: 0] ADDI; //DMA address increment 55 | bit CNTM; //DMA counter source mode (0: IMM8, 1: RAMx) 56 | bit [ 1: 0] CNTS; //DMA TN0 source (RAMx) 57 | bit [ 3: 0] CTI; //DMA counter source DATA RAM address increment 58 | // bit HOLD; 59 | } DMAInst_t; 60 | 61 | typedef struct packed 62 | { 63 | bit BTM; 64 | bit LPS; 65 | bit END; 66 | bit EI; 67 | } CtlInst_t; 68 | 69 | typedef struct packed 70 | { 71 | bit ALU; 72 | XBusInst_t XBUS; 73 | YBusInst_t YBUS; 74 | D1BusInst_t D1BUS; 75 | bit JPCW; //Set PC in JUMP command 76 | DMAInst_t DMA; 77 | CtlInst_t CTL; 78 | } DecInst_t; 79 | 80 | parameter DecInst_t DECINST_RESET = '{1'b0, 81 | {2'b00, 1'b0, 1'b0, 1'b0, 4'b0000}, 82 | {2'b00, 2'b00, 1'b0, 1'b0, 4'b0000}, 83 | {1'b0, 2'b00, 1'b0, 2'b00, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 4'b0000, 4'b0000, 4'b0000}, 84 | 1'b0, 85 | {1'b0, 1'b0, 4'b0000, 1'b0, 4'b0000, 2'b00/*, 3'b000*/, 1'b0, 2'b00, 4'b0000/*, 1'b0*/}, 86 | {1'b0, 1'b0, 1'b0, 1'b0}}; 87 | 88 | function DecInst_t Decode(input bit [31:0] IC, bit COND); 89 | DecInst_t di; 90 | 91 | di = DECINST_RESET; 92 | case (IC[31:28]) 93 | 4'b0000,4'b0001,4'b0010,4'b0011: begin 94 | di.ALU = |IC[29:26]; 95 | 96 | di.XBUS.RAMS = IC[21:20]; 97 | di.XBUS.MULS = ~IC[23]; 98 | di.XBUS.RXW = IC[25]; 99 | di.XBUS.PW = IC[24]; 100 | case (IC[21:20]) 101 | 2'b00: di.XBUS.CTI[0] = |IC[25:23] & IC[22]; 102 | 2'b01: di.XBUS.CTI[1] = |IC[25:23] & IC[22]; 103 | 2'b10: di.XBUS.CTI[2] = |IC[25:23] & IC[22]; 104 | 2'b11: di.XBUS.CTI[3] = |IC[25:23] & IC[22]; 105 | endcase 106 | 107 | di.YBUS.RAMS = IC[15:14]; 108 | di.YBUS.ACS = IC[18:17]; 109 | di.YBUS.RYW = IC[19]; 110 | di.YBUS.ACW = |IC[18:17]; 111 | case (IC[15:14]) 112 | 2'b00: di.YBUS.CTI[0] = |IC[19:17] & IC[16]; 113 | 2'b01: di.YBUS.CTI[1] = |IC[19:17] & IC[16]; 114 | 2'b10: di.YBUS.CTI[2] = |IC[19:17] & IC[16]; 115 | 2'b11: di.YBUS.CTI[3] = |IC[19:17] & IC[16]; 116 | endcase 117 | 118 | di.D1BUS.IMMS = ~IC[13] & IC[12]; 119 | di.D1BUS.IMMT = 2'b00; 120 | di.D1BUS.ALUS = IC[13] & IC[12] & (IC[3:0] == 4'h9 | IC[3:0] == 4'hA); 121 | di.D1BUS.RAMS = IC[1:0]; 122 | case (IC[11:8]) 123 | 4'b0000: di.D1BUS.RAMW[0] = IC[12]; 124 | 4'b0001: di.D1BUS.RAMW[1] = IC[12]; 125 | 4'b0010: di.D1BUS.RAMW[2] = IC[12]; 126 | 4'b0011: di.D1BUS.RAMW[3] = IC[12]; 127 | 4'b0100: di.D1BUS.RXW = IC[12]; 128 | 4'b0101: di.D1BUS.PW = IC[12]; 129 | 4'b0110: di.D1BUS.RA0W = IC[12]; 130 | 4'b0111: di.D1BUS.WA0W = IC[12]; 131 | 4'b1010: di.D1BUS.LOPW = IC[12]; 132 | 4'b1011: di.D1BUS.TOPW = IC[12]; 133 | 4'b1100: di.D1BUS.CTW[0] = IC[12]; 134 | 4'b1101: di.D1BUS.CTW[1] = IC[12]; 135 | 4'b1110: di.D1BUS.CTW[2] = IC[12]; 136 | 4'b1111: di.D1BUS.CTW[3] = IC[12]; 137 | default:; 138 | endcase 139 | case (IC[1:0]) 140 | 2'b00: di.D1BUS.CTI[0] = &IC[13:12] & ~IC[3] & IC[2]; 141 | 2'b01: di.D1BUS.CTI[1] = &IC[13:12] & ~IC[3] & IC[2]; 142 | 2'b10: di.D1BUS.CTI[2] = &IC[13:12] & ~IC[3] & IC[2]; 143 | 2'b11: di.D1BUS.CTI[3] = &IC[13:12] & ~IC[3] & IC[2]; 144 | endcase 145 | case (IC[9:8]) 146 | 2'b00: di.D1BUS.CTI[0] = |IC[13:12] & ~IC[11] & ~IC[10]; 147 | 2'b01: di.D1BUS.CTI[1] = |IC[13:12] & ~IC[11] & ~IC[10]; 148 | 2'b10: di.D1BUS.CTI[2] = |IC[13:12] & ~IC[11] & ~IC[10]; 149 | 2'b11: di.D1BUS.CTI[3] = |IC[13:12] & ~IC[11] & ~IC[10]; 150 | endcase 151 | end 152 | 153 | 4'b1000,4'b1001,4'b1010,4'b1011: begin 154 | di.D1BUS.IMMS = 1; 155 | di.D1BUS.IMMT = {1'b1,IC[25]}; 156 | case (IC[29:26]) 157 | 4'b0000: di.D1BUS.RAMW[0] = ~IC[25] | COND; 158 | 4'b0001: di.D1BUS.RAMW[1] = ~IC[25] | COND; 159 | 4'b0010: di.D1BUS.RAMW[2] = ~IC[25] | COND; 160 | 4'b0011: di.D1BUS.RAMW[3] = ~IC[25] | COND; 161 | 4'b0100: di.D1BUS.RXW = ~IC[25] | COND; 162 | 4'b0101: di.D1BUS.PW = ~IC[25] | COND; 163 | 4'b0110: di.D1BUS.RA0W = ~IC[25] | COND; 164 | 4'b0111: di.D1BUS.WA0W = ~IC[25] | COND; 165 | 4'b1010: di.D1BUS.LOPW = ~IC[25] | COND; 166 | //4'b1011: di.D1BUS.TOPW = ~IC[25] | COND; 167 | 4'b1100: di.D1BUS.PCW = ~IC[25] | COND; 168 | default:; 169 | endcase 170 | case (IC[27:26]) 171 | 2'b00: di.D1BUS.CTI[0] = ~IC[29] & ~IC[28] & (~IC[25] | COND); 172 | 2'b01: di.D1BUS.CTI[1] = ~IC[29] & ~IC[28] & (~IC[25] | COND); 173 | 2'b10: di.D1BUS.CTI[2] = ~IC[29] & ~IC[28] & (~IC[25] | COND); 174 | 2'b11: di.D1BUS.CTI[3] = ~IC[29] & ~IC[28] & (~IC[25] | COND); 175 | endcase 176 | end 177 | 178 | 4'b1100: begin 179 | di.DMA.ST = 1; 180 | di.DMA.DIR = IC[12]; 181 | case (IC[9:8]) 182 | 2'b00: di.DMA.RAMW[0] = ~IC[10] & ~IC[12]; 183 | 2'b01: di.DMA.RAMW[1] = ~IC[10] & ~IC[12]; 184 | 2'b10: di.DMA.RAMW[2] = ~IC[10] & ~IC[12]; 185 | 2'b11: di.DMA.RAMW[3] = ~IC[10] & ~IC[12]; 186 | endcase 187 | di.DMA.PRGW = IC[10] & ~IC[12]; 188 | case (IC[9:8]) 189 | 2'b00: di.DMA.RAMR[0] = ~IC[10] & IC[12]; 190 | 2'b01: di.DMA.RAMR[1] = ~IC[10] & IC[12]; 191 | 2'b10: di.DMA.RAMR[2] = ~IC[10] & IC[12]; 192 | 2'b11: di.DMA.RAMR[3] = ~IC[10] & IC[12]; 193 | endcase 194 | di.DMA.RAMS = IC[9:8]; 195 | // di.DMA.ADDI = IC[17:15]; 196 | di.DMA.CNTM = IC[13]; 197 | di.DMA.CNTS = IC[1:0]; 198 | case (IC[1:0]) 199 | 2'b00: di.DMA.CTI[0] = IC[13] & IC[2]; 200 | 2'b01: di.DMA.CTI[1] = IC[13] & IC[2]; 201 | 2'b10: di.DMA.CTI[2] = IC[13] & IC[2]; 202 | 2'b11: di.DMA.CTI[3] = IC[13] & IC[2]; 203 | endcase 204 | // di.DMA.HOLD = IC[14]; 205 | di.D1BUS.DMAW = 1; 206 | end 207 | 208 | 4'b1101: begin 209 | di.JPCW = ~IC[25] | COND; 210 | end 211 | 212 | 4'b1110: begin 213 | di.CTL.BTM = ~IC[27]; 214 | di.CTL.LPS = IC[27]; 215 | end 216 | 217 | 4'b1111: begin 218 | di.CTL.END = 1; 219 | di.CTL.EI = IC[27]; 220 | end 221 | 222 | default: ; 223 | endcase 224 | 225 | return di; 226 | endfunction 227 | 228 | function bit [31:0] ImmSext(input bit [31:0] val, input bit [1:0] mode); 229 | bit [31:0] res; 230 | 231 | //0: 8->32, 2: 25->32, 3: 19->32 232 | res[7:0] = val[7:0]; 233 | case (mode) 234 | 2'b10: res[18:8] = val[18:8]; 235 | 2'b11: res[18:8] = val[18:8]; 236 | default: res[18:8] = {11{val[7]}}; 237 | endcase 238 | case (mode) 239 | 2'b10: res[24:19] = val[24:19]; 240 | 2'b11: res[24:19] = {6{val[18]}}; 241 | default: res[24:19] = {6{val[7]}}; 242 | endcase 243 | case (mode) 244 | 2'b10: res[31:25] = {7{val[24]}}; 245 | 2'b11: res[31:25] = {7{val[18]}}; 246 | default: res[31:25] = {7{val[7]}}; 247 | endcase 248 | 249 | return res; 250 | endfunction 251 | 252 | function bit [8:0] DMAAddrAdd(input bit [2:0] mode, input bit dir); 253 | bit [8:0] res; 254 | 255 | res = 9'd0; 256 | // if (!dir) begin 257 | case (mode) 258 | 3'b000: res = 9'd0; 259 | 3'b001: res = 9'd4; 260 | 3'b010: res = 9'd8; 261 | 3'b011: res = 9'd16; 262 | 3'b100: res = 9'd32; 263 | 3'b101: res = 9'd64; 264 | 3'b110: res = 9'd128; 265 | 3'b111: res = 9'd256; 266 | endcase 267 | // end else begin 268 | // case (mode) 269 | // 3'b000: res = 7'd0; 270 | // 3'b001: res = 7'd1; 271 | // endcase 272 | // end 273 | 274 | return res; 275 | endfunction 276 | 277 | endpackage 278 | -------------------------------------------------------------------------------- /SCU/RAM.sv: -------------------------------------------------------------------------------- 1 | // synopsys translate_off 2 | `define SIM 3 | // synopsys translate_on 4 | 5 | module DSP_DPRAM 6 | #( 7 | parameter addr_width = 8, 8 | parameter data_width = 8, 9 | parameter mem_init_file = " ", 10 | parameter mem_sim_file = " " 11 | ) 12 | ( 13 | input CLK, 14 | 15 | input [addr_width-1:0] ADDR_A, 16 | input [data_width-1:0] DATA_A, 17 | input WREN_A, 18 | output [data_width-1:0] Q_A, 19 | 20 | input [addr_width-1:0] ADDR_B, 21 | input [data_width-1:0] DATA_B, 22 | input WREN_B, 23 | output [data_width-1:0] Q_B 24 | ); 25 | 26 | `ifdef SIM 27 | 28 | reg [data_width-1:0] MEM [2**addr_width]; 29 | 30 | initial begin 31 | $readmemh(mem_sim_file, MEM); 32 | end 33 | 34 | always @(posedge CLK) begin 35 | if (WREN_A) begin 36 | MEM[ADDR_A] <= DATA_A; 37 | end 38 | if (WREN_B) begin 39 | MEM[ADDR_B] <= DATA_B; 40 | end 41 | end 42 | 43 | assign Q_A = MEM[ADDR_A]; 44 | assign Q_B = MEM[ADDR_B]; 45 | 46 | `else 47 | 48 | wire [data_width-1:0] sub_wire0, sub_wire1; 49 | 50 | altsyncram altsyncram_component ( 51 | .address_a (ADDR_A), 52 | .address_b (ADDR_B), 53 | .clock0 (CLK), 54 | .clock1 (CLK), 55 | .data_a (DATA_A), 56 | .data_b (DATA_B), 57 | .wren_a (WREN_A), 58 | .wren_b (WREN_B), 59 | .q_a (sub_wire0), 60 | .q_b (sub_wire1), 61 | .aclr0 (1'b0), 62 | .aclr1 (1'b0), 63 | .addressstall_a (1'b0), 64 | .addressstall_b (1'b0), 65 | .byteena_a (1'b1), 66 | .byteena_b (1'b1), 67 | .clocken0 (1'b1), 68 | .clocken1 (1'b1), 69 | .clocken2 (1'b1), 70 | .clocken3 (1'b1), 71 | .eccstatus (), 72 | .rden_a (1'b1), 73 | .rden_b (1'b1)); 74 | defparam 75 | altsyncram_component.address_reg_b = "CLOCK1", 76 | altsyncram_component.clock_enable_input_a = "BYPASS", 77 | altsyncram_component.clock_enable_input_b = "BYPASS", 78 | // altsyncram_component.clock_enable_output_a = "BYPASS", 79 | altsyncram_component.clock_enable_output_b = "BYPASS", 80 | // altsyncram_component.indata_reg_b = "CLOCK1", 81 | altsyncram_component.intended_device_family = "Cyclone V", 82 | altsyncram_component.lpm_type = "altsyncram", 83 | altsyncram_component.numwords_a = 2**addr_width, 84 | altsyncram_component.numwords_b = 2**addr_width, 85 | altsyncram_component.operation_mode = "DUAL_PORT", 86 | // altsyncram_component.outdata_aclr_a = "NONE", 87 | altsyncram_component.outdata_aclr_b = "NONE", 88 | // altsyncram_component.outdata_reg_a = "UNREGISTERED", 89 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 90 | altsyncram_component.power_up_uninitialized = "FALSE", 91 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 92 | altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", 93 | altsyncram_component.widthad_a = addr_width, 94 | altsyncram_component.widthad_b = addr_width, 95 | altsyncram_component.width_a = data_width, 96 | altsyncram_component.width_b = data_width, 97 | altsyncram_component.width_byteena_a = 1, 98 | // altsyncram_component.width_byteena_b = 1, 99 | altsyncram_component.init_file = mem_init_file; 100 | 101 | 102 | assign Q_A = sub_wire0; 103 | assign Q_B = sub_wire1; 104 | 105 | `endif 106 | 107 | endmodule 108 | 109 | 110 | module DSP_PRG_RAM 111 | #( 112 | parameter addr_width = 8, 113 | parameter data_width = 8, 114 | parameter mem_init_file = " ", 115 | parameter mem_sim_file = " " 116 | ) 117 | ( 118 | input CLK, 119 | 120 | input [addr_width-1:0] ADDR, 121 | input [data_width-1:0] DATA, 122 | input WREN, 123 | output [data_width-1:0] Q 124 | ); 125 | 126 | `ifdef SIM 127 | 128 | reg [data_width-1:0] MEM [2**addr_width]; 129 | 130 | initial begin 131 | $readmemh(mem_sim_file, MEM); 132 | end 133 | 134 | always @(posedge CLK) begin 135 | if (WREN) begin 136 | MEM[ADDR] <= DATA; 137 | end 138 | end 139 | 140 | assign Q = MEM[ADDR]; 141 | 142 | //`elsif DEBUG 143 | // 144 | // wire [data_width-1:0] sub_wire0; 145 | // 146 | // altdpram altdpram_component ( 147 | // .data (DATA), 148 | // .inclock (CLK), 149 | // .rdaddress (ADDR), 150 | // .wraddress (ADDR), 151 | // .wren (WREN), 152 | // .q (sub_wire0), 153 | // .aclr (1'b0), 154 | // .byteena (1'b1), 155 | // .inclocken (1'b1), 156 | // .rdaddressstall (1'b0), 157 | // .rden (1'b1), 158 | //// .sclr (1'b0), 159 | // .wraddressstall (1'b0)); 160 | // defparam 161 | // altdpram_component.indata_aclr = "OFF", 162 | // altdpram_component.indata_reg = "INCLOCK", 163 | // altdpram_component.intended_device_family = "Cyclone V", 164 | // altdpram_component.lpm_type = "altdpram", 165 | // altdpram_component.outdata_aclr = "OFF", 166 | // altdpram_component.outdata_reg = "UNREGISTERED", 167 | // altdpram_component.ram_block_type = "MLAB", 168 | // altdpram_component.rdaddress_aclr = "OFF", 169 | // altdpram_component.rdaddress_reg = "UNREGISTERED", 170 | // altdpram_component.rdcontrol_aclr = "OFF", 171 | // altdpram_component.rdcontrol_reg = "UNREGISTERED", 172 | // altdpram_component.read_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE", 173 | // altdpram_component.width = data_width, 174 | // altdpram_component.widthad = addr_width, 175 | // altdpram_component.width_byteena = 1, 176 | // altdpram_component.wraddress_aclr = "OFF", 177 | // altdpram_component.wraddress_reg = "INCLOCK", 178 | // altdpram_component.wrcontrol_aclr = "OFF", 179 | // altdpram_component.wrcontrol_reg = "INCLOCK"; 180 | // 181 | // assign Q = sub_wire0; 182 | 183 | `else 184 | 185 | wire [data_width-1:0] sub_wire0; 186 | 187 | altsyncram altsyncram_component ( 188 | .address_a (ADDR), 189 | .clock0 (CLK), 190 | .data_a (DATA), 191 | .wren_a (WREN), 192 | .q_a (sub_wire0), 193 | .aclr0 (1'b0), 194 | .aclr1 (1'b0), 195 | .address_b (1'b1), 196 | .addressstall_a (1'b0), 197 | .addressstall_b (1'b0), 198 | .byteena_a (1'b1), 199 | .byteena_b (1'b1), 200 | .clock1 (1'b1), 201 | .clocken0 (1'b1), 202 | .clocken1 (1'b1), 203 | .clocken2 (1'b1), 204 | .clocken3 (1'b1), 205 | .data_b (1'b1), 206 | .eccstatus (), 207 | .q_b (), 208 | .rden_a (1'b1), 209 | .rden_b (1'b1), 210 | .wren_b (1'b0)); 211 | 212 | defparam 213 | altsyncram_component.clock_enable_input_a = "BYPASS", 214 | altsyncram_component.clock_enable_output_a = "BYPASS", 215 | altsyncram_component.intended_device_family = "Cyclone V", 216 | altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO", 217 | altsyncram_component.lpm_type = "altsyncram", 218 | altsyncram_component.numwords_a = 2**addr_width, 219 | altsyncram_component.operation_mode = "SINGLE_PORT", 220 | altsyncram_component.outdata_aclr_a = "NONE", 221 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 222 | altsyncram_component.power_up_uninitialized = "FALSE", 223 | altsyncram_component.ram_block_type = "M10K", 224 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 225 | altsyncram_component.widthad_a = addr_width, 226 | altsyncram_component.width_a = data_width, 227 | altsyncram_component.width_byteena_a = 1, 228 | altsyncram_component.init_file = mem_init_file; 229 | 230 | assign Q = sub_wire0; 231 | 232 | `endif 233 | 234 | endmodule 235 | 236 | 237 | module DSP_DATA_RAM 238 | #( 239 | parameter addr_width = 8, 240 | parameter data_width = 8, 241 | parameter mem_init_file = " ", 242 | parameter mem_sim_file = " " 243 | ) 244 | ( 245 | input CLK, 246 | 247 | input [addr_width-1:0] ADDR, 248 | input [data_width-1:0] DATA, 249 | input WREN, 250 | output [data_width-1:0] Q 251 | ); 252 | 253 | `ifdef SIM 254 | 255 | reg [data_width-1:0] MEM [2**addr_width]; 256 | 257 | initial begin 258 | $readmemh(mem_sim_file, MEM); 259 | end 260 | 261 | always @(posedge CLK) begin 262 | if (WREN) begin 263 | MEM[ADDR] <= DATA; 264 | end 265 | end 266 | 267 | assign Q = MEM[ADDR]; 268 | 269 | `else 270 | 271 | wire [data_width-1:0] sub_wire0; 272 | 273 | altdpram altdpram_component ( 274 | .data (DATA), 275 | .inclock (CLK), 276 | .rdaddress (ADDR), 277 | .wraddress (ADDR), 278 | .wren (WREN), 279 | .q (sub_wire0), 280 | .aclr (1'b0), 281 | .byteena (1'b1), 282 | .inclocken (1'b1), 283 | .rdaddressstall (1'b0), 284 | .rden (1'b1), 285 | // .sclr (1'b0), 286 | .wraddressstall (1'b0)); 287 | defparam 288 | altdpram_component.indata_aclr = "OFF", 289 | altdpram_component.indata_reg = "INCLOCK", 290 | altdpram_component.intended_device_family = "Cyclone V", 291 | altdpram_component.lpm_type = "altdpram", 292 | altdpram_component.outdata_aclr = "OFF", 293 | altdpram_component.outdata_reg = "UNREGISTERED", 294 | altdpram_component.ram_block_type = "MLAB", 295 | altdpram_component.rdaddress_aclr = "OFF", 296 | altdpram_component.rdaddress_reg = "UNREGISTERED", 297 | altdpram_component.rdcontrol_aclr = "OFF", 298 | altdpram_component.rdcontrol_reg = "UNREGISTERED", 299 | altdpram_component.read_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE", 300 | altdpram_component.width = data_width, 301 | altdpram_component.widthad = addr_width, 302 | altdpram_component.width_byteena = 1, 303 | altdpram_component.wraddress_aclr = "OFF", 304 | altdpram_component.wraddress_reg = "INCLOCK", 305 | altdpram_component.wrcontrol_aclr = "OFF", 306 | altdpram_component.wrcontrol_reg = "INCLOCK"; 307 | 308 | assign Q = sub_wire0; 309 | 310 | `endif 311 | 312 | endmodule 313 | 314 | 315 | module SCU_DMA_FIFO ( 316 | CLK, 317 | DATA, 318 | WRREQ, 319 | RDREQ, 320 | Q, 321 | EMPTY, 322 | FULL); 323 | 324 | input CLK; 325 | input [36:0] DATA; 326 | input RDREQ; 327 | input WRREQ; 328 | output EMPTY; 329 | output FULL; 330 | output [36:0] Q; 331 | 332 | wire sub_wire0; 333 | wire sub_wire1; 334 | wire [36:0] sub_wire2; 335 | wire EMPTY = sub_wire0; 336 | wire FULL = sub_wire1; 337 | wire [36:0] Q = sub_wire2[36:0]; 338 | 339 | scfifo scfifo_component ( 340 | .clock (CLK), 341 | .data (DATA), 342 | .rdreq (RDREQ), 343 | .wrreq (WRREQ), 344 | .empty (sub_wire0), 345 | .full (sub_wire1), 346 | .q (sub_wire2), 347 | .aclr (), 348 | .almost_empty (), 349 | .almost_full (), 350 | .sclr (), 351 | .usedw ()); 352 | defparam 353 | scfifo_component.add_ram_output_register = "OFF", 354 | scfifo_component.intended_device_family = "Cyclone V", 355 | scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=MLAB", 356 | scfifo_component.lpm_numwords = 8, 357 | scfifo_component.lpm_showahead = "ON", 358 | scfifo_component.lpm_type = "scfifo", 359 | scfifo_component.lpm_width = 37, 360 | scfifo_component.lpm_widthu = 3, 361 | scfifo_component.overflow_checking = "OFF", 362 | scfifo_component.underflow_checking = "OFF", 363 | scfifo_component.use_eab = "ON"; 364 | 365 | endmodule 366 | 367 | module SCU_DMA_FIFO2 ( 368 | input CLK, 369 | input [36:0] DATA, 370 | input WRREQ, 371 | input RDREQ, 372 | output [36:0] Q, 373 | output EMPTY, 374 | output FULL 375 | ); 376 | 377 | wire [36: 0] sub_wire0; 378 | bit [ 2: 0] RADDR; 379 | bit [ 2: 0] WADDR; 380 | bit [ 3: 0] AMOUNT; 381 | 382 | always @(posedge CLK) begin 383 | if (WRREQ && !AMOUNT[3]) begin 384 | WADDR <= WADDR + 3'd1; 385 | end 386 | if (RDREQ && AMOUNT) begin 387 | RADDR <= RADDR + 3'd1; 388 | end 389 | 390 | if (WRREQ && !RDREQ && !AMOUNT[3]) begin 391 | AMOUNT <= AMOUNT + 4'd1; 392 | end else if (!WRREQ && RDREQ && AMOUNT) begin 393 | AMOUNT <= AMOUNT - 4'd1; 394 | end 395 | end 396 | assign EMPTY = ~|AMOUNT; 397 | assign FULL = AMOUNT[3]; 398 | 399 | altdpram altdpram_component ( 400 | .data (DATA), 401 | .inclock (CLK), 402 | .rdaddress (RADDR), 403 | .wraddress (WADDR), 404 | .wren (WRREQ), 405 | .q (sub_wire0), 406 | .aclr (1'b0), 407 | .byteena (1'b1), 408 | .inclocken (1'b1), 409 | .rdaddressstall (1'b0), 410 | .rden (1'b1), 411 | // .sclr (1'b0), 412 | .wraddressstall (1'b0)); 413 | defparam 414 | altdpram_component.indata_aclr = "OFF", 415 | altdpram_component.indata_reg = "INCLOCK", 416 | altdpram_component.intended_device_family = "Cyclone V", 417 | altdpram_component.lpm_type = "altdpram", 418 | altdpram_component.outdata_aclr = "OFF", 419 | altdpram_component.outdata_reg = "UNREGISTERED", 420 | altdpram_component.ram_block_type = "MLAB", 421 | altdpram_component.rdaddress_aclr = "OFF", 422 | altdpram_component.rdaddress_reg = "UNREGISTERED", 423 | altdpram_component.rdcontrol_aclr = "OFF", 424 | altdpram_component.rdcontrol_reg = "UNREGISTERED", 425 | altdpram_component.read_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE", 426 | altdpram_component.width = 37, 427 | altdpram_component.widthad = 3, 428 | altdpram_component.width_byteena = 1, 429 | altdpram_component.wraddress_aclr = "OFF", 430 | altdpram_component.wraddress_reg = "INCLOCK", 431 | altdpram_component.wrcontrol_aclr = "OFF", 432 | altdpram_component.wrcontrol_reg = "INCLOCK"; 433 | 434 | assign Q = sub_wire0; 435 | 436 | endmodule 437 | 438 | module SCU_CBUS_CACHE 439 | ( 440 | input CLK, 441 | 442 | input [ 2:0] WADDR, 443 | input [31:0] DATA, 444 | input WREN, 445 | input [ 2:0] RADDR, 446 | output [31:0] Q 447 | ); 448 | 449 | `ifdef SIM 450 | 451 | reg [31:0] MEM [8]; 452 | 453 | always @(posedge CLK) begin 454 | if (WREN) begin 455 | MEM[WADDR] <= DATA; 456 | end 457 | end 458 | 459 | assign Q = MEM[RADDR]; 460 | 461 | `else 462 | 463 | wire [31:0] sub_wire0; 464 | 465 | altdpram altdpram_component ( 466 | .data (DATA), 467 | .inclock (CLK), 468 | .rdaddress (RADDR), 469 | .wraddress (WADDR), 470 | .wren (WREN), 471 | .q (sub_wire0), 472 | .aclr (1'b0), 473 | .byteena (1'b1), 474 | .inclocken (1'b1), 475 | .rdaddressstall (1'b0), 476 | .rden (1'b1), 477 | // .sclr (1'b0), 478 | .wraddressstall (1'b0)); 479 | defparam 480 | altdpram_component.indata_aclr = "OFF", 481 | altdpram_component.indata_reg = "INCLOCK", 482 | altdpram_component.intended_device_family = "Cyclone V", 483 | altdpram_component.lpm_type = "altdpram", 484 | altdpram_component.outdata_aclr = "OFF", 485 | altdpram_component.outdata_reg = "UNREGISTERED", 486 | altdpram_component.ram_block_type = "MLAB", 487 | altdpram_component.rdaddress_aclr = "OFF", 488 | altdpram_component.rdaddress_reg = "UNREGISTERED", 489 | altdpram_component.rdcontrol_aclr = "OFF", 490 | altdpram_component.rdcontrol_reg = "UNREGISTERED", 491 | altdpram_component.read_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE", 492 | altdpram_component.width = 32, 493 | altdpram_component.widthad = 3, 494 | altdpram_component.width_byteena = 1, 495 | altdpram_component.wraddress_aclr = "OFF", 496 | altdpram_component.wraddress_reg = "INCLOCK", 497 | altdpram_component.wrcontrol_aclr = "OFF", 498 | altdpram_component.wrcontrol_reg = "INCLOCK"; 499 | 500 | assign Q = sub_wire0; 501 | 502 | `endif 503 | 504 | endmodule 505 | -------------------------------------------------------------------------------- /SCU/SCU DSP.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/SCU/SCU DSP.xlsx -------------------------------------------------------------------------------- /SCU/SCU.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) DSP_PKG.sv ] 2 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) RAM.sv ] 3 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) DSP.sv ] 4 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU_PKG.sv ] 5 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU.sv ] 6 | -------------------------------------------------------------------------------- /SCU/SCU.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 20:16:21 November 28, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "20:16:21 November 28, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "SCU" 31 | -------------------------------------------------------------------------------- /SCU/SCU.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 20:16:21 November 28, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # SCU_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEMA6F31I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY SCU 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:16:21 NOVEMBER 28, 2020" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name SYSTEMVERILOG_FILE SCU.sv 50 | set_global_assignment -name SYSTEMVERILOG_FILE SCU_PKG.sv 51 | set_global_assignment -name SYSTEMVERILOG_FILE DSP.sv 52 | set_global_assignment -name SYSTEMVERILOG_FILE RAM.sv 53 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 54 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 55 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 56 | set_global_assignment -name SYSTEMVERILOG_FILE SCU_tb.sv 57 | set_global_assignment -name SYSTEMVERILOG_FILE DSP_PKG.sv 58 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /SCU/SCU_PKG.sv: -------------------------------------------------------------------------------- 1 | package SCU_PKG; 2 | 3 | typedef bit [31:0] DxR_t; //R/W,25FE0000,25FE0020,25FE0040 4 | parameter bit [31:0] DxR_WMASK = 32'h07FFFFFF; 5 | parameter bit [31:0] DxR_RMASK = 32'h07FFFFFF; 6 | 7 | typedef bit [31:0] DxW_t; //R/W,25FE0004,25FE0024,25FE0044 8 | parameter bit [31:0] DxW_WMASK = 32'h07FFFFFF; 9 | parameter bit [31:0] DxW_RMASK = 32'h07FFFFFF; 10 | 11 | typedef bit [31:0] DxC_t; //R/W,25FE0008,25FE0028,25FE0048 12 | parameter bit [31:0] D0C_WMASK = 32'h000FFFFF; 13 | parameter bit [31:0] D0C_RMASK = 32'h000FFFFF; 14 | parameter bit [31:0] D12C_WMASK = 32'h00000FFF; 15 | parameter bit [31:0] D12C_RMASK = 32'h00000FFF; 16 | 17 | typedef struct packed //W,25FE000C,25FE002C,25FE004C 18 | { 19 | bit [22: 0] UNUSED; 20 | bit DRA; //W 21 | bit [ 4: 0] UNUSED2; 22 | bit [ 2: 0] DWA; //W 23 | } DxAD_t; 24 | parameter bit [31:0] DxAD_WMASK = 32'h00000107; 25 | parameter bit [31:0] DxAD_RMASK = 32'h00000000; 26 | parameter bit [31:0] DxAD_INIT = 32'h00000101; 27 | 28 | typedef struct packed //W,25FE0010,25FE0030,25FE0050 29 | { 30 | bit [22: 0] UNUSED; 31 | bit EN; //W 32 | bit [ 6: 0] UNUSED2; 33 | bit GO; //W 34 | } DxEN_t; 35 | parameter bit [31:0] DxEN_WMASK = 32'h00000101; 36 | parameter bit [31:0] DxEN_RMASK = 32'h00000000; 37 | parameter bit [31:0] DxEN_INIT = 32'h00000000; 38 | 39 | typedef struct packed //W,25FE0014,25FE0034,25FE0054 40 | { 41 | bit [ 6: 0] UNUSED; 42 | bit MOD; //W 43 | bit [ 6: 0] UNUSED2; 44 | bit RUP; //W 45 | bit [ 6: 0] UNUSED3; 46 | bit WUP; //W 47 | bit [ 4: 0] UNUSED4; 48 | bit [ 2: 0] FT; //W 49 | } DxMD_t; 50 | parameter bit [31:0] DxMD_WMASK = 32'h01010107; 51 | parameter bit [31:0] DxMD_RMASK = 32'h00000000; 52 | parameter bit [31:0] DxMD_INIT = 32'h00000007; 53 | 54 | typedef struct packed //W,25FE0060 55 | { 56 | bit [30: 0] UNUSED; 57 | bit STOP; //W 58 | } DSTP_t; 59 | parameter bit [31:0] DSTP_WMASK = 32'h00000001; 60 | parameter bit [31:0] DSTP_RMASK = 32'h00000000; 61 | parameter bit [31:0] DSTP_INIT = 32'h00000000; 62 | 63 | typedef struct packed //R,25FE007C 64 | { 65 | bit [ 8: 0] UNUSED; 66 | bit DACSD; //R 67 | bit DACSB; //R 68 | bit DACSA; //R 69 | bit [ 1: 0] UNUSED2; 70 | bit D1BK; //R 71 | bit D0BK; //R 72 | bit [ 1: 0] UNUSED3; 73 | bit D2WT; //R 74 | bit D2MV; //R 75 | bit [ 1: 0] UNUSED4; 76 | bit D1WT; //R 77 | bit D1MV; //R 78 | bit [ 1: 0] UNUSED5; 79 | bit D0WT; //R 80 | bit D0MV; //R 81 | bit [ 1: 0] UNUSED6; 82 | bit DDWT; //R 83 | bit DDMV; //R 84 | } DSTA_t; 85 | parameter bit [31:0] DSTA_WMASK = 32'h00000000; 86 | parameter bit [31:0] DSTA_RMASK = 32'h00733333; 87 | parameter bit [31:0] DSTA_INIT = 32'h00000000; 88 | 89 | typedef struct packed //R/W,25FE0080 90 | { 91 | bit [ 4: 0] UNUSED; 92 | bit PR; //W 93 | bit EP; //W 94 | bit UNUSED2; 95 | bit T0; //R 96 | bit S; //R 97 | bit Z; //R 98 | bit C; //R 99 | bit V; //R 100 | bit E; //R 101 | bit ES; //W 102 | bit EX; //R/W 103 | bit LE; //W 104 | bit [ 6: 0] UNUSED3; 105 | bit [ 7: 0] P; //R/W 106 | } PPAF_t; 107 | parameter bit [31:0] PPAF_WMASK = 32'h060380FF; 108 | parameter bit [31:0] PPAF_RMASK = 32'h00FD80FF; 109 | parameter bit [31:0] PPAF_INIT = 32'h00000000; 110 | 111 | typedef bit [31:0] PPD_t; //W,25FE0084 112 | parameter bit [31:0] PPD_WMASK = 32'hFFFFFFFF; 113 | parameter bit [31:0] PPD_RMASK = 32'h00000000; 114 | 115 | typedef struct packed //W,25FE0088 116 | { 117 | bit [23: 0] UNUSED; 118 | bit [ 7: 0] RA; //W 119 | } PDA_t; 120 | parameter bit [31:0] PDA_WMASK = 32'h000000FF; 121 | parameter bit [31:0] PDA_RMASK = 32'h00000000; 122 | parameter bit [31:0] PDA_INIT = 32'h00000000; 123 | 124 | typedef bit [31:0] PDD_t; //W/R,25FE008C 125 | parameter bit [31:0] PDD_WMASK = 32'hFFFFFFFF; 126 | parameter bit [31:0] PDD_RMASK = 32'hFFFFFFFF; 127 | 128 | typedef bit [31:0] T0C_t; //W,25FE0090 129 | parameter bit [31:0] T0C_WMASK = 32'h000003FF; 130 | parameter bit [31:0] T0C_RMASK = 32'h00000000; 131 | 132 | typedef bit [31:0] T1S_t; //W,25FE0094 133 | parameter bit [31:0] T1S_WMASK = 32'h000001FF; 134 | parameter bit [31:0] T1S_RMASK = 32'h00000000; 135 | 136 | typedef struct packed //W,25FE0098 137 | { 138 | bit [22: 0] UNUSED; 139 | bit MD; //W 140 | bit [ 6: 0] UNUSED3; 141 | bit ENB; //W 142 | } T1MD_t; 143 | parameter bit [31:0] T1MD_WMASK = 32'h00000101; 144 | parameter bit [31:0] T1MD_RMASK = 32'h00000000; 145 | parameter bit [31:0] T1MD_INIT = 32'h00000000; 146 | 147 | typedef struct packed //W,25FE00A0 148 | { 149 | bit [15: 0] UNUSED; 150 | bit MS15; //W 151 | bit UNUSED2; 152 | bit MS13; //W 153 | bit MS12; //W 154 | bit MS11; //W 155 | bit MS10; //W 156 | bit MS9; //W 157 | bit MS8; //W 158 | bit MS7; //W 159 | bit MS6; //W 160 | bit MS5; //W 161 | bit MS4; //W 162 | bit MS3; //W 163 | bit MS2; //W 164 | bit MS1; //W 165 | bit MS0; //W 166 | } IMS_t; 167 | parameter bit [31:0] IMS_WMASK = 32'h0000BFFF; 168 | parameter bit [31:0] IMS_RMASK = 32'h00000000; 169 | parameter bit [31:0] IMS_INIT = 32'h0000BFFF; 170 | 171 | typedef struct packed //R/W,25FE00A4 172 | { 173 | bit [15: 0] EIS; //R/W 174 | bit [ 1: 0] UNUSED; 175 | bit SDEI; //R/W 176 | bit DII; //R/W 177 | bit D0EI; //R/W 178 | bit D1EI; //R/W 179 | bit D2EI; //R/W 180 | bit PADI; //R/W 181 | bit SMI; //R/W 182 | bit SRI; //R/W 183 | bit DSPEI; //R/W 184 | bit T1I; //R/W 185 | bit T0I; //R/W 186 | bit HBII; //R/W 187 | bit VBOI; //R/W 188 | bit VBII; //R/W 189 | } IST_t; 190 | parameter bit [31:0] IST_WMASK = 32'hFFFF3FFF; 191 | parameter bit [31:0] IST_RMASK = 32'hFFFF3FFF; 192 | parameter bit [31:0] IST_INIT = 32'h00000000; 193 | 194 | typedef bit AIACK_t; //R/W,25FE00A8 195 | parameter bit [31:0] AIACK_WMASK = 32'h00000001; 196 | parameter bit [31:0] AIACK_RMASK = 32'h00000001; 197 | parameter bit [31:0] AIACK_INIT = 32'h00000000; 198 | 199 | typedef struct packed //W,25FE00B0 200 | { 201 | bit A0PRD; //W 202 | bit A0WPC; //W 203 | bit A0RPC; //W 204 | bit A0EWT; //W 205 | bit [ 3: 0] A0BW; //W 206 | bit [ 3: 0] A0NW; //W 207 | bit [ 1: 0] A0LN; //W 208 | bit UNUSED; 209 | bit A0SZ; //W 210 | bit A1PRD; //W 211 | bit A1WPC; //W 212 | bit A1RPC; //W 213 | bit A1EWT; //W 214 | bit [ 3: 0] A1BW; //W 215 | bit [ 3: 0] A1NW; //W 216 | bit [ 1: 0] A1LN; //W 217 | bit UNUSED2; 218 | bit A1SZ; //W 219 | } ASR0_t; 220 | parameter bit [31:0] ASR0_WMASK = 32'hFFFDFFFD; 221 | parameter bit [31:0] ASR0_RMASK = 32'h00000000; 222 | parameter bit [31:0] ASR0_INIT = 32'h00000000; 223 | 224 | typedef struct packed //W,25FE00B4 225 | { 226 | bit A2PRD; //W 227 | bit A2WPC; //W 228 | bit A2RPC; //W 229 | bit A2EWT; //W 230 | bit [ 7: 0] UNUSED; 231 | bit [ 1: 0] A2LN; //W 232 | bit UNUSED2; 233 | bit A2SZ; //W 234 | bit A3PRD; //W 235 | bit A3WPC; //W 236 | bit A3RPC; //W 237 | bit A3EWT; //W 238 | bit [ 3: 0] A3BW; //W 239 | bit [ 3: 0] A3NW; //W 240 | bit [ 1: 0] A3LN; //W 241 | bit UNUSED3; 242 | bit A3SZ; //W 243 | } ASR1_t; 244 | parameter bit [31:0] ASR1_WMASK = 32'hF00DFFFD; 245 | parameter bit [31:0] ASR1_RMASK = 32'h00000000; 246 | parameter bit [31:0] ASR1_INIT = 32'h00000000; 247 | 248 | typedef struct packed //W,25FE00B8 249 | { 250 | bit [26: 0] UNUSED; 251 | bit ARFEN; //W 252 | bit [ 3: 0] ARWT; //W 253 | } AREF_t; 254 | parameter bit [31:0] AREF_WMASK = 32'h0000001F; 255 | parameter bit [31:0] AREF_RMASK = 32'h00000000; 256 | parameter bit [31:0] AREF_INIT = 32'h00000000; 257 | 258 | typedef bit RSEL_t; //R/W,25FE00C4 259 | parameter bit [31:0] RSEL_WMASK = 32'h00000001; 260 | parameter bit [31:0] RSEL_RMASK = 32'h00000001; 261 | parameter bit RSEL_INIT = 1'h0; 262 | 263 | typedef bit [31:0] VER_t; //R,25FE00C8 264 | parameter bit [31:0] VER_WMASK = 32'h00000000; 265 | parameter bit [31:0] VER_RMASK = 32'h0000000F; 266 | parameter bit [31:0] VER_INIT = 32'h00000000; 267 | 268 | endpackage 269 | -------------------------------------------------------------------------------- /SCU/SCU_tb.sv: -------------------------------------------------------------------------------- 1 | module SCU_tb; 2 | 3 | import SCU_PKG::*; 4 | 5 | bit CLK; 6 | bit RST_N; 7 | bit CE_R, CE_F; 8 | 9 | bit [1:0] SCU_A; 10 | bit [31:0] SCU_DO; 11 | bit [31:0] SCU_DI; 12 | bit [3:0] SCU_WR; 13 | bit SCU_RD; 14 | 15 | bit [31:0] RAM_DO, RAM_DI; 16 | bit RAM_WE; 17 | 18 | //clock generation 19 | always #5 CLK = ~CLK; 20 | 21 | //reset generation 22 | initial begin 23 | RST_N = 0; 24 | #12 RST_N = 1; 25 | end 26 | 27 | initial begin 28 | SCU_A = '0; 29 | SCU_DI = '0; 30 | SCU_WR = 0; 31 | 32 | #20 SCU_A = 2'h2; 33 | SCU_DI = 32'h00000040; 34 | SCU_WR = 1; 35 | #20 SCU_WR = 0; 36 | 37 | #20 SCU_A = 2'h3; 38 | SCU_DI = 32'h00000000; 39 | SCU_WR = 1; 40 | #20 SCU_WR = 0; 41 | 42 | #20 SCU_A = 2'h3; 43 | SCU_DI = 32'h00000000; 44 | SCU_WR = 1; 45 | #20 SCU_WR = 0; 46 | 47 | #20 SCU_A = 2'h0; 48 | SCU_DI = 32'h00010000; 49 | SCU_WR = 1; 50 | #20 SCU_WR = 0; 51 | end 52 | 53 | always @(posedge CLK) begin 54 | CE_R <= ~CE_R; 55 | end 56 | assign CE_F = ~CE_R; 57 | 58 | SCU scu 59 | ( 60 | .CLK(CLK), 61 | .RST_N(RST_N), 62 | .CE_R(CE_R), 63 | .CE_F(CE_F), 64 | 65 | .A(SCU_A), 66 | .DI(SCU_DI), 67 | .DO(SCU_DO), 68 | .WR(SCU_WR), 69 | .RD(SCU_RD), 70 | 71 | .IRQ() 72 | 73 | ); 74 | 75 | endmodule 76 | -------------------------------------------------------------------------------- /SCU/prg.txt: -------------------------------------------------------------------------------- 1 | 00001C00 2 | 00001D00 3 | 98000000 4 | C0008001 5 | D3400004 6 | 00000000 7 | C0008101 8 | D3400007 9 | 00000000 10 | 00001C00 11 | 00021D00 12 | 02494000 13 | 01000000 14 | 18003209 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | F8000000 -------------------------------------------------------------------------------- /SCU/transcript: -------------------------------------------------------------------------------- 1 | # do temp_simlib_comp.tmp 2 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 3 | # Start time: 13:36:04 on Nov 30,2020 4 | # vlog -work cyclonev_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/mentor/cyclonev_atoms_ncrypt.v 5 | # 6 | # Top level modules: 7 | # End time: 13:36:06 on Nov 30,2020, Elapsed time: 0:00:02 8 | # Errors: 0, Warnings: 0 9 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 10 | # Start time: 13:36:06 on Nov 30,2020 11 | # vlog -work cyclonev_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/mentor/cyclonev_hmi_atoms_ncrypt.v 12 | # 13 | # Top level modules: 14 | # End time: 13:36:07 on Nov 30,2020, Elapsed time: 0:00:01 15 | # Errors: 0, Warnings: 0 16 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 17 | # Start time: 13:36:08 on Nov 30,2020 18 | # vlog -work cyclonev_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/cyclonev_atoms.v 19 | # -- Compiling UDP CYCLONEV_PRIM_DFFE 20 | # -- Compiling UDP CYCLONEV_PRIM_DFFEAS 21 | # -- Compiling UDP CYCLONEV_PRIM_DFFEAS_HIGH 22 | # -- Compiling module cyclonev_dffe 23 | # -- Compiling module cyclonev_mux21 24 | # -- Compiling module cyclonev_mux41 25 | # -- Compiling module cyclonev_and1 26 | # -- Compiling module cyclonev_and16 27 | # -- Compiling module cyclonev_bmux21 28 | # -- Compiling module cyclonev_b17mux21 29 | # -- Compiling module cyclonev_nmux21 30 | # -- Compiling module cyclonev_b5mux21 31 | # -- Compiling module cyclonev_ff 32 | # -- Compiling module cyclonev_lcell_comb 33 | # -- Compiling module cyclonev_routing_wire 34 | # -- Compiling module cyclonev_ram_block 35 | # -- Compiling module cyclonev_mlab_cell 36 | # -- Compiling module cyclonev_io_ibuf 37 | # -- Compiling module cyclonev_io_obuf 38 | # -- Compiling module cyclonev_ddio_out 39 | # -- Compiling module cyclonev_ddio_oe 40 | # -- Compiling module cyclonev_ddio_in 41 | # -- Compiling module cyclonev_io_pad 42 | # -- Compiling module cyclonev_pseudo_diff_out 43 | # -- Compiling module cyclonev_bias_logic 44 | # -- Compiling module cyclonev_bias_generator 45 | # -- Compiling module cyclonev_bias_block 46 | # -- Compiling module cyclonev_clk_phase_select 47 | # -- Compiling module cyclonev_clkena 48 | # -- Compiling module cyclonev_clkselect 49 | # -- Compiling module cyclonev_delay_chain 50 | # -- Compiling module cyclonev_dll_offset_ctrl 51 | # -- Compiling module cyclonev_dll 52 | # -- Compiling module cyclonev_dqs_config 53 | # -- Compiling module cyclonev_dqs_delay_chain 54 | # -- Compiling module cyclonev_dqs_enable_ctrl 55 | # -- Compiling module cyclonev_duty_cycle_adjustment 56 | # -- Compiling module cyclonev_fractional_pll 57 | # -- Compiling module cyclonev_half_rate_input 58 | # -- Compiling module cyclonev_input_phase_alignment 59 | # -- Compiling module cyclonev_io_clock_divider 60 | # -- Compiling module cyclonev_io_config 61 | # -- Compiling module cyclonev_leveling_delay_chain 62 | # -- Compiling module cyclonev_pll_dll_output 63 | # -- Compiling module cyclonev_pll_dpa_output 64 | # -- Compiling module cyclonev_pll_extclk_output 65 | # -- Compiling module cyclonev_pll_lvds_output 66 | # -- Compiling module cyclonev_pll_output_counter 67 | # -- Compiling module cyclonev_pll_reconfig 68 | # -- Compiling module cyclonev_pll_refclk_select 69 | # -- Compiling module cyclonev_termination_logic 70 | # -- Compiling module cyclonev_termination 71 | # -- Compiling module cyclonev_asmiblock 72 | # -- Compiling module cyclonev_chipidblock 73 | # -- Compiling module cyclonev_controller 74 | # -- Compiling module cyclonev_crcblock 75 | # -- Compiling module cyclonev_jtag 76 | # -- Compiling module cyclonev_prblock 77 | # -- Compiling module cyclonev_rublock 78 | # -- Compiling module cyclonev_tsdblock 79 | # -- Compiling module cyclonev_read_fifo 80 | # -- Compiling module cyclonev_read_fifo_read_enable 81 | # -- Compiling module cyclonev_phy_clkbuf 82 | # -- Compiling module cyclonev_ir_fifo_userdes 83 | # -- Compiling module cyclonev_read_fifo_read_clock_select 84 | # -- Compiling module cyclonev_lfifo 85 | # -- Compiling module cyclonev_vfifo 86 | # -- Compiling module cyclonev_mac 87 | # -- Compiling module cyclonev_mem_phy 88 | # -- Compiling module cyclonev_oscillator 89 | # -- Compiling module cyclonev_hps_interface_fpga2sdram 90 | # 91 | # Top level modules: 92 | # cyclonev_dffe 93 | # cyclonev_mux41 94 | # cyclonev_and1 95 | # cyclonev_and16 96 | # cyclonev_bmux21 97 | # cyclonev_b17mux21 98 | # cyclonev_nmux21 99 | # cyclonev_b5mux21 100 | # cyclonev_ff 101 | # cyclonev_lcell_comb 102 | # cyclonev_routing_wire 103 | # cyclonev_ram_block 104 | # cyclonev_mlab_cell 105 | # cyclonev_io_ibuf 106 | # cyclonev_io_obuf 107 | # cyclonev_ddio_out 108 | # cyclonev_ddio_oe 109 | # cyclonev_ddio_in 110 | # cyclonev_io_pad 111 | # cyclonev_pseudo_diff_out 112 | # cyclonev_bias_block 113 | # cyclonev_clk_phase_select 114 | # cyclonev_clkena 115 | # cyclonev_clkselect 116 | # cyclonev_delay_chain 117 | # cyclonev_dll_offset_ctrl 118 | # cyclonev_dll 119 | # cyclonev_dqs_config 120 | # cyclonev_dqs_delay_chain 121 | # cyclonev_dqs_enable_ctrl 122 | # cyclonev_duty_cycle_adjustment 123 | # cyclonev_fractional_pll 124 | # cyclonev_half_rate_input 125 | # cyclonev_input_phase_alignment 126 | # cyclonev_io_clock_divider 127 | # cyclonev_io_config 128 | # cyclonev_leveling_delay_chain 129 | # cyclonev_pll_dll_output 130 | # cyclonev_pll_dpa_output 131 | # cyclonev_pll_extclk_output 132 | # cyclonev_pll_lvds_output 133 | # cyclonev_pll_output_counter 134 | # cyclonev_pll_reconfig 135 | # cyclonev_pll_refclk_select 136 | # cyclonev_termination_logic 137 | # cyclonev_termination 138 | # cyclonev_asmiblock 139 | # cyclonev_chipidblock 140 | # cyclonev_controller 141 | # cyclonev_crcblock 142 | # cyclonev_jtag 143 | # cyclonev_prblock 144 | # cyclonev_rublock 145 | # cyclonev_tsdblock 146 | # cyclonev_read_fifo 147 | # cyclonev_read_fifo_read_enable 148 | # cyclonev_phy_clkbuf 149 | # cyclonev_ir_fifo_userdes 150 | # cyclonev_read_fifo_read_clock_select 151 | # cyclonev_lfifo 152 | # cyclonev_vfifo 153 | # cyclonev_mac 154 | # cyclonev_mem_phy 155 | # cyclonev_oscillator 156 | # cyclonev_hps_interface_fpga2sdram 157 | # End time: 13:36:08 on Nov 30,2020, Elapsed time: 0:00:00 158 | # Errors: 0, Warnings: 0 159 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 160 | # Start time: 13:36:08 on Nov 30,2020 161 | # vlog -work cyclonev_hssi_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/mentor/cyclonev_hssi_atoms_ncrypt.v 162 | # 163 | # Top level modules: 164 | # End time: 13:36:09 on Nov 30,2020, Elapsed time: 0:00:01 165 | # Errors: 0, Warnings: 0 166 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 167 | # Start time: 13:36:09 on Nov 30,2020 168 | # vlog -work cyclonev_hssi_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/cyclonev_hssi_atoms.v 169 | # -- Compiling module cyclonev_hssi_8g_pcs_aggregate 170 | # -- Compiling module cyclonev_hssi_8g_rx_pcs 171 | # -- Compiling module cyclonev_hssi_8g_tx_pcs 172 | # -- Compiling module cyclonev_hssi_common_pcs_pma_interface 173 | # -- Compiling module cyclonev_hssi_common_pld_pcs_interface 174 | # -- Compiling module cyclonev_hssi_pipe_gen1_2 175 | # -- Compiling module cyclonev_hssi_pma_aux 176 | # -- Compiling module cyclonev_hssi_pma_int 177 | # -- Compiling module cyclonev_hssi_pma_rx_buf 178 | # -- Compiling module cyclonev_hssi_pma_rx_deser 179 | # -- Compiling module cyclonev_hssi_pma_tx_buf 180 | # -- Compiling module cyclonev_hssi_pma_tx_cgb 181 | # -- Compiling module cyclonev_hssi_pma_tx_ser 182 | # -- Compiling module cyclonev_hssi_pma_cdr_refclk_select_mux 183 | # -- Compiling module cyclonev_hssi_rx_pcs_pma_interface 184 | # -- Compiling module cyclonev_hssi_rx_pld_pcs_interface 185 | # -- Compiling module cyclonev_hssi_tx_pcs_pma_interface 186 | # -- Compiling module cyclonev_hssi_tx_pld_pcs_interface 187 | # -- Compiling module cyclonev_hssi_refclk_divider 188 | # -- Compiling module cyclonev_pll_aux 189 | # -- Compiling module cyclonev_channel_pll 190 | # -- Compiling module cyclonev_hssi_avmm_interface 191 | # -- Compiling module cyclonev_hssi_pma_hi_pmaif 192 | # -- Compiling module cyclonev_hssi_pma_hi_xcvrif 193 | # -- Compiling module arriav_hssi_8g_pcs_aggregate 194 | # -- Compiling module arriav_hssi_8g_rx_pcs 195 | # -- Compiling module arriav_hssi_8g_tx_pcs 196 | # -- Compiling module arriav_hssi_common_pcs_pma_interface 197 | # -- Compiling module arriav_hssi_common_pld_pcs_interface 198 | # -- Compiling module arriav_hssi_pipe_gen1_2 199 | # -- Compiling module arriav_hssi_pma_aux 200 | # -- Compiling module arriav_hssi_pma_int 201 | # -- Compiling module arriav_hssi_pma_rx_buf 202 | # -- Compiling module arriav_hssi_pma_rx_deser 203 | # -- Compiling module arriav_hssi_pma_tx_buf 204 | # -- Compiling module arriav_hssi_pma_tx_cgb 205 | # -- Compiling module arriav_hssi_pma_tx_ser 206 | # -- Compiling module arriav_hssi_pma_cdr_refclk_select_mux 207 | # -- Compiling module arriav_hssi_rx_pcs_pma_interface 208 | # -- Compiling module arriav_hssi_rx_pld_pcs_interface 209 | # -- Compiling module arriav_hssi_tx_pcs_pma_interface 210 | # -- Compiling module arriav_hssi_tx_pld_pcs_interface 211 | # -- Compiling module arriav_hssi_refclk_divider 212 | # -- Compiling module arriav_pll_aux 213 | # -- Compiling module arriav_channel_pll 214 | # -- Compiling module arriav_hssi_avmm_interface 215 | # -- Compiling module arriav_hssi_pma_hi_pmaif 216 | # -- Compiling module arriav_hssi_pma_hi_xcvrif 217 | # 218 | # Top level modules: 219 | # cyclonev_hssi_8g_pcs_aggregate 220 | # cyclonev_hssi_8g_rx_pcs 221 | # cyclonev_hssi_8g_tx_pcs 222 | # cyclonev_hssi_common_pcs_pma_interface 223 | # cyclonev_hssi_common_pld_pcs_interface 224 | # cyclonev_hssi_pipe_gen1_2 225 | # cyclonev_hssi_pma_aux 226 | # cyclonev_hssi_pma_int 227 | # cyclonev_hssi_pma_rx_buf 228 | # cyclonev_hssi_pma_rx_deser 229 | # cyclonev_hssi_pma_tx_buf 230 | # cyclonev_hssi_pma_tx_cgb 231 | # cyclonev_hssi_pma_tx_ser 232 | # cyclonev_hssi_pma_cdr_refclk_select_mux 233 | # cyclonev_hssi_rx_pcs_pma_interface 234 | # cyclonev_hssi_rx_pld_pcs_interface 235 | # cyclonev_hssi_tx_pcs_pma_interface 236 | # cyclonev_hssi_tx_pld_pcs_interface 237 | # cyclonev_hssi_refclk_divider 238 | # cyclonev_pll_aux 239 | # cyclonev_channel_pll 240 | # cyclonev_hssi_avmm_interface 241 | # cyclonev_hssi_pma_hi_pmaif 242 | # cyclonev_hssi_pma_hi_xcvrif 243 | # arriav_hssi_8g_pcs_aggregate 244 | # arriav_hssi_8g_rx_pcs 245 | # arriav_hssi_8g_tx_pcs 246 | # arriav_hssi_common_pcs_pma_interface 247 | # arriav_hssi_common_pld_pcs_interface 248 | # arriav_hssi_pipe_gen1_2 249 | # arriav_hssi_pma_aux 250 | # arriav_hssi_pma_int 251 | # arriav_hssi_pma_rx_buf 252 | # arriav_hssi_pma_rx_deser 253 | # arriav_hssi_pma_tx_buf 254 | # arriav_hssi_pma_tx_cgb 255 | # arriav_hssi_pma_tx_ser 256 | # arriav_hssi_pma_cdr_refclk_select_mux 257 | # arriav_hssi_rx_pcs_pma_interface 258 | # arriav_hssi_rx_pld_pcs_interface 259 | # arriav_hssi_tx_pcs_pma_interface 260 | # arriav_hssi_tx_pld_pcs_interface 261 | # arriav_hssi_refclk_divider 262 | # arriav_pll_aux 263 | # arriav_channel_pll 264 | # arriav_hssi_avmm_interface 265 | # arriav_hssi_pma_hi_pmaif 266 | # arriav_hssi_pma_hi_xcvrif 267 | # End time: 13:36:10 on Nov 30,2020, Elapsed time: 0:00:01 268 | # Errors: 0, Warnings: 0 269 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 270 | # Start time: 13:36:10 on Nov 30,2020 271 | # vlog -work cyclonev_pcie_hip_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/mentor/cyclonev_pcie_hip_atoms_ncrypt.v 272 | # 273 | # Top level modules: 274 | # End time: 13:36:12 on Nov 30,2020, Elapsed time: 0:00:02 275 | # Errors: 0, Warnings: 0 276 | # Model Technology ModelSim SE-64 vlog 10.6d Compiler 2018.02 Feb 24 2018 277 | # Start time: 13:36:12 on Nov 30,2020 278 | # vlog -work cyclonev_pcie_hip_ver -vlog01compat c:/intelfpga/17.1/quartus/eda/sim_lib/cyclonev_pcie_hip_atoms.v 279 | # -- Compiling module cyclonev_hd_altpe2_hip_top 280 | # -- Compiling module arriav_hd_altpe2_hip_top 281 | # 282 | # Top level modules: 283 | # cyclonev_hd_altpe2_hip_top 284 | # End time: 13:36:12 on Nov 30,2020, Elapsed time: 0:00:00 285 | # Errors: 0, Warnings: 0 286 | -------------------------------------------------------------------------------- /SCU/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/SCU/vsim.wlf -------------------------------------------------------------------------------- /SCU/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /SCU_tb/scu/CLK 4 | add wave -noupdate /SCU_tb/scu/CE_R 5 | add wave -noupdate /SCU_tb/scu/A 6 | add wave -noupdate /SCU_tb/scu/DI 7 | add wave -noupdate /SCU_tb/scu/DO 8 | add wave -noupdate /SCU_tb/scu/WR 9 | add wave -noupdate /SCU_tb/scu/RD 10 | add wave -noupdate /SCU_tb/scu/dsp/RUN 11 | add wave -noupdate /SCU_tb/scu/dsp/IC 12 | add wave -noupdate /SCU_tb/scu/dsp/DECI 13 | add wave -noupdate /SCU_tb/scu/dsp/PC 14 | add wave -noupdate /SCU_tb/scu/dsp/AC 15 | add wave -noupdate /SCU_tb/scu/dsp/P 16 | add wave -noupdate /SCU_tb/scu/dsp/RX 17 | add wave -noupdate /SCU_tb/scu/dsp/RY 18 | add wave -noupdate /SCU_tb/scu/dsp/EX 19 | add wave -noupdate /SCU_tb/scu/dsp/EP 20 | add wave -noupdate /SCU_tb/scu/dsp/PR 21 | add wave -noupdate /SCU_tb/scu/dsp/ES 22 | add wave -noupdate /SCU_tb/scu/dsp/LE 23 | add wave -noupdate /SCU_tb/scu/dsp/CT0 24 | add wave -noupdate /SCU_tb/scu/dsp/CT1 25 | add wave -noupdate /SCU_tb/scu/dsp/CT2 26 | add wave -noupdate /SCU_tb/scu/dsp/CT3 27 | add wave -noupdate /SCU_tb/scu/dsp/RA0 28 | add wave -noupdate /SCU_tb/scu/dsp/TN0 29 | add wave -noupdate /SCU_tb/scu/dsp/T0 30 | add wave -noupdate /SCU_tb/scu/dsp/D1BUS 31 | add wave -noupdate /SCU_tb/scu/dsp/XBUS 32 | add wave -noupdate /SCU_tb/scu/dsp/YBUS 33 | add wave -noupdate /SCU_tb/scu/dsp/ALU_Q 34 | add wave -noupdate /SCU_tb/scu/dsp/ALU_C 35 | add wave -noupdate /SCU_tb/scu/dsp/DMA_A 36 | add wave -noupdate /SCU_tb/scu/dsp/DMA_DI 37 | add wave -noupdate /SCU_tb/scu/dsp/DMA_DO 38 | add wave -noupdate /SCU_tb/scu/dsp/DMA_WR 39 | add wave -noupdate /SCU_tb/scu/dsp/DMA_REQ 40 | add wave -noupdate /SCU_tb/scu/dsp/DMA_ACK 41 | add wave -noupdate /SCU_tb/scu/dsp/PRG_RAM_Q 42 | add wave -noupdate /SCU_tb/scu/dsp/DATA_RAM0/dpram/MEM 43 | TreeUpdate [SetDefaultTree] 44 | WaveRestoreCursors {{Cursor 1} {515 ns} 0} 45 | quietly wave cursor active 1 46 | configure wave -namecolwidth 150 47 | configure wave -valuecolwidth 100 48 | configure wave -justifyvalue left 49 | configure wave -signalnamewidth 0 50 | configure wave -snapdistance 10 51 | configure wave -datasetprefix 0 52 | configure wave -rowmargin 4 53 | configure wave -childrowmargin 2 54 | configure wave -gridoffset 0 55 | configure wave -gridperiod 1 56 | configure wave -griddelta 40 57 | configure wave -timeline 0 58 | configure wave -timelineunits us 59 | update 60 | WaveRestoreZoom {0 ns} {250 ns} 61 | -------------------------------------------------------------------------------- /SMPC.sv: -------------------------------------------------------------------------------- 1 | module SMPC ( 2 | input CLK, 3 | input RST_N, 4 | input CE, 5 | 6 | input MRES_N, 7 | input TIME_SET, 8 | 9 | input [ 3: 0] AC, 10 | 11 | input [ 6: 1] A, 12 | input [ 7: 0] DI, 13 | output [ 7: 0] DO, 14 | input CS_N, 15 | input RW_N, 16 | 17 | input SRES_N, 18 | 19 | input IRQV_N, 20 | input EXL, 21 | 22 | output reg MSHRES_N, 23 | output reg MSHNMI_N, 24 | output reg SSHRES_N, 25 | output reg SSHNMI_N, 26 | output reg SYSRES_N, 27 | output reg SNDRES_N, 28 | output reg CDRES_N, 29 | 30 | output reg MIRQ_N, 31 | 32 | output reg DOTSEL, 33 | 34 | input [ 6: 0] PDR1I, 35 | output reg [ 6: 0] PDR1O, 36 | output reg [ 6: 0] DDR1, 37 | input [ 6: 0] PDR2I, 38 | output reg [ 6: 0] PDR2O, 39 | output reg [ 6: 0] DDR2, 40 | 41 | output reg INPUT_ACT, 42 | output [ 4: 0] INPUT_POS, 43 | input [ 7: 0] INPUT_DATA, 44 | input INPUT_WE 45 | ); 46 | 47 | //Registers 48 | bit [7:0] COMREG; 49 | bit [7:0] SR; 50 | bit SF; 51 | bit [7:0] IREG[7]; 52 | bit PDR1O7; 53 | bit PDR2O7; 54 | // bit [1:0] IOSEL; 55 | // bit [1:0] EXLE; 56 | 57 | bit RESD; 58 | bit STE; 59 | 60 | bit [7:0] SEC; 61 | bit [7:0] MIN; 62 | bit [7:0] HOUR; 63 | bit [7:0] DAY; 64 | 65 | bit [7:0] SMEM[4]; 66 | 67 | parameter SR_PDE = 2; 68 | parameter SR_RESB = 3; 69 | 70 | bit SEC_CLK; 71 | always @(posedge CLK or negedge RST_N) begin 72 | bit [21:0] CLK_CNT; 73 | 74 | if (!RST_N) begin 75 | SEC_CLK <= 0; 76 | CLK_CNT <= '0; 77 | end else if (CE) begin 78 | SEC_CLK <= 0; 79 | 80 | CLK_CNT <= CLK_CNT + 3'd1; 81 | if (CLK_CNT == 22'd4000000-1) begin 82 | CLK_CNT <= 22'd0; 83 | SEC_CLK <= 1; 84 | end 85 | end 86 | end 87 | 88 | always @(posedge CLK or negedge RST_N) begin 89 | if (!RST_N) begin 90 | SEC <= '0; 91 | MIN <= '0; 92 | HOUR <= '0; 93 | DAY <= '0; 94 | end else if (SEC_CLK && CE) begin 95 | `ifdef DEBUG 96 | SEC[3:0] <= SEC[3:0] + 4'd1; 97 | if (SEC[3:0] == 4'd9) begin 98 | SEC[3:0] <= 4'd0; 99 | SEC[7:4] <= SEC[7:4] + 4'd1; 100 | if (SEC[7:4] == 4'd5) begin 101 | SEC[7:4] <= 4'd0; 102 | MIN[3:0] <= MIN[3:0] + 4'd1; 103 | if (MIN[3:0] == 4'd9) begin 104 | MIN[3:0] <= 4'd0; 105 | MIN[7:4] <= MIN[7:4] + 4'd1; 106 | if (MIN[7:4] == 4'd5) begin 107 | MIN[7:4] <= 4'd0; 108 | HOUR[3:0] <= HOUR[3:0] + 4'd1; 109 | if (HOUR[3:0] == 4'd9) begin 110 | HOUR[3:0] <= 4'd0; 111 | HOUR[7:4] <= HOUR[7:4] + 4'd1; 112 | if (HOUR[7:4] == 4'd2 && HOUR[3:0] == 4'd3) begin 113 | HOUR[7:4] <= 4'd0; 114 | HOUR[3:0] <= 4'd0; 115 | DAY[3:0] <= DAY[3:0] + 4'd1; 116 | if (DAY[3:0] == 4'd9) begin 117 | DAY[7:4] <= DAY[7:4] + 4'd1; 118 | DAY[3:0] <= 4'd0; 119 | if (DAY[7:4] == 4'd3 && HOUR[3:0] == 4'd1) begin//TODO 120 | DAY[7:4] <= 4'd0; 121 | DAY[3:0] <= 4'd1; 122 | end 123 | end 124 | end 125 | end 126 | end 127 | end 128 | end 129 | end 130 | `endif 131 | end 132 | end 133 | 134 | typedef enum bit [6:0] { 135 | CS_IDLE = 7'b0000001, 136 | CS_START = 7'b0000010, 137 | CS_RESET = 7'b0000100, 138 | CS_WAIT = 7'b0001000, 139 | CS_EXEC = 7'b0010000, 140 | CS_INTBACK_PERI = 7'b0100000, 141 | CS_END = 7'b1000000 142 | } CommExecState_t; 143 | CommExecState_t COMM_ST; 144 | 145 | bit [7:0] REG_DO; 146 | bit [ 4:0] OREG_CNT; 147 | always @(posedge CLK or negedge RST_N) begin 148 | bit RW_N_OLD; 149 | bit CS_N_OLD; 150 | bit IRQV_N_OLD; 151 | bit [19:0] WAIT_CNT; 152 | bit [15:0] INTBACK_WAIT_CNT; 153 | bit SRES_EXEC; 154 | bit INTBACK_EXEC; 155 | bit INTBACK_PERI; 156 | bit INTBACK_OPTIM; 157 | bit COMREG_SET; 158 | bit CONT; 159 | bit SF_CLR; 160 | 161 | if (!RST_N) begin 162 | COMREG <= '0; 163 | SR <= '0; 164 | SF <= 0; 165 | IREG <= '{7{'0}}; 166 | PDR1O <= '0; 167 | PDR2O <= '0; 168 | DDR1 <= '0; 169 | DDR2 <= '0; 170 | // IOSEL <= '0; 171 | // EXLE <= '0; 172 | 173 | MSHRES_N <= 0; 174 | MSHNMI_N <= 0; 175 | SSHRES_N <= 0; 176 | SSHNMI_N <= 0; 177 | SYSRES_N <= 0; 178 | SNDRES_N <= 0; 179 | CDRES_N <= 0; 180 | MIRQ_N <= 1; 181 | DOTSEL <= 0; 182 | RESD <= 1; 183 | STE <= 0; 184 | 185 | REG_DO <= '0; 186 | RW_N_OLD <= 1; 187 | CS_N_OLD <= 1; 188 | IRQV_N_OLD <= 1; 189 | COMM_ST <= CS_IDLE; 190 | SRES_EXEC <= 0; 191 | INTBACK_EXEC <= 0; 192 | INTBACK_PERI <= 0; 193 | CONT <= 0; 194 | 195 | INPUT_ACT <= 0; 196 | end 197 | else if (!MRES_N) begin 198 | MSHRES_N <= 1; 199 | MSHNMI_N <= 1; 200 | SSHRES_N <= 0; 201 | SSHNMI_N <= 1; 202 | SYSRES_N <= 1; 203 | SNDRES_N <= 0; 204 | CDRES_N <= 1; 205 | MIRQ_N <= 1; 206 | DOTSEL <= 0; 207 | SR <= '0; 208 | RESD <= 1; 209 | STE <= TIME_SET;///////////////// 210 | end else begin 211 | OREG_RAM_WE <= 0; 212 | 213 | if (CE) begin 214 | IRQV_N_OLD <= IRQV_N; 215 | 216 | if (WAIT_CNT) WAIT_CNT <= WAIT_CNT - 20'd1; 217 | 218 | if (!SRES_N && !RESD && !SRES_EXEC) begin 219 | MSHNMI_N <= 0; 220 | SSHNMI_N <= 0; 221 | WAIT_CNT <= 16'd60000; 222 | SRES_EXEC <= 1; 223 | end else if (SRES_EXEC && !WAIT_CNT) begin 224 | MSHNMI_N <= 1; 225 | SSHNMI_N <= 1; 226 | end 227 | 228 | if (INTBACK_WAIT_CNT) INTBACK_WAIT_CNT <= INTBACK_WAIT_CNT - 16'd1; 229 | if (!IRQV_N /*&& !IRQV_N_OLD*/) INTBACK_WAIT_CNT <= 16'd52200; 230 | 231 | if (!IRQV_N && IRQV_N_OLD) begin 232 | INTBACK_EXEC <= 0; 233 | INTBACK_PERI <= 0; 234 | SF <= 0; 235 | end 236 | 237 | SR[4:0] <= {~SRES_N,IREG[1][7:4]}; 238 | 239 | case (COMM_ST) 240 | CS_IDLE: begin 241 | if (INTBACK_PERI && ((!INTBACK_WAIT_CNT && INTBACK_OPTIM) || !INTBACK_OPTIM) && !SRES_EXEC /*&& IRQV_N*/) begin 242 | INTBACK_PERI <= 0; 243 | SF <= 1; 244 | OREG_CNT <= '0; 245 | COMM_ST <= CS_INTBACK_PERI; 246 | INPUT_ACT <= 1; 247 | end else if (COMREG_SET && !SRES_EXEC) begin 248 | COMREG_SET <= 0; 249 | OREG_CNT <= '0; 250 | COMM_ST <= CS_START; 251 | end 252 | MIRQ_N <= 1; 253 | end 254 | 255 | CS_START: begin 256 | case (COMREG) 257 | 8'h00: begin //MSHON 258 | WAIT_CNT <= 20'd120; 259 | COMM_ST <= CS_WAIT; 260 | end 261 | 262 | 8'h02: begin //SSHON 263 | WAIT_CNT <= 20'd120; 264 | COMM_ST <= CS_WAIT; 265 | end 266 | 267 | 8'h03: begin //SSHOFF 268 | WAIT_CNT <= 20'd120; 269 | COMM_ST <= CS_WAIT; 270 | end 271 | 272 | 8'h06: begin //SNDON 273 | WAIT_CNT <= 20'd120; 274 | COMM_ST <= CS_WAIT; 275 | end 276 | 277 | 8'h07: begin //SNDOFF 278 | WAIT_CNT <= 20'd120; 279 | COMM_ST <= CS_WAIT; 280 | end 281 | 282 | 8'h08: begin //CDON 283 | WAIT_CNT <= 20'd159; 284 | COMM_ST <= CS_WAIT; 285 | end 286 | 287 | 8'h09: begin //CDOFF 288 | WAIT_CNT <= 20'd159; 289 | COMM_ST <= CS_WAIT; 290 | end 291 | 292 | 8'h0D: begin //SYSRES 293 | MSHRES_N <= 0; 294 | MSHNMI_N <= 0; 295 | SSHRES_N <= 0; 296 | SSHNMI_N <= 0; 297 | SNDRES_N <= 0; 298 | CDRES_N <= 0; 299 | SYSRES_N <= 0; 300 | WAIT_CNT <= 20'd400000; 301 | COMM_ST <= CS_RESET; 302 | end 303 | 304 | 8'h0E: begin //CKCHG352 305 | SSHRES_N <= 0; 306 | SSHNMI_N <= 0; 307 | SNDRES_N <= 0; 308 | SYSRES_N <= 0; 309 | DOTSEL <= 1; 310 | WAIT_CNT <= 20'd400000; 311 | COMM_ST <= CS_RESET; 312 | end 313 | 314 | 8'h0F: begin //CKCHG320 315 | SSHRES_N <= 0; 316 | SSHNMI_N <= 0; 317 | SNDRES_N <= 0; 318 | SYSRES_N <= 0; 319 | DOTSEL <= 0; 320 | WAIT_CNT <= 20'd400000; 321 | COMM_ST <= CS_RESET; 322 | end 323 | 324 | 8'h10: begin //INTBACK 325 | if (IREG[2] == 8'hF0 && (IREG[0][0] || IREG[1][3])) begin 326 | if (IREG[0][0]) begin 327 | WAIT_CNT <= 20'd500; 328 | COMM_ST <= CS_WAIT; 329 | end else begin 330 | INTBACK_EXEC <= 1; 331 | INTBACK_PERI <= 1; 332 | INTBACK_OPTIM <= ~IREG[1][1]; 333 | CONT <= 0; 334 | // SR[7:5] <= 3'b010; 335 | COMM_ST <= CS_END; 336 | end 337 | end else begin 338 | COMM_ST <= CS_END; 339 | end 340 | end 341 | 342 | 8'h16: begin //SETTIME 343 | WAIT_CNT <= 20'd279; 344 | COMM_ST <= CS_WAIT; 345 | end 346 | 347 | 8'h17: begin //SETSMEM 348 | WAIT_CNT <= 20'd159; 349 | COMM_ST <= CS_WAIT; 350 | end 351 | 352 | 8'h18: begin //NMIREQ 353 | WAIT_CNT <= 20'd127; 354 | COMM_ST <= CS_WAIT; 355 | end 356 | 357 | 8'h19: begin //RESENAB 358 | WAIT_CNT <= 20'd127; 359 | COMM_ST <= CS_WAIT; 360 | end 361 | 362 | 8'h1A: begin //RESDISA 363 | WAIT_CNT <= 20'd127; 364 | COMM_ST <= CS_WAIT; 365 | end 366 | 367 | default: begin 368 | COMM_ST <= CS_EXEC; 369 | end 370 | endcase 371 | end 372 | 373 | CS_RESET: begin 374 | case (COMREG) 375 | 8'h0D: begin //SYSRES 376 | CDRES_N <= 1; 377 | SNDRES_N <= 1; 378 | SYSRES_N <= 1; 379 | COMM_ST <= CS_WAIT; 380 | end 381 | 382 | 8'h0E: begin //CKCHG352 383 | SNDRES_N <= 1; 384 | SYSRES_N <= 1; 385 | COMM_ST <= CS_WAIT; 386 | end 387 | 388 | 8'h0F: begin //CKCHG320 389 | SNDRES_N <= 1; 390 | SYSRES_N <= 1; 391 | COMM_ST <= CS_WAIT; 392 | end 393 | 394 | default: begin 395 | COMM_ST <= CS_WAIT; 396 | end 397 | endcase 398 | end 399 | 400 | CS_WAIT: begin 401 | if (!WAIT_CNT) COMM_ST <= CS_EXEC; 402 | end 403 | 404 | CS_EXEC: begin 405 | SF_CLR <= 1; 406 | 407 | OREG_RAM_WA <= 5'd31; 408 | OREG_RAM_D <= COMREG; 409 | OREG_RAM_WE <= 1; 410 | case (COMREG) 411 | 8'h00: begin //MSHON 412 | MSHRES_N <= 1; 413 | MSHNMI_N <= 1;//? 414 | COMM_ST <= CS_END; 415 | end 416 | 417 | 8'h02: begin //SSHON 418 | SSHRES_N <= 1; 419 | SSHNMI_N <= 1;//? 420 | COMM_ST <= CS_END; 421 | end 422 | 423 | 8'h03: begin //SSHOFF 424 | SSHRES_N <= 0; 425 | SSHNMI_N <= 1;//? 426 | COMM_ST <= CS_END; 427 | end 428 | 429 | 8'h06: begin //SNDON 430 | SNDRES_N <= 1; 431 | COMM_ST <= CS_END; 432 | end 433 | 434 | 8'h07: begin //SNDOFF 435 | SNDRES_N <= 0; 436 | COMM_ST <= CS_END; 437 | end 438 | 439 | 8'h08: begin //CDON 440 | CDRES_N <= 1; 441 | COMM_ST <= CS_END; 442 | end 443 | 444 | 8'h09: begin //CDOFF 445 | CDRES_N <= 0; 446 | COMM_ST <= CS_END; 447 | end 448 | 449 | 8'h0D: begin //SYSRES 450 | COMM_ST <= CS_END; 451 | end 452 | 453 | 8'h0E: begin //CKCHG352 454 | MSHNMI_N <= 0; 455 | COMM_ST <= CS_END; 456 | end 457 | 458 | 8'h0F: begin //CKCHG320 459 | MSHNMI_N <= 0; 460 | COMM_ST <= CS_END; 461 | end 462 | 463 | 8'h10: begin //INTBACK 464 | if (!INTBACK_EXEC) begin 465 | OREG_RAM_WA <= OREG_CNT; 466 | case (OREG_CNT) 467 | 5'd0: OREG_RAM_D <= {STE,RESD,6'b000000}; 468 | 5'd1: OREG_RAM_D <= 8'h20; 469 | 5'd2: OREG_RAM_D <= 8'h22; 470 | 5'd3: OREG_RAM_D <= 8'h01; 471 | 5'd4: OREG_RAM_D <= DAY; 472 | 5'd5: OREG_RAM_D <= HOUR; 473 | 5'd6: OREG_RAM_D <= MIN; 474 | 5'd7: OREG_RAM_D <= SEC; 475 | 5'd8: OREG_RAM_D <= 8'h00; 476 | 5'd9: OREG_RAM_D <= {4'b0000,AC}; 477 | 5'd10: OREG_RAM_D <= {1'b0,DOTSEL,2'b11,~MSHNMI_N,1'b1,~SYSRES_N,~SNDRES_N}; 478 | 5'd11: OREG_RAM_D <= {1'b0,~CDRES_N,6'b000000}; 479 | 5'd12: OREG_RAM_D <= SMEM[0]; 480 | 5'd13: OREG_RAM_D <= SMEM[1]; 481 | 5'd14: OREG_RAM_D <= SMEM[2]; 482 | 5'd15: OREG_RAM_D <= SMEM[3]; 483 | 5'd31: OREG_RAM_D <= COMREG; 484 | default:OREG_RAM_D <= 8'h00; 485 | endcase 486 | OREG_RAM_WE <= 1; 487 | 488 | if (OREG_CNT == 5'd31) begin 489 | SR[7:5] <= 3'b010; 490 | if (IREG[1][3]) begin 491 | INTBACK_EXEC <= 1; 492 | INTBACK_OPTIM <= ~IREG[1][1]; 493 | SR[5] <= 1; 494 | SF_CLR <= 0; 495 | end 496 | CONT <= 0; 497 | MIRQ_N <= 0; 498 | COMM_ST <= CS_END; 499 | end 500 | OREG_CNT <= OREG_CNT + 5'd1; 501 | end else begin 502 | COMM_ST <= CS_END; 503 | end 504 | end 505 | 506 | 8'h16: begin //SETTIME 507 | STE <= 1; 508 | COMM_ST <= CS_END; 509 | end 510 | 511 | 8'h17: begin //SETSMEM 512 | SMEM[0] <= IREG[0]; 513 | SMEM[1] <= IREG[1]; 514 | SMEM[2] <= IREG[2]; 515 | SMEM[3] <= IREG[3]; 516 | COMM_ST <= CS_END; 517 | end 518 | 519 | 8'h18: begin //NMIREQ 520 | MSHNMI_N <= 0; 521 | COMM_ST <= CS_END; 522 | end 523 | 524 | 8'h19: begin //RESENAB 525 | RESD <= 0; 526 | COMM_ST <= CS_END; 527 | end 528 | 529 | 8'h1A: begin //RESDISA 530 | RESD <= 1; 531 | COMM_ST <= CS_END; 532 | end 533 | 534 | default: begin 535 | COMM_ST <= CS_END; 536 | end 537 | endcase 538 | end 539 | 540 | CS_INTBACK_PERI: begin 541 | if (INPUT_ACT && INPUT_WE) begin 542 | OREG_CNT <= OREG_CNT + 5'd1; 543 | if (OREG_CNT == 5'd30) begin 544 | INPUT_ACT <= 0; 545 | end 546 | OREG_RAM_WA <= OREG_CNT; 547 | OREG_RAM_D <= INPUT_DATA; 548 | OREG_RAM_WE <= 1; 549 | end 550 | else if (OREG_CNT == 5'd31) begin 551 | OREG_CNT <= OREG_CNT + 5'd1; 552 | OREG_RAM_WA <= OREG_CNT; 553 | OREG_RAM_D <= COMREG; 554 | OREG_RAM_WE <= 1; 555 | SR[7:5] <= {1'b1,1'b1,1'b0}; 556 | SF <= 0; 557 | MIRQ_N <= 0; 558 | COMM_ST <= CS_IDLE; 559 | end 560 | end 561 | 562 | CS_END: begin 563 | case (COMREG) 564 | 8'h00: begin //MSHON 565 | 566 | end 567 | 568 | 8'h02: begin //SSHON 569 | 570 | end 571 | 572 | 8'h03: begin //SSHOFF 573 | 574 | end 575 | 576 | 8'h06: begin //SNDON 577 | 578 | end 579 | 580 | 8'h07: begin //SNDOFF 581 | 582 | end 583 | 584 | 8'h08: begin //CDON 585 | 586 | end 587 | 588 | 8'h09: begin //CDOFF 589 | 590 | end 591 | 592 | 8'h0D: begin //SYSRES 593 | MSHRES_N <= 1; 594 | MSHNMI_N <= 1; 595 | SSHRES_N <= 1; 596 | SSHNMI_N <= 1; 597 | end 598 | 599 | 8'h0E: begin //CKCHG352 600 | MSHNMI_N <= 1; 601 | end 602 | 603 | 8'h0F: begin //CKCHG320 604 | MSHNMI_N <= 1; 605 | end 606 | 607 | 8'h10: begin //INTBACK 608 | 609 | end 610 | 611 | 8'h16: begin //SETTIME 612 | 613 | end 614 | 615 | 8'h17: begin //SETSMEM 616 | 617 | end 618 | 619 | 8'h18: begin //NMIREQ 620 | MSHNMI_N <= 1; 621 | end 622 | 623 | 8'h19: begin //RESENAB 624 | 625 | end 626 | 627 | 8'h1A: begin //RESDISA 628 | 629 | end 630 | 631 | default:; 632 | endcase 633 | if (SF_CLR) SF <= 0; 634 | SF_CLR <= 0; 635 | COMM_ST <= CS_IDLE; 636 | end 637 | endcase 638 | end 639 | 640 | 641 | RW_N_OLD <= RW_N; 642 | if (!RW_N && RW_N_OLD && !CS_N) begin 643 | case ({A,1'b1}) 644 | 7'h01: begin 645 | if (INTBACK_EXEC) begin 646 | if (DI[6]) begin 647 | INTBACK_EXEC <= 0; 648 | SF <= 0; 649 | SR[7:5] <= 3'b000; 650 | end else if (CONT != DI[7]) begin 651 | INTBACK_PERI <= 1; 652 | SF <= 1; 653 | end 654 | CONT <= DI[7]; 655 | end else begin 656 | IREG[0] <= DI; 657 | end 658 | end 659 | 7'h03: IREG[1] <= DI; 660 | 7'h05: IREG[2] <= DI; 661 | 7'h07: IREG[3] <= DI; 662 | 7'h09: IREG[4] <= DI; 663 | 7'h0B: IREG[5] <= DI; 664 | 7'h0D: IREG[6] <= DI; 665 | 7'h1F: begin COMREG <= DI; COMREG_SET <= 1; end 666 | 7'h63: if (DI[0]) SF <= 1; 667 | 7'h75: {PDR1O7,PDR1O} <= DI; 668 | 7'h77: {PDR2O7,PDR2O} <= DI; 669 | 7'h79: DDR1 <= DI[6:0]; 670 | 7'h7B: DDR2 <= DI[6:0]; 671 | // 7'h7D: IOSEL <= DI[1:0]; 672 | // 7'h7F: EXLE <= DI[1:0]; 673 | default:; 674 | endcase 675 | end 676 | 677 | CS_N_OLD <= CS_N; 678 | if (!CS_N && CS_N_OLD && RW_N) begin 679 | if ({A,1'b1} <= 7'h5F) 680 | REG_DO <= OREG_RAM_Q; 681 | else 682 | case ({A,1'b1}) 683 | 7'h61: REG_DO <= SR; 684 | 7'h63: REG_DO <= {7'b0000000,SF}; 685 | 7'h75: REG_DO <= {PDR1O7,PDR1I}; 686 | 7'h77: REG_DO <= {PDR2O7,PDR2I}; 687 | default: REG_DO <= '0; 688 | endcase 689 | end 690 | end 691 | end 692 | 693 | bit [4:0] OREG_RAM_WA; 694 | bit [7:0] OREG_RAM_D; 695 | bit OREG_RAM_WE; 696 | bit [7:0] OREG_RAM_Q; 697 | SMPC_OREG_RAM OREG_RAM (CLK, OREG_RAM_WA, OREG_RAM_D, OREG_RAM_WE, (A - 6'h10), OREG_RAM_Q); 698 | 699 | assign INPUT_POS = OREG_CNT; 700 | 701 | assign DO = REG_DO; 702 | 703 | endmodule 704 | 705 | 706 | module SMPC_OREG_RAM 707 | ( 708 | input CLK, 709 | input [4:0] WADDR, 710 | input [7:0] DATA, 711 | input [1:0] WREN, 712 | input [4:0] RADDR, 713 | output [7:0] Q 714 | ); 715 | 716 | wire [7:0] sub_wire0; 717 | 718 | altdpram altdpram_component ( 719 | .data (DATA), 720 | .inclock (CLK), 721 | .rdaddress (RADDR), 722 | .wraddress (WADDR), 723 | .wren (WREN[0]), 724 | .q (sub_wire0), 725 | .aclr (1'b0), 726 | .byteena (1'b1), 727 | .inclocken (1'b1), 728 | .rdaddressstall (1'b0), 729 | .rden (1'b1), 730 | // .sclr (1'b0), 731 | .wraddressstall (1'b0)); 732 | defparam 733 | altdpram_component.indata_aclr = "OFF", 734 | altdpram_component.indata_reg = "INCLOCK", 735 | altdpram_component.intended_device_family = "Cyclone V", 736 | altdpram_component.lpm_type = "altdpram", 737 | altdpram_component.outdata_aclr = "OFF", 738 | altdpram_component.outdata_reg = "UNREGISTERED", 739 | altdpram_component.ram_block_type = "MLAB", 740 | altdpram_component.rdaddress_aclr = "OFF", 741 | altdpram_component.rdaddress_reg = "UNREGISTERED", 742 | altdpram_component.rdcontrol_aclr = "OFF", 743 | altdpram_component.rdcontrol_reg = "UNREGISTERED", 744 | altdpram_component.read_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE", 745 | altdpram_component.width = 8, 746 | altdpram_component.widthad = 5, 747 | altdpram_component.width_byteena = 1, 748 | altdpram_component.wraddress_aclr = "OFF", 749 | altdpram_component.wraddress_reg = "INCLOCK", 750 | altdpram_component.wrcontrol_aclr = "OFF", 751 | altdpram_component.wrcontrol_reg = "INCLOCK"; 752 | 753 | assign Q = sub_wire0; 754 | 755 | endmodule 756 | -------------------------------------------------------------------------------- /Saturn.qip: -------------------------------------------------------------------------------- 1 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) Saturn.sv ] 2 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SMPC.sv ] 3 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) DCC.sv ] 4 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU/DSP_PKG.sv ] 5 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU/RAM.sv ] 6 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU/DSP.sv ] 7 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU/SCU_PKG.sv ] 8 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCU/SCU.sv ] 9 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) VDP1/VDP1_pkg.sv ] 10 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) VDP1/VDP1.sv ] 11 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) VDP2/VDP2_pkg.sv ] 12 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) VDP2/VDP2.sv ] 13 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) VDP2/VDP2_MEM.sv] 14 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCSP/SCSP_pkg.sv ] 15 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) SCSP/SCSP.sv ] 16 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) CD/YGR019.sv ] 17 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) CD/YGR019_PKG.sv ] 18 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) CD/SH1.sv ] 19 | set_global_assignment -name SYSTEMVERILOG_FILE [file join $::quartus(qip_path) CART.sv ] 20 | -------------------------------------------------------------------------------- /Saturn.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 10:02:47 December 11, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "10:02:47 December 11, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "Saturn" 31 | -------------------------------------------------------------------------------- /Saturn.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 10:02:47 December 11, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # Saturn_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEMA6F31I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY Saturn 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:02:47 DECEMBER 11, 2020" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 50 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 51 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 52 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 53 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 54 | set_global_assignment -name QIP_FILE ../SH2/SH7604.qip 55 | set_global_assignment -name QIP_FILE FX68K/fx68k.qip 56 | set_global_assignment -name QIP_FILE SCU/SCU.qip 57 | set_global_assignment -name SYSTEMVERILOG_FILE Saturn.sv 58 | set_global_assignment -name SYSTEMVERILOG_FILE VDP1/VDP1_pkg.sv 59 | set_global_assignment -name SYSTEMVERILOG_FILE VDP1/VDP1.sv 60 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2/VDP2_pkg.sv 61 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2/VDP2_pal.sv 62 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2/VDP2.sv 63 | set_global_assignment -name SYSTEMVERILOG_FILE SCSP/SCSP_pkg.sv 64 | set_global_assignment -name SYSTEMVERILOG_FILE SCSP/SCSP.sv 65 | set_global_assignment -name SYSTEMVERILOG_FILE DCC.sv 66 | set_global_assignment -name SYSTEMVERILOG_FILE SMPC.sv 67 | set_global_assignment -name SYSTEMVERILOG_FILE RAM.sv 68 | set_global_assignment -name SYSTEMVERILOG_FILE Saturn_tb.sv 69 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /Saturn_tb.sv: -------------------------------------------------------------------------------- 1 | `timescale 1 ns / 1 ns 2 | 3 | module Saturn_tb; 4 | 5 | import SCU_PKG::*; 6 | 7 | bit CLK; 8 | bit RST_N; 9 | 10 | bit [24:0] MEM_A; 11 | bit [31:0] MEM_DO; 12 | bit [31:0] MEM_DI; 13 | bit [3:0] MEM_DQM_N; 14 | bit MEM_RD_N; 15 | bit ROM_CS_N; 16 | bit RAML_CS_N; 17 | bit RAMH_CS_N; 18 | 19 | bit [18:1] SCSP_RAM_A; 20 | bit [15:0] SCSP_RAM_D; 21 | bit [1:0] SCSP_RAM_WE; 22 | bit [15:0] SCSP_RAM_Q; 23 | 24 | //clock generation 25 | always #5 CLK = ~CLK; 26 | 27 | //reset generation 28 | initial begin 29 | RST_N = 0; 30 | #12 RST_N = 1; 31 | end 32 | 33 | Saturn Saturn 34 | ( 35 | .CLK(CLK), 36 | .RST_N(RST_N), 37 | .CE(1'b1), 38 | 39 | .MEM_A(MEM_A), 40 | .MEM_DI(MEM_DI), 41 | .MEM_DO(MEM_DO), 42 | .MEM_DQM_N(MEM_DQM_N), 43 | .MEM_RD_N(MEM_RD_N), 44 | .MEM_WAIT_N(1), 45 | 46 | .ROM_CS_N(ROM_CS_N), 47 | .RAML_CS_N(RAML_CS_N), 48 | .RAMH_CS_N(RAMH_CS_N), 49 | 50 | .SCSP_RAM_A(SCSP_RAM_A), 51 | .SCSP_RAM_D(SCSP_RAM_D), 52 | .SCSP_RAM_WE(SCSP_RAM_WE), 53 | .SCSP_RAM_Q(SCSP_RAM_Q) 54 | ); 55 | 56 | bit [15:0] BIOS_Q; 57 | RAM_tb #(18,16,"bios.txt") bios(CLK, MEM_A[18:1], MEM_DO[15:0], ~ROM_CS_N, 2'b00, BIOS_Q); 58 | 59 | bit [15:0] RAML_Q; 60 | RAM_tb #(19,16,"") raml(CLK, MEM_A[19:1], MEM_DO[15:0], ~RAML_CS_N, ~MEM_DQM_N[1:0], RAML_Q); 61 | 62 | bit [31:0] RAMH_Q; 63 | RAM_tb #(18,32,"") ramh(CLK, MEM_A[19:2], MEM_DO, ~RAMH_CS_N, ~MEM_DQM_N, RAMH_Q); 64 | 65 | assign MEM_DI = !ROM_CS_N ? {16'h0000,BIOS_Q} : 66 | !RAML_CS_N ? {16'h0000,RAML_Q} : 67 | !RAMH_CS_N ? RAMH_Q : 68 | 32'hDEEDDEED; 69 | 70 | 71 | RAM_tb #(18,16,"") sndram(CLK, SCSP_RAM_A, SCSP_RAM_D, 1'b1, SCSP_RAM_WE, SCSP_RAM_Q); 72 | 73 | endmodule 74 | -------------------------------------------------------------------------------- /VDP1/RAM_tb.sv: -------------------------------------------------------------------------------- 1 | module RAM_tb 2 | #( 3 | parameter addr_width = 8, 4 | parameter data_width = 8, 5 | parameter mem_sim_file = "" 6 | ) 7 | ( 8 | input CLK, 9 | 10 | input [addr_width-1:0] ADDR, 11 | input [data_width-1:0] DATA, 12 | input CS, 13 | input [data_width/8-1:0] WREN, 14 | output [data_width-1:0] Q 15 | ); 16 | 17 | // synopsys translate_off 18 | `define SIM 19 | // synopsys translate_on 20 | 21 | `ifdef SIM 22 | 23 | reg [data_width-1:0] MEM [2**addr_width]; 24 | 25 | initial begin 26 | MEM = '{2**addr_width{'0}}; 27 | $readmemh(mem_sim_file, MEM); 28 | end 29 | 30 | always @(posedge CLK) begin 31 | bit [data_width-1:0] temp; 32 | 33 | if (data_width > 0) temp[ 7: 0] = WREN[0] ? DATA[ 7: 0] : Q[ 7: 0]; 34 | if (data_width > 8) temp[15: 8] = WREN[1] ? DATA[15: 8] : Q[15: 8]; 35 | if (data_width > 16) temp[23:16] = WREN[2] ? DATA[23:16] : Q[23:16]; 36 | if (data_width > 24) temp[31:24] = WREN[3] ? DATA[31:24] : Q[31:24]; 37 | 38 | if (WREN && CS) begin 39 | MEM[ADDR] <= temp; 40 | end 41 | end 42 | 43 | assign Q = MEM[ADDR]; 44 | 45 | `else 46 | 47 | 48 | 49 | `endif 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /VDP1/VDP1.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 20:24:58 February 04, 2021 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "20:24:58 February 04, 2021" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "VDP1" 31 | -------------------------------------------------------------------------------- /VDP1/VDP1.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 20:24:58 February 04, 2021 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # VDP1_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEBA6U23I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY VDP1 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:24:58 FEBRUARY 04, 2021" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 50 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 51 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 53 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 54 | set_global_assignment -name SYSTEMVERILOG_FILE VDP1.sv 55 | set_global_assignment -name SYSTEMVERILOG_FILE VDP1_pkg.sv 56 | set_global_assignment -name SYSTEMVERILOG_FILE COL_TBL.sv 57 | set_global_assignment -name SYSTEMVERILOG_FILE VDP1_tb.sv 58 | set_global_assignment -name SYSTEMVERILOG_FILE RAM_tb.sv 59 | set_global_assignment -name QIP_FILE VDP1_FIFO.qip 60 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top 61 | set_global_assignment -name QIP_FILE DIV.qip -------------------------------------------------------------------------------- /VDP1/VDP1_pkg.sv: -------------------------------------------------------------------------------- 1 | package VDP1_PKG; 2 | 3 | //Registers 4 | typedef struct packed //WO,100000 5 | { 6 | bit [11: 0] UNUSED; 7 | bit VBE; 8 | bit [ 2: 0] TVM; 9 | } TVMR_t; 10 | parameter bit [15:0] TVMR_MASK = 16'h000F; 11 | 12 | typedef struct packed //WO,100002 13 | { 14 | bit [10: 0] UNUSED; 15 | bit EOS; 16 | bit DIE; 17 | bit DIL; 18 | bit FCM; 19 | bit FCT; 20 | } FBCR_t; 21 | parameter bit [15:0] FBCR_MASK = 16'h001F; 22 | 23 | typedef struct packed //WO,100004 24 | { 25 | bit [13: 0] UNUSED; 26 | bit [ 1: 0] PTM; 27 | } PTMR_t; 28 | parameter bit [15:0] PTMR_MASK = 16'h0003; 29 | 30 | typedef bit [15:0] EWDR_t; //WO,100006 31 | parameter bit [15:0] EWDR_MASK = 16'hFFFF; 32 | 33 | typedef struct packed //WO,100008 34 | { 35 | bit UNUSED; 36 | bit [ 8: 3] X1; 37 | bit [ 8: 0] Y1; 38 | } EWLR_t; 39 | parameter bit [15:0] EWLR_MASK = 16'h7FFF; 40 | 41 | typedef struct packed //WO,10000A 42 | { 43 | bit [ 9: 3] X3; 44 | bit [ 8: 0] Y3; 45 | } EWRR_t; 46 | parameter bit [15:0] EWRR_MASK = 16'hFFFF; 47 | 48 | typedef bit [15:0] ENDR_t; //WO,10000C 49 | parameter bit [15:0] ENDR_MASK = 16'h0000; 50 | 51 | typedef struct packed //RO,100010 52 | { 53 | bit [13: 0] UNUSED; 54 | bit CEF; 55 | bit BEF; 56 | } EDSR_t; 57 | parameter bit [15:0] EDSR_MASK = 16'h0003; 58 | 59 | typedef bit [15:0] LOPR_t; //RO,100012 60 | parameter bit [15:0] LOPR_MASK = 16'hFFFC; 61 | 62 | typedef bit [15:0] COPR_t; //RO,100014 63 | parameter bit [15:0] COPR_MASK = 16'hFFFC; 64 | 65 | typedef struct packed //RO,100016 66 | { 67 | bit [ 3: 0] VER; 68 | bit [ 2: 0] UNUSED; 69 | bit PTM1; 70 | bit EOS; 71 | bit DIE; 72 | bit DIL; 73 | bit FCM; 74 | bit VBE; 75 | bit [ 2: 0] TVM; 76 | } MODR_t; 77 | parameter bit [15:0] MODR_MASK = 16'hF1FF; 78 | 79 | //Command tables 80 | typedef struct packed //00 81 | { 82 | bit END; 83 | bit [ 2: 0] JP; 84 | bit [ 3: 0] ZP; 85 | bit [ 1: 0] UNUSED; 86 | bit [ 1: 0] DIR; 87 | bit [ 3: 0] COMM; 88 | } CMDCTRL_t; 89 | parameter bit [15:0] CMDCTRL_MASK = 16'hFF3F; 90 | 91 | typedef bit [15:0] CMDLINK_t; //02 92 | parameter bit [15:0] CMDLINK_MASK = 16'hFFFC; 93 | 94 | typedef struct packed //04 95 | { 96 | bit MON; 97 | bit [ 1: 0] UNUSED; 98 | bit HSS; 99 | bit PCLP; 100 | bit CLIP; 101 | bit CMOD; 102 | bit MESH; 103 | bit ECD; 104 | bit SPD; 105 | bit [ 2: 0] CM; 106 | bit [ 2: 0] CCB; 107 | } CMDPMOD_t; 108 | parameter bit [15:0] CMDPMOD_MASK = 16'h9FFF; 109 | 110 | typedef bit [15:0] CMDCOLR_t; //06 111 | parameter bit [15:0] CMDCOLR_MASK = 16'hFFFF; 112 | 113 | typedef bit [15:0] CMDSRCA_t; //08 114 | parameter bit [15:0] CMDSRCA_MASK = 16'hFFFF; 115 | 116 | typedef struct packed //0A 117 | { 118 | bit [ 1: 0] UNUSED; 119 | bit [ 8: 3] SX; 120 | bit [ 7: 0] SY; 121 | } CMDSIZE_t; 122 | parameter bit [15:0] CMDSIZE_MASK = 16'h3FFF; 123 | 124 | typedef struct packed //0C-1A 125 | { 126 | bit [ 4: 0] EXT; 127 | bit [10: 0] COORD; 128 | } CMDCRD_t; 129 | parameter bit [15:0] CMDCRD_MASK = 16'hFFFF; 130 | 131 | typedef bit [15:0] CMDGRDA_t; //1C 132 | parameter bit [15:0] CMDGRDA_MASK = 16'hFFFF; 133 | 134 | typedef struct packed 135 | { 136 | CMDCTRL_t CMDCTRL; //00 137 | CMDLINK_t CMDLINK; //02 138 | CMDPMOD_t CMDPMOD; //04 139 | CMDCOLR_t CMDCOLR; //06 140 | CMDSRCA_t CMDSRCA; //08 141 | CMDSIZE_t CMDSIZE; //0A 142 | CMDCRD_t CMDXA; //0C 143 | CMDCRD_t CMDYA; //0E 144 | CMDCRD_t CMDXB; //10 145 | CMDCRD_t CMDYB; //12 146 | CMDCRD_t CMDXC; //14 147 | CMDCRD_t CMDYC; //16 148 | CMDCRD_t CMDXD; //18 149 | CMDCRD_t CMDYD; //1A 150 | CMDGRDA_t CMDGRDA; //1C 151 | bit [15: 0] UNUSED; //1E 152 | } CMDTBL_t; 153 | 154 | //Command value 155 | parameter CMD_NSPR = 4'h0; //Normal sprite draw 156 | parameter CMD_SSPR = 4'h1; //Scaled sprite draw 157 | parameter CMD_DSPR = 4'h2; //Distorted sprite draw 158 | parameter CMD_POLY = 4'h4; //Polygon draw 159 | parameter CMD_PLIN = 4'h5; //Polyline draw 160 | parameter CMD_LINE = 4'h6; //Line draw 161 | parameter CMD_UCLIP = 4'h8; //Set user clipping coordinate 162 | parameter CMD_SCLIP = 4'h9; //Set system clipping coordinate 163 | parameter CMD_LCORD = 4'hA; //Set local coordinate 164 | 165 | 166 | typedef struct packed 167 | { 168 | bit [10: 0] X1; 169 | bit [10: 0] Y1; 170 | bit [10: 0] X2; 171 | bit [10: 0] Y2; 172 | } Clip_t; 173 | parameter Clip_t CLIP_NULL = {11'h000,11'h000,11'h000,11'h000}; 174 | 175 | typedef struct packed 176 | { 177 | bit [10: 0] X; 178 | bit [10: 0] Y; 179 | } Coord_t; 180 | parameter Coord_t COORD_NULL = {11'h000,11'h000}; 181 | 182 | 183 | typedef struct packed 184 | { 185 | bit [10: 0] X; 186 | bit [10: 0] Y; 187 | } Vertex_t; 188 | parameter Vertex_t VERT_NULL = {11'h000,11'h000}; 189 | 190 | function bit [18:1] SprAddr(input bit [16:3] OFFSY, input CMDSRCA_t CMDSRCA, input bit [2:0] CM); 191 | bit [18:1] ADDR; 192 | 193 | case (CM) 194 | 3'b000, 195 | 3'b001: ADDR = {CMDSRCA,2'b00} + {3'b000,OFFSY,1'b0}; 196 | 3'b010, 197 | 3'b011, 198 | 3'b100: ADDR = {CMDSRCA,2'b00} + {2'b00,OFFSY,2'b00}; 199 | default: ADDR = {CMDSRCA[15:1],1'b0,2'b00} + {1'b0,OFFSY,3'b000}; 200 | endcase 201 | return ADDR; 202 | endfunction 203 | 204 | typedef struct packed 205 | { 206 | bit [15: 0] C; 207 | bit TP; 208 | bit EC; 209 | } Pattern_t; 210 | parameter Pattern_t PATTERN_NULL = {16'h0000,1'b0,1'b0}; 211 | 212 | function Pattern_t GetPattern(input bit [15:0] DATA, input bit [2:0] CM, input bit [1:0] OFFSX); 213 | bit [15:0] C; 214 | bit TP; 215 | bit EC; 216 | 217 | case (CM) 218 | 3'b000, 219 | 3'b001: 220 | case (OFFSX) 221 | 2'b00: begin C = {12'h000,DATA[15:12]}; TP = ~|DATA[15:12]; EC = &DATA[15:12]; end 222 | 2'b01: begin C = {12'h000,DATA[11: 8]}; TP = ~|DATA[11: 8]; EC = &DATA[11: 8]; end 223 | 2'b10: begin C = {12'h000,DATA[ 7: 4]}; TP = ~|DATA[ 7: 4]; EC = &DATA[ 7: 4]; end 224 | 2'b11: begin C = {12'h000,DATA[ 3: 0]}; TP = ~|DATA[ 3: 0]; EC = &DATA[ 3: 0]; end 225 | endcase 226 | 3'b010, 227 | 3'b011, 228 | 3'b100: 229 | case (OFFSX[1]) 230 | 1'b0: begin C = {8'h00,DATA[15: 8]}; TP = ~|DATA[15: 8]; EC = &DATA[15: 8]; end 231 | 1'b1: begin C = {8'h00,DATA[ 7: 0]}; TP = ~|DATA[ 7: 0]; EC = &DATA[ 7: 0]; end 232 | endcase 233 | default: begin C = DATA; TP = ~DATA[15]; EC = (DATA == 16'h7FFF); end 234 | endcase 235 | 236 | return {C,TP,EC}; 237 | endfunction 238 | 239 | typedef struct packed 240 | { 241 | bit [ 4: 0] B; 242 | bit [ 4: 0] G; 243 | bit [ 4: 0] R; 244 | } RGB_t; 245 | 246 | function RGB_t ColorHalf(input RGB_t CA); 247 | RGB_t CH; 248 | 249 | CH.R = {1'b0,CA.R[4:1]}; 250 | CH.G = {1'b0,CA.G[4:1]}; 251 | CH.B = {1'b0,CA.B[4:1]}; 252 | return CH; 253 | endfunction 254 | 255 | function RGB_t ColorAdd(input RGB_t CA, input RGB_t CB); 256 | RGB_t CR; 257 | 258 | CR.R = CA.R + CB.R; 259 | CR.G = CA.G + CB.G; 260 | CR.B = CA.B + CB.B; 261 | return CR; 262 | endfunction 263 | 264 | function RGB_t GouraudAdd(input RGB_t CO, input RGB_t CG); 265 | bit [6:0] SUMR,SUMG,SUMB; 266 | RGB_t CR; 267 | 268 | SUMR = {2'b00,CO.R} + {2'b00,CG.R} - 7'h10; 269 | SUMG = {2'b00,CO.G} + {2'b00,CG.G} - 7'h10; 270 | SUMB = {2'b00,CO.B} + {2'b00,CG.B} - 7'h10; 271 | 272 | CR.R = SUMR[6:5] == 2'b11 ? 5'h00 : SUMR[6:5] == 2'b01 ? 5'h1F : SUMR[4:0]; 273 | CR.G = SUMG[6:5] == 2'b11 ? 5'h00 : SUMG[6:5] == 2'b01 ? 5'h1F : SUMG[4:0]; 274 | CR.B = SUMB[6:5] == 2'b11 ? 5'h00 : SUMB[6:5] == 2'b01 ? 5'h1F : SUMB[4:0]; 275 | 276 | return CR; 277 | endfunction 278 | 279 | function bit [15:0] ColorCalc(input bit [15:0] ORIG, input bit [15:0] BACK, input bit [14:0] CG, input bit [2:0] CCB, input bit MON); 280 | RGB_t GOUR; 281 | RGB_t ORIG_HALF,ORIG_ONE; 282 | RGB_t GOUR_HALF,GOUR_ONE; 283 | RGB_t BACK_HALF,BACK_ONE; 284 | RGB_t A,B,S; 285 | bit MSB; 286 | 287 | GOUR = GouraudAdd(ORIG[14:0],CG); 288 | 289 | ORIG_HALF = ColorHalf(ORIG[14:0]); 290 | ORIG_ONE = ORIG[14:0]; 291 | GOUR_HALF = ColorHalf(GOUR); 292 | GOUR_ONE = GOUR; 293 | BACK_HALF = ColorHalf(BACK[14:0]); 294 | BACK_ONE = BACK[14:0]; 295 | 296 | case (CCB) 297 | 3'b000: begin A = ORIG_ONE; B = '0; MSB = ORIG[15]; end 298 | 3'b001: begin A = '0; B = BACK[15] ? BACK_HALF : BACK_ONE; MSB = BACK[15]; end 299 | 3'b010: begin A = ORIG_HALF; B = '0; MSB = ORIG[15]; end 300 | 3'b011: begin A = BACK[15] ? ORIG_HALF : ORIG_ONE; B = BACK[15] ? BACK_HALF : '0; MSB = BACK[15] | ORIG[15]; end 301 | 3'b100: begin A = GOUR_ONE; B = '0; MSB = ORIG[15]; end 302 | 3'b101: begin A = '0; B = BACK_ONE; MSB = BACK[15]; end 303 | 3'b110: begin A = GOUR_HALF; B = '0; MSB = ORIG[15]; end 304 | 3'b111: begin A = BACK[15] ? GOUR_HALF : GOUR_ONE; B = BACK[15] ? BACK_HALF : '0; MSB = BACK[15] | ORIG[15]; end 305 | endcase 306 | S = ColorAdd(A,B); 307 | 308 | return {MON|MSB,S}; 309 | endfunction 310 | 311 | function bit [10:0] Abs(input bit [11:0] C); 312 | bit [11:0] abs; 313 | 314 | abs = $signed(C) >= 0 ? $signed(C) : -$signed(C); 315 | return abs[10:0]; 316 | endfunction 317 | 318 | endpackage 319 | -------------------------------------------------------------------------------- /VDP1/VDP1_tb.sv: -------------------------------------------------------------------------------- 1 | module VDP1_tb; 2 | 3 | bit CLK; 4 | bit RST_N; 5 | bit CE_R, CE_F; 6 | 7 | always #5 CLK = ~CLK; 8 | 9 | initial begin 10 | RST_N = 0; 11 | #12 RST_N = 1; 12 | end 13 | 14 | always @(posedge CLK) begin 15 | CE_R <= ~CE_R; 16 | end 17 | assign CE_F = ~CE_R; 18 | 19 | bit [18:1] VRAM_A; 20 | bit [15:0] VRAM_D; 21 | bit [15:0] VRAM_Q; 22 | bit [1:0] VRAM_WE; 23 | bit VRAM_RD; 24 | bit [15:0] RA1_DO; 25 | bit VTIM_N; 26 | 27 | bit [17:1] FB0_A,FB1_A; 28 | bit [15:0] FB0_D,FB1_D; 29 | bit [15:0] FB0_Q,FB1_Q; 30 | bit FB0_WE,FB1_WE; 31 | 32 | initial begin 33 | VTIM_N = 1; 34 | 35 | #100 36 | VTIM_N = 0; 37 | #100 38 | VTIM_N = 1; 39 | end 40 | 41 | VDP1 VDP1 42 | ( 43 | .CLK(CLK), 44 | .RST_N(RST_N), 45 | .CE_R(CE_R), 46 | .CE_F(CE_F), 47 | 48 | .RES_N(1'b1), 49 | 50 | .DI('0), 51 | .DO(), 52 | .CS_N(1'b1), 53 | .AD_N(1'b1), 54 | .DTEN_N(1'b1), 55 | .WE_N(2'b11), 56 | .RDY_N(), 57 | 58 | .HTIM_N(1'b1), 59 | .VTIM_N(VTIM_N), 60 | 61 | .VRAM_A(VRAM_A), 62 | .VRAM_D(VRAM_D), 63 | .VRAM_WE(VRAM_WE), 64 | .VRAM_RD(VRAM_RD), 65 | .VRAM_Q(VRAM_Q), 66 | .VRAM_RDY(1'b1), 67 | 68 | .FB0_A(FB0_A), 69 | .FB0_D(FB0_D), 70 | .FB0_WE(FB0_WE), 71 | .FB0_RD(), 72 | .FB0_Q(FB0_Q), 73 | 74 | .FB1_A(FB1_A), 75 | .FB1_D(FB1_D), 76 | .FB1_WE(FB1_WE), 77 | .FB1_RD(), 78 | .FB1_Q(FB1_Q) 79 | ); 80 | 81 | RAM_tb #(18,16,"vram.txt") VRAM(CLK, VRAM_A, VRAM_D, 1'b1, VRAM_WE, VRAM_Q); 82 | RAM_tb #(17,16," ") FB0(CLK, FB0_A, FB0_D, 1'b1, {2{FB0_WE}}, FB0_Q); 83 | RAM_tb #(17,16," ") FB1(CLK, FB1_A, FB1_D, 1'b1, {2{FB1_WE}}, FB1_Q); 84 | 85 | 86 | 87 | endmodule 88 | 89 | -------------------------------------------------------------------------------- /VDP1/vram.bin: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/VDP1/vram.bin -------------------------------------------------------------------------------- /VDP1/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /VDP1_tb/VDP1/CE_R 4 | add wave -noupdate /VDP1_tb/VDP1/CE_F 5 | add wave -noupdate /VDP1_tb/VDP1/VRAM_A 6 | add wave -noupdate /VDP1_tb/VDP1/VRAM_D 7 | add wave -noupdate /VDP1_tb/VDP1/VRAM_Q 8 | add wave -noupdate /VDP1_tb/VDP1/VRAM_WE 9 | add wave -noupdate /VDP1_tb/VDP1/VRAM_RD 10 | add wave -noupdate /VDP1_tb/VDP1/CMD_ST 11 | add wave -noupdate /VDP1_tb/VDP1/CMD_READ 12 | add wave -noupdate /VDP1_tb/VDP1/CMD_ADDR 13 | add wave -noupdate -expand -subitemconfig {/VDP1_tb/VDP1/CMD.CMDCTRL -expand} /VDP1_tb/VDP1/CMD 14 | add wave -noupdate /VDP1_tb/VDP1/EDSR.CEF 15 | add wave -noupdate /VDP1_tb/VDP1/COPR 16 | add wave -noupdate /VDP1_tb/VDP1/SYS_CLIP 17 | add wave -noupdate /VDP1_tb/VDP1/USR_CLIP 18 | add wave -noupdate /VDP1_tb/VDP1/LOC_COORD 19 | add wave -noupdate /VDP1_tb/VDP1/VRAM_ST 20 | add wave -noupdate /VDP1_tb/VDP1/VRAM_DONE 21 | add wave -noupdate /VDP1_tb/VDP1/CMD_JRET 22 | add wave -noupdate /VDP1_tb/VDP1/SPR_X 23 | add wave -noupdate /VDP1_tb/VDP1/SPR_Y 24 | add wave -noupdate /VDP1_tb/VDP1/DRAW_X 25 | add wave -noupdate /VDP1_tb/VDP1/DRAW_Y 26 | add wave -noupdate /VDP1_tb/VDP1/SCLIP 27 | add wave -noupdate /VDP1_tb/VDP1/UCLIP 28 | add wave -noupdate /VDP1_tb/VDP1/FB_DRAW_A 29 | add wave -noupdate /VDP1_tb/VDP1/FB_DRAW_D 30 | add wave -noupdate /VDP1_tb/VDP1/FB_DRAW_WE 31 | add wave -noupdate /VDP1_tb/VDP1/SPR_PAT 32 | add wave -noupdate /VDP1_tb/VDP1/CLT_RA 33 | TreeUpdate [SetDefaultTree] 34 | WaveRestoreCursors {{Cursor 1} {8558665 ns} 0} 35 | quietly wave cursor active 1 36 | configure wave -namecolwidth 150 37 | configure wave -valuecolwidth 100 38 | configure wave -justifyvalue left 39 | configure wave -signalnamewidth 0 40 | configure wave -snapdistance 10 41 | configure wave -datasetprefix 0 42 | configure wave -rowmargin 4 43 | configure wave -childrowmargin 2 44 | configure wave -gridoffset 0 45 | configure wave -gridperiod 1 46 | configure wave -griddelta 40 47 | configure wave -timeline 0 48 | configure wave -timelineunits us 49 | update 50 | WaveRestoreZoom {7783946 ns} {7787946 ns} 51 | -------------------------------------------------------------------------------- /VDP2/RAM_tb.sv: -------------------------------------------------------------------------------- 1 | module RAM_tb 2 | #( 3 | parameter addr_width = 8, 4 | parameter data_width = 8, 5 | parameter mem_sim_file = "" 6 | ) 7 | ( 8 | input CLK, 9 | 10 | input [addr_width-1:0] ADDR, 11 | input [data_width-1:0] DATA, 12 | input CS, 13 | input [data_width/8-1:0] WREN, 14 | output [data_width-1:0] Q 15 | ); 16 | 17 | // synopsys translate_off 18 | `define SIM 19 | // synopsys translate_on 20 | 21 | `ifdef SIM 22 | 23 | reg [data_width-1:0] MEM [2**addr_width]; 24 | 25 | initial begin 26 | MEM = '{2**addr_width{'0}}; 27 | $readmemh(mem_sim_file, MEM); 28 | end 29 | 30 | always @(posedge CLK) begin 31 | bit [data_width-1:0] temp; 32 | 33 | if (data_width > 0) temp[ 7: 0] = WREN[0] ? DATA[ 7: 0] : Q[ 7: 0]; 34 | if (data_width > 8) temp[15: 8] = WREN[1] ? DATA[15: 8] : Q[15: 8]; 35 | if (data_width > 16) temp[23:16] = WREN[2] ? DATA[23:16] : Q[23:16]; 36 | if (data_width > 24) temp[31:24] = WREN[3] ? DATA[31:24] : Q[31:24]; 37 | 38 | if (WREN && CS) begin 39 | MEM[ADDR] <= temp; 40 | end 41 | end 42 | 43 | assign Q = MEM[ADDR]; 44 | 45 | `else 46 | 47 | 48 | 49 | `endif 50 | 51 | endmodule 52 | -------------------------------------------------------------------------------- /VDP2/VDP2.qpf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 13:43:55 October 17, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | 25 | QUARTUS_VERSION = "17.1" 26 | DATE = "13:43:55 October 17, 2020" 27 | 28 | # Revisions 29 | 30 | PROJECT_REVISION = "VDP2" 31 | -------------------------------------------------------------------------------- /VDP2/VDP2.qsf: -------------------------------------------------------------------------------- 1 | # -------------------------------------------------------------------------- # 2 | # 3 | # Copyright (C) 2017 Intel Corporation. All rights reserved. 4 | # Your use of Intel Corporation's design tools, logic functions 5 | # and other software and tools, and its AMPP partner logic 6 | # functions, and any output files from any of the foregoing 7 | # (including device programming or simulation files), and any 8 | # associated documentation or information are expressly subject 9 | # to the terms and conditions of the Intel Program License 10 | # Subscription Agreement, the Intel Quartus Prime License Agreement, 11 | # the Intel FPGA IP License Agreement, or other applicable license 12 | # agreement, including, without limitation, that your use is for 13 | # the sole purpose of programming logic devices manufactured by 14 | # Intel and sold by Intel or its authorized distributors. Please 15 | # refer to the applicable agreement for further details. 16 | # 17 | # -------------------------------------------------------------------------- # 18 | # 19 | # Quartus Prime 20 | # Version 17.1.1 Internal Build 593 12/11/2017 SJ Standard Edition 21 | # Date created = 13:43:55 October 17, 2020 22 | # 23 | # -------------------------------------------------------------------------- # 24 | # 25 | # Notes: 26 | # 27 | # 1) The default values for assignments are stored in the file: 28 | # VDP2_assignment_defaults.qdf 29 | # If this file doesn't exist, see file: 30 | # assignment_defaults.qdf 31 | # 32 | # 2) Altera recommends that you do not modify this file. This 33 | # file is updated automatically by the Quartus Prime software 34 | # and any changes you make may be lost or overwritten. 35 | # 36 | # -------------------------------------------------------------------------- # 37 | 38 | 39 | set_global_assignment -name FAMILY "Cyclone V" 40 | set_global_assignment -name DEVICE 5CSEMA6F31I7 41 | set_global_assignment -name TOP_LEVEL_ENTITY VDP2 42 | set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.1.1 43 | set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:43:55 OCTOBER 17, 2020" 44 | set_global_assignment -name LAST_QUARTUS_VERSION "17.1.1 Standard Edition" 45 | set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files 46 | set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40" 47 | set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100 48 | set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 49 | set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top 50 | set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top 51 | set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top 52 | set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" 53 | set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" 54 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2.sv 55 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2_pal.sv 56 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2_pkg.sv 57 | set_global_assignment -name SYSTEMVERILOG_FILE RAM_tb.sv 58 | set_global_assignment -name SYSTEMVERILOG_FILE VDP2_tb.sv 59 | set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -------------------------------------------------------------------------------- /VDP2/VDP2.xlsx: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/VDP2/VDP2.xlsx -------------------------------------------------------------------------------- /VDP2/VDP2_MEM.sv: -------------------------------------------------------------------------------- 1 | module VDP2_PAL_RAM ( 2 | input CLK, 3 | 4 | input [ 9:0] ADDR_A, 5 | input [15:0] DATA_A, 6 | input [ 1:0] WREN_A, 7 | output [15:0] Q_A, 8 | 9 | input [ 9:0] ADDR_B, 10 | input [15:0] DATA_B, 11 | input [ 1:0] WREN_B, 12 | output [15:0] Q_B 13 | ); 14 | 15 | wire [15:0] sub_wire0; 16 | wire [15:0] sub_wire1; 17 | 18 | altsyncram altsyncram_component ( 19 | .clock0 (CLK), 20 | .wren_a (|WREN_A), 21 | .address_b (ADDR_B), 22 | .data_b (DATA_B), 23 | .wren_b (|WREN_B), 24 | .address_a (ADDR_A), 25 | .data_a (DATA_A), 26 | .q_a (sub_wire0), 27 | .q_b (sub_wire1), 28 | .aclr0 (1'b0), 29 | .aclr1 (1'b0), 30 | .addressstall_a (1'b0), 31 | .addressstall_b (1'b0), 32 | .byteena_a (WREN_A), 33 | .byteena_b (WREN_B), 34 | .clock1 (1'b1), 35 | .clocken0 (1'b1), 36 | .clocken1 (1'b1), 37 | .clocken2 (1'b1), 38 | .clocken3 (1'b1), 39 | .eccstatus (), 40 | .rden_a (1'b1), 41 | .rden_b (1'b1)); 42 | defparam 43 | altsyncram_component.address_reg_b = "CLOCK0", 44 | altsyncram_component.byteena_reg_b = "CLOCK0", 45 | altsyncram_component.byte_size = 8, 46 | altsyncram_component.clock_enable_input_a = "BYPASS", 47 | altsyncram_component.clock_enable_input_b = "BYPASS", 48 | altsyncram_component.clock_enable_output_a = "BYPASS", 49 | altsyncram_component.clock_enable_output_b = "BYPASS", 50 | altsyncram_component.indata_reg_b = "CLOCK0", 51 | altsyncram_component.intended_device_family = "Cyclone V", 52 | altsyncram_component.lpm_type = "altsyncram", 53 | altsyncram_component.numwords_a = 1024, 54 | altsyncram_component.numwords_b = 1024, 55 | altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", 56 | altsyncram_component.outdata_aclr_a = "NONE", 57 | altsyncram_component.outdata_aclr_b = "NONE", 58 | altsyncram_component.outdata_reg_a = "UNREGISTERED", 59 | altsyncram_component.outdata_reg_b = "UNREGISTERED", 60 | altsyncram_component.power_up_uninitialized = "FALSE", 61 | altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", 62 | altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", 63 | altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", 64 | altsyncram_component.widthad_a = 10, 65 | altsyncram_component.widthad_b = 10, 66 | altsyncram_component.width_a = 16, 67 | altsyncram_component.width_b = 16, 68 | altsyncram_component.width_byteena_a = 2, 69 | altsyncram_component.width_byteena_b = 2, 70 | altsyncram_component.wrcontrol_wraddress_reg_b = "CLOCK0"; 71 | 72 | assign Q_A = sub_wire0; 73 | assign Q_B = sub_wire1; 74 | 75 | endmodule 76 | 77 | module VDP2_WRITE_FIFO ( 78 | input CLK, 79 | input RST_N, 80 | 81 | input [33:0] DATA, 82 | input WRREQ, 83 | input RDREQ, 84 | output [33:0] Q, 85 | output EMPTY, 86 | output FULL, 87 | output LAST 88 | ); 89 | 90 | wire [33: 0] sub_wire0; 91 | bit [ 2: 0] RADDR; 92 | bit [ 2: 0] WADDR; 93 | bit [ 3: 0] AMOUNT; 94 | 95 | always @(posedge CLK or negedge RST_N) begin 96 | if (!RST_N) begin 97 | AMOUNT <= '0; 98 | RADDR <= '0; 99 | WADDR <= '0; 100 | end 101 | else begin 102 | if (WRREQ && !AMOUNT[3]) begin 103 | WADDR <= WADDR + 3'd1; 104 | end 105 | if (RDREQ && AMOUNT) begin 106 | RADDR <= RADDR + 3'd1; 107 | end 108 | 109 | if (WRREQ && !RDREQ && !AMOUNT[3]) begin 110 | AMOUNT <= AMOUNT + 4'd1; 111 | end else if (!WRREQ && RDREQ && AMOUNT) begin 112 | AMOUNT <= AMOUNT - 4'd1; 113 | end 114 | end 115 | end 116 | assign EMPTY = ~|AMOUNT; 117 | assign FULL = AMOUNT[3]; 118 | assign LAST = (AMOUNT == 4'd1); 119 | 120 | altdpram altdpram_component ( 121 | .data (DATA), 122 | .inclock (CLK), 123 | .rdaddress (RADDR), 124 | .wraddress (WADDR), 125 | .wren (WRREQ), 126 | .q (sub_wire0), 127 | .aclr (1'b0), 128 | .byteena (1'b1), 129 | .inclocken (1'b1), 130 | .rdaddressstall (1'b0), 131 | .rden (1'b1), 132 | // .sclr (1'b0), 133 | .wraddressstall (1'b0)); 134 | defparam 135 | altdpram_component.indata_aclr = "OFF", 136 | altdpram_component.indata_reg = "INCLOCK", 137 | altdpram_component.intended_device_family = "Cyclone V", 138 | altdpram_component.lpm_type = "altdpram", 139 | altdpram_component.outdata_aclr = "OFF", 140 | altdpram_component.outdata_reg = "UNREGISTERED", 141 | altdpram_component.ram_block_type = "MLAB", 142 | altdpram_component.rdaddress_aclr = "OFF", 143 | altdpram_component.rdaddress_reg = "UNREGISTERED", 144 | altdpram_component.rdcontrol_aclr = "OFF", 145 | altdpram_component.rdcontrol_reg = "UNREGISTERED", 146 | altdpram_component.read_during_write_mode_mixed_ports = "CONSTRAINED_DONT_CARE", 147 | altdpram_component.width = 34, 148 | altdpram_component.widthad = 3, 149 | altdpram_component.width_byteena = 1, 150 | altdpram_component.wraddress_aclr = "OFF", 151 | altdpram_component.wraddress_reg = "INCLOCK", 152 | altdpram_component.wrcontrol_aclr = "OFF", 153 | altdpram_component.wrcontrol_reg = "INCLOCK"; 154 | 155 | assign Q = sub_wire0; 156 | 157 | endmodule 158 | -------------------------------------------------------------------------------- /VDP2/VDP2_tb.sv: -------------------------------------------------------------------------------- 1 | module VDP2_tb; 2 | 3 | bit CLK; 4 | bit RST_N; 5 | bit CE_R, CE_F; 6 | 7 | always #5 CLK = ~CLK; 8 | 9 | initial begin 10 | RST_N = 0; 11 | #12 RST_N = 1; 12 | end 13 | 14 | always @(posedge CLK) begin 15 | CE_R <= ~CE_R; 16 | end 17 | assign CE_F = ~CE_R; 18 | 19 | bit [19:1] RA0_A; 20 | bit [15:0] RA0_DI; 21 | bit [15:0] RA0_DO; 22 | bit [19:1] RA1_A; 23 | bit [15:0] RA1_DI; 24 | bit [15:0] RA1_DO; 25 | VDP2 VDP2 26 | ( 27 | .CLK(CLK), 28 | .RST_N(RST_N), 29 | .CE_R(CE_R), 30 | .CE_F(CE_F), 31 | 32 | .RES_N(1'b1), 33 | 34 | .DI('0), 35 | .DO(), 36 | .CS_N(1'b1), 37 | .WE_N(1'b1), 38 | .RD_N(1'b1), 39 | 40 | .RA0_A(RA0_A), 41 | .RA0_DI(RA0_DI), 42 | .RA1_A(RA1_A), 43 | .RA1_DI(RA1_DI) 44 | ); 45 | 46 | assign RA0_DO = '0; 47 | assign RA1_DO = '0; 48 | 49 | RAM_tb #(19,16,"vram_a0.txt") VRAM_A0(CLK, RA0_A, RA0_DO, 1'b0, 2'b00, RA0_DI); 50 | RAM_tb #(19,16,"vram_a1.txt") VRAM_A1(CLK, RA1_A, RA1_DO, 1'b0, 2'b00, RA1_DI); 51 | 52 | 53 | 54 | endmodule 55 | 56 | -------------------------------------------------------------------------------- /VDP2/vsim.wlf: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srg320/Saturn/19ab08424136d5506bc1952d921be94d46930e02/VDP2/vsim.wlf -------------------------------------------------------------------------------- /VDP2/wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /VDP2_tb/VDP2/CLK 4 | add wave -noupdate /VDP2_tb/VDP2/HS_N 5 | add wave -noupdate /VDP2_tb/VDP2/VS_N 6 | add wave -noupdate /VDP2_tb/VDP2/HBL_N 7 | add wave -noupdate /VDP2_tb/VDP2/VBL_N 8 | add wave -noupdate /VDP2_tb/VDP2/DOT_CE 9 | add wave -noupdate {/VDP2_tb/VDP2/VA_PIPE[0].H_CNT} 10 | add wave -noupdate {/VDP2_tb/VDP2/VA_PIPE[0].V_CNT} 11 | add wave -noupdate /VDP2_tb/VDP2/ACCESS_TIME 12 | add wave -noupdate -expand {/VDP2_tb/VDP2/VA_PIPE[0]} 13 | add wave -noupdate /VDP2_tb/VDP2/N0CH_ADDR_LSB 14 | add wave -noupdate -expand {/VDP2_tb/VDP2/VA_PIPE[1]} 15 | add wave -noupdate /VDP2_tb/VDP2/VRAMA0_ADDR 16 | add wave -noupdate /VDP2_tb/VDP2/VRAMA1_ADDR 17 | add wave -noupdate /VDP2_tb/VDP2/RA0_DI 18 | add wave -noupdate /VDP2_tb/VDP2/RA1_DI 19 | add wave -noupdate /VDP2_tb/VDP2/PN0 20 | add wave -noupdate -expand /VDP2_tb/VDP2/CD0 21 | add wave -noupdate /VDP2_tb/VDP2/DCOL 22 | add wave -noupdate /VDP2_tb/VDP2/R 23 | add wave -noupdate /VDP2_tb/VDP2/G 24 | add wave -noupdate /VDP2_tb/VDP2/B 25 | TreeUpdate [SetDefaultTree] 26 | WaveRestoreCursors {{Cursor 1} {731 ns} 0} 27 | quietly wave cursor active 1 28 | configure wave -namecolwidth 150 29 | configure wave -valuecolwidth 100 30 | configure wave -justifyvalue left 31 | configure wave -signalnamewidth 0 32 | configure wave -snapdistance 10 33 | configure wave -datasetprefix 0 34 | configure wave -rowmargin 4 35 | configure wave -childrowmargin 2 36 | configure wave -gridoffset 0 37 | configure wave -gridperiod 1 38 | configure wave -griddelta 40 39 | configure wave -timeline 0 40 | configure wave -timelineunits us 41 | update 42 | WaveRestoreZoom {1059 ns} {2067 ns} 43 | -------------------------------------------------------------------------------- /wave.do: -------------------------------------------------------------------------------- 1 | onerror {resume} 2 | quietly WaveActivateNextPane {} 0 3 | add wave -noupdate /Saturn_tb/Saturn/CE_R 4 | add wave -noupdate /Saturn_tb/Saturn/CE_F 5 | add wave -noupdate /Saturn_tb/Saturn/MSH/A 6 | add wave -noupdate /Saturn_tb/Saturn/MSH/DI 7 | add wave -noupdate /Saturn_tb/Saturn/MSH/DO 8 | add wave -noupdate /Saturn_tb/Saturn/MSH/CS0_N 9 | add wave -noupdate /Saturn_tb/Saturn/MSH/CS1_N 10 | add wave -noupdate /Saturn_tb/Saturn/MSH/CS2_N 11 | add wave -noupdate /Saturn_tb/Saturn/MSH/CS3_N 12 | add wave -noupdate /Saturn_tb/Saturn/MSH/WE_N 13 | add wave -noupdate /Saturn_tb/Saturn/MSH/RD_N 14 | add wave -noupdate /Saturn_tb/Saturn/MSH/NMI_N 15 | add wave -noupdate /Saturn_tb/Saturn/MSH/IRL_N 16 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_A 17 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_DI 18 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_DO 19 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_WR 20 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_BA 21 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_REQ 22 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/BUS_WAIT 23 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/PC 24 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/INTI 25 | add wave -noupdate /Saturn_tb/Saturn/ROM_CS_N 26 | add wave -noupdate /Saturn_tb/Saturn/RAML_CS_N 27 | add wave -noupdate /Saturn_tb/Saturn/RAMH_CS_N 28 | add wave -noupdate /Saturn_tb/ramh/ADDR 29 | add wave -noupdate /Saturn_tb/ramh/DATA 30 | add wave -noupdate /Saturn_tb/ramh/CS 31 | add wave -noupdate /Saturn_tb/ramh/WREN 32 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/PIPE.EX 33 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/PIPE.MA 34 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/PIPE.WB 35 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/PIPE.WB2 36 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/ALU_A 37 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/ALU_B 38 | add wave -noupdate /Saturn_tb/Saturn/MSH/core/ALU_RES 39 | add wave -noupdate -expand /Saturn_tb/Saturn/MSH/core/regfile/GR 40 | add wave -noupdate /Saturn_tb/Saturn/SCU/DMA_ST 41 | add wave -noupdate /Saturn_tb/Saturn/SCU/BBUS_ST 42 | add wave -noupdate /Saturn_tb/Saturn/SCU/BCSS_N 43 | add wave -noupdate /Saturn_tb/Saturn/SCU/BADDT_N 44 | add wave -noupdate /Saturn_tb/Saturn/BA 45 | add wave -noupdate /Saturn_tb/Saturn/BD 46 | add wave -noupdate /Saturn_tb/Saturn/SCSP_RAM_A 47 | add wave -noupdate /Saturn_tb/Saturn/SCSP_RAM_D 48 | add wave -noupdate /Saturn_tb/Saturn/SCSP_RAM_WE 49 | add wave -noupdate /Saturn_tb/Saturn/SCSP_RAM_Q 50 | TreeUpdate [SetDefaultTree] 51 | WaveRestoreCursors {{Cursor 1} {187908388 ns} 0} 52 | quietly wave cursor active 1 53 | configure wave -namecolwidth 150 54 | configure wave -valuecolwidth 100 55 | configure wave -justifyvalue left 56 | configure wave -signalnamewidth 0 57 | configure wave -snapdistance 10 58 | configure wave -datasetprefix 0 59 | configure wave -rowmargin 4 60 | configure wave -childrowmargin 2 61 | configure wave -gridoffset 0 62 | configure wave -gridperiod 1 63 | configure wave -griddelta 40 64 | configure wave -timeline 0 65 | configure wave -timelineunits us 66 | update 67 | WaveRestoreZoom {187908203 ns} {187908459 ns} 68 | --------------------------------------------------------------------------------