├── Final_SOC ├── README.md ├── CORTEXM0INTEGRATION.v ├── cortexm0ds_logic.v ├── baudgen.v ├── counter.v ├── vga_image.v ├── dual_port_ram_sync.v ├── fifo.v ├── vga_sync.v ├── uart_rx.v ├── AHBDCD.v ├── AHBMUX.v ├── uart_tx.v ├── AHBUART.v ├── AHB2BRAM.v ├── AHBVGASYS.v ├── vga_console.v ├── AHBLITE_SYS.v └── font_rom.v ├── SimpleLEDSOC ├── images │ ├── v │ ├── MS2.png │ ├── mux.png │ ├── AHBLITEM.png │ ├── AHBLITES.png │ ├── Decoder.png │ ├── MasterS.png │ ├── SOCIMPL.jpeg │ ├── SlaveS.png │ ├── memorymap.png │ ├── Blockdiagram.png │ ├── Lab4_image1.png │ └── Global_Signals.png ├── cortexm0ds_logic.v ├── CORTEXM0INTEGRATION.v ├── VIVARDO_FILES │ ├── README.md │ └── AHBLITE_SYS.bit ├── AHBDCD.v ├── AHBMUX.v ├── code.hex ├── AHB2LED.v ├── AHB2BRAM.v ├── README.md ├── AHBLITE_SYS.v └── Arty_A7_Master.xdc ├── README.md └── LICENSE /Final_SOC/README.md: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /SimpleLEDSOC/images/v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Final_SOC/CORTEXM0INTEGRATION.v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /Final_SOC/cortexm0ds_logic.v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /SimpleLEDSOC/cortexm0ds_logic.v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /SimpleLEDSOC/CORTEXM0INTEGRATION.v: -------------------------------------------------------------------------------- 1 | 2 | -------------------------------------------------------------------------------- /SimpleLEDSOC/VIVARDO_FILES/README.md: -------------------------------------------------------------------------------- 1 | ### Vivardo Files 2 | -------------------------------------------------------------------------------- /SimpleLEDSOC/AHBDCD.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srimanthtenneti/SOC-Design-ARM-M0/HEAD/SimpleLEDSOC/AHBDCD.v -------------------------------------------------------------------------------- /SimpleLEDSOC/AHBMUX.v: -------------------------------------------------------------------------------- https://raw.githubusercontent.com/srimanthtenneti/SOC-Design-ARM-M0/HEAD/SimpleLEDSOC/AHBMUX.v -------------------------------------------------------------------------------- /SimpleLEDSOC/images/MS2.png: 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https://raw.githubusercontent.com/srimanthtenneti/SOC-Design-ARM-M0/HEAD/SimpleLEDSOC/VIVARDO_FILES/AHBLITE_SYS.bit -------------------------------------------------------------------------------- /README.md: -------------------------------------------------------------------------------- 1 | # SOC-Design-ARM-M0 2 | This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms. 3 | -------------------------------------------------------------------------------- /Final_SOC/baudgen.v: -------------------------------------------------------------------------------- 1 | 2 | module BAUDGEN 3 | ( 4 | input wire clk, 5 | input wire resetn, 6 | output wire baudtick 7 | ); 8 | 9 | 10 | reg [21:0] count_reg; 11 | wire [21:0] count_next; 12 | 13 | //Counter 14 | always @ (posedge clk, negedge resetn) 15 | begin 16 | if(!resetn) 17 | count_reg <= 0; 18 | else 19 | count_reg <= count_next; 20 | end 21 | 22 | 23 | //Baudrate = 19200 = 50Mhz/(163*16) 24 | assign count_next = ((count_reg == 162) ? 0 : count_reg + 1'b1); 25 | 26 | assign baudtick = ((count_reg == 162) ? 1'b1 : 1'b0); 27 | 28 | endmodule 29 | -------------------------------------------------------------------------------- /SimpleLEDSOC/code.hex: -------------------------------------------------------------------------------- 1 | 00003FFC 2 | 00000081 3 | 00000000 4 | 00000000 5 | 00000000 6 | 00000000 7 | 00000000 8 | 00000000 9 | 00000000 10 | 00000000 11 | 00000000 12 | 00000000 13 | 00000000 14 | 00000000 15 | 00000000 16 | 00000000 17 | 00000000 18 | 00000000 19 | 00000000 20 | 00000000 21 | 00000000 22 | 00000000 23 | 00000000 24 | 00000000 25 | 00000000 26 | 00000000 27 | 00000000 28 | 00000000 29 | 00000000 30 | 00000000 31 | 00000000 32 | 00000000 33 | 48074906 34 | 48076008 35 | D1FD1E40 36 | 48064903 37 | 48046008 38 | D1FD1E40 39 | 0000E7F2 40 | 50000000 41 | 00000055 42 | 002FFFFF 43 | 000000AA 44 | -------------------------------------------------------------------------------- /Final_SOC/counter.v: -------------------------------------------------------------------------------- 1 | `timescale 1ns / 1ps 2 | 3 | 4 | module GenericCounter( 5 | CLK, 6 | RESET, 7 | ENABLE_IN, 8 | TRIG_OUT, 9 | COUNT 10 | ); 11 | parameter COUNTER_WIDTH=4; 12 | parameter COUNTER_MAX=4; 13 | 14 | input CLK; 15 | input RESET; 16 | input ENABLE_IN; 17 | output TRIG_OUT; 18 | output [COUNTER_WIDTH-1:0] COUNT; 19 | 20 | reg [COUNTER_WIDTH-1:0] counter; 21 | reg triggerout; 22 | 23 | 24 | always@(posedge CLK)begin 25 | if (RESET) 26 | counter<=0; 27 | else begin 28 | if (ENABLE_IN) begin 29 | if (counter==(COUNTER_MAX)) 30 | counter<=0; 31 | else 32 | counter<=counter+1; 33 | end 34 | end 35 | end 36 | 37 | always@(posedge CLK)begin 38 | if (RESET) 39 | triggerout<=0; 40 | else begin 41 | if (ENABLE_IN && (counter==(COUNTER_MAX))) 42 | triggerout<=1; 43 | else 44 | triggerout<=0; 45 | end 46 | end 47 | 48 | assign COUNT=counter; 49 | assign TRIG_OUT=triggerout; 50 | 51 | endmodule -------------------------------------------------------------------------------- /Final_SOC/vga_image.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module vga_image( 5 | input wire clk, 6 | input wire resetn, 7 | input wire [9:0] pixel_x, 8 | input wire [9:0] pixel_y, 9 | input wire image_we, 10 | input wire [7:0] image_data, 11 | input wire [15:0] address, 12 | output wire [7:0] image_rgb 13 | ); 14 | 15 | 16 | wire [15:0] addr_r; 17 | wire [14:0] addr_w; 18 | wire [7:0] din; 19 | wire [7:0] dout; 20 | 21 | wire [9:0] img_x; 22 | wire [9:0] img_y; 23 | 24 | reg [15:0] address_reg; 25 | 26 | //buffer address = bus address -1 , as the first address is used for console 27 | always @(posedge clk) 28 | address_reg <= address-1; 29 | 30 | //Frame buffer 31 | dual_port_ram_sync 32 | #(.ADDR_WIDTH(15), .DATA_WIDTH(8)) 33 | uimage_ram 34 | ( .clk(clk), 35 | .reset_n(resetn), 36 | .we(image_we), 37 | .addr_a(addr_w), 38 | .addr_b(addr_r), 39 | .din_a(din), 40 | .dout_a(), 41 | .dout_b(dout) 42 | ); 43 | 44 | assign addr_w = address_reg[14:0]; 45 | assign din = image_data; 46 | 47 | assign img_x = pixel_x[9:0]-240; 48 | assign img_y = pixel_y[9:0]; 49 | 50 | assign addr_r = {1'b0,img_y[8:2], img_x[8:2]}; 51 | 52 | assign image_rgb = dout; 53 | 54 | 55 | 56 | endmodule 57 | -------------------------------------------------------------------------------- /Final_SOC/dual_port_ram_sync.v: -------------------------------------------------------------------------------- 1 | 2 | module dual_port_ram_sync 3 | #( 4 | parameter ADDR_WIDTH = 6, 5 | parameter DATA_WIDTH = 8 6 | ) 7 | ( 8 | input wire clk, 9 | input wire reset_n, 10 | input wire we, 11 | input wire [ADDR_WIDTH-1:0] addr_a, 12 | input wire [ADDR_WIDTH-1:0] addr_b, 13 | input wire [DATA_WIDTH-1:0] din_a, 14 | 15 | output wire [DATA_WIDTH-1:0] dout_a, 16 | output wire [DATA_WIDTH-1:0] dout_b 17 | ); 18 | 19 | reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0]; 20 | reg [ADDR_WIDTH-1:0] addr_a_reg; 21 | reg [ADDR_WIDTH-1:0] addr_b_reg; 22 | 23 | reg [ADDR_WIDTH:0] reset_addr; 24 | reg [1:0] reset_n_buf; 25 | 26 | always @ (posedge clk) 27 | begin 28 | // Clear each data when reset 29 | reset_n_buf = {reset_n_buf[0], reset_n}; 30 | if (reset_n_buf == 2'b10) 31 | begin 32 | reset_addr <= 0; 33 | end 34 | else if ((!we) && (reset_addr[ADDR_WIDTH] == 1'b0)) 35 | begin 36 | reset_addr <= reset_addr + 1; 37 | end 38 | 39 | if (we || (reset_addr[ADDR_WIDTH] == 1'b0)) 40 | ram[we ? addr_a : reset_addr] <= we ? din_a : {DATA_WIDTH{1'b0}}; 41 | addr_a_reg <= addr_a; 42 | addr_b_reg <= addr_b; 43 | end 44 | 45 | assign dout_a = ram[addr_a_reg]; 46 | assign dout_b = ram[addr_b_reg]; 47 | 48 | endmodule 49 | -------------------------------------------------------------------------------- /SimpleLEDSOC/AHB2LED.v: -------------------------------------------------------------------------------- 1 | module AHB2LED( 2 | //AHBLITE INTERFACE 3 | //Slave Select Signals 4 | input wire HSEL, 5 | //Global Signal 6 | input wire HCLK, 7 | input wire HRESETn, 8 | //Address, Control & Write Data 9 | input wire HREADY, 10 | input wire [31:0] HADDR, 11 | input wire [1:0] HTRANS, 12 | input wire HWRITE, 13 | input wire [2:0] HSIZE, 14 | 15 | input wire [31:0] HWDATA, 16 | // Transfer Response & Read Data 17 | output wire HREADYOUT, 18 | output wire [31:0] HRDATA, 19 | //LED Output 20 | output wire [7:0] LED 21 | ); 22 | 23 | //Address Phase Sampling Registers 24 | reg rHSEL; 25 | reg [31:0] rHADDR; 26 | reg [1:0] rHTRANS; 27 | reg rHWRITE; 28 | reg [2:0] rHSIZE; 29 | 30 | reg [7:0] rLED; 31 | 32 | //Address Phase Sampling 33 | always @(posedge HCLK or negedge HRESETn) 34 | begin 35 | if(!HRESETn) 36 | begin 37 | rHSEL <= 1'b0; 38 | rHADDR <= 32'h0; 39 | rHTRANS <= 2'b00; 40 | rHWRITE <= 1'b0; 41 | rHSIZE <= 3'b000; 42 | end 43 | else if(HREADY) 44 | begin 45 | rHSEL <= HSEL; 46 | rHADDR <= HADDR; 47 | rHTRANS <= HTRANS; 48 | rHWRITE <= HWRITE; 49 | rHSIZE <= HSIZE; 50 | end 51 | end 52 | 53 | //Data Phase data transfer 54 | always @(posedge HCLK or negedge HRESETn) 55 | begin 56 | if(!HRESETn) 57 | rLED <= 8'b0000_0000; 58 | else if(rHSEL & rHWRITE & rHTRANS[1]) 59 | rLED <= HWDATA[7:0]; 60 | end 61 | 62 | //Transfer Response 63 | assign HREADYOUT = 1'b1; //Single cycle Write & Read. Zero Wait state operations 64 | 65 | //Read Data 66 | assign HRDATA = {24'h0000_00,rLED}; 67 | 68 | assign LED = rLED; 69 | 70 | endmodule 71 | 72 | -------------------------------------------------------------------------------- /Final_SOC/fifo.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module FIFO #(parameter DWIDTH=8, AWIDTH=1) 5 | ( 6 | input wire clk, 7 | input wire resetn, 8 | input wire rd, 9 | input wire wr, 10 | input wire [DWIDTH-1:0] w_data, 11 | 12 | output wire empty, 13 | output wire full, 14 | output wire [DWIDTH-1:0] r_data 15 | ); 16 | 17 | //Internal Signal declarations 18 | 19 | reg [DWIDTH-1:0] array_reg [2**AWIDTH-1:0]; 20 | reg [AWIDTH-1:0] w_ptr_reg; 21 | reg [AWIDTH-1:0] w_ptr_next; 22 | reg [AWIDTH-1:0] w_ptr_succ; 23 | reg [AWIDTH-1:0] r_ptr_reg; 24 | reg [AWIDTH-1:0] r_ptr_next; 25 | reg [AWIDTH-1:0] r_ptr_succ; 26 | 27 | reg full_reg; 28 | reg empty_reg; 29 | reg full_next; 30 | 31 | 32 | 33 | 34 | 35 | reg empty_next; 36 | 37 | wire w_en; 38 | 39 | 40 | always @ (posedge clk) 41 | if(w_en) 42 | begin 43 | array_reg[w_ptr_reg] <= w_data; 44 | end 45 | 46 | assign r_data = array_reg[r_ptr_reg]; 47 | 48 | assign w_en = wr & ~full_reg; 49 | 50 | //State Machine 51 | always @ (posedge clk, negedge resetn) 52 | begin 53 | if(!resetn) 54 | begin 55 | w_ptr_reg <= 0; 56 | r_ptr_reg <= 0; 57 | full_reg <= 1'b0; 58 | empty_reg <= 1'b1; 59 | end 60 | else 61 | begin 62 | w_ptr_reg <= w_ptr_next; 63 | r_ptr_reg <= r_ptr_next; 64 | full_reg <= full_next; 65 | empty_reg <= empty_next; 66 | end 67 | end 68 | 69 | 70 | //Next State Logic 71 | always @* 72 | begin 73 | w_ptr_succ = w_ptr_reg + 1; 74 | r_ptr_succ = r_ptr_reg + 1; 75 | 76 | w_ptr_next = w_ptr_reg; 77 | r_ptr_next = r_ptr_reg; 78 | full_next = full_reg; 79 | empty_next = empty_reg; 80 | 81 | case({w_en,rd}) 82 | //2'b00: nop 83 | 2'b01: 84 | if(~empty_reg) 85 | begin 86 | r_ptr_next = r_ptr_succ; 87 | full_next = 1'b0; 88 | if (r_ptr_succ == w_ptr_reg) 89 | empty_next = 1'b1; 90 | end 91 | 2'b10: 92 | if(~full_reg) 93 | begin 94 | w_ptr_next = w_ptr_succ; 95 | empty_next = 1'b0; 96 | if (w_ptr_succ == r_ptr_reg) 97 | full_next = 1'b1; 98 | end 99 | 2'b11: 100 | begin 101 | w_ptr_next = w_ptr_succ; 102 | r_ptr_next = r_ptr_succ; 103 | end 104 | endcase 105 | end 106 | 107 | //Set Full and Empty 108 | 109 | assign full = full_reg; 110 | assign empty = empty_reg; 111 | 112 | endmodule 113 | 114 | 115 | 116 | 117 | 118 | -------------------------------------------------------------------------------- /Final_SOC/vga_sync.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | //END USER LICENCE AGREEMENT // 3 | 4 | 5 | module VGAInterface( 6 | input CLK, 7 | input [7:0] COLOUR_IN, 8 | output reg [7:0] cout, 9 | output reg hs, 10 | output reg vs, 11 | output reg [9:0] addrh, 12 | output reg [9:0] addrv 13 | ); 14 | 15 | 16 | // Time in Vertical Lines 17 | parameter VertTimeToPulseWidthEnd = 10'd2; 18 | parameter VertTimeToBackPorchEnd = 10'd31; 19 | parameter VertTimeToDisplayTimeEnd = 10'd511; 20 | parameter VertTimeToFrontPorchEnd = 10'd521; 21 | 22 | // Time in Horizontal Lines 23 | parameter HorzTimeToPulseWidthEnd = 10'd96; 24 | parameter HorzTimeToBackPorchEnd = 10'd144; 25 | parameter HorzTimeToDisplayTimeEnd = 10'd784; 26 | parameter HorzTimeToFrontPorchEnd = 10'd800; 27 | 28 | wire TrigHOut, TrigDiv; 29 | wire [9:0] HorzCount; 30 | wire [9:0] VertCount; 31 | 32 | //Divide the clock frequency 33 | GenericCounter #(.COUNTER_WIDTH(1), .COUNTER_MAX(1)) 34 | FreqDivider 35 | ( 36 | .CLK(CLK), 37 | .RESET(1'b0), 38 | .ENABLE_IN(1'b1), 39 | .TRIG_OUT(TrigDiv) 40 | ); 41 | 42 | //Horizontal counter 43 | GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(HorzTimeToFrontPorchEnd)) 44 | HorzAddrCounter 45 | ( 46 | .CLK(CLK), 47 | .RESET(1'b0), 48 | .ENABLE_IN(TrigDiv), 49 | .TRIG_OUT(TrigHOut), 50 | .COUNT(HorzCount) 51 | ); 52 | 53 | //Vertical counter 54 | GenericCounter #(.COUNTER_WIDTH(10), .COUNTER_MAX(VertTimeToFrontPorchEnd)) 55 | VertAddrCounter 56 | ( 57 | .CLK(CLK), 58 | .RESET(1'b0), 59 | .ENABLE_IN(TrigHOut), 60 | .COUNT(VertCount) 61 | ); 62 | 63 | //Synchronisation signals 64 | always@(posedge CLK) begin 65 | if(HorzCount= HorzTimeToBackPorchEnd ) && (HorzCount < HorzTimeToDisplayTimeEnd) ) && 79 | ( (VertCount >= VertTimeToBackPorchEnd ) && (VertCount < VertTimeToDisplayTimeEnd) ) ) 80 | cout <= COLOUR_IN; 81 | else 82 | cout <= 8'b00000000; 83 | end 84 | 85 | //output horizontal and vertical addresses 86 | always@(posedge CLK)begin 87 | if ((HorzCount>HorzTimeToBackPorchEnd)&&(HorzCountVertTimeToBackPorchEnd)&&(VertCount> 1; 100 | if(count_reg == 7) //8 data bits 101 | next_state = stop_st; 102 | else 103 | count_next = count_reg + 1; 104 | end 105 | else 106 | b_next = b_reg + 1; 107 | end 108 | 109 | stop_st: //send stop bit 110 | begin 111 | tx_next = 1'b1; 112 | if(b_tick) 113 | if(b_reg == 15) //one stop bit 114 | begin 115 | next_state = idle_st; 116 | tx_done = 1'b1; 117 | end 118 | else 119 | b_next = b_reg + 1; 120 | end 121 | endcase 122 | end 123 | 124 | assign tx = tx_reg; 125 | 126 | endmodule 127 | -------------------------------------------------------------------------------- /Final_SOC/AHBUART.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | 4 | module AHBUART( 5 | //AHB Signals 6 | input wire HCLK, 7 | input wire HRESETn, 8 | input wire [31:0] HADDR, 9 | input wire [1:0] HTRANS, 10 | input wire [31:0] HWDATA, 11 | input wire HWRITE, 12 | input wire HREADY, 13 | 14 | output wire HREADYOUT, 15 | output wire [31:0] HRDATA, 16 | 17 | input wire HSEL, 18 | 19 | //Serial Port Signals 20 | input wire RsRx, //Input from RS-232 21 | output wire RsTx, //Output to RS-232 22 | //UART Interrupt 23 | 24 | output wire uart_irq //Interrupt 25 | ); 26 | 27 | //Internal Signals 28 | 29 | //Data I/O between AHB and FIFO 30 | wire [7:0] uart_wdata; 31 | wire [7:0] uart_rdata; 32 | 33 | //Signals from TX/RX to FIFOs 34 | wire uart_wr; 35 | wire uart_rd; 36 | 37 | //wires between FIFO and TX/RX 38 | wire [7:0] tx_data; 39 | wire [7:0] rx_data; 40 | wire [7:0] status; 41 | 42 | //FIFO Status 43 | wire tx_full; 44 | wire tx_empty; 45 | wire rx_full; 46 | wire rx_empty; 47 | 48 | //UART status ticks 49 | wire tx_done; 50 | wire rx_done; 51 | 52 | //baud rate signal 53 | wire b_tick; 54 | 55 | //AHB Regs 56 | reg [1:0] last_HTRANS; 57 | reg [31:0] last_HADDR; 58 | reg last_HWRITE; 59 | reg last_HSEL; 60 | 61 | 62 | //Set Registers for AHB Address State 63 | always@ (posedge HCLK) 64 | begin 65 | if(HREADY) 66 | begin 67 | last_HTRANS <= HTRANS; 68 | last_HWRITE <= HWRITE; 69 | last_HSEL <= HSEL; 70 | last_HADDR <= HADDR; 71 | end 72 | end 73 | 74 | 75 | //If Read and FIFO_RX is empty - wait. 76 | assign HREADYOUT = ~tx_full; 77 | 78 | //UART write select 79 | assign uart_wr = last_HTRANS[1] & last_HWRITE & last_HSEL& (last_HADDR[7:0]==8'h00); 80 | //Only write last 8 bits of Data 81 | assign uart_wdata = HWDATA[7:0]; 82 | 83 | //UART read select 84 | assign uart_rd = last_HTRANS[1] & ~last_HWRITE & last_HSEL & (last_HADDR[7:0]==8'h00); 85 | 86 | 87 | assign HRDATA = (last_HADDR[7:0]==8'h00) ? {24'h0000_00,uart_rdata}:{24'h0000_00,status}; 88 | assign status = {6'b000000,tx_full,rx_empty}; 89 | 90 | assign uart_irq = ~rx_empty; 91 | 92 | //generate a fixed baud rate 19200bps 93 | BAUDGEN uBAUDGEN( 94 | .clk(HCLK), 95 | .resetn(HRESETn), 96 | .baudtick(b_tick) 97 | ); 98 | 99 | //Transmitter FIFO 100 | FIFO 101 | #(.DWIDTH(8), .AWIDTH(4)) 102 | uFIFO_TX 103 | ( 104 | .clk(HCLK), 105 | .resetn(HRESETn), 106 | .rd(tx_done), 107 | .wr(uart_wr), 108 | .w_data(uart_wdata[7:0]), 109 | .empty(tx_empty), 110 | .full(tx_full), 111 | .r_data(tx_data[7:0]) 112 | ); 113 | 114 | //Receiver FIFO 115 | FIFO 116 | #(.DWIDTH(8), .AWIDTH(4)) 117 | uFIFO_RX( 118 | .clk(HCLK), 119 | .resetn(HRESETn), 120 | .rd(uart_rd), 121 | .wr(rx_done), 122 | .w_data(rx_data[7:0]), 123 | .empty(rx_empty), 124 | .full(rx_full), 125 | .r_data(uart_rdata[7:0]) 126 | ); 127 | 128 | //UART receiver 129 | UART_RX uUART_RX( 130 | .clk(HCLK), 131 | .resetn(HRESETn), 132 | .b_tick(b_tick), 133 | .rx(RsRx), 134 | .rx_done(rx_done), 135 | .dout(rx_data[7:0]) 136 | ); 137 | 138 | //UART transmitter 139 | UART_TX uUART_TX( 140 | .clk(HCLK), 141 | .resetn(HRESETn), 142 | .tx_start(!tx_empty), 143 | .b_tick(b_tick), 144 | .d_in(tx_data[7:0]), 145 | .tx_done(tx_done), 146 | .tx(RsTx) 147 | ); 148 | 149 | 150 | 151 | endmodule 152 | -------------------------------------------------------------------------------- /Final_SOC/AHB2BRAM.v: -------------------------------------------------------------------------------- 1 | // --========================================================================-- 2 | // Version and Release Control Information: 3 | // 4 | // File Name : AHB2BRAM.v 5 | // File Revision : 1.60 6 | // 7 | // ---------------------------------------------------------------------------- 8 | // Purpose : Basic AHBLITE Internal Memory Default Size = 16KB 9 | // 10 | // --========================================================================-- 11 | module AHB2MEM 12 | #(parameter MEMWIDTH = 14) // SIZE[Bytes] = 2 ^ MEMWIDTH[Bytes] = 2 ^ MEMWIDTH / 4[Entries] 13 | ( 14 | //AHBLITE INTERFACE 15 | //Slave Select Signals 16 | input wire HSEL, 17 | //Global Signal 18 | input wire HCLK, 19 | input wire HRESETn, 20 | //Address, Control & Write Data 21 | input wire HREADY, 22 | input wire [31:0] HADDR, 23 | input wire [1:0] HTRANS, 24 | input wire HWRITE, 25 | input wire [2:0] HSIZE, 26 | 27 | input wire [31:0] HWDATA, 28 | // Transfer Response & Read Data 29 | output wire HREADYOUT, 30 | output reg [31:0] HRDATA 31 | ); 32 | 33 | assign HREADYOUT = 1'b1; // Always ready 34 | 35 | // Memory Array 36 | reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)]; 37 | 38 | initial 39 | begin 40 | $readmemh("code.hex", memory); 41 | end 42 | 43 | // Registers to store Adress Phase Signals 44 | reg APhase_HSEL; 45 | reg APhase_HWRITE; 46 | reg [1:0] APhase_HTRANS; 47 | reg [31:0] APhase_HRADDR; 48 | reg [31:0] APhase_HWADDR; 49 | reg [2:0] APhase_HSIZE; 50 | 51 | // Sample the Address Phase 52 | always @(posedge HCLK or negedge HRESETn) 53 | begin 54 | if(!HRESETn) 55 | begin 56 | APhase_HSEL <= 1'b0; 57 | APhase_HWRITE <= 1'b0; 58 | APhase_HTRANS <= 2'b00; 59 | APhase_HWADDR <= 32'h0; 60 | APhase_HSIZE <= 3'b000; 61 | APhase_HRADDR[MEMWIDTH-2:0] <= {(MEMWIDTH-1){1'b0}}; 62 | end 63 | else if(HREADY) 64 | begin 65 | APhase_HSEL <= HSEL; 66 | APhase_HWRITE <= HWRITE; 67 | APhase_HTRANS <= HTRANS; 68 | APhase_HWADDR <= HADDR; 69 | APhase_HSIZE <= HSIZE; 70 | APhase_HRADDR[MEMWIDTH-2:0] <= HADDR[MEMWIDTH:2]; 71 | end 72 | end 73 | 74 | // Decode the bytes lanes depending on HSIZE & HADDR[1:0] 75 | 76 | wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0]; 77 | wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0]; 78 | wire tx_word = APhase_HSIZE[1]; 79 | 80 | wire byte_at_00 = tx_byte & ~APhase_HWADDR[1] & ~APhase_HWADDR[0]; 81 | wire byte_at_01 = tx_byte & ~APhase_HWADDR[1] & APhase_HWADDR[0]; 82 | wire byte_at_10 = tx_byte & APhase_HWADDR[1] & ~APhase_HWADDR[0]; 83 | wire byte_at_11 = tx_byte & APhase_HWADDR[1] & APhase_HWADDR[0]; 84 | 85 | wire half_at_00 = tx_half & ~APhase_HWADDR[1]; 86 | wire half_at_10 = tx_half & APhase_HWADDR[1]; 87 | 88 | wire word_at_00 = tx_word; 89 | 90 | wire byte0 = word_at_00 | half_at_00 | byte_at_00; 91 | wire byte1 = word_at_00 | half_at_00 | byte_at_01; 92 | wire byte2 = word_at_00 | half_at_10 | byte_at_10; 93 | wire byte3 = word_at_00 | half_at_10 | byte_at_11; 94 | 95 | always @ (posedge HCLK) 96 | begin 97 | if(APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1]) 98 | begin 99 | if(byte0) 100 | memory[APhase_HWADDR[MEMWIDTH:2]][ 7: 0] <= HWDATA[ 7: 0]; 101 | if(byte1) 102 | memory[APhase_HWADDR[MEMWIDTH:2]][15: 8] <= HWDATA[15: 8]; 103 | if(byte2) 104 | memory[APhase_HWADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16]; 105 | if(byte3) 106 | memory[APhase_HWADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24]; 107 | end 108 | 109 | HRDATA = memory[HADDR[MEMWIDTH:2]]; 110 | end 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /SimpleLEDSOC/AHB2BRAM.v: -------------------------------------------------------------------------------- 1 | // --========================================================================-- 2 | // Version and Release Control Information: 3 | // 4 | // File Name : AHB2BRAM.v 5 | // File Revision : 1.60 6 | // 7 | // ---------------------------------------------------------------------------- 8 | // Purpose : Basic AHBLITE Internal Memory Default Size = 16KB 9 | // 10 | // --========================================================================-- 11 | module AHB2MEM 12 | #(parameter MEMWIDTH = 14) // SIZE[Bytes] = 2 ^ MEMWIDTH[Bytes] = 2 ^ MEMWIDTH / 4[Entries] 13 | ( 14 | //AHBLITE INTERFACE 15 | //Slave Select Signals 16 | input wire HSEL, 17 | //Global Signal 18 | input wire HCLK, 19 | input wire HRESETn, 20 | //Address, Control & Write Data 21 | input wire HREADY, 22 | input wire [31:0] HADDR, 23 | input wire [1:0] HTRANS, 24 | input wire HWRITE, 25 | input wire [2:0] HSIZE, 26 | 27 | input wire [31:0] HWDATA, 28 | // Transfer Response & Read Data 29 | output wire HREADYOUT, 30 | output reg [31:0] HRDATA 31 | ); 32 | 33 | assign HREADYOUT = 1'b1; // Always ready 34 | 35 | // Memory Array 36 | reg [31:0] memory[0:(2**(MEMWIDTH-2)-1)]; 37 | 38 | initial 39 | begin 40 | $readmemh("code.hex", memory); 41 | end 42 | 43 | // Registers to store Adress Phase Signals 44 | reg APhase_HSEL; 45 | reg APhase_HWRITE; 46 | reg [1:0] APhase_HTRANS; 47 | reg [31:0] APhase_HRADDR; 48 | reg [31:0] APhase_HWADDR; 49 | reg [2:0] APhase_HSIZE; 50 | 51 | // Sample the Address Phase 52 | always @(posedge HCLK or negedge HRESETn) 53 | begin 54 | if(!HRESETn) 55 | begin 56 | APhase_HSEL <= 1'b0; 57 | APhase_HWRITE <= 1'b0; 58 | APhase_HTRANS <= 2'b00; 59 | APhase_HWADDR <= 32'h0; 60 | APhase_HSIZE <= 3'b000; 61 | APhase_HRADDR[MEMWIDTH-2:0] <= {(MEMWIDTH-1){1'b0}}; 62 | end 63 | else if(HREADY) 64 | begin 65 | APhase_HSEL <= HSEL; 66 | APhase_HWRITE <= HWRITE; 67 | APhase_HTRANS <= HTRANS; 68 | APhase_HWADDR <= HADDR; 69 | APhase_HSIZE <= HSIZE; 70 | APhase_HRADDR[MEMWIDTH-2:0] <= HADDR[MEMWIDTH:2]; 71 | end 72 | end 73 | 74 | // Decode the bytes lanes depending on HSIZE & HADDR[1:0] 75 | 76 | wire tx_byte = ~APhase_HSIZE[1] & ~APhase_HSIZE[0]; 77 | wire tx_half = ~APhase_HSIZE[1] & APhase_HSIZE[0]; 78 | wire tx_word = APhase_HSIZE[1]; 79 | 80 | wire byte_at_00 = tx_byte & ~APhase_HWADDR[1] & ~APhase_HWADDR[0]; 81 | wire byte_at_01 = tx_byte & ~APhase_HWADDR[1] & APhase_HWADDR[0]; 82 | wire byte_at_10 = tx_byte & APhase_HWADDR[1] & ~APhase_HWADDR[0]; 83 | wire byte_at_11 = tx_byte & APhase_HWADDR[1] & APhase_HWADDR[0]; 84 | 85 | wire half_at_00 = tx_half & ~APhase_HWADDR[1]; 86 | wire half_at_10 = tx_half & APhase_HWADDR[1]; 87 | 88 | wire word_at_00 = tx_word; 89 | 90 | wire byte0 = word_at_00 | half_at_00 | byte_at_00; 91 | wire byte1 = word_at_00 | half_at_00 | byte_at_01; 92 | wire byte2 = word_at_00 | half_at_10 | byte_at_10; 93 | wire byte3 = word_at_00 | half_at_10 | byte_at_11; 94 | 95 | always @ (posedge HCLK) 96 | begin 97 | if(APhase_HSEL & APhase_HWRITE & APhase_HTRANS[1]) 98 | begin 99 | if(byte0) 100 | memory[APhase_HWADDR[MEMWIDTH:2]][ 7: 0] <= HWDATA[ 7: 0]; 101 | if(byte1) 102 | memory[APhase_HWADDR[MEMWIDTH:2]][15: 8] <= HWDATA[15: 8]; 103 | if(byte2) 104 | memory[APhase_HWADDR[MEMWIDTH:2]][23:16] <= HWDATA[23:16]; 105 | if(byte3) 106 | memory[APhase_HWADDR[MEMWIDTH:2]][31:24] <= HWDATA[31:24]; 107 | end 108 | 109 | HRDATA = memory[HADDR[MEMWIDTH:2]]; 110 | end 111 | 112 | endmodule 113 | -------------------------------------------------------------------------------- /Final_SOC/AHBVGASYS.v: -------------------------------------------------------------------------------- 1 | 2 | module AHBVGA( 3 | input wire HCLK, 4 | input wire HRESETn, 5 | input wire [31:0] HADDR, 6 | input wire [31:0] HWDATA, 7 | input wire HREADY, 8 | input wire HWRITE, 9 | input wire [1:0] HTRANS, 10 | input wire HSEL, 11 | 12 | output wire [31:0] HRDATA, 13 | output wire HREADYOUT, 14 | 15 | output wire hsync, 16 | output wire vsync, 17 | output wire [7:0] rgb 18 | ); 19 | //Register locations 20 | localparam IMAGEADDR = 4'hA; 21 | localparam CONSOLEADDR = 4'h0; 22 | 23 | //Internal AHB signals 24 | reg last_HWRITE; 25 | reg last_HSEL; 26 | reg [1:0] last_HTRANS; 27 | reg [31:0] last_HADDR; 28 | 29 | wire [7:0] console_rgb; //console rgb signal 30 | wire [9:0] pixel_x; //current x pixel 31 | wire [9:0] pixel_y; //current y pixel 32 | 33 | reg console_write; //write to console 34 | reg [7:0] console_wdata;//data to write to console 35 | reg image_write; //write to image 36 | reg [7:0] image_wdata; //data to write to image 37 | 38 | wire [7:0] image_rgb; //image color 39 | 40 | wire scroll; //scrolling signal 41 | 42 | wire sel_console; 43 | wire sel_image; 44 | reg [7:0] cin; 45 | 46 | 47 | always @(posedge HCLK) 48 | if(HREADY) 49 | begin 50 | last_HADDR <= HADDR; 51 | last_HWRITE <= HWRITE; 52 | last_HSEL <= HSEL; 53 | last_HTRANS <= HTRANS; 54 | end 55 | 56 | //Give time for the screen to refresh before writing 57 | assign HREADYOUT = ~scroll; 58 | 59 | //VGA interface: control the synchronization and color signals for a particular resolution 60 | VGAInterface uVGAInterface ( 61 | .CLK(HCLK), 62 | .COLOUR_IN(cin), 63 | .cout(rgb), 64 | .hs(hsync), 65 | .vs(vsync), 66 | .addrh(pixel_x), 67 | .addrv(pixel_y) 68 | ); 69 | 70 | //VGA console module: output the pixels in the text region 71 | vga_console uvga_console( 72 | .clk(HCLK), 73 | .resetn(HRESETn), 74 | .pixel_x(pixel_x), 75 | .pixel_y(pixel_y), 76 | .text_rgb(console_rgb), 77 | .font_we(console_write), 78 | .font_data(console_wdata), 79 | .scroll(scroll) 80 | ); 81 | 82 | //VGA image buffer: output the pixels in the image region 83 | vga_image uvga_image( 84 | .clk(HCLK), 85 | .resetn(HRESETn), 86 | .address(last_HADDR[15:2]), 87 | .pixel_x(pixel_x), 88 | .pixel_y(pixel_y), 89 | .image_we(image_write), 90 | .image_data(image_wdata), 91 | .image_rgb(image_rgb) 92 | ); 93 | 94 | assign sel_console = (last_HADDR[23:0]== 12'h000000000000); 95 | assign sel_image = (last_HADDR[23:0] != 12'h000000000000); 96 | 97 | //Set console write and write data 98 | always @(posedge HCLK, negedge HRESETn) 99 | begin 100 | if(!HRESETn) 101 | begin 102 | console_write <= 0; 103 | console_wdata <= 0; 104 | end 105 | else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_console) 106 | begin 107 | console_write <= 1'b1; 108 | console_wdata <= HWDATA[7:0]; 109 | end 110 | else 111 | begin 112 | console_write <= 1'b0; 113 | console_wdata <= 0; 114 | end 115 | end 116 | 117 | //Set image write and image write data 118 | always @(posedge HCLK, negedge HRESETn) 119 | begin 120 | if(!HRESETn) 121 | begin 122 | image_write <= 0; 123 | image_wdata <= 0; 124 | end 125 | else if(last_HWRITE & last_HSEL & last_HTRANS[1] & HREADYOUT & sel_image) 126 | begin 127 | image_write <= 1'b1; 128 | image_wdata <= HWDATA[7:0]; 129 | end 130 | else 131 | begin 132 | image_write <= 1'b0; 133 | image_wdata <= 0; 134 | end 135 | end 136 | 137 | //Select the rgb color for a particular region 138 | always @* 139 | begin 140 | if(!HRESETn) 141 | cin <= 8'h00; 142 | else 143 | if(pixel_x[9:0]< 240 ) 144 | cin <= console_rgb ; 145 | else 146 | cin <= image_rgb; 147 | end 148 | 149 | endmodule 150 | 151 | 152 | -------------------------------------------------------------------------------- /Final_SOC/vga_console.v: -------------------------------------------------------------------------------- 1 | ////////////////////////////////////////////////////////////////////////////////// 2 | //END USER LICENCE AGREEMENT // 3 | // // 4 | 5 | 6 | module vga_console( 7 | input wire clk, 8 | input wire resetn, 9 | input wire [9:0] pixel_x, 10 | input wire [9:0] pixel_y, 11 | 12 | input wire font_we, //font write 13 | input wire [7:0] font_data, //input 7-bit ascii value 14 | 15 | output reg [7:0] text_rgb, //output color 16 | output reg scroll //signals scrolling 17 | ); 18 | 19 | //Screen tile parameters 20 | localparam MAX_X = 30; //Number of horizontal tiles 21 | localparam MAX_Y = 30; //Number of tile rows 22 | 23 | //Font ROM 24 | wire [10:0] rom_addr; 25 | wire [6:0] char_addr; 26 | wire [3:0] row_addr; 27 | wire [2:0] bit_addr; 28 | wire [7:0] font_word; 29 | wire font_bit; 30 | 31 | //Dual port RAM 32 | wire [11:0] addr_r; 33 | wire [11:0] addr_w; 34 | wire [6:0] din; 35 | wire [6:0] dout; 36 | 37 | //Cursor 38 | reg [6:0] cur_x_reg; 39 | wire [6:0] cur_x_next; 40 | reg [4:0] cur_y_reg; 41 | wire [4:0] cur_y_next; 42 | // wire cursor_on; 43 | 44 | //pixel buffers 45 | reg [9:0] pixel_x1; 46 | reg [9:0] pixel_x2; 47 | reg [9:0] pixel_y1; 48 | reg [9:0] pixel_y2; 49 | 50 | wire [7:0] font_rgb; //color for text 51 | wire [7:0] font_inv_rgb; //color for text with cursor on top 52 | 53 | reg current_state; 54 | reg next_state; 55 | 56 | wire return_key; //carriage return or '\n' 57 | wire new_line; //move cursor to next line 58 | 59 | //reg scroll; 60 | reg scroll_next; 61 | reg [4:0] yn; //row count 62 | reg [4:0] yn_next; 63 | reg [6:0] xn; //horizontal count 64 | reg [6:0] xn_next; 65 | 66 | //Module Instantiation 67 | font_rom ufont_rom( 68 | .clk(clk), 69 | .addr(rom_addr), 70 | .data(font_word) 71 | ); 72 | 73 | dual_port_ram_sync 74 | #(.ADDR_WIDTH(12), .DATA_WIDTH(7)) 75 | uvideo_ram 76 | ( .clk(clk), 77 | .reset_n(resetn), 78 | .we(we), 79 | .addr_a(addr_w), 80 | .addr_b(addr_r), 81 | .din_a(din), 82 | .dout_a(), 83 | .dout_b(dout) 84 | ); 85 | 86 | //State Machine for cursor and pixel buffer 87 | always @ (posedge clk, negedge resetn) 88 | begin 89 | if(!resetn) 90 | begin 91 | cur_x_reg <= 0; 92 | cur_y_reg <= 0; 93 | end 94 | else 95 | begin 96 | cur_x_reg <= cur_x_next; 97 | cur_y_reg <= cur_y_next; 98 | pixel_x1 <= pixel_x; 99 | pixel_x2 <= pixel_x1; 100 | pixel_y1 <= pixel_y; 101 | pixel_y2 <= pixel_y1; 102 | end 103 | end 104 | 105 | 106 | //Font ROM Access 107 | assign row_addr = pixel_y[3:0]; //row value 108 | assign rom_addr = {char_addr,row_addr}; //ascii value and row of character 109 | assign bit_addr = pixel_x2[2:0]; //delayed 110 | assign font_bit = font_word[~bit_addr]; //output from font rom 111 | 112 | //Return key found 113 | assign return_key = (din == 6'b001101 || din == 6'b001010) && ~scroll; // Return || "\n" 114 | 115 | //Backspace 116 | assign back_space = (din == 6'b001000); 117 | 118 | //New line logic 119 | assign new_line = font_we && ((cur_x_reg == MAX_X-1) || return_key); 120 | 121 | //Next Cursor Position logic 122 | assign cur_x_next = (new_line) ? 2 : 123 | (back_space && cur_x_reg) ? cur_x_reg - 1 : 124 | (font_we && ~back_space && ~scroll) ? cur_x_reg + 1 : cur_x_reg; 125 | 126 | assign cur_y_next = (cur_y_reg == MAX_Y-1) ? cur_y_reg : 127 | ((new_line) ? cur_y_reg + 1 : cur_y_reg ); 128 | 129 | //Color Generation 130 | assign font_rgb = (font_bit) ? 8'b00011100 : 8'b00000000; //green:black 131 | assign font_inv_rgb = (font_bit) ? 8'b0000000 : 8'b00011100; //black:green 132 | 133 | //Display logic for cursor 134 | // assign cursor_on = (pixel_x2[9:3] == cur_x_reg) && (pixel_y2[8:4] == cur_y_reg); 135 | 136 | //RAM Write Enable 137 | assign we = font_we || scroll; 138 | 139 | //Display combinational logic 140 | always @* 141 | begin 142 | text_rgb = font_rgb; 143 | end 144 | 145 | //Console state machine 146 | always @(posedge clk, negedge resetn) 147 | if(!resetn) 148 | begin 149 | scroll <= 1'b0; 150 | yn <= 5'b00000; 151 | xn <= 7'b0000000; 152 | current_state <= 1'b0; 153 | end 154 | else 155 | begin 156 | scroll <= scroll_next; 157 | yn <= yn_next; 158 | xn <= xn_next; 159 | current_state <= next_state; 160 | end 161 | 162 | //Console next state logic 163 | always @* 164 | begin 165 | scroll_next = scroll; 166 | xn_next = xn; 167 | yn_next = yn; 168 | next_state = current_state; 169 | case(current_state) 170 | 1'b0: //Waits for a new line and the cursor on the last line of the screen 171 | if(new_line && (cur_y_reg == MAX_Y-1)) 172 | begin 173 | scroll_next = 1'b1; 174 | next_state = 1'b1; 175 | yn_next = 0; 176 | xn_next = 7'b1111111; //Delayed by one cycle 177 | end 178 | else 179 | scroll_next = 1'b0; 180 | 1'b1: //Counts through every tile and refreshes 181 | begin 182 | if(xn_next == MAX_X) 183 | begin 184 | xn_next = 7'b1111111; //Delayed by one cycle 185 | yn_next = yn + 1'b1; 186 | if(yn_next == MAX_Y) 187 | begin 188 | next_state = 1'b0; 189 | scroll_next = 0; 190 | end 191 | end 192 | else 193 | xn_next = xn + 1'b1; 194 | 195 | 196 | end 197 | endcase 198 | end 199 | 200 | 201 | //RAM Write 202 | assign addr_w = (scroll) ? {yn,xn} : {cur_y_reg, cur_x_reg}; 203 | assign din = (scroll) ? dout : font_data[6:0]; 204 | //RAM Read 205 | assign addr_r =(scroll) ? {yn+1'b1,xn_next} : {pixel_y[8:4],pixel_x[9:3]}; 206 | assign char_addr = dout; 207 | 208 | 209 | 210 | endmodule 211 | -------------------------------------------------------------------------------- /SimpleLEDSOC/README.md: -------------------------------------------------------------------------------- 1 | # Simple LED SOC 2 | ## The idea 3 | The main idea behind this simple project is to understand the concepts of the AHB-Lite bus , understand the working of the Cortex-M0 processor and learn to add peripherals to the AHB-Lite bus. 4 | 5 | The hardware components of the SoC include: 6 | 7 | • An Arm Cortex-M0 microprocessor 8 | • An AHB-Lite system bus 9 | • Two AHB peripherals : 10 | 11 | • Program memory (implemented using on-chip memory blocks) 12 | • A simple LED peripheral 13 | 14 | ## LED SOC design(Architecture) 15 | ![Courtesy ARM](images/Lab4_image1.png) 16 | 17 | ## SOC Block Diagram 18 | ![Screenshot](images/Blockdiagram.png) 19 | 20 | The above diagram reprasents the general architecture for AHB based designs from ARM. In this SOC we have 2 slave devices one being the code memory and the other is the LED block. 21 | 22 | ## Description 23 | 24 | ### ARM Cortex-m0 25 | The logic of the Arm Cortex-M0 processor is written in Verilog code, and thus can be prototyped (synthesized and implemented) on an FPGA platform. The Cortex-M0 DesignStart has almost the same functionality of an industry-standard Cortex-M0 processor, except that some features are reduced; e.g., the number of interrupts is reduced from the original 32 to 16 interrupts. 26 | 27 | Files used from ARM IP : 28 | 29 | • cortexm0ds_logic.v 30 | • CORTEXM0INTEGRATION.v 31 | • AHBMUX.v 32 | • AHBDCD.v 33 | 34 | Link for ARM IP : https://developer.arm.com/products/designstart 35 | 36 | ### Memory Map 37 | ![Screenshot](images/memorymap.png) 38 | 39 | ### JTAG Programming interface 40 | For programming the processor we need an interface. So, in this project I have used the JTAG interface to do that. The verilog code below is the interface I used in this project. 41 | 42 | wire dbg_tdo; // SWV / JTAG TDO 43 | wire dbg_tdo_nen; // SWV / JTAG TDO tristate enable (active low) 44 | wire dbg_swdo; // SWD I/O 3-state output 45 | wire dbg_swdo_en; // SWD I/O 3-state enable 46 | wire dbg_jtag_nsw; // SWD in JTAG state (HIGH) 47 | wire dbg_swo; // Serial wire viewer/output 48 | wire tdo_enable = !dbg_tdo_nen | !dbg_jtag_nsw; 49 | wire tdo_tms = dbg_jtag_nsw ? dbg_tdo : dbg_swo; 50 | assign TMS = dbg_swdo_en ? dbg_swdo : 1'bz; 51 | assign TDO = tdo_enable ? tdo_tms : 1'bz; 52 | 53 | ### AHB-Lite Bus 54 | AMBA AHB-Lite addresses the requirements of high-performance synthesizable designs. It is a bus interface that supports a single bus master and provides high-bandwidth operation. 55 | 56 | AHB-Lite implements the features required for high-performance, high clock frequency systems including: 57 | • burst transfers 58 | • single-clock edge operation 59 | • non-tristate implementation 60 | • wide data bus configurations, 64, 128, 256, 512, and 1024 bits 61 | 62 | #### AHB-Lite Master 63 | An AHB-Lite master provides address and control information to initiate read and writem operations. The figure below shows a typical AHB-Lite Master. 64 | ![Screenshot](images/AHBLITES.png) 65 | 66 | #### AHB-Lite Slave 67 | An AHB-Lite slave responds to transfers initiated by masters in the system. The slave uses the HSELx select signal from the decoder to control when it responds to a bus 68 | transfer. The slave signals back to the master: 69 | 70 | • The success 71 | • Failure 72 | • Waiting of the data transfer 73 | 74 | ![Screenshot](images/AHBLITEM.png) 75 | 76 | #### Working 77 | The master starts a transfer by driving the address and control signals. These signals provide information about the address, direction, width of the transfer, and indicate if 78 | the transfer forms part of a burst. 79 | 80 | Transfers can be: 81 | 82 | • Single 83 | • Incrementing bursts that do not wrap at address boundaries 84 | • Wrapping bursts that wrap at particular address boundaries. 85 | 86 | The write data bus moves data from the master to a slave, and the read data bus moves data from a slave to the master. 87 | Every transfer consists of: 88 | 89 | • Address phase one address and control cycle 90 | • Data phase one or more cycles for the data. 91 | 92 | A slave cannot request that the address phase is extended and therefore all slaves must be capable of sampling the address during this time. However, a slave can request that 93 | the master extends the data phase by using HREADY. This signal, when LOW, causes wait states to be inserted into the transfer and enables the slave to have extra time to 94 | provide or sample data. The slave uses HRESP to indicate the success or failure of a transfer. 95 | 96 | #### Signals Description [Courtesy of ARM] 97 | ![Screenshot](images/Global_Signals.png) 98 | 99 | ![Screenshot](images/MasterS.png) 100 | 101 | ![Screenshot](images/MS2.png) 102 | 103 | ![Screenshot](images/SlaveS.png) 104 | 105 | ![Screenshot](images/Decoder.png) 106 | 107 | ![Screenshot](images/mux.png) 108 | 109 | *** For more info on AHB-Lite do check this documentation by ARM : https://developer.arm.com/documentation/ihi0033/a/ *** 110 | 111 | ### Peripherals 112 | The two peripherals in this SOC are the Block RAM and the LEDs. 113 | 114 | #### Block RAM AHB interface 115 | The physical memory used to store the instructions is called a program memory. In this basic SoC platform, the program memory is implemented using the on-chip memory blocks, rather than off-chip memories. For example, the block RAM (BRAM) is one type of on-chip memory on Xilinx FPGAs. Normally, in order to load your program into the on-chip memory of an FPGA, the program image needs to be merged into your hardware design during synthesizing. For example, if you need to preload a program file into the hardware, the program file (e.g., “code.hex”) needs to be referred to in your Verilog code, using syntax such as: 116 | 117 | initial begin 118 | $readmemh("code.hex", memory); 119 | end 120 | 121 | The verilog code below instantiates the AHB Block RAM interface. 122 | 123 | AHB2MEM uAHB2RAM ( 124 | //AHBLITE Signals 125 | .HSEL(hsel_mem), 126 | .HCLK(fclk), 127 | .HRESETn(hresetn), 128 | .HREADY(hreadys), 129 | .HADDR(haddrs), 130 | .HTRANS(htranss), 131 | .HWRITE(hwrites), 132 | .HSIZE(hsizes), 133 | .HWDATA(hwdatas), 134 | 135 | .HRDATA(hrdata_mem), 136 | .HREADYOUT(hready_mem) 137 | ); 138 | 139 | #### LED AHB interface 140 | The LED peripheral is a simple module used to interface with the 8-bit LEDs. It has an AHB bus interface, which allows the LED to be connected to the system AHB bus, and controlled by the Cortex-M0 processor. 141 | 142 | The verilog code below instantiates the AHB LED interface. 143 | 144 | AHB2LED uAHB2LED ( 145 | //AHBLITE Signals 146 | .HSEL(hsel_led), 147 | .HCLK(fclk), 148 | .HRESETn(hresetn), 149 | .HREADY(hreadys), 150 | .HADDR(haddrs), 151 | .HTRANS(htranss), 152 | .HWRITE(hwrites), 153 | .HSIZE(hsizes), 154 | .HWDATA(hwdatas), 155 | 156 | .HRDATA(hrdata_led), 157 | .HREADYOUT(hready_led), 158 | //Sideband Signals 159 | .LED(LED[6:0]) 160 | ); 161 | 162 | ### Implementation on FPGA 163 | ![Screenshot](images/SOCIMPL.jpeg) 164 | 165 | ### Video Link 166 | 1. Video Series : https://www.youtube.com/watch?v=j7KdeELvnns 167 | 2. Demo : https://www.youtube.com/watch?v=2oi_iIShGdU 168 | 169 | 170 | 171 | -------------------------------------------------------------------------------- /SimpleLEDSOC/AHBLITE_SYS.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module AHBLITE_SYS( 4 | input wire CLK, // Oscillator - 100MHz 5 | input wire RESET, // Reset 6 | 7 | // TO BOARD LEDs 8 | output wire [7:0] LED, 9 | 10 | 11 | // Debug 12 | input wire TDI, // JTAG TDI 13 | input wire TCK, // SWD Clk / JTAG TCK 14 | inout wire TMS, // SWD I/O / JTAG TMS 15 | output wire TDO // SWV / JTAG TDO 16 | ); 17 | 18 | // Clock 19 | wire fclk; // Free running clock 20 | // Reset 21 | wire reset_n = RESET; 22 | 23 | // Select signals 24 | wire [3:0] mux_sel; 25 | 26 | wire hsel_mem; 27 | wire hsel_led; 28 | 29 | // Slave read data 30 | wire [31:0] hrdata_mem; 31 | wire [31:0] hrdata_led; 32 | 33 | // Slave hready 34 | wire hready_mem; 35 | wire hready_led; 36 | 37 | // CM-DS Sideband signals 38 | wire lockup; 39 | wire lockup_reset_req; 40 | wire sys_reset_req; 41 | wire txev; 42 | wire sleeping; 43 | wire [31:0] irq; 44 | 45 | // Interrupt signals 46 | assign irq = {32'b0}; 47 | // assign LED[7] = lockup; 48 | 49 | // Clock divider, divide the frequency by two, hence less time constraint 50 | reg clk_div; 51 | always @(posedge CLK) 52 | begin 53 | clk_div=~clk_div; 54 | end 55 | BUFG BUFG_CLK ( 56 | .O(fclk), 57 | .I(clk_div) 58 | ); 59 | 60 | // Reset synchronizer 61 | reg [4:0] reset_sync_reg; 62 | always @(posedge fclk or negedge reset_n) 63 | begin 64 | if (!reset_n) 65 | reset_sync_reg <= 5'b00000; 66 | else 67 | begin 68 | reset_sync_reg[3:0] <= {reset_sync_reg[2:0], 1'b1}; 69 | reset_sync_reg[4] <= reset_sync_reg[2] & (~sys_reset_req); 70 | end 71 | end 72 | 73 | // CPU System Bus 74 | wire hresetn = reset_sync_reg[4]; 75 | wire [31:0] haddrs; 76 | wire [2:0] hbursts; 77 | wire hmastlocks; 78 | wire [3:0] hprots; 79 | wire [2:0] hsizes; 80 | wire [1:0] htranss; 81 | wire [31:0] hwdatas; 82 | wire hwrites; 83 | wire [31:0] hrdatas; 84 | wire hreadys; 85 | wire [1:0] hresps = 2'b00; // System generates no error response 86 | wire exresps = 1'b0; 87 | 88 | // Debug signals (TDO pin is used for SWV unless JTAG mode is active) 89 | wire dbg_tdo; // SWV / JTAG TDO 90 | wire dbg_tdo_nen; // SWV / JTAG TDO tristate enable (active low) 91 | wire dbg_swdo; // SWD I/O 3-state output 92 | wire dbg_swdo_en; // SWD I/O 3-state enable 93 | wire dbg_jtag_nsw; // SWD in JTAG state (HIGH) 94 | wire dbg_swo; // Serial wire viewer/output 95 | wire tdo_enable = !dbg_tdo_nen | !dbg_jtag_nsw; 96 | wire tdo_tms = dbg_jtag_nsw ? dbg_tdo : dbg_swo; 97 | assign TMS = dbg_swdo_en ? dbg_swdo : 1'bz; 98 | assign TDO = tdo_enable ? tdo_tms : 1'bz; 99 | 100 | // CoreSight requires a loopback from REQ to ACK for a minimal 101 | // debug power control implementation 102 | wire cpu0cdbgpwrupreq; 103 | wire cpu0cdbgpwrupack; 104 | assign cpu0cdbgpwrupack = cpu0cdbgpwrupreq; 105 | 106 | // DesignStart simplified integration level 107 | CORTEXM0INTEGRATION u_CORTEXM0INTEGRATION ( 108 | // CLOCK AND RESETS 109 | .FCLK (fclk), // Free running clock 110 | .SCLK (fclk), // System clock 111 | .HCLK (fclk), // AHB clock 112 | .DCLK (fclk), // Debug system clock 113 | .PORESETn (reset_sync_reg[2]), // Power on reset 114 | .DBGRESETn (reset_sync_reg[3]), // Debug reset 115 | .HRESETn (hresetn), // AHB and System reset 116 | 117 | // AHB-LITE MASTER PORT 118 | .HADDR (haddrs), 119 | .HBURST (hbursts), 120 | .HMASTLOCK (hmastlocks), 121 | .HPROT (hprots), 122 | .HSIZE (hsizes), 123 | .HTRANS (htranss), 124 | .HWDATA (hwdatas), 125 | .HWRITE (hwrites), 126 | .HRDATA (hrdatas), 127 | .HREADY (hreadys), 128 | .HRESP (hresps), 129 | .HMASTER (), 130 | 131 | // CODE SEQUENTIALITY AND SPECULATION 132 | .CODENSEQ (), 133 | .CODEHINTDE (), 134 | .SPECHTRANS (), 135 | 136 | // DEBUG 137 | .nTRST (1'b1), 138 | .SWCLKTCK (TCK), 139 | .SWDITMS (TMS), 140 | .TDI (TDI), 141 | .SWDO (dbg_swdo), 142 | .SWDOEN (dbg_swdo_en), 143 | .TDO (dbg_tdo), 144 | .nTDOEN (dbg_tdo_nen), 145 | .DBGRESTART (1'b0), // Debug Restart request - Not needed in a single CPU system 146 | .DBGRESTARTED (), 147 | .EDBGRQ (1'b0), // External Debug request to CPU 148 | .HALTED (), 149 | 150 | // MISC 151 | .NMI (1'b0), // Non-maskable interrupt input 152 | .IRQ (irq), // Interrupt request inputs 153 | .TXEV (), // Event output (SEV executed) 154 | .RXEV (1'b0), // Event input 155 | .LOCKUP (lockup), // Core is locked-up 156 | .SYSRESETREQ (sys_reset_req), // System reset request 157 | .STCALIB ({1'b1, // No alternative clock source 158 | 1'b0, // Exact multiple of 10ms from FCLK 159 | 24'h007A11F}), // Calibration value for SysTick for 50 MHz source 160 | .STCLKEN (1'b0), // SysTick SCLK clock disable 161 | .IRQLATENCY (8'h00), 162 | .ECOREVNUM (28'h0), 163 | 164 | // POWER MANAGEMENT 165 | .GATEHCLK (), // When high, HCLK can be turned off 166 | .SLEEPING (), // Core and NVIC sleeping 167 | .SLEEPDEEP (), // The processor is in deep sleep mode 168 | .WAKEUP (), // Active HIGH signal from WIC to the PMU that indicates a wake-up event has 169 | // occurred and the system requires clocks and power 170 | .WICSENSE (), 171 | .SLEEPHOLDREQn (1'b1), // Extend Sleep request 172 | .SLEEPHOLDACKn (), // Acknowledge for SLEEPHOLDREQn 173 | .WICENREQ (1'b0), // Active HIGH request for deep sleep to be WIC-based deep sleep 174 | .WICENACK (), // Acknowledge for WICENREQ - WIC operation deep sleep mode 175 | .CDBGPWRUPREQ (cpu0cdbgpwrupreq), // Debug Power Domain up request 176 | .CDBGPWRUPACK (cpu0cdbgpwrupack), // Debug Power Domain up acknowledge. 177 | 178 | // SCAN IO 179 | .SE (1'b0), // DFT is tied off in this example 180 | .RSTBYPASS (1'b0) // Reset bypass - active high to disable internal generated reset for testing 181 | ); 182 | 183 | // Address Decoder 184 | AHBDCD uAHBDCD ( 185 | .HADDR(haddrs), 186 | 187 | .HSEL_S0(hsel_mem), 188 | .HSEL_S1(hsel_led), 189 | .HSEL_S2(), 190 | .HSEL_S3(), 191 | .HSEL_S4(), 192 | .HSEL_S5(), 193 | .HSEL_S6(), 194 | .HSEL_S7(), 195 | .HSEL_S8(), 196 | .HSEL_S9(), 197 | .HSEL_NOMAP(), 198 | 199 | .MUX_SEL(mux_sel[3:0]) 200 | ); 201 | 202 | // Slave to Master Mulitplexor 203 | AHBMUX uAHBMUX ( 204 | .HCLK(fclk), 205 | .HRESETn(hresetn), 206 | .MUX_SEL(mux_sel[3:0]), 207 | 208 | .HRDATA_S0(hrdata_mem), 209 | .HRDATA_S1(hrdata_led), 210 | .HRDATA_S2(), 211 | .HRDATA_S3(), 212 | .HRDATA_S4(), 213 | .HRDATA_S5(), 214 | .HRDATA_S6(), 215 | .HRDATA_S7(), 216 | .HRDATA_S8(), 217 | .HRDATA_S9(), 218 | .HRDATA_NOMAP(32'hDEADBEEF), 219 | 220 | .HREADYOUT_S0(hready_mem), 221 | .HREADYOUT_S1(hready_led), 222 | .HREADYOUT_S2(), 223 | .HREADYOUT_S3(), 224 | .HREADYOUT_S4(), 225 | .HREADYOUT_S5(), 226 | .HREADYOUT_S6(1'b1), 227 | .HREADYOUT_S7(1'b1), 228 | .HREADYOUT_S8(1'b1), 229 | .HREADYOUT_S9(1'b1), 230 | .HREADYOUT_NOMAP(1'b1), 231 | 232 | .HRDATA(hrdatas), 233 | .HREADY(hreadys) 234 | ); 235 | 236 | // AHBLite Peripherals 237 | 238 | // AHB-Lite RAM 239 | AHB2MEM uAHB2RAM ( 240 | //AHBLITE Signals 241 | .HSEL(hsel_mem), 242 | .HCLK(fclk), 243 | .HRESETn(hresetn), 244 | .HREADY(hreadys), 245 | .HADDR(haddrs), 246 | .HTRANS(htranss), 247 | .HWRITE(hwrites), 248 | .HSIZE(hsizes), 249 | .HWDATA(hwdatas), 250 | 251 | .HRDATA(hrdata_mem), 252 | .HREADYOUT(hready_mem) 253 | ); 254 | 255 | AHB2LED uAHB2LED ( 256 | //AHBLITE Signals 257 | .HSEL(hsel_led), 258 | .HCLK(fclk), 259 | .HRESETn(hresetn), 260 | .HREADY(hreadys), 261 | .HADDR(haddrs), 262 | .HTRANS(htranss), 263 | .HWRITE(hwrites), 264 | .HSIZE(hsizes), 265 | .HWDATA(hwdatas), 266 | 267 | .HRDATA(hrdata_led), 268 | .HREADYOUT(hready_led), 269 | //Sideband Signals 270 | .LED(LED[6:0]) 271 | ); 272 | 273 | 274 | 275 | endmodule 276 | -------------------------------------------------------------------------------- /LICENSE: -------------------------------------------------------------------------------- 1 | Apache License 2 | Version 2.0, January 2004 3 | http://www.apache.org/licenses/ 4 | 5 | TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION 6 | 7 | 1. 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We also recommend that a 185 | file or class name and description of purpose be included on the 186 | same "printed page" as the copyright notice for easier 187 | identification within third-party archives. 188 | 189 | Copyright [yyyy] [name of copyright owner] 190 | 191 | Licensed under the Apache License, Version 2.0 (the "License"); 192 | you may not use this file except in compliance with the License. 193 | You may obtain a copy of the License at 194 | 195 | http://www.apache.org/licenses/LICENSE-2.0 196 | 197 | Unless required by applicable law or agreed to in writing, software 198 | distributed under the License is distributed on an "AS IS" BASIS, 199 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 200 | See the License for the specific language governing permissions and 201 | limitations under the License. 202 | -------------------------------------------------------------------------------- /Final_SOC/AHBLITE_SYS.v: -------------------------------------------------------------------------------- 1 | module AHBLITE_SYS( 2 | input wire CLK, // Oscillator - 100MHz 3 | input wire RESET, // Reset 4 | 5 | // TO BOARD LEDs 6 | output wire [7:0] LED, 7 | 8 | // VGA IO 9 | output wire [2:0] vgaRed, 10 | output wire [2:0] vgaGreen, 11 | output wire [1:0] vgaBlue, 12 | output wire Hsync, // VGA Horizontal Sync 13 | output wire Vsync, // VGA Vertical Sync 14 | 15 | // TO UART 16 | input wire RsRx, 17 | output wire RsTx, 18 | 19 | // Switch Inputs 20 | input wire [7:0] sw, 21 | 22 | // 7 Segment display 23 | output wire [6:0] seg, 24 | output wire dp, 25 | output wire [3:0] an, 26 | 27 | 28 | 29 | // Debug 30 | input wire TDI, // JTAG TDI 31 | input wire TCK, // SWD Clk / JTAG TCK 32 | inout wire TMS, // SWD I/O / JTAG TMS 33 | output wire TDO // SWV / JTAG TDO 34 | ); 35 | 36 | // Clock 37 | wire fclk; // Free running clock 38 | // Reset 39 | wire reset_n = RESET; 40 | 41 | // Select signals 42 | wire [3:0] mux_sel; 43 | 44 | wire hsel_mem; 45 | wire hsel_led; 46 | wire hsel_vga; 47 | wire hsel_uart; 48 | 49 | // Slave read data 50 | wire [31:0] hrdata_mem; 51 | wire [31:0] hrdata_led; 52 | wire [31:0] hrdata_vga; 53 | wire [31:0] hrdata_uart; 54 | 55 | // Slave hready 56 | wire hready_mem; 57 | wire hready_led; 58 | wire hready_vga; 59 | wire hready_uart; 60 | 61 | // CM-DS Sideband signals 62 | wire lockup; 63 | wire lockup_reset_req; 64 | wire sys_reset_req; 65 | wire txev; 66 | wire sleeping; 67 | wire [31:0] irq; 68 | 69 | 70 | // Interrupt signals 71 | assign irq = {32'b0}; 72 | // assign LED[7] = lockup; 73 | 74 | // Clock divider, divide the frequency by two, hence less time constraint 75 | reg clk_div; 76 | always @(posedge CLK) 77 | begin 78 | clk_div=~clk_div; 79 | end 80 | BUFG BUFG_CLK ( 81 | .O(fclk), 82 | .I(clk_div) 83 | ); 84 | 85 | // Reset synchronizer 86 | reg [4:0] reset_sync_reg; 87 | always @(posedge fclk or negedge reset_n) 88 | begin 89 | if (!reset_n) 90 | reset_sync_reg <= 5'b00000; 91 | else 92 | begin 93 | reset_sync_reg[3:0] <= {reset_sync_reg[2:0], 1'b1}; 94 | reset_sync_reg[4] <= reset_sync_reg[2] & (~sys_reset_req); 95 | end 96 | end 97 | 98 | // CPU System Bus 99 | wire hresetn = reset_sync_reg[4]; 100 | wire [31:0] haddrs; 101 | wire [2:0] hbursts; 102 | wire hmastlocks; 103 | wire [3:0] hprots; 104 | wire [2:0] hsizes; 105 | wire [1:0] htranss; 106 | wire [31:0] hwdatas; 107 | wire hwrites; 108 | wire [31:0] hrdatas; 109 | wire hreadys; 110 | wire [1:0] hresps = 2'b00; // System generates no error response 111 | wire exresps = 1'b0; 112 | 113 | // Debug signals (TDO pin is used for SWV unless JTAG mode is active) 114 | wire dbg_tdo; // SWV / JTAG TDO 115 | wire dbg_tdo_nen; // SWV / JTAG TDO tristate enable (active low) 116 | wire dbg_swdo; // SWD I/O 3-state output 117 | wire dbg_swdo_en; // SWD I/O 3-state enable 118 | wire dbg_jtag_nsw; // SWD in JTAG state (HIGH) 119 | wire dbg_swo; // Serial wire viewer/output 120 | wire tdo_enable = !dbg_tdo_nen | !dbg_jtag_nsw; 121 | wire tdo_tms = dbg_jtag_nsw ? dbg_tdo : dbg_swo; 122 | assign TMS = dbg_swdo_en ? dbg_swdo : 1'bz; 123 | assign TDO = tdo_enable ? tdo_tms : 1'bz; 124 | 125 | // CoreSight requires a loopback from REQ to ACK for a minimal 126 | // debug power control implementation 127 | wire cpu0cdbgpwrupreq; 128 | wire cpu0cdbgpwrupack; 129 | assign cpu0cdbgpwrupack = cpu0cdbgpwrupreq; 130 | 131 | // DesignStart simplified integration level 132 | CORTEXM0INTEGRATION u_CORTEXM0INTEGRATION ( 133 | // CLOCK AND RESETS 134 | .FCLK (fclk), // Free running clock 135 | .SCLK (fclk), // System clock 136 | .HCLK (fclk), // AHB clock 137 | .DCLK (fclk), // Debug system clock 138 | .PORESETn (reset_sync_reg[2]), // Power on reset 139 | .DBGRESETn (reset_sync_reg[3]), // Debug reset 140 | .HRESETn (hresetn), // AHB and System reset 141 | 142 | // AHB-LITE MASTER PORT 143 | .HADDR (haddrs), 144 | .HBURST (hbursts), 145 | .HMASTLOCK (hmastlocks), 146 | .HPROT (hprots), 147 | .HSIZE (hsizes), 148 | .HTRANS (htranss), 149 | .HWDATA (hwdatas), 150 | .HWRITE (hwrites), 151 | .HRDATA (hrdatas), 152 | .HREADY (hreadys), 153 | .HRESP (hresps), 154 | .HMASTER (), 155 | 156 | // CODE SEQUENTIALITY AND SPECULATION 157 | .CODENSEQ (), 158 | .CODEHINTDE (), 159 | .SPECHTRANS (), 160 | 161 | // DEBUG 162 | .nTRST (1'b1), 163 | .SWCLKTCK (TCK), 164 | .SWDITMS (TMS), 165 | .TDI (TDI), 166 | .SWDO (dbg_swdo), 167 | .SWDOEN (dbg_swdo_en), 168 | .TDO (dbg_tdo), 169 | .nTDOEN (dbg_tdo_nen), 170 | .DBGRESTART (1'b0), // Debug Restart request - Not needed in a single CPU system 171 | .DBGRESTARTED (), 172 | .EDBGRQ (1'b0), // External Debug request to CPU 173 | .HALTED (), 174 | 175 | // MISC 176 | .NMI (1'b0), // Non-maskable interrupt input 177 | .IRQ (irq), // Interrupt request inputs 178 | .TXEV (), // Event output (SEV executed) 179 | .RXEV (1'b0), // Event input 180 | .LOCKUP (lockup), // Core is locked-up 181 | .SYSRESETREQ (sys_reset_req), // System reset request 182 | .STCALIB ({1'b1, // No alternative clock source 183 | 1'b0, // Exact multiple of 10ms from FCLK 184 | 24'h007A11F}), // Calibration value for SysTick for 50 MHz source 185 | .STCLKEN (1'b0), // SysTick SCLK clock disable 186 | .IRQLATENCY (8'h00), 187 | .ECOREVNUM (28'h0), 188 | 189 | // POWER MANAGEMENT 190 | .GATEHCLK (), // When high, HCLK can be turned off 191 | .SLEEPING (), // Core and NVIC sleeping 192 | .SLEEPDEEP (), // The processor is in deep sleep mode 193 | .WAKEUP (), // Active HIGH signal from WIC to the PMU that indicates a wake-up event has 194 | // occurred and the system requires clocks and power 195 | .WICSENSE (), 196 | .SLEEPHOLDREQn (1'b1), // Extend Sleep request 197 | .SLEEPHOLDACKn (), // Acknowledge for SLEEPHOLDREQn 198 | .WICENREQ (1'b0), // Active HIGH request for deep sleep to be WIC-based deep sleep 199 | .WICENACK (), // Acknowledge for WICENREQ - WIC operation deep sleep mode 200 | .CDBGPWRUPREQ (cpu0cdbgpwrupreq), // Debug Power Domain up request 201 | .CDBGPWRUPACK (cpu0cdbgpwrupack), // Debug Power Domain up acknowledge. 202 | 203 | // SCAN IO 204 | .SE (1'b0), // DFT is tied off in this example 205 | .RSTBYPASS (1'b0) // Reset bypass - active high to disable internal generated reset for testing 206 | ); 207 | 208 | // Address Decoder 209 | AHBDCD uAHBDCD ( 210 | .HADDR(haddrs), 211 | 212 | .HSEL_S0(hsel_mem), 213 | .HSEL_S1(hsel_vga), 214 | .HSEL_S2(hsel_uart), 215 | .HSEL_S3(), 216 | .HSEL_S4(), 217 | .HSEL_S5(), 218 | .HSEL_S6(), 219 | .HSEL_S7(), 220 | .HSEL_S8(), 221 | .HSEL_S9(), 222 | .HSEL_NOMAP(), 223 | 224 | .MUX_SEL(mux_sel[3:0]) 225 | ); 226 | 227 | // Slave to Master Mulitplexor 228 | AHBMUX uAHBMUX ( 229 | .HCLK(fclk), 230 | .HRESETn(hresetn), 231 | .MUX_SEL(mux_sel[3:0]), 232 | 233 | .HRDATA_S0(hrdata_mem), 234 | .HRDATA_S1(hrdata_vga), 235 | .HRDATA_S2(hrdata_uart), 236 | .HRDATA_S3(), 237 | .HRDATA_S4(), 238 | .HRDATA_S5(), 239 | .HRDATA_S6(), 240 | .HRDATA_S7(), 241 | .HRDATA_S8(), 242 | .HRDATA_S9(), 243 | .HRDATA_NOMAP(32'hDEADBEEF), 244 | 245 | .HREADYOUT_S0(hready_mem), 246 | .HREADYOUT_S1(hready_vga), 247 | .HREADYOUT_S2(hready_uart), 248 | .HREADYOUT_S3(), 249 | .HREADYOUT_S4(), 250 | .HREADYOUT_S5(), 251 | .HREADYOUT_S6(1'b1), 252 | .HREADYOUT_S7(1'b1), 253 | .HREADYOUT_S8(1'b1), 254 | .HREADYOUT_S9(1'b1), 255 | .HREADYOUT_NOMAP(1'b1), 256 | 257 | .HRDATA(hrdatas), 258 | .HREADY(hreadys) 259 | ); 260 | 261 | // AHBLite Peripherals 262 | 263 | // AHBLite Memory Controller 264 | AHB2MEM uAHB2RAM ( 265 | //AHBLITE Signals 266 | .HSEL(hsel_mem), 267 | .HCLK(fclk), 268 | .HRESETn(hresetn), 269 | .HREADY(hreadys), 270 | .HADDR(haddrs), 271 | .HTRANS(htranss), 272 | .HWRITE(hwrites), 273 | .HSIZE(hsizes), 274 | .HWDATA(hwdatas), 275 | 276 | .HRDATA(hrdata_mem), 277 | .HREADYOUT(hready_mem) 278 | ); 279 | 280 | 281 | 282 | // AHBLite VGA Controller 283 | AHBVGA uAHBVGA ( 284 | .HCLK(fclk), 285 | .HRESETn(hresetn), 286 | .HADDR(haddrs), 287 | .HWDATA(hwdatas), 288 | .HREADY(hreadys), 289 | .HWRITE(hwrites), 290 | .HTRANS(htranss), 291 | .HSEL(hsel_vga), 292 | .HRDATA(hrdata_vga), 293 | .HREADYOUT(hready_vga), 294 | .hsync(Hsync), 295 | .vsync(Vsync), 296 | .rgb({vgaRed,vgaGreen,vgaBlue}) 297 | ); 298 | 299 | // AHBLite UART Peripheral 300 | AHBUART uAHBUART( 301 | .HCLK(fclk), 302 | .HRESETn(hresetn), 303 | .HADDR(haddrs), 304 | .HTRANS(htranss), 305 | .HWDATA(hwdatas), 306 | .HWRITE(hwrites), 307 | .HREADY(hreadys), 308 | .HREADYOUT(hready_uart), 309 | .HRDATA(hrdata_uart), 310 | .HSEL(hsel_uart), 311 | 312 | .RsRx(RsRx), 313 | .RsTx(RsTx) 314 | ); 315 | 316 | // AHBLite 7-segment Pheripheral 317 | AHB7SEGDEC uAHB7SEGDEC( 318 | .HCLK(fclk), 319 | .HRESETn(hresetn), 320 | .HADDR(haddrs), 321 | .HTRANS(htranss), 322 | .HWDATA(hwdatas), 323 | .HWRITE(hwrites), 324 | .HREADY(hreadys), 325 | .HREADYOUT(hready_7seg), 326 | .HRDATA(hrdata_7seg), 327 | .HSEL(hsel_7seg), 328 | 329 | .seg(seg), 330 | .an(an), 331 | .dp(dp) 332 | ); 333 | 334 | // AHBLite timer 335 | AHBTIMER uAHBTIMER( 336 | .HCLK(fclk), 337 | .HRESETn(hresetn), 338 | .HADDR(haddrs), 339 | .HTRANS(htranss), 340 | .HWDATA(hwdatas), 341 | .HWRITE(hwrites), 342 | .HREADY(hreadys), 343 | .HREADYOUT(hready_timer), 344 | .HRDATA(hrdata_timer), 345 | .HSEL(hsel_timer) 346 | ); 347 | 348 | // AHBLite GPIO 349 | AHBGPIO uAHBGPIO( 350 | .HCLK(fclk), 351 | .HRESETn(hresetn), 352 | .HADDR(haddrs), 353 | .HWRITE(hwrites), 354 | .HWDATA(hwdatas), 355 | .HTRANS(htranss), 356 | .HSEL(hsel_gpio), 357 | .HREADY(hreadys), 358 | .GPIOIN({8'b00000000, sw[7:0]}), 359 | .HREADYOUT(hready_gpio), 360 | .HRDATA(hrdata_gpio), 361 | .GPIOOUT(LED[7:0]) 362 | ); 363 | 364 | 365 | 366 | 367 | endmodule 368 | -------------------------------------------------------------------------------- /SimpleLEDSOC/Arty_A7_Master.xdc: -------------------------------------------------------------------------------- 1 | ## This file is a general .xdc for the ARTY Rev. B 2 | ## To use it in a project: 3 | ## - uncomment the lines corresponding to used pins 4 | ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project 5 | 6 | ## Clock signal 7 | 8 | set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] 9 | create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK }]; 10 | 11 | 12 | set_property IOSTANDARD LVCMOS33 [get_ports TCK] 13 | set_property IOSTANDARD LVCMOS33 [get_ports TDI] 14 | set_property IOSTANDARD LVCMOS33 [get_ports TDO] 15 | set_property IOSTANDARD LVCMOS33 [get_ports TMS] 16 | set_property SLEW FAST [get_ports TDO] 17 | set_property SLEW FAST [get_ports TMS] 18 | set_property PACKAGE_PIN H4 [get_ports TMS] 19 | set_property PACKAGE_PIN H1 [get_ports TDI] 20 | set_property PACKAGE_PIN G1 [get_ports TDO] 21 | set_property PACKAGE_PIN G3 [get_ports TCK] 22 | 23 | create_clock -period 20.000 -name dbg_tck_pin -waveform {0.000 10.000} -add [get_ports TCK] 24 | set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TCK] 25 | 26 | ##Switches 27 | 28 | set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports { RESET }]; #IO_L12N_T1_MRCC_16 Sch=sw[0] 29 | #set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L13P_T2_MRCC_16 Sch=sw[1] 30 | #set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L13N_T2_MRCC_16 Sch=sw[2] 31 | #set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L14P_T2_SRCC_16 Sch=sw[3] 32 | 33 | ##RGB LEDs 34 | 35 | set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L18N_T2_35 Sch=led0_b 36 | #set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { led0_g }]; #IO_L19N_T3_VREF_35 Sch=led0_g 37 | #set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { led0_r }]; #IO_L19P_T3_35 Sch=led0_r 38 | set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L20P_T3_35 Sch=led1_b 39 | #set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { led1_g }]; #IO_L21P_T3_DQS_35 Sch=led1_g 40 | #set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { led1_r }]; #IO_L20N_T3_35 Sch=led1_r 41 | #set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { }]; #IO_L21N_T3_DQS_35 Sch=led2_b 42 | set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L22N_T3_35 Sch=led2_g 43 | #set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { led2_r }]; #IO_L22P_T3_35 Sch=led2_r 44 | set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L23P_T3_35 Sch=led3_b 45 | #set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { led3_g }]; #IO_L24P_T3_35 Sch=led3_g 46 | #set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { led3_r }]; #IO_L23N_T3_35 Sch=led3_r 47 | 48 | ##LEDs 49 | 50 | set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L24N_T3_35 Sch=led[4] 51 | set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_25_35 Sch=led[5] 52 | set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L24P_T3_A01_D17_14 Sch=led[6] 53 | set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L24N_T3_A00_D16_14 Sch=led[7] 54 | 55 | ##Buttons 56 | 57 | #set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L6N_T0_VREF_16 Sch=btn[0] 58 | #set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L11P_T1_SRCC_16 Sch=btn[1] 59 | #set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L11N_T1_SRCC_16 Sch=btn[2] 60 | #set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L12P_T1_MRCC_16 Sch=btn[3] 61 | 62 | ##Pmod Header JA 63 | 64 | #set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_0_15 Sch=ja[1] 65 | #set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4P_T0_15 Sch=ja[2] 66 | #set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L4N_T0_15 Sch=ja[3] 67 | #set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L6P_T0_15 Sch=ja[4] 68 | #set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L6N_T0_VREF_15 Sch=ja[7] 69 | #set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L10P_T1_AD11P_15 Sch=ja[8] 70 | #set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L10N_T1_AD11N_15 Sch=ja[9] 71 | #set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_25_15 Sch=ja[10] 72 | 73 | ##Pmod Header JB 74 | 75 | #set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { jb[0] }]; #IO_L11P_T1_SRCC_15 Sch=jb_p[1] 76 | #set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { jb[1] }]; #IO_L11N_T1_SRCC_15 Sch=jb_n[1] 77 | #set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { jb[2] }]; #IO_L12P_T1_MRCC_15 Sch=jb_p[2] 78 | #set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { jb[3] }]; #IO_L12N_T1_MRCC_15 Sch=jb_n[2] 79 | #set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { jb[4] }]; #IO_L23P_T3_FOE_B_15 Sch=jb_p[3] 80 | #set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { jb[5] }]; #IO_L23N_T3_FWE_B_15 Sch=jb_n[3] 81 | #set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { jb[6] }]; #IO_L24P_T3_RS1_15 Sch=jb_p[4] 82 | #set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { jb[7] }]; #IO_L24N_T3_RS0_15 Sch=jb_n[4] 83 | 84 | ##Pmod Header JC 85 | 86 | #set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { jc[0] }]; #IO_L20P_T3_A08_D24_14 Sch=jc_p[1] 87 | #set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { jc[1] }]; #IO_L20N_T3_A07_D23_14 Sch=jc_n[1] 88 | #set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { jc[2] }]; #IO_L21P_T3_DQS_14 Sch=jc_p[2] 89 | #set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { jc[3] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=jc_n[2] 90 | #set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { jc[4] }]; #IO_L22P_T3_A05_D21_14 Sch=jc_p[3] 91 | #set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { jc[5] }]; #IO_L22N_T3_A04_D20_14 Sch=jc_n[3] 92 | #set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { jc[6] }]; #IO_L23P_T3_A03_D19_14 Sch=jc_p[4] 93 | #set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { jc[7] }]; #IO_L23N_T3_A02_D18_14 Sch=jc_n[4] 94 | 95 | ##Pmod Header JD 96 | 97 | #set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports { jd[0] }]; #IO_L11N_T1_SRCC_35 Sch=jd[1] 98 | #set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { jd[1] }]; #IO_L12N_T1_MRCC_35 Sch=jd[2] 99 | #set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { jd[2] }]; #IO_L13P_T2_MRCC_35 Sch=jd[3] 100 | #set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { jd[3] }]; #IO_L13N_T2_MRCC_35 Sch=jd[4] 101 | #set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { jd[4] }]; #IO_L14P_T2_SRCC_35 Sch=jd[7] 102 | #set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { jd[5] }]; #IO_L14N_T2_SRCC_35 Sch=jd[8] 103 | #set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { jd[6] }]; #IO_L15P_T2_DQS_35 Sch=jd[9] 104 | #set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { jd[7] }]; #IO_L15N_T2_DQS_35 Sch=jd[10] 105 | 106 | ##USB-UART Interface 107 | 108 | #set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L19N_T3_VREF_16 Sch=uart_rxd_out 109 | #set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L14N_T2_SRCC_16 Sch=uart_txd_in 110 | 111 | ##ChipKit Single Ended Analog Inputs 112 | ##NOTE: The ck_an_p pins can be used as single ended analog inputs with voltages from 0-3.3V (Chipkit Analog pins A0-A5). 113 | ## These signals should only be connected to the XADC core. When using these pins as digital I/O, use pins ck_io[14-19]. 114 | 115 | #set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ck_an_n[0] 116 | #set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ck_an_p[0] 117 | #set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[1] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=ck_an_n[1] 118 | #set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[1] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=ck_an_p[1] 119 | #set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[2] }]; #IO_L7N_T1_AD6N_35 Sch=ck_an_n[2] 120 | #set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[2] }]; #IO_L7P_T1_AD6P_35 Sch=ck_an_p[2] 121 | #set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[3] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=ck_an_n[3] 122 | #set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[3] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=ck_an_p[3] 123 | #set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[4] }]; #IO_L10N_T1_AD15N_35 Sch=ck_an_n[4] 124 | #set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[4] }]; #IO_L10P_T1_AD15P_35 Sch=ck_an_p[4] 125 | #set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_n[5] }]; #IO_L1N_T0_AD0N_15 Sch=ck_an_n[5] 126 | #set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { ck_an_p[5] }]; #IO_L1P_T0_AD0P_15 Sch=ck_an_p[5] 127 | 128 | ##ChipKit Digital I/O Low 129 | 130 | #set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[0] }]; #IO_L16P_T2_CSI_B_14 Sch=ck_io[0] 131 | #set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[1] }]; #IO_L18P_T2_A12_D28_14 Sch=ck_io[1] 132 | #set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[2] }]; #IO_L8N_T1_D12_14 Sch=ck_io[2] 133 | #set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[3] }]; #IO_L19P_T3_A10_D26_14 Sch=ck_io[3] 134 | #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { ck_io[4] }]; #IO_L5P_T0_D06_14 Sch=ck_io[4] 135 | #set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[5] }]; #IO_L14P_T2_SRCC_14 Sch=ck_io[5] 136 | #set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[6] }]; #IO_L14N_T2_SRCC_14 Sch=ck_io[6] 137 | #set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[7] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=ck_io[7] 138 | #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[8] }]; #IO_L11P_T1_SRCC_14 Sch=ck_io[8] 139 | #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[9] }]; #IO_L10P_T1_D14_14 Sch=ck_io[9] 140 | #set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[10] }]; #IO_L18N_T2_A11_D27_14 Sch=ck_io[10] 141 | #set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[11] }]; #IO_L17N_T2_A13_D29_14 Sch=ck_io[11] 142 | #set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[12] }]; #IO_L12N_T1_MRCC_14 Sch=ck_io[12] 143 | #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[13] }]; #IO_L12P_T1_MRCC_14 Sch=ck_io[13] 144 | 145 | ##ChipKit Digital I/O On Outer Analog Header 146 | ##NOTE: These pins should be used when using the analog header signals A0-A5 as digital I/O (Chipkit digital pins 14-19) 147 | 148 | #set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[14] }]; #IO_0_35 Sch=ck_a[0] 149 | #set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { ck_io[15] }]; #IO_L4P_T0_35 Sch=ck_a[1] 150 | #set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[16] }]; #IO_L4N_T0_35 Sch=ck_a[2] 151 | #set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[17] }]; #IO_L6P_T0_35 Sch=ck_a[3] 152 | #set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[18] }]; #IO_L6N_T0_VREF_35 Sch=ck_a[4] 153 | #set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[19] }]; #IO_L11P_T1_SRCC_35 Sch=ck_a[5] 154 | 155 | ##ChipKit Digital I/O On Inner Analog Header 156 | ##NOTE: These pins will need to be connected to the XADC core when used as differential analog inputs (Chipkit analog pins A6-A11) 157 | 158 | #set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { ck_io[20] }]; #IO_L2P_T0_AD12P_35 Sch=ad_p[12] 159 | #set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[21] }]; #IO_L2N_T0_AD12N_35 Sch=ad_n[12] 160 | #set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { ck_io[22] }]; #IO_L5P_T0_AD13P_35 Sch=ad_p[13] 161 | #set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { ck_io[23] }]; #IO_L5N_T0_AD13N_35 Sch=ad_n[13] 162 | #set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { ck_io[24] }]; #IO_L8P_T1_AD14P_35 Sch=ad_p[14] 163 | #set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { ck_io[25] }]; #IO_L8N_T1_AD14N_35 Sch=ad_n[14] 164 | 165 | ##ChipKit Digital I/O High 166 | 167 | #set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[26] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=ck_io[26] 168 | #set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[27] }]; #IO_L16N_T2_A15_D31_14 Sch=ck_io[27] 169 | #set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[28] }]; #IO_L6N_T0_D08_VREF_14 Sch=ck_io[28] 170 | #set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { ck_io[29] }]; #IO_25_14 Sch=ck_io[29] 171 | #set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { ck_io[30] }]; #IO_0_14 Sch=ck_io[30] 172 | #set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { ck_io[31] }]; #IO_L5N_T0_D07_14 Sch=ck_io[31] 173 | #set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[32] }]; #IO_L13N_T2_MRCC_14 Sch=ck_io[32] 174 | #set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ck_io[33] }]; #IO_L13P_T2_MRCC_14 Sch=ck_io[33] 175 | #set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[34] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=ck_io[34] 176 | #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { ck_io[35] }]; #IO_L11N_T1_SRCC_14 Sch=ck_io[35] 177 | #set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { ck_io[36] }]; #IO_L8P_T1_D11_14 Sch=ck_io[36] 178 | #set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[37] }]; #IO_L17P_T2_A14_D30_14 Sch=ck_io[37] 179 | #set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[38] }]; #IO_L7N_T1_D10_14 Sch=ck_io[38] 180 | #set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[39] }]; #IO_L7P_T1_D09_14 Sch=ck_io[39] 181 | #set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { ck_io[40] }]; #IO_L9N_T1_DQS_D13_14 Sch=ck_io[40] 182 | #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { ck_io[41] }]; #IO_L9P_T1_DQS_14 Sch=ck_io[41] 183 | 184 | ## ChipKit SPI 185 | 186 | #set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { ck_miso }]; #IO_L17N_T2_35 Sch=ck_miso 187 | #set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { ck_mosi }]; #IO_L17P_T2_35 Sch=ck_mosi 188 | #set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { ck_sck }]; #IO_L18P_T2_35 Sch=ck_sck 189 | #set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { ck_ss }]; #IO_L16N_T2_35 Sch=ck_ss 190 | 191 | ## ChipKit I2C 192 | 193 | #set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ck_scl }]; #IO_L4P_T0_D04_14 Sch=ck_scl 194 | #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { ck_sda }]; #IO_L4N_T0_D05_14 Sch=ck_sda 195 | #set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { scl_pup }]; #IO_L9N_T1_DQS_AD3N_15 Sch=scl_pup 196 | #set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVCMOS33 } [get_ports { sda_pup }]; #IO_L9P_T1_DQS_AD3P_15 Sch=sda_pup 197 | 198 | ##Misc. ChipKit signals 199 | 200 | #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { ck_ioa }]; #IO_L10N_T1_D15_14 Sch=ck_ioa 201 | #set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { ck_rst }]; #IO_L16P_T2_35 Sch=ck_rst 202 | 203 | ##SMSC Ethernet PHY 204 | 205 | #set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { eth_col }]; #IO_L16N_T2_A27_15 Sch=eth_col 206 | #set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { eth_crs }]; #IO_L15N_T2_DQS_ADV_B_15 Sch=eth_crs 207 | #set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { eth_mdc }]; #IO_L14N_T2_SRCC_15 Sch=eth_mdc 208 | #set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { eth_mdio }]; #IO_L17P_T2_A26_15 Sch=eth_mdio 209 | #set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { eth_ref_clk }]; #IO_L22P_T3_A17_15 Sch=eth_ref_clk 210 | #set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { eth_rstn }]; #IO_L20P_T3_A20_15 Sch=eth_rstn 211 | #set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_clk }]; #IO_L14P_T2_SRCC_15 Sch=eth_rx_clk 212 | #set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { eth_rx_dv }]; #IO_L13N_T2_MRCC_15 Sch=eth_rx_dv 213 | #set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[0] }]; #IO_L21N_T3_DQS_A18_15 Sch=eth_rxd[0] 214 | #set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[1] }]; #IO_L16P_T2_A28_15 Sch=eth_rxd[1] 215 | #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[2] }]; #IO_L21P_T3_DQS_15 Sch=eth_rxd[2] 216 | #set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxd[3] }]; #IO_L18N_T2_A23_15 Sch=eth_rxd[3] 217 | #set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { eth_rxerr }]; #IO_L20N_T3_A19_15 Sch=eth_rxerr 218 | #set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_clk }]; #IO_L13P_T2_MRCC_15 Sch=eth_tx_clk 219 | #set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { eth_tx_en }]; #IO_L19N_T3_A21_VREF_15 Sch=eth_tx_en 220 | #set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[0] }]; #IO_L15P_T2_DQS_15 Sch=eth_txd[0] 221 | #set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[1] }]; #IO_L19P_T3_A22_15 Sch=eth_txd[1] 222 | #set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[2] }]; #IO_L17N_T2_A25_15 Sch=eth_txd[2] 223 | #set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { eth_txd[3] }]; #IO_L18P_T2_A24_15 Sch=eth_txd[3] 224 | 225 | ##Quad SPI Flash 226 | 227 | #set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs 228 | #set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] 229 | #set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] 230 | #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] 231 | #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] 232 | 233 | ##Power Measurements 234 | 235 | #set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_n }]; #IO_L7N_T1_AD2N_15 Sch=ad_n[2] 236 | #set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { vsnsvu_p }]; #IO_L7P_T1_AD2P_15 Sch=ad_p[2] 237 | #set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_n }]; #IO_L3N_T0_DQS_AD1N_15 Sch=ad_n[1] 238 | #set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { vsns5v0_p }]; #IO_L3P_T0_DQS_AD1P_15 Sch=ad_p[1] 239 | #set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_n }]; #IO_L5N_T0_AD9N_15 Sch=ad_n[9] 240 | #set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { isns5v0_p }]; #IO_L5P_T0_AD9P_15 Sch=ad_p[9] 241 | #set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_n }]; #IO_L8N_T1_AD10N_15 Sch=ad_n[10] 242 | #set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { isns0v95_p }]; #IO_L8P_T1_AD10P_15 Sch=ad_p[10] -------------------------------------------------------------------------------- /Final_SOC/font_rom.v: -------------------------------------------------------------------------------- 1 | 2 | 3 | module font_rom 4 | ( 5 | input wire clk, 6 | input wire [10:0] addr, 7 | output reg [7:0] data 8 | ); 9 | 10 | // signal declaration 11 | reg [10:0] addr_reg; 12 | 13 | // body 14 | always @(posedge clk) 15 | addr_reg <= addr; 16 | 17 | always @* 18 | case (addr_reg) 19 | //code x00 20 | 11'h000: data = 8'b00000000; // 21 | 11'h001: data = 8'b00000000; // 22 | 11'h002: data = 8'b00000000; // 23 | 11'h003: data = 8'b00000000; // 24 | 11'h004: data = 8'b00000000; // 25 | 11'h005: data = 8'b00000000; // 26 | 11'h006: data = 8'b00000000; // 27 | 11'h007: data = 8'b00000000; // 28 | 11'h008: data = 8'b00000000; // 29 | 11'h009: data = 8'b00000000; // 30 | 11'h00a: data = 8'b00000000; // 31 | 11'h00b: data = 8'b00000000; // 32 | 11'h00c: data = 8'b00000000; // 33 | 11'h00d: data = 8'b00000000; // 34 | 11'h00e: data = 8'b00000000; // 35 | 11'h00f: data = 8'b00000000; // 36 | //code x01 37 | 11'h010: data = 8'b00000000; // 38 | 11'h011: data = 8'b00000000; // 39 | 11'h012: data = 8'b01111110; // ****** 40 | 11'h013: data = 8'b10000001; // * * 41 | 11'h014: data = 8'b10100101; // * * * * 42 | 11'h015: data = 8'b10000001; // * * 43 | 11'h016: data = 8'b10000001; // * * 44 | 11'h017: data = 8'b10111101; // * **** * 45 | 11'h018: data = 8'b10011001; // * ** * 46 | 11'h019: data = 8'b10000001; // * * 47 | 11'h01a: data = 8'b10000001; // * * 48 | 11'h01b: data = 8'b01111110; // ****** 49 | 11'h01c: data = 8'b00000000; // 50 | 11'h01d: data = 8'b00000000; // 51 | 11'h01e: data = 8'b00000000; // 52 | 11'h01f: data = 8'b00000000; // 53 | //code x02 54 | 11'h020: data = 8'b00000000; // 55 | 11'h021: data = 8'b00000000; // 56 | 11'h022: data = 8'b01111110; // ****** 57 | 11'h023: data = 8'b11111111; // ******** 58 | 11'h024: data = 8'b11011011; // ** ** ** 59 | 11'h025: data = 8'b11111111; // ******** 60 | 11'h026: data = 8'b11111111; // ******** 61 | 11'h027: data = 8'b11000011; // ** ** 62 | 11'h028: data = 8'b11100111; // *** *** 63 | 11'h029: data = 8'b11111111; // ******** 64 | 11'h02a: data = 8'b11111111; // ******** 65 | 11'h02b: data = 8'b01111110; // ****** 66 | 11'h02c: data = 8'b00000000; // 67 | 11'h02d: data = 8'b00000000; // 68 | 11'h02e: data = 8'b00000000; // 69 | 11'h02f: data = 8'b00000000; // 70 | //code x03 71 | 11'h030: data = 8'b00000000; // 72 | 11'h031: data = 8'b00000000; // 73 | 11'h032: data = 8'b00000000; // 74 | 11'h033: data = 8'b00000000; // 75 | 11'h034: data = 8'b01101100; // ** ** 76 | 11'h035: data = 8'b11111110; // ******* 77 | 11'h036: data = 8'b11111110; // ******* 78 | 11'h037: data = 8'b11111110; // ******* 79 | 11'h038: data = 8'b11111110; // ******* 80 | 11'h039: data = 8'b01111100; // ***** 81 | 11'h03a: data = 8'b00111000; // *** 82 | 11'h03b: data = 8'b00010000; // * 83 | 11'h03c: data = 8'b00000000; // 84 | 11'h03d: data = 8'b00000000; // 85 | 11'h03e: data = 8'b00000000; // 86 | 11'h03f: data = 8'b00000000; // 87 | //code x04 88 | 11'h040: data = 8'b00000000; // 89 | 11'h041: data = 8'b00000000; // 90 | 11'h042: data = 8'b00000000; // 91 | 11'h043: data = 8'b00000000; // 92 | 11'h044: data = 8'b00010000; // * 93 | 11'h045: data = 8'b00111000; // *** 94 | 11'h046: data = 8'b01111100; // ***** 95 | 11'h047: data = 8'b11111110; // ******* 96 | 11'h048: data = 8'b01111100; // ***** 97 | 11'h049: data = 8'b00111000; // *** 98 | 11'h04a: data = 8'b00010000; // * 99 | 11'h04b: data = 8'b00000000; // 100 | 11'h04c: data = 8'b00000000; // 101 | 11'h04d: data = 8'b00000000; // 102 | 11'h04e: data = 8'b00000000; // 103 | 11'h04f: data = 8'b00000000; // 104 | //code x05 105 | 11'h050: data = 8'b00000000; // 106 | 11'h051: data = 8'b00000000; // 107 | 11'h052: data = 8'b00000000; // 108 | 11'h053: data = 8'b00011000; // ** 109 | 11'h054: data = 8'b00111100; // **** 110 | 11'h055: data = 8'b00111100; // **** 111 | 11'h056: data = 8'b11100111; // *** *** 112 | 11'h057: data = 8'b11100111; // *** *** 113 | 11'h058: data = 8'b11100111; // *** *** 114 | 11'h059: data = 8'b00011000; // ** 115 | 11'h05a: data = 8'b00011000; // ** 116 | 11'h05b: data = 8'b00111100; // **** 117 | 11'h05c: data = 8'b00000000; // 118 | 11'h05d: data = 8'b00000000; // 119 | 11'h05e: data = 8'b00000000; // 120 | 11'h05f: data = 8'b00000000; // 121 | //code x06 122 | 11'h060: data = 8'b00000000; // 123 | 11'h061: data = 8'b00000000; // 124 | 11'h062: data = 8'b00000000; // 125 | 11'h063: data = 8'b00011000; // ** 126 | 11'h064: data = 8'b00111100; // **** 127 | 11'h065: data = 8'b01111110; // ****** 128 | 11'h066: data = 8'b11111111; // ******** 129 | 11'h067: data = 8'b11111111; // ******** 130 | 11'h068: data = 8'b01111110; // ****** 131 | 11'h069: data = 8'b00011000; // ** 132 | 11'h06a: data = 8'b00011000; // ** 133 | 11'h06b: data = 8'b00111100; // **** 134 | 11'h06c: data = 8'b00000000; // 135 | 11'h06d: data = 8'b00000000; // 136 | 11'h06e: data = 8'b00000000; // 137 | 11'h06f: data = 8'b00000000; // 138 | //code x07 139 | 11'h070: data = 8'b00000000; // 140 | 11'h071: data = 8'b00000000; // 141 | 11'h072: data = 8'b00000000; // 142 | 11'h073: data = 8'b00000000; // 143 | 11'h074: data = 8'b00000000; // 144 | 11'h075: data = 8'b00000000; // 145 | 11'h076: data = 8'b00011000; // ** 146 | 11'h077: data = 8'b00111100; // **** 147 | 11'h078: data = 8'b00111100; // **** 148 | 11'h079: data = 8'b00011000; // ** 149 | 11'h07a: data = 8'b00000000; // 150 | 11'h07b: data = 8'b00000000; // 151 | 11'h07c: data = 8'b00000000; // 152 | 11'h07d: data = 8'b00000000; // 153 | 11'h07e: data = 8'b00000000; // 154 | 11'h07f: data = 8'b00000000; // 155 | //code x08 156 | 11'h080: data = 8'b00000000; // 157 | 11'h081: data = 8'b00000000; // 158 | 11'h082: data = 8'b00000000; // 159 | 11'h083: data = 8'b00000000; // 160 | 11'h084: data = 8'b00000000; // 161 | 11'h085: data = 8'b00000000; // 162 | 11'h086: data = 8'b00000000; // 163 | 11'h087: data = 8'b00000000; // 164 | 11'h088: data = 8'b00000000; // 165 | 11'h089: data = 8'b00000000; // 166 | 11'h08a: data = 8'b00000000; // 167 | 11'h08b: data = 8'b00000000; // 168 | 11'h08c: data = 8'b00000000; // 169 | 11'h08d: data = 8'b00000000; // 170 | 11'h08e: data = 8'b00000000; // 171 | 11'h08f: data = 8'b00000000; // 172 | //code x09 173 | 11'h090: data = 8'b00000000; // 174 | 11'h091: data = 8'b00000000; // 175 | 11'h092: data = 8'b00000000; // 176 | 11'h093: data = 8'b00000000; // 177 | 11'h094: data = 8'b00000000; // 178 | 11'h095: data = 8'b00111100; // **** 179 | 11'h096: data = 8'b01100110; // ** ** 180 | 11'h097: data = 8'b01000010; // * * 181 | 11'h098: data = 8'b01000010; // * * 182 | 11'h099: data = 8'b01100110; // ** ** 183 | 11'h09a: data = 8'b00111100; // **** 184 | 11'h09b: data = 8'b00000000; // 185 | 11'h09c: data = 8'b00000000; // 186 | 11'h09d: data = 8'b00000000; // 187 | 11'h09e: data = 8'b00000000; // 188 | 11'h09f: data = 8'b00000000; // 189 | //code x0a 190 | 11'h0a0: data = 8'b00000000; // 191 | 11'h0a1: data = 8'b00000000; // 192 | 11'h0a2: data = 8'b00000000; // 193 | 11'h0a3: data = 8'b00000000; // 194 | 11'h0a4: data = 8'b00000000; // 195 | 11'h0a5: data = 8'b00000000; // 196 | 11'h0a6: data = 8'b00000000; // 197 | 11'h0a7: data = 8'b00000000; // 198 | 11'h0a8: data = 8'b00000000; // 199 | 11'h0a9: data = 8'b00000000; // 200 | 11'h0aa: data = 8'b00000000; // 201 | 11'h0ab: data = 8'b00000000; // 202 | 11'h0ac: data = 8'b00000000; // 203 | 11'h0ad: data = 8'b00000000; // 204 | 11'h0ae: data = 8'b00000000; // 205 | 11'h0af: data = 8'b00000000; // 206 | //code x0b 207 | 11'h0b0: data = 8'b00000000; // 208 | 11'h0b1: data = 8'b00000000; // 209 | 11'h0b2: data = 8'b00011110; // **** 210 | 11'h0b3: data = 8'b00001110; // *** 211 | 11'h0b4: data = 8'b00011010; // ** * 212 | 11'h0b5: data = 8'b00110010; // ** * 213 | 11'h0b6: data = 8'b01111000; // **** 214 | 11'h0b7: data = 8'b11001100; // ** ** 215 | 11'h0b8: data = 8'b11001100; // ** ** 216 | 11'h0b9: data = 8'b11001100; // ** ** 217 | 11'h0ba: data = 8'b11001100; // ** ** 218 | 11'h0bb: data = 8'b01111000; // **** 219 | 11'h0bc: data = 8'b00000000; // 220 | 11'h0bd: data = 8'b00000000; // 221 | 11'h0be: data = 8'b00000000; // 222 | 11'h0bf: data = 8'b00000000; // 223 | //code x0c 224 | 11'h0c0: data = 8'b00000000; // 225 | 11'h0c1: data = 8'b00000000; // 226 | 11'h0c2: data = 8'b00111100; // **** 227 | 11'h0c3: data = 8'b01100110; // ** ** 228 | 11'h0c4: data = 8'b01100110; // ** ** 229 | 11'h0c5: data = 8'b01100110; // ** ** 230 | 11'h0c6: data = 8'b01100110; // ** ** 231 | 11'h0c7: data = 8'b00111100; // **** 232 | 11'h0c8: data = 8'b00011000; // ** 233 | 11'h0c9: data = 8'b01111110; // ****** 234 | 11'h0ca: data = 8'b00011000; // ** 235 | 11'h0cb: data = 8'b00011000; // ** 236 | 11'h0cc: data = 8'b00000000; // 237 | 11'h0cd: data = 8'b00000000; // 238 | 11'h0ce: data = 8'b00000000; // 239 | 11'h0cf: data = 8'b00000000; // 240 | //code x0d 241 | 11'h0d0: data = 8'b00000000; // 242 | 11'h0d1: data = 8'b00000000; // 243 | 11'h0d2: data = 8'b00000000; // 244 | 11'h0d3: data = 8'b00000000; // 245 | 11'h0d4: data = 8'b00000000; // 246 | 11'h0d5: data = 8'b00000000; // 247 | 11'h0d6: data = 8'b00000000; // 248 | 11'h0d7: data = 8'b00000000; // 249 | 11'h0d8: data = 8'b00000000; // 250 | 11'h0d9: data = 8'b00000000; // 251 | 11'h0da: data = 8'b00000000; // 252 | 11'h0db: data = 8'b00000000; // 253 | 11'h0dc: data = 8'b00000000; // 254 | 11'h0dd: data = 8'b00000000; // 255 | 11'h0de: data = 8'b00000000; // 256 | 11'h0df: data = 8'b00000000; // 257 | //code x0e 258 | 11'h0e0: data = 8'b00000000; // 259 | 11'h0e1: data = 8'b00000000; // 260 | 11'h0e2: data = 8'b01111111; // ******* 261 | 11'h0e3: data = 8'b01100011; // ** ** 262 | 11'h0e4: data = 8'b01111111; // ******* 263 | 11'h0e5: data = 8'b01100011; // ** ** 264 | 11'h0e6: data = 8'b01100011; // ** ** 265 | 11'h0e7: data = 8'b01100011; // ** ** 266 | 11'h0e8: data = 8'b01100011; // ** ** 267 | 11'h0e9: data = 8'b01100111; // ** *** 268 | 11'h0ea: data = 8'b11100111; // *** *** 269 | 11'h0eb: data = 8'b11100110; // *** ** 270 | 11'h0ec: data = 8'b11000000; // ** 271 | 11'h0ed: data = 8'b00000000; // 272 | 11'h0ee: data = 8'b00000000; // 273 | 11'h0ef: data = 8'b00000000; // 274 | //code x0f 275 | 11'h0f0: data = 8'b00000000; // 276 | 11'h0f1: data = 8'b00000000; // 277 | 11'h0f2: data = 8'b00000000; // 278 | 11'h0f3: data = 8'b00011000; // ** 279 | 11'h0f4: data = 8'b00011000; // ** 280 | 11'h0f5: data = 8'b11011011; // ** ** ** 281 | 11'h0f6: data = 8'b00111100; // **** 282 | 11'h0f7: data = 8'b11100111; // *** *** 283 | 11'h0f8: data = 8'b00111100; // **** 284 | 11'h0f9: data = 8'b11011011; // ** ** ** 285 | 11'h0fa: data = 8'b00011000; // ** 286 | 11'h0fb: data = 8'b00011000; // ** 287 | 11'h0fc: data = 8'b00000000; // 288 | 11'h0fd: data = 8'b00000000; // 289 | 11'h0fe: data = 8'b00000000; // 290 | 11'h0ff: data = 8'b00000000; // 291 | //code x10 292 | 11'h100: data = 8'b00000000; // 293 | 11'h101: data = 8'b10000000; // * 294 | 11'h102: data = 8'b11000000; // ** 295 | 11'h103: data = 8'b11100000; // *** 296 | 11'h104: data = 8'b11110000; // **** 297 | 11'h105: data = 8'b11111000; // ***** 298 | 11'h106: data = 8'b11111110; // ******* 299 | 11'h107: data = 8'b11111000; // ***** 300 | 11'h108: data = 8'b11110000; // **** 301 | 11'h109: data = 8'b11100000; // *** 302 | 11'h10a: data = 8'b11000000; // ** 303 | 11'h10b: data = 8'b10000000; // * 304 | 11'h10c: data = 8'b00000000; // 305 | 11'h10d: data = 8'b00000000; // 306 | 11'h10e: data = 8'b00000000; // 307 | 11'h10f: data = 8'b00000000; // 308 | //code x11 309 | 11'h110: data = 8'b00000000; // 310 | 11'h111: data = 8'b00000010; // * 311 | 11'h112: data = 8'b00000110; // ** 312 | 11'h113: data = 8'b00001110; // *** 313 | 11'h114: data = 8'b00011110; // **** 314 | 11'h115: data = 8'b00111110; // ***** 315 | 11'h116: data = 8'b11111110; // ******* 316 | 11'h117: data = 8'b00111110; // ***** 317 | 11'h118: data = 8'b00011110; // **** 318 | 11'h119: data = 8'b00001110; // *** 319 | 11'h11a: data = 8'b00000110; // ** 320 | 11'h11b: data = 8'b00000010; // * 321 | 11'h11c: data = 8'b00000000; // 322 | 11'h11d: data = 8'b00000000; // 323 | 11'h11e: data = 8'b00000000; // 324 | 11'h11f: data = 8'b00000000; // 325 | //code x12 326 | 11'h120: data = 8'b00000000; // 327 | 11'h121: data = 8'b00000000; // 328 | 11'h122: data = 8'b00011000; // ** 329 | 11'h123: data = 8'b00111100; // **** 330 | 11'h124: data = 8'b01111110; // ****** 331 | 11'h125: data = 8'b00011000; // ** 332 | 11'h126: data = 8'b00011000; // ** 333 | 11'h127: data = 8'b00011000; // ** 334 | 11'h128: data = 8'b01111110; // ****** 335 | 11'h129: data = 8'b00111100; // **** 336 | 11'h12a: data = 8'b00011000; // ** 337 | 11'h12b: data = 8'b00000000; // 338 | 11'h12c: data = 8'b00000000; // 339 | 11'h12d: data = 8'b00000000; // 340 | 11'h12e: data = 8'b00000000; // 341 | 11'h12f: data = 8'b00000000; // 342 | //code x13 343 | 11'h130: data = 8'b00000000; // 344 | 11'h131: data = 8'b00000000; // 345 | 11'h132: data = 8'b01100110; // ** ** 346 | 11'h133: data = 8'b01100110; // ** ** 347 | 11'h134: data = 8'b01100110; // ** ** 348 | 11'h135: data = 8'b01100110; // ** ** 349 | 11'h136: data = 8'b01100110; // ** ** 350 | 11'h137: data = 8'b01100110; // ** ** 351 | 11'h138: data = 8'b01100110; // ** ** 352 | 11'h139: data = 8'b00000000; // 353 | 11'h13a: data = 8'b01100110; // ** ** 354 | 11'h13b: data = 8'b01100110; // ** ** 355 | 11'h13c: data = 8'b00000000; // 356 | 11'h13d: data = 8'b00000000; // 357 | 11'h13e: data = 8'b00000000; // 358 | 11'h13f: data = 8'b00000000; // 359 | //code x14 360 | 11'h140: data = 8'b00000000; // 361 | 11'h141: data = 8'b00000000; // 362 | 11'h142: data = 8'b01111111; // ******* 363 | 11'h143: data = 8'b11011011; // ** ** ** 364 | 11'h144: data = 8'b11011011; // ** ** ** 365 | 11'h145: data = 8'b11011011; // ** ** ** 366 | 11'h146: data = 8'b01111011; // **** ** 367 | 11'h147: data = 8'b00011011; // ** ** 368 | 11'h148: data = 8'b00011011; // ** ** 369 | 11'h149: data = 8'b00011011; // ** ** 370 | 11'h14a: data = 8'b00011011; // ** ** 371 | 11'h14b: data = 8'b00011011; // ** ** 372 | 11'h14c: data = 8'b00000000; // 373 | 11'h14d: data = 8'b00000000; // 374 | 11'h14e: data = 8'b00000000; // 375 | 11'h14f: data = 8'b00000000; // 376 | //code x15 377 | 11'h150: data = 8'b00000000; // 378 | 11'h151: data = 8'b01111100; // ***** 379 | 11'h152: data = 8'b11000110; // ** ** 380 | 11'h153: data = 8'b01100000; // ** 381 | 11'h154: data = 8'b00111000; // *** 382 | 11'h155: data = 8'b01101100; // ** ** 383 | 11'h156: data = 8'b11000110; // ** ** 384 | 11'h157: data = 8'b11000110; // ** ** 385 | 11'h158: data = 8'b01101100; // ** ** 386 | 11'h159: data = 8'b00111000; // *** 387 | 11'h15a: data = 8'b00001100; // ** 388 | 11'h15b: data = 8'b11000110; // ** ** 389 | 11'h15c: data = 8'b01111100; // ***** 390 | 11'h15d: data = 8'b00000000; // 391 | 11'h15e: data = 8'b00000000; // 392 | 11'h15f: data = 8'b00000000; // 393 | //code x16 394 | 11'h160: data = 8'b00000000; // 395 | 11'h161: data = 8'b00000000; // 396 | 11'h162: data = 8'b00000000; // 397 | 11'h163: data = 8'b00000000; // 398 | 11'h164: data = 8'b00000000; // 399 | 11'h165: data = 8'b00000000; // 400 | 11'h166: data = 8'b00000000; // 401 | 11'h167: data = 8'b00000000; // 402 | 11'h168: data = 8'b11111110; // ******* 403 | 11'h169: data = 8'b11111110; // ******* 404 | 11'h16a: data = 8'b11111110; // ******* 405 | 11'h16b: data = 8'b11111110; // ******* 406 | 11'h16c: data = 8'b00000000; // 407 | 11'h16d: data = 8'b00000000; // 408 | 11'h16e: data = 8'b00000000; // 409 | 11'h16f: data = 8'b00000000; // 410 | //code x17 411 | 11'h170: data = 8'b00000000; // 412 | 11'h171: data = 8'b00000000; // 413 | 11'h172: data = 8'b00011000; // ** 414 | 11'h173: data = 8'b00111100; // **** 415 | 11'h174: data = 8'b01111110; // ****** 416 | 11'h175: data = 8'b00011000; // ** 417 | 11'h176: data = 8'b00011000; // ** 418 | 11'h177: data = 8'b00011000; // ** 419 | 11'h178: data = 8'b01111110; // ****** 420 | 11'h179: data = 8'b00111100; // **** 421 | 11'h17a: data = 8'b00011000; // ** 422 | 11'h17b: data = 8'b01111110; // ****** 423 | 11'h17c: data = 8'b00110000; // 424 | 11'h17d: data = 8'b00000000; // 425 | 11'h17e: data = 8'b00000000; // 426 | 11'h17f: data = 8'b00000000; // 427 | //code x18 428 | 11'h180: data = 8'b00000000; // 429 | 11'h181: data = 8'b00000000; // 430 | 11'h182: data = 8'b00011000; // ** 431 | 11'h183: data = 8'b00111100; // **** 432 | 11'h184: data = 8'b01111110; // ****** 433 | 11'h185: data = 8'b00011000; // ** 434 | 11'h186: data = 8'b00011000; // ** 435 | 11'h187: data = 8'b00011000; // ** 436 | 11'h188: data = 8'b00011000; // ** 437 | 11'h189: data = 8'b00011000; // ** 438 | 11'h18a: data = 8'b00011000; // ** 439 | 11'h18b: data = 8'b00011000; // ** 440 | 11'h18c: data = 8'b00000000; // 441 | 11'h18d: data = 8'b00000000; // 442 | 11'h18e: data = 8'b00000000; // 443 | 11'h18f: data = 8'b00000000; // 444 | //code x19 445 | 11'h190: data = 8'b00000000; // 446 | 11'h191: data = 8'b00000000; // 447 | 11'h192: data = 8'b00011000; // ** 448 | 11'h193: data = 8'b00011000; // ** 449 | 11'h194: data = 8'b00011000; // ** 450 | 11'h195: data = 8'b00011000; // ** 451 | 11'h196: data = 8'b00011000; // ** 452 | 11'h197: data = 8'b00011000; // ** 453 | 11'h198: data = 8'b00011000; // ** 454 | 11'h199: data = 8'b01111110; // ****** 455 | 11'h19a: data = 8'b00111100; // **** 456 | 11'h19b: data = 8'b00011000; // ** 457 | 11'h19c: data = 8'b00000000; // 458 | 11'h19d: data = 8'b00000000; // 459 | 11'h19e: data = 8'b00000000; // 460 | 11'h19f: data = 8'b00000000; // 461 | //code x1a 462 | 11'h1a0: data = 8'b00000000; // 463 | 11'h1a1: data = 8'b00000000; // 464 | 11'h1a2: data = 8'b00000000; // 465 | 11'h1a3: data = 8'b00000000; // 466 | 11'h1a4: data = 8'b00000000; // 467 | 11'h1a5: data = 8'b00011000; // ** 468 | 11'h1a6: data = 8'b00001100; // ** 469 | 11'h1a7: data = 8'b11111110; // ******* 470 | 11'h1a8: data = 8'b00001100; // ** 471 | 11'h1a9: data = 8'b00011000; // ** 472 | 11'h1aa: data = 8'b00000000; // 473 | 11'h1ab: data = 8'b00000000; // 474 | 11'h1ac: data = 8'b00000000; // 475 | 11'h1ad: data = 8'b00000000; // 476 | 11'h1ae: data = 8'b00000000; // 477 | 11'h1af: data = 8'b00000000; // 478 | //code x1b 479 | 11'h1b0: data = 8'b00000000; // 480 | 11'h1b1: data = 8'b00000000; // 481 | 11'h1b2: data = 8'b00000000; // 482 | 11'h1b3: data = 8'b00000000; // 483 | 11'h1b4: data = 8'b00000000; // 484 | 11'h1b5: data = 8'b00110000; // ** 485 | 11'h1b6: data = 8'b01100000; // ** 486 | 11'h1b7: data = 8'b11111110; // ******* 487 | 11'h1b8: data = 8'b01100000; // ** 488 | 11'h1b9: data = 8'b00110000; // ** 489 | 11'h1ba: data = 8'b00000000; // 490 | 11'h1bb: data = 8'b00000000; // 491 | 11'h1bc: data = 8'b00000000; // 492 | 11'h1bd: data = 8'b00000000; // 493 | 11'h1be: data = 8'b00000000; // 494 | 11'h1bf: data = 8'b00000000; // 495 | //code x1c 496 | 11'h1c0: data = 8'b00000000; // 497 | 11'h1c1: data = 8'b00000000; // 498 | 11'h1c2: data = 8'b00000000; // 499 | 11'h1c3: data = 8'b00000000; // 500 | 11'h1c4: data = 8'b00000000; // 501 | 11'h1c5: data = 8'b00000000; // 502 | 11'h1c6: data = 8'b11000000; // ** 503 | 11'h1c7: data = 8'b11000000; // ** 504 | 11'h1c8: data = 8'b11000000; // ** 505 | 11'h1c9: data = 8'b11111110; // ******* 506 | 11'h1ca: data = 8'b00000000; // 507 | 11'h1cb: data = 8'b00000000; // 508 | 11'h1cc: data = 8'b00000000; // 509 | 11'h1cd: data = 8'b00000000; // 510 | 11'h1ce: data = 8'b00000000; // 511 | 11'h1cf: data = 8'b00000000; // 512 | //code x1d 513 | 11'h1d0: data = 8'b00000000; // 514 | 11'h1d1: data = 8'b00000000; // 515 | 11'h1d2: data = 8'b00000000; // 516 | 11'h1d3: data = 8'b00000000; // 517 | 11'h1d4: data = 8'b00000000; // 518 | 11'h1d5: data = 8'b00100100; // * * 519 | 11'h1d6: data = 8'b01100110; // ** ** 520 | 11'h1d7: data = 8'b11111111; // ******** 521 | 11'h1d8: data = 8'b01100110; // ** ** 522 | 11'h1d9: data = 8'b00100100; // * * 523 | 11'h1da: data = 8'b00000000; // 524 | 11'h1db: data = 8'b00000000; // 525 | 11'h1dc: data = 8'b00000000; // 526 | 11'h1dd: data = 8'b00000000; // 527 | 11'h1de: data = 8'b00000000; // 528 | 11'h1df: data = 8'b00000000; // 529 | //code x1e 530 | 11'h1e0: data = 8'b00000000; // 531 | 11'h1e1: data = 8'b00000000; // 532 | 11'h1e2: data = 8'b00000000; // 533 | 11'h1e3: data = 8'b00000000; // 534 | 11'h1e4: data = 8'b00010000; // * 535 | 11'h1e5: data = 8'b00111000; // *** 536 | 11'h1e6: data = 8'b00111000; // *** 537 | 11'h1e7: data = 8'b01111100; // ***** 538 | 11'h1e8: data = 8'b01111100; // ***** 539 | 11'h1e9: data = 8'b11111110; // ******* 540 | 11'h1ea: data = 8'b11111110; // ******* 541 | 11'h1eb: data = 8'b00000000; // 542 | 11'h1ec: data = 8'b00000000; // 543 | 11'h1ed: data = 8'b00000000; // 544 | 11'h1ee: data = 8'b00000000; // 545 | 11'h1ef: data = 8'b00000000; // 546 | //code x1f 547 | 11'h1f0: data = 8'b00000000; // 548 | 11'h1f1: data = 8'b00000000; // 549 | 11'h1f2: data = 8'b00000000; // 550 | 11'h1f3: data = 8'b00000000; // 551 | 11'h1f4: data = 8'b11111110; // ******* 552 | 11'h1f5: data = 8'b11111110; // ******* 553 | 11'h1f6: data = 8'b01111100; // ***** 554 | 11'h1f7: data = 8'b01111100; // ***** 555 | 11'h1f8: data = 8'b00111000; // *** 556 | 11'h1f9: data = 8'b00111000; // *** 557 | 11'h1fa: data = 8'b00010000; // * 558 | 11'h1fb: data = 8'b00000000; // 559 | 11'h1fc: data = 8'b00000000; // 560 | 11'h1fd: data = 8'b00000000; // 561 | 11'h1fe: data = 8'b00000000; // 562 | 11'h1ff: data = 8'b00000000; // 563 | //code x20 564 | 11'h200: data = 8'b00000000; // 565 | 11'h201: data = 8'b00000000; // 566 | 11'h202: data = 8'b00000000; // 567 | 11'h203: data = 8'b00000000; // 568 | 11'h204: data = 8'b00000000; // 569 | 11'h205: data = 8'b00000000; // 570 | 11'h206: data = 8'b00000000; // 571 | 11'h207: data = 8'b00000000; // 572 | 11'h208: data = 8'b00000000; // 573 | 11'h209: data = 8'b00000000; // 574 | 11'h20a: data = 8'b00000000; // 575 | 11'h20b: data = 8'b00000000; // 576 | 11'h20c: data = 8'b00000000; // 577 | 11'h20d: data = 8'b00000000; // 578 | 11'h20e: data = 8'b00000000; // 579 | 11'h20f: data = 8'b00000000; // 580 | //code x21 581 | 11'h210: data = 8'b00000000; // 582 | 11'h211: data = 8'b00000000; // 583 | 11'h212: data = 8'b00011000; // ** 584 | 11'h213: data = 8'b00111100; // **** 585 | 11'h214: data = 8'b00111100; // **** 586 | 11'h215: data = 8'b00111100; // **** 587 | 11'h216: data = 8'b00011000; // ** 588 | 11'h217: data = 8'b00011000; // ** 589 | 11'h218: data = 8'b00011000; // ** 590 | 11'h219: data = 8'b00000000; // 591 | 11'h21a: data = 8'b00011000; // ** 592 | 11'h21b: data = 8'b00011000; // ** 593 | 11'h21c: data = 8'b00000000; // 594 | 11'h21d: data = 8'b00000000; // 595 | 11'h21e: data = 8'b00000000; // 596 | 11'h21f: data = 8'b00000000; // 597 | //code x22 598 | 11'h220: data = 8'b00000000; // 599 | 11'h221: data = 8'b01100110; // ** ** 600 | 11'h222: data = 8'b01100110; // ** ** 601 | 11'h223: data = 8'b01100110; // ** ** 602 | 11'h224: data = 8'b00100100; // * * 603 | 11'h225: data = 8'b00000000; // 604 | 11'h226: data = 8'b00000000; // 605 | 11'h227: data = 8'b00000000; // 606 | 11'h228: data = 8'b00000000; // 607 | 11'h229: data = 8'b00000000; // 608 | 11'h22a: data = 8'b00000000; // 609 | 11'h22b: data = 8'b00000000; // 610 | 11'h22c: data = 8'b00000000; // 611 | 11'h22d: data = 8'b00000000; // 612 | 11'h22e: data = 8'b00000000; // 613 | 11'h22f: data = 8'b00000000; // 614 | //code x23 615 | 11'h230: data = 8'b00000000; // 616 | 11'h231: data = 8'b00000000; // 617 | 11'h232: data = 8'b00000000; // 618 | 11'h233: data = 8'b01101100; // ** ** 619 | 11'h234: data = 8'b01101100; // ** ** 620 | 11'h235: data = 8'b11111110; // ******* 621 | 11'h236: data = 8'b01101100; // ** ** 622 | 11'h237: data = 8'b01101100; // ** ** 623 | 11'h238: data = 8'b01101100; // ** ** 624 | 11'h239: data = 8'b11111110; // ******* 625 | 11'h23a: data = 8'b01101100; // ** ** 626 | 11'h23b: data = 8'b01101100; // ** ** 627 | 11'h23c: data = 8'b00000000; // 628 | 11'h23d: data = 8'b00000000; // 629 | 11'h23e: data = 8'b00000000; // 630 | 11'h23f: data = 8'b00000000; // 631 | //code x24 632 | 11'h240: data = 8'b00011000; // ** 633 | 11'h241: data = 8'b00011000; // ** 634 | 11'h242: data = 8'b01111100; // ***** 635 | 11'h243: data = 8'b11000110; // ** ** 636 | 11'h244: data = 8'b11000010; // ** * 637 | 11'h245: data = 8'b11000000; // ** 638 | 11'h246: data = 8'b01111100; // ***** 639 | 11'h247: data = 8'b00000110; // ** 640 | 11'h248: data = 8'b00000110; // ** 641 | 11'h249: data = 8'b10000110; // * ** 642 | 11'h24a: data = 8'b11000110; // ** ** 643 | 11'h24b: data = 8'b01111100; // ***** 644 | 11'h24c: data = 8'b00011000; // ** 645 | 11'h24d: data = 8'b00011000; // ** 646 | 11'h24e: data = 8'b00000000; // 647 | 11'h24f: data = 8'b00000000; // 648 | //code x25 649 | 11'h250: data = 8'b00000000; // 650 | 11'h251: data = 8'b00000000; // 651 | 11'h252: data = 8'b00000000; // 652 | 11'h253: data = 8'b00000000; // 653 | 11'h254: data = 8'b11000010; // ** * 654 | 11'h255: data = 8'b11000110; // ** ** 655 | 11'h256: data = 8'b00001100; // ** 656 | 11'h257: data = 8'b00011000; // ** 657 | 11'h258: data = 8'b00110000; // ** 658 | 11'h259: data = 8'b01100000; // ** 659 | 11'h25a: data = 8'b11000110; // ** ** 660 | 11'h25b: data = 8'b10000110; // * ** 661 | 11'h25c: data = 8'b00000000; // 662 | 11'h25d: data = 8'b00000000; // 663 | 11'h25e: data = 8'b00000000; // 664 | 11'h25f: data = 8'b00000000; // 665 | //code x26 666 | 11'h260: data = 8'b00000000; // 667 | 11'h261: data = 8'b00000000; // 668 | 11'h262: data = 8'b00111000; // *** 669 | 11'h263: data = 8'b01101100; // ** ** 670 | 11'h264: data = 8'b01101100; // ** ** 671 | 11'h265: data = 8'b00111000; // *** 672 | 11'h266: data = 8'b01110110; // *** ** 673 | 11'h267: data = 8'b11011100; // ** *** 674 | 11'h268: data = 8'b11001100; // ** ** 675 | 11'h269: data = 8'b11001100; // ** ** 676 | 11'h26a: data = 8'b11001100; // ** ** 677 | 11'h26b: data = 8'b01110110; // *** ** 678 | 11'h26c: data = 8'b00000000; // 679 | 11'h26d: data = 8'b00000000; // 680 | 11'h26e: data = 8'b00000000; // 681 | 11'h26f: data = 8'b00000000; // 682 | //code x27 683 | 11'h270: data = 8'b00000000; // 684 | 11'h271: data = 8'b00110000; // ** 685 | 11'h272: data = 8'b00110000; // ** 686 | 11'h273: data = 8'b00110000; // ** 687 | 11'h274: data = 8'b01100000; // ** 688 | 11'h275: data = 8'b00000000; // 689 | 11'h276: data = 8'b00000000; // 690 | 11'h277: data = 8'b00000000; // 691 | 11'h278: data = 8'b00000000; // 692 | 11'h279: data = 8'b00000000; // 693 | 11'h27a: data = 8'b00000000; // 694 | 11'h27b: data = 8'b00000000; // 695 | 11'h27c: data = 8'b00000000; // 696 | 11'h27d: data = 8'b00000000; // 697 | 11'h27e: data = 8'b00000000; // 698 | 11'h27f: data = 8'b00000000; // 699 | //code x28 700 | 11'h280: data = 8'b00000000; // 701 | 11'h281: data = 8'b00000000; // 702 | 11'h282: data = 8'b00001100; // ** 703 | 11'h283: data = 8'b00011000; // ** 704 | 11'h284: data = 8'b00110000; // ** 705 | 11'h285: data = 8'b00110000; // ** 706 | 11'h286: data = 8'b00110000; // ** 707 | 11'h287: data = 8'b00110000; // ** 708 | 11'h288: data = 8'b00110000; // ** 709 | 11'h289: data = 8'b00110000; // ** 710 | 11'h28a: data = 8'b00011000; // ** 711 | 11'h28b: data = 8'b00001100; // ** 712 | 11'h28c: data = 8'b00000000; // 713 | 11'h28d: data = 8'b00000000; // 714 | 11'h28e: data = 8'b00000000; // 715 | 11'h28f: data = 8'b00000000; // 716 | //code x29 717 | 11'h290: data = 8'b00000000; // 718 | 11'h291: data = 8'b00000000; // 719 | 11'h292: data = 8'b00110000; // ** 720 | 11'h293: data = 8'b00011000; // ** 721 | 11'h294: data = 8'b00001100; // ** 722 | 11'h295: data = 8'b00001100; // ** 723 | 11'h296: data = 8'b00001100; // ** 724 | 11'h297: data = 8'b00001100; // ** 725 | 11'h298: data = 8'b00001100; // ** 726 | 11'h299: data = 8'b00001100; // ** 727 | 11'h29a: data = 8'b00011000; // ** 728 | 11'h29b: data = 8'b00110000; // ** 729 | 11'h29c: data = 8'b00000000; // 730 | 11'h29d: data = 8'b00000000; // 731 | 11'h29e: data = 8'b00000000; // 732 | 11'h29f: data = 8'b00000000; // 733 | //code x2a 734 | 11'h2a0: data = 8'b00000000; // 735 | 11'h2a1: data = 8'b00000000; // 736 | 11'h2a2: data = 8'b00000000; // 737 | 11'h2a3: data = 8'b00000000; // 738 | 11'h2a4: data = 8'b00000000; // 739 | 11'h2a5: data = 8'b01100110; // ** ** 740 | 11'h2a6: data = 8'b00111100; // **** 741 | 11'h2a7: data = 8'b11111111; // ******** 742 | 11'h2a8: data = 8'b00111100; // **** 743 | 11'h2a9: data = 8'b01100110; // ** ** 744 | 11'h2aa: data = 8'b00000000; // 745 | 11'h2ab: data = 8'b00000000; // 746 | 11'h2ac: data = 8'b00000000; // 747 | 11'h2ad: data = 8'b00000000; // 748 | 11'h2ae: data = 8'b00000000; // 749 | 11'h2af: data = 8'b00000000; // 750 | //code x2b 751 | 11'h2b0: data = 8'b00000000; // 752 | 11'h2b1: data = 8'b00000000; // 753 | 11'h2b2: data = 8'b00000000; // 754 | 11'h2b3: data = 8'b00000000; // 755 | 11'h2b4: data = 8'b00000000; // 756 | 11'h2b5: data = 8'b00011000; // ** 757 | 11'h2b6: data = 8'b00011000; // ** 758 | 11'h2b7: data = 8'b01111110; // ****** 759 | 11'h2b8: data = 8'b00011000; // ** 760 | 11'h2b9: data = 8'b00011000; // ** 761 | 11'h2ba: data = 8'b00000000; // 762 | 11'h2bb: data = 8'b00000000; // 763 | 11'h2bc: data = 8'b00000000; // 764 | 11'h2bd: data = 8'b00000000; // 765 | 11'h2be: data = 8'b00000000; // 766 | 11'h2bf: data = 8'b00000000; // 767 | //code x2c 768 | 11'h2c0: data = 8'b00000000; // 769 | 11'h2c1: data = 8'b00000000; // 770 | 11'h2c2: data = 8'b00000000; // 771 | 11'h2c3: data = 8'b00000000; // 772 | 11'h2c4: data = 8'b00000000; // 773 | 11'h2c5: data = 8'b00000000; // 774 | 11'h2c6: data = 8'b00000000; // 775 | 11'h2c7: data = 8'b00000000; // 776 | 11'h2c8: data = 8'b00000000; // 777 | 11'h2c9: data = 8'b00011000; // ** 778 | 11'h2ca: data = 8'b00011000; // ** 779 | 11'h2cb: data = 8'b00011000; // ** 780 | 11'h2cc: data = 8'b00110000; // ** 781 | 11'h2cd: data = 8'b00000000; // 782 | 11'h2ce: data = 8'b00000000; // 783 | 11'h2cf: data = 8'b00000000; // 784 | //code x2d 785 | 11'h2d0: data = 8'b00000000; // 786 | 11'h2d1: data = 8'b00000000; // 787 | 11'h2d2: data = 8'b00000000; // 788 | 11'h2d3: data = 8'b00000000; // 789 | 11'h2d4: data = 8'b00000000; // 790 | 11'h2d5: data = 8'b00000000; // 791 | 11'h2d6: data = 8'b00000000; // 792 | 11'h2d7: data = 8'b01111110; // ****** 793 | 11'h2d8: data = 8'b00000000; // 794 | 11'h2d9: data = 8'b00000000; // 795 | 11'h2da: data = 8'b00000000; // 796 | 11'h2db: data = 8'b00000000; // 797 | 11'h2dc: data = 8'b00000000; // 798 | 11'h2dd: data = 8'b00000000; // 799 | 11'h2de: data = 8'b00000000; // 800 | 11'h2df: data = 8'b00000000; // 801 | //code x2e 802 | 11'h2e0: data = 8'b00000000; // 803 | 11'h2e1: data = 8'b00000000; // 804 | 11'h2e2: data = 8'b00000000; // 805 | 11'h2e3: data = 8'b00000000; // 806 | 11'h2e4: data = 8'b00000000; // 807 | 11'h2e5: data = 8'b00000000; // 808 | 11'h2e6: data = 8'b00000000; // 809 | 11'h2e7: data = 8'b00000000; // 810 | 11'h2e8: data = 8'b00000000; // 811 | 11'h2e9: data = 8'b00000000; // 812 | 11'h2ea: data = 8'b00011000; // ** 813 | 11'h2eb: data = 8'b00011000; // ** 814 | 11'h2ec: data = 8'b00000000; // 815 | 11'h2ed: data = 8'b00000000; // 816 | 11'h2ee: data = 8'b00000000; // 817 | 11'h2ef: data = 8'b00000000; // 818 | //code x2f 819 | 11'h2f0: data = 8'b00000000; // 820 | 11'h2f1: data = 8'b00000000; // 821 | 11'h2f2: data = 8'b00000000; // 822 | 11'h2f3: data = 8'b00000000; // 823 | 11'h2f4: data = 8'b00000010; // * 824 | 11'h2f5: data = 8'b00000110; // ** 825 | 11'h2f6: data = 8'b00001100; // ** 826 | 11'h2f7: data = 8'b00011000; // ** 827 | 11'h2f8: data = 8'b00110000; // ** 828 | 11'h2f9: data = 8'b01100000; // ** 829 | 11'h2fa: data = 8'b11000000; // ** 830 | 11'h2fb: data = 8'b10000000; // * 831 | 11'h2fc: data = 8'b00000000; // 832 | 11'h2fd: data = 8'b00000000; // 833 | 11'h2fe: data = 8'b00000000; // 834 | 11'h2ff: data = 8'b00000000; // 835 | //code x30 836 | 11'h300: data = 8'b00000000; // 837 | 11'h301: data = 8'b00000000; // 838 | 11'h302: data = 8'b01111100; // ***** 839 | 11'h303: data = 8'b11000110; // ** ** 840 | 11'h304: data = 8'b11000110; // ** ** 841 | 11'h305: data = 8'b11001110; // ** *** 842 | 11'h306: data = 8'b11011110; // ** **** 843 | 11'h307: data = 8'b11110110; // **** ** 844 | 11'h308: data = 8'b11100110; // *** ** 845 | 11'h309: data = 8'b11000110; // ** ** 846 | 11'h30a: data = 8'b11000110; // ** ** 847 | 11'h30b: data = 8'b01111100; // ***** 848 | 11'h30c: data = 8'b00000000; // 849 | 11'h30d: data = 8'b00000000; // 850 | 11'h30e: data = 8'b00000000; // 851 | 11'h30f: data = 8'b00000000; // 852 | //code x31 853 | 11'h310: data = 8'b00000000; // 854 | 11'h311: data = 8'b00000000; // 855 | 11'h312: data = 8'b00011000; // 856 | 11'h313: data = 8'b00111000; // 857 | 11'h314: data = 8'b01111000; // ** 858 | 11'h315: data = 8'b00011000; // *** 859 | 11'h316: data = 8'b00011000; // **** 860 | 11'h317: data = 8'b00011000; // ** 861 | 11'h318: data = 8'b00011000; // ** 862 | 11'h319: data = 8'b00011000; // ** 863 | 11'h31a: data = 8'b00011000; // ** 864 | 11'h31b: data = 8'b01111110; // ** 865 | 11'h31c: data = 8'b00000000; // ** 866 | 11'h31d: data = 8'b00000000; // ****** 867 | 11'h31e: data = 8'b00000000; // 868 | 11'h31f: data = 8'b00000000; // 869 | //code x32 870 | 11'h320: data = 8'b00000000; // 871 | 11'h321: data = 8'b00000000; // 872 | 11'h322: data = 8'b01111100; // ***** 873 | 11'h323: data = 8'b11000110; // ** ** 874 | 11'h324: data = 8'b00000110; // ** 875 | 11'h325: data = 8'b00001100; // ** 876 | 11'h326: data = 8'b00011000; // ** 877 | 11'h327: data = 8'b00110000; // ** 878 | 11'h328: data = 8'b01100000; // ** 879 | 11'h329: data = 8'b11000000; // ** 880 | 11'h32a: data = 8'b11000110; // ** ** 881 | 11'h32b: data = 8'b11111110; // ******* 882 | 11'h32c: data = 8'b00000000; // 883 | 11'h32d: data = 8'b00000000; // 884 | 11'h32e: data = 8'b00000000; // 885 | 11'h32f: data = 8'b00000000; // 886 | //code x33 887 | 11'h330: data = 8'b00000000; // 888 | 11'h331: data = 8'b00000000; // 889 | 11'h332: data = 8'b01111100; // ***** 890 | 11'h333: data = 8'b11000110; // ** ** 891 | 11'h334: data = 8'b00000110; // ** 892 | 11'h335: data = 8'b00000110; // ** 893 | 11'h336: data = 8'b00111100; // **** 894 | 11'h337: data = 8'b00000110; // ** 895 | 11'h338: data = 8'b00000110; // ** 896 | 11'h339: data = 8'b00000110; // ** 897 | 11'h33a: data = 8'b11000110; // ** ** 898 | 11'h33b: data = 8'b01111100; // ***** 899 | 11'h33c: data = 8'b00000000; // 900 | 11'h33d: data = 8'b00000000; // 901 | 11'h33e: data = 8'b00000000; // 902 | 11'h33f: data = 8'b00000000; // 903 | //code x34 904 | 11'h340: data = 8'b00000000; // 905 | 11'h341: data = 8'b00000000; // 906 | 11'h342: data = 8'b00001100; // ** 907 | 11'h343: data = 8'b00011100; // *** 908 | 11'h344: data = 8'b00111100; // **** 909 | 11'h345: data = 8'b01101100; // ** ** 910 | 11'h346: data = 8'b11001100; // ** ** 911 | 11'h347: data = 8'b11111110; // ******* 912 | 11'h348: data = 8'b00001100; // ** 913 | 11'h349: data = 8'b00001100; // ** 914 | 11'h34a: data = 8'b00001100; // ** 915 | 11'h34b: data = 8'b00011110; // **** 916 | 11'h34c: data = 8'b00000000; // 917 | 11'h34d: data = 8'b00000000; // 918 | 11'h34e: data = 8'b00000000; // 919 | 11'h34f: data = 8'b00000000; // 920 | //code x35 921 | 11'h350: data = 8'b00000000; // 922 | 11'h351: data = 8'b00000000; // 923 | 11'h352: data = 8'b11111110; // ******* 924 | 11'h353: data = 8'b11000000; // ** 925 | 11'h354: data = 8'b11000000; // ** 926 | 11'h355: data = 8'b11000000; // ** 927 | 11'h356: data = 8'b11111100; // ****** 928 | 11'h357: data = 8'b00000110; // ** 929 | 11'h358: data = 8'b00000110; // ** 930 | 11'h359: data = 8'b00000110; // ** 931 | 11'h35a: data = 8'b11000110; // ** ** 932 | 11'h35b: data = 8'b01111100; // ***** 933 | 11'h35c: data = 8'b00000000; // 934 | 11'h35d: data = 8'b00000000; // 935 | 11'h35e: data = 8'b00000000; // 936 | 11'h35f: data = 8'b00000000; // 937 | //code x36 938 | 11'h360: data = 8'b00000000; // 939 | 11'h361: data = 8'b00000000; // 940 | 11'h362: data = 8'b00111000; // *** 941 | 11'h363: data = 8'b01100000; // ** 942 | 11'h364: data = 8'b11000000; // ** 943 | 11'h365: data = 8'b11000000; // ** 944 | 11'h366: data = 8'b11111100; // ****** 945 | 11'h367: data = 8'b11000110; // ** ** 946 | 11'h368: data = 8'b11000110; // ** ** 947 | 11'h369: data = 8'b11000110; // ** ** 948 | 11'h36a: data = 8'b11000110; // ** ** 949 | 11'h36b: data = 8'b01111100; // ***** 950 | 11'h36c: data = 8'b00000000; // 951 | 11'h36d: data = 8'b00000000; // 952 | 11'h36e: data = 8'b00000000; // 953 | 11'h36f: data = 8'b00000000; // 954 | //code x37 955 | 11'h370: data = 8'b00000000; // 956 | 11'h371: data = 8'b00000000; // 957 | 11'h372: data = 8'b11111110; // ******* 958 | 11'h373: data = 8'b11000110; // ** ** 959 | 11'h374: data = 8'b00000110; // ** 960 | 11'h375: data = 8'b00000110; // ** 961 | 11'h376: data = 8'b00001100; // ** 962 | 11'h377: data = 8'b00011000; // ** 963 | 11'h378: data = 8'b00110000; // ** 964 | 11'h379: data = 8'b00110000; // ** 965 | 11'h37a: data = 8'b00110000; // ** 966 | 11'h37b: data = 8'b00110000; // ** 967 | 11'h37c: data = 8'b00000000; // 968 | 11'h37d: data = 8'b00000000; // 969 | 11'h37e: data = 8'b00000000; // 970 | 11'h37f: data = 8'b00000000; // 971 | //code x38 972 | 11'h380: data = 8'b00000000; // 973 | 11'h381: data = 8'b00000000; // 974 | 11'h382: data = 8'b01111100; // ***** 975 | 11'h383: data = 8'b11000110; // ** ** 976 | 11'h384: data = 8'b11000110; // ** ** 977 | 11'h385: data = 8'b11000110; // ** ** 978 | 11'h386: data = 8'b01111100; // ***** 979 | 11'h387: data = 8'b11000110; // ** ** 980 | 11'h388: data = 8'b11000110; // ** ** 981 | 11'h389: data = 8'b11000110; // ** ** 982 | 11'h38a: data = 8'b11000110; // ** ** 983 | 11'h38b: data = 8'b01111100; // ***** 984 | 11'h38c: data = 8'b00000000; // 985 | 11'h38d: data = 8'b00000000; // 986 | 11'h38e: data = 8'b00000000; // 987 | 11'h38f: data = 8'b00000000; // 988 | //code x39 989 | 11'h390: data = 8'b00000000; // 990 | 11'h391: data = 8'b00000000; // 991 | 11'h392: data = 8'b01111100; // ***** 992 | 11'h393: data = 8'b11000110; // ** ** 993 | 11'h394: data = 8'b11000110; // ** ** 994 | 11'h395: data = 8'b11000110; // ** ** 995 | 11'h396: data = 8'b01111110; // ****** 996 | 11'h397: data = 8'b00000110; // ** 997 | 11'h398: data = 8'b00000110; // ** 998 | 11'h399: data = 8'b00000110; // ** 999 | 11'h39a: data = 8'b00001100; // ** 1000 | 11'h39b: data = 8'b01111000; // **** 1001 | 11'h39c: data = 8'b00000000; // 1002 | 11'h39d: data = 8'b00000000; // 1003 | 11'h39e: data = 8'b00000000; // 1004 | 11'h39f: data = 8'b00000000; // 1005 | //code x3a 1006 | 11'h3a0: data = 8'b00000000; // 1007 | 11'h3a1: data = 8'b00000000; // 1008 | 11'h3a2: data = 8'b00000000; // 1009 | 11'h3a3: data = 8'b00000000; // 1010 | 11'h3a4: data = 8'b00011000; // ** 1011 | 11'h3a5: data = 8'b00011000; // ** 1012 | 11'h3a6: data = 8'b00000000; // 1013 | 11'h3a7: data = 8'b00000000; // 1014 | 11'h3a8: data = 8'b00000000; // 1015 | 11'h3a9: data = 8'b00011000; // ** 1016 | 11'h3aa: data = 8'b00011000; // ** 1017 | 11'h3ab: data = 8'b00000000; // 1018 | 11'h3ac: data = 8'b00000000; // 1019 | 11'h3ad: data = 8'b00000000; // 1020 | 11'h3ae: data = 8'b00000000; // 1021 | 11'h3af: data = 8'b00000000; // 1022 | //code x3b 1023 | 11'h3b0: data = 8'b00000000; // 1024 | 11'h3b1: data = 8'b00000000; // 1025 | 11'h3b2: data = 8'b00000000; // 1026 | 11'h3b3: data = 8'b00000000; // 1027 | 11'h3b4: data = 8'b00011000; // ** 1028 | 11'h3b5: data = 8'b00011000; // ** 1029 | 11'h3b6: data = 8'b00000000; // 1030 | 11'h3b7: data = 8'b00000000; // 1031 | 11'h3b8: data = 8'b00000000; // 1032 | 11'h3b9: data = 8'b00011000; // ** 1033 | 11'h3ba: data = 8'b00011000; // ** 1034 | 11'h3bb: data = 8'b00110000; // ** 1035 | 11'h3bc: data = 8'b00000000; // 1036 | 11'h3bd: data = 8'b00000000; // 1037 | 11'h3be: data = 8'b00000000; // 1038 | 11'h3bf: data = 8'b00000000; // 1039 | //code x3c 1040 | 11'h3c0: data = 8'b00000000; // 1041 | 11'h3c1: data = 8'b00000000; // 1042 | 11'h3c2: data = 8'b00000000; // 1043 | 11'h3c3: data = 8'b00000110; // ** 1044 | 11'h3c4: data = 8'b00001100; // ** 1045 | 11'h3c5: data = 8'b00011000; // ** 1046 | 11'h3c6: data = 8'b00110000; // ** 1047 | 11'h3c7: data = 8'b01100000; // ** 1048 | 11'h3c8: data = 8'b00110000; // ** 1049 | 11'h3c9: data = 8'b00011000; // ** 1050 | 11'h3ca: data = 8'b00001100; // ** 1051 | 11'h3cb: data = 8'b00000110; // ** 1052 | 11'h3cc: data = 8'b00000000; // 1053 | 11'h3cd: data = 8'b00000000; // 1054 | 11'h3ce: data = 8'b00000000; // 1055 | 11'h3cf: data = 8'b00000000; // 1056 | //code x3d 1057 | 11'h3d0: data = 8'b00000000; // 1058 | 11'h3d1: data = 8'b00000000; // 1059 | 11'h3d2: data = 8'b00000000; // 1060 | 11'h3d3: data = 8'b00000000; // 1061 | 11'h3d4: data = 8'b00000000; // 1062 | 11'h3d5: data = 8'b01111110; // ****** 1063 | 11'h3d6: data = 8'b00000000; // 1064 | 11'h3d7: data = 8'b00000000; // 1065 | 11'h3d8: data = 8'b01111110; // ****** 1066 | 11'h3d9: data = 8'b00000000; // 1067 | 11'h3da: data = 8'b00000000; // 1068 | 11'h3db: data = 8'b00000000; // 1069 | 11'h3dc: data = 8'b00000000; // 1070 | 11'h3dd: data = 8'b00000000; // 1071 | 11'h3de: data = 8'b00000000; // 1072 | 11'h3df: data = 8'b00000000; // 1073 | //code x3e 1074 | 11'h3e0: data = 8'b00000000; // 1075 | 11'h3e1: data = 8'b00000000; // 1076 | 11'h3e2: data = 8'b00000000; // 1077 | 11'h3e3: data = 8'b01100000; // ** 1078 | 11'h3e4: data = 8'b00110000; // ** 1079 | 11'h3e5: data = 8'b00011000; // ** 1080 | 11'h3e6: data = 8'b00001100; // ** 1081 | 11'h3e7: data = 8'b00000110; // ** 1082 | 11'h3e8: data = 8'b00001100; // ** 1083 | 11'h3e9: data = 8'b00011000; // ** 1084 | 11'h3ea: data = 8'b00110000; // ** 1085 | 11'h3eb: data = 8'b01100000; // ** 1086 | 11'h3ec: data = 8'b00000000; // 1087 | 11'h3ed: data = 8'b00000000; // 1088 | 11'h3ee: data = 8'b00000000; // 1089 | 11'h3ef: data = 8'b00000000; // 1090 | //code x3f 1091 | 11'h3f0: data = 8'b00000000; // 1092 | 11'h3f1: data = 8'b00000000; // 1093 | 11'h3f2: data = 8'b01111100; // ***** 1094 | 11'h3f3: data = 8'b11000110; // ** ** 1095 | 11'h3f4: data = 8'b11000110; // ** ** 1096 | 11'h3f5: data = 8'b00001100; // ** 1097 | 11'h3f6: data = 8'b00011000; // ** 1098 | 11'h3f7: data = 8'b00011000; // ** 1099 | 11'h3f8: data = 8'b00011000; // ** 1100 | 11'h3f9: data = 8'b00000000; // 1101 | 11'h3fa: data = 8'b00011000; // ** 1102 | 11'h3fb: data = 8'b00011000; // ** 1103 | 11'h3fc: data = 8'b00000000; // 1104 | 11'h3fd: data = 8'b00000000; // 1105 | 11'h3fe: data = 8'b00000000; // 1106 | 11'h3ff: data = 8'b00000000; // 1107 | //code x40 1108 | 11'h400: data = 8'b00000000; // 1109 | 11'h401: data = 8'b00000000; // 1110 | 11'h402: data = 8'b01111100; // ***** 1111 | 11'h403: data = 8'b11000110; // ** ** 1112 | 11'h404: data = 8'b11000110; // ** ** 1113 | 11'h405: data = 8'b11000110; // ** ** 1114 | 11'h406: data = 8'b11011110; // ** **** 1115 | 11'h407: data = 8'b11011110; // ** **** 1116 | 11'h408: data = 8'b11011110; // ** **** 1117 | 11'h409: data = 8'b11011100; // ** *** 1118 | 11'h40a: data = 8'b11000000; // ** 1119 | 11'h40b: data = 8'b01111100; // ***** 1120 | 11'h40c: data = 8'b00000000; // 1121 | 11'h40d: data = 8'b00000000; // 1122 | 11'h40e: data = 8'b00000000; // 1123 | 11'h40f: data = 8'b00000000; // 1124 | //code x41 1125 | 11'h410: data = 8'b00000000; // 1126 | 11'h411: data = 8'b00000000; // 1127 | 11'h412: data = 8'b00010000; // * 1128 | 11'h413: data = 8'b00111000; // *** 1129 | 11'h414: data = 8'b01101100; // ** ** 1130 | 11'h415: data = 8'b11000110; // ** ** 1131 | 11'h416: data = 8'b11000110; // ** ** 1132 | 11'h417: data = 8'b11111110; // ******* 1133 | 11'h418: data = 8'b11000110; // ** ** 1134 | 11'h419: data = 8'b11000110; // ** ** 1135 | 11'h41a: data = 8'b11000110; // ** ** 1136 | 11'h41b: data = 8'b11000110; // ** ** 1137 | 11'h41c: data = 8'b00000000; // 1138 | 11'h41d: data = 8'b00000000; // 1139 | 11'h41e: data = 8'b00000000; // 1140 | 11'h41f: data = 8'b00000000; // 1141 | //code x42 1142 | 11'h420: data = 8'b00000000; // 1143 | 11'h421: data = 8'b00000000; // 1144 | 11'h422: data = 8'b11111100; // ****** 1145 | 11'h423: data = 8'b01100110; // ** ** 1146 | 11'h424: data = 8'b01100110; // ** ** 1147 | 11'h425: data = 8'b01100110; // ** ** 1148 | 11'h426: data = 8'b01111100; // ***** 1149 | 11'h427: data = 8'b01100110; // ** ** 1150 | 11'h428: data = 8'b01100110; // ** ** 1151 | 11'h429: data = 8'b01100110; // ** ** 1152 | 11'h42a: data = 8'b01100110; // ** ** 1153 | 11'h42b: data = 8'b11111100; // ****** 1154 | 11'h42c: data = 8'b00000000; // 1155 | 11'h42d: data = 8'b00000000; // 1156 | 11'h42e: data = 8'b00000000; // 1157 | 11'h42f: data = 8'b00000000; // 1158 | //code x43 1159 | 11'h430: data = 8'b00000000; // 1160 | 11'h431: data = 8'b00000000; // 1161 | 11'h432: data = 8'b00111100; // **** 1162 | 11'h433: data = 8'b01100110; // ** ** 1163 | 11'h434: data = 8'b11000010; // ** * 1164 | 11'h435: data = 8'b11000000; // ** 1165 | 11'h436: data = 8'b11000000; // ** 1166 | 11'h437: data = 8'b11000000; // ** 1167 | 11'h438: data = 8'b11000000; // ** 1168 | 11'h439: data = 8'b11000010; // ** * 1169 | 11'h43a: data = 8'b01100110; // ** ** 1170 | 11'h43b: data = 8'b00111100; // **** 1171 | 11'h43c: data = 8'b00000000; // 1172 | 11'h43d: data = 8'b00000000; // 1173 | 11'h43e: data = 8'b00000000; // 1174 | 11'h43f: data = 8'b00000000; // 1175 | //code x44 1176 | 11'h440: data = 8'b00000000; // 1177 | 11'h441: data = 8'b00000000; // 1178 | 11'h442: data = 8'b11111000; // ***** 1179 | 11'h443: data = 8'b01101100; // ** ** 1180 | 11'h444: data = 8'b01100110; // ** ** 1181 | 11'h445: data = 8'b01100110; // ** ** 1182 | 11'h446: data = 8'b01100110; // ** ** 1183 | 11'h447: data = 8'b01100110; // ** ** 1184 | 11'h448: data = 8'b01100110; // ** ** 1185 | 11'h449: data = 8'b01100110; // ** ** 1186 | 11'h44a: data = 8'b01101100; // ** ** 1187 | 11'h44b: data = 8'b11111000; // ***** 1188 | 11'h44c: data = 8'b00000000; // 1189 | 11'h44d: data = 8'b00000000; // 1190 | 11'h44e: data = 8'b00000000; // 1191 | 11'h44f: data = 8'b00000000; // 1192 | //code x45 1193 | 11'h450: data = 8'b00000000; // 1194 | 11'h451: data = 8'b00000000; // 1195 | 11'h452: data = 8'b11111110; // ******* 1196 | 11'h453: data = 8'b01100110; // ** ** 1197 | 11'h454: data = 8'b01100010; // ** * 1198 | 11'h455: data = 8'b01101000; // ** * 1199 | 11'h456: data = 8'b01111000; // **** 1200 | 11'h457: data = 8'b01101000; // ** * 1201 | 11'h458: data = 8'b01100000; // ** 1202 | 11'h459: data = 8'b01100010; // ** * 1203 | 11'h45a: data = 8'b01100110; // ** ** 1204 | 11'h45b: data = 8'b11111110; // ******* 1205 | 11'h45c: data = 8'b00000000; // 1206 | 11'h45d: data = 8'b00000000; // 1207 | 11'h45e: data = 8'b00000000; // 1208 | 11'h45f: data = 8'b00000000; // 1209 | //code x46 1210 | 11'h460: data = 8'b00000000; // 1211 | 11'h461: data = 8'b00000000; // 1212 | 11'h462: data = 8'b11111110; // ******* 1213 | 11'h463: data = 8'b01100110; // ** ** 1214 | 11'h464: data = 8'b01100010; // ** * 1215 | 11'h465: data = 8'b01101000; // ** * 1216 | 11'h466: data = 8'b01111000; // **** 1217 | 11'h467: data = 8'b01101000; // ** * 1218 | 11'h468: data = 8'b01100000; // ** 1219 | 11'h469: data = 8'b01100000; // ** 1220 | 11'h46a: data = 8'b01100000; // ** 1221 | 11'h46b: data = 8'b11110000; // **** 1222 | 11'h46c: data = 8'b00000000; // 1223 | 11'h46d: data = 8'b00000000; // 1224 | 11'h46e: data = 8'b00000000; // 1225 | 11'h46f: data = 8'b00000000; // 1226 | //code x47 1227 | 11'h470: data = 8'b00000000; // 1228 | 11'h471: data = 8'b00000000; // 1229 | 11'h472: data = 8'b00111100; // **** 1230 | 11'h473: data = 8'b01100110; // ** ** 1231 | 11'h474: data = 8'b11000010; // ** * 1232 | 11'h475: data = 8'b11000000; // ** 1233 | 11'h476: data = 8'b11000000; // ** 1234 | 11'h477: data = 8'b11011110; // ** **** 1235 | 11'h478: data = 8'b11000110; // ** ** 1236 | 11'h479: data = 8'b11000110; // ** ** 1237 | 11'h47a: data = 8'b01100110; // ** ** 1238 | 11'h47b: data = 8'b00111010; // *** * 1239 | 11'h47c: data = 8'b00000000; // 1240 | 11'h47d: data = 8'b00000000; // 1241 | 11'h47e: data = 8'b00000000; // 1242 | 11'h47f: data = 8'b00000000; // 1243 | //code x48 1244 | 11'h480: data = 8'b00000000; // 1245 | 11'h481: data = 8'b00000000; // 1246 | 11'h482: data = 8'b11000110; // ** ** 1247 | 11'h483: data = 8'b11000110; // ** ** 1248 | 11'h484: data = 8'b11000110; // ** ** 1249 | 11'h485: data = 8'b11000110; // ** ** 1250 | 11'h486: data = 8'b11111110; // ******* 1251 | 11'h487: data = 8'b11000110; // ** ** 1252 | 11'h488: data = 8'b11000110; // ** ** 1253 | 11'h489: data = 8'b11000110; // ** ** 1254 | 11'h48a: data = 8'b11000110; // ** ** 1255 | 11'h48b: data = 8'b11000110; // ** ** 1256 | 11'h48c: data = 8'b00000000; // 1257 | 11'h48d: data = 8'b00000000; // 1258 | 11'h48e: data = 8'b00000000; // 1259 | 11'h48f: data = 8'b00000000; // 1260 | //code x49 1261 | 11'h490: data = 8'b00000000; // 1262 | 11'h491: data = 8'b00000000; // 1263 | 11'h492: data = 8'b00111100; // **** 1264 | 11'h493: data = 8'b00011000; // ** 1265 | 11'h494: data = 8'b00011000; // ** 1266 | 11'h495: data = 8'b00011000; // ** 1267 | 11'h496: data = 8'b00011000; // ** 1268 | 11'h497: data = 8'b00011000; // ** 1269 | 11'h498: data = 8'b00011000; // ** 1270 | 11'h499: data = 8'b00011000; // ** 1271 | 11'h49a: data = 8'b00011000; // ** 1272 | 11'h49b: data = 8'b00111100; // **** 1273 | 11'h49c: data = 8'b00000000; // 1274 | 11'h49d: data = 8'b00000000; // 1275 | 11'h49e: data = 8'b00000000; // 1276 | 11'h49f: data = 8'b00000000; // 1277 | //code x4a 1278 | 11'h4a0: data = 8'b00000000; // 1279 | 11'h4a1: data = 8'b00000000; // 1280 | 11'h4a2: data = 8'b00011110; // **** 1281 | 11'h4a3: data = 8'b00001100; // ** 1282 | 11'h4a4: data = 8'b00001100; // ** 1283 | 11'h4a5: data = 8'b00001100; // ** 1284 | 11'h4a6: data = 8'b00001100; // ** 1285 | 11'h4a7: data = 8'b00001100; // ** 1286 | 11'h4a8: data = 8'b11001100; // ** ** 1287 | 11'h4a9: data = 8'b11001100; // ** ** 1288 | 11'h4aa: data = 8'b11001100; // ** ** 1289 | 11'h4ab: data = 8'b01111000; // **** 1290 | 11'h4ac: data = 8'b00000000; // 1291 | 11'h4ad: data = 8'b00000000; // 1292 | 11'h4ae: data = 8'b00000000; // 1293 | 11'h4af: data = 8'b00000000; // 1294 | //code x4b 1295 | 11'h4b0: data = 8'b00000000; // 1296 | 11'h4b1: data = 8'b00000000; // 1297 | 11'h4b2: data = 8'b11100110; // *** ** 1298 | 11'h4b3: data = 8'b01100110; // ** ** 1299 | 11'h4b4: data = 8'b01100110; // ** ** 1300 | 11'h4b5: data = 8'b01101100; // ** ** 1301 | 11'h4b6: data = 8'b01111000; // **** 1302 | 11'h4b7: data = 8'b01111000; // **** 1303 | 11'h4b8: data = 8'b01101100; // ** ** 1304 | 11'h4b9: data = 8'b01100110; // ** ** 1305 | 11'h4ba: data = 8'b01100110; // ** ** 1306 | 11'h4bb: data = 8'b11100110; // *** ** 1307 | 11'h4bc: data = 8'b00000000; // 1308 | 11'h4bd: data = 8'b00000000; // 1309 | 11'h4be: data = 8'b00000000; // 1310 | 11'h4bf: data = 8'b00000000; // 1311 | //code x4c 1312 | 11'h4c0: data = 8'b00000000; // 1313 | 11'h4c1: data = 8'b00000000; // 1314 | 11'h4c2: data = 8'b11110000; // **** 1315 | 11'h4c3: data = 8'b01100000; // ** 1316 | 11'h4c4: data = 8'b01100000; // ** 1317 | 11'h4c5: data = 8'b01100000; // ** 1318 | 11'h4c6: data = 8'b01100000; // ** 1319 | 11'h4c7: data = 8'b01100000; // ** 1320 | 11'h4c8: data = 8'b01100000; // ** 1321 | 11'h4c9: data = 8'b01100010; // ** * 1322 | 11'h4ca: data = 8'b01100110; // ** ** 1323 | 11'h4cb: data = 8'b11111110; // ******* 1324 | 11'h4cc: data = 8'b00000000; // 1325 | 11'h4cd: data = 8'b00000000; // 1326 | 11'h4ce: data = 8'b00000000; // 1327 | 11'h4cf: data = 8'b00000000; // 1328 | //code x4d 1329 | 11'h4d0: data = 8'b00000000; // 1330 | 11'h4d1: data = 8'b00000000; // 1331 | 11'h4d2: data = 8'b11000011; // ** ** 1332 | 11'h4d3: data = 8'b11100111; // *** *** 1333 | 11'h4d4: data = 8'b11111111; // ******** 1334 | 11'h4d5: data = 8'b11111111; // ******** 1335 | 11'h4d6: data = 8'b11011011; // ** ** ** 1336 | 11'h4d7: data = 8'b11000011; // ** ** 1337 | 11'h4d8: data = 8'b11000011; // ** ** 1338 | 11'h4d9: data = 8'b11000011; // ** ** 1339 | 11'h4da: data = 8'b11000011; // ** ** 1340 | 11'h4db: data = 8'b11000011; // ** ** 1341 | 11'h4dc: data = 8'b00000000; // 1342 | 11'h4dd: data = 8'b00000000; // 1343 | 11'h4de: data = 8'b00000000; // 1344 | 11'h4df: data = 8'b00000000; // 1345 | //code x4e 1346 | 11'h4e0: data = 8'b00000000; // 1347 | 11'h4e1: data = 8'b00000000; // 1348 | 11'h4e2: data = 8'b11000110; // ** ** 1349 | 11'h4e3: data = 8'b11100110; // *** ** 1350 | 11'h4e4: data = 8'b11110110; // **** ** 1351 | 11'h4e5: data = 8'b11111110; // ******* 1352 | 11'h4e6: data = 8'b11011110; // ** **** 1353 | 11'h4e7: data = 8'b11001110; // ** *** 1354 | 11'h4e8: data = 8'b11000110; // ** ** 1355 | 11'h4e9: data = 8'b11000110; // ** ** 1356 | 11'h4ea: data = 8'b11000110; // ** ** 1357 | 11'h4eb: data = 8'b11000110; // ** ** 1358 | 11'h4ec: data = 8'b00000000; // 1359 | 11'h4ed: data = 8'b00000000; // 1360 | 11'h4ee: data = 8'b00000000; // 1361 | 11'h4ef: data = 8'b00000000; // 1362 | //code x4f 1363 | 11'h4f0: data = 8'b00000000; // 1364 | 11'h4f1: data = 8'b00000000; // 1365 | 11'h4f2: data = 8'b01111100; // ***** 1366 | 11'h4f3: data = 8'b11000110; // ** ** 1367 | 11'h4f4: data = 8'b11000110; // ** ** 1368 | 11'h4f5: data = 8'b11000110; // ** ** 1369 | 11'h4f6: data = 8'b11000110; // ** ** 1370 | 11'h4f7: data = 8'b11000110; // ** ** 1371 | 11'h4f8: data = 8'b11000110; // ** ** 1372 | 11'h4f9: data = 8'b11000110; // ** ** 1373 | 11'h4fa: data = 8'b11000110; // ** ** 1374 | 11'h4fb: data = 8'b01111100; // ***** 1375 | 11'h4fc: data = 8'b00000000; // 1376 | 11'h4fd: data = 8'b00000000; // 1377 | 11'h4fe: data = 8'b00000000; // 1378 | 11'h4ff: data = 8'b00000000; // 1379 | //code x50 1380 | 11'h500: data = 8'b00000000; // 1381 | 11'h501: data = 8'b00000000; // 1382 | 11'h502: data = 8'b11111100; // ****** 1383 | 11'h503: data = 8'b01100110; // ** ** 1384 | 11'h504: data = 8'b01100110; // ** ** 1385 | 11'h505: data = 8'b01100110; // ** ** 1386 | 11'h506: data = 8'b01111100; // ***** 1387 | 11'h507: data = 8'b01100000; // ** 1388 | 11'h508: data = 8'b01100000; // ** 1389 | 11'h509: data = 8'b01100000; // ** 1390 | 11'h50a: data = 8'b01100000; // ** 1391 | 11'h50b: data = 8'b11110000; // **** 1392 | 11'h50c: data = 8'b00000000; // 1393 | 11'h50d: data = 8'b00000000; // 1394 | 11'h50e: data = 8'b00000000; // 1395 | 11'h50f: data = 8'b00000000; // 1396 | //code x510f 1397 | 11'h510: data = 8'b00000000; // 1398 | 11'h511: data = 8'b00000000; // 1399 | 11'h512: data = 8'b01111100; // ***** 1400 | 11'h513: data = 8'b11000110; // ** ** 1401 | 11'h514: data = 8'b11000110; // ** ** 1402 | 11'h515: data = 8'b11000110; // ** ** 1403 | 11'h516: data = 8'b11000110; // ** ** 1404 | 11'h517: data = 8'b11000110; // ** ** 1405 | 11'h518: data = 8'b11000110; // ** ** 1406 | 11'h519: data = 8'b11010110; // ** * ** 1407 | 11'h51a: data = 8'b11011110; // ** **** 1408 | 11'h51b: data = 8'b01111100; // ***** 1409 | 11'h51c: data = 8'b00001100; // ** 1410 | 11'h51d: data = 8'b00001110; // *** 1411 | 11'h51e: data = 8'b00000000; // 1412 | 11'h51f: data = 8'b00000000; // 1413 | //code x52 1414 | 11'h520: data = 8'b00000000; // 1415 | 11'h521: data = 8'b00000000; // 1416 | 11'h522: data = 8'b11111100; // ****** 1417 | 11'h523: data = 8'b01100110; // ** ** 1418 | 11'h524: data = 8'b01100110; // ** ** 1419 | 11'h525: data = 8'b01100110; // ** ** 1420 | 11'h526: data = 8'b01111100; // ***** 1421 | 11'h527: data = 8'b01101100; // ** ** 1422 | 11'h528: data = 8'b01100110; // ** ** 1423 | 11'h529: data = 8'b01100110; // ** ** 1424 | 11'h52a: data = 8'b01100110; // ** ** 1425 | 11'h52b: data = 8'b11100110; // *** ** 1426 | 11'h52c: data = 8'b00000000; // 1427 | 11'h52d: data = 8'b00000000; // 1428 | 11'h52e: data = 8'b00000000; // 1429 | 11'h52f: data = 8'b00000000; // 1430 | //code x53 1431 | 11'h530: data = 8'b00000000; // 1432 | 11'h531: data = 8'b00000000; // 1433 | 11'h532: data = 8'b01111100; // ***** 1434 | 11'h533: data = 8'b11000110; // ** ** 1435 | 11'h534: data = 8'b11000110; // ** ** 1436 | 11'h535: data = 8'b01100000; // ** 1437 | 11'h536: data = 8'b00111000; // *** 1438 | 11'h537: data = 8'b00001100; // ** 1439 | 11'h538: data = 8'b00000110; // ** 1440 | 11'h539: data = 8'b11000110; // ** ** 1441 | 11'h53a: data = 8'b11000110; // ** ** 1442 | 11'h53b: data = 8'b01111100; // ***** 1443 | 11'h53c: data = 8'b00000000; // 1444 | 11'h53d: data = 8'b00000000; // 1445 | 11'h53e: data = 8'b00000000; // 1446 | 11'h53f: data = 8'b00000000; // 1447 | //code x54 1448 | 11'h540: data = 8'b00000000; // 1449 | 11'h541: data = 8'b00000000; // 1450 | 11'h542: data = 8'b11111111; // ******** 1451 | 11'h543: data = 8'b11011011; // ** ** ** 1452 | 11'h544: data = 8'b10011001; // * ** * 1453 | 11'h545: data = 8'b00011000; // ** 1454 | 11'h546: data = 8'b00011000; // ** 1455 | 11'h547: data = 8'b00011000; // ** 1456 | 11'h548: data = 8'b00011000; // ** 1457 | 11'h549: data = 8'b00011000; // ** 1458 | 11'h54a: data = 8'b00011000; // ** 1459 | 11'h54b: data = 8'b00111100; // **** 1460 | 11'h54c: data = 8'b00000000; // 1461 | 11'h54d: data = 8'b00000000; // 1462 | 11'h54e: data = 8'b00000000; // 1463 | 11'h54f: data = 8'b00000000; // 1464 | //code x55 1465 | 11'h550: data = 8'b00000000; // 1466 | 11'h551: data = 8'b00000000; // 1467 | 11'h552: data = 8'b11000110; // ** ** 1468 | 11'h553: data = 8'b11000110; // ** ** 1469 | 11'h554: data = 8'b11000110; // ** ** 1470 | 11'h555: data = 8'b11000110; // ** ** 1471 | 11'h556: data = 8'b11000110; // ** ** 1472 | 11'h557: data = 8'b11000110; // ** ** 1473 | 11'h558: data = 8'b11000110; // ** ** 1474 | 11'h559: data = 8'b11000110; // ** ** 1475 | 11'h55a: data = 8'b11000110; // ** ** 1476 | 11'h55b: data = 8'b01111100; // ***** 1477 | 11'h55c: data = 8'b00000000; // 1478 | 11'h55d: data = 8'b00000000; // 1479 | 11'h55e: data = 8'b00000000; // 1480 | 11'h55f: data = 8'b00000000; // 1481 | //code x56 1482 | 11'h560: data = 8'b00000000; // 1483 | 11'h561: data = 8'b00000000; // 1484 | 11'h562: data = 8'b11000011; // ** ** 1485 | 11'h563: data = 8'b11000011; // ** ** 1486 | 11'h564: data = 8'b11000011; // ** ** 1487 | 11'h565: data = 8'b11000011; // ** ** 1488 | 11'h566: data = 8'b11000011; // ** ** 1489 | 11'h567: data = 8'b11000011; // ** ** 1490 | 11'h568: data = 8'b11000011; // ** ** 1491 | 11'h569: data = 8'b01100110; // ** ** 1492 | 11'h56a: data = 8'b00111100; // **** 1493 | 11'h56b: data = 8'b00011000; // ** 1494 | 11'h56c: data = 8'b00000000; // 1495 | 11'h56d: data = 8'b00000000; // 1496 | 11'h56e: data = 8'b00000000; // 1497 | 11'h56f: data = 8'b00000000; // 1498 | //code x57 1499 | 11'h570: data = 8'b00000000; // 1500 | 11'h571: data = 8'b00000000; // 1501 | 11'h572: data = 8'b11000011; // ** ** 1502 | 11'h573: data = 8'b11000011; // ** ** 1503 | 11'h574: data = 8'b11000011; // ** ** 1504 | 11'h575: data = 8'b11000011; // ** ** 1505 | 11'h576: data = 8'b11000011; // ** ** 1506 | 11'h577: data = 8'b11011011; // ** ** ** 1507 | 11'h578: data = 8'b11011011; // ** ** ** 1508 | 11'h579: data = 8'b11111111; // ******** 1509 | 11'h57a: data = 8'b01100110; // ** ** 1510 | 11'h57b: data = 8'b01100110; // ** ** 1511 | 11'h57c: data = 8'b00000000; // 1512 | 11'h57d: data = 8'b00000000; // 1513 | 11'h57e: data = 8'b00000000; // 1514 | 11'h57f: data = 8'b00000000; // 1515 | //code x58 1516 | 11'h580: data = 8'b00000000; // 1517 | 11'h581: data = 8'b00000000; // 1518 | 11'h582: data = 8'b11000011; // ** ** 1519 | 11'h583: data = 8'b11000011; // ** ** 1520 | 11'h584: data = 8'b01100110; // ** ** 1521 | 11'h585: data = 8'b00111100; // **** 1522 | 11'h586: data = 8'b00011000; // ** 1523 | 11'h587: data = 8'b00011000; // ** 1524 | 11'h588: data = 8'b00111100; // **** 1525 | 11'h589: data = 8'b01100110; // ** ** 1526 | 11'h58a: data = 8'b11000011; // ** ** 1527 | 11'h58b: data = 8'b11000011; // ** ** 1528 | 11'h58c: data = 8'b00000000; // 1529 | 11'h58d: data = 8'b00000000; // 1530 | 11'h58e: data = 8'b00000000; // 1531 | 11'h58f: data = 8'b00000000; // 1532 | //code x59 1533 | 11'h590: data = 8'b00000000; // 1534 | 11'h591: data = 8'b00000000; // 1535 | 11'h592: data = 8'b11000011; // ** ** 1536 | 11'h593: data = 8'b11000011; // ** ** 1537 | 11'h594: data = 8'b11000011; // ** ** 1538 | 11'h595: data = 8'b01100110; // ** ** 1539 | 11'h596: data = 8'b00111100; // **** 1540 | 11'h597: data = 8'b00011000; // ** 1541 | 11'h598: data = 8'b00011000; // ** 1542 | 11'h599: data = 8'b00011000; // ** 1543 | 11'h59a: data = 8'b00011000; // ** 1544 | 11'h59b: data = 8'b00111100; // **** 1545 | 11'h59c: data = 8'b00000000; // 1546 | 11'h59d: data = 8'b00000000; // 1547 | 11'h59e: data = 8'b00000000; // 1548 | 11'h59f: data = 8'b00000000; // 1549 | //code x5a 1550 | 11'h5a0: data = 8'b00000000; // 1551 | 11'h5a1: data = 8'b00000000; // 1552 | 11'h5a2: data = 8'b11111111; // ******** 1553 | 11'h5a3: data = 8'b11000011; // ** ** 1554 | 11'h5a4: data = 8'b10000110; // * ** 1555 | 11'h5a5: data = 8'b00001100; // ** 1556 | 11'h5a6: data = 8'b00011000; // ** 1557 | 11'h5a7: data = 8'b00110000; // ** 1558 | 11'h5a8: data = 8'b01100000; // ** 1559 | 11'h5a9: data = 8'b11000001; // ** * 1560 | 11'h5aa: data = 8'b11000011; // ** ** 1561 | 11'h5ab: data = 8'b11111111; // ******** 1562 | 11'h5ac: data = 8'b00000000; // 1563 | 11'h5ad: data = 8'b00000000; // 1564 | 11'h5ae: data = 8'b00000000; // 1565 | 11'h5af: data = 8'b00000000; // 1566 | //code x5b 1567 | 11'h5b0: data = 8'b00000000; // 1568 | 11'h5b1: data = 8'b00000000; // 1569 | 11'h5b2: data = 8'b00111100; // **** 1570 | 11'h5b3: data = 8'b00110000; // ** 1571 | 11'h5b4: data = 8'b00110000; // ** 1572 | 11'h5b5: data = 8'b00110000; // ** 1573 | 11'h5b6: data = 8'b00110000; // ** 1574 | 11'h5b7: data = 8'b00110000; // ** 1575 | 11'h5b8: data = 8'b00110000; // ** 1576 | 11'h5b9: data = 8'b00110000; // ** 1577 | 11'h5ba: data = 8'b00110000; // ** 1578 | 11'h5bb: data = 8'b00111100; // **** 1579 | 11'h5bc: data = 8'b00000000; // 1580 | 11'h5bd: data = 8'b00000000; // 1581 | 11'h5be: data = 8'b00000000; // 1582 | 11'h5bf: data = 8'b00000000; // 1583 | //code x5c 1584 | 11'h5c0: data = 8'b00000000; // 1585 | 11'h5c1: data = 8'b00000000; // 1586 | 11'h5c2: data = 8'b00000000; // 1587 | 11'h5c3: data = 8'b10000000; // * 1588 | 11'h5c4: data = 8'b11000000; // ** 1589 | 11'h5c5: data = 8'b11100000; // *** 1590 | 11'h5c6: data = 8'b01110000; // *** 1591 | 11'h5c7: data = 8'b00111000; // *** 1592 | 11'h5c8: data = 8'b00011100; // *** 1593 | 11'h5c9: data = 8'b00001110; // *** 1594 | 11'h5ca: data = 8'b00000110; // ** 1595 | 11'h5cb: data = 8'b00000010; // * 1596 | 11'h5cc: data = 8'b00000000; // 1597 | 11'h5cd: data = 8'b00000000; // 1598 | 11'h5ce: data = 8'b00000000; // 1599 | 11'h5cf: data = 8'b00000000; // 1600 | //code x5d 1601 | 11'h5d0: data = 8'b00000000; // 1602 | 11'h5d1: data = 8'b00000000; // 1603 | 11'h5d2: data = 8'b00111100; // **** 1604 | 11'h5d3: data = 8'b00001100; // ** 1605 | 11'h5d4: data = 8'b00001100; // ** 1606 | 11'h5d5: data = 8'b00001100; // ** 1607 | 11'h5d6: data = 8'b00001100; // ** 1608 | 11'h5d7: data = 8'b00001100; // ** 1609 | 11'h5d8: data = 8'b00001100; // ** 1610 | 11'h5d9: data = 8'b00001100; // ** 1611 | 11'h5da: data = 8'b00001100; // ** 1612 | 11'h5db: data = 8'b00111100; // **** 1613 | 11'h5dc: data = 8'b00000000; // 1614 | 11'h5dd: data = 8'b00000000; // 1615 | 11'h5de: data = 8'b00000000; // 1616 | 11'h5df: data = 8'b00000000; // 1617 | //code x5e 1618 | 11'h5e0: data = 8'b00010000; // * 1619 | 11'h5e1: data = 8'b00111000; // *** 1620 | 11'h5e2: data = 8'b01101100; // ** ** 1621 | 11'h5e3: data = 8'b11000110; // ** ** 1622 | 11'h5e4: data = 8'b00000000; // 1623 | 11'h5e5: data = 8'b00000000; // 1624 | 11'h5e6: data = 8'b00000000; // 1625 | 11'h5e7: data = 8'b00000000; // 1626 | 11'h5e8: data = 8'b00000000; // 1627 | 11'h5e9: data = 8'b00000000; // 1628 | 11'h5ea: data = 8'b00000000; // 1629 | 11'h5eb: data = 8'b00000000; // 1630 | 11'h5ec: data = 8'b00000000; // 1631 | 11'h5ed: data = 8'b00000000; // 1632 | 11'h5ee: data = 8'b00000000; // 1633 | 11'h5ef: data = 8'b00000000; // 1634 | //code x5f 1635 | 11'h5f0: data = 8'b00000000; // 1636 | 11'h5f1: data = 8'b00000000; // 1637 | 11'h5f2: data = 8'b00000000; // 1638 | 11'h5f3: data = 8'b00000000; // 1639 | 11'h5f4: data = 8'b00000000; // 1640 | 11'h5f5: data = 8'b00000000; // 1641 | 11'h5f6: data = 8'b00000000; // 1642 | 11'h5f7: data = 8'b00000000; // 1643 | 11'h5f8: data = 8'b00000000; // 1644 | 11'h5f9: data = 8'b00000000; // 1645 | 11'h5fa: data = 8'b00000000; // 1646 | 11'h5fb: data = 8'b00000000; // 1647 | 11'h5fc: data = 8'b00000000; // 1648 | 11'h5fd: data = 8'b11111111; // ******** 1649 | 11'h5fe: data = 8'b00000000; // 1650 | 11'h5ff: data = 8'b00000000; // 1651 | //code x60 1652 | 11'h600: data = 8'b00110000; // ** 1653 | 11'h601: data = 8'b00110000; // ** 1654 | 11'h602: data = 8'b00011000; // ** 1655 | 11'h603: data = 8'b00000000; // 1656 | 11'h604: data = 8'b00000000; // 1657 | 11'h605: data = 8'b00000000; // 1658 | 11'h606: data = 8'b00000000; // 1659 | 11'h607: data = 8'b00000000; // 1660 | 11'h608: data = 8'b00000000; // 1661 | 11'h609: data = 8'b00000000; // 1662 | 11'h60a: data = 8'b00000000; // 1663 | 11'h60b: data = 8'b00000000; // 1664 | 11'h60c: data = 8'b00000000; // 1665 | 11'h60d: data = 8'b00000000; // 1666 | 11'h60e: data = 8'b00000000; // 1667 | 11'h60f: data = 8'b00000000; // 1668 | //code x61 1669 | 11'h610: data = 8'b00000000; // 1670 | 11'h611: data = 8'b00000000; // 1671 | 11'h612: data = 8'b00000000; // 1672 | 11'h613: data = 8'b00000000; // 1673 | 11'h614: data = 8'b00000000; // 1674 | 11'h615: data = 8'b01111000; // **** 1675 | 11'h616: data = 8'b00001100; // ** 1676 | 11'h617: data = 8'b01111100; // ***** 1677 | 11'h618: data = 8'b11001100; // ** ** 1678 | 11'h619: data = 8'b11001100; // ** ** 1679 | 11'h61a: data = 8'b11001100; // ** ** 1680 | 11'h61b: data = 8'b01110110; // *** ** 1681 | 11'h61c: data = 8'b00000000; // 1682 | 11'h61d: data = 8'b00000000; // 1683 | 11'h61e: data = 8'b00000000; // 1684 | 11'h61f: data = 8'b00000000; // 1685 | //code x62 1686 | 11'h620: data = 8'b00000000; // 1687 | 11'h621: data = 8'b00000000; // 1688 | 11'h622: data = 8'b11100000; // *** 1689 | 11'h623: data = 8'b01100000; // ** 1690 | 11'h624: data = 8'b01100000; // ** 1691 | 11'h625: data = 8'b01111000; // **** 1692 | 11'h626: data = 8'b01101100; // ** ** 1693 | 11'h627: data = 8'b01100110; // ** ** 1694 | 11'h628: data = 8'b01100110; // ** ** 1695 | 11'h629: data = 8'b01100110; // ** ** 1696 | 11'h62a: data = 8'b01100110; // ** ** 1697 | 11'h62b: data = 8'b01111100; // ***** 1698 | 11'h62c: data = 8'b00000000; // 1699 | 11'h62d: data = 8'b00000000; // 1700 | 11'h62e: data = 8'b00000000; // 1701 | 11'h62f: data = 8'b00000000; // 1702 | //code x63 1703 | 11'h630: data = 8'b00000000; // 1704 | 11'h631: data = 8'b00000000; // 1705 | 11'h632: data = 8'b00000000; // 1706 | 11'h633: data = 8'b00000000; // 1707 | 11'h634: data = 8'b00000000; // 1708 | 11'h635: data = 8'b01111100; // ***** 1709 | 11'h636: data = 8'b11000110; // ** ** 1710 | 11'h637: data = 8'b11000000; // ** 1711 | 11'h638: data = 8'b11000000; // ** 1712 | 11'h639: data = 8'b11000000; // ** 1713 | 11'h63a: data = 8'b11000110; // ** ** 1714 | 11'h63b: data = 8'b01111100; // ***** 1715 | 11'h63c: data = 8'b00000000; // 1716 | 11'h63d: data = 8'b00000000; // 1717 | 11'h63e: data = 8'b00000000; // 1718 | 11'h63f: data = 8'b00000000; // 1719 | //code x64 1720 | 11'h640: data = 8'b00000000; // 1721 | 11'h641: data = 8'b00000000; // 1722 | 11'h642: data = 8'b00011100; // *** 1723 | 11'h643: data = 8'b00001100; // ** 1724 | 11'h644: data = 8'b00001100; // ** 1725 | 11'h645: data = 8'b00111100; // **** 1726 | 11'h646: data = 8'b01101100; // ** ** 1727 | 11'h647: data = 8'b11001100; // ** ** 1728 | 11'h648: data = 8'b11001100; // ** ** 1729 | 11'h649: data = 8'b11001100; // ** ** 1730 | 11'h64a: data = 8'b11001100; // ** ** 1731 | 11'h64b: data = 8'b01110110; // *** ** 1732 | 11'h64c: data = 8'b00000000; // 1733 | 11'h64d: data = 8'b00000000; // 1734 | 11'h64e: data = 8'b00000000; // 1735 | 11'h64f: data = 8'b00000000; // 1736 | //code x65 1737 | 11'h650: data = 8'b00000000; // 1738 | 11'h651: data = 8'b00000000; // 1739 | 11'h652: data = 8'b00000000; // 1740 | 11'h653: data = 8'b00000000; // 1741 | 11'h654: data = 8'b00000000; // 1742 | 11'h655: data = 8'b01111100; // ***** 1743 | 11'h656: data = 8'b11000110; // ** ** 1744 | 11'h657: data = 8'b11111110; // ******* 1745 | 11'h658: data = 8'b11000000; // ** 1746 | 11'h659: data = 8'b11000000; // ** 1747 | 11'h65a: data = 8'b11000110; // ** ** 1748 | 11'h65b: data = 8'b01111100; // ***** 1749 | 11'h65c: data = 8'b00000000; // 1750 | 11'h65d: data = 8'b00000000; // 1751 | 11'h65e: data = 8'b00000000; // 1752 | 11'h65f: data = 8'b00000000; // 1753 | //code x66 1754 | 11'h660: data = 8'b00000000; // 1755 | 11'h661: data = 8'b00000000; // 1756 | 11'h662: data = 8'b00111000; // *** 1757 | 11'h663: data = 8'b01101100; // ** ** 1758 | 11'h664: data = 8'b01100100; // ** * 1759 | 11'h665: data = 8'b01100000; // ** 1760 | 11'h666: data = 8'b11110000; // **** 1761 | 11'h667: data = 8'b01100000; // ** 1762 | 11'h668: data = 8'b01100000; // ** 1763 | 11'h669: data = 8'b01100000; // ** 1764 | 11'h66a: data = 8'b01100000; // ** 1765 | 11'h66b: data = 8'b11110000; // **** 1766 | 11'h66c: data = 8'b00000000; // 1767 | 11'h66d: data = 8'b00000000; // 1768 | 11'h66e: data = 8'b00000000; // 1769 | 11'h66f: data = 8'b00000000; // 1770 | //code x67 1771 | 11'h670: data = 8'b00000000; // 1772 | 11'h671: data = 8'b00000000; // 1773 | 11'h672: data = 8'b00000000; // 1774 | 11'h673: data = 8'b00000000; // 1775 | 11'h674: data = 8'b00000000; // 1776 | 11'h675: data = 8'b01110110; // *** ** 1777 | 11'h676: data = 8'b11001100; // ** ** 1778 | 11'h677: data = 8'b11001100; // ** ** 1779 | 11'h678: data = 8'b11001100; // ** ** 1780 | 11'h679: data = 8'b11001100; // ** ** 1781 | 11'h67a: data = 8'b11001100; // ** ** 1782 | 11'h67b: data = 8'b01111100; // ***** 1783 | 11'h67c: data = 8'b00001100; // ** 1784 | 11'h67d: data = 8'b11001100; // ** ** 1785 | 11'h67e: data = 8'b01111000; // **** 1786 | 11'h67f: data = 8'b00000000; // 1787 | //code x68 1788 | 11'h680: data = 8'b00000000; // 1789 | 11'h681: data = 8'b00000000; // 1790 | 11'h682: data = 8'b11100000; // *** 1791 | 11'h683: data = 8'b01100000; // ** 1792 | 11'h684: data = 8'b01100000; // ** 1793 | 11'h685: data = 8'b01101100; // ** ** 1794 | 11'h686: data = 8'b01110110; // *** ** 1795 | 11'h687: data = 8'b01100110; // ** ** 1796 | 11'h688: data = 8'b01100110; // ** ** 1797 | 11'h689: data = 8'b01100110; // ** ** 1798 | 11'h68a: data = 8'b01100110; // ** ** 1799 | 11'h68b: data = 8'b11100110; // *** ** 1800 | 11'h68c: data = 8'b00000000; // 1801 | 11'h68d: data = 8'b00000000; // 1802 | 11'h68e: data = 8'b00000000; // 1803 | 11'h68f: data = 8'b00000000; // 1804 | //code x69 1805 | 11'h690: data = 8'b00000000; // 1806 | 11'h691: data = 8'b00000000; // 1807 | 11'h692: data = 8'b00011000; // ** 1808 | 11'h693: data = 8'b00011000; // ** 1809 | 11'h694: data = 8'b00000000; // 1810 | 11'h695: data = 8'b00111000; // *** 1811 | 11'h696: data = 8'b00011000; // ** 1812 | 11'h697: data = 8'b00011000; // ** 1813 | 11'h698: data = 8'b00011000; // ** 1814 | 11'h699: data = 8'b00011000; // ** 1815 | 11'h69a: data = 8'b00011000; // ** 1816 | 11'h69b: data = 8'b00111100; // **** 1817 | 11'h69c: data = 8'b00000000; // 1818 | 11'h69d: data = 8'b00000000; // 1819 | 11'h69e: data = 8'b00000000; // 1820 | 11'h69f: data = 8'b00000000; // 1821 | //code x6a 1822 | 11'h6a0: data = 8'b00000000; // 1823 | 11'h6a1: data = 8'b00000000; // 1824 | 11'h6a2: data = 8'b00000110; // ** 1825 | 11'h6a3: data = 8'b00000110; // ** 1826 | 11'h6a4: data = 8'b00000000; // 1827 | 11'h6a5: data = 8'b00001110; // *** 1828 | 11'h6a6: data = 8'b00000110; // ** 1829 | 11'h6a7: data = 8'b00000110; // ** 1830 | 11'h6a8: data = 8'b00000110; // ** 1831 | 11'h6a9: data = 8'b00000110; // ** 1832 | 11'h6aa: data = 8'b00000110; // ** 1833 | 11'h6ab: data = 8'b00000110; // ** 1834 | 11'h6ac: data = 8'b01100110; // ** ** 1835 | 11'h6ad: data = 8'b01100110; // ** ** 1836 | 11'h6ae: data = 8'b00111100; // **** 1837 | 11'h6af: data = 8'b00000000; // 1838 | //code x6b 1839 | 11'h6b0: data = 8'b00000000; // 1840 | 11'h6b1: data = 8'b00000000; // 1841 | 11'h6b2: data = 8'b11100000; // *** 1842 | 11'h6b3: data = 8'b01100000; // ** 1843 | 11'h6b4: data = 8'b01100000; // ** 1844 | 11'h6b5: data = 8'b01100110; // ** ** 1845 | 11'h6b6: data = 8'b01101100; // ** ** 1846 | 11'h6b7: data = 8'b01111000; // **** 1847 | 11'h6b8: data = 8'b01111000; // **** 1848 | 11'h6b9: data = 8'b01101100; // ** ** 1849 | 11'h6ba: data = 8'b01100110; // ** ** 1850 | 11'h6bb: data = 8'b11100110; // *** ** 1851 | 11'h6bc: data = 8'b00000000; // 1852 | 11'h6bd: data = 8'b00000000; // 1853 | 11'h6be: data = 8'b00000000; // 1854 | 11'h6bf: data = 8'b00000000; // 1855 | //code x6c 1856 | 11'h6c0: data = 8'b00000000; // 1857 | 11'h6c1: data = 8'b00000000; // 1858 | 11'h6c2: data = 8'b00111000; // *** 1859 | 11'h6c3: data = 8'b00011000; // ** 1860 | 11'h6c4: data = 8'b00011000; // ** 1861 | 11'h6c5: data = 8'b00011000; // ** 1862 | 11'h6c6: data = 8'b00011000; // ** 1863 | 11'h6c7: data = 8'b00011000; // ** 1864 | 11'h6c8: data = 8'b00011000; // ** 1865 | 11'h6c9: data = 8'b00011000; // ** 1866 | 11'h6ca: data = 8'b00011000; // ** 1867 | 11'h6cb: data = 8'b00111100; // **** 1868 | 11'h6cc: data = 8'b00000000; // 1869 | 11'h6cd: data = 8'b00000000; // 1870 | 11'h6ce: data = 8'b00000000; // 1871 | 11'h6cf: data = 8'b00000000; // 1872 | //code x6d 1873 | 11'h6d0: data = 8'b00000000; // 1874 | 11'h6d1: data = 8'b00000000; // 1875 | 11'h6d2: data = 8'b00000000; // 1876 | 11'h6d3: data = 8'b00000000; // 1877 | 11'h6d4: data = 8'b00000000; // 1878 | 11'h6d5: data = 8'b11100110; // *** ** 1879 | 11'h6d6: data = 8'b11111111; // ******** 1880 | 11'h6d7: data = 8'b11011011; // ** ** ** 1881 | 11'h6d8: data = 8'b11011011; // ** ** ** 1882 | 11'h6d9: data = 8'b11011011; // ** ** ** 1883 | 11'h6da: data = 8'b11011011; // ** ** ** 1884 | 11'h6db: data = 8'b11011011; // ** ** ** 1885 | 11'h6dc: data = 8'b00000000; // 1886 | 11'h6dd: data = 8'b00000000; // 1887 | 11'h6de: data = 8'b00000000; // 1888 | 11'h6df: data = 8'b00000000; // 1889 | //code x6e 1890 | 11'h6e0: data = 8'b00000000; // 1891 | 11'h6e1: data = 8'b00000000; // 1892 | 11'h6e2: data = 8'b00000000; // 1893 | 11'h6e3: data = 8'b00000000; // 1894 | 11'h6e4: data = 8'b00000000; // 1895 | 11'h6e5: data = 8'b11011100; // ** *** 1896 | 11'h6e6: data = 8'b01100110; // ** ** 1897 | 11'h6e7: data = 8'b01100110; // ** ** 1898 | 11'h6e8: data = 8'b01100110; // ** ** 1899 | 11'h6e9: data = 8'b01100110; // ** ** 1900 | 11'h6ea: data = 8'b01100110; // ** ** 1901 | 11'h6eb: data = 8'b01100110; // ** ** 1902 | 11'h6ec: data = 8'b00000000; // 1903 | 11'h6ed: data = 8'b00000000; // 1904 | 11'h6ee: data = 8'b00000000; // 1905 | 11'h6ef: data = 8'b00000000; // 1906 | //code x6f 1907 | 11'h6f0: data = 8'b00000000; // 1908 | 11'h6f1: data = 8'b00000000; // 1909 | 11'h6f2: data = 8'b00000000; // 1910 | 11'h6f3: data = 8'b00000000; // 1911 | 11'h6f4: data = 8'b00000000; // 1912 | 11'h6f5: data = 8'b01111100; // ***** 1913 | 11'h6f6: data = 8'b11000110; // ** ** 1914 | 11'h6f7: data = 8'b11000110; // ** ** 1915 | 11'h6f8: data = 8'b11000110; // ** ** 1916 | 11'h6f9: data = 8'b11000110; // ** ** 1917 | 11'h6fa: data = 8'b11000110; // ** ** 1918 | 11'h6fb: data = 8'b01111100; // ***** 1919 | 11'h6fc: data = 8'b00000000; // 1920 | 11'h6fd: data = 8'b00000000; // 1921 | 11'h6fe: data = 8'b00000000; // 1922 | 11'h6ff: data = 8'b00000000; // 1923 | //code x70 1924 | 11'h700: data = 8'b00000000; // 1925 | 11'h701: data = 8'b00000000; // 1926 | 11'h702: data = 8'b00000000; // 1927 | 11'h703: data = 8'b00000000; // 1928 | 11'h704: data = 8'b00000000; // 1929 | 11'h705: data = 8'b11011100; // ** *** 1930 | 11'h706: data = 8'b01100110; // ** ** 1931 | 11'h707: data = 8'b01100110; // ** ** 1932 | 11'h708: data = 8'b01100110; // ** ** 1933 | 11'h709: data = 8'b01100110; // ** ** 1934 | 11'h70a: data = 8'b01100110; // ** ** 1935 | 11'h70b: data = 8'b01111100; // ***** 1936 | 11'h70c: data = 8'b01100000; // ** 1937 | 11'h70d: data = 8'b01100000; // ** 1938 | 11'h70e: data = 8'b11110000; // **** 1939 | 11'h70f: data = 8'b00000000; // 1940 | //code x71 1941 | 11'h710: data = 8'b00000000; // 1942 | 11'h711: data = 8'b00000000; // 1943 | 11'h712: data = 8'b00000000; // 1944 | 11'h713: data = 8'b00000000; // 1945 | 11'h714: data = 8'b00000000; // 1946 | 11'h715: data = 8'b01110110; // *** ** 1947 | 11'h716: data = 8'b11001100; // ** ** 1948 | 11'h717: data = 8'b11001100; // ** ** 1949 | 11'h718: data = 8'b11001100; // ** ** 1950 | 11'h719: data = 8'b11001100; // ** ** 1951 | 11'h71a: data = 8'b11001100; // ** ** 1952 | 11'h71b: data = 8'b01111100; // ***** 1953 | 11'h71c: data = 8'b00001100; // ** 1954 | 11'h71d: data = 8'b00001100; // ** 1955 | 11'h71e: data = 8'b00011110; // **** 1956 | 11'h71f: data = 8'b00000000; // 1957 | //code x72 1958 | 11'h720: data = 8'b00000000; // 1959 | 11'h721: data = 8'b00000000; // 1960 | 11'h722: data = 8'b00000000; // 1961 | 11'h723: data = 8'b00000000; // 1962 | 11'h724: data = 8'b00000000; // 1963 | 11'h725: data = 8'b11011100; // ** *** 1964 | 11'h726: data = 8'b01110110; // *** ** 1965 | 11'h727: data = 8'b01100110; // ** ** 1966 | 11'h728: data = 8'b01100000; // ** 1967 | 11'h729: data = 8'b01100000; // ** 1968 | 11'h72a: data = 8'b01100000; // ** 1969 | 11'h72b: data = 8'b11110000; // **** 1970 | 11'h72c: data = 8'b00000000; // 1971 | 11'h72d: data = 8'b00000000; // 1972 | 11'h72e: data = 8'b00000000; // 1973 | 11'h72f: data = 8'b00000000; // 1974 | //code x73 1975 | 11'h730: data = 8'b00000000; // 1976 | 11'h731: data = 8'b00000000; // 1977 | 11'h732: data = 8'b00000000; // 1978 | 11'h733: data = 8'b00000000; // 1979 | 11'h734: data = 8'b00000000; // 1980 | 11'h735: data = 8'b01111100; // ***** 1981 | 11'h736: data = 8'b11000110; // ** ** 1982 | 11'h737: data = 8'b01100000; // ** 1983 | 11'h738: data = 8'b00111000; // *** 1984 | 11'h739: data = 8'b00001100; // ** 1985 | 11'h73a: data = 8'b11000110; // ** ** 1986 | 11'h73b: data = 8'b01111100; // ***** 1987 | 11'h73c: data = 8'b00000000; // 1988 | 11'h73d: data = 8'b00000000; // 1989 | 11'h73e: data = 8'b00000000; // 1990 | 11'h73f: data = 8'b00000000; // 1991 | //code x74 1992 | 11'h740: data = 8'b00000000; // 1993 | 11'h741: data = 8'b00000000; // 1994 | 11'h742: data = 8'b00010000; // * 1995 | 11'h743: data = 8'b00110000; // ** 1996 | 11'h744: data = 8'b00110000; // ** 1997 | 11'h745: data = 8'b11111100; // ****** 1998 | 11'h746: data = 8'b00110000; // ** 1999 | 11'h747: data = 8'b00110000; // ** 2000 | 11'h748: data = 8'b00110000; // ** 2001 | 11'h749: data = 8'b00110000; // ** 2002 | 11'h74a: data = 8'b00110110; // ** ** 2003 | 11'h74b: data = 8'b00011100; // *** 2004 | 11'h74c: data = 8'b00000000; // 2005 | 11'h74d: data = 8'b00000000; // 2006 | 11'h74e: data = 8'b00000000; // 2007 | 11'h74f: data = 8'b00000000; // 2008 | //code x75 2009 | 11'h750: data = 8'b00000000; // 2010 | 11'h751: data = 8'b00000000; // 2011 | 11'h752: data = 8'b00000000; // 2012 | 11'h753: data = 8'b00000000; // 2013 | 11'h754: data = 8'b00000000; // 2014 | 11'h755: data = 8'b11001100; // ** ** 2015 | 11'h756: data = 8'b11001100; // ** ** 2016 | 11'h757: data = 8'b11001100; // ** ** 2017 | 11'h758: data = 8'b11001100; // ** ** 2018 | 11'h759: data = 8'b11001100; // ** ** 2019 | 11'h75a: data = 8'b11001100; // ** ** 2020 | 11'h75b: data = 8'b01110110; // *** ** 2021 | 11'h75c: data = 8'b00000000; // 2022 | 11'h75d: data = 8'b00000000; // 2023 | 11'h75e: data = 8'b00000000; // 2024 | 11'h75f: data = 8'b00000000; // 2025 | //code x76 2026 | 11'h760: data = 8'b00000000; // 2027 | 11'h761: data = 8'b00000000; // 2028 | 11'h762: data = 8'b00000000; // 2029 | 11'h763: data = 8'b00000000; // 2030 | 11'h764: data = 8'b00000000; // 2031 | 11'h765: data = 8'b11000011; // ** ** 2032 | 11'h766: data = 8'b11000011; // ** ** 2033 | 11'h767: data = 8'b11000011; // ** ** 2034 | 11'h768: data = 8'b11000011; // ** ** 2035 | 11'h769: data = 8'b01100110; // ** ** 2036 | 11'h76a: data = 8'b00111100; // **** 2037 | 11'h76b: data = 8'b00011000; // ** 2038 | 11'h76c: data = 8'b00000000; // 2039 | 11'h76d: data = 8'b00000000; // 2040 | 11'h76e: data = 8'b00000000; // 2041 | 11'h76f: data = 8'b00000000; // 2042 | //code x77 2043 | 11'h770: data = 8'b00000000; // 2044 | 11'h771: data = 8'b00000000; // 2045 | 11'h772: data = 8'b00000000; // 2046 | 11'h773: data = 8'b00000000; // 2047 | 11'h774: data = 8'b00000000; // 2048 | 11'h775: data = 8'b11000011; // ** ** 2049 | 11'h776: data = 8'b11000011; // ** ** 2050 | 11'h777: data = 8'b11000011; // ** ** 2051 | 11'h778: data = 8'b11011011; // ** ** ** 2052 | 11'h779: data = 8'b11011011; // ** ** ** 2053 | 11'h77a: data = 8'b11111111; // ******** 2054 | 11'h77b: data = 8'b01100110; // ** ** 2055 | 11'h77c: data = 8'b00000000; // 2056 | 11'h77d: data = 8'b00000000; // 2057 | 11'h77e: data = 8'b00000000; // 2058 | 11'h77f: data = 8'b00000000; // 2059 | //code x78 2060 | 11'h780: data = 8'b00000000; // 2061 | 11'h781: data = 8'b00000000; // 2062 | 11'h782: data = 8'b00000000; // 2063 | 11'h783: data = 8'b00000000; // 2064 | 11'h784: data = 8'b00000000; // 2065 | 11'h785: data = 8'b11000011; // ** ** 2066 | 11'h786: data = 8'b01100110; // ** ** 2067 | 11'h787: data = 8'b00111100; // **** 2068 | 11'h788: data = 8'b00011000; // ** 2069 | 11'h789: data = 8'b00111100; // **** 2070 | 11'h78a: data = 8'b01100110; // ** ** 2071 | 11'h78b: data = 8'b11000011; // ** ** 2072 | 11'h78c: data = 8'b00000000; // 2073 | 11'h78d: data = 8'b00000000; // 2074 | 11'h78e: data = 8'b00000000; // 2075 | 11'h78f: data = 8'b00000000; // 2076 | //code x79 2077 | 11'h790: data = 8'b00000000; // 2078 | 11'h791: data = 8'b00000000; // 2079 | 11'h792: data = 8'b00000000; // 2080 | 11'h793: data = 8'b00000000; // 2081 | 11'h794: data = 8'b00000000; // 2082 | 11'h795: data = 8'b11000110; // ** ** 2083 | 11'h796: data = 8'b11000110; // ** ** 2084 | 11'h797: data = 8'b11000110; // ** ** 2085 | 11'h798: data = 8'b11000110; // ** ** 2086 | 11'h799: data = 8'b11000110; // ** ** 2087 | 11'h79a: data = 8'b11000110; // ** ** 2088 | 11'h79b: data = 8'b01111110; // ****** 2089 | 11'h79c: data = 8'b00000110; // ** 2090 | 11'h79d: data = 8'b00001100; // ** 2091 | 11'h79e: data = 8'b11111000; // ***** 2092 | 11'h79f: data = 8'b00000000; // 2093 | //code x7a 2094 | 11'h7a0: data = 8'b00000000; // 2095 | 11'h7a1: data = 8'b00000000; // 2096 | 11'h7a2: data = 8'b00000000; // 2097 | 11'h7a3: data = 8'b00000000; // 2098 | 11'h7a4: data = 8'b00000000; // 2099 | 11'h7a5: data = 8'b11111110; // ******* 2100 | 11'h7a6: data = 8'b11001100; // ** ** 2101 | 11'h7a7: data = 8'b00011000; // ** 2102 | 11'h7a8: data = 8'b00110000; // ** 2103 | 11'h7a9: data = 8'b01100000; // ** 2104 | 11'h7aa: data = 8'b11000110; // ** ** 2105 | 11'h7ab: data = 8'b11111110; // ******* 2106 | 11'h7ac: data = 8'b00000000; // 2107 | 11'h7ad: data = 8'b00000000; // 2108 | 11'h7ae: data = 8'b00000000; // 2109 | 11'h7af: data = 8'b00000000; // 2110 | //code x7b 2111 | 11'h7b0: data = 8'b00000000; // 2112 | 11'h7b1: data = 8'b00000000; // 2113 | 11'h7b2: data = 8'b00001110; // *** 2114 | 11'h7b3: data = 8'b00011000; // ** 2115 | 11'h7b4: data = 8'b00011000; // ** 2116 | 11'h7b5: data = 8'b00011000; // ** 2117 | 11'h7b6: data = 8'b01110000; // *** 2118 | 11'h7b7: data = 8'b00011000; // ** 2119 | 11'h7b8: data = 8'b00011000; // ** 2120 | 11'h7b9: data = 8'b00011000; // ** 2121 | 11'h7ba: data = 8'b00011000; // ** 2122 | 11'h7bb: data = 8'b00001110; // *** 2123 | 11'h7bc: data = 8'b00000000; // 2124 | 11'h7bd: data = 8'b00000000; // 2125 | 11'h7be: data = 8'b00000000; // 2126 | 11'h7bf: data = 8'b00000000; // 2127 | //code x7c 2128 | 11'h7c0: data = 8'b00000000; // 2129 | 11'h7c1: data = 8'b00000000; // 2130 | 11'h7c2: data = 8'b00011000; // ** 2131 | 11'h7c3: data = 8'b00011000; // ** 2132 | 11'h7c4: data = 8'b00011000; // ** 2133 | 11'h7c5: data = 8'b00011000; // ** 2134 | 11'h7c6: data = 8'b00000000; // 2135 | 11'h7c7: data = 8'b00011000; // ** 2136 | 11'h7c8: data = 8'b00011000; // ** 2137 | 11'h7c9: data = 8'b00011000; // ** 2138 | 11'h7ca: data = 8'b00011000; // ** 2139 | 11'h7cb: data = 8'b00011000; // ** 2140 | 11'h7cc: data = 8'b00000000; // 2141 | 11'h7cd: data = 8'b00000000; // 2142 | 11'h7ce: data = 8'b00000000; // 2143 | 11'h7cf: data = 8'b00000000; // 2144 | //code x7d 2145 | 11'h7d0: data = 8'b00000000; // 2146 | 11'h7d1: data = 8'b00000000; // 2147 | 11'h7d2: data = 8'b01110000; // *** 2148 | 11'h7d3: data = 8'b00011000; // ** 2149 | 11'h7d4: data = 8'b00011000; // ** 2150 | 11'h7d5: data = 8'b00011000; // ** 2151 | 11'h7d6: data = 8'b00001110; // *** 2152 | 11'h7d7: data = 8'b00011000; // ** 2153 | 11'h7d8: data = 8'b00011000; // ** 2154 | 11'h7d9: data = 8'b00011000; // ** 2155 | 11'h7da: data = 8'b00011000; // ** 2156 | 11'h7db: data = 8'b01110000; // *** 2157 | 11'h7dc: data = 8'b00000000; // 2158 | 11'h7dd: data = 8'b00000000; // 2159 | 11'h7de: data = 8'b00000000; // 2160 | 11'h7df: data = 8'b00000000; // 2161 | //code x7e 2162 | 11'h7e0: data = 8'b00000000; // 2163 | 11'h7e1: data = 8'b00000000; // 2164 | 11'h7e2: data = 8'b01110110; // *** ** 2165 | 11'h7e3: data = 8'b11011100; // ** *** 2166 | 11'h7e4: data = 8'b00000000; // 2167 | 11'h7e5: data = 8'b00000000; // 2168 | 11'h7e6: data = 8'b00000000; // 2169 | 11'h7e7: data = 8'b00000000; // 2170 | 11'h7e8: data = 8'b00000000; // 2171 | 11'h7e9: data = 8'b00000000; // 2172 | 11'h7ea: data = 8'b00000000; // 2173 | 11'h7eb: data = 8'b00000000; // 2174 | 11'h7ec: data = 8'b00000000; // 2175 | 11'h7ed: data = 8'b00000000; // 2176 | 11'h7ee: data = 8'b00000000; // 2177 | 11'h7ef: data = 8'b00000000; // 2178 | //code x7f 2179 | 11'h7f0: data = 8'b00000000; // 2180 | 11'h7f1: data = 8'b00000000; // 2181 | 11'h7f2: data = 8'b00000000; // 2182 | 11'h7f3: data = 8'b00000000; // 2183 | 11'h7f4: data = 8'b00010000; // * 2184 | 11'h7f5: data = 8'b00111000; // *** 2185 | 11'h7f6: data = 8'b01101100; // ** ** 2186 | 11'h7f7: data = 8'b11000110; // ** ** 2187 | 11'h7f8: data = 8'b11000110; // ** ** 2188 | 11'h7f9: data = 8'b11000110; // ** ** 2189 | 11'h7fa: data = 8'b11111110; // ******* 2190 | 11'h7fb: data = 8'b00000000; // 2191 | 11'h7fc: data = 8'b00000000; // 2192 | 11'h7fd: data = 8'b00000000; // 2193 | 11'h7fe: data = 8'b00000000; // 2194 | 11'h7ff: data = 8'b00000000; // 2195 | endcase 2196 | 2197 | endmodule 2198 | --------------------------------------------------------------------------------